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authorSteven King <sfking@fdwdc.com>2012-05-21 16:10:19 -0400
committerGreg Ungerer <gerg@uclinux.org>2012-07-15 19:59:21 -0400
commiteac57949947fa24f47a2e993a1dbbfdb573b4301 (patch)
tree7ef7fadfbbb7153c788dbc036445ed1f74012f28
parent14be4252eae2ce40abec5872bf6011891d753433 (diff)
m68knommu: refactor Coldfire GPIO not to require GPIOLIB, eliminate mcf_gpio_chips.
If we're not connecting external GPIO extenders via i2c or spi or whatever, we probably don't need GPIOLIB. If we provide an alternate implementation of the GPIOLIB functions to use when only on-chip GPIO is needed, we can change ARCH_REQUIRE_GPIOLIB to ARCH_WANTS_OPTIONAL_GPIOLIB so that GPIOLIB becomes optional. The downside is that in the GPIOLIB=n case, we lose all error checking done by gpiolib, ie multiply allocating the gpio, free'ing gpio etc., so that the only checking that can be done is if we reference a gpio on an external part. Targets that need the extra error checking can still select GPIOLIB=y. For the case where GPIOLIB=y, we can simplify the table of gpio chips to use a single chip, eliminating the tables of chips in the 5xxx.c files. The original motivation for the definition of multiple chips was to match the way many of the Coldfire variants defined their gpio as a spare array in memory. However, all this really gains us is some error checking when we request a gpio, gpiolib can check that it doesn't fall in one of the holes. If thats important, I think we can still come up with a better way of accomplishing that. Also in this patch is some general cleanup and reorganizing of the gpio header files (I'm sure I must have had a reason why I sometimes used a prefix of mcf_gpio and other times mcfgpio but for the life of me I can't think of it now). Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat
-rw-r--r--arch/m68k/Kconfig.cpu2
-rw-r--r--arch/m68k/include/asm/gpio.h169
-rw-r--r--arch/m68k/include/asm/mcfgpio.h329
-rw-r--r--arch/m68k/include/asm/pinmux.h30
-rw-r--r--arch/m68k/platform/coldfire/Makefile2
-rw-r--r--arch/m68k/platform/coldfire/gpio.c172
-rw-r--r--arch/m68k/platform/coldfire/m5206.c9
-rw-r--r--arch/m68k/platform/coldfire/m520x.c16
-rw-r--r--arch/m68k/platform/coldfire/m523x.c22
-rw-r--r--arch/m68k/platform/coldfire/m5249.c10
-rw-r--r--arch/m68k/platform/coldfire/m5272.c11
-rw-r--r--arch/m68k/platform/coldfire/m527x.c43
-rw-r--r--arch/m68k/platform/coldfire/m528x.c33
-rw-r--r--arch/m68k/platform/coldfire/m5307.c9
-rw-r--r--arch/m68k/platform/coldfire/m532x.c25
-rw-r--r--arch/m68k/platform/coldfire/m5407.c9
-rw-r--r--arch/m68k/platform/coldfire/m54xx.c7
-rw-r--r--arch/m68k/platform/coldfire/pinmux.c28
18 files changed, 375 insertions, 551 deletions
diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu
index 2b53254ad994..ff2314d5d934 100644
--- a/arch/m68k/Kconfig.cpu
+++ b/arch/m68k/Kconfig.cpu
@@ -23,7 +23,7 @@ config M68KCLASSIC
23config COLDFIRE 23config COLDFIRE
24 bool "Coldfire CPU family support" 24 bool "Coldfire CPU family support"
25 select GENERIC_GPIO 25 select GENERIC_GPIO
26 select ARCH_REQUIRE_GPIOLIB 26 select ARCH_WANT_OPTIONAL_GPIOLIB
27 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAVE_CUSTOM_GPIO_H
28 select CPU_HAS_NO_BITFIELDS 28 select CPU_HAS_NO_BITFIELDS
29 select CPU_HAS_NO_MULDIV64 29 select CPU_HAS_NO_MULDIV64
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index 00d0071de4c3..530862207ecf 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -17,170 +17,9 @@
17#define coldfire_gpio_h 17#define coldfire_gpio_h
18 18
19#include <linux/io.h> 19#include <linux/io.h>
20#include <asm-generic/gpio.h>
21#include <asm/coldfire.h> 20#include <asm/coldfire.h>
22#include <asm/mcfsim.h> 21#include <asm/mcfsim.h>
23 22#include <asm/mcfgpio.h>
24/*
25 * The Freescale Coldfire family is quite varied in how they implement GPIO.
26 * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
27 * only one port, others have multiple ports; some have a single data latch
28 * for both input and output, others have a separate pin data register to read
29 * input; some require a read-modify-write access to change an output, others
30 * have set and clear registers for some of the outputs; Some have all the
31 * GPIOs in a single control area, others have some GPIOs implemented in
32 * different modules.
33 *
34 * This implementation attempts accommodate the differences while presenting
35 * a generic interface that will optimize to as few instructions as possible.
36 */
37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
38 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
39 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
40 defined(CONFIG_M532x) || defined(CONFIG_M54xx)
41
42/* These parts have GPIO organized by 8 bit ports */
43
44#define MCFGPIO_PORTTYPE u8
45#define MCFGPIO_PORTSIZE 8
46#define mcfgpio_read(port) __raw_readb(port)
47#define mcfgpio_write(data, port) __raw_writeb(data, port)
48
49#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
50
51/* These parts have GPIO organized by 16 bit ports */
52
53#define MCFGPIO_PORTTYPE u16
54#define MCFGPIO_PORTSIZE 16
55#define mcfgpio_read(port) __raw_readw(port)
56#define mcfgpio_write(data, port) __raw_writew(data, port)
57
58#elif defined(CONFIG_M5249)
59
60/* These parts have GPIO organized by 32 bit ports */
61
62#define MCFGPIO_PORTTYPE u32
63#define MCFGPIO_PORTSIZE 32
64#define mcfgpio_read(port) __raw_readl(port)
65#define mcfgpio_write(data, port) __raw_writel(data, port)
66
67#endif
68
69#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
70#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
71
72#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
73 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
74/*
75 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
76 * read-modify-write to change an output and a GPIO module which has separate
77 * set/clr registers to directly change outputs with a single write access.
78 */
79#if defined(CONFIG_M528x)
80/*
81 * The 528x also has GPIOs in other modules (GPT, QADC) which use
82 * read-modify-write as well as those controlled by the EPORT and GPIO modules.
83 */
84#define MCFGPIO_SCR_START 40
85#else
86#define MCFGPIO_SCR_START 8
87#endif
88
89#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
90 mcfgpio_port(gpio - MCFGPIO_SCR_START))
91
92#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
93 mcfgpio_port(gpio - MCFGPIO_SCR_START))
94#else
95
96#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
97/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
98#define MCFGPIO_SETR_PORT(gpio) 0
99#define MCFGPIO_CLRR_PORT(gpio) 0
100
101#endif
102/*
103 * Coldfire specific helper functions
104 */
105
106/* return the port pin data register for a gpio */
107static inline u32 __mcf_gpio_ppdr(unsigned gpio)
108{
109#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
110 defined(CONFIG_M5307) || defined(CONFIG_M5407)
111 return MCFSIM_PADAT;
112#elif defined(CONFIG_M5272)
113 if (gpio < 16)
114 return MCFSIM_PADAT;
115 else if (gpio < 32)
116 return MCFSIM_PBDAT;
117 else
118 return MCFSIM_PCDAT;
119#elif defined(CONFIG_M5249)
120 if (gpio < 32)
121 return MCFSIM2_GPIOREAD;
122 else
123 return MCFSIM2_GPIO1READ;
124#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
125 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
126 if (gpio < 8)
127 return MCFEPORT_EPPDR;
128#if defined(CONFIG_M528x)
129 else if (gpio < 16)
130 return MCFGPTA_GPTPORT;
131 else if (gpio < 24)
132 return MCFGPTB_GPTPORT;
133 else if (gpio < 32)
134 return MCFQADC_PORTQA;
135 else if (gpio < 40)
136 return MCFQADC_PORTQB;
137#endif
138 else
139 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
140#else
141 return 0;
142#endif
143}
144
145/* return the port output data register for a gpio */
146static inline u32 __mcf_gpio_podr(unsigned gpio)
147{
148#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
149 defined(CONFIG_M5307) || defined(CONFIG_M5407)
150 return MCFSIM_PADAT;
151#elif defined(CONFIG_M5272)
152 if (gpio < 16)
153 return MCFSIM_PADAT;
154 else if (gpio < 32)
155 return MCFSIM_PBDAT;
156 else
157 return MCFSIM_PCDAT;
158#elif defined(CONFIG_M5249)
159 if (gpio < 32)
160 return MCFSIM2_GPIOWRITE;
161 else
162 return MCFSIM2_GPIO1WRITE;
163#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
164 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
165 if (gpio < 8)
166 return MCFEPORT_EPDR;
167#if defined(CONFIG_M528x)
168 else if (gpio < 16)
169 return MCFGPTA_GPTPORT;
170 else if (gpio < 24)
171 return MCFGPTB_GPTPORT;
172 else if (gpio < 32)
173 return MCFQADC_PORTQA;
174 else if (gpio < 40)
175 return MCFQADC_PORTQB;
176#endif
177 else
178 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
179#else
180 return 0;
181#endif
182}
183
184/* 23/*
185 * The Generic GPIO functions 24 * The Generic GPIO functions
186 * 25 *
@@ -191,7 +30,7 @@ static inline u32 __mcf_gpio_podr(unsigned gpio)
191static inline int gpio_get_value(unsigned gpio) 30static inline int gpio_get_value(unsigned gpio)
192{ 31{
193 if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX) 32 if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX)
194 return mcfgpio_read(__mcf_gpio_ppdr(gpio)) & mcfgpio_bit(gpio); 33 return mcfgpio_read(__mcfgpio_ppdr(gpio)) & mcfgpio_bit(gpio);
195 else 34 else
196 return __gpio_get_value(gpio); 35 return __gpio_get_value(gpio);
197} 36}
@@ -204,12 +43,12 @@ static inline void gpio_set_value(unsigned gpio, int value)
204 MCFGPIO_PORTTYPE data; 43 MCFGPIO_PORTTYPE data;
205 44
206 local_irq_save(flags); 45 local_irq_save(flags);
207 data = mcfgpio_read(__mcf_gpio_podr(gpio)); 46 data = mcfgpio_read(__mcfgpio_podr(gpio));
208 if (value) 47 if (value)
209 data |= mcfgpio_bit(gpio); 48 data |= mcfgpio_bit(gpio);
210 else 49 else
211 data &= ~mcfgpio_bit(gpio); 50 data &= ~mcfgpio_bit(gpio);
212 mcfgpio_write(data, __mcf_gpio_podr(gpio)); 51 mcfgpio_write(data, __mcfgpio_podr(gpio));
213 local_irq_restore(flags); 52 local_irq_restore(flags);
214 } else { 53 } else {
215 if (value) 54 if (value)
diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h
index fe468eaa51e0..67ba20ffedbe 100644
--- a/arch/m68k/include/asm/mcfgpio.h
+++ b/arch/m68k/include/asm/mcfgpio.h
@@ -16,82 +16,275 @@
16#ifndef mcfgpio_h 16#ifndef mcfgpio_h
17#define mcfgpio_h 17#define mcfgpio_h
18 18
19#include <linux/io.h> 19#ifdef CONFIG_GPIOLIB
20#include <asm-generic/gpio.h> 20#include <asm-generic/gpio.h>
21#else
22
23int __mcfgpio_get_value(unsigned gpio);
24void __mcfgpio_set_value(unsigned gpio, int value);
25int __mcfgpio_direction_input(unsigned gpio);
26int __mcfgpio_direction_output(unsigned gpio, int value);
27int __mcfgpio_request(unsigned gpio);
28void __mcfgpio_free(unsigned gpio);
29
30/* our alternate 'gpiolib' functions */
31static inline int __gpio_get_value(unsigned gpio)
32{
33 if (gpio < MCFGPIO_PIN_MAX)
34 return __mcfgpio_get_value(gpio);
35 else
36 return -EINVAL;
37}
38
39static inline void __gpio_set_value(unsigned gpio, int value)
40{
41 if (gpio < MCFGPIO_PIN_MAX)
42 __mcfgpio_set_value(gpio, value);
43}
44
45static inline int __gpio_cansleep(unsigned gpio)
46{
47 if (gpio < MCFGPIO_PIN_MAX)
48 return 0;
49 else
50 return -EINVAL;
51}
52
53static inline int __gpio_to_irq(unsigned gpio)
54{
55 return -EINVAL;
56}
57
58static inline int gpio_direction_input(unsigned gpio)
59{
60 if (gpio < MCFGPIO_PIN_MAX)
61 return __mcfgpio_direction_input(gpio);
62 else
63 return -EINVAL;
64}
65
66static inline int gpio_direction_output(unsigned gpio, int value)
67{
68 if (gpio < MCFGPIO_PIN_MAX)
69 return __mcfgpio_direction_output(gpio, value);
70 else
71 return -EINVAL;
72}
73
74static inline int gpio_request(unsigned gpio, const char *label)
75{
76 if (gpio < MCFGPIO_PIN_MAX)
77 return __mcfgpio_request(gpio);
78 else
79 return -EINVAL;
80}
81
82static inline void gpio_free(unsigned gpio)
83{
84 if (gpio < MCFGPIO_PIN_MAX)
85 __mcfgpio_free(gpio);
86}
87
88#endif /* CONFIG_GPIOLIB */
21 89
22struct mcf_gpio_chip {
23 struct gpio_chip gpio_chip;
24 void __iomem *pddr;
25 void __iomem *podr;
26 void __iomem *ppdr;
27 void __iomem *setr;
28 void __iomem *clrr;
29 const u8 *gpio_to_pinmux;
30};
31
32extern struct mcf_gpio_chip mcf_gpio_chips[];
33extern unsigned int mcf_gpio_chips_size;
34
35int mcf_gpio_direction_input(struct gpio_chip *, unsigned);
36int mcf_gpio_get_value(struct gpio_chip *, unsigned);
37int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int);
38void mcf_gpio_set_value(struct gpio_chip *, unsigned, int);
39void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int);
40int mcf_gpio_request(struct gpio_chip *, unsigned);
41void mcf_gpio_free(struct gpio_chip *, unsigned);
42 90
43/* 91/*
44 * Define macros to ease the pain of setting up the GPIO tables. There 92 * The Freescale Coldfire family is quite varied in how they implement GPIO.
45 * are two cases we need to deal with here, they cover all currently 93 * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
46 * available ColdFire GPIO hardware. There are of course minor differences 94 * only one port, others have multiple ports; some have a single data latch
47 * in the layout and number of bits in each ColdFire part, but the macros 95 * for both input and output, others have a separate pin data register to read
48 * take all that in. 96 * input; some require a read-modify-write access to change an output, others
97 * have set and clear registers for some of the outputs; Some have all the
98 * GPIOs in a single control area, others have some GPIOs implemented in
99 * different modules.
49 * 100 *
50 * Firstly is the conventional GPIO registers where we toggle individual 101 * This implementation attempts accommodate the differences while presenting
51 * bits in a register, preserving the other bits in the register. For 102 * a generic interface that will optimize to as few instructions as possible.
52 * lack of a better term I have called this the slow method.
53 */ 103 */
54#define MCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr) \ 104#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
55 { \ 105 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
56 .gpio_chip = { \ 106 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
57 .label = #mlabel, \ 107 defined(CONFIG_M532x) || defined(CONFIG_M54xx)
58 .request = mcf_gpio_request, \ 108
59 .free = mcf_gpio_free, \ 109/* These parts have GPIO organized by 8 bit ports */
60 .direction_input = mcf_gpio_direction_input, \ 110
61 .direction_output = mcf_gpio_direction_output,\ 111#define MCFGPIO_PORTTYPE u8
62 .get = mcf_gpio_get_value, \ 112#define MCFGPIO_PORTSIZE 8
63 .set = mcf_gpio_set_value, \ 113#define mcfgpio_read(port) __raw_readb(port)
64 .base = mbase, \ 114#define mcfgpio_write(data, port) __raw_writeb(data, port)
65 .ngpio = mngpio, \ 115
66 }, \ 116#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
67 .pddr = (void __iomem *) mpddr, \ 117
68 .podr = (void __iomem *) mpodr, \ 118/* These parts have GPIO organized by 16 bit ports */
69 .ppdr = (void __iomem *) mppdr, \ 119
70 } 120#define MCFGPIO_PORTTYPE u16
121#define MCFGPIO_PORTSIZE 16
122#define mcfgpio_read(port) __raw_readw(port)
123#define mcfgpio_write(data, port) __raw_writew(data, port)
124
125#elif defined(CONFIG_M5249)
126
127/* These parts have GPIO organized by 32 bit ports */
128
129#define MCFGPIO_PORTTYPE u32
130#define MCFGPIO_PORTSIZE 32
131#define mcfgpio_read(port) __raw_readl(port)
132#define mcfgpio_write(data, port) __raw_writel(data, port)
133
134#endif
71 135
136#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
137#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
138
139#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
140 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
141/*
142 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
143 * read-modify-write to change an output and a GPIO module which has separate
144 * set/clr registers to directly change outputs with a single write access.
145 */
146#if defined(CONFIG_M528x)
72/* 147/*
73 * Secondly is the faster case, where we have set and clear registers 148 * The 528x also has GPIOs in other modules (GPT, QADC) which use
74 * that allow us to set or clear a bit with a single write, not having 149 * read-modify-write as well as those controlled by the EPORT and GPIO modules.
75 * to worry about preserving other bits.
76 */ 150 */
77#define MCFGPF(mlabel, mbase, mngpio) \ 151#define MCFGPIO_SCR_START 40
78 { \ 152#else
79 .gpio_chip = { \ 153#define MCFGPIO_SCR_START 8
80 .label = #mlabel, \ 154#endif
81 .request = mcf_gpio_request, \ 155
82 .free = mcf_gpio_free, \ 156#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
83 .direction_input = mcf_gpio_direction_input, \ 157 mcfgpio_port(gpio - MCFGPIO_SCR_START))
84 .direction_output = mcf_gpio_direction_output,\ 158
85 .get = mcf_gpio_get_value, \ 159#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
86 .set = mcf_gpio_set_value_fast, \ 160 mcfgpio_port(gpio - MCFGPIO_SCR_START))
87 .base = mbase, \ 161#else
88 .ngpio = mngpio, \ 162
89 }, \ 163#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
90 .pddr = (void __iomem *) MCFGPIO_PDDR_##mlabel, \ 164/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
91 .podr = (void __iomem *) MCFGPIO_PODR_##mlabel, \ 165#define MCFGPIO_SETR_PORT(gpio) 0
92 .ppdr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \ 166#define MCFGPIO_CLRR_PORT(gpio) 0
93 .setr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
94 .clrr = (void __iomem *) MCFGPIO_PCLRR_##mlabel, \
95 }
96 167
97#endif 168#endif
169/*
170 * Coldfire specific helper functions
171 */
172
173/* return the port pin data register for a gpio */
174static inline u32 __mcfgpio_ppdr(unsigned gpio)
175{
176#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
177 defined(CONFIG_M5307) || defined(CONFIG_M5407)
178 return MCFSIM_PADAT;
179#elif defined(CONFIG_M5272)
180 if (gpio < 16)
181 return MCFSIM_PADAT;
182 else if (gpio < 32)
183 return MCFSIM_PBDAT;
184 else
185 return MCFSIM_PCDAT;
186#elif defined(CONFIG_M5249)
187 if (gpio < 32)
188 return MCFSIM2_GPIOREAD;
189 else
190 return MCFSIM2_GPIO1READ;
191#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
192 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
193 if (gpio < 8)
194 return MCFEPORT_EPPDR;
195#if defined(CONFIG_M528x)
196 else if (gpio < 16)
197 return MCFGPTA_GPTPORT;
198 else if (gpio < 24)
199 return MCFGPTB_GPTPORT;
200 else if (gpio < 32)
201 return MCFQADC_PORTQA;
202 else if (gpio < 40)
203 return MCFQADC_PORTQB;
204#endif
205 else
206 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
207#else
208 return 0;
209#endif
210}
211
212/* return the port output data register for a gpio */
213static inline u32 __mcfgpio_podr(unsigned gpio)
214{
215#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
216 defined(CONFIG_M5307) || defined(CONFIG_M5407)
217 return MCFSIM_PADAT;
218#elif defined(CONFIG_M5272)
219 if (gpio < 16)
220 return MCFSIM_PADAT;
221 else if (gpio < 32)
222 return MCFSIM_PBDAT;
223 else
224 return MCFSIM_PCDAT;
225#elif defined(CONFIG_M5249)
226 if (gpio < 32)
227 return MCFSIM2_GPIOWRITE;
228 else
229 return MCFSIM2_GPIO1WRITE;
230#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
231 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
232 if (gpio < 8)
233 return MCFEPORT_EPDR;
234#if defined(CONFIG_M528x)
235 else if (gpio < 16)
236 return MCFGPTA_GPTPORT;
237 else if (gpio < 24)
238 return MCFGPTB_GPTPORT;
239 else if (gpio < 32)
240 return MCFQADC_PORTQA;
241 else if (gpio < 40)
242 return MCFQADC_PORTQB;
243#endif
244 else
245 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
246#else
247 return 0;
248#endif
249}
250
251/* return the port direction data register for a gpio */
252static inline u32 __mcfgpio_pddr(unsigned gpio)
253{
254#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
255 defined(CONFIG_M5307) || defined(CONFIG_M5407)
256 return MCFSIM_PADDR;
257#elif defined(CONFIG_M5272)
258 if (gpio < 16)
259 return MCFSIM_PADDR;
260 else if (gpio < 32)
261 return MCFSIM_PBDDR;
262 else
263 return MCFSIM_PCDDR;
264#elif defined(CONFIG_M5249)
265 if (gpio < 32)
266 return MCFSIM2_GPIOENABLE;
267 else
268 return MCFSIM2_GPIO1ENABLE;
269#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
270 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
271 if (gpio < 8)
272 return MCFEPORT_EPDDR;
273#if defined(CONFIG_M528x)
274 else if (gpio < 16)
275 return MCFGPTA_GPTDDR;
276 else if (gpio < 24)
277 return MCFGPTB_GPTDDR;
278 else if (gpio < 32)
279 return MCFQADC_DDRQA;
280 else if (gpio < 40)
281 return MCFQADC_DDRQB;
282#endif
283 else
284 return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
285#else
286 return 0;
287#endif
288}
289
290#endif /* mcfgpio_h */
diff --git a/arch/m68k/include/asm/pinmux.h b/arch/m68k/include/asm/pinmux.h
deleted file mode 100644
index 119ee686dbd1..000000000000
--- a/arch/m68k/include/asm/pinmux.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Coldfire generic GPIO pinmux support.
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef pinmux_h
17#define pinmux_h
18
19#define MCFPINMUX_NONE -1
20
21extern int mcf_pinmux_request(unsigned, unsigned);
22extern void mcf_pinmux_release(unsigned, unsigned);
23
24static inline int mcf_pinmux_is_valid(unsigned pinmux)
25{
26 return pinmux != MCFPINMUX_NONE;
27}
28
29#endif
30
diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile
index 76d389d9a84e..69bc0ae2538d 100644
--- a/arch/m68k/platform/coldfire/Makefile
+++ b/arch/m68k/platform/coldfire/Makefile
@@ -32,5 +32,5 @@ obj-$(CONFIG_NETtel) += nettel.o
32obj-$(CONFIG_CLEOPATRA) += nettel.o 32obj-$(CONFIG_CLEOPATRA) += nettel.o
33obj-$(CONFIG_FIREBEE) += firebee.o 33obj-$(CONFIG_FIREBEE) += firebee.o
34 34
35obj-y += pinmux.o gpio.o 35obj-y += gpio.o
36extra-y := head.o 36extra-y := head.o
diff --git a/arch/m68k/platform/coldfire/gpio.c b/arch/m68k/platform/coldfire/gpio.c
index 4c8c42450a4e..9cd2b5c70519 100644
--- a/arch/m68k/platform/coldfire/gpio.c
+++ b/arch/m68k/platform/coldfire/gpio.c
@@ -14,119 +14,161 @@
14 */ 14 */
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/module.h>
17#include <linux/init.h> 18#include <linux/init.h>
18#include <linux/device.h> 19#include <linux/device.h>
19 20
20#include <asm/gpio.h> 21#include <linux/io.h>
21#include <asm/pinmux.h> 22#include <asm/coldfire.h>
23#include <asm/mcfsim.h>
22#include <asm/mcfgpio.h> 24#include <asm/mcfgpio.h>
23 25
24#define MCF_CHIP(chip) container_of(chip, struct mcf_gpio_chip, gpio_chip) 26int __mcfgpio_get_value(unsigned gpio)
27{
28 return mcfgpio_read(__mcfgpio_ppdr(gpio)) & mcfgpio_bit(gpio);
29}
30EXPORT_SYMBOL(__mcfgpio_get_value);
31
32void __mcfgpio_set_value(unsigned gpio, int value)
33{
34 if (gpio < MCFGPIO_SCR_START) {
35 unsigned long flags;
36 MCFGPIO_PORTTYPE data;
37
38 local_irq_save(flags);
39 data = mcfgpio_read(__mcfgpio_podr(gpio));
40 if (value)
41 data |= mcfgpio_bit(gpio);
42 else
43 data &= ~mcfgpio_bit(gpio);
44 mcfgpio_write(data, __mcfgpio_podr(gpio));
45 local_irq_restore(flags);
46 } else {
47 if (value)
48 mcfgpio_write(mcfgpio_bit(gpio),
49 MCFGPIO_SETR_PORT(gpio));
50 else
51 mcfgpio_write(~mcfgpio_bit(gpio),
52 MCFGPIO_CLRR_PORT(gpio));
53 }
54}
55EXPORT_SYMBOL(__mcfgpio_set_value);
25 56
26int mcf_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 57int __mcfgpio_direction_input(unsigned gpio)
27{ 58{
28 unsigned long flags; 59 unsigned long flags;
29 MCFGPIO_PORTTYPE dir; 60 MCFGPIO_PORTTYPE dir;
30 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
31 61
32 local_irq_save(flags); 62 local_irq_save(flags);
33 dir = mcfgpio_read(mcf_chip->pddr); 63 dir = mcfgpio_read(__mcfgpio_pddr(gpio));
34 dir &= ~mcfgpio_bit(chip->base + offset); 64 dir &= ~mcfgpio_bit(gpio);
35 mcfgpio_write(dir, mcf_chip->pddr); 65 mcfgpio_write(dir, __mcfgpio_pddr(gpio));
36 local_irq_restore(flags); 66 local_irq_restore(flags);
37 67
38 return 0; 68 return 0;
39} 69}
70EXPORT_SYMBOL(__mcfgpio_direction_input);
40 71
41int mcf_gpio_get_value(struct gpio_chip *chip, unsigned offset) 72int __mcfgpio_direction_output(unsigned gpio, int value)
42{
43 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
44
45 return mcfgpio_read(mcf_chip->ppdr) & mcfgpio_bit(chip->base + offset);
46}
47
48int mcf_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
49 int value)
50{ 73{
51 unsigned long flags; 74 unsigned long flags;
52 MCFGPIO_PORTTYPE data; 75 MCFGPIO_PORTTYPE data;
53 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
54 76
55 local_irq_save(flags); 77 local_irq_save(flags);
56 /* write the value to the output latch */ 78 data = mcfgpio_read(__mcfgpio_pddr(gpio));
57 data = mcfgpio_read(mcf_chip->podr);
58 if (value) 79 if (value)
59 data |= mcfgpio_bit(chip->base + offset); 80 data |= mcfgpio_bit(gpio);
60 else 81 else
61 data &= ~mcfgpio_bit(chip->base + offset); 82 data &= mcfgpio_bit(gpio);
62 mcfgpio_write(data, mcf_chip->podr); 83 mcfgpio_write(data, __mcfgpio_pddr(gpio));
63 84
64 /* now set the direction to output */ 85 /* now set the data to output */
65 data = mcfgpio_read(mcf_chip->pddr); 86 if (gpio < MCFGPIO_SCR_START) {
66 data |= mcfgpio_bit(chip->base + offset); 87 data = mcfgpio_read(__mcfgpio_podr(gpio));
67 mcfgpio_write(data, mcf_chip->pddr); 88 if (value)
89 data |= mcfgpio_bit(gpio);
90 else
91 data &= ~mcfgpio_bit(gpio);
92 mcfgpio_write(data, __mcfgpio_podr(gpio));
93 } else {
94 if (value)
95 mcfgpio_write(mcfgpio_bit(gpio),
96 MCFGPIO_SETR_PORT(gpio));
97 else
98 mcfgpio_write(~mcfgpio_bit(gpio),
99 MCFGPIO_CLRR_PORT(gpio));
100 }
68 local_irq_restore(flags); 101 local_irq_restore(flags);
102 return 0;
103}
104EXPORT_SYMBOL(__mcfgpio_direction_output);
69 105
106int __mcfgpio_request(unsigned gpio)
107{
70 return 0; 108 return 0;
71} 109}
110EXPORT_SYMBOL(__mcfgpio_request);
72 111
73void mcf_gpio_set_value(struct gpio_chip *chip, unsigned offset, int value) 112void __mcfgpio_free(unsigned gpio)
74{ 113{
75 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); 114 __mcfgpio_direction_input(gpio);
115}
116EXPORT_SYMBOL(__mcfgpio_free);
76 117
77 unsigned long flags; 118#ifdef CONFIG_GPIOLIB
78 MCFGPIO_PORTTYPE data;
79 119
80 local_irq_save(flags); 120int mcfgpio_direction_input(struct gpio_chip *chip, unsigned offset)
81 data = mcfgpio_read(mcf_chip->podr); 121{
82 if (value) 122 return __mcfgpio_direction_input(offset);
83 data |= mcfgpio_bit(chip->base + offset);
84 else
85 data &= ~mcfgpio_bit(chip->base + offset);
86 mcfgpio_write(data, mcf_chip->podr);
87 local_irq_restore(flags);
88} 123}
89 124
90void mcf_gpio_set_value_fast(struct gpio_chip *chip, unsigned offset, int value) 125int mcfgpio_get_value(struct gpio_chip *chip, unsigned offset)
91{ 126{
92 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); 127 return __mcfgpio_get_value(offset);
93
94 if (value)
95 mcfgpio_write(mcfgpio_bit(chip->base + offset), mcf_chip->setr);
96 else
97 mcfgpio_write(~mcfgpio_bit(chip->base + offset), mcf_chip->clrr);
98} 128}
99 129
100int mcf_gpio_request(struct gpio_chip *chip, unsigned offset) 130int mcfgpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
101{ 131{
102 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); 132 return __mcfgpio_direction_output(offset, value);
103
104 return mcf_chip->gpio_to_pinmux ?
105 mcf_pinmux_request(mcf_chip->gpio_to_pinmux[offset], 0) : 0;
106} 133}
107 134
108void mcf_gpio_free(struct gpio_chip *chip, unsigned offset) 135void mcfgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
109{ 136{
110 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); 137 __mcfgpio_set_value(offset, value);
138}
111 139
112 mcf_gpio_direction_input(chip, offset); 140int mcfgpio_request(struct gpio_chip *chip, unsigned offset)
141{
142 return __mcfgpio_request(offset);
143}
113 144
114 if (mcf_chip->gpio_to_pinmux) 145void mcfgpio_free(struct gpio_chip *chip, unsigned offset)
115 mcf_pinmux_release(mcf_chip->gpio_to_pinmux[offset], 0); 146{
147 __mcfgpio_free(offset);
116} 148}
117 149
118struct bus_type mcf_gpio_subsys = { 150struct bus_type mcfgpio_subsys = {
119 .name = "gpio", 151 .name = "gpio",
120 .dev_name = "gpio", 152 .dev_name = "gpio",
121}; 153};
122 154
123static int __init mcf_gpio_sysinit(void) 155static struct gpio_chip mcfgpio_chip = {
124{ 156 .label = "mcfgpio",
125 unsigned int i = 0; 157 .request = mcfgpio_request,
158 .free = mcfgpio_free,
159 .direction_input = mcfgpio_direction_input,
160 .direction_output = mcfgpio_direction_output,
161 .get = mcfgpio_get_value,
162 .set = mcfgpio_set_value,
163 .base = 0,
164 .ngpio = MCFGPIO_PIN_MAX,
165};
126 166
127 while (i < mcf_gpio_chips_size) 167static int __init mcfgpio_sysinit(void)
128 gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); 168{
129 return subsys_system_register(&mcf_gpio_subsys, NULL); 169 gpiochip_add(&mcfgpio_chip);
170 return subsys_system_register(&mcfgpio_subsys, NULL);
130} 171}
131 172
132core_initcall(mcf_gpio_sysinit); 173core_initcall(mcfgpio_sysinit);
174#endif
diff --git a/arch/m68k/platform/coldfire/m5206.c b/arch/m68k/platform/coldfire/m5206.c
index a8b81df653f0..6bfbeebd231b 100644
--- a/arch/m68k/platform/coldfire/m5206.c
+++ b/arch/m68k/platform/coldfire/m5206.c
@@ -16,15 +16,6 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfgpio.h>
20
21/***************************************************************************/
22
23struct mcf_gpio_chip mcf_gpio_chips[] = {
24 MCFGPS(PP, 0, 8, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
25};
26
27unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
28 19
29/***************************************************************************/ 20/***************************************************************************/
30 21
diff --git a/arch/m68k/platform/coldfire/m520x.c b/arch/m68k/platform/coldfire/m520x.c
index 3264b8883d5f..09df4b89e8be 100644
--- a/arch/m68k/platform/coldfire/m520x.c
+++ b/arch/m68k/platform/coldfire/m520x.c
@@ -19,22 +19,6 @@
19#include <asm/coldfire.h> 19#include <asm/coldfire.h>
20#include <asm/mcfsim.h> 20#include <asm/mcfsim.h>
21#include <asm/mcfuart.h> 21#include <asm/mcfuart.h>
22#include <asm/mcfgpio.h>
23
24/***************************************************************************/
25
26struct mcf_gpio_chip mcf_gpio_chips[] = {
27 MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
28 MCFGPF(CS, 9, 3),
29 MCFGPF(FECI2C, 16, 4),
30 MCFGPF(QSPI, 24, 4),
31 MCFGPF(TIMER, 32, 4),
32 MCFGPF(UART, 40, 8),
33 MCFGPF(FECH, 48, 8),
34 MCFGPF(FECL, 56, 8),
35};
36
37unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
38 22
39/***************************************************************************/ 23/***************************************************************************/
40 24
diff --git a/arch/m68k/platform/coldfire/m523x.c b/arch/m68k/platform/coldfire/m523x.c
index 5d57a4249412..d47dfd8f50a2 100644
--- a/arch/m68k/platform/coldfire/m523x.c
+++ b/arch/m68k/platform/coldfire/m523x.c
@@ -19,28 +19,6 @@
19#include <asm/machdep.h> 19#include <asm/machdep.h>
20#include <asm/coldfire.h> 20#include <asm/coldfire.h>
21#include <asm/mcfsim.h> 21#include <asm/mcfsim.h>
22#include <asm/mcfgpio.h>
23
24/***************************************************************************/
25
26struct mcf_gpio_chip mcf_gpio_chips[] = {
27 MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
28 MCFGPF(ADDR, 13, 3),
29 MCFGPF(DATAH, 16, 8),
30 MCFGPF(DATAL, 24, 8),
31 MCFGPF(BUSCTL, 32, 8),
32 MCFGPF(BS, 40, 4),
33 MCFGPF(CS, 49, 7),
34 MCFGPF(SDRAM, 56, 6),
35 MCFGPF(FECI2C, 64, 4),
36 MCFGPF(UARTH, 72, 2),
37 MCFGPF(UARTL, 80, 8),
38 MCFGPF(QSPI, 88, 5),
39 MCFGPF(TIMER, 96, 8),
40 MCFGPF(ETPU, 104, 3),
41};
42
43unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
44 22
45/***************************************************************************/ 23/***************************************************************************/
46 24
diff --git a/arch/m68k/platform/coldfire/m5249.c b/arch/m68k/platform/coldfire/m5249.c
index fdfa1edfd1ac..300e729a58d0 100644
--- a/arch/m68k/platform/coldfire/m5249.c
+++ b/arch/m68k/platform/coldfire/m5249.c
@@ -16,16 +16,6 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfgpio.h>
20
21/***************************************************************************/
22
23struct mcf_gpio_chip mcf_gpio_chips[] = {
24 MCFGPS(GPIO0, 0, 32, MCFSIM2_GPIOENABLE, MCFSIM2_GPIOWRITE, MCFSIM2_GPIOREAD),
25 MCFGPS(GPIO1, 32, 32, MCFSIM2_GPIO1ENABLE, MCFSIM2_GPIO1WRITE, MCFSIM2_GPIO1READ),
26};
27
28unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
29 19
30/***************************************************************************/ 20/***************************************************************************/
31 21
diff --git a/arch/m68k/platform/coldfire/m5272.c b/arch/m68k/platform/coldfire/m5272.c
index 43e36060da18..e68bc7a148eb 100644
--- a/arch/m68k/platform/coldfire/m5272.c
+++ b/arch/m68k/platform/coldfire/m5272.c
@@ -19,7 +19,6 @@
19#include <asm/coldfire.h> 19#include <asm/coldfire.h>
20#include <asm/mcfsim.h> 20#include <asm/mcfsim.h>
21#include <asm/mcfuart.h> 21#include <asm/mcfuart.h>
22#include <asm/mcfgpio.h>
23 22
24/***************************************************************************/ 23/***************************************************************************/
25 24
@@ -31,16 +30,6 @@ unsigned char ledbank = 0xff;
31 30
32/***************************************************************************/ 31/***************************************************************************/
33 32
34struct mcf_gpio_chip mcf_gpio_chips[] = {
35 MCFGPS(PA, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
36 MCFGPS(PB, 16, 16, MCFSIM_PBDDR, MCFSIM_PBDAT, MCFSIM_PBDAT),
37 MCFGPS(Pc, 32, 16, MCFSIM_PCDDR, MCFSIM_PCDAT, MCFSIM_PCDAT),
38};
39
40unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
41
42/***************************************************************************/
43
44static void __init m5272_uarts_init(void) 33static void __init m5272_uarts_init(void)
45{ 34{
46 u32 v; 35 u32 v;
diff --git a/arch/m68k/platform/coldfire/m527x.c b/arch/m68k/platform/coldfire/m527x.c
index 9b0b66aabd1b..b3cb378c5e94 100644
--- a/arch/m68k/platform/coldfire/m527x.c
+++ b/arch/m68k/platform/coldfire/m527x.c
@@ -20,49 +20,6 @@
20#include <asm/coldfire.h> 20#include <asm/coldfire.h>
21#include <asm/mcfsim.h> 21#include <asm/mcfsim.h>
22#include <asm/mcfuart.h> 22#include <asm/mcfuart.h>
23#include <asm/mcfgpio.h>
24
25/***************************************************************************/
26
27struct mcf_gpio_chip mcf_gpio_chips[] = {
28#if defined(CONFIG_M5271)
29 MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
30 MCFGPF(ADDR, 13, 3),
31 MCFGPF(DATAH, 16, 8),
32 MCFGPF(DATAL, 24, 8),
33 MCFGPF(BUSCTL, 32, 8),
34 MCFGPF(BS, 40, 4),
35 MCFGPF(CS, 49, 7),
36 MCFGPF(SDRAM, 56, 6),
37 MCFGPF(FECI2C, 64, 4),
38 MCFGPF(UARTH, 72, 2),
39 MCFGPF(UARTL, 80, 8),
40 MCFGPF(QSPI, 88, 5),
41 MCFGPF(TIMER, 96, 8),
42#elif defined(CONFIG_M5275)
43 MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
44 MCFGPF(BUSCTL, 8, 8),
45 MCFGPF(ADDR, 21, 3),
46 MCFGPF(CS, 25, 7),
47 MCFGPF(FEC0H, 32, 8),
48 MCFGPF(FEC0L, 40, 8),
49 MCFGPF(FECI2C, 48, 6),
50 MCFGPF(QSPI, 56, 7),
51 MCFGPF(SDRAM, 64, 8),
52 MCFGPF(TIMERH, 72, 4),
53 MCFGPF(TIMERL, 80, 4),
54 MCFGPF(UARTL, 88, 8),
55 MCFGPF(FEC1H, 96, 8),
56 MCFGPF(FEC1L, 104, 8),
57 MCFGPF(BS, 114, 2),
58 MCFGPF(IRQ, 121, 7),
59 MCFGPF(USBH, 128, 1),
60 MCFGPF(USBL, 136, 8),
61 MCFGPF(UARTH, 144, 4),
62#endif
63};
64
65unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
66 23
67/***************************************************************************/ 24/***************************************************************************/
68 25
diff --git a/arch/m68k/platform/coldfire/m528x.c b/arch/m68k/platform/coldfire/m528x.c
index 7ed1276b29dc..f1319e5d2546 100644
--- a/arch/m68k/platform/coldfire/m528x.c
+++ b/arch/m68k/platform/coldfire/m528x.c
@@ -21,37 +21,6 @@
21#include <asm/coldfire.h> 21#include <asm/coldfire.h>
22#include <asm/mcfsim.h> 22#include <asm/mcfsim.h>
23#include <asm/mcfuart.h> 23#include <asm/mcfuart.h>
24#include <asm/mcfgpio.h>
25
26/***************************************************************************/
27
28struct mcf_gpio_chip mcf_gpio_chips[] = {
29 MCFGPS(NQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
30 MCFGPS(TA, 8, 4, MCFGPTA_GPTDDR, MCFGPTA_GPTPORT, MCFGPTB_GPTPORT),
31 MCFGPS(TB, 16, 4, MCFGPTB_GPTDDR, MCFGPTB_GPTPORT, MCFGPTB_GPTPORT),
32 MCFGPS(QA, 24, 4, MCFQADC_DDRQA, MCFQADC_PORTQA, MCFQADC_PORTQA),
33 MCFGPS(QB, 32, 4, MCFQADC_DDRQB, MCFQADC_PORTQB, MCFQADC_PORTQB),
34 MCFGPF(A, 40, 8),
35 MCFGPF(B, 48, 8),
36 MCFGPF(C, 56, 8),
37 MCFGPF(D, 64, 8),
38 MCFGPF(E, 72, 8),
39 MCFGPF(F, 80, 8),
40 MCFGPF(G, 88, 8),
41 MCFGPF(H, 96, 8),
42 MCFGPF(J, 104, 8),
43 MCFGPF(DD, 112, 8),
44 MCFGPF(EH, 120, 8),
45 MCFGPF(EL, 128, 8),
46 MCFGPF(AS, 136, 6),
47 MCFGPF(QS, 144, 7),
48 MCFGPF(SD, 152, 6),
49 MCFGPF(TC, 160, 4),
50 MCFGPF(TD, 168, 4),
51 MCFGPF(UA, 176, 4),
52};
53
54unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
55 24
56/***************************************************************************/ 25/***************************************************************************/
57 26
@@ -74,7 +43,7 @@ static void __init m528x_uarts_init(void)
74 /* make sure PUAPAR is set for UART0 and UART1 */ 43 /* make sure PUAPAR is set for UART0 and UART1 */
75 port = readb(MCF5282_GPIO_PUAPAR); 44 port = readb(MCF5282_GPIO_PUAPAR);
76 port |= 0x03 | (0x03 << 2); 45 port |= 0x03 | (0x03 << 2);
77 writeb(port, MCF5282_GPIO_PUAPAR); 46 writeb(port, MCFGPIO_PUAPAR);
78} 47}
79 48
80/***************************************************************************/ 49/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m5307.c b/arch/m68k/platform/coldfire/m5307.c
index 93b484976ab3..a568d2870d15 100644
--- a/arch/m68k/platform/coldfire/m5307.c
+++ b/arch/m68k/platform/coldfire/m5307.c
@@ -16,7 +16,6 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfgpio.h>
20#include <asm/mcfwdebug.h> 19#include <asm/mcfwdebug.h>
21 20
22/***************************************************************************/ 21/***************************************************************************/
@@ -29,14 +28,6 @@ unsigned char ledbank = 0xff;
29 28
30/***************************************************************************/ 29/***************************************************************************/
31 30
32struct mcf_gpio_chip mcf_gpio_chips[] = {
33 MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
34};
35
36unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
37
38/***************************************************************************/
39
40void __init config_BSP(char *commandp, int size) 31void __init config_BSP(char *commandp, int size)
41{ 32{
42#if defined(CONFIG_NETtel) || \ 33#if defined(CONFIG_NETtel) || \
diff --git a/arch/m68k/platform/coldfire/m532x.c b/arch/m68k/platform/coldfire/m532x.c
index 5394223639f8..21d6cb1c7004 100644
--- a/arch/m68k/platform/coldfire/m532x.c
+++ b/arch/m68k/platform/coldfire/m532x.c
@@ -26,35 +26,10 @@
26#include <asm/mcfsim.h> 26#include <asm/mcfsim.h>
27#include <asm/mcfuart.h> 27#include <asm/mcfuart.h>
28#include <asm/mcfdma.h> 28#include <asm/mcfdma.h>
29#include <asm/mcfgpio.h>
30#include <asm/mcfwdebug.h> 29#include <asm/mcfwdebug.h>
31 30
32/***************************************************************************/ 31/***************************************************************************/
33 32
34struct mcf_gpio_chip mcf_gpio_chips[] = {
35 MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
36 MCFGPF(FECH, 8, 8),
37 MCFGPF(FECL, 16, 8),
38 MCFGPF(SSI, 24, 5),
39 MCFGPF(BUSCTL, 32, 4),
40 MCFGPF(BE, 40, 4),
41 MCFGPF(CS, 49, 5),
42 MCFGPF(PWM, 58, 4),
43 MCFGPF(FECI2C, 64, 4),
44 MCFGPF(UART, 72, 8),
45 MCFGPF(QSPI, 80, 6),
46 MCFGPF(TIMER, 88, 4),
47 MCFGPF(LCDDATAH, 96, 2),
48 MCFGPF(LCDDATAM, 104, 8),
49 MCFGPF(LCDDATAL, 112, 8),
50 MCFGPF(LCDCTLH, 120, 1),
51 MCFGPF(LCDCTLL, 128, 8),
52};
53
54unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
55
56/***************************************************************************/
57
58#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 33#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
59 34
60static void __init m532x_qspi_init(void) 35static void __init m532x_qspi_init(void)
diff --git a/arch/m68k/platform/coldfire/m5407.c b/arch/m68k/platform/coldfire/m5407.c
index faa6680b3404..bb6c746ae819 100644
--- a/arch/m68k/platform/coldfire/m5407.c
+++ b/arch/m68k/platform/coldfire/m5407.c
@@ -16,15 +16,6 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfgpio.h>
20
21/***************************************************************************/
22
23struct mcf_gpio_chip mcf_gpio_chips[] = {
24 MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
25};
26
27unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
28 19
29/***************************************************************************/ 20/***************************************************************************/
30 21
diff --git a/arch/m68k/platform/coldfire/m54xx.c b/arch/m68k/platform/coldfire/m54xx.c
index 20672dadb252..2081c6cbb3de 100644
--- a/arch/m68k/platform/coldfire/m54xx.c
+++ b/arch/m68k/platform/coldfire/m54xx.c
@@ -21,19 +21,12 @@
21#include <asm/m54xxsim.h> 21#include <asm/m54xxsim.h>
22#include <asm/mcfuart.h> 22#include <asm/mcfuart.h>
23#include <asm/m54xxgpt.h> 23#include <asm/m54xxgpt.h>
24#include <asm/mcfgpio.h>
25#ifdef CONFIG_MMU 24#ifdef CONFIG_MMU
26#include <asm/mmu_context.h> 25#include <asm/mmu_context.h>
27#endif 26#endif
28 27
29/***************************************************************************/ 28/***************************************************************************/
30 29
31struct mcf_gpio_chip mcf_gpio_chips[] = { };
32
33unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
34
35/***************************************************************************/
36
37static void __init m54xx_uarts_init(void) 30static void __init m54xx_uarts_init(void)
38{ 31{
39 /* enable io pins */ 32 /* enable io pins */
diff --git a/arch/m68k/platform/coldfire/pinmux.c b/arch/m68k/platform/coldfire/pinmux.c
deleted file mode 100644
index 8c62b825939f..000000000000
--- a/arch/m68k/platform/coldfire/pinmux.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Coldfire generic GPIO pinmux support.
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/kernel.h>
18
19#include <asm/pinmux.h>
20
21int mcf_pinmux_request(unsigned pinmux, unsigned func)
22{
23 return 0;
24}
25
26void mcf_pinmux_release(unsigned pinmux, unsigned func)
27{
28}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 05:22:20 -0500