diff options
author | Maarten Lankhorst <maarten.lankhorst@canonical.com> | 2013-07-07 04:37:48 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2013-07-07 20:52:07 -0400 |
commit | d2989b534ef6834ebf2425aecc040b894b567c91 (patch) | |
tree | f4db09ba08185f5f30a09566b4bc1cb88c984dc6 | |
parent | 1bb3f6a252c92cbc07884091e185a51b4ccb4f1d (diff) |
drm/nvc0/gr: fix gpc firmware regression
"drm/nve0-/gr: some new gpc registers can have multiple copies"
5ee86c4190f9e caused a regression for nvc0, because the bit indicating last
transfer has occured was no longer set, resulting in random system lockups.
Reported-by: Ronald Uitermark <ronald645@gmail.com>
Tested-by: Ronald Uitermark <ronald645@gmail.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h | 40 |
2 files changed, 23 insertions, 20 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc index b52f4a8b8699..5547c1b3f4f2 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc | |||
@@ -352,6 +352,9 @@ ctx_xfer: | |||
352 | 352 | ||
353 | // per-TPC mmio context | 353 | // per-TPC mmio context |
354 | xbit $r10 $flags $p1 // direction | 354 | xbit $r10 $flags $p1 // direction |
355 | #if !NV_PGRAPH_GPCX_UNK__SIZE | ||
356 | or $r10 4 // last | ||
357 | #endif | ||
355 | mov $r11 0x4000 | 358 | mov $r11 0x4000 |
356 | sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0 | 359 | sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0 |
357 | ld b32 $r12 D[$r0 + #gpc_id] | 360 | ld b32 $r12 D[$r0 + #gpc_id] |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h index 2afe75ce89e9..f2b0dea80116 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h | |||
@@ -400,26 +400,26 @@ uint32_t nvc0_grgpc_code[] = { | |||
400 | 0x0d98000c, | 400 | 0x0d98000c, |
401 | 0x00e7f001, | 401 | 0x00e7f001, |
402 | 0x016621f5, | 402 | 0x016621f5, |
403 | 0xf101acf0, | 403 | 0xf001acf0, |
404 | 0xf04000b7, | 404 | 0xb7f104a5, |
405 | 0x0c9850b3, | 405 | 0xb3f04000, |
406 | 0x0fc4b604, | 406 | 0x040c9850, |
407 | 0x9800bcbb, | 407 | 0xbb0fc4b6, |
408 | 0x0d98010c, | 408 | 0x0c9800bc, |
409 | 0x060f9802, | 409 | 0x020d9801, |
410 | 0x0800e7f1, | 410 | 0xf1060f98, |
411 | 0x016621f5, | 411 | 0xf50800e7, |
412 | 0x021521f5, | 412 | 0xf5016621, |
413 | 0xf40601f4, | 413 | 0xf4021521, |
414 | /* 0x0532: ctx_xfer_post */ | 414 | 0x12f40601, |
415 | 0x17f11412, | 415 | /* 0x0535: ctx_xfer_post */ |
416 | 0x13f04afc, | 416 | 0xfc17f114, |
417 | 0x0d27f002, | 417 | 0x0213f04a, |
418 | 0xf50012d0, | 418 | 0xd00d27f0, |
419 | /* 0x0543: ctx_xfer_done */ | 419 | 0x21f50012, |
420 | 0xf5021521, | 420 | /* 0x0546: ctx_xfer_done */ |
421 | 0xf8047921, | 421 | 0x21f50215, |
422 | 0x00000000, | 422 | 0x00f80479, |
423 | 0x00000000, | 423 | 0x00000000, |
424 | 0x00000000, | 424 | 0x00000000, |
425 | 0x00000000, | 425 | 0x00000000, |