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authorYuval Mintz <yuvalmin@broadcom.com>2012-06-20 15:05:19 -0400
committerDavid S. Miller <davem@davemloft.net>2012-06-22 20:20:32 -0400
commitd231023eb17134e43bf1dcea631dd156d9904b70 (patch)
treea26da7102042d2fd69545afca22efed1a2821743
parentd0b8a6f926be5109d711937a74b8d327b29470ba (diff)
bnx2x: link cleanup
This patch does several things: 1. Add static to function when possible. 2. Correct comments. 3. Change msleep(small) --> usleep_range(small, small*2). Also correct existing calls to usleep_range. 4. Remove dead code. 5. Change 'if(rc != 0)' --> if(rc) Most of these changes are purely semantic. Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com> Signed-off-by: Yaniv Rosner <yaniv.rosner@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c340
1 files changed, 167 insertions, 173 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index 9e008e4534d4..b3c33ed2bc96 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -284,7 +284,6 @@
284#define ETS_E3B0_PBF_MIN_W_VAL (10000) 284#define ETS_E3B0_PBF_MIN_W_VAL (10000)
285 285
286#define MAX_PACKET_SIZE (9700) 286#define MAX_PACKET_SIZE (9700)
287#define WC_UC_TIMEOUT 100
288#define MAX_KR_LINK_RETRY 4 287#define MAX_KR_LINK_RETRY 4
289 288
290/**********************************************************/ 289/**********************************************************/
@@ -1627,7 +1626,7 @@ static void bnx2x_umac_enable(struct link_params *params,
1627 /* Reset UMAC */ 1626 /* Reset UMAC */
1628 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1627 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1629 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1628 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1630 usleep_range(1000, 1000); 1629 usleep_range(1000, 2000);
1631 1630
1632 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1631 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1633 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1632 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
@@ -1729,7 +1728,7 @@ static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1729 /* Hard reset */ 1728 /* Hard reset */
1730 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1729 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1731 MISC_REGISTERS_RESET_REG_2_XMAC); 1730 MISC_REGISTERS_RESET_REG_2_XMAC);
1732 usleep_range(1000, 1000); 1731 usleep_range(1000, 2000);
1733 1732
1734 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1733 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1735 MISC_REGISTERS_RESET_REG_2_XMAC); 1734 MISC_REGISTERS_RESET_REG_2_XMAC);
@@ -1759,7 +1758,7 @@ static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1759 /* Soft reset */ 1758 /* Soft reset */
1760 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1759 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1761 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1760 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1762 usleep_range(1000, 1000); 1761 usleep_range(1000, 2000);
1763 1762
1764 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1763 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1765 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1764 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
@@ -1880,11 +1879,6 @@ static int bnx2x_emac_enable(struct link_params *params,
1880 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1879 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1881 EMAC_TX_MODE_RESET); 1880 EMAC_TX_MODE_RESET);
1882 1881
1883 if (CHIP_REV_IS_SLOW(bp)) {
1884 /* config GMII mode */
1885 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1886 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1887 } else { /* ASIC */
1888 /* pause enable/disable */ 1882 /* pause enable/disable */
1889 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1883 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1890 EMAC_RX_MODE_FLOW_EN); 1884 EMAC_RX_MODE_FLOW_EN);
@@ -1907,7 +1901,6 @@ static int bnx2x_emac_enable(struct link_params *params,
1907 } else 1901 } else
1908 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1902 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1909 EMAC_TX_MODE_FLOW_EN); 1903 EMAC_TX_MODE_FLOW_EN);
1910 }
1911 1904
1912 /* KEEP_VLAN_TAG, promiscuous */ 1905 /* KEEP_VLAN_TAG, promiscuous */
1913 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); 1906 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
@@ -1946,23 +1939,23 @@ static int bnx2x_emac_enable(struct link_params *params,
1946 val &= ~0x810; 1939 val &= ~0x810;
1947 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); 1940 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1948 1941
1949 /* enable emac */ 1942 /* Enable emac */
1950 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); 1943 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1951 1944
1952 /* enable emac for jumbo packets */ 1945 /* Enable emac for jumbo packets */
1953 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, 1946 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1954 (EMAC_RX_MTU_SIZE_JUMBO_ENA | 1947 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1955 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); 1948 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1956 1949
1957 /* strip CRC */ 1950 /* Strip CRC */
1958 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); 1951 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1959 1952
1960 /* disable the NIG in/out to the bmac */ 1953 /* Disable the NIG in/out to the bmac */
1961 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); 1954 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1962 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); 1955 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1963 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); 1956 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1964 1957
1965 /* enable the NIG in/out to the emac */ 1958 /* Enable the NIG in/out to the emac */
1966 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); 1959 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1967 val = 0; 1960 val = 0;
1968 if ((params->feature_config_flags & 1961 if ((params->feature_config_flags &
@@ -1997,7 +1990,7 @@ static void bnx2x_update_pfc_bmac1(struct link_params *params,
1997 wb_data[1] = 0; 1990 wb_data[1] = 0;
1998 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); 1991 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1999 1992
2000 /* tx control */ 1993 /* TX control */
2001 val = 0xc0; 1994 val = 0xc0;
2002 if (!(params->feature_config_flags & 1995 if (!(params->feature_config_flags &
2003 FEATURE_CONFIG_PFC_ENABLED) && 1996 FEATURE_CONFIG_PFC_ENABLED) &&
@@ -2057,7 +2050,7 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
2057 wb_data[0] &= ~(1<<2); 2050 wb_data[0] &= ~(1<<2);
2058 } else { 2051 } else {
2059 DP(NETIF_MSG_LINK, "PFC is disabled\n"); 2052 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2060 /* disable PFC RX & TX & STATS and set 8 COS */ 2053 /* Disable PFC RX & TX & STATS and set 8 COS */
2061 wb_data[0] = 0x8; 2054 wb_data[0] = 0x8;
2062 wb_data[1] = 0; 2055 wb_data[1] = 0;
2063 } 2056 }
@@ -2151,7 +2144,7 @@ static int bnx2x_pfc_brb_get_config_params(
2151 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE; 2144 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2152 config_val->pauseable_th.full_xon = 2145 config_val->pauseable_th.full_xon =
2153 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE; 2146 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2154 /* non pause able*/ 2147 /* Non pause able*/
2155 config_val->non_pauseable_th.pause_xoff = 2148 config_val->non_pauseable_th.pause_xoff =
2156 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; 2149 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2157 config_val->non_pauseable_th.pause_xon = 2150 config_val->non_pauseable_th.pause_xon =
@@ -2179,7 +2172,7 @@ static int bnx2x_pfc_brb_get_config_params(
2179 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE; 2172 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2180 config_val->pauseable_th.full_xon = 2173 config_val->pauseable_th.full_xon =
2181 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE; 2174 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2182 /* non pause able*/ 2175 /* Non pause able*/
2183 config_val->non_pauseable_th.pause_xoff = 2176 config_val->non_pauseable_th.pause_xoff =
2184 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; 2177 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2185 config_val->non_pauseable_th.pause_xon = 2178 config_val->non_pauseable_th.pause_xon =
@@ -2209,7 +2202,7 @@ static int bnx2x_pfc_brb_get_config_params(
2209 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE; 2202 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2210 config_val->pauseable_th.full_xon = 2203 config_val->pauseable_th.full_xon =
2211 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE; 2204 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2212 /* non pause able*/ 2205 /* Non pause able*/
2213 config_val->non_pauseable_th.pause_xoff = 2206 config_val->non_pauseable_th.pause_xoff =
2214 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; 2207 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2215 config_val->non_pauseable_th.pause_xon = 2208 config_val->non_pauseable_th.pause_xon =
@@ -2227,7 +2220,7 @@ static int bnx2x_pfc_brb_get_config_params(
2227 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE; 2220 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2228 config_val->pauseable_th.full_xon = 2221 config_val->pauseable_th.full_xon =
2229 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE; 2222 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2230 /* non pause able*/ 2223 /* Non pause able*/
2231 config_val->non_pauseable_th.pause_xoff = 2224 config_val->non_pauseable_th.pause_xoff =
2232 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; 2225 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2233 config_val->non_pauseable_th.pause_xon = 2226 config_val->non_pauseable_th.pause_xon =
@@ -2284,7 +2277,7 @@ static void bnx2x_pfc_brb_get_e3b0_config_params(
2284 2277
2285 if (pfc_params->cos0_pauseable != 2278 if (pfc_params->cos0_pauseable !=
2286 pfc_params->cos1_pauseable) { 2279 pfc_params->cos1_pauseable) {
2287 /* nonpauseable= Lossy + pauseable = Lossless*/ 2280 /* Nonpauseable= Lossy + pauseable = Lossless*/
2288 e3b0_val->lb_guarantied = 2281 e3b0_val->lb_guarantied =
2289 PFC_E3B0_2P_MIX_PAUSE_LB_GUART; 2282 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2290 e3b0_val->mac_0_class_t_guarantied = 2283 e3b0_val->mac_0_class_t_guarantied =
@@ -2483,9 +2476,9 @@ static int bnx2x_update_pfc_brb(struct link_params *params,
2483* This function is needed because NIG ARB_CREDIT_WEIGHT_X are 2476* This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2484* not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 2477* not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2485******************************************************************************/ 2478******************************************************************************/
2486int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, 2479static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2487 u8 cos_entry, 2480 u8 cos_entry,
2488 u32 priority_mask, u8 port) 2481 u32 priority_mask, u8 port)
2489{ 2482{
2490 u32 nig_reg_rx_priority_mask_add = 0; 2483 u32 nig_reg_rx_priority_mask_add = 0;
2491 2484
@@ -2612,7 +2605,7 @@ static void bnx2x_update_pfc_nig(struct link_params *params,
2612 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : 2605 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2613 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); 2606 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2614 2607
2615 /* output enable for RX_XCM # IF */ 2608 /* Output enable for RX_XCM # IF */
2616 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : 2609 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2617 NIG_REG_XCM0_OUT_EN, xcm_out_en); 2610 NIG_REG_XCM0_OUT_EN, xcm_out_en);
2618 2611
@@ -2661,10 +2654,10 @@ int bnx2x_update_pfc(struct link_params *params,
2661 2654
2662 bnx2x_update_mng(params, vars->link_status); 2655 bnx2x_update_mng(params, vars->link_status);
2663 2656
2664 /* update NIG params */ 2657 /* Update NIG params */
2665 bnx2x_update_pfc_nig(params, vars, pfc_params); 2658 bnx2x_update_pfc_nig(params, vars, pfc_params);
2666 2659
2667 /* update BRB params */ 2660 /* Update BRB params */
2668 bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params); 2661 bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2669 if (bnx2x_status) 2662 if (bnx2x_status)
2670 return bnx2x_status; 2663 return bnx2x_status;
@@ -2719,7 +2712,7 @@ static int bnx2x_bmac1_enable(struct link_params *params,
2719 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, 2712 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2720 wb_data, 2); 2713 wb_data, 2);
2721 2714
2722 /* tx MAC SA */ 2715 /* TX MAC SA */
2723 wb_data[0] = ((params->mac_addr[2] << 24) | 2716 wb_data[0] = ((params->mac_addr[2] << 24) |
2724 (params->mac_addr[3] << 16) | 2717 (params->mac_addr[3] << 16) |
2725 (params->mac_addr[4] << 8) | 2718 (params->mac_addr[4] << 8) |
@@ -2728,7 +2721,7 @@ static int bnx2x_bmac1_enable(struct link_params *params,
2728 params->mac_addr[1]); 2721 params->mac_addr[1]);
2729 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); 2722 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2730 2723
2731 /* mac control */ 2724 /* MAC control */
2732 val = 0x3; 2725 val = 0x3;
2733 if (is_lb) { 2726 if (is_lb) {
2734 val |= 0x4; 2727 val |= 0x4;
@@ -2738,24 +2731,24 @@ static int bnx2x_bmac1_enable(struct link_params *params,
2738 wb_data[1] = 0; 2731 wb_data[1] = 0;
2739 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); 2732 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2740 2733
2741 /* set rx mtu */ 2734 /* Set rx mtu */
2742 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2735 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2743 wb_data[1] = 0; 2736 wb_data[1] = 0;
2744 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); 2737 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2745 2738
2746 bnx2x_update_pfc_bmac1(params, vars); 2739 bnx2x_update_pfc_bmac1(params, vars);
2747 2740
2748 /* set tx mtu */ 2741 /* Set tx mtu */
2749 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2742 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2750 wb_data[1] = 0; 2743 wb_data[1] = 0;
2751 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); 2744 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2752 2745
2753 /* set cnt max size */ 2746 /* Set cnt max size */
2754 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2747 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2755 wb_data[1] = 0; 2748 wb_data[1] = 0;
2756 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2749 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2757 2750
2758 /* configure safc */ 2751 /* Configure SAFC */
2759 wb_data[0] = 0x1000200; 2752 wb_data[0] = 0x1000200;
2760 wb_data[1] = 0; 2753 wb_data[1] = 0;
2761 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, 2754 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
@@ -2789,7 +2782,7 @@ static int bnx2x_bmac2_enable(struct link_params *params,
2789 2782
2790 udelay(30); 2783 udelay(30);
2791 2784
2792 /* tx MAC SA */ 2785 /* TX MAC SA */
2793 wb_data[0] = ((params->mac_addr[2] << 24) | 2786 wb_data[0] = ((params->mac_addr[2] << 24) |
2794 (params->mac_addr[3] << 16) | 2787 (params->mac_addr[3] << 16) |
2795 (params->mac_addr[4] << 8) | 2788 (params->mac_addr[4] << 8) |
@@ -2808,18 +2801,18 @@ static int bnx2x_bmac2_enable(struct link_params *params,
2808 wb_data, 2); 2801 wb_data, 2);
2809 udelay(30); 2802 udelay(30);
2810 2803
2811 /* set rx mtu */ 2804 /* Set RX MTU */
2812 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2805 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2813 wb_data[1] = 0; 2806 wb_data[1] = 0;
2814 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); 2807 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2815 udelay(30); 2808 udelay(30);
2816 2809
2817 /* set tx mtu */ 2810 /* Set TX MTU */
2818 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2811 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2819 wb_data[1] = 0; 2812 wb_data[1] = 0;
2820 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); 2813 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2821 udelay(30); 2814 udelay(30);
2822 /* set cnt max size */ 2815 /* Set cnt max size */
2823 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; 2816 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2824 wb_data[1] = 0; 2817 wb_data[1] = 0;
2825 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2818 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
@@ -2837,15 +2830,15 @@ static int bnx2x_bmac_enable(struct link_params *params,
2837 u8 port = params->port; 2830 u8 port = params->port;
2838 struct bnx2x *bp = params->bp; 2831 struct bnx2x *bp = params->bp;
2839 u32 val; 2832 u32 val;
2840 /* reset and unreset the BigMac */ 2833 /* Reset and unreset the BigMac */
2841 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2834 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2842 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2835 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2843 msleep(1); 2836 usleep_range(1000, 2000);
2844 2837
2845 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2838 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2846 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2839 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2847 2840
2848 /* enable access for bmac registers */ 2841 /* Enable access for bmac registers */
2849 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2842 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2850 2843
2851 /* Enable BMAC according to BMAC type*/ 2844 /* Enable BMAC according to BMAC type*/
@@ -2903,7 +2896,7 @@ static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2903 BIGMAC_REGISTER_BMAC_CONTROL, 2896 BIGMAC_REGISTER_BMAC_CONTROL,
2904 wb_data, 2); 2897 wb_data, 2);
2905 } 2898 }
2906 msleep(1); 2899 usleep_range(1000, 2000);
2907 } 2900 }
2908} 2901}
2909 2902
@@ -2915,17 +2908,16 @@ static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2915 u32 init_crd, crd; 2908 u32 init_crd, crd;
2916 u32 count = 1000; 2909 u32 count = 1000;
2917 2910
2918 /* disable port */ 2911 /* Disable port */
2919 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 2912 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2920 2913
2921 /* wait for init credit */ 2914 /* Wait for init credit */
2922 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); 2915 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2923 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2916 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2924 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); 2917 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2925 2918
2926 while ((init_crd != crd) && count) { 2919 while ((init_crd != crd) && count) {
2927 msleep(5); 2920 usleep_range(5000, 10000);
2928
2929 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2921 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2930 count--; 2922 count--;
2931 } 2923 }
@@ -2942,18 +2934,18 @@ static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2942 line_speed == SPEED_1000 || 2934 line_speed == SPEED_1000 ||
2943 line_speed == SPEED_2500) { 2935 line_speed == SPEED_2500) {
2944 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); 2936 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2945 /* update threshold */ 2937 /* Update threshold */
2946 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); 2938 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2947 /* update init credit */ 2939 /* Update init credit */
2948 init_crd = 778; /* (800-18-4) */ 2940 init_crd = 778; /* (800-18-4) */
2949 2941
2950 } else { 2942 } else {
2951 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + 2943 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2952 ETH_OVREHEAD)/16; 2944 ETH_OVREHEAD)/16;
2953 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 2945 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2954 /* update threshold */ 2946 /* Update threshold */
2955 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); 2947 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2956 /* update init credit */ 2948 /* Update init credit */
2957 switch (line_speed) { 2949 switch (line_speed) {
2958 case SPEED_10000: 2950 case SPEED_10000:
2959 init_crd = thresh + 553 - 22; 2951 init_crd = thresh + 553 - 22;
@@ -2968,12 +2960,12 @@ static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2968 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", 2960 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2969 line_speed, init_crd); 2961 line_speed, init_crd);
2970 2962
2971 /* probe the credit changes */ 2963 /* Probe the credit changes */
2972 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); 2964 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2973 msleep(5); 2965 usleep_range(5000, 10000);
2974 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); 2966 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2975 2967
2976 /* enable port */ 2968 /* Enable port */
2977 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); 2969 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2978 return 0; 2970 return 0;
2979} 2971}
@@ -3040,7 +3032,7 @@ static int bnx2x_cl22_write(struct bnx2x *bp,
3040 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 3032 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3041 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 3033 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3042 3034
3043 /* address */ 3035 /* Address */
3044 tmp = ((phy->addr << 21) | (reg << 16) | val | 3036 tmp = ((phy->addr << 21) | (reg << 16) | val |
3045 EMAC_MDIO_COMM_COMMAND_WRITE_22 | 3037 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3046 EMAC_MDIO_COMM_START_BUSY); 3038 EMAC_MDIO_COMM_START_BUSY);
@@ -3076,7 +3068,7 @@ static int bnx2x_cl22_read(struct bnx2x *bp,
3076 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 3068 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3077 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 3069 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3078 3070
3079 /* address */ 3071 /* Address */
3080 val = ((phy->addr << 21) | (reg << 16) | 3072 val = ((phy->addr << 21) | (reg << 16) |
3081 EMAC_MDIO_COMM_COMMAND_READ_22 | 3073 EMAC_MDIO_COMM_COMMAND_READ_22 |
3082 EMAC_MDIO_COMM_START_BUSY); 3074 EMAC_MDIO_COMM_START_BUSY);
@@ -3114,7 +3106,7 @@ static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
3114 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 3106 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3115 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 3107 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3116 EMAC_MDIO_STATUS_10MB); 3108 EMAC_MDIO_STATUS_10MB);
3117 /* address */ 3109 /* Address */
3118 val = ((phy->addr << 21) | (devad << 16) | reg | 3110 val = ((phy->addr << 21) | (devad << 16) | reg |
3119 EMAC_MDIO_COMM_COMMAND_ADDRESS | 3111 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3120 EMAC_MDIO_COMM_START_BUSY); 3112 EMAC_MDIO_COMM_START_BUSY);
@@ -3135,7 +3127,7 @@ static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
3135 *ret_val = 0; 3127 *ret_val = 0;
3136 rc = -EFAULT; 3128 rc = -EFAULT;
3137 } else { 3129 } else {
3138 /* data */ 3130 /* Data */
3139 val = ((phy->addr << 21) | (devad << 16) | 3131 val = ((phy->addr << 21) | (devad << 16) |
3140 EMAC_MDIO_COMM_COMMAND_READ_45 | 3132 EMAC_MDIO_COMM_COMMAND_READ_45 |
3141 EMAC_MDIO_COMM_START_BUSY); 3133 EMAC_MDIO_COMM_START_BUSY);
@@ -3183,7 +3175,7 @@ static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3183 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 3175 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3184 EMAC_MDIO_STATUS_10MB); 3176 EMAC_MDIO_STATUS_10MB);
3185 3177
3186 /* address */ 3178 /* Address */
3187 tmp = ((phy->addr << 21) | (devad << 16) | reg | 3179 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3188 EMAC_MDIO_COMM_COMMAND_ADDRESS | 3180 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3189 EMAC_MDIO_COMM_START_BUSY); 3181 EMAC_MDIO_COMM_START_BUSY);
@@ -3203,7 +3195,7 @@ static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3203 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 3195 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3204 rc = -EFAULT; 3196 rc = -EFAULT;
3205 } else { 3197 } else {
3206 /* data */ 3198 /* Data */
3207 tmp = ((phy->addr << 21) | (devad << 16) | val | 3199 tmp = ((phy->addr << 21) | (devad << 16) | val |
3208 EMAC_MDIO_COMM_COMMAND_WRITE_45 | 3200 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3209 EMAC_MDIO_COMM_START_BUSY); 3201 EMAC_MDIO_COMM_START_BUSY);
@@ -3293,23 +3285,23 @@ static int bnx2x_bsc_read(struct link_params *params,
3293 3285
3294 xfer_cnt = 16 - lc_addr; 3286 xfer_cnt = 16 - lc_addr;
3295 3287
3296 /* enable the engine */ 3288 /* Enable the engine */
3297 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3289 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3298 val |= MCPR_IMC_COMMAND_ENABLE; 3290 val |= MCPR_IMC_COMMAND_ENABLE;
3299 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3291 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3300 3292
3301 /* program slave device ID */ 3293 /* Program slave device ID */
3302 val = (sl_devid << 16) | sl_addr; 3294 val = (sl_devid << 16) | sl_addr;
3303 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); 3295 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3304 3296
3305 /* start xfer with 0 byte to update the address pointer ???*/ 3297 /* Start xfer with 0 byte to update the address pointer ???*/
3306 val = (MCPR_IMC_COMMAND_ENABLE) | 3298 val = (MCPR_IMC_COMMAND_ENABLE) |
3307 (MCPR_IMC_COMMAND_WRITE_OP << 3299 (MCPR_IMC_COMMAND_WRITE_OP <<
3308 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3300 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3309 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); 3301 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3310 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3302 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3311 3303
3312 /* poll for completion */ 3304 /* Poll for completion */
3313 i = 0; 3305 i = 0;
3314 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3306 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3315 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3307 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
@@ -3325,7 +3317,7 @@ static int bnx2x_bsc_read(struct link_params *params,
3325 if (rc == -EFAULT) 3317 if (rc == -EFAULT)
3326 return rc; 3318 return rc;
3327 3319
3328 /* start xfer with read op */ 3320 /* Start xfer with read op */
3329 val = (MCPR_IMC_COMMAND_ENABLE) | 3321 val = (MCPR_IMC_COMMAND_ENABLE) |
3330 (MCPR_IMC_COMMAND_READ_OP << 3322 (MCPR_IMC_COMMAND_READ_OP <<
3331 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3323 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
@@ -3333,7 +3325,7 @@ static int bnx2x_bsc_read(struct link_params *params,
3333 (xfer_cnt); 3325 (xfer_cnt);
3334 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3326 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3335 3327
3336 /* poll for completion */ 3328 /* Poll for completion */
3337 i = 0; 3329 i = 0;
3338 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3330 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3339 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3331 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
@@ -3436,7 +3428,7 @@ static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3436 port = port ^ 1; 3428 port = port ^ 1;
3437 3429
3438 lane = (port<<1) + path; 3430 lane = (port<<1) + path;
3439 } else { /* two port mode - no port swap */ 3431 } else { /* Two port mode - no port swap */
3440 3432
3441 /* Figure out path swap value */ 3433 /* Figure out path swap value */
3442 path_swap_ovr = 3434 path_swap_ovr =
@@ -3514,7 +3506,7 @@ static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3514 3506
3515 val = SERDES_RESET_BITS << (port*16); 3507 val = SERDES_RESET_BITS << (port*16);
3516 3508
3517 /* reset and unreset the SerDes/XGXS */ 3509 /* Reset and unreset the SerDes/XGXS */
3518 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3510 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3519 udelay(500); 3511 udelay(500);
3520 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3512 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
@@ -3535,7 +3527,7 @@ static void bnx2x_xgxs_deassert(struct link_params *params)
3535 3527
3536 val = XGXS_RESET_BITS << (port*16); 3528 val = XGXS_RESET_BITS << (port*16);
3537 3529
3538 /* reset and unreset the SerDes/XGXS */ 3530 /* Reset and unreset the SerDes/XGXS */
3539 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3531 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3540 udelay(500); 3532 udelay(500);
3541 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3533 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
@@ -3627,7 +3619,7 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params,
3627{ 3619{
3628 u16 val; 3620 u16 val;
3629 struct bnx2x *bp = params->bp; 3621 struct bnx2x *bp = params->bp;
3630 /* read modify write pause advertizing */ 3622 /* Read modify write pause advertizing */
3631 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); 3623 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3632 3624
3633 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 3625 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
@@ -3945,7 +3937,7 @@ static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3945 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3937 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3946 MDIO_WC_REG_RX66_CONTROL, 0xF9); 3938 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3947 3939
3948 /* set and clear loopback to cause a reset to 64/66 decoder */ 3940 /* Set and clear loopback to cause a reset to 64/66 decoder */
3949 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3941 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3950 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); 3942 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3951 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3943 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
@@ -4373,7 +4365,7 @@ static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4373 if (!vars->turn_to_run_wc_rt) 4365 if (!vars->turn_to_run_wc_rt)
4374 return; 4366 return;
4375 4367
4376 /* return if there is no link partner */ 4368 /* Return if there is no link partner */
4377 if (!(bnx2x_warpcore_get_sigdet(phy, params))) { 4369 if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4378 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n"); 4370 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4379 return; 4371 return;
@@ -4407,7 +4399,7 @@ static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4407 bnx2x_warpcore_reset_lane(bp, phy, 1); 4399 bnx2x_warpcore_reset_lane(bp, phy, 1);
4408 bnx2x_warpcore_reset_lane(bp, phy, 0); 4400 bnx2x_warpcore_reset_lane(bp, phy, 0);
4409 4401
4410 /* restart Autoneg */ 4402 /* Restart Autoneg */
4411 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 4403 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4412 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4404 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4413 4405
@@ -4645,8 +4637,9 @@ static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4645} 4637}
4646 4638
4647 4639
4648void bnx2x_sync_link(struct link_params *params, 4640
4649 struct link_vars *vars) 4641static void bnx2x_sync_link(struct link_params *params,
4642 struct link_vars *vars)
4650{ 4643{
4651 struct bnx2x *bp = params->bp; 4644 struct bnx2x *bp = params->bp;
4652 u8 link_10g_plus; 4645 u8 link_10g_plus;
@@ -4719,7 +4712,7 @@ void bnx2x_sync_link(struct link_params *params,
4719 USES_WARPCORE(bp) && 4712 USES_WARPCORE(bp) &&
4720 (vars->line_speed == SPEED_1000)) 4713 (vars->line_speed == SPEED_1000))
4721 vars->phy_flags |= PHY_SGMII_FLAG; 4714 vars->phy_flags |= PHY_SGMII_FLAG;
4722 /* anything 10 and over uses the bmac */ 4715 /* Anything 10 and over uses the bmac */
4723 link_10g_plus = (vars->line_speed >= SPEED_10000); 4716 link_10g_plus = (vars->line_speed >= SPEED_10000);
4724 4717
4725 if (link_10g_plus) { 4718 if (link_10g_plus) {
@@ -4733,7 +4726,7 @@ void bnx2x_sync_link(struct link_params *params,
4733 else 4726 else
4734 vars->mac_type = MAC_TYPE_EMAC; 4727 vars->mac_type = MAC_TYPE_EMAC;
4735 } 4728 }
4736 } else { /* link down */ 4729 } else { /* Link down */
4737 DP(NETIF_MSG_LINK, "phy link down\n"); 4730 DP(NETIF_MSG_LINK, "phy link down\n");
4738 4731
4739 vars->phy_link_up = 0; 4732 vars->phy_link_up = 0;
@@ -4742,7 +4735,7 @@ void bnx2x_sync_link(struct link_params *params,
4742 vars->duplex = DUPLEX_FULL; 4735 vars->duplex = DUPLEX_FULL;
4743 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4736 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4744 4737
4745 /* indicate no mac active */ 4738 /* Indicate no mac active */
4746 vars->mac_type = MAC_TYPE_NONE; 4739 vars->mac_type = MAC_TYPE_NONE;
4747 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4740 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4748 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 4741 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
@@ -4813,7 +4806,7 @@ static void bnx2x_set_master_ln(struct link_params *params,
4813 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 4806 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4814 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 4807 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4815 4808
4816 /* set the master_ln for AN */ 4809 /* Set the master_ln for AN */
4817 CL22_RD_OVER_CL45(bp, phy, 4810 CL22_RD_OVER_CL45(bp, phy,
4818 MDIO_REG_BANK_XGXS_BLOCK2, 4811 MDIO_REG_BANK_XGXS_BLOCK2,
4819 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4812 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
@@ -4836,7 +4829,7 @@ static int bnx2x_reset_unicore(struct link_params *params,
4836 MDIO_REG_BANK_COMBO_IEEE0, 4829 MDIO_REG_BANK_COMBO_IEEE0,
4837 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); 4830 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4838 4831
4839 /* reset the unicore */ 4832 /* Reset the unicore */
4840 CL22_WR_OVER_CL45(bp, phy, 4833 CL22_WR_OVER_CL45(bp, phy,
4841 MDIO_REG_BANK_COMBO_IEEE0, 4834 MDIO_REG_BANK_COMBO_IEEE0,
4842 MDIO_COMBO_IEEE0_MII_CONTROL, 4835 MDIO_COMBO_IEEE0_MII_CONTROL,
@@ -4845,11 +4838,11 @@ static int bnx2x_reset_unicore(struct link_params *params,
4845 if (set_serdes) 4838 if (set_serdes)
4846 bnx2x_set_serdes_access(bp, params->port); 4839 bnx2x_set_serdes_access(bp, params->port);
4847 4840
4848 /* wait for the reset to self clear */ 4841 /* Wait for the reset to self clear */
4849 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { 4842 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4850 udelay(5); 4843 udelay(5);
4851 4844
4852 /* the reset erased the previous bank value */ 4845 /* The reset erased the previous bank value */
4853 CL22_RD_OVER_CL45(bp, phy, 4846 CL22_RD_OVER_CL45(bp, phy,
4854 MDIO_REG_BANK_COMBO_IEEE0, 4847 MDIO_REG_BANK_COMBO_IEEE0,
4855 MDIO_COMBO_IEEE0_MII_CONTROL, 4848 MDIO_COMBO_IEEE0_MII_CONTROL,
@@ -5067,7 +5060,7 @@ static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
5067 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); 5060 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5068} 5061}
5069 5062
5070/* program SerDes, forced speed */ 5063/* Program SerDes, forced speed */
5071static void bnx2x_program_serdes(struct bnx2x_phy *phy, 5064static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5072 struct link_params *params, 5065 struct link_params *params,
5073 struct link_vars *vars) 5066 struct link_vars *vars)
@@ -5075,7 +5068,7 @@ static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5075 struct bnx2x *bp = params->bp; 5068 struct bnx2x *bp = params->bp;
5076 u16 reg_val; 5069 u16 reg_val;
5077 5070
5078 /* program duplex, disable autoneg and sgmii*/ 5071 /* Program duplex, disable autoneg and sgmii*/
5079 CL22_RD_OVER_CL45(bp, phy, 5072 CL22_RD_OVER_CL45(bp, phy,
5080 MDIO_REG_BANK_COMBO_IEEE0, 5073 MDIO_REG_BANK_COMBO_IEEE0,
5081 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val); 5074 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
@@ -5094,7 +5087,7 @@ static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5094 CL22_RD_OVER_CL45(bp, phy, 5087 CL22_RD_OVER_CL45(bp, phy,
5095 MDIO_REG_BANK_SERDES_DIGITAL, 5088 MDIO_REG_BANK_SERDES_DIGITAL,
5096 MDIO_SERDES_DIGITAL_MISC1, &reg_val); 5089 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5097 /* clearing the speed value before setting the right speed */ 5090 /* Clearing the speed value before setting the right speed */
5098 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); 5091 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5099 5092
5100 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | 5093 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
@@ -5123,7 +5116,7 @@ static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5123 struct bnx2x *bp = params->bp; 5116 struct bnx2x *bp = params->bp;
5124 u16 val = 0; 5117 u16 val = 0;
5125 5118
5126 /* set extended capabilities */ 5119 /* Set extended capabilities */
5127 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 5120 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5128 val |= MDIO_OVER_1G_UP1_2_5G; 5121 val |= MDIO_OVER_1G_UP1_2_5G;
5129 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5122 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
@@ -5143,7 +5136,7 @@ static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5143{ 5136{
5144 struct bnx2x *bp = params->bp; 5137 struct bnx2x *bp = params->bp;
5145 u16 val; 5138 u16 val;
5146 /* for AN, we are always publishing full duplex */ 5139 /* For AN, we are always publishing full duplex */
5147 5140
5148 CL22_WR_OVER_CL45(bp, phy, 5141 CL22_WR_OVER_CL45(bp, phy,
5149 MDIO_REG_BANK_COMBO_IEEE0, 5142 MDIO_REG_BANK_COMBO_IEEE0,
@@ -5205,14 +5198,14 @@ static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5205 struct bnx2x *bp = params->bp; 5198 struct bnx2x *bp = params->bp;
5206 u16 control1; 5199 u16 control1;
5207 5200
5208 /* in SGMII mode, the unicore is always slave */ 5201 /* In SGMII mode, the unicore is always slave */
5209 5202
5210 CL22_RD_OVER_CL45(bp, phy, 5203 CL22_RD_OVER_CL45(bp, phy,
5211 MDIO_REG_BANK_SERDES_DIGITAL, 5204 MDIO_REG_BANK_SERDES_DIGITAL,
5212 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5205 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5213 &control1); 5206 &control1);
5214 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; 5207 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5215 /* set sgmii mode (and not fiber) */ 5208 /* Set sgmii mode (and not fiber) */
5216 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | 5209 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5217 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | 5210 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5218 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); 5211 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
@@ -5221,9 +5214,9 @@ static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5221 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5214 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5222 control1); 5215 control1);
5223 5216
5224 /* if forced speed */ 5217 /* If forced speed */
5225 if (!(vars->line_speed == SPEED_AUTO_NEG)) { 5218 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5226 /* set speed, disable autoneg */ 5219 /* Set speed, disable autoneg */
5227 u16 mii_control; 5220 u16 mii_control;
5228 5221
5229 CL22_RD_OVER_CL45(bp, phy, 5222 CL22_RD_OVER_CL45(bp, phy,
@@ -5244,16 +5237,16 @@ static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5244 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; 5237 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5245 break; 5238 break;
5246 case SPEED_10: 5239 case SPEED_10:
5247 /* there is nothing to set for 10M */ 5240 /* There is nothing to set for 10M */
5248 break; 5241 break;
5249 default: 5242 default:
5250 /* invalid speed for SGMII */ 5243 /* Invalid speed for SGMII */
5251 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5244 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5252 vars->line_speed); 5245 vars->line_speed);
5253 break; 5246 break;
5254 } 5247 }
5255 5248
5256 /* setting the full duplex */ 5249 /* Setting the full duplex */
5257 if (phy->req_duplex == DUPLEX_FULL) 5250 if (phy->req_duplex == DUPLEX_FULL)
5258 mii_control |= 5251 mii_control |=
5259 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5252 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
@@ -5263,7 +5256,7 @@ static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5263 mii_control); 5256 mii_control);
5264 5257
5265 } else { /* AN mode */ 5258 } else { /* AN mode */
5266 /* enable and restart AN */ 5259 /* Enable and restart AN */
5267 bnx2x_restart_autoneg(phy, params, 0); 5260 bnx2x_restart_autoneg(phy, params, 0);
5268 } 5261 }
5269} 5262}
@@ -5359,7 +5352,7 @@ static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5359 struct bnx2x *bp = params->bp; 5352 struct bnx2x *bp = params->bp;
5360 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5353 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5361 5354
5362 /* resolve from gp_status in case of AN complete and not sgmii */ 5355 /* Resolve from gp_status in case of AN complete and not sgmii */
5363 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 5356 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5364 /* Update the advertised flow-controled of LD/LP in AN */ 5357 /* Update the advertised flow-controled of LD/LP in AN */
5365 if (phy->req_line_speed == SPEED_AUTO_NEG) 5358 if (phy->req_line_speed == SPEED_AUTO_NEG)
@@ -5583,7 +5576,7 @@ static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5583 bnx2x_xgxs_an_resolve(phy, params, vars, 5576 bnx2x_xgxs_an_resolve(phy, params, vars,
5584 gp_status); 5577 gp_status);
5585 } 5578 }
5586 } else { /* link_down */ 5579 } else { /* Link_down */
5587 if ((phy->req_line_speed == SPEED_AUTO_NEG) && 5580 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5588 SINGLE_MEDIA_DIRECT(params)) { 5581 SINGLE_MEDIA_DIRECT(params)) {
5589 /* Check signal is detected */ 5582 /* Check signal is detected */
@@ -5732,12 +5725,12 @@ static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5732 u16 tx_driver; 5725 u16 tx_driver;
5733 u16 bank; 5726 u16 bank;
5734 5727
5735 /* read precomp */ 5728 /* Read precomp */
5736 CL22_RD_OVER_CL45(bp, phy, 5729 CL22_RD_OVER_CL45(bp, phy,
5737 MDIO_REG_BANK_OVER_1G, 5730 MDIO_REG_BANK_OVER_1G,
5738 MDIO_OVER_1G_LP_UP2, &lp_up2); 5731 MDIO_OVER_1G_LP_UP2, &lp_up2);
5739 5732
5740 /* bits [10:7] at lp_up2, positioned at [15:12] */ 5733 /* Bits [10:7] at lp_up2, positioned at [15:12] */
5741 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> 5734 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5742 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << 5735 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5743 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); 5736 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
@@ -5751,7 +5744,7 @@ static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5751 bank, 5744 bank,
5752 MDIO_TX0_TX_DRIVER, &tx_driver); 5745 MDIO_TX0_TX_DRIVER, &tx_driver);
5753 5746
5754 /* replace tx_driver bits [15:12] */ 5747 /* Replace tx_driver bits [15:12] */
5755 if (lp_up2 != 5748 if (lp_up2 !=
5756 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { 5749 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5757 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 5750 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
@@ -5847,16 +5840,16 @@ static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5847 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) 5840 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5848 bnx2x_set_preemphasis(phy, params); 5841 bnx2x_set_preemphasis(phy, params);
5849 5842
5850 /* forced speed requested? */ 5843 /* Forced speed requested? */
5851 if (vars->line_speed != SPEED_AUTO_NEG || 5844 if (vars->line_speed != SPEED_AUTO_NEG ||
5852 (SINGLE_MEDIA_DIRECT(params) && 5845 (SINGLE_MEDIA_DIRECT(params) &&
5853 params->loopback_mode == LOOPBACK_EXT)) { 5846 params->loopback_mode == LOOPBACK_EXT)) {
5854 DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); 5847 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5855 5848
5856 /* disable autoneg */ 5849 /* Disable autoneg */
5857 bnx2x_set_autoneg(phy, params, vars, 0); 5850 bnx2x_set_autoneg(phy, params, vars, 0);
5858 5851
5859 /* program speed and duplex */ 5852 /* Program speed and duplex */
5860 bnx2x_program_serdes(phy, params, vars); 5853 bnx2x_program_serdes(phy, params, vars);
5861 5854
5862 } else { /* AN_mode */ 5855 } else { /* AN_mode */
@@ -5865,14 +5858,14 @@ static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5865 /* AN enabled */ 5858 /* AN enabled */
5866 bnx2x_set_brcm_cl37_advertisement(phy, params); 5859 bnx2x_set_brcm_cl37_advertisement(phy, params);
5867 5860
5868 /* program duplex & pause advertisement (for aneg) */ 5861 /* Program duplex & pause advertisement (for aneg) */
5869 bnx2x_set_ieee_aneg_advertisement(phy, params, 5862 bnx2x_set_ieee_aneg_advertisement(phy, params,
5870 vars->ieee_fc); 5863 vars->ieee_fc);
5871 5864
5872 /* enable autoneg */ 5865 /* Enable autoneg */
5873 bnx2x_set_autoneg(phy, params, vars, enable_cl73); 5866 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5874 5867
5875 /* enable and restart AN */ 5868 /* Enable and restart AN */
5876 bnx2x_restart_autoneg(phy, params, enable_cl73); 5869 bnx2x_restart_autoneg(phy, params, enable_cl73);
5877 } 5870 }
5878 5871
@@ -5908,12 +5901,12 @@ static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5908 bnx2x_set_master_ln(params, phy); 5901 bnx2x_set_master_ln(params, phy);
5909 5902
5910 rc = bnx2x_reset_unicore(params, phy, 0); 5903 rc = bnx2x_reset_unicore(params, phy, 0);
5911 /* reset the SerDes and wait for reset bit return low */ 5904 /* Reset the SerDes and wait for reset bit return low */
5912 if (rc != 0) 5905 if (rc)
5913 return rc; 5906 return rc;
5914 5907
5915 bnx2x_set_aer_mmd(params, phy); 5908 bnx2x_set_aer_mmd(params, phy);
5916 /* setting the masterLn_def again after the reset */ 5909 /* Setting the masterLn_def again after the reset */
5917 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { 5910 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5918 bnx2x_set_master_ln(params, phy); 5911 bnx2x_set_master_ln(params, phy);
5919 bnx2x_set_swap_lanes(params, phy); 5912 bnx2x_set_swap_lanes(params, phy);
@@ -5938,7 +5931,7 @@ static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5938 MDIO_PMA_REG_CTRL, &ctrl); 5931 MDIO_PMA_REG_CTRL, &ctrl);
5939 if (!(ctrl & (1<<15))) 5932 if (!(ctrl & (1<<15)))
5940 break; 5933 break;
5941 msleep(1); 5934 usleep_range(1000, 2000);
5942 } 5935 }
5943 5936
5944 if (cnt == 1000) 5937 if (cnt == 1000)
@@ -6169,7 +6162,7 @@ static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6169 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); 6162 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6170 6163
6171 if (!CHIP_IS_E3(bp)) { 6164 if (!CHIP_IS_E3(bp)) {
6172 /* change the uni_phy_addr in the nig */ 6165 /* Change the uni_phy_addr in the nig */
6173 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + 6166 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6174 port*0x18)); 6167 port*0x18));
6175 6168
@@ -6189,11 +6182,11 @@ static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6189 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 6182 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6190 0x6041); 6183 0x6041);
6191 msleep(200); 6184 msleep(200);
6192 /* set aer mmd back */ 6185 /* Set aer mmd back */
6193 bnx2x_set_aer_mmd(params, phy); 6186 bnx2x_set_aer_mmd(params, phy);
6194 6187
6195 if (!CHIP_IS_E3(bp)) { 6188 if (!CHIP_IS_E3(bp)) {
6196 /* and md_devad */ 6189 /* And md_devad */
6197 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6190 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6198 md_devad); 6191 md_devad);
6199 } 6192 }
@@ -6390,7 +6383,7 @@ int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6390 MDIO_REG_BANK_GP_STATUS, 6383 MDIO_REG_BANK_GP_STATUS,
6391 MDIO_GP_STATUS_TOP_AN_STATUS1, 6384 MDIO_GP_STATUS_TOP_AN_STATUS1,
6392 &gp_status); 6385 &gp_status);
6393 /* link is up only if both local phy and external phy are up */ 6386 /* Link is up only if both local phy and external phy are up */
6394 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) 6387 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6395 return -ESRCH; 6388 return -ESRCH;
6396 } 6389 }
@@ -6512,7 +6505,7 @@ static int bnx2x_link_initialize(struct link_params *params,
6512static void bnx2x_int_link_reset(struct bnx2x_phy *phy, 6505static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6513 struct link_params *params) 6506 struct link_params *params)
6514{ 6507{
6515 /* reset the SerDes/XGXS */ 6508 /* Reset the SerDes/XGXS */
6516 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, 6509 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6517 (0x1ff << (params->port*16))); 6510 (0x1ff << (params->port*16)));
6518} 6511}
@@ -6545,10 +6538,10 @@ static int bnx2x_update_link_down(struct link_params *params,
6545 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); 6538 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6546 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 6539 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6547 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; 6540 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6548 /* indicate no mac active */ 6541 /* Indicate no mac active */
6549 vars->mac_type = MAC_TYPE_NONE; 6542 vars->mac_type = MAC_TYPE_NONE;
6550 6543
6551 /* update shared memory */ 6544 /* Update shared memory */
6552 vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK | 6545 vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6553 LINK_STATUS_LINK_UP | 6546 LINK_STATUS_LINK_UP |
6554 LINK_STATUS_PHYSICAL_LINK_FLAG | 6547 LINK_STATUS_PHYSICAL_LINK_FLAG |
@@ -6561,15 +6554,15 @@ static int bnx2x_update_link_down(struct link_params *params,
6561 vars->line_speed = 0; 6554 vars->line_speed = 0;
6562 bnx2x_update_mng(params, vars->link_status); 6555 bnx2x_update_mng(params, vars->link_status);
6563 6556
6564 /* activate nig drain */ 6557 /* Activate nig drain */
6565 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 6558 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6566 6559
6567 /* disable emac */ 6560 /* Disable emac */
6568 if (!CHIP_IS_E3(bp)) 6561 if (!CHIP_IS_E3(bp))
6569 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6562 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6570 6563
6571 msleep(10); 6564 usleep_range(10000, 20000);
6572 /* reset BigMac/Xmac */ 6565 /* Reset BigMac/Xmac */
6573 if (CHIP_IS_E1x(bp) || 6566 if (CHIP_IS_E1x(bp) ||
6574 CHIP_IS_E2(bp)) { 6567 CHIP_IS_E2(bp)) {
6575 bnx2x_bmac_rx_disable(bp, params->port); 6568 bnx2x_bmac_rx_disable(bp, params->port);
@@ -6578,6 +6571,7 @@ static int bnx2x_update_link_down(struct link_params *params,
6578 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 6571 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6579 } 6572 }
6580 if (CHIP_IS_E3(bp)) { 6573 if (CHIP_IS_E3(bp)) {
6574 /* Prevent LPI Generation by chip */
6581 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 6575 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6582 0); 6576 0);
6583 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 0); 6577 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 0);
@@ -6668,10 +6662,10 @@ static int bnx2x_update_link_up(struct link_params *params,
6668 rc |= bnx2x_pbf_update(params, vars->flow_ctrl, 6662 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6669 vars->line_speed); 6663 vars->line_speed);
6670 6664
6671 /* disable drain */ 6665 /* Disable drain */
6672 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); 6666 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6673 6667
6674 /* update shared memory */ 6668 /* Update shared memory */
6675 bnx2x_update_mng(params, vars->link_status); 6669 bnx2x_update_mng(params, vars->link_status);
6676 bnx2x_update_mng_eee(params, vars->eee_status); 6670 bnx2x_update_mng_eee(params, vars->eee_status);
6677 /* Check remote fault */ 6671 /* Check remote fault */
@@ -6739,7 +6733,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6739 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6733 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6740 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6734 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6741 6735
6742 /* disable emac */ 6736 /* Disable emac */
6743 if (!CHIP_IS_E3(bp)) 6737 if (!CHIP_IS_E3(bp))
6744 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6738 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6745 6739
@@ -6884,11 +6878,11 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6884 } else if (prev_line_speed != vars->line_speed) { 6878 } else if (prev_line_speed != vars->line_speed) {
6885 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 6879 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6886 0); 6880 0);
6887 msleep(1); 6881 usleep_range(1000, 2000);
6888 } 6882 }
6889 } 6883 }
6890 6884
6891 /* anything 10 and over uses the bmac */ 6885 /* Anything 10 and over uses the bmac */
6892 link_10g_plus = (vars->line_speed >= SPEED_10000); 6886 link_10g_plus = (vars->line_speed >= SPEED_10000);
6893 6887
6894 bnx2x_link_int_ack(params, vars, link_10g_plus); 6888 bnx2x_link_int_ack(params, vars, link_10g_plus);
@@ -6954,7 +6948,7 @@ void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6954{ 6948{
6955 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6949 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6956 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 6950 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6957 msleep(1); 6951 usleep_range(1000, 2000);
6958 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6952 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6959 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 6953 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6960} 6954}
@@ -7051,7 +7045,7 @@ static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7051 MDIO_PMA_REG_GEN_CTRL, 7045 MDIO_PMA_REG_GEN_CTRL,
7052 0x0001); 7046 0x0001);
7053 7047
7054 /* ucode reboot and rst */ 7048 /* Ucode reboot and rst */
7055 bnx2x_cl45_write(bp, phy, 7049 bnx2x_cl45_write(bp, phy,
7056 MDIO_PMA_DEVAD, 7050 MDIO_PMA_DEVAD,
7057 MDIO_PMA_REG_GEN_CTRL, 7051 MDIO_PMA_REG_GEN_CTRL,
@@ -7095,7 +7089,7 @@ static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7095 MDIO_PMA_DEVAD, 7089 MDIO_PMA_DEVAD,
7096 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); 7090 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7097 7091
7098 msleep(1); 7092 usleep_range(1000, 2000);
7099 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || 7093 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7100 ((fw_msgout & 0xff) != 0x03 && (phy->type == 7094 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7101 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); 7095 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
@@ -7189,11 +7183,11 @@ static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7189 "XAUI workaround has completed\n"); 7183 "XAUI workaround has completed\n");
7190 return 0; 7184 return 0;
7191 } 7185 }
7192 msleep(3); 7186 usleep_range(3000, 6000);
7193 } 7187 }
7194 break; 7188 break;
7195 } 7189 }
7196 msleep(3); 7190 usleep_range(3000, 6000);
7197 } 7191 }
7198 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); 7192 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7199 return -EINVAL; 7193 return -EINVAL;
@@ -7267,7 +7261,7 @@ static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7267 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7261 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7268 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7262 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7269 7263
7270 /* enable LASI */ 7264 /* Enable LASI */
7271 bnx2x_cl45_write(bp, phy, 7265 bnx2x_cl45_write(bp, phy,
7272 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); 7266 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7273 bnx2x_cl45_write(bp, phy, 7267 bnx2x_cl45_write(bp, phy,
@@ -7415,7 +7409,7 @@ static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7415 7409
7416 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); 7410 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7417 7411
7418 /* clear the interrupt LASI status register */ 7412 /* Clear the interrupt LASI status register */
7419 bnx2x_cl45_read(bp, phy, 7413 bnx2x_cl45_read(bp, phy,
7420 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7414 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7421 bnx2x_cl45_read(bp, phy, 7415 bnx2x_cl45_read(bp, phy,
@@ -7794,7 +7788,7 @@ static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7794 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7788 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7795 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 7789 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7796 return 0; 7790 return 0;
7797 msleep(1); 7791 usleep_range(1000, 2000);
7798 } 7792 }
7799 return -EINVAL; 7793 return -EINVAL;
7800} 7794}
@@ -7876,7 +7870,7 @@ static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7876 /* Wait appropriate time for two-wire command to finish before 7870 /* Wait appropriate time for two-wire command to finish before
7877 * polling the status register 7871 * polling the status register
7878 */ 7872 */
7879 msleep(1); 7873 usleep_range(1000, 2000);
7880 7874
7881 /* Wait up to 500us for command complete status */ 7875 /* Wait up to 500us for command complete status */
7882 for (i = 0; i < 100; i++) { 7876 for (i = 0; i < 100; i++) {
@@ -7912,7 +7906,7 @@ static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7912 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7906 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7913 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 7907 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7914 return 0; 7908 return 0;
7915 msleep(1); 7909 usleep_range(1000, 2000);
7916 } 7910 }
7917 7911
7918 return -EINVAL; 7912 return -EINVAL;
@@ -8091,7 +8085,7 @@ static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8091 return 0; 8085 return 0;
8092 } 8086 }
8093 8087
8094 /* format the warning message */ 8088 /* Format the warning message */
8095 if (bnx2x_read_sfp_module_eeprom(phy, 8089 if (bnx2x_read_sfp_module_eeprom(phy,
8096 params, 8090 params,
8097 SFP_EEPROM_VENDOR_NAME_ADDR, 8091 SFP_EEPROM_VENDOR_NAME_ADDR,
@@ -8137,7 +8131,7 @@ static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8137 timeout * 5); 8131 timeout * 5);
8138 return 0; 8132 return 0;
8139 } 8133 }
8140 msleep(5); 8134 usleep_range(5000, 10000);
8141 } 8135 }
8142 return -EINVAL; 8136 return -EINVAL;
8143} 8137}
@@ -8472,7 +8466,7 @@ int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8472 DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); 8466 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8473 return -EINVAL; 8467 return -EINVAL;
8474 } else if (bnx2x_verify_sfp_module(phy, params) != 0) { 8468 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8475 /* check SFP+ module compatibility */ 8469 /* Check SFP+ module compatibility */
8476 DP(NETIF_MSG_LINK, "Module verification failed!!\n"); 8470 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8477 rc = -EINVAL; 8471 rc = -EINVAL;
8478 /* Turn on fault module-detected led */ 8472 /* Turn on fault module-detected led */
@@ -8603,7 +8597,7 @@ static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8603 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 8597 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8604 MDIO_PMA_LASI_TXCTRL); 8598 MDIO_PMA_LASI_TXCTRL);
8605 8599
8606 /* clear LASI indication*/ 8600 /* Clear LASI indication*/
8607 bnx2x_cl45_read(bp, phy, 8601 bnx2x_cl45_read(bp, phy,
8608 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 8602 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8609 bnx2x_cl45_read(bp, phy, 8603 bnx2x_cl45_read(bp, phy,
@@ -8671,7 +8665,7 @@ static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8671 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); 8665 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8672 if (val) 8666 if (val)
8673 break; 8667 break;
8674 msleep(10); 8668 usleep_range(10000, 20000);
8675 } 8669 }
8676 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); 8670 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8677 if ((params->feature_config_flags & 8671 if ((params->feature_config_flags &
@@ -8800,7 +8794,7 @@ static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8800 MDIO_PMA_REG_GEN_CTRL, 8794 MDIO_PMA_REG_GEN_CTRL,
8801 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 8795 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8802 8796
8803 /* wait for 150ms for microcode load */ 8797 /* Wait for 150ms for microcode load */
8804 msleep(150); 8798 msleep(150);
8805 8799
8806 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ 8800 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
@@ -9011,7 +9005,7 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9011 lasi_ctrl_val = 0x0006; 9005 lasi_ctrl_val = 0x0006;
9012 9006
9013 DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); 9007 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9014 /* enable LASI */ 9008 /* Enable LASI */
9015 bnx2x_cl45_write(bp, phy, 9009 bnx2x_cl45_write(bp, phy,
9016 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9010 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9017 rx_alarm_ctrl_val); 9011 rx_alarm_ctrl_val);
@@ -9733,7 +9727,7 @@ static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9733 MDIO_84833_CMD_HDLR_STATUS, &val); 9727 MDIO_84833_CMD_HDLR_STATUS, &val);
9734 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) 9728 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9735 break; 9729 break;
9736 msleep(1); 9730 usleep_range(1000, 2000);
9737 } 9731 }
9738 if (idx >= PHY84833_CMDHDLR_WAIT) { 9732 if (idx >= PHY84833_CMDHDLR_WAIT) {
9739 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); 9733 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
@@ -9754,7 +9748,7 @@ static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9754 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || 9748 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9755 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) 9749 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9756 break; 9750 break;
9757 msleep(1); 9751 usleep_range(1000, 2000);
9758 } 9752 }
9759 if ((idx >= PHY84833_CMDHDLR_WAIT) || 9753 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9760 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { 9754 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
@@ -9924,7 +9918,7 @@ static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
9924 /* Prevent Phy from working in EEE and advertising it */ 9918 /* Prevent Phy from working in EEE and advertising it */
9925 rc = bnx2x_84833_cmd_hdlr(phy, params, 9919 rc = bnx2x_84833_cmd_hdlr(phy, params,
9926 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 9920 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9927 if (rc != 0) { 9921 if (rc) {
9928 DP(NETIF_MSG_LINK, "EEE disable failed.\n"); 9922 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
9929 return rc; 9923 return rc;
9930 } 9924 }
@@ -9947,7 +9941,7 @@ static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
9947 9941
9948 rc = bnx2x_84833_cmd_hdlr(phy, params, 9942 rc = bnx2x_84833_cmd_hdlr(phy, params,
9949 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 9943 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9950 if (rc != 0) { 9944 if (rc) {
9951 DP(NETIF_MSG_LINK, "EEE enable failed.\n"); 9945 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
9952 return rc; 9946 return rc;
9953 } 9947 }
@@ -9975,7 +9969,7 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9975 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; 9969 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
9976 int rc = 0; 9970 int rc = 0;
9977 9971
9978 msleep(1); 9972 usleep_range(1000, 2000);
9979 9973
9980 if (!(CHIP_IS_E1(bp))) 9974 if (!(CHIP_IS_E1(bp)))
9981 port = BP_PATH(bp); 9975 port = BP_PATH(bp);
@@ -10064,7 +10058,7 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10064 rc = bnx2x_84833_cmd_hdlr(phy, params, 10058 rc = bnx2x_84833_cmd_hdlr(phy, params,
10065 PHY84833_CMD_SET_EEE_MODE, cmd_args, 10059 PHY84833_CMD_SET_EEE_MODE, cmd_args,
10066 PHY84833_CMDHDLR_MAX_ARGS); 10060 PHY84833_CMDHDLR_MAX_ARGS);
10067 if (rc != 0) 10061 if (rc)
10068 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); 10062 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10069 } 10063 }
10070 if (initialize) 10064 if (initialize)
@@ -10108,7 +10102,7 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10108 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; 10102 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
10109 10103
10110 rc = bnx2x_8483x_eee_timers(params, vars); 10104 rc = bnx2x_8483x_eee_timers(params, vars);
10111 if (rc != 0) { 10105 if (rc) {
10112 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 10106 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10113 bnx2x_8483x_disable_eee(phy, params, vars); 10107 bnx2x_8483x_disable_eee(phy, params, vars);
10114 return rc; 10108 return rc;
@@ -10121,7 +10115,7 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10121 rc = bnx2x_8483x_enable_eee(phy, params, vars); 10115 rc = bnx2x_8483x_enable_eee(phy, params, vars);
10122 else 10116 else
10123 rc = bnx2x_8483x_disable_eee(phy, params, vars); 10117 rc = bnx2x_8483x_disable_eee(phy, params, vars);
10124 if (rc != 0) { 10118 if (rc) {
10125 DP(NETIF_MSG_LINK, "Failed to set EEE advertisment\n"); 10119 DP(NETIF_MSG_LINK, "Failed to set EEE advertisment\n");
10126 return rc; 10120 return rc;
10127 } 10121 }
@@ -10222,7 +10216,7 @@ static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10222 } 10216 }
10223 } 10217 }
10224 if (link_up) { 10218 if (link_up) {
10225 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n", 10219 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10226 vars->line_speed); 10220 vars->line_speed);
10227 bnx2x_ext_phy_resolve_fc(phy, params, vars); 10221 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10228 10222
@@ -10564,7 +10558,7 @@ static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10564 u32 cfg_pin; 10558 u32 cfg_pin;
10565 10559
10566 DP(NETIF_MSG_LINK, "54618SE cfg init\n"); 10560 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10567 usleep_range(1000, 1000); 10561 usleep_range(1000, 2000);
10568 10562
10569 /* This works with E3 only, no need to check the chip 10563 /* This works with E3 only, no need to check the chip
10570 * before determining the port. 10564 * before determining the port.
@@ -10633,7 +10627,7 @@ static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10633 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 10627 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10634 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 10628 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10635 10629
10636 /* read all advertisement */ 10630 /* Read all advertisement */
10637 bnx2x_cl22_read(bp, phy, 10631 bnx2x_cl22_read(bp, phy,
10638 0x09, 10632 0x09,
10639 &an_1000_val); 10633 &an_1000_val);
@@ -10670,7 +10664,7 @@ static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10670 0x09, 10664 0x09,
10671 &an_1000_val); 10665 &an_1000_val);
10672 10666
10673 /* set 100 speed advertisement */ 10667 /* Set 100 speed advertisement */
10674 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 10668 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10675 (phy->speed_cap_mask & 10669 (phy->speed_cap_mask &
10676 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | 10670 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
@@ -10684,7 +10678,7 @@ static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10684 DP(NETIF_MSG_LINK, "Advertising 100M\n"); 10678 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10685 } 10679 }
10686 10680
10687 /* set 10 speed advertisement */ 10681 /* Set 10 speed advertisement */
10688 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 10682 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10689 (phy->speed_cap_mask & 10683 (phy->speed_cap_mask &
10690 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | 10684 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
@@ -11050,7 +11044,7 @@ static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11050 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", 11044 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11051 val2, val1); 11045 val2, val1);
11052 link_up = ((val1 & 4) == 4); 11046 link_up = ((val1 & 4) == 4);
11053 /* if link is up print the AN outcome of the SFX7101 PHY */ 11047 /* If link is up print the AN outcome of the SFX7101 PHY */
11054 if (link_up) { 11048 if (link_up) {
11055 bnx2x_cl45_read(bp, phy, 11049 bnx2x_cl45_read(bp, phy,
11056 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, 11050 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
@@ -11062,7 +11056,7 @@ static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11062 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 11056 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11063 bnx2x_ext_phy_resolve_fc(phy, params, vars); 11057 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11064 11058
11065 /* read LP advertised speeds */ 11059 /* Read LP advertised speeds */
11066 if (val2 & (1<<11)) 11060 if (val2 & (1<<11))
11067 vars->link_status |= 11061 vars->link_status |=
11068 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 11062 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
@@ -12260,7 +12254,7 @@ int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12260 vars->mac_type = MAC_TYPE_NONE; 12254 vars->mac_type = MAC_TYPE_NONE;
12261 vars->phy_flags = 0; 12255 vars->phy_flags = 0;
12262 12256
12263 /* disable attentions */ 12257 /* Disable attentions */
12264 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 12258 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12265 (NIG_MASK_XGXS0_LINK_STATUS | 12259 (NIG_MASK_XGXS0_LINK_STATUS |
12266 NIG_MASK_XGXS0_LINK10G | 12260 NIG_MASK_XGXS0_LINK10G |
@@ -12320,7 +12314,7 @@ int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12320 struct bnx2x *bp = params->bp; 12314 struct bnx2x *bp = params->bp;
12321 u8 phy_index, port = params->port, clear_latch_ind = 0; 12315 u8 phy_index, port = params->port, clear_latch_ind = 0;
12322 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); 12316 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12323 /* disable attentions */ 12317 /* Disable attentions */
12324 vars->link_status = 0; 12318 vars->link_status = 0;
12325 bnx2x_update_mng(params, vars->link_status); 12319 bnx2x_update_mng(params, vars->link_status);
12326 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 12320 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
@@ -12332,10 +12326,10 @@ int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12332 NIG_MASK_SERDES0_LINK_STATUS | 12326 NIG_MASK_SERDES0_LINK_STATUS |
12333 NIG_MASK_MI_INT)); 12327 NIG_MASK_MI_INT));
12334 12328
12335 /* activate nig drain */ 12329 /* Activate nig drain */
12336 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 12330 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12337 12331
12338 /* disable nig egress interface */ 12332 /* Disable nig egress interface */
12339 if (!CHIP_IS_E3(bp)) { 12333 if (!CHIP_IS_E3(bp)) {
12340 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); 12334 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12341 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); 12335 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
@@ -12348,15 +12342,15 @@ int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12348 bnx2x_xmac_disable(params); 12342 bnx2x_xmac_disable(params);
12349 bnx2x_umac_disable(params); 12343 bnx2x_umac_disable(params);
12350 } 12344 }
12351 /* disable emac */ 12345 /* Disable emac */
12352 if (!CHIP_IS_E3(bp)) 12346 if (!CHIP_IS_E3(bp))
12353 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 12347 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12354 12348
12355 msleep(10); 12349 usleep_range(10000, 20000);
12356 /* The PHY reset is controlled by GPIO 1 12350 /* The PHY reset is controlled by GPIO 1
12357 * Hold it as vars low 12351 * Hold it as vars low
12358 */ 12352 */
12359 /* clear link led */ 12353 /* Clear link led */
12360 bnx2x_set_mdio_clk(bp, params->chip_id, port); 12354 bnx2x_set_mdio_clk(bp, params->chip_id, port);
12361 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 12355 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12362 12356
@@ -12386,9 +12380,9 @@ int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12386 params->phy[INT_PHY].link_reset( 12380 params->phy[INT_PHY].link_reset(
12387 &params->phy[INT_PHY], params); 12381 &params->phy[INT_PHY], params);
12388 12382
12389 /* disable nig ingress interface */ 12383 /* Disable nig ingress interface */
12390 if (!CHIP_IS_E3(bp)) { 12384 if (!CHIP_IS_E3(bp)) {
12391 /* reset BigMac */ 12385 /* Reset BigMac */
12392 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 12386 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12393 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 12387 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12394 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); 12388 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
@@ -12445,7 +12439,7 @@ static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12445 DP(NETIF_MSG_LINK, "populate_phy failed\n"); 12439 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12446 return -EINVAL; 12440 return -EINVAL;
12447 } 12441 }
12448 /* disable attentions */ 12442 /* Disable attentions */
12449 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 12443 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12450 port_of_path*4, 12444 port_of_path*4,
12451 (NIG_MASK_XGXS0_LINK_STATUS | 12445 (NIG_MASK_XGXS0_LINK_STATUS |
@@ -12519,7 +12513,7 @@ static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12519 bnx2x_cl45_write(bp, phy_blk[port], 12513 bnx2x_cl45_write(bp, phy_blk[port],
12520 MDIO_PMA_DEVAD, 12514 MDIO_PMA_DEVAD,
12521 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 12515 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12522 msleep(15); 12516 usleep_range(15000, 30000);
12523 12517
12524 /* Read modify write the SPI-ROM version select register */ 12518 /* Read modify write the SPI-ROM version select register */
12525 bnx2x_cl45_read(bp, phy_blk[port], 12519 bnx2x_cl45_read(bp, phy_blk[port],
@@ -12551,7 +12545,7 @@ static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12551 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 12545 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12552 12546
12553 bnx2x_ext_phy_hw_reset(bp, 0); 12547 bnx2x_ext_phy_hw_reset(bp, 0);
12554 msleep(5); 12548 usleep_range(5000, 10000);
12555 for (port = 0; port < PORT_MAX; port++) { 12549 for (port = 0; port < PORT_MAX; port++) {
12556 u32 shmem_base, shmem2_base; 12550 u32 shmem_base, shmem2_base;
12557 12551
@@ -12658,11 +12652,11 @@ static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
12658 /* Initiate PHY reset*/ 12652 /* Initiate PHY reset*/
12659 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, 12653 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12660 port); 12654 port);
12661 msleep(1); 12655 usleep_range(1000, 2000);
12662 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, 12656 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12663 port); 12657 port);
12664 12658
12665 msleep(5); 12659 usleep_range(5000, 10000);
12666 12660
12667 /* PART1 - Reset both phys */ 12661 /* PART1 - Reset both phys */
12668 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12662 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
@@ -12756,7 +12750,7 @@ static int bnx2x_84833_pre_init_phy(struct bnx2x *bp,
12756 MDIO_PMA_REG_CTRL, &val); 12750 MDIO_PMA_REG_CTRL, &val);
12757 if (!(val & (1<<15))) 12751 if (!(val & (1<<15)))
12758 break; 12752 break;
12759 msleep(1); 12753 usleep_range(1000, 2000);
12760 } 12754 }
12761 if (cnt >= 1500) { 12755 if (cnt >= 1500) {
12762 DP(NETIF_MSG_LINK, "84833 reset timeout\n"); 12756 DP(NETIF_MSG_LINK, "84833 reset timeout\n");
@@ -12846,7 +12840,7 @@ static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12846 break; 12840 break;
12847 } 12841 }
12848 12842
12849 if (rc != 0) 12843 if (rc)
12850 netdev_err(bp->dev, "Warning: PHY was not initialized," 12844 netdev_err(bp->dev, "Warning: PHY was not initialized,"
12851 " Port %d\n", 12845 " Port %d\n",
12852 0); 12846 0);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 07:11:45 -0500