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authorLinus Torvalds <torvalds@linux-foundation.org>2014-12-09 20:25:00 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-12-09 20:25:00 -0500
commita0e4467726cd26bacb16f13d207ffcfa82ffc07d (patch)
tree98b5fcbda0cd787b07d09da90d25c87b3883c567
parented8efd2de75479a175bd21df073d9e97df65a820 (diff)
parentcb61f6769b8836081940ba26249f1b756400c7df (diff)
Merge tag 'asm-generic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic
Pull asm-generic asm/io.h rewrite from Arnd Bergmann: "While there normally is no reason to have a pull request for asm-generic but have all changes get merged through whichever tree needs them, I do have a series for 3.19. There are two sets of patches that change significant portions of asm/io.h, and this branch contains both in order to resolve the conflicts: - Will Deacon has done a set of patches to ensure that all architectures define {read,write}{b,w,l,q}_relaxed() functions or get them by including asm-generic/io.h. These functions are commonly used on ARM specific drivers to avoid expensive L2 cache synchronization implied by the normal {read,write}{b,w,l,q}, but we need to define them on all architectures in order to share the drivers across architectures and to enable CONFIG_COMPILE_TEST configurations for them - Thierry Reding has done an unrelated set of patches that extends the asm-generic/io.h file to the degree necessary to make it useful on ARM64 and potentially other architectures" * tag 'asm-generic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (29 commits) ARM64: use GENERIC_PCI_IOMAP sparc: io: remove duplicate relaxed accessors on sparc32 ARM: sa11x0: Use void __iomem * in MMIO accessors arm64: Use include/asm-generic/io.h ARM: Use include/asm-generic/io.h asm-generic/io.h: Implement generic {read,write}s*() asm-generic/io.h: Reconcile I/O accessor overrides /dev/mem: Use more consistent data types Change xlate_dev_{kmem,mem}_ptr() prototypes ARM: ixp4xx: Properly override I/O accessors ARM: ixp4xx: Fix build with IXP4XX_INDIRECT_PCI ARM: ebsa110: Properly override I/O accessors ARC: Remove redundant PCI_IOBASE declaration documentation: memory-barriers: clarify relaxed io accessor semantics x86: io: implement dummy relaxed accessor macros for writes tile: io: implement dummy relaxed accessor macros for writes sparc: io: implement dummy relaxed accessor macros for writes powerpc: io: implement dummy relaxed accessor macros for writes parisc: io: implement dummy relaxed accessor macros for writes mn10300: io: implement dummy relaxed accessor macros for writes ...
Diffstat
-rw-r--r--Documentation/memory-barriers.txt13
-rw-r--r--arch/arc/include/asm/io.h2
-rw-r--r--arch/arm/include/asm/io.h89
-rw-r--r--arch/arm/include/asm/memory.h4
-rw-r--r--arch/arm/mach-ebsa110/include/mach/io.h25
-rw-r--r--arch/arm/mach-ebsa110/io.c14
-rw-r--r--arch/arm/mach-ixp4xx/common.c2
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/io.h24
-rw-r--r--arch/arm/mach-sa1100/pci-nanoengine.c8
-rw-r--r--arch/arm64/Kconfig2
-rw-r--r--arch/arm64/include/asm/io.h122
-rw-r--r--arch/arm64/include/asm/memory.h2
-rw-r--r--arch/cris/include/asm/io.h3
-rw-r--r--arch/frv/include/asm/io.h3
-rw-r--r--arch/ia64/include/asm/io.h4
-rw-r--r--arch/ia64/include/asm/uaccess.h16
-rw-r--r--arch/m32r/include/asm/io.h3
-rw-r--r--arch/m68k/include/asm/io.h8
-rw-r--r--arch/m68k/include/asm/io_no.h4
-rw-r--r--arch/microblaze/include/asm/io.h8
-rw-r--r--arch/mn10300/include/asm/io.h4
-rw-r--r--arch/parisc/include/asm/io.h12
-rw-r--r--arch/powerpc/include/asm/io.h12
-rw-r--r--arch/s390/include/asm/io.h10
-rw-r--r--arch/s390/mm/maccess.c4
-rw-r--r--arch/sparc/include/asm/io_32.h4
-rw-r--r--arch/sparc/include/asm/io_64.h14
-rw-r--r--arch/tile/include/asm/io.h4
-rw-r--r--arch/x86/include/asm/io.h8
-rw-r--r--arch/x86/mm/ioremap.c4
-rw-r--r--arch/xtensa/include/asm/io.h7
-rw-r--r--drivers/char/mem.c13
-rw-r--r--include/asm-generic/io.h751
33 files changed, 835 insertions, 368 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index 22a969cdd476..4af4cea8cff0 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -2465,10 +2465,15 @@ functions:
2465 Please refer to the PCI specification for more information on interactions 2465 Please refer to the PCI specification for more information on interactions
2466 between PCI transactions. 2466 between PCI transactions.
2467 2467
2468 (*) readX_relaxed() 2468 (*) readX_relaxed(), writeX_relaxed()
2469 2469
2470 These are similar to readX(), but are not guaranteed to be ordered in any 2470 These are similar to readX() and writeX(), but provide weaker memory
2471 way. Be aware that there is no I/O read barrier available. 2471 ordering guarantees. Specifically, they do not guarantee ordering with
2472 respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee
2473 ordering with respect to LOCK or UNLOCK operations. If the latter is
2474 required, an mmiowb() barrier can be used. Note that relaxed accesses to
2475 the same peripheral are guaranteed to be ordered with respect to each
2476 other.
2472 2477
2473 (*) ioreadX(), iowriteX() 2478 (*) ioreadX(), iowriteX()
2474 2479
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index 334ce7017a18..cabd518cb253 100644
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -13,8 +13,6 @@
13#include <asm/byteorder.h> 13#include <asm/byteorder.h>
14#include <asm/page.h> 14#include <asm/page.h>
15 15
16#define PCI_IOBASE ((void __iomem *)0)
17
18extern void __iomem *ioremap(unsigned long physaddr, unsigned long size); 16extern void __iomem *ioremap(unsigned long physaddr, unsigned long size);
19extern void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size, 17extern void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
20 unsigned long flags); 18 unsigned long flags);
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 180567408ee8..db58deb00aa7 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -47,13 +47,13 @@ extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set);
47 * Generic IO read/write. These perform native-endian accesses. Note 47 * Generic IO read/write. These perform native-endian accesses. Note
48 * that some architectures will want to re-define __raw_{read,write}w. 48 * that some architectures will want to re-define __raw_{read,write}w.
49 */ 49 */
50extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen); 50void __raw_writesb(volatile void __iomem *addr, const void *data, int bytelen);
51extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen); 51void __raw_writesw(volatile void __iomem *addr, const void *data, int wordlen);
52extern void __raw_writesl(void __iomem *addr, const void *data, int longlen); 52void __raw_writesl(volatile void __iomem *addr, const void *data, int longlen);
53 53
54extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen); 54void __raw_readsb(const volatile void __iomem *addr, void *data, int bytelen);
55extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen); 55void __raw_readsw(const volatile void __iomem *addr, void *data, int wordlen);
56extern void __raw_readsl(const void __iomem *addr, void *data, int longlen); 56void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen);
57 57
58#if __LINUX_ARM_ARCH__ < 6 58#if __LINUX_ARM_ARCH__ < 6
59/* 59/*
@@ -69,6 +69,7 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
69 * writeback addressing modes as these incur a significant performance 69 * writeback addressing modes as these incur a significant performance
70 * overhead (the address generation must be emulated in software). 70 * overhead (the address generation must be emulated in software).
71 */ 71 */
72#define __raw_writew __raw_writew
72static inline void __raw_writew(u16 val, volatile void __iomem *addr) 73static inline void __raw_writew(u16 val, volatile void __iomem *addr)
73{ 74{
74 asm volatile("strh %1, %0" 75 asm volatile("strh %1, %0"
@@ -76,6 +77,7 @@ static inline void __raw_writew(u16 val, volatile void __iomem *addr)
76 : "r" (val)); 77 : "r" (val));
77} 78}
78 79
80#define __raw_readw __raw_readw
79static inline u16 __raw_readw(const volatile void __iomem *addr) 81static inline u16 __raw_readw(const volatile void __iomem *addr)
80{ 82{
81 u16 val; 83 u16 val;
@@ -86,6 +88,7 @@ static inline u16 __raw_readw(const volatile void __iomem *addr)
86} 88}
87#endif 89#endif
88 90
91#define __raw_writeb __raw_writeb
89static inline void __raw_writeb(u8 val, volatile void __iomem *addr) 92static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
90{ 93{
91 asm volatile("strb %1, %0" 94 asm volatile("strb %1, %0"
@@ -93,6 +96,7 @@ static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
93 : "r" (val)); 96 : "r" (val));
94} 97}
95 98
99#define __raw_writel __raw_writel
96static inline void __raw_writel(u32 val, volatile void __iomem *addr) 100static inline void __raw_writel(u32 val, volatile void __iomem *addr)
97{ 101{
98 asm volatile("str %1, %0" 102 asm volatile("str %1, %0"
@@ -100,6 +104,7 @@ static inline void __raw_writel(u32 val, volatile void __iomem *addr)
100 : "r" (val)); 104 : "r" (val));
101} 105}
102 106
107#define __raw_readb __raw_readb
103static inline u8 __raw_readb(const volatile void __iomem *addr) 108static inline u8 __raw_readb(const volatile void __iomem *addr)
104{ 109{
105 u8 val; 110 u8 val;
@@ -109,6 +114,7 @@ static inline u8 __raw_readb(const volatile void __iomem *addr)
109 return val; 114 return val;
110} 115}
111 116
117#define __raw_readl __raw_readl
112static inline u32 __raw_readl(const volatile void __iomem *addr) 118static inline u32 __raw_readl(const volatile void __iomem *addr)
113{ 119{
114 u32 val; 120 u32 val;
@@ -267,20 +273,6 @@ extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
267#define insl(p,d,l) __raw_readsl(__io(p),d,l) 273#define insl(p,d,l) __raw_readsl(__io(p),d,l)
268#endif 274#endif
269 275
270#define outb_p(val,port) outb((val),(port))
271#define outw_p(val,port) outw((val),(port))
272#define outl_p(val,port) outl((val),(port))
273#define inb_p(port) inb((port))
274#define inw_p(port) inw((port))
275#define inl_p(port) inl((port))
276
277#define outsb_p(port,from,len) outsb(port,from,len)
278#define outsw_p(port,from,len) outsw(port,from,len)
279#define outsl_p(port,from,len) outsl(port,from,len)
280#define insb_p(port,to,len) insb(port,to,len)
281#define insw_p(port,to,len) insw(port,to,len)
282#define insl_p(port,to,len) insl(port,to,len)
283
284/* 276/*
285 * String version of IO memory access ops: 277 * String version of IO memory access ops:
286 */ 278 */
@@ -347,40 +339,42 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
347#define iounmap __arm_iounmap 339#define iounmap __arm_iounmap
348 340
349/* 341/*
350 * io{read,write}{8,16,32} macros 342 * io{read,write}{16,32}be() macros
351 */ 343 */
352#ifndef ioread8 344#define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
353#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __iormb(); __v; }) 345#define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
354#define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })
355#define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })
356
357#define ioread16be(p) ({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
358#define ioread32be(p) ({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
359
360#define iowrite8(v,p) ({ __iowmb(); __raw_writeb(v, p); })
361#define iowrite16(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_le16(v), p); })
362#define iowrite32(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_le32(v), p); })
363 346
364#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); }) 347#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
365#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); }) 348#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
366
367#define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
368#define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
369#define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
370
371#define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
372#define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
373#define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
374 349
350#ifndef ioport_map
351#define ioport_map ioport_map
375extern void __iomem *ioport_map(unsigned long port, unsigned int nr); 352extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
353#endif
354#ifndef ioport_unmap
355#define ioport_unmap ioport_unmap
376extern void ioport_unmap(void __iomem *addr); 356extern void ioport_unmap(void __iomem *addr);
377#endif 357#endif
378 358
379struct pci_dev; 359struct pci_dev;
380 360
361#define pci_iounmap pci_iounmap
381extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); 362extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
382 363
383/* 364/*
365 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
366 * access
367 */
368#define xlate_dev_mem_ptr(p) __va(p)
369
370/*
371 * Convert a virtual cached pointer to an uncached pointer
372 */
373#define xlate_dev_kmem_ptr(p) p
374
375#include <asm-generic/io.h>
376
377/*
384 * can the hardware map this into one segment or not, given no other 378 * can the hardware map this into one segment or not, given no other
385 * constraints. 379 * constraints.
386 */ 380 */
@@ -402,17 +396,6 @@ extern int devmem_is_allowed(unsigned long pfn);
402#endif 396#endif
403 397
404/* 398/*
405 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
406 * access
407 */
408#define xlate_dev_mem_ptr(p) __va(p)
409
410/*
411 * Convert a virtual cached pointer to an uncached pointer
412 */
413#define xlate_dev_kmem_ptr(p) p
414
415/*
416 * Register ISA memory and port locations for glibc iopl/inb/outb 399 * Register ISA memory and port locations for glibc iopl/inb/outb
417 * emulation. 400 * emulation.
418 */ 401 */
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index e731018869a7..184def0e1652 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -274,11 +274,13 @@ static inline unsigned long __phys_to_virt(phys_addr_t x)
274 * translation for translating DMA addresses. Use the driver 274 * translation for translating DMA addresses. Use the driver
275 * DMA support - see dma-mapping.h. 275 * DMA support - see dma-mapping.h.
276 */ 276 */
277#define virt_to_phys virt_to_phys
277static inline phys_addr_t virt_to_phys(const volatile void *x) 278static inline phys_addr_t virt_to_phys(const volatile void *x)
278{ 279{
279 return __virt_to_phys((unsigned long)(x)); 280 return __virt_to_phys((unsigned long)(x));
280} 281}
281 282
283#define phys_to_virt phys_to_virt
282static inline void *phys_to_virt(phys_addr_t x) 284static inline void *phys_to_virt(phys_addr_t x)
283{ 285{
284 return (void *)__phys_to_virt(x); 286 return (void *)__phys_to_virt(x);
@@ -322,11 +324,13 @@ static inline phys_addr_t __virt_to_idmap(unsigned long x)
322#endif 324#endif
323 325
324#ifdef CONFIG_VIRT_TO_BUS 326#ifdef CONFIG_VIRT_TO_BUS
327#define virt_to_bus virt_to_bus
325static inline __deprecated unsigned long virt_to_bus(void *x) 328static inline __deprecated unsigned long virt_to_bus(void *x)
326{ 329{
327 return __virt_to_bus((unsigned long)x); 330 return __virt_to_bus((unsigned long)x);
328} 331}
329 332
333#define bus_to_virt bus_to_virt
330static inline __deprecated void *bus_to_virt(unsigned long x) 334static inline __deprecated void *bus_to_virt(unsigned long x)
331{ 335{
332 return (void *)__bus_to_virt(x); 336 return (void *)__bus_to_virt(x);
diff --git a/arch/arm/mach-ebsa110/include/mach/io.h b/arch/arm/mach-ebsa110/include/mach/io.h
index 11bb0799424b..69975784acfa 100644
--- a/arch/arm/mach-ebsa110/include/mach/io.h
+++ b/arch/arm/mach-ebsa110/include/mach/io.h
@@ -29,9 +29,9 @@ u8 __readb(const volatile void __iomem *addr);
29u16 __readw(const volatile void __iomem *addr); 29u16 __readw(const volatile void __iomem *addr);
30u32 __readl(const volatile void __iomem *addr); 30u32 __readl(const volatile void __iomem *addr);
31 31
32void __writeb(u8 val, void __iomem *addr); 32void __writeb(u8 val, volatile void __iomem *addr);
33void __writew(u16 val, void __iomem *addr); 33void __writew(u16 val, volatile void __iomem *addr);
34void __writel(u32 val, void __iomem *addr); 34void __writel(u32 val, volatile void __iomem *addr);
35 35
36/* 36/*
37 * Argh, someone forgot the IOCS16 line. We therefore have to handle 37 * Argh, someone forgot the IOCS16 line. We therefore have to handle
@@ -62,20 +62,31 @@ void __writel(u32 val, void __iomem *addr);
62#define writew(v,b) __writew(v,b) 62#define writew(v,b) __writew(v,b)
63#define writel(v,b) __writel(v,b) 63#define writel(v,b) __writel(v,b)
64 64
65#define insb insb
65extern void insb(unsigned int port, void *buf, int sz); 66extern void insb(unsigned int port, void *buf, int sz);
67#define insw insw
66extern void insw(unsigned int port, void *buf, int sz); 68extern void insw(unsigned int port, void *buf, int sz);
69#define insl insl
67extern void insl(unsigned int port, void *buf, int sz); 70extern void insl(unsigned int port, void *buf, int sz);
68 71
72#define outsb outsb
69extern void outsb(unsigned int port, const void *buf, int sz); 73extern void outsb(unsigned int port, const void *buf, int sz);
74#define outsw outsw
70extern void outsw(unsigned int port, const void *buf, int sz); 75extern void outsw(unsigned int port, const void *buf, int sz);
76#define outsl outsl
71extern void outsl(unsigned int port, const void *buf, int sz); 77extern void outsl(unsigned int port, const void *buf, int sz);
72 78
73/* can't support writesb atm */ 79/* can't support writesb atm */
74extern void writesw(void __iomem *addr, const void *data, int wordlen); 80#define writesw writesw
75extern void writesl(void __iomem *addr, const void *data, int longlen); 81extern void writesw(volatile void __iomem *addr, const void *data, int wordlen);
82#define writesl writesl
83extern void writesl(volatile void __iomem *addr, const void *data, int longlen);
76 84
77/* can't support readsb atm */ 85/* can't support readsb atm */
78extern void readsw(const void __iomem *addr, void *data, int wordlen); 86#define readsw readsw
79extern void readsl(const void __iomem *addr, void *data, int longlen); 87extern void readsw(const volatile void __iomem *addr, void *data, int wordlen);
88
89#define readsl readsl
90extern void readsl(const volatile void __iomem *addr, void *data, int longlen);
80 91
81#endif 92#endif
diff --git a/arch/arm/mach-ebsa110/io.c b/arch/arm/mach-ebsa110/io.c
index 756cc377a73d..b57980b435fd 100644
--- a/arch/arm/mach-ebsa110/io.c
+++ b/arch/arm/mach-ebsa110/io.c
@@ -102,7 +102,7 @@ EXPORT_SYMBOL(__readb);
102EXPORT_SYMBOL(__readw); 102EXPORT_SYMBOL(__readw);
103EXPORT_SYMBOL(__readl); 103EXPORT_SYMBOL(__readl);
104 104
105void readsw(const void __iomem *addr, void *data, int len) 105void readsw(const volatile void __iomem *addr, void *data, int len)
106{ 106{
107 void __iomem *a = __isamem_convert_addr(addr); 107 void __iomem *a = __isamem_convert_addr(addr);
108 108
@@ -112,7 +112,7 @@ void readsw(const void __iomem *addr, void *data, int len)
112} 112}
113EXPORT_SYMBOL(readsw); 113EXPORT_SYMBOL(readsw);
114 114
115void readsl(const void __iomem *addr, void *data, int len) 115void readsl(const volatile void __iomem *addr, void *data, int len)
116{ 116{
117 void __iomem *a = __isamem_convert_addr(addr); 117 void __iomem *a = __isamem_convert_addr(addr);
118 118
@@ -122,7 +122,7 @@ void readsl(const void __iomem *addr, void *data, int len)
122} 122}
123EXPORT_SYMBOL(readsl); 123EXPORT_SYMBOL(readsl);
124 124
125void __writeb(u8 val, void __iomem *addr) 125void __writeb(u8 val, volatile void __iomem *addr)
126{ 126{
127 void __iomem *a = __isamem_convert_addr(addr); 127 void __iomem *a = __isamem_convert_addr(addr);
128 128
@@ -132,7 +132,7 @@ void __writeb(u8 val, void __iomem *addr)
132 __raw_writeb(val, a); 132 __raw_writeb(val, a);
133} 133}
134 134
135void __writew(u16 val, void __iomem *addr) 135void __writew(u16 val, volatile void __iomem *addr)
136{ 136{
137 void __iomem *a = __isamem_convert_addr(addr); 137 void __iomem *a = __isamem_convert_addr(addr);
138 138
@@ -142,7 +142,7 @@ void __writew(u16 val, void __iomem *addr)
142 __raw_writew(val, a); 142 __raw_writew(val, a);
143} 143}
144 144
145void __writel(u32 val, void __iomem *addr) 145void __writel(u32 val, volatile void __iomem *addr)
146{ 146{
147 void __iomem *a = __isamem_convert_addr(addr); 147 void __iomem *a = __isamem_convert_addr(addr);
148 148
@@ -157,7 +157,7 @@ EXPORT_SYMBOL(__writeb);
157EXPORT_SYMBOL(__writew); 157EXPORT_SYMBOL(__writew);
158EXPORT_SYMBOL(__writel); 158EXPORT_SYMBOL(__writel);
159 159
160void writesw(void __iomem *addr, const void *data, int len) 160void writesw(volatile void __iomem *addr, const void *data, int len)
161{ 161{
162 void __iomem *a = __isamem_convert_addr(addr); 162 void __iomem *a = __isamem_convert_addr(addr);
163 163
@@ -167,7 +167,7 @@ void writesw(void __iomem *addr, const void *data, int len)
167} 167}
168EXPORT_SYMBOL(writesw); 168EXPORT_SYMBOL(writesw);
169 169
170void writesl(void __iomem *addr, const void *data, int len) 170void writesl(volatile void __iomem *addr, const void *data, int len)
171{ 171{
172 void __iomem *a = __isamem_convert_addr(addr); 172 void __iomem *a = __isamem_convert_addr(addr);
173 173
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index fc4b7b24265e..8537d4c41e34 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -652,7 +652,7 @@ static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
652 return (void __iomem *)addr; 652 return (void __iomem *)addr;
653} 653}
654 654
655static void ixp4xx_iounmap(void __iomem *addr) 655static void ixp4xx_iounmap(volatile void __iomem *addr)
656{ 656{
657 if (!is_pci_memory((__force u32)addr)) 657 if (!is_pci_memory((__force u32)addr))
658 __iounmap(addr); 658 __iounmap(addr);
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index 7d11979da030..6a722860e34d 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -58,6 +58,10 @@ static inline int is_pci_memory(u32 addr)
58#define writew(v, p) __indirect_writew(v, p) 58#define writew(v, p) __indirect_writew(v, p)
59#define writel(v, p) __indirect_writel(v, p) 59#define writel(v, p) __indirect_writel(v, p)
60 60
61#define writeb_relaxed(v, p) __indirect_writeb(v, p)
62#define writew_relaxed(v, p) __indirect_writew(v, p)
63#define writel_relaxed(v, p) __indirect_writel(v, p)
64
61#define writesb(p, v, l) __indirect_writesb(p, v, l) 65#define writesb(p, v, l) __indirect_writesb(p, v, l)
62#define writesw(p, v, l) __indirect_writesw(p, v, l) 66#define writesw(p, v, l) __indirect_writesw(p, v, l)
63#define writesl(p, v, l) __indirect_writesl(p, v, l) 67#define writesl(p, v, l) __indirect_writesl(p, v, l)
@@ -66,6 +70,10 @@ static inline int is_pci_memory(u32 addr)
66#define readw(p) __indirect_readw(p) 70#define readw(p) __indirect_readw(p)
67#define readl(p) __indirect_readl(p) 71#define readl(p) __indirect_readl(p)
68 72
73#define readb_relaxed(p) __indirect_readb(p)
74#define readw_relaxed(p) __indirect_readw(p)
75#define readl_relaxed(p) __indirect_readl(p)
76
69#define readsb(p, v, l) __indirect_readsb(p, v, l) 77#define readsb(p, v, l) __indirect_readsb(p, v, l)
70#define readsw(p, v, l) __indirect_readsw(p, v, l) 78#define readsw(p, v, l) __indirect_readsw(p, v, l)
71#define readsl(p, v, l) __indirect_readsl(p, v, l) 79#define readsl(p, v, l) __indirect_readsl(p, v, l)
@@ -99,7 +107,7 @@ static inline void __indirect_writew(u16 value, volatile void __iomem *p)
99 u32 n, byte_enables, data; 107 u32 n, byte_enables, data;
100 108
101 if (!is_pci_memory(addr)) { 109 if (!is_pci_memory(addr)) {
102 __raw_writew(value, addr); 110 __raw_writew(value, p);
103 return; 111 return;
104 } 112 }
105 113
@@ -164,7 +172,7 @@ static inline unsigned short __indirect_readw(const volatile void __iomem *p)
164 u32 n, byte_enables, data; 172 u32 n, byte_enables, data;
165 173
166 if (!is_pci_memory(addr)) 174 if (!is_pci_memory(addr))
167 return __raw_readw(addr); 175 return __raw_readw(p);
168 176
169 n = addr % 4; 177 n = addr % 4;
170 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; 178 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
@@ -226,6 +234,7 @@ static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
226 * I/O functions. 234 * I/O functions.
227 */ 235 */
228 236
237#define outb outb
229static inline void outb(u8 value, u32 addr) 238static inline void outb(u8 value, u32 addr)
230{ 239{
231 u32 n, byte_enables, data; 240 u32 n, byte_enables, data;
@@ -235,12 +244,14 @@ static inline void outb(u8 value, u32 addr)
235 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); 244 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
236} 245}
237 246
247#define outsb outsb
238static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count) 248static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count)
239{ 249{
240 while (count--) 250 while (count--)
241 outb(*vaddr++, io_addr); 251 outb(*vaddr++, io_addr);
242} 252}
243 253
254#define outw outw
244static inline void outw(u16 value, u32 addr) 255static inline void outw(u16 value, u32 addr)
245{ 256{
246 u32 n, byte_enables, data; 257 u32 n, byte_enables, data;
@@ -250,23 +261,27 @@ static inline void outw(u16 value, u32 addr)
250 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); 261 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
251} 262}
252 263
264#define outsw outsw
253static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count) 265static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count)
254{ 266{
255 while (count--) 267 while (count--)
256 outw(cpu_to_le16(*vaddr++), io_addr); 268 outw(cpu_to_le16(*vaddr++), io_addr);
257} 269}
258 270
271#define outl outl
259static inline void outl(u32 value, u32 addr) 272static inline void outl(u32 value, u32 addr)
260{ 273{
261 ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); 274 ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
262} 275}
263 276
277#define outsl outsl
264static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count) 278static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count)
265{ 279{
266 while (count--) 280 while (count--)
267 outl(cpu_to_le32(*vaddr++), io_addr); 281 outl(cpu_to_le32(*vaddr++), io_addr);
268} 282}
269 283
284#define inb inb
270static inline u8 inb(u32 addr) 285static inline u8 inb(u32 addr)
271{ 286{
272 u32 n, byte_enables, data; 287 u32 n, byte_enables, data;
@@ -278,12 +293,14 @@ static inline u8 inb(u32 addr)
278 return data >> (8*n); 293 return data >> (8*n);
279} 294}
280 295
296#define insb insb
281static inline void insb(u32 io_addr, u8 *vaddr, u32 count) 297static inline void insb(u32 io_addr, u8 *vaddr, u32 count)
282{ 298{
283 while (count--) 299 while (count--)
284 *vaddr++ = inb(io_addr); 300 *vaddr++ = inb(io_addr);
285} 301}
286 302
303#define inw inw
287static inline u16 inw(u32 addr) 304static inline u16 inw(u32 addr)
288{ 305{
289 u32 n, byte_enables, data; 306 u32 n, byte_enables, data;
@@ -295,12 +312,14 @@ static inline u16 inw(u32 addr)
295 return data>>(8*n); 312 return data>>(8*n);
296} 313}
297 314
315#define insw insw
298static inline void insw(u32 io_addr, u16 *vaddr, u32 count) 316static inline void insw(u32 io_addr, u16 *vaddr, u32 count)
299{ 317{
300 while (count--) 318 while (count--)
301 *vaddr++ = le16_to_cpu(inw(io_addr)); 319 *vaddr++ = le16_to_cpu(inw(io_addr));
302} 320}
303 321
322#define inl inl
304static inline u32 inl(u32 addr) 323static inline u32 inl(u32 addr)
305{ 324{
306 u32 data; 325 u32 data;
@@ -310,6 +329,7 @@ static inline u32 inl(u32 addr)
310 return data; 329 return data;
311} 330}
312 331
332#define insl insl
313static inline void insl(u32 io_addr, u32 *vaddr, u32 count) 333static inline void insl(u32 io_addr, u32 *vaddr, u32 count)
314{ 334{
315 while (count--) 335 while (count--)
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
index ff02e2da99f2..b704433c529c 100644
--- a/arch/arm/mach-sa1100/pci-nanoengine.c
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -33,12 +33,12 @@
33static DEFINE_SPINLOCK(nano_lock); 33static DEFINE_SPINLOCK(nano_lock);
34 34
35static int nanoengine_get_pci_address(struct pci_bus *bus, 35static int nanoengine_get_pci_address(struct pci_bus *bus,
36 unsigned int devfn, int where, unsigned long *address) 36 unsigned int devfn, int where, void __iomem **address)
37{ 37{
38 int ret = PCIBIOS_DEVICE_NOT_FOUND; 38 int ret = PCIBIOS_DEVICE_NOT_FOUND;
39 unsigned int busnr = bus->number; 39 unsigned int busnr = bus->number;
40 40
41 *address = NANO_PCI_CONFIG_SPACE_VIRT + 41 *address = (void __iomem *)NANO_PCI_CONFIG_SPACE_VIRT +
42 ((bus->number << 16) | (devfn << 8) | (where & ~3)); 42 ((bus->number << 16) | (devfn << 8) | (where & ~3));
43 43
44 ret = (busnr > 255 || devfn > 255 || where > 255) ? 44 ret = (busnr > 255 || devfn > 255 || where > 255) ?
@@ -51,7 +51,7 @@ static int nanoengine_read_config(struct pci_bus *bus, unsigned int devfn, int w
51 int size, u32 *val) 51 int size, u32 *val)
52{ 52{
53 int ret; 53 int ret;
54 unsigned long address; 54 void __iomem *address;
55 unsigned long flags; 55 unsigned long flags;
56 u32 v; 56 u32 v;
57 57
@@ -85,7 +85,7 @@ static int nanoengine_write_config(struct pci_bus *bus, unsigned int devfn, int
85 int size, u32 val) 85 int size, u32 val)
86{ 86{
87 int ret; 87 int ret;
88 unsigned long address; 88 void __iomem *address;
89 unsigned long flags; 89 unsigned long flags;
90 unsigned shift; 90 unsigned shift;
91 u32 v; 91 u32 v;
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index f385273f4b24..6b1ebd964c10 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -24,9 +24,9 @@ config ARM64
24 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 24 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
25 select GENERIC_CPU_AUTOPROBE 25 select GENERIC_CPU_AUTOPROBE
26 select GENERIC_EARLY_IOREMAP 26 select GENERIC_EARLY_IOREMAP
27 select GENERIC_IOMAP
28 select GENERIC_IRQ_PROBE 27 select GENERIC_IRQ_PROBE
29 select GENERIC_IRQ_SHOW 28 select GENERIC_IRQ_SHOW
29 select GENERIC_PCI_IOMAP
30 select GENERIC_SCHED_CLOCK 30 select GENERIC_SCHED_CLOCK
31 select GENERIC_SMP_IDLE_THREAD 31 select GENERIC_SMP_IDLE_THREAD
32 select GENERIC_STRNCPY_FROM_USER 32 select GENERIC_STRNCPY_FROM_USER
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index 75825b63464d..949c406d4df4 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -36,26 +36,31 @@
36/* 36/*
37 * Generic IO read/write. These perform native-endian accesses. 37 * Generic IO read/write. These perform native-endian accesses.
38 */ 38 */
39#define __raw_writeb __raw_writeb
39static inline void __raw_writeb(u8 val, volatile void __iomem *addr) 40static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
40{ 41{
41 asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr)); 42 asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr));
42} 43}
43 44
45#define __raw_writew __raw_writew
44static inline void __raw_writew(u16 val, volatile void __iomem *addr) 46static inline void __raw_writew(u16 val, volatile void __iomem *addr)
45{ 47{
46 asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr)); 48 asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr));
47} 49}
48 50
51#define __raw_writel __raw_writel
49static inline void __raw_writel(u32 val, volatile void __iomem *addr) 52static inline void __raw_writel(u32 val, volatile void __iomem *addr)
50{ 53{
51 asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr)); 54 asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr));
52} 55}
53 56
57#define __raw_writeq __raw_writeq
54static inline void __raw_writeq(u64 val, volatile void __iomem *addr) 58static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
55{ 59{
56 asm volatile("str %0, [%1]" : : "r" (val), "r" (addr)); 60 asm volatile("str %0, [%1]" : : "r" (val), "r" (addr));
57} 61}
58 62
63#define __raw_readb __raw_readb
59static inline u8 __raw_readb(const volatile void __iomem *addr) 64static inline u8 __raw_readb(const volatile void __iomem *addr)
60{ 65{
61 u8 val; 66 u8 val;
@@ -66,6 +71,7 @@ static inline u8 __raw_readb(const volatile void __iomem *addr)
66 return val; 71 return val;
67} 72}
68 73
74#define __raw_readw __raw_readw
69static inline u16 __raw_readw(const volatile void __iomem *addr) 75static inline u16 __raw_readw(const volatile void __iomem *addr)
70{ 76{
71 u16 val; 77 u16 val;
@@ -77,6 +83,7 @@ static inline u16 __raw_readw(const volatile void __iomem *addr)
77 return val; 83 return val;
78} 84}
79 85
86#define __raw_readl __raw_readl
80static inline u32 __raw_readl(const volatile void __iomem *addr) 87static inline u32 __raw_readl(const volatile void __iomem *addr)
81{ 88{
82 u32 val; 89 u32 val;
@@ -87,6 +94,7 @@ static inline u32 __raw_readl(const volatile void __iomem *addr)
87 return val; 94 return val;
88} 95}
89 96
97#define __raw_readq __raw_readq
90static inline u64 __raw_readq(const volatile void __iomem *addr) 98static inline u64 __raw_readq(const volatile void __iomem *addr)
91{ 99{
92 u64 val; 100 u64 val;
@@ -140,94 +148,6 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
140#define IO_SPACE_LIMIT (SZ_32M - 1) 148#define IO_SPACE_LIMIT (SZ_32M - 1)
141#define PCI_IOBASE ((void __iomem *)(MODULES_VADDR - SZ_32M)) 149#define PCI_IOBASE ((void __iomem *)(MODULES_VADDR - SZ_32M))
142 150
143static inline u8 inb(unsigned long addr)
144{
145 return readb(addr + PCI_IOBASE);
146}
147
148static inline u16 inw(unsigned long addr)
149{
150 return readw(addr + PCI_IOBASE);
151}
152
153static inline u32 inl(unsigned long addr)
154{
155 return readl(addr + PCI_IOBASE);
156}
157
158static inline void outb(u8 b, unsigned long addr)
159{
160 writeb(b, addr + PCI_IOBASE);
161}
162
163static inline void outw(u16 b, unsigned long addr)
164{
165 writew(b, addr + PCI_IOBASE);
166}
167
168static inline void outl(u32 b, unsigned long addr)
169{
170 writel(b, addr + PCI_IOBASE);
171}
172
173#define inb_p(addr) inb(addr)
174#define inw_p(addr) inw(addr)
175#define inl_p(addr) inl(addr)
176
177#define outb_p(x, addr) outb((x), (addr))
178#define outw_p(x, addr) outw((x), (addr))
179#define outl_p(x, addr) outl((x), (addr))
180
181static inline void insb(unsigned long addr, void *buffer, int count)
182{
183 u8 *buf = buffer;
184 while (count--)
185 *buf++ = __raw_readb(addr + PCI_IOBASE);
186}
187
188static inline void insw(unsigned long addr, void *buffer, int count)
189{
190 u16 *buf = buffer;
191 while (count--)
192 *buf++ = __raw_readw(addr + PCI_IOBASE);
193}
194
195static inline void insl(unsigned long addr, void *buffer, int count)
196{
197 u32 *buf = buffer;
198 while (count--)
199 *buf++ = __raw_readl(addr + PCI_IOBASE);
200}
201
202static inline void outsb(unsigned long addr, const void *buffer, int count)
203{
204 const u8 *buf = buffer;
205 while (count--)
206 __raw_writeb(*buf++, addr + PCI_IOBASE);
207}
208
209static inline void outsw(unsigned long addr, const void *buffer, int count)
210{
211 const u16 *buf = buffer;
212 while (count--)
213 __raw_writew(*buf++, addr + PCI_IOBASE);
214}
215
216static inline void outsl(unsigned long addr, const void *buffer, int count)
217{
218 const u32 *buf = buffer;
219 while (count--)
220 __raw_writel(*buf++, addr + PCI_IOBASE);
221}
222
223#define insb_p(port,to,len) insb(port,to,len)
224#define insw_p(port,to,len) insw(port,to,len)
225#define insl_p(port,to,len) insl(port,to,len)
226
227#define outsb_p(port,from,len) outsb(port,from,len)
228#define outsw_p(port,from,len) outsw(port,from,len)
229#define outsl_p(port,from,len) outsl(port,from,len)
230
231/* 151/*
232 * String version of I/O memory access operations. 152 * String version of I/O memory access operations.
233 */ 153 */
@@ -251,18 +171,14 @@ extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
251#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC)) 171#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
252#define iounmap __iounmap 172#define iounmap __iounmap
253 173
254#define ARCH_HAS_IOREMAP_WC
255#include <asm-generic/iomap.h>
256
257/* 174/*
258 * More restrictive address range checking than the default implementation 175 * io{read,write}{16,32}be() macros
259 * (PHYS_OFFSET and PHYS_MASK taken into account).
260 */ 176 */
261#define ARCH_HAS_VALID_PHYS_ADDR_RANGE 177#define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
262extern int valid_phys_addr_range(phys_addr_t addr, size_t size); 178#define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
263extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
264 179
265extern int devmem_is_allowed(unsigned long pfn); 180#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
181#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
266 182
267/* 183/*
268 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 184 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
@@ -275,6 +191,18 @@ extern int devmem_is_allowed(unsigned long pfn);
275 */ 191 */
276#define xlate_dev_kmem_ptr(p) p 192#define xlate_dev_kmem_ptr(p) p
277 193
194#include <asm-generic/io.h>
195
196/*
197 * More restrictive address range checking than the default implementation
198 * (PHYS_OFFSET and PHYS_MASK taken into account).
199 */
200#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
201extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
202extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
203
204extern int devmem_is_allowed(unsigned long pfn);
205
278struct bio_vec; 206struct bio_vec;
279extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, 207extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
280 const struct bio_vec *vec2); 208 const struct bio_vec *vec2);
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index a62cd077457b..6486b2bfd562 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -120,11 +120,13 @@ extern phys_addr_t memstart_addr;
120 * translation for translating DMA addresses. Use the driver 120 * translation for translating DMA addresses. Use the driver
121 * DMA support - see dma-mapping.h. 121 * DMA support - see dma-mapping.h.
122 */ 122 */
123#define virt_to_phys virt_to_phys
123static inline phys_addr_t virt_to_phys(const volatile void *x) 124static inline phys_addr_t virt_to_phys(const volatile void *x)
124{ 125{
125 return __virt_to_phys((unsigned long)(x)); 126 return __virt_to_phys((unsigned long)(x));
126} 127}
127 128
129#define phys_to_virt phys_to_virt
128static inline void *phys_to_virt(phys_addr_t x) 130static inline void *phys_to_virt(phys_addr_t x)
129{ 131{
130 return (void *)(__phys_to_virt(x)); 132 return (void *)(__phys_to_virt(x));
diff --git a/arch/cris/include/asm/io.h b/arch/cris/include/asm/io.h
index e59dba12ce94..752a3f45df60 100644
--- a/arch/cris/include/asm/io.h
+++ b/arch/cris/include/asm/io.h
@@ -112,6 +112,9 @@ static inline void writel(unsigned int b, volatile void __iomem *addr)
112 else 112 else
113 *(volatile unsigned int __force *) addr = b; 113 *(volatile unsigned int __force *) addr = b;
114} 114}
115#define writeb_relaxed(b, addr) writeb(b, addr)
116#define writew_relaxed(b, addr) writew(b, addr)
117#define writel_relaxed(b, addr) writel(b, addr)
115#define __raw_writeb writeb 118#define __raw_writeb writeb
116#define __raw_writew writew 119#define __raw_writew writew
117#define __raw_writel writel 120#define __raw_writel writel
diff --git a/arch/frv/include/asm/io.h b/arch/frv/include/asm/io.h
index 8cb50a2fbcb2..99bb7efaf9b7 100644
--- a/arch/frv/include/asm/io.h
+++ b/arch/frv/include/asm/io.h
@@ -243,6 +243,9 @@ static inline void writel(uint32_t datum, volatile void __iomem *addr)
243 __flush_PCI_writes(); 243 __flush_PCI_writes();
244} 244}
245 245
246#define writeb_relaxed writeb
247#define writew_relaxed writew
248#define writel_relaxed writel
246 249
247/* Values for nocacheflag and cmode */ 250/* Values for nocacheflag and cmode */
248#define IOMAP_FULL_CACHING 0 251#define IOMAP_FULL_CACHING 0
diff --git a/arch/ia64/include/asm/io.h b/arch/ia64/include/asm/io.h
index bee0acd52f7e..80a7e34be009 100644
--- a/arch/ia64/include/asm/io.h
+++ b/arch/ia64/include/asm/io.h
@@ -393,6 +393,10 @@ __writeq (unsigned long val, volatile void __iomem *addr)
393#define writew(v,a) __writew((v), (a)) 393#define writew(v,a) __writew((v), (a))
394#define writel(v,a) __writel((v), (a)) 394#define writel(v,a) __writel((v), (a))
395#define writeq(v,a) __writeq((v), (a)) 395#define writeq(v,a) __writeq((v), (a))
396#define writeb_relaxed(v,a) __writeb((v), (a))
397#define writew_relaxed(v,a) __writew((v), (a))
398#define writel_relaxed(v,a) __writel((v), (a))
399#define writeq_relaxed(v,a) __writeq((v), (a))
396#define __raw_writeb writeb 400#define __raw_writeb writeb
397#define __raw_writew writew 401#define __raw_writew writew
398#define __raw_writel writel 402#define __raw_writel writel
diff --git a/arch/ia64/include/asm/uaccess.h b/arch/ia64/include/asm/uaccess.h
index 449c8c0fa2bd..103bedc59644 100644
--- a/arch/ia64/include/asm/uaccess.h
+++ b/arch/ia64/include/asm/uaccess.h
@@ -365,15 +365,15 @@ ia64_done_with_exception (struct pt_regs *regs)
365} 365}
366 366
367#define ARCH_HAS_TRANSLATE_MEM_PTR 1 367#define ARCH_HAS_TRANSLATE_MEM_PTR 1
368static __inline__ char * 368static __inline__ void *
369xlate_dev_mem_ptr (unsigned long p) 369xlate_dev_mem_ptr(phys_addr_t p)
370{ 370{
371 struct page *page; 371 struct page *page;
372 char * ptr; 372 void *ptr;
373 373
374 page = pfn_to_page(p >> PAGE_SHIFT); 374 page = pfn_to_page(p >> PAGE_SHIFT);
375 if (PageUncached(page)) 375 if (PageUncached(page))
376 ptr = (char *)p + __IA64_UNCACHED_OFFSET; 376 ptr = (void *)p + __IA64_UNCACHED_OFFSET;
377 else 377 else
378 ptr = __va(p); 378 ptr = __va(p);
379 379
@@ -383,15 +383,15 @@ xlate_dev_mem_ptr (unsigned long p)
383/* 383/*
384 * Convert a virtual cached kernel memory pointer to an uncached pointer 384 * Convert a virtual cached kernel memory pointer to an uncached pointer
385 */ 385 */
386static __inline__ char * 386static __inline__ void *
387xlate_dev_kmem_ptr (char * p) 387xlate_dev_kmem_ptr(void *p)
388{ 388{
389 struct page *page; 389 struct page *page;
390 char * ptr; 390 void *ptr;
391 391
392 page = virt_to_page((unsigned long)p); 392 page = virt_to_page((unsigned long)p);
393 if (PageUncached(page)) 393 if (PageUncached(page))
394 ptr = (char *)__pa(p) + __IA64_UNCACHED_OFFSET; 394 ptr = (void *)__pa(p) + __IA64_UNCACHED_OFFSET;
395 else 395 else
396 ptr = p; 396 ptr = p;
397 397
diff --git a/arch/m32r/include/asm/io.h b/arch/m32r/include/asm/io.h
index 4010f1fc5b65..6e7787f3dac7 100644
--- a/arch/m32r/include/asm/io.h
+++ b/arch/m32r/include/asm/io.h
@@ -161,6 +161,9 @@ static inline void _writel(unsigned long l, unsigned long addr)
161#define __raw_writeb writeb 161#define __raw_writeb writeb
162#define __raw_writew writew 162#define __raw_writew writew
163#define __raw_writel writel 163#define __raw_writel writel
164#define writeb_relaxed writeb
165#define writew_relaxed writew
166#define writel_relaxed writel
164 167
165#define ioread8 read 168#define ioread8 read
166#define ioread16 readw 169#define ioread16 readw
diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h
index c70cc9155003..bccd5a914eb6 100644
--- a/arch/m68k/include/asm/io.h
+++ b/arch/m68k/include/asm/io.h
@@ -3,3 +3,11 @@
3#else 3#else
4#include <asm/io_mm.h> 4#include <asm/io_mm.h>
5#endif 5#endif
6
7#define readb_relaxed(addr) readb(addr)
8#define readw_relaxed(addr) readw(addr)
9#define readl_relaxed(addr) readl(addr)
10
11#define writeb_relaxed(b, addr) writeb(b, addr)
12#define writew_relaxed(b, addr) writew(b, addr)
13#define writel_relaxed(b, addr) writel(b, addr)
diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h
index be4b5a813ad4..a93c8cde4d38 100644
--- a/arch/m68k/include/asm/io_no.h
+++ b/arch/m68k/include/asm/io_no.h
@@ -40,10 +40,6 @@ static inline unsigned int _swapl(volatile unsigned long v)
40#define readl(addr) \ 40#define readl(addr) \
41 ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; }) 41 ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
42 42
43#define readb_relaxed(addr) readb(addr)
44#define readw_relaxed(addr) readw(addr)
45#define readl_relaxed(addr) readl(addr)
46
47#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b)) 43#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
48#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b)) 44#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
49#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b)) 45#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index 433751b2a003..940f5fc1d1da 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -69,12 +69,4 @@ extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
69 69
70#include <asm-generic/io.h> 70#include <asm-generic/io.h>
71 71
72#define readb_relaxed readb
73#define readw_relaxed readw
74#define readl_relaxed readl
75
76#define writeb_relaxed writeb
77#define writew_relaxed writew
78#define writel_relaxed writel
79
80#endif /* _ASM_MICROBLAZE_IO_H */ 72#endif /* _ASM_MICROBLAZE_IO_H */
diff --git a/arch/mn10300/include/asm/io.h b/arch/mn10300/include/asm/io.h
index e6ed0d897ccc..897ba3c12b32 100644
--- a/arch/mn10300/include/asm/io.h
+++ b/arch/mn10300/include/asm/io.h
@@ -67,6 +67,10 @@ static inline void writel(u32 b, volatile void __iomem *addr)
67#define __raw_writew writew 67#define __raw_writew writew
68#define __raw_writel writel 68#define __raw_writel writel
69 69
70#define writeb_relaxed writeb
71#define writew_relaxed writew
72#define writel_relaxed writel
73
70/*****************************************************************************/ 74/*****************************************************************************/
71/* 75/*
72 * traditional input/output functions 76 * traditional input/output functions
diff --git a/arch/parisc/include/asm/io.h b/arch/parisc/include/asm/io.h
index 1f6d2ae7aba5..8cd0abf28ffb 100644
--- a/arch/parisc/include/asm/io.h
+++ b/arch/parisc/include/asm/io.h
@@ -217,10 +217,14 @@ static inline void writeq(unsigned long long q, volatile void __iomem *addr)
217#define writel writel 217#define writel writel
218#define writeq writeq 218#define writeq writeq
219 219
220#define readb_relaxed(addr) readb(addr) 220#define readb_relaxed(addr) readb(addr)
221#define readw_relaxed(addr) readw(addr) 221#define readw_relaxed(addr) readw(addr)
222#define readl_relaxed(addr) readl(addr) 222#define readl_relaxed(addr) readl(addr)
223#define readq_relaxed(addr) readq(addr) 223#define readq_relaxed(addr) readq(addr)
224#define writeb_relaxed(b, addr) writeb(b, addr)
225#define writew_relaxed(w, addr) writew(w, addr)
226#define writel_relaxed(l, addr) writel(l, addr)
227#define writeq_relaxed(q, addr) writeq(q, addr)
224 228
225#define mmiowb() do { } while (0) 229#define mmiowb() do { } while (0)
226 230
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 97d3869991ca..9eaf301ac952 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -617,10 +617,14 @@ static inline void name at \
617/* 617/*
618 * We don't do relaxed operations yet, at least not with this semantic 618 * We don't do relaxed operations yet, at least not with this semantic
619 */ 619 */
620#define readb_relaxed(addr) readb(addr) 620#define readb_relaxed(addr) readb(addr)
621#define readw_relaxed(addr) readw(addr) 621#define readw_relaxed(addr) readw(addr)
622#define readl_relaxed(addr) readl(addr) 622#define readl_relaxed(addr) readl(addr)
623#define readq_relaxed(addr) readq(addr) 623#define readq_relaxed(addr) readq(addr)
624#define writeb_relaxed(v, addr) writeb(v, addr)
625#define writew_relaxed(v, addr) writew(v, addr)
626#define writel_relaxed(v, addr) writel(v, addr)
627#define writeq_relaxed(v, addr) writeq(v, addr)
624 628
625#ifdef CONFIG_PPC32 629#ifdef CONFIG_PPC32
626#define mmiowb() 630#define mmiowb()
diff --git a/arch/s390/include/asm/io.h b/arch/s390/include/asm/io.h
index cd6b9ee7b69c..6ad9013c67e7 100644
--- a/arch/s390/include/asm/io.h
+++ b/arch/s390/include/asm/io.h
@@ -13,9 +13,10 @@
13#include <asm/page.h> 13#include <asm/page.h>
14#include <asm/pci_io.h> 14#include <asm/pci_io.h>
15 15
16void *xlate_dev_mem_ptr(unsigned long phys);
17#define xlate_dev_mem_ptr xlate_dev_mem_ptr 16#define xlate_dev_mem_ptr xlate_dev_mem_ptr
18void unxlate_dev_mem_ptr(unsigned long phys, void *addr); 17void *xlate_dev_mem_ptr(phys_addr_t phys);
18#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
19void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
19 20
20/* 21/*
21 * Convert a virtual cached pointer to an uncached pointer 22 * Convert a virtual cached pointer to an uncached pointer
@@ -60,11 +61,6 @@ static inline void iounmap(volatile void __iomem *addr)
60#define __raw_writel zpci_write_u32 61#define __raw_writel zpci_write_u32
61#define __raw_writeq zpci_write_u64 62#define __raw_writeq zpci_write_u64
62 63
63#define readb_relaxed readb
64#define readw_relaxed readw
65#define readl_relaxed readl
66#define readq_relaxed readq
67
68#endif /* CONFIG_PCI */ 64#endif /* CONFIG_PCI */
69 65
70#include <asm-generic/io.h> 66#include <asm-generic/io.h>
diff --git a/arch/s390/mm/maccess.c b/arch/s390/mm/maccess.c
index 2a2e35416d2f..2eb34bdfc613 100644
--- a/arch/s390/mm/maccess.c
+++ b/arch/s390/mm/maccess.c
@@ -176,7 +176,7 @@ static int is_swapped(unsigned long addr)
176 * For swapped prefix pages a new buffer is returned that contains a copy of 176 * For swapped prefix pages a new buffer is returned that contains a copy of
177 * the absolute memory. The buffer size is maximum one page large. 177 * the absolute memory. The buffer size is maximum one page large.
178 */ 178 */
179void *xlate_dev_mem_ptr(unsigned long addr) 179void *xlate_dev_mem_ptr(phys_addr_t addr)
180{ 180{
181 void *bounce = (void *) addr; 181 void *bounce = (void *) addr;
182 unsigned long size; 182 unsigned long size;
@@ -197,7 +197,7 @@ void *xlate_dev_mem_ptr(unsigned long addr)
197/* 197/*
198 * Free converted buffer for /dev/mem access (if necessary) 198 * Free converted buffer for /dev/mem access (if necessary)
199 */ 199 */
200void unxlate_dev_mem_ptr(unsigned long addr, void *buf) 200void unxlate_dev_mem_ptr(phys_addr_t addr, void *buf)
201{ 201{
202 if ((void *) addr != buf) 202 if ((void *) addr != buf)
203 free_page((unsigned long) buf); 203 free_page((unsigned long) buf);
diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index 9f532902627c..407ac14295f4 100644
--- a/arch/sparc/include/asm/io_32.h
+++ b/arch/sparc/include/asm/io_32.h
@@ -4,10 +4,6 @@
4#include <linux/kernel.h> 4#include <linux/kernel.h>
5#include <linux/ioport.h> /* struct resource */ 5#include <linux/ioport.h> /* struct resource */
6 6
7#define readb_relaxed(__addr) readb(__addr)
8#define readw_relaxed(__addr) readw(__addr)
9#define readl_relaxed(__addr) readl(__addr)
10
11#define IO_SPACE_LIMIT 0xffffffff 7#define IO_SPACE_LIMIT 0xffffffff
12 8
13#define memset_io(d,c,sz) _memset_io(d,c,sz) 9#define memset_io(d,c,sz) _memset_io(d,c,sz)
diff --git a/arch/sparc/include/asm/io_64.h b/arch/sparc/include/asm/io_64.h
index 80b54b326d49..9b672be70dda 100644
--- a/arch/sparc/include/asm/io_64.h
+++ b/arch/sparc/include/asm/io_64.h
@@ -101,6 +101,7 @@ static inline void __raw_writeq(u64 q, const volatile void __iomem *addr)
101 * the cache by using ASI_PHYS_BYPASS_EC_E_L 101 * the cache by using ASI_PHYS_BYPASS_EC_E_L
102 */ 102 */
103#define readb readb 103#define readb readb
104#define readb_relaxed readb
104static inline u8 readb(const volatile void __iomem *addr) 105static inline u8 readb(const volatile void __iomem *addr)
105{ u8 ret; 106{ u8 ret;
106 107
@@ -112,6 +113,7 @@ static inline u8 readb(const volatile void __iomem *addr)
112} 113}
113 114
114#define readw readw 115#define readw readw
116#define readw_relaxed readw
115static inline u16 readw(const volatile void __iomem *addr) 117static inline u16 readw(const volatile void __iomem *addr)
116{ u16 ret; 118{ u16 ret;
117 119
@@ -124,6 +126,7 @@ static inline u16 readw(const volatile void __iomem *addr)
124} 126}
125 127
126#define readl readl 128#define readl readl
129#define readl_relaxed readl
127static inline u32 readl(const volatile void __iomem *addr) 130static inline u32 readl(const volatile void __iomem *addr)
128{ u32 ret; 131{ u32 ret;
129 132
@@ -136,6 +139,7 @@ static inline u32 readl(const volatile void __iomem *addr)
136} 139}
137 140
138#define readq readq 141#define readq readq
142#define readq_relaxed readq
139static inline u64 readq(const volatile void __iomem *addr) 143static inline u64 readq(const volatile void __iomem *addr)
140{ u64 ret; 144{ u64 ret;
141 145
@@ -148,6 +152,7 @@ static inline u64 readq(const volatile void __iomem *addr)
148} 152}
149 153
150#define writeb writeb 154#define writeb writeb
155#define writeb_relaxed writeb
151static inline void writeb(u8 b, volatile void __iomem *addr) 156static inline void writeb(u8 b, volatile void __iomem *addr)
152{ 157{
153 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */" 158 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
@@ -157,6 +162,7 @@ static inline void writeb(u8 b, volatile void __iomem *addr)
157} 162}
158 163
159#define writew writew 164#define writew writew
165#define writew_relaxed writew
160static inline void writew(u16 w, volatile void __iomem *addr) 166static inline void writew(u16 w, volatile void __iomem *addr)
161{ 167{
162 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */" 168 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
@@ -166,6 +172,7 @@ static inline void writew(u16 w, volatile void __iomem *addr)
166} 172}
167 173
168#define writel writel 174#define writel writel
175#define writel_relaxed writel
169static inline void writel(u32 l, volatile void __iomem *addr) 176static inline void writel(u32 l, volatile void __iomem *addr)
170{ 177{
171 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */" 178 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
@@ -175,6 +182,7 @@ static inline void writel(u32 l, volatile void __iomem *addr)
175} 182}
176 183
177#define writeq writeq 184#define writeq writeq
185#define writeq_relaxed writeq
178static inline void writeq(u64 q, volatile void __iomem *addr) 186static inline void writeq(u64 q, volatile void __iomem *addr)
179{ 187{
180 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */" 188 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
@@ -183,7 +191,6 @@ static inline void writeq(u64 q, volatile void __iomem *addr)
183 : "memory"); 191 : "memory");
184} 192}
185 193
186
187#define inb inb 194#define inb inb
188static inline u8 inb(unsigned long addr) 195static inline u8 inb(unsigned long addr)
189{ 196{
@@ -264,11 +271,6 @@ static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned l
264 outsl((unsigned long __force)port, buf, count); 271 outsl((unsigned long __force)port, buf, count);
265} 272}
266 273
267#define readb_relaxed(__addr) readb(__addr)
268#define readw_relaxed(__addr) readw(__addr)
269#define readl_relaxed(__addr) readl(__addr)
270#define readq_relaxed(__addr) readq(__addr)
271
272/* Valid I/O Space regions are anywhere, because each PCI bus supported 274/* Valid I/O Space regions are anywhere, because each PCI bus supported
273 * can live in an arbitrary area of the physical address range. 275 * can live in an arbitrary area of the physical address range.
274 */ 276 */
diff --git a/arch/tile/include/asm/io.h b/arch/tile/include/asm/io.h
index 9fe434969fab..d372641054d9 100644
--- a/arch/tile/include/asm/io.h
+++ b/arch/tile/include/asm/io.h
@@ -241,6 +241,10 @@ static inline void writeq(u64 val, unsigned long addr)
241#define readw_relaxed readw 241#define readw_relaxed readw
242#define readl_relaxed readl 242#define readl_relaxed readl
243#define readq_relaxed readq 243#define readq_relaxed readq
244#define writeb_relaxed writeb
245#define writew_relaxed writew
246#define writel_relaxed writel
247#define writeq_relaxed writeq
244 248
245#define ioread8 readb 249#define ioread8 readb
246#define ioread16 readw 250#define ioread16 readw
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index b8237d8a1e0c..0cdbe6e81b45 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -74,6 +74,9 @@ build_mmio_write(__writel, "l", unsigned int, "r", )
74#define __raw_readw __readw 74#define __raw_readw __readw
75#define __raw_readl __readl 75#define __raw_readl __readl
76 76
77#define writeb_relaxed(v, a) __writeb(v, a)
78#define writew_relaxed(v, a) __writew(v, a)
79#define writel_relaxed(v, a) __writel(v, a)
77#define __raw_writeb __writeb 80#define __raw_writeb __writeb
78#define __raw_writew __writew 81#define __raw_writew __writew
79#define __raw_writel __writel 82#define __raw_writel __writel
@@ -86,6 +89,7 @@ build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
86build_mmio_write(writeq, "q", unsigned long, "r", :"memory") 89build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
87 90
88#define readq_relaxed(a) readq(a) 91#define readq_relaxed(a) readq(a)
92#define writeq_relaxed(v, a) writeq(v, a)
89 93
90#define __raw_readq(a) readq(a) 94#define __raw_readq(a) readq(a)
91#define __raw_writeq(val, addr) writeq(val, addr) 95#define __raw_writeq(val, addr) writeq(val, addr)
@@ -310,8 +314,8 @@ BUILDIO(b, b, char)
310BUILDIO(w, w, short) 314BUILDIO(w, w, short)
311BUILDIO(l, , int) 315BUILDIO(l, , int)
312 316
313extern void *xlate_dev_mem_ptr(unsigned long phys); 317extern void *xlate_dev_mem_ptr(phys_addr_t phys);
314extern void unxlate_dev_mem_ptr(unsigned long phys, void *addr); 318extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
315 319
316extern int ioremap_change_attr(unsigned long vaddr, unsigned long size, 320extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
317 unsigned long prot_val); 321 unsigned long prot_val);
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index af78e50ca6ce..b12f43c192cf 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -327,7 +327,7 @@ EXPORT_SYMBOL(iounmap);
327 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 327 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
328 * access 328 * access
329 */ 329 */
330void *xlate_dev_mem_ptr(unsigned long phys) 330void *xlate_dev_mem_ptr(phys_addr_t phys)
331{ 331{
332 void *addr; 332 void *addr;
333 unsigned long start = phys & PAGE_MASK; 333 unsigned long start = phys & PAGE_MASK;
@@ -343,7 +343,7 @@ void *xlate_dev_mem_ptr(unsigned long phys)
343 return addr; 343 return addr;
344} 344}
345 345
346void unxlate_dev_mem_ptr(unsigned long phys, void *addr) 346void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)
347{ 347{
348 if (page_is_ram(phys >> PAGE_SHIFT)) 348 if (page_is_ram(phys >> PAGE_SHIFT))
349 return; 349 return;
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index 74944207167e..fe1600a09438 100644
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -74,13 +74,6 @@ static inline void iounmap(volatile void __iomem *addr)
74 74
75#endif /* CONFIG_MMU */ 75#endif /* CONFIG_MMU */
76 76
77/*
78 * Generic I/O
79 */
80#define readb_relaxed readb
81#define readw_relaxed readw
82#define readl_relaxed readl
83
84#endif /* __KERNEL__ */ 77#endif /* __KERNEL__ */
85 78
86#include <asm-generic/io.h> 79#include <asm-generic/io.h>
diff --git a/drivers/char/mem.c b/drivers/char/mem.c
index 524b707894ef..4c58333b4257 100644
--- a/drivers/char/mem.c
+++ b/drivers/char/mem.c
@@ -84,9 +84,12 @@ static inline int range_is_allowed(unsigned long pfn, unsigned long size)
84} 84}
85#endif 85#endif
86 86
87void __weak unxlate_dev_mem_ptr(unsigned long phys, void *addr) 87#ifndef unxlate_dev_mem_ptr
88#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
89void __weak unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)
88{ 90{
89} 91}
92#endif
90 93
91/* 94/*
92 * This funcion reads the *physical* memory. The f_pos points directly to the 95 * This funcion reads the *physical* memory. The f_pos points directly to the
@@ -97,7 +100,7 @@ static ssize_t read_mem(struct file *file, char __user *buf,
97{ 100{
98 phys_addr_t p = *ppos; 101 phys_addr_t p = *ppos;
99 ssize_t read, sz; 102 ssize_t read, sz;
100 char *ptr; 103 void *ptr;
101 104
102 if (p != *ppos) 105 if (p != *ppos)
103 return 0; 106 return 0;
@@ -400,7 +403,7 @@ static ssize_t read_kmem(struct file *file, char __user *buf,
400 * uncached, then it must also be accessed uncached 403 * uncached, then it must also be accessed uncached
401 * by the kernel or data corruption may occur 404 * by the kernel or data corruption may occur
402 */ 405 */
403 kbuf = xlate_dev_kmem_ptr((char *)p); 406 kbuf = xlate_dev_kmem_ptr((void *)p);
404 407
405 if (copy_to_user(buf, kbuf, sz)) 408 if (copy_to_user(buf, kbuf, sz))
406 return -EFAULT; 409 return -EFAULT;
@@ -461,7 +464,7 @@ static ssize_t do_write_kmem(unsigned long p, const char __user *buf,
461#endif 464#endif
462 465
463 while (count > 0) { 466 while (count > 0) {
464 char *ptr; 467 void *ptr;
465 468
466 sz = size_inside_page(p, count); 469 sz = size_inside_page(p, count);
467 470
@@ -470,7 +473,7 @@ static ssize_t do_write_kmem(unsigned long p, const char __user *buf,
470 * it must also be accessed uncached by the kernel or data 473 * it must also be accessed uncached by the kernel or data
471 * corruption may occur. 474 * corruption may occur.
472 */ 475 */
473 ptr = xlate_dev_kmem_ptr((char *)p); 476 ptr = xlate_dev_kmem_ptr((void *)p);
474 477
475 copied = copy_from_user(ptr, buf, sz); 478 copied = copy_from_user(ptr, buf, sz);
476 if (copied) { 479 if (copied) {
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index b8fdc57a7335..9db042304df3 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -12,6 +12,7 @@
12#define __ASM_GENERIC_IO_H 12#define __ASM_GENERIC_IO_H
13 13
14#include <asm/page.h> /* I/O is all done through memory accesses */ 14#include <asm/page.h> /* I/O is all done through memory accesses */
15#include <linux/string.h> /* for memset() and memcpy() */
15#include <linux/types.h> 16#include <linux/types.h>
16 17
17#ifdef CONFIG_GENERIC_IOMAP 18#ifdef CONFIG_GENERIC_IOMAP
@@ -24,260 +25,691 @@
24#define mmiowb() do {} while (0) 25#define mmiowb() do {} while (0)
25#endif 26#endif
26 27
27/*****************************************************************************/
28/* 28/*
29 * readX/writeX() are used to access memory mapped devices. On some 29 * __raw_{read,write}{b,w,l,q}() access memory in native endianness.
30 * architectures the memory mapped IO stuff needs to be accessed 30 *
31 * differently. On the simple architectures, we just read/write the 31 * On some architectures memory mapped IO needs to be accessed differently.
32 * memory location directly. 32 * On the simple architectures, we just read/write the memory location
33 * directly.
33 */ 34 */
35
34#ifndef __raw_readb 36#ifndef __raw_readb
37#define __raw_readb __raw_readb
35static inline u8 __raw_readb(const volatile void __iomem *addr) 38static inline u8 __raw_readb(const volatile void __iomem *addr)
36{ 39{
37 return *(const volatile u8 __force *) addr; 40 return *(const volatile u8 __force *)addr;
38} 41}
39#endif 42#endif
40 43
41#ifndef __raw_readw 44#ifndef __raw_readw
45#define __raw_readw __raw_readw
42static inline u16 __raw_readw(const volatile void __iomem *addr) 46static inline u16 __raw_readw(const volatile void __iomem *addr)
43{ 47{
44 return *(const volatile u16 __force *) addr; 48 return *(const volatile u16 __force *)addr;
45} 49}
46#endif 50#endif
47 51
48#ifndef __raw_readl 52#ifndef __raw_readl
53#define __raw_readl __raw_readl
49static inline u32 __raw_readl(const volatile void __iomem *addr) 54static inline u32 __raw_readl(const volatile void __iomem *addr)
50{ 55{
51 return *(const volatile u32 __force *) addr; 56 return *(const volatile u32 __force *)addr;
52} 57}
53#endif 58#endif
54 59
55#define readb __raw_readb 60#ifdef CONFIG_64BIT
56 61#ifndef __raw_readq
57#define readw readw 62#define __raw_readq __raw_readq
58static inline u16 readw(const volatile void __iomem *addr) 63static inline u64 __raw_readq(const volatile void __iomem *addr)
59{
60 return __le16_to_cpu(__raw_readw(addr));
61}
62
63#define readl readl
64static inline u32 readl(const volatile void __iomem *addr)
65{ 64{
66 return __le32_to_cpu(__raw_readl(addr)); 65 return *(const volatile u64 __force *)addr;
67} 66}
67#endif
68#endif /* CONFIG_64BIT */
68 69
69#ifndef __raw_writeb 70#ifndef __raw_writeb
70static inline void __raw_writeb(u8 b, volatile void __iomem *addr) 71#define __raw_writeb __raw_writeb
72static inline void __raw_writeb(u8 value, volatile void __iomem *addr)
71{ 73{
72 *(volatile u8 __force *) addr = b; 74 *(volatile u8 __force *)addr = value;
73} 75}
74#endif 76#endif
75 77
76#ifndef __raw_writew 78#ifndef __raw_writew
77static inline void __raw_writew(u16 b, volatile void __iomem *addr) 79#define __raw_writew __raw_writew
80static inline void __raw_writew(u16 value, volatile void __iomem *addr)
78{ 81{
79 *(volatile u16 __force *) addr = b; 82 *(volatile u16 __force *)addr = value;
80} 83}
81#endif 84#endif
82 85
83#ifndef __raw_writel 86#ifndef __raw_writel
84static inline void __raw_writel(u32 b, volatile void __iomem *addr) 87#define __raw_writel __raw_writel
88static inline void __raw_writel(u32 value, volatile void __iomem *addr)
85{ 89{
86 *(volatile u32 __force *) addr = b; 90 *(volatile u32 __force *)addr = value;
87} 91}
88#endif 92#endif
89 93
90#define writeb __raw_writeb
91#define writew(b,addr) __raw_writew(__cpu_to_le16(b),addr)
92#define writel(b,addr) __raw_writel(__cpu_to_le32(b),addr)
93
94#ifdef CONFIG_64BIT 94#ifdef CONFIG_64BIT
95#ifndef __raw_readq 95#ifndef __raw_writeq
96static inline u64 __raw_readq(const volatile void __iomem *addr) 96#define __raw_writeq __raw_writeq
97static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
97{ 98{
98 return *(const volatile u64 __force *) addr; 99 *(volatile u64 __force *)addr = value;
99} 100}
100#endif 101#endif
102#endif /* CONFIG_64BIT */
101 103
102#define readq readq 104/*
103static inline u64 readq(const volatile void __iomem *addr) 105 * {read,write}{b,w,l,q}() access little endian memory and return result in
104{ 106 * native endianness.
105 return __le64_to_cpu(__raw_readq(addr)); 107 */
106}
107 108
108#ifndef __raw_writeq 109#ifndef readb
109static inline void __raw_writeq(u64 b, volatile void __iomem *addr) 110#define readb readb
111static inline u8 readb(const volatile void __iomem *addr)
110{ 112{
111 *(volatile u64 __force *) addr = b; 113 return __raw_readb(addr);
112} 114}
113#endif 115#endif
114 116
115#define writeq(b, addr) __raw_writeq(__cpu_to_le64(b), addr) 117#ifndef readw
116#endif /* CONFIG_64BIT */ 118#define readw readw
117 119static inline u16 readw(const volatile void __iomem *addr)
118#ifndef PCI_IOBASE 120{
119#define PCI_IOBASE ((void __iomem *) 0) 121 return __le16_to_cpu(__raw_readw(addr));
122}
120#endif 123#endif
121 124
122/*****************************************************************************/ 125#ifndef readl
123/* 126#define readl readl
124 * traditional input/output functions 127static inline u32 readl(const volatile void __iomem *addr)
125 */
126
127static inline u8 inb(unsigned long addr)
128{ 128{
129 return readb(addr + PCI_IOBASE); 129 return __le32_to_cpu(__raw_readl(addr));
130} 130}
131#endif
131 132
132static inline u16 inw(unsigned long addr) 133#ifdef CONFIG_64BIT
134#ifndef readq
135#define readq readq
136static inline u64 readq(const volatile void __iomem *addr)
133{ 137{
134 return readw(addr + PCI_IOBASE); 138 return __le64_to_cpu(__raw_readq(addr));
135} 139}
140#endif
141#endif /* CONFIG_64BIT */
136 142
137static inline u32 inl(unsigned long addr) 143#ifndef writeb
144#define writeb writeb
145static inline void writeb(u8 value, volatile void __iomem *addr)
138{ 146{
139 return readl(addr + PCI_IOBASE); 147 __raw_writeb(value, addr);
140} 148}
149#endif
141 150
142static inline void outb(u8 b, unsigned long addr) 151#ifndef writew
152#define writew writew
153static inline void writew(u16 value, volatile void __iomem *addr)
143{ 154{
144 writeb(b, addr + PCI_IOBASE); 155 __raw_writew(cpu_to_le16(value), addr);
145} 156}
157#endif
146 158
147static inline void outw(u16 b, unsigned long addr) 159#ifndef writel
160#define writel writel
161static inline void writel(u32 value, volatile void __iomem *addr)
148{ 162{
149 writew(b, addr + PCI_IOBASE); 163 __raw_writel(__cpu_to_le32(value), addr);
150} 164}
165#endif
151 166
152static inline void outl(u32 b, unsigned long addr) 167#ifdef CONFIG_64BIT
168#ifndef writeq
169#define writeq writeq
170static inline void writeq(u64 value, volatile void __iomem *addr)
153{ 171{
154 writel(b, addr + PCI_IOBASE); 172 __raw_writeq(__cpu_to_le64(value), addr);
155} 173}
174#endif
175#endif /* CONFIG_64BIT */
176
177/*
178 * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
179 * are not guaranteed to provide ordering against spinlocks or memory
180 * accesses.
181 */
182#ifndef readb_relaxed
183#define readb_relaxed readb
184#endif
156 185
157#define inb_p(addr) inb(addr) 186#ifndef readw_relaxed
158#define inw_p(addr) inw(addr) 187#define readw_relaxed readw
159#define inl_p(addr) inl(addr) 188#endif
160#define outb_p(x, addr) outb((x), (addr))
161#define outw_p(x, addr) outw((x), (addr))
162#define outl_p(x, addr) outl((x), (addr))
163 189
164#ifndef insb 190#ifndef readl_relaxed
165static inline void insb(unsigned long addr, void *buffer, int count) 191#define readl_relaxed readl
192#endif
193
194#ifndef readq_relaxed
195#define readq_relaxed readq
196#endif
197
198#ifndef writeb_relaxed
199#define writeb_relaxed writeb
200#endif
201
202#ifndef writew_relaxed
203#define writew_relaxed writew
204#endif
205
206#ifndef writel_relaxed
207#define writel_relaxed writel
208#endif
209
210#ifndef writeq_relaxed
211#define writeq_relaxed writeq
212#endif
213
214/*
215 * {read,write}s{b,w,l,q}() repeatedly access the same memory address in
216 * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times).
217 */
218#ifndef readsb
219#define readsb readsb
220static inline void readsb(const volatile void __iomem *addr, void *buffer,
221 unsigned int count)
166{ 222{
167 if (count) { 223 if (count) {
168 u8 *buf = buffer; 224 u8 *buf = buffer;
225
169 do { 226 do {
170 u8 x = __raw_readb(addr + PCI_IOBASE); 227 u8 x = __raw_readb(addr);
171 *buf++ = x; 228 *buf++ = x;
172 } while (--count); 229 } while (--count);
173 } 230 }
174} 231}
175#endif 232#endif
176 233
177#ifndef insw 234#ifndef readsw
178static inline void insw(unsigned long addr, void *buffer, int count) 235#define readsw readsw
236static inline void readsw(const volatile void __iomem *addr, void *buffer,
237 unsigned int count)
179{ 238{
180 if (count) { 239 if (count) {
181 u16 *buf = buffer; 240 u16 *buf = buffer;
241
182 do { 242 do {
183 u16 x = __raw_readw(addr + PCI_IOBASE); 243 u16 x = __raw_readw(addr);
184 *buf++ = x; 244 *buf++ = x;
185 } while (--count); 245 } while (--count);
186 } 246 }
187} 247}
188#endif 248#endif
189 249
190#ifndef insl 250#ifndef readsl
191static inline void insl(unsigned long addr, void *buffer, int count) 251#define readsl readsl
252static inline void readsl(const volatile void __iomem *addr, void *buffer,
253 unsigned int count)
192{ 254{
193 if (count) { 255 if (count) {
194 u32 *buf = buffer; 256 u32 *buf = buffer;
257
195 do { 258 do {
196 u32 x = __raw_readl(addr + PCI_IOBASE); 259 u32 x = __raw_readl(addr);
197 *buf++ = x; 260 *buf++ = x;
198 } while (--count); 261 } while (--count);
199 } 262 }
200} 263}
201#endif 264#endif
202 265
203#ifndef outsb 266#ifdef CONFIG_64BIT
204static inline void outsb(unsigned long addr, const void *buffer, int count) 267#ifndef readsq
268#define readsq readsq
269static inline void readsq(const volatile void __iomem *addr, void *buffer,
270 unsigned int count)
271{
272 if (count) {
273 u64 *buf = buffer;
274
275 do {
276 u64 x = __raw_readq(addr);
277 *buf++ = x;
278 } while (--count);
279 }
280}
281#endif
282#endif /* CONFIG_64BIT */
283
284#ifndef writesb
285#define writesb writesb
286static inline void writesb(volatile void __iomem *addr, const void *buffer,
287 unsigned int count)
205{ 288{
206 if (count) { 289 if (count) {
207 const u8 *buf = buffer; 290 const u8 *buf = buffer;
291
208 do { 292 do {
209 __raw_writeb(*buf++, addr + PCI_IOBASE); 293 __raw_writeb(*buf++, addr);
210 } while (--count); 294 } while (--count);
211 } 295 }
212} 296}
213#endif 297#endif
214 298
215#ifndef outsw 299#ifndef writesw
216static inline void outsw(unsigned long addr, const void *buffer, int count) 300#define writesw writesw
301static inline void writesw(volatile void __iomem *addr, const void *buffer,
302 unsigned int count)
217{ 303{
218 if (count) { 304 if (count) {
219 const u16 *buf = buffer; 305 const u16 *buf = buffer;
306
220 do { 307 do {
221 __raw_writew(*buf++, addr + PCI_IOBASE); 308 __raw_writew(*buf++, addr);
222 } while (--count); 309 } while (--count);
223 } 310 }
224} 311}
225#endif 312#endif
226 313
227#ifndef outsl 314#ifndef writesl
228static inline void outsl(unsigned long addr, const void *buffer, int count) 315#define writesl writesl
316static inline void writesl(volatile void __iomem *addr, const void *buffer,
317 unsigned int count)
229{ 318{
230 if (count) { 319 if (count) {
231 const u32 *buf = buffer; 320 const u32 *buf = buffer;
321
232 do { 322 do {
233 __raw_writel(*buf++, addr + PCI_IOBASE); 323 __raw_writel(*buf++, addr);
234 } while (--count); 324 } while (--count);
235 } 325 }
236} 326}
237#endif 327#endif
238 328
239#ifndef CONFIG_GENERIC_IOMAP 329#ifdef CONFIG_64BIT
240#define ioread8(addr) readb(addr) 330#ifndef writesq
241#define ioread16(addr) readw(addr) 331#define writesq writesq
242#define ioread16be(addr) __be16_to_cpu(__raw_readw(addr)) 332static inline void writesq(volatile void __iomem *addr, const void *buffer,
243#define ioread32(addr) readl(addr) 333 unsigned int count)
244#define ioread32be(addr) __be32_to_cpu(__raw_readl(addr)) 334{
245 335 if (count) {
246#define iowrite8(v, addr) writeb((v), (addr)) 336 const u64 *buf = buffer;
247#define iowrite16(v, addr) writew((v), (addr)) 337
248#define iowrite16be(v, addr) __raw_writew(__cpu_to_be16(v), addr) 338 do {
249#define iowrite32(v, addr) writel((v), (addr)) 339 __raw_writeq(*buf++, addr);
250#define iowrite32be(v, addr) __raw_writel(__cpu_to_be32(v), addr) 340 } while (--count);
251 341 }
252#define ioread8_rep(p, dst, count) \ 342}
253 insb((unsigned long) (p), (dst), (count)) 343#endif
254#define ioread16_rep(p, dst, count) \ 344#endif /* CONFIG_64BIT */
255 insw((unsigned long) (p), (dst), (count)) 345
256#define ioread32_rep(p, dst, count) \ 346#ifndef PCI_IOBASE
257 insl((unsigned long) (p), (dst), (count)) 347#define PCI_IOBASE ((void __iomem *)0)
258 348#endif
259#define iowrite8_rep(p, src, count) \
260 outsb((unsigned long) (p), (src), (count))
261#define iowrite16_rep(p, src, count) \
262 outsw((unsigned long) (p), (src), (count))
263#define iowrite32_rep(p, src, count) \
264 outsl((unsigned long) (p), (src), (count))
265#endif /* CONFIG_GENERIC_IOMAP */
266 349
267#ifndef IO_SPACE_LIMIT 350#ifndef IO_SPACE_LIMIT
268#define IO_SPACE_LIMIT 0xffff 351#define IO_SPACE_LIMIT 0xffff
269#endif 352#endif
270 353
354/*
355 * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be
356 * implemented on hardware that needs an additional delay for I/O accesses to
357 * take effect.
358 */
359
360#ifndef inb
361#define inb inb
362static inline u8 inb(unsigned long addr)
363{
364 return readb(PCI_IOBASE + addr);
365}
366#endif
367
368#ifndef inw
369#define inw inw
370static inline u16 inw(unsigned long addr)
371{
372 return readw(PCI_IOBASE + addr);
373}
374#endif
375
376#ifndef inl
377#define inl inl
378static inline u32 inl(unsigned long addr)
379{
380 return readl(PCI_IOBASE + addr);
381}
382#endif
383
384#ifndef outb
385#define outb outb
386static inline void outb(u8 value, unsigned long addr)
387{
388 writeb(value, PCI_IOBASE + addr);
389}
390#endif
391
392#ifndef outw
393#define outw outw
394static inline void outw(u16 value, unsigned long addr)
395{
396 writew(value, PCI_IOBASE + addr);
397}
398#endif
399
400#ifndef outl
401#define outl outl
402static inline void outl(u32 value, unsigned long addr)
403{
404 writel(value, PCI_IOBASE + addr);
405}
406#endif
407
408#ifndef inb_p
409#define inb_p inb_p
410static inline u8 inb_p(unsigned long addr)
411{
412 return inb(addr);
413}
414#endif
415
416#ifndef inw_p
417#define inw_p inw_p
418static inline u16 inw_p(unsigned long addr)
419{
420 return inw(addr);
421}
422#endif
423
424#ifndef inl_p
425#define inl_p inl_p
426static inline u32 inl_p(unsigned long addr)
427{
428 return inl(addr);
429}
430#endif
431
432#ifndef outb_p
433#define outb_p outb_p
434static inline void outb_p(u8 value, unsigned long addr)
435{
436 outb(value, addr);
437}
438#endif
439
440#ifndef outw_p
441#define outw_p outw_p
442static inline void outw_p(u16 value, unsigned long addr)
443{
444 outw(value, addr);
445}
446#endif
447
448#ifndef outl_p
449#define outl_p outl_p
450static inline void outl_p(u32 value, unsigned long addr)
451{
452 outl(value, addr);
453}
454#endif
455
456/*
457 * {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a
458 * single I/O port multiple times.
459 */
460
461#ifndef insb
462#define insb insb
463static inline void insb(unsigned long addr, void *buffer, unsigned int count)
464{
465 readsb(PCI_IOBASE + addr, buffer, count);
466}
467#endif
468
469#ifndef insw
470#define insw insw
471static inline void insw(unsigned long addr, void *buffer, unsigned int count)
472{
473 readsw(PCI_IOBASE + addr, buffer, count);
474}
475#endif
476
477#ifndef insl
478#define insl insl
479static inline void insl(unsigned long addr, void *buffer, unsigned int count)
480{
481 readsl(PCI_IOBASE + addr, buffer, count);
482}
483#endif
484
485#ifndef outsb
486#define outsb outsb
487static inline void outsb(unsigned long addr, const void *buffer,
488 unsigned int count)
489{
490 writesb(PCI_IOBASE + addr, buffer, count);
491}
492#endif
493
494#ifndef outsw
495#define outsw outsw
496static inline void outsw(unsigned long addr, const void *buffer,
497 unsigned int count)
498{
499 writesw(PCI_IOBASE + addr, buffer, count);
500}
501#endif
502
503#ifndef outsl
504#define outsl outsl
505static inline void outsl(unsigned long addr, const void *buffer,
506 unsigned int count)
507{
508 writesl(PCI_IOBASE + addr, buffer, count);
509}
510#endif
511
512#ifndef insb_p
513#define insb_p insb_p
514static inline void insb_p(unsigned long addr, void *buffer, unsigned int count)
515{
516 insb(addr, buffer, count);
517}
518#endif
519
520#ifndef insw_p
521#define insw_p insw_p
522static inline void insw_p(unsigned long addr, void *buffer, unsigned int count)
523{
524 insw(addr, buffer, count);
525}
526#endif
527
528#ifndef insl_p
529#define insl_p insl_p
530static inline void insl_p(unsigned long addr, void *buffer, unsigned int count)
531{
532 insl(addr, buffer, count);
533}
534#endif
535
536#ifndef outsb_p
537#define outsb_p outsb_p
538static inline void outsb_p(unsigned long addr, const void *buffer,
539 unsigned int count)
540{
541 outsb(addr, buffer, count);
542}
543#endif
544
545#ifndef outsw_p
546#define outsw_p outsw_p
547static inline void outsw_p(unsigned long addr, const void *buffer,
548 unsigned int count)
549{
550 outsw(addr, buffer, count);
551}
552#endif
553
554#ifndef outsl_p
555#define outsl_p outsl_p
556static inline void outsl_p(unsigned long addr, const void *buffer,
557 unsigned int count)
558{
559 outsl(addr, buffer, count);
560}
561#endif
562
563#ifndef CONFIG_GENERIC_IOMAP
564#ifndef ioread8
565#define ioread8 ioread8
566static inline u8 ioread8(const volatile void __iomem *addr)
567{
568 return readb(addr);
569}
570#endif
571
572#ifndef ioread16
573#define ioread16 ioread16
574static inline u16 ioread16(const volatile void __iomem *addr)
575{
576 return readw(addr);
577}
578#endif
579
580#ifndef ioread32
581#define ioread32 ioread32
582static inline u32 ioread32(const volatile void __iomem *addr)
583{
584 return readl(addr);
585}
586#endif
587
588#ifndef iowrite8
589#define iowrite8 iowrite8
590static inline void iowrite8(u8 value, volatile void __iomem *addr)
591{
592 writeb(value, addr);
593}
594#endif
595
596#ifndef iowrite16
597#define iowrite16 iowrite16
598static inline void iowrite16(u16 value, volatile void __iomem *addr)
599{
600 writew(value, addr);
601}
602#endif
603
604#ifndef iowrite32
605#define iowrite32 iowrite32
606static inline void iowrite32(u32 value, volatile void __iomem *addr)
607{
608 writel(value, addr);
609}
610#endif
611
612#ifndef ioread16be
613#define ioread16be ioread16be
614static inline u16 ioread16be(const volatile void __iomem *addr)
615{
616 return __be16_to_cpu(__raw_readw(addr));
617}
618#endif
619
620#ifndef ioread32be
621#define ioread32be ioread32be
622static inline u32 ioread32be(const volatile void __iomem *addr)
623{
624 return __be32_to_cpu(__raw_readl(addr));
625}
626#endif
627
628#ifndef iowrite16be
629#define iowrite16be iowrite16be
630static inline void iowrite16be(u16 value, void volatile __iomem *addr)
631{
632 __raw_writew(__cpu_to_be16(value), addr);
633}
634#endif
635
636#ifndef iowrite32be
637#define iowrite32be iowrite32be
638static inline void iowrite32be(u32 value, volatile void __iomem *addr)
639{
640 __raw_writel(__cpu_to_be32(value), addr);
641}
642#endif
643
644#ifndef ioread8_rep
645#define ioread8_rep ioread8_rep
646static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer,
647 unsigned int count)
648{
649 readsb(addr, buffer, count);
650}
651#endif
652
653#ifndef ioread16_rep
654#define ioread16_rep ioread16_rep
655static inline void ioread16_rep(const volatile void __iomem *addr,
656 void *buffer, unsigned int count)
657{
658 readsw(addr, buffer, count);
659}
660#endif
661
662#ifndef ioread32_rep
663#define ioread32_rep ioread32_rep
664static inline void ioread32_rep(const volatile void __iomem *addr,
665 void *buffer, unsigned int count)
666{
667 readsl(addr, buffer, count);
668}
669#endif
670
671#ifndef iowrite8_rep
672#define iowrite8_rep iowrite8_rep
673static inline void iowrite8_rep(volatile void __iomem *addr,
674 const void *buffer,
675 unsigned int count)
676{
677 writesb(addr, buffer, count);
678}
679#endif
680
681#ifndef iowrite16_rep
682#define iowrite16_rep iowrite16_rep
683static inline void iowrite16_rep(volatile void __iomem *addr,
684 const void *buffer,
685 unsigned int count)
686{
687 writesw(addr, buffer, count);
688}
689#endif
690
691#ifndef iowrite32_rep
692#define iowrite32_rep iowrite32_rep
693static inline void iowrite32_rep(volatile void __iomem *addr,
694 const void *buffer,
695 unsigned int count)
696{
697 writesl(addr, buffer, count);
698}
699#endif
700#endif /* CONFIG_GENERIC_IOMAP */
701
271#ifdef __KERNEL__ 702#ifdef __KERNEL__
272 703
273#include <linux/vmalloc.h> 704#include <linux/vmalloc.h>
274#define __io_virt(x) ((void __force *) (x)) 705#define __io_virt(x) ((void __force *)(x))
275 706
276#ifndef CONFIG_GENERIC_IOMAP 707#ifndef CONFIG_GENERIC_IOMAP
277struct pci_dev; 708struct pci_dev;
278extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); 709extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
279 710
280#ifndef pci_iounmap 711#ifndef pci_iounmap
712#define pci_iounmap pci_iounmap
281static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p) 713static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
282{ 714{
283} 715}
@@ -289,11 +721,15 @@ static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
289 * These are pretty trivial 721 * These are pretty trivial
290 */ 722 */
291#ifndef virt_to_phys 723#ifndef virt_to_phys
724#define virt_to_phys virt_to_phys
292static inline unsigned long virt_to_phys(volatile void *address) 725static inline unsigned long virt_to_phys(volatile void *address)
293{ 726{
294 return __pa((unsigned long)address); 727 return __pa((unsigned long)address);
295} 728}
729#endif
296 730
731#ifndef phys_to_virt
732#define phys_to_virt phys_to_virt
297static inline void *phys_to_virt(unsigned long address) 733static inline void *phys_to_virt(unsigned long address)
298{ 734{
299 return __va(address); 735 return __va(address);
@@ -306,37 +742,65 @@ static inline void *phys_to_virt(unsigned long address)
306 * This implementation is for the no-MMU case only... if you have an MMU 742 * This implementation is for the no-MMU case only... if you have an MMU
307 * you'll need to provide your own definitions. 743 * you'll need to provide your own definitions.
308 */ 744 */
745
309#ifndef CONFIG_MMU 746#ifndef CONFIG_MMU
310static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size) 747#ifndef ioremap
748#define ioremap ioremap
749static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
311{ 750{
312 return (void __iomem*) (unsigned long)offset; 751 return (void __iomem *)(unsigned long)offset;
313} 752}
753#endif
314 754
315#define __ioremap(offset, size, flags) ioremap(offset, size) 755#ifndef __ioremap
756#define __ioremap __ioremap
757static inline void __iomem *__ioremap(phys_addr_t offset, size_t size,
758 unsigned long flags)
759{
760 return ioremap(offset, size);
761}
762#endif
316 763
317#ifndef ioremap_nocache 764#ifndef ioremap_nocache
318#define ioremap_nocache ioremap 765#define ioremap_nocache ioremap_nocache
766static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size)
767{
768 return ioremap(offset, size);
769}
319#endif 770#endif
320 771
321#ifndef ioremap_wc 772#ifndef ioremap_wc
322#define ioremap_wc ioremap_nocache 773#define ioremap_wc ioremap_wc
774static inline void __iomem *ioremap_wc(phys_addr_t offset, size_t size)
775{
776 return ioremap_nocache(offset, size);
777}
323#endif 778#endif
324 779
780#ifndef iounmap
781#define iounmap iounmap
325static inline void iounmap(void __iomem *addr) 782static inline void iounmap(void __iomem *addr)
326{ 783{
327} 784}
785#endif
328#endif /* CONFIG_MMU */ 786#endif /* CONFIG_MMU */
329 787
330#ifdef CONFIG_HAS_IOPORT_MAP 788#ifdef CONFIG_HAS_IOPORT_MAP
331#ifndef CONFIG_GENERIC_IOMAP 789#ifndef CONFIG_GENERIC_IOMAP
790#ifndef ioport_map
791#define ioport_map ioport_map
332static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) 792static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
333{ 793{
334 return PCI_IOBASE + (port & IO_SPACE_LIMIT); 794 return PCI_IOBASE + (port & IO_SPACE_LIMIT);
335} 795}
796#endif
336 797
798#ifndef ioport_unmap
799#define ioport_unmap ioport_unmap
337static inline void ioport_unmap(void __iomem *p) 800static inline void ioport_unmap(void __iomem *p)
338{ 801{
339} 802}
803#endif
340#else /* CONFIG_GENERIC_IOMAP */ 804#else /* CONFIG_GENERIC_IOMAP */
341extern void __iomem *ioport_map(unsigned long port, unsigned int nr); 805extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
342extern void ioport_unmap(void __iomem *p); 806extern void ioport_unmap(void __iomem *p);
@@ -344,35 +808,68 @@ extern void ioport_unmap(void __iomem *p);
344#endif /* CONFIG_HAS_IOPORT_MAP */ 808#endif /* CONFIG_HAS_IOPORT_MAP */
345 809
346#ifndef xlate_dev_kmem_ptr 810#ifndef xlate_dev_kmem_ptr
347#define xlate_dev_kmem_ptr(p) p 811#define xlate_dev_kmem_ptr xlate_dev_kmem_ptr
812static inline void *xlate_dev_kmem_ptr(void *addr)
813{
814 return addr;
815}
348#endif 816#endif
817
349#ifndef xlate_dev_mem_ptr 818#ifndef xlate_dev_mem_ptr
350#define xlate_dev_mem_ptr(p) __va(p) 819#define xlate_dev_mem_ptr xlate_dev_mem_ptr
820static inline void *xlate_dev_mem_ptr(phys_addr_t addr)
821{
822 return __va(addr);
823}
824#endif
825
826#ifndef unxlate_dev_mem_ptr
827#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
828static inline void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)
829{
830}
351#endif 831#endif
352 832
353#ifdef CONFIG_VIRT_TO_BUS 833#ifdef CONFIG_VIRT_TO_BUS
354#ifndef virt_to_bus 834#ifndef virt_to_bus
355static inline unsigned long virt_to_bus(volatile void *address) 835static inline unsigned long virt_to_bus(void *address)
356{ 836{
357 return ((unsigned long) address); 837 return (unsigned long)address;
358} 838}
359 839
360static inline void *bus_to_virt(unsigned long address) 840static inline void *bus_to_virt(unsigned long address)
361{ 841{
362 return (void *) address; 842 return (void *)address;
363} 843}
364#endif 844#endif
365#endif 845#endif
366 846
367#ifndef memset_io 847#ifndef memset_io
368#define memset_io(a, b, c) memset(__io_virt(a), (b), (c)) 848#define memset_io memset_io
849static inline void memset_io(volatile void __iomem *addr, int value,
850 size_t size)
851{
852 memset(__io_virt(addr), value, size);
853}
369#endif 854#endif
370 855
371#ifndef memcpy_fromio 856#ifndef memcpy_fromio
372#define memcpy_fromio(a, b, c) memcpy((a), __io_virt(b), (c)) 857#define memcpy_fromio memcpy_fromio
858static inline void memcpy_fromio(void *buffer,
859 const volatile void __iomem *addr,
860 size_t size)
861{
862 memcpy(buffer, __io_virt(addr), size);
863}
373#endif 864#endif
865
374#ifndef memcpy_toio 866#ifndef memcpy_toio
375#define memcpy_toio(a, b, c) memcpy(__io_virt(a), (b), (c)) 867#define memcpy_toio memcpy_toio
868static inline void memcpy_toio(volatile void __iomem *addr, const void *buffer,
869 size_t size)
870{
871 memcpy(__io_virt(addr), buffer, size);
872}
376#endif 873#endif
377 874
378#endif /* __KERNEL__ */ 875#endif /* __KERNEL__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-28 04:31:46 -0500