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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2012-06-13 13:01:28 -0400
committerArnd Bergmann <arnd@arndb.de>2012-07-10 09:47:49 -0400
commit9ae6f740b49f933eeff972a79fd2a8b7e4592cf5 (patch)
tree6f9f7bd976089aaea0787de925e91e3ddb041196
parent31af49db7b2d700fdaf26ab55ca96428bc2e8b06 (diff)
arm: mach-mvebu: add support for Armada 370 and Armada XP with DT
[ben.dooks@codethink.co.uk: ensure error check on of_property_read_u32] [ben.dooks@codethink.co.uk: use mpic address instead of bus-unit's ] [ben.dooks@codethink.co.uk: BUG_ON() if the of_iomap() fails for mpic] [ben.dooks@codethink.co.uk: move mpic per-cpu register base ] [ben.dooks@codethink.co.uk: number fetch should use irqd_to_hwirq()] Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Yehuda Yitschak <yehuday@marvell.com> Tested-by: Lior Amsalem <alior@marvell.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts42
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi68
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi35
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts50
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi55
-rw-r--r--arch/arm/mach-mvebu/Kconfig9
-rw-r--r--arch/arm/mach-mvebu/Makefile1
-rw-r--r--arch/arm/mach-mvebu/armada-370-xp.c63
-rw-r--r--arch/arm/mach-mvebu/common.h3
-rw-r--r--arch/arm/mach-mvebu/include/mach/armada-370-xp.h22
-rw-r--r--arch/arm/mach-mvebu/irq-armada-370-xp.c130
11 files changed, 478 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
new file mode 100644
index 000000000000..fffd5c2a3041
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -0,0 +1,42 @@
1/*
2 * Device Tree file for Marvell Armada 370 evaluation board
3 * (DB-88F6710-BP-DDR3)
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16/dts-v1/;
17/include/ "armada-370.dtsi"
18
19/ {
20 model = "Marvell Armada 370 Evaluation Board";
21 compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
22
23 chosen {
24 bootargs = "console=ttyS0,115200 earlyprintk";
25 };
26
27 memory {
28 device_type = "memory";
29 reg = <0x00000000 0x20000000>; /* 512 MB */
30 };
31
32 soc {
33 serial@d0012000 {
34 clock-frequency = <200000000>;
35 status = "okay";
36 };
37 timer@d0020300 {
38 clock-frequency = <600000000>;
39 status = "okay";
40 };
41 };
42};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
new file mode 100644
index 000000000000..6b6b932a5a7d
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -0,0 +1,68 @@
1/*
2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
15 * This file contains the definitions that are common to the Armada
16 * 370 and Armada XP SoC.
17 */
18
19/include/ "skeleton.dtsi"
20
21/ {
22 model = "Marvell Armada 370 and XP SoC";
23 compatible = "marvell,armada_370_xp";
24
25 cpus {
26 cpu@0 {
27 compatible = "marvell,sheeva-v7";
28 };
29 };
30
31 mpic: interrupt-controller@d0020000 {
32 compatible = "marvell,mpic";
33 #interrupt-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <1>;
36 interrupt-controller;
37 };
38
39 soc {
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "simple-bus";
43 interrupt-parent = <&mpic>;
44 ranges;
45
46 serial@d0012000 {
47 compatible = "ns16550";
48 reg = <0xd0012000 0x100>;
49 reg-shift = <2>;
50 interrupts = <41>;
51 status = "disabled";
52 };
53 serial@d0012100 {
54 compatible = "ns16550";
55 reg = <0xd0012100 0x100>;
56 reg-shift = <2>;
57 interrupts = <42>;
58 status = "disabled";
59 };
60
61 timer@d0020300 {
62 compatible = "marvell,armada-370-xp-timer";
63 reg = <0xd0020300 0x30>;
64 interrupts = <37>, <38>, <39>, <40>;
65 };
66 };
67};
68
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
new file mode 100644
index 000000000000..3228ccc83332
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -0,0 +1,35 @@
1/*
2 * Device Tree Include file for Marvell Armada 370 family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * Contains definitions specific to the Armada 370 SoC that are not
15 * common to all Armada SoCs.
16 */
17
18/include/ "armada-370-xp.dtsi"
19
20/ {
21 model = "Marvell Armada 370 family SoC";
22 compatible = "marvell,armada370", "marvell,armada-370-xp";
23
24 mpic: interrupt-controller@d0020000 {
25 reg = <0xd0020a00 0x1d0>,
26 <0xd0021870 0x58>;
27 };
28
29 soc {
30 system-controller@d0018200 {
31 compatible = "marvell,armada-370-xp-system-controller";
32 reg = <0xd0018200 0x100>;
33 };
34 };
35};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
new file mode 100644
index 000000000000..f97040d4258d
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -0,0 +1,50 @@
1/*
2 * Device Tree file for Marvell Armada XP evaluation board
3 * (DB-78460-BP)
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16/dts-v1/;
17/include/ "armada-xp.dtsi"
18
19/ {
20 model = "Marvell Armada XP Evaluation Board";
21 compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
22
23 chosen {
24 bootargs = "console=ttyS0,115200 earlyprintk";
25 };
26
27 memory {
28 device_type = "memory";
29 reg = <0x00000000 0x80000000>; /* 2 GB */
30 };
31
32 soc {
33 serial@d0012000 {
34 clock-frequency = <250000000>;
35 status = "okay";
36 };
37 serial@d0012100 {
38 clock-frequency = <250000000>;
39 status = "okay";
40 };
41 serial@d0012200 {
42 clock-frequency = <250000000>;
43 status = "okay";
44 };
45 serial@d0012300 {
46 clock-frequency = <250000000>;
47 status = "okay";
48 };
49 };
50};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
new file mode 100644
index 000000000000..e1fa7e6edfe8
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -0,0 +1,55 @@
1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
15 * Contains definitions specific to the Armada 370 SoC that are not
16 * common to all Armada SoCs.
17 */
18
19/include/ "armada-370-xp.dtsi"
20
21/ {
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24
25 mpic: interrupt-controller@d0020000 {
26 reg = <0xd0020a00 0x1d0>,
27 <0xd0021870 0x58>;
28 };
29
30 soc {
31 serial@d0012200 {
32 compatible = "ns16550";
33 reg = <0xd0012200 0x100>;
34 reg-shift = <2>;
35 interrupts = <43>;
36 status = "disabled";
37 };
38 serial@d0012300 {
39 compatible = "ns16550";
40 reg = <0xd0012300 0x100>;
41 reg-shift = <2>;
42 interrupts = <44>;
43 status = "disabled";
44 };
45
46 timer@d0020300 {
47 marvell,timer-25Mhz;
48 };
49
50 system-controller@d0018200 {
51 compatible = "marvell,armada-370-xp-system-controller";
52 reg = <0xd0018200 0x500>;
53 };
54 };
55};
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 72d39e5c0ff4..caa2c5e734fe 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -2,6 +2,15 @@ if ARCH_MVEBU
2 2
3menu "Marvell SOC with device tree" 3menu "Marvell SOC with device tree"
4 4
5config MACH_ARMADA_370_XP
6 bool "Marvell Armada 370 and Aramada XP boards"
7 select ARMADA_370_XP_TIMER
8 select CPU_V7
9 help
10
11 Say 'Y' here if you want your kernel to support boards based on
12 Marvell Armada 370 or Armada XP with device tree.
13
5endmenu 14endmenu
6 15
7endif 16endif
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 7366ae7357f3..e61d2b8fdf50 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1 +1,2 @@
1obj-y += system-controller.o 1obj-y += system-controller.o
2obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
new file mode 100644
index 000000000000..4ef923b032ec
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -0,0 +1,63 @@
1/*
2 * Device Tree support for Armada 370 and XP platforms.
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/of_platform.h>
18#include <linux/io.h>
19#include <linux/time-armada-370-xp.h>
20#include <asm/mach/arch.h>
21#include <asm/mach/map.h>
22#include <asm/mach/time.h>
23#include <mach/armada-370-xp.h>
24#include "common.h"
25
26static struct map_desc armada_370_xp_io_desc[] __initdata = {
27 {
28 .virtual = ARMADA_370_XP_REGS_VIRT_BASE,
29 .pfn = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
30 .length = ARMADA_370_XP_REGS_SIZE,
31 .type = MT_DEVICE,
32 },
33};
34
35void __init armada_370_xp_map_io(void)
36{
37 iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
38}
39
40struct sys_timer armada_370_xp_timer = {
41 .init = armada_370_xp_timer_init,
42};
43
44static void __init armada_370_xp_dt_init(void)
45{
46 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
47}
48
49static const char * const armada_370_xp_dt_board_dt_compat[] = {
50 "marvell,a370-db",
51 "marvell,axp-db",
52 NULL,
53};
54
55DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)")
56 .init_machine = armada_370_xp_dt_init,
57 .map_io = armada_370_xp_map_io,
58 .init_irq = armada_370_xp_init_irq,
59 .handle_irq = armada_370_xp_handle_irq,
60 .timer = &armada_370_xp_timer,
61 .restart = mvebu_restart,
62 .dt_compat = armada_370_xp_dt_board_dt_compat,
63MACHINE_END
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index f0eaa215e629..02f89eaa25fe 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -17,4 +17,7 @@
17 17
18void mvebu_restart(char mode, const char *cmd); 18void mvebu_restart(char mode, const char *cmd);
19 19
20void armada_370_xp_init_irq(void);
21void armada_370_xp_handle_irq(struct pt_regs *regs);
22
20#endif 23#endif
diff --git a/arch/arm/mach-mvebu/include/mach/armada-370-xp.h b/arch/arm/mach-mvebu/include/mach/armada-370-xp.h
new file mode 100644
index 000000000000..25f0ca8d7820
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/armada-370-xp.h
@@ -0,0 +1,22 @@
1/*
2 * Generic definitions for Marvell Armada_370_XP SoCs
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __MACH_ARMADA_370_XP_H
16#define __MACH_ARMADA_370_XP_H
17
18#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
19#define ARMADA_370_XP_REGS_VIRT_BASE 0xfeb00000
20#define ARMADA_370_XP_REGS_SIZE SZ_1M
21
22#endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
new file mode 100644
index 000000000000..645a8d3698eb
--- /dev/null
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -0,0 +1,130 @@
1/*
2 * Marvell Armada 370 and Armada XP SoC IRQ handling
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
24#include <linux/irqdomain.h>
25#include <asm/mach/arch.h>
26#include <asm/exception.h>
27
28/* Interrupt Controller Registers Map */
29#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
30#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
31
32#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
33#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
34
35#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
36
37#define ARMADA_370_XP_NR_IRQS (115)
38
39static void __iomem *per_cpu_int_base;
40static void __iomem *main_int_base;
41static struct irq_domain *armada_370_xp_mpic_domain;
42
43static void armada_370_xp_irq_mask(struct irq_data *d)
44{
45 writel(irqd_to_hwirq(d),
46 per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
47}
48
49static void armada_370_xp_irq_unmask(struct irq_data *d)
50{
51 writel(irqd_to_hwirq(d),
52 per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
53}
54
55static struct irq_chip armada_370_xp_irq_chip = {
56 .name = "armada_370_xp_irq",
57 .irq_mask = armada_370_xp_irq_mask,
58 .irq_mask_ack = armada_370_xp_irq_mask,
59 .irq_unmask = armada_370_xp_irq_unmask,
60};
61
62static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
63 unsigned int virq, irq_hw_number_t hw)
64{
65 armada_370_xp_irq_mask(irq_get_irq_data(virq));
66 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
67
68 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
69 handle_level_irq);
70 irq_set_status_flags(virq, IRQ_LEVEL);
71 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
72
73 return 0;
74}
75
76static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
77 .map = armada_370_xp_mpic_irq_map,
78 .xlate = irq_domain_xlate_onecell,
79};
80
81static int __init armada_370_xp_mpic_of_init(struct device_node *node,
82 struct device_node *parent)
83{
84 main_int_base = of_iomap(node, 0);
85 per_cpu_int_base = of_iomap(node, 1);
86
87 BUG_ON(!main_int_base);
88 BUG_ON(!per_cpu_int_base);
89
90 armada_370_xp_mpic_domain =
91 irq_domain_add_linear(node, ARMADA_370_XP_NR_IRQS,
92 &armada_370_xp_mpic_irq_ops, NULL);
93
94 if (!armada_370_xp_mpic_domain)
95 panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
96
97 irq_set_default_host(armada_370_xp_mpic_domain);
98 return 0;
99}
100
101asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
102 *regs)
103{
104 u32 irqstat, irqnr;
105
106 do {
107 irqstat = readl_relaxed(per_cpu_int_base +
108 ARMADA_370_XP_CPU_INTACK_OFFS);
109 irqnr = irqstat & 0x3FF;
110
111 if (irqnr < 1023) {
112 irqnr =
113 irq_find_mapping(armada_370_xp_mpic_domain, irqnr);
114 handle_IRQ(irqnr, regs);
115 continue;
116 }
117
118 break;
119 } while (1);
120}
121
122static const struct of_device_id mpic_of_match[] __initconst = {
123 {.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
124 {},
125};
126
127void __init armada_370_xp_init_irq(void)
128{
129 of_irq_init(mpic_of_match);
130}
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