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authorGrant Likely <grant.likely@secretlab.ca>2011-06-16 15:31:42 -0400
committerGrant Likely <grant.likely@secretlab.ca>2011-06-16 15:31:42 -0400
commit8e46ea3ec8b132bffd989741e8d154accb623645 (patch)
tree2c413b2e379c928c5aa0de445b29f345df1351ab
parent2bc7c85210d75b7a8a7326284b4f608a16f52ffc (diff)
parente5ff4440cf5206fbb99d9a354ed9024eb3da047d (diff)
Merge branch 'for_3.1/gpio-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into gpio/next
Diffstat
-rw-r--r--arch/arm/mach-omap1/gpio15xx.c22
-rw-r--r--arch/arm/mach-omap1/gpio16xx.c28
-rw-r--r--arch/arm/mach-omap1/gpio7xx.c27
-rw-r--r--arch/arm/mach-omap2/gpio.c32
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h20
-rw-r--r--drivers/gpio/gpio-omap.c723
6 files changed, 282 insertions, 570 deletions
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 04c4b04cf54e..f79c6aef11af 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -34,11 +34,22 @@ static struct __initdata resource omap15xx_mpu_gpio_resources[] = {
34 }, 34 },
35}; 35};
36 36
37static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
38 .revision = USHRT_MAX,
39 .direction = OMAP_MPUIO_IO_CNTL,
40 .datain = OMAP_MPUIO_INPUT_LATCH,
41 .dataout = OMAP_MPUIO_OUTPUT,
42 .irqstatus = OMAP_MPUIO_GPIO_INT,
43 .irqenable = OMAP_MPUIO_GPIO_MASKIT,
44 .irqenable_inv = true,
45};
46
37static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = { 47static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
38 .virtual_irq_start = IH_MPUIO_BASE, 48 .virtual_irq_start = IH_MPUIO_BASE,
39 .bank_type = METHOD_MPUIO, 49 .bank_type = METHOD_MPUIO,
40 .bank_width = 16, 50 .bank_width = 16,
41 .bank_stride = 1, 51 .bank_stride = 1,
52 .regs = &omap15xx_mpuio_regs,
42}; 53};
43 54
44static struct __initdata platform_device omap15xx_mpu_gpio = { 55static struct __initdata platform_device omap15xx_mpu_gpio = {
@@ -64,10 +75,21 @@ static struct __initdata resource omap15xx_gpio_resources[] = {
64 }, 75 },
65}; 76};
66 77
78static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
79 .revision = USHRT_MAX,
80 .direction = OMAP1510_GPIO_DIR_CONTROL,
81 .datain = OMAP1510_GPIO_DATA_INPUT,
82 .dataout = OMAP1510_GPIO_DATA_OUTPUT,
83 .irqstatus = OMAP1510_GPIO_INT_STATUS,
84 .irqenable = OMAP1510_GPIO_INT_MASK,
85 .irqenable_inv = true,
86};
87
67static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = { 88static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
68 .virtual_irq_start = IH_GPIO_BASE, 89 .virtual_irq_start = IH_GPIO_BASE,
69 .bank_type = METHOD_GPIO_1510, 90 .bank_type = METHOD_GPIO_1510,
70 .bank_width = 16, 91 .bank_width = 16,
92 .regs = &omap15xx_gpio_regs,
71}; 93};
72 94
73static struct __initdata platform_device omap15xx_gpio = { 95static struct __initdata platform_device omap15xx_gpio = {
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 5dd0d4c82b24..c69b3b104286 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -37,11 +37,22 @@ static struct __initdata resource omap16xx_mpu_gpio_resources[] = {
37 }, 37 },
38}; 38};
39 39
40static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {
41 .revision = USHRT_MAX,
42 .direction = OMAP_MPUIO_IO_CNTL,
43 .datain = OMAP_MPUIO_INPUT_LATCH,
44 .dataout = OMAP_MPUIO_OUTPUT,
45 .irqstatus = OMAP_MPUIO_GPIO_INT,
46 .irqenable = OMAP_MPUIO_GPIO_MASKIT,
47 .irqenable_inv = true,
48};
49
40static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = { 50static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
41 .virtual_irq_start = IH_MPUIO_BASE, 51 .virtual_irq_start = IH_MPUIO_BASE,
42 .bank_type = METHOD_MPUIO, 52 .bank_type = METHOD_MPUIO,
43 .bank_width = 16, 53 .bank_width = 16,
44 .bank_stride = 1, 54 .bank_stride = 1,
55 .regs = &omap16xx_mpuio_regs,
45}; 56};
46 57
47static struct __initdata platform_device omap16xx_mpu_gpio = { 58static struct __initdata platform_device omap16xx_mpu_gpio = {
@@ -67,10 +78,24 @@ static struct __initdata resource omap16xx_gpio1_resources[] = {
67 }, 78 },
68}; 79};
69 80
81static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
82 .revision = OMAP1610_GPIO_REVISION,
83 .direction = OMAP1610_GPIO_DIRECTION,
84 .set_dataout = OMAP1610_GPIO_SET_DATAOUT,
85 .clr_dataout = OMAP1610_GPIO_CLEAR_DATAOUT,
86 .datain = OMAP1610_GPIO_DATAIN,
87 .dataout = OMAP1610_GPIO_DATAOUT,
88 .irqstatus = OMAP1610_GPIO_IRQSTATUS1,
89 .irqenable = OMAP1610_GPIO_IRQENABLE1,
90 .set_irqenable = OMAP1610_GPIO_SET_IRQENABLE1,
91 .clr_irqenable = OMAP1610_GPIO_CLEAR_IRQENABLE1,
92};
93
70static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = { 94static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
71 .virtual_irq_start = IH_GPIO_BASE, 95 .virtual_irq_start = IH_GPIO_BASE,
72 .bank_type = METHOD_GPIO_1610, 96 .bank_type = METHOD_GPIO_1610,
73 .bank_width = 16, 97 .bank_width = 16,
98 .regs = &omap16xx_gpio_regs,
74}; 99};
75 100
76static struct __initdata platform_device omap16xx_gpio1 = { 101static struct __initdata platform_device omap16xx_gpio1 = {
@@ -100,6 +125,7 @@ static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = {
100 .virtual_irq_start = IH_GPIO_BASE + 16, 125 .virtual_irq_start = IH_GPIO_BASE + 16,
101 .bank_type = METHOD_GPIO_1610, 126 .bank_type = METHOD_GPIO_1610,
102 .bank_width = 16, 127 .bank_width = 16,
128 .regs = &omap16xx_gpio_regs,
103}; 129};
104 130
105static struct __initdata platform_device omap16xx_gpio2 = { 131static struct __initdata platform_device omap16xx_gpio2 = {
@@ -129,6 +155,7 @@ static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = {
129 .virtual_irq_start = IH_GPIO_BASE + 32, 155 .virtual_irq_start = IH_GPIO_BASE + 32,
130 .bank_type = METHOD_GPIO_1610, 156 .bank_type = METHOD_GPIO_1610,
131 .bank_width = 16, 157 .bank_width = 16,
158 .regs = &omap16xx_gpio_regs,
132}; 159};
133 160
134static struct __initdata platform_device omap16xx_gpio3 = { 161static struct __initdata platform_device omap16xx_gpio3 = {
@@ -158,6 +185,7 @@ static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = {
158 .virtual_irq_start = IH_GPIO_BASE + 48, 185 .virtual_irq_start = IH_GPIO_BASE + 48,
159 .bank_type = METHOD_GPIO_1610, 186 .bank_type = METHOD_GPIO_1610,
160 .bank_width = 16, 187 .bank_width = 16,
188 .regs = &omap16xx_gpio_regs,
161}; 189};
162 190
163static struct __initdata platform_device omap16xx_gpio4 = { 191static struct __initdata platform_device omap16xx_gpio4 = {
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 1204c8b871af..d7f2ad3e6ac7 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -39,11 +39,22 @@ static struct __initdata resource omap7xx_mpu_gpio_resources[] = {
39 }, 39 },
40}; 40};
41 41
42static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
43 .revision = USHRT_MAX,
44 .direction = OMAP_MPUIO_IO_CNTL / 2,
45 .datain = OMAP_MPUIO_INPUT_LATCH / 2,
46 .dataout = OMAP_MPUIO_OUTPUT / 2,
47 .irqstatus = OMAP_MPUIO_GPIO_INT / 2,
48 .irqenable = OMAP_MPUIO_GPIO_MASKIT / 2,
49 .irqenable_inv = true,
50};
51
42static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = { 52static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
43 .virtual_irq_start = IH_MPUIO_BASE, 53 .virtual_irq_start = IH_MPUIO_BASE,
44 .bank_type = METHOD_MPUIO, 54 .bank_type = METHOD_MPUIO,
45 .bank_width = 32, 55 .bank_width = 32,
46 .bank_stride = 2, 56 .bank_stride = 2,
57 .regs = &omap7xx_mpuio_regs,
47}; 58};
48 59
49static struct __initdata platform_device omap7xx_mpu_gpio = { 60static struct __initdata platform_device omap7xx_mpu_gpio = {
@@ -69,10 +80,21 @@ static struct __initdata resource omap7xx_gpio1_resources[] = {
69 }, 80 },
70}; 81};
71 82
83static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
84 .revision = USHRT_MAX,
85 .direction = OMAP7XX_GPIO_DIR_CONTROL,
86 .datain = OMAP7XX_GPIO_DATA_INPUT,
87 .dataout = OMAP7XX_GPIO_DATA_OUTPUT,
88 .irqstatus = OMAP7XX_GPIO_INT_STATUS,
89 .irqenable = OMAP7XX_GPIO_INT_MASK,
90 .irqenable_inv = true,
91};
92
72static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = { 93static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
73 .virtual_irq_start = IH_GPIO_BASE, 94 .virtual_irq_start = IH_GPIO_BASE,
74 .bank_type = METHOD_GPIO_7XX, 95 .bank_type = METHOD_GPIO_7XX,
75 .bank_width = 32, 96 .bank_width = 32,
97 .regs = &omap7xx_gpio_regs,
76}; 98};
77 99
78static struct __initdata platform_device omap7xx_gpio1 = { 100static struct __initdata platform_device omap7xx_gpio1 = {
@@ -102,6 +124,7 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = {
102 .virtual_irq_start = IH_GPIO_BASE + 32, 124 .virtual_irq_start = IH_GPIO_BASE + 32,
103 .bank_type = METHOD_GPIO_7XX, 125 .bank_type = METHOD_GPIO_7XX,
104 .bank_width = 32, 126 .bank_width = 32,
127 .regs = &omap7xx_gpio_regs,
105}; 128};
106 129
107static struct __initdata platform_device omap7xx_gpio2 = { 130static struct __initdata platform_device omap7xx_gpio2 = {
@@ -131,6 +154,7 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = {
131 .virtual_irq_start = IH_GPIO_BASE + 64, 154 .virtual_irq_start = IH_GPIO_BASE + 64,
132 .bank_type = METHOD_GPIO_7XX, 155 .bank_type = METHOD_GPIO_7XX,
133 .bank_width = 32, 156 .bank_width = 32,
157 .regs = &omap7xx_gpio_regs,
134}; 158};
135 159
136static struct __initdata platform_device omap7xx_gpio3 = { 160static struct __initdata platform_device omap7xx_gpio3 = {
@@ -160,6 +184,7 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = {
160 .virtual_irq_start = IH_GPIO_BASE + 96, 184 .virtual_irq_start = IH_GPIO_BASE + 96,
161 .bank_type = METHOD_GPIO_7XX, 185 .bank_type = METHOD_GPIO_7XX,
162 .bank_width = 32, 186 .bank_width = 32,
187 .regs = &omap7xx_gpio_regs,
163}; 188};
164 189
165static struct __initdata platform_device omap7xx_gpio4 = { 190static struct __initdata platform_device omap7xx_gpio4 = {
@@ -189,6 +214,7 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = {
189 .virtual_irq_start = IH_GPIO_BASE + 128, 214 .virtual_irq_start = IH_GPIO_BASE + 128,
190 .bank_type = METHOD_GPIO_7XX, 215 .bank_type = METHOD_GPIO_7XX,
191 .bank_width = 32, 216 .bank_width = 32,
217 .regs = &omap7xx_gpio_regs,
192}; 218};
193 219
194static struct __initdata platform_device omap7xx_gpio5 = { 220static struct __initdata platform_device omap7xx_gpio5 = {
@@ -218,6 +244,7 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = {
218 .virtual_irq_start = IH_GPIO_BASE + 160, 244 .virtual_irq_start = IH_GPIO_BASE + 160,
219 .bank_type = METHOD_GPIO_7XX, 245 .bank_type = METHOD_GPIO_7XX,
220 .bank_width = 32, 246 .bank_width = 32,
247 .regs = &omap7xx_gpio_regs,
221}; 248};
222 249
223static struct __initdata platform_device omap7xx_gpio6 = { 250static struct __initdata platform_device omap7xx_gpio6 = {
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 9529842ae054..9a46d7773a48 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -61,13 +61,45 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
61 pdata->dbck_flag = dev_attr->dbck_flag; 61 pdata->dbck_flag = dev_attr->dbck_flag;
62 pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1); 62 pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
63 63
64 pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
65 if (!pdata) {
66 pr_err("gpio%d: Memory allocation failed\n", id);
67 return -ENOMEM;
68 }
69
64 switch (oh->class->rev) { 70 switch (oh->class->rev) {
65 case 0: 71 case 0:
66 case 1: 72 case 1:
67 pdata->bank_type = METHOD_GPIO_24XX; 73 pdata->bank_type = METHOD_GPIO_24XX;
74 pdata->regs->revision = OMAP24XX_GPIO_REVISION;
75 pdata->regs->direction = OMAP24XX_GPIO_OE;
76 pdata->regs->datain = OMAP24XX_GPIO_DATAIN;
77 pdata->regs->dataout = OMAP24XX_GPIO_DATAOUT;
78 pdata->regs->set_dataout = OMAP24XX_GPIO_SETDATAOUT;
79 pdata->regs->clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT;
80 pdata->regs->irqstatus = OMAP24XX_GPIO_IRQSTATUS1;
81 pdata->regs->irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2;
82 pdata->regs->irqenable = OMAP24XX_GPIO_IRQENABLE1;
83 pdata->regs->set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1;
84 pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1;
85 pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;
86 pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
68 break; 87 break;
69 case 2: 88 case 2:
70 pdata->bank_type = METHOD_GPIO_44XX; 89 pdata->bank_type = METHOD_GPIO_44XX;
90 pdata->regs->revision = OMAP4_GPIO_REVISION;
91 pdata->regs->direction = OMAP4_GPIO_OE;
92 pdata->regs->datain = OMAP4_GPIO_DATAIN;
93 pdata->regs->dataout = OMAP4_GPIO_DATAOUT;
94 pdata->regs->set_dataout = OMAP4_GPIO_SETDATAOUT;
95 pdata->regs->clr_dataout = OMAP4_GPIO_CLEARDATAOUT;
96 pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0;
97 pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1;
98 pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0;
99 pdata->regs->set_irqenable = OMAP4_GPIO_IRQSTATUSSET0;
100 pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0;
101 pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;
102 pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
71 break; 103 break;
72 default: 104 default:
73 WARN(1, "Invalid gpio bank_type\n"); 105 WARN(1, "Invalid gpio bank_type\n");
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index ec97e00cb581..91e8de3db085 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -174,12 +174,32 @@ struct omap_gpio_dev_attr {
174 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ 174 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
175}; 175};
176 176
177struct omap_gpio_reg_offs {
178 u16 revision;
179 u16 direction;
180 u16 datain;
181 u16 dataout;
182 u16 set_dataout;
183 u16 clr_dataout;
184 u16 irqstatus;
185 u16 irqstatus2;
186 u16 irqenable;
187 u16 set_irqenable;
188 u16 clr_irqenable;
189 u16 debounce;
190 u16 debounce_en;
191
192 bool irqenable_inv;
193};
194
177struct omap_gpio_platform_data { 195struct omap_gpio_platform_data {
178 u16 virtual_irq_start; 196 u16 virtual_irq_start;
179 int bank_type; 197 int bank_type;
180 int bank_width; /* GPIO bank width */ 198 int bank_width; /* GPIO bank width */
181 int bank_stride; /* Only needed for omap1 MPUIO */ 199 int bank_stride; /* Only needed for omap1 MPUIO */
182 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ 200 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
201
202 struct omap_gpio_reg_offs *regs;
183}; 203};
184 204
185/* TODO: Analyze removing gpio_bank_count usage from driver code */ 205/* TODO: Analyze removing gpio_bank_count usage from driver code */
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 01f74a8459d9..501ca3d6a49e 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -54,6 +54,11 @@ struct gpio_bank {
54 struct device *dev; 54 struct device *dev;
55 bool dbck_flag; 55 bool dbck_flag;
56 int stride; 56 int stride;
57 u32 width;
58
59 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
60
61 struct omap_gpio_reg_offs *regs;
57}; 62};
58 63
59#ifdef CONFIG_ARCH_OMAP3 64#ifdef CONFIG_ARCH_OMAP3
@@ -79,121 +84,18 @@ static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
79 */ 84 */
80static struct gpio_bank *gpio_bank; 85static struct gpio_bank *gpio_bank;
81 86
82static int bank_width;
83
84/* TODO: Analyze removing gpio_bank_count usage from driver code */ 87/* TODO: Analyze removing gpio_bank_count usage from driver code */
85int gpio_bank_count; 88int gpio_bank_count;
86 89
87static inline struct gpio_bank *get_gpio_bank(int gpio) 90#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
88{ 91#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
89 if (cpu_is_omap15xx()) {
90 if (OMAP_GPIO_IS_MPUIO(gpio))
91 return &gpio_bank[0];
92 return &gpio_bank[1];
93 }
94 if (cpu_is_omap16xx()) {
95 if (OMAP_GPIO_IS_MPUIO(gpio))
96 return &gpio_bank[0];
97 return &gpio_bank[1 + (gpio >> 4)];
98 }
99 if (cpu_is_omap7xx()) {
100 if (OMAP_GPIO_IS_MPUIO(gpio))
101 return &gpio_bank[0];
102 return &gpio_bank[1 + (gpio >> 5)];
103 }
104 if (cpu_is_omap24xx())
105 return &gpio_bank[gpio >> 5];
106 if (cpu_is_omap34xx() || cpu_is_omap44xx())
107 return &gpio_bank[gpio >> 5];
108 BUG();
109 return NULL;
110}
111
112static inline int get_gpio_index(int gpio)
113{
114 if (cpu_is_omap7xx())
115 return gpio & 0x1f;
116 if (cpu_is_omap24xx())
117 return gpio & 0x1f;
118 if (cpu_is_omap34xx() || cpu_is_omap44xx())
119 return gpio & 0x1f;
120 return gpio & 0x0f;
121}
122
123static inline int gpio_valid(int gpio)
124{
125 if (gpio < 0)
126 return -1;
127 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
128 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
129 return -1;
130 return 0;
131 }
132 if (cpu_is_omap15xx() && gpio < 16)
133 return 0;
134 if ((cpu_is_omap16xx()) && gpio < 64)
135 return 0;
136 if (cpu_is_omap7xx() && gpio < 192)
137 return 0;
138 if (cpu_is_omap2420() && gpio < 128)
139 return 0;
140 if (cpu_is_omap2430() && gpio < 160)
141 return 0;
142 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
143 return 0;
144 return -1;
145}
146
147static int check_gpio(int gpio)
148{
149 if (unlikely(gpio_valid(gpio) < 0)) {
150 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
151 dump_stack();
152 return -1;
153 }
154 return 0;
155}
156 92
157static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) 93static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
158{ 94{
159 void __iomem *reg = bank->base; 95 void __iomem *reg = bank->base;
160 u32 l; 96 u32 l;
161 97
162 switch (bank->method) { 98 reg += bank->regs->direction;
163#ifdef CONFIG_ARCH_OMAP1
164 case METHOD_MPUIO:
165 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
166 break;
167#endif
168#ifdef CONFIG_ARCH_OMAP15XX
169 case METHOD_GPIO_1510:
170 reg += OMAP1510_GPIO_DIR_CONTROL;
171 break;
172#endif
173#ifdef CONFIG_ARCH_OMAP16XX
174 case METHOD_GPIO_1610:
175 reg += OMAP1610_GPIO_DIRECTION;
176 break;
177#endif
178#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
179 case METHOD_GPIO_7XX:
180 reg += OMAP7XX_GPIO_DIR_CONTROL;
181 break;
182#endif
183#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
184 case METHOD_GPIO_24XX:
185 reg += OMAP24XX_GPIO_OE;
186 break;
187#endif
188#if defined(CONFIG_ARCH_OMAP4)
189 case METHOD_GPIO_44XX:
190 reg += OMAP4_GPIO_OE;
191 break;
192#endif
193 default:
194 WARN_ON(1);
195 return;
196 }
197 l = __raw_readl(reg); 99 l = __raw_readl(reg);
198 if (is_input) 100 if (is_input)
199 l |= 1 << gpio; 101 l |= 1 << gpio;
@@ -202,165 +104,48 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
202 __raw_writel(l, reg); 104 __raw_writel(l, reg);
203} 105}
204 106
205static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) 107
108/* set data out value using dedicate set/clear register */
109static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
206{ 110{
207 void __iomem *reg = bank->base; 111 void __iomem *reg = bank->base;
208 u32 l = 0; 112 u32 l = GPIO_BIT(bank, gpio);
113
114 if (enable)
115 reg += bank->regs->set_dataout;
116 else
117 reg += bank->regs->clr_dataout;
209 118
210 switch (bank->method) {
211#ifdef CONFIG_ARCH_OMAP1
212 case METHOD_MPUIO:
213 reg += OMAP_MPUIO_OUTPUT / bank->stride;
214 l = __raw_readl(reg);
215 if (enable)
216 l |= 1 << gpio;
217 else
218 l &= ~(1 << gpio);
219 break;
220#endif
221#ifdef CONFIG_ARCH_OMAP15XX
222 case METHOD_GPIO_1510:
223 reg += OMAP1510_GPIO_DATA_OUTPUT;
224 l = __raw_readl(reg);
225 if (enable)
226 l |= 1 << gpio;
227 else
228 l &= ~(1 << gpio);
229 break;
230#endif
231#ifdef CONFIG_ARCH_OMAP16XX
232 case METHOD_GPIO_1610:
233 if (enable)
234 reg += OMAP1610_GPIO_SET_DATAOUT;
235 else
236 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
237 l = 1 << gpio;
238 break;
239#endif
240#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
241 case METHOD_GPIO_7XX:
242 reg += OMAP7XX_GPIO_DATA_OUTPUT;
243 l = __raw_readl(reg);
244 if (enable)
245 l |= 1 << gpio;
246 else
247 l &= ~(1 << gpio);
248 break;
249#endif
250#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
251 case METHOD_GPIO_24XX:
252 if (enable)
253 reg += OMAP24XX_GPIO_SETDATAOUT;
254 else
255 reg += OMAP24XX_GPIO_CLEARDATAOUT;
256 l = 1 << gpio;
257 break;
258#endif
259#ifdef CONFIG_ARCH_OMAP4
260 case METHOD_GPIO_44XX:
261 if (enable)
262 reg += OMAP4_GPIO_SETDATAOUT;
263 else
264 reg += OMAP4_GPIO_CLEARDATAOUT;
265 l = 1 << gpio;
266 break;
267#endif
268 default:
269 WARN_ON(1);
270 return;
271 }
272 __raw_writel(l, reg); 119 __raw_writel(l, reg);
273} 120}
274 121
275static int _get_gpio_datain(struct gpio_bank *bank, int gpio) 122/* set data out value using mask register */
123static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
276{ 124{
277 void __iomem *reg; 125 void __iomem *reg = bank->base + bank->regs->dataout;
126 u32 gpio_bit = GPIO_BIT(bank, gpio);
127 u32 l;
278 128
279 if (check_gpio(gpio) < 0) 129 l = __raw_readl(reg);
280 return -EINVAL; 130 if (enable)
281 reg = bank->base; 131 l |= gpio_bit;
282 switch (bank->method) { 132 else
283#ifdef CONFIG_ARCH_OMAP1 133 l &= ~gpio_bit;
284 case METHOD_MPUIO: 134 __raw_writel(l, reg);
285 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
286 break;
287#endif
288#ifdef CONFIG_ARCH_OMAP15XX
289 case METHOD_GPIO_1510:
290 reg += OMAP1510_GPIO_DATA_INPUT;
291 break;
292#endif
293#ifdef CONFIG_ARCH_OMAP16XX
294 case METHOD_GPIO_1610:
295 reg += OMAP1610_GPIO_DATAIN;
296 break;
297#endif
298#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
299 case METHOD_GPIO_7XX:
300 reg += OMAP7XX_GPIO_DATA_INPUT;
301 break;
302#endif
303#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
304 case METHOD_GPIO_24XX:
305 reg += OMAP24XX_GPIO_DATAIN;
306 break;
307#endif
308#ifdef CONFIG_ARCH_OMAP4
309 case METHOD_GPIO_44XX:
310 reg += OMAP4_GPIO_DATAIN;
311 break;
312#endif
313 default:
314 return -EINVAL;
315 }
316 return (__raw_readl(reg)
317 & (1 << get_gpio_index(gpio))) != 0;
318} 135}
319 136
320static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) 137static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
321{ 138{
322 void __iomem *reg; 139 void __iomem *reg = bank->base + bank->regs->datain;
323 140
324 if (check_gpio(gpio) < 0) 141 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
325 return -EINVAL; 142}
326 reg = bank->base;
327 143
328 switch (bank->method) { 144static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
329#ifdef CONFIG_ARCH_OMAP1 145{
330 case METHOD_MPUIO: 146 void __iomem *reg = bank->base + bank->regs->dataout;
331 reg += OMAP_MPUIO_OUTPUT / bank->stride;
332 break;
333#endif
334#ifdef CONFIG_ARCH_OMAP15XX
335 case METHOD_GPIO_1510:
336 reg += OMAP1510_GPIO_DATA_OUTPUT;
337 break;
338#endif
339#ifdef CONFIG_ARCH_OMAP16XX
340 case METHOD_GPIO_1610:
341 reg += OMAP1610_GPIO_DATAOUT;
342 break;
343#endif
344#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
345 case METHOD_GPIO_7XX:
346 reg += OMAP7XX_GPIO_DATA_OUTPUT;
347 break;
348#endif
349#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
350 case METHOD_GPIO_24XX:
351 reg += OMAP24XX_GPIO_DATAOUT;
352 break;
353#endif
354#ifdef CONFIG_ARCH_OMAP4
355 case METHOD_GPIO_44XX:
356 reg += OMAP4_GPIO_DATAOUT;
357 break;
358#endif
359 default:
360 return -EINVAL;
361 }
362 147
363 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; 148 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
364} 149}
365 150
366#define MOD_REG_BIT(reg, bit_mask, set) \ 151#define MOD_REG_BIT(reg, bit_mask, set) \
@@ -383,7 +168,7 @@ do { \
383static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, 168static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
384 unsigned debounce) 169 unsigned debounce)
385{ 170{
386 void __iomem *reg = bank->base; 171 void __iomem *reg;
387 u32 val; 172 u32 val;
388 u32 l; 173 u32 l;
389 174
@@ -397,21 +182,12 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
397 else 182 else
398 debounce = (debounce / 0x1f) - 1; 183 debounce = (debounce / 0x1f) - 1;
399 184
400 l = 1 << get_gpio_index(gpio); 185 l = GPIO_BIT(bank, gpio);
401
402 if (bank->method == METHOD_GPIO_44XX)
403 reg += OMAP4_GPIO_DEBOUNCINGTIME;
404 else
405 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
406 186
187 reg = bank->base + bank->regs->debounce;
407 __raw_writel(debounce, reg); 188 __raw_writel(debounce, reg);
408 189
409 reg = bank->base; 190 reg = bank->base + bank->regs->debounce_en;
410 if (bank->method == METHOD_GPIO_44XX)
411 reg += OMAP4_GPIO_DEBOUNCENABLE;
412 else
413 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
414
415 val = __raw_readl(reg); 191 val = __raw_readl(reg);
416 192
417 if (debounce) { 193 if (debounce) {
@@ -628,9 +404,6 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
628 else 404 else
629 gpio = d->irq - IH_GPIO_BASE; 405 gpio = d->irq - IH_GPIO_BASE;
630 406
631 if (check_gpio(gpio) < 0)
632 return -EINVAL;
633
634 if (type & ~IRQ_TYPE_SENSE_MASK) 407 if (type & ~IRQ_TYPE_SENSE_MASK)
635 return -EINVAL; 408 return -EINVAL;
636 409
@@ -641,7 +414,7 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
641 414
642 bank = irq_data_get_irq_chip_data(d); 415 bank = irq_data_get_irq_chip_data(d);
643 spin_lock_irqsave(&bank->lock, flags); 416 spin_lock_irqsave(&bank->lock, flags);
644 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); 417 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
645 spin_unlock_irqrestore(&bank->lock, flags); 418 spin_unlock_irqrestore(&bank->lock, flags);
646 419
647 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 420 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
@@ -656,195 +429,81 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
656{ 429{
657 void __iomem *reg = bank->base; 430 void __iomem *reg = bank->base;
658 431
659 switch (bank->method) { 432 reg += bank->regs->irqstatus;
660#ifdef CONFIG_ARCH_OMAP1
661 case METHOD_MPUIO:
662 /* MPUIO irqstatus is reset by reading the status register,
663 * so do nothing here */
664 return;
665#endif
666#ifdef CONFIG_ARCH_OMAP15XX
667 case METHOD_GPIO_1510:
668 reg += OMAP1510_GPIO_INT_STATUS;
669 break;
670#endif
671#ifdef CONFIG_ARCH_OMAP16XX
672 case METHOD_GPIO_1610:
673 reg += OMAP1610_GPIO_IRQSTATUS1;
674 break;
675#endif
676#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
677 case METHOD_GPIO_7XX:
678 reg += OMAP7XX_GPIO_INT_STATUS;
679 break;
680#endif
681#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
682 case METHOD_GPIO_24XX:
683 reg += OMAP24XX_GPIO_IRQSTATUS1;
684 break;
685#endif
686#if defined(CONFIG_ARCH_OMAP4)
687 case METHOD_GPIO_44XX:
688 reg += OMAP4_GPIO_IRQSTATUS0;
689 break;
690#endif
691 default:
692 WARN_ON(1);
693 return;
694 }
695 __raw_writel(gpio_mask, reg); 433 __raw_writel(gpio_mask, reg);
696 434
697 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 435 /* Workaround for clearing DSP GPIO interrupts to allow retention */
698 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 436 if (bank->regs->irqstatus2) {
699 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; 437 reg = bank->base + bank->regs->irqstatus2;
700 else if (cpu_is_omap44xx())
701 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
702
703 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
704 __raw_writel(gpio_mask, reg); 438 __raw_writel(gpio_mask, reg);
439 }
705 440
706 /* Flush posted write for the irq status to avoid spurious interrupts */ 441 /* Flush posted write for the irq status to avoid spurious interrupts */
707 __raw_readl(reg); 442 __raw_readl(reg);
708 }
709} 443}
710 444
711static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) 445static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
712{ 446{
713 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); 447 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
714} 448}
715 449
716static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) 450static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
717{ 451{
718 void __iomem *reg = bank->base; 452 void __iomem *reg = bank->base;
719 int inv = 0;
720 u32 l; 453 u32 l;
721 u32 mask; 454 u32 mask = (1 << bank->width) - 1;
722
723 switch (bank->method) {
724#ifdef CONFIG_ARCH_OMAP1
725 case METHOD_MPUIO:
726 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
727 mask = 0xffff;
728 inv = 1;
729 break;
730#endif
731#ifdef CONFIG_ARCH_OMAP15XX
732 case METHOD_GPIO_1510:
733 reg += OMAP1510_GPIO_INT_MASK;
734 mask = 0xffff;
735 inv = 1;
736 break;
737#endif
738#ifdef CONFIG_ARCH_OMAP16XX
739 case METHOD_GPIO_1610:
740 reg += OMAP1610_GPIO_IRQENABLE1;
741 mask = 0xffff;
742 break;
743#endif
744#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
745 case METHOD_GPIO_7XX:
746 reg += OMAP7XX_GPIO_INT_MASK;
747 mask = 0xffffffff;
748 inv = 1;
749 break;
750#endif
751#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
752 case METHOD_GPIO_24XX:
753 reg += OMAP24XX_GPIO_IRQENABLE1;
754 mask = 0xffffffff;
755 break;
756#endif
757#if defined(CONFIG_ARCH_OMAP4)
758 case METHOD_GPIO_44XX:
759 reg += OMAP4_GPIO_IRQSTATUSSET0;
760 mask = 0xffffffff;
761 break;
762#endif
763 default:
764 WARN_ON(1);
765 return 0;
766 }
767 455
456 reg += bank->regs->irqenable;
768 l = __raw_readl(reg); 457 l = __raw_readl(reg);
769 if (inv) 458 if (bank->regs->irqenable_inv)
770 l = ~l; 459 l = ~l;
771 l &= mask; 460 l &= mask;
772 return l; 461 return l;
773} 462}
774 463
775static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) 464static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
776{ 465{
777 void __iomem *reg = bank->base; 466 void __iomem *reg = bank->base;
778 u32 l; 467 u32 l;
779 468
780 switch (bank->method) { 469 if (bank->regs->set_irqenable) {
781#ifdef CONFIG_ARCH_OMAP1 470 reg += bank->regs->set_irqenable;
782 case METHOD_MPUIO: 471 l = gpio_mask;
783 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride; 472 } else {
784 l = __raw_readl(reg); 473 reg += bank->regs->irqenable;
785 if (enable)
786 l &= ~(gpio_mask);
787 else
788 l |= gpio_mask;
789 break;
790#endif
791#ifdef CONFIG_ARCH_OMAP15XX
792 case METHOD_GPIO_1510:
793 reg += OMAP1510_GPIO_INT_MASK;
794 l = __raw_readl(reg); 474 l = __raw_readl(reg);
795 if (enable) 475 if (bank->regs->irqenable_inv)
796 l &= ~(gpio_mask); 476 l &= ~gpio_mask;
797 else 477 else
798 l |= gpio_mask; 478 l |= gpio_mask;
799 break; 479 }
800#endif 480
801#ifdef CONFIG_ARCH_OMAP16XX 481 __raw_writel(l, reg);
802 case METHOD_GPIO_1610: 482}
803 if (enable) 483
804 reg += OMAP1610_GPIO_SET_IRQENABLE1; 484static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
805 else 485{
806 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; 486 void __iomem *reg = bank->base;
487 u32 l;
488
489 if (bank->regs->clr_irqenable) {
490 reg += bank->regs->clr_irqenable;
807 l = gpio_mask; 491 l = gpio_mask;
808 break; 492 } else {
809#endif 493 reg += bank->regs->irqenable;
810#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
811 case METHOD_GPIO_7XX:
812 reg += OMAP7XX_GPIO_INT_MASK;
813 l = __raw_readl(reg); 494 l = __raw_readl(reg);
814 if (enable) 495 if (bank->regs->irqenable_inv)
815 l &= ~(gpio_mask);
816 else
817 l |= gpio_mask; 496 l |= gpio_mask;
818 break;
819#endif
820#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
821 case METHOD_GPIO_24XX:
822 if (enable)
823 reg += OMAP24XX_GPIO_SETIRQENABLE1;
824 else
825 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
826 l = gpio_mask;
827 break;
828#endif
829#ifdef CONFIG_ARCH_OMAP4
830 case METHOD_GPIO_44XX:
831 if (enable)
832 reg += OMAP4_GPIO_IRQSTATUSSET0;
833 else 497 else
834 reg += OMAP4_GPIO_IRQSTATUSCLR0; 498 l &= ~gpio_mask;
835 l = gpio_mask;
836 break;
837#endif
838 default:
839 WARN_ON(1);
840 return;
841 } 499 }
500
842 __raw_writel(l, reg); 501 __raw_writel(l, reg);
843} 502}
844 503
845static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) 504static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
846{ 505{
847 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); 506 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
848} 507}
849 508
850/* 509/*
@@ -857,50 +516,32 @@ static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int ena
857 */ 516 */
858static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) 517static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
859{ 518{
860 unsigned long uninitialized_var(flags); 519 u32 gpio_bit = GPIO_BIT(bank, gpio);
520 unsigned long flags;
861 521
862 switch (bank->method) { 522 if (bank->non_wakeup_gpios & gpio_bit) {
863#ifdef CONFIG_ARCH_OMAP16XX 523 dev_err(bank->dev,
864 case METHOD_MPUIO: 524 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
865 case METHOD_GPIO_1610:
866 spin_lock_irqsave(&bank->lock, flags);
867 if (enable)
868 bank->suspend_wakeup |= (1 << gpio);
869 else
870 bank->suspend_wakeup &= ~(1 << gpio);
871 spin_unlock_irqrestore(&bank->lock, flags);
872 return 0;
873#endif
874#ifdef CONFIG_ARCH_OMAP2PLUS
875 case METHOD_GPIO_24XX:
876 case METHOD_GPIO_44XX:
877 if (bank->non_wakeup_gpios & (1 << gpio)) {
878 printk(KERN_ERR "Unable to modify wakeup on "
879 "non-wakeup GPIO%d\n",
880 (bank - gpio_bank) * 32 + gpio);
881 return -EINVAL;
882 }
883 spin_lock_irqsave(&bank->lock, flags);
884 if (enable)
885 bank->suspend_wakeup |= (1 << gpio);
886 else
887 bank->suspend_wakeup &= ~(1 << gpio);
888 spin_unlock_irqrestore(&bank->lock, flags);
889 return 0;
890#endif
891 default:
892 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
893 bank->method);
894 return -EINVAL; 525 return -EINVAL;
895 } 526 }
527
528 spin_lock_irqsave(&bank->lock, flags);
529 if (enable)
530 bank->suspend_wakeup |= gpio_bit;
531 else
532 bank->suspend_wakeup &= ~gpio_bit;
533
534 spin_unlock_irqrestore(&bank->lock, flags);
535
536 return 0;
896} 537}
897 538
898static void _reset_gpio(struct gpio_bank *bank, int gpio) 539static void _reset_gpio(struct gpio_bank *bank, int gpio)
899{ 540{
900 _set_gpio_direction(bank, get_gpio_index(gpio), 1); 541 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
901 _set_gpio_irqenable(bank, gpio, 0); 542 _set_gpio_irqenable(bank, gpio, 0);
902 _clear_gpio_irqstatus(bank, gpio); 543 _clear_gpio_irqstatus(bank, gpio);
903 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); 544 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
904} 545}
905 546
906/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ 547/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
@@ -910,10 +551,8 @@ static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
910 struct gpio_bank *bank; 551 struct gpio_bank *bank;
911 int retval; 552 int retval;
912 553
913 if (check_gpio(gpio) < 0)
914 return -ENODEV;
915 bank = irq_data_get_irq_chip_data(d); 554 bank = irq_data_get_irq_chip_data(d);
916 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); 555 retval = _set_gpio_wakeup(bank, gpio, enable);
917 556
918 return retval; 557 return retval;
919} 558}
@@ -1029,31 +668,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1029 chained_irq_enter(chip, desc); 668 chained_irq_enter(chip, desc);
1030 669
1031 bank = irq_get_handler_data(irq); 670 bank = irq_get_handler_data(irq);
1032#ifdef CONFIG_ARCH_OMAP1 671 isr_reg = bank->base + bank->regs->irqstatus;
1033 if (bank->method == METHOD_MPUIO)
1034 isr_reg = bank->base +
1035 OMAP_MPUIO_GPIO_INT / bank->stride;
1036#endif
1037#ifdef CONFIG_ARCH_OMAP15XX
1038 if (bank->method == METHOD_GPIO_1510)
1039 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1040#endif
1041#if defined(CONFIG_ARCH_OMAP16XX)
1042 if (bank->method == METHOD_GPIO_1610)
1043 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1044#endif
1045#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1046 if (bank->method == METHOD_GPIO_7XX)
1047 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1048#endif
1049#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1050 if (bank->method == METHOD_GPIO_24XX)
1051 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1052#endif
1053#if defined(CONFIG_ARCH_OMAP4)
1054 if (bank->method == METHOD_GPIO_44XX)
1055 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1056#endif
1057 672
1058 if (WARN_ON(!isr_reg)) 673 if (WARN_ON(!isr_reg))
1059 goto exit; 674 goto exit;
@@ -1075,9 +690,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1075 /* clear edge sensitive interrupts before handler(s) are 690 /* clear edge sensitive interrupts before handler(s) are
1076 called so that we don't miss any interrupt occurred while 691 called so that we don't miss any interrupt occurred while
1077 executing them */ 692 executing them */
1078 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); 693 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
1079 _clear_gpio_irqbank(bank, isr_saved & ~level_mask); 694 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1080 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); 695 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
1081 696
1082 /* if there is only edge sensitive GPIO pin interrupts 697 /* if there is only edge sensitive GPIO pin interrupts
1083 configured, we could unmask GPIO bank interrupt immediately */ 698 configured, we could unmask GPIO bank interrupt immediately */
@@ -1093,7 +708,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1093 708
1094 gpio_irq = bank->virtual_irq_start; 709 gpio_irq = bank->virtual_irq_start;
1095 for (; isr != 0; isr >>= 1, gpio_irq++) { 710 for (; isr != 0; isr >>= 1, gpio_irq++) {
1096 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq)); 711 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
1097 712
1098 if (!(isr & 1)) 713 if (!(isr & 1))
1099 continue; 714 continue;
@@ -1149,7 +764,7 @@ static void gpio_mask_irq(struct irq_data *d)
1149 764
1150 spin_lock_irqsave(&bank->lock, flags); 765 spin_lock_irqsave(&bank->lock, flags);
1151 _set_gpio_irqenable(bank, gpio, 0); 766 _set_gpio_irqenable(bank, gpio, 0);
1152 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); 767 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
1153 spin_unlock_irqrestore(&bank->lock, flags); 768 spin_unlock_irqrestore(&bank->lock, flags);
1154} 769}
1155 770
@@ -1157,13 +772,13 @@ static void gpio_unmask_irq(struct irq_data *d)
1157{ 772{
1158 unsigned int gpio = d->irq - IH_GPIO_BASE; 773 unsigned int gpio = d->irq - IH_GPIO_BASE;
1159 struct gpio_bank *bank = irq_data_get_irq_chip_data(d); 774 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1160 unsigned int irq_mask = 1 << get_gpio_index(gpio); 775 unsigned int irq_mask = GPIO_BIT(bank, gpio);
1161 u32 trigger = irqd_get_trigger_type(d); 776 u32 trigger = irqd_get_trigger_type(d);
1162 unsigned long flags; 777 unsigned long flags;
1163 778
1164 spin_lock_irqsave(&bank->lock, flags); 779 spin_lock_irqsave(&bank->lock, flags);
1165 if (trigger) 780 if (trigger)
1166 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); 781 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
1167 782
1168 /* For level-triggered GPIOs, the clearing must be done after 783 /* For level-triggered GPIOs, the clearing must be done after
1169 * the HW source is cleared, thus after the handler has run */ 784 * the HW source is cleared, thus after the handler has run */
@@ -1190,45 +805,8 @@ static struct irq_chip gpio_irq_chip = {
1190 805
1191#ifdef CONFIG_ARCH_OMAP1 806#ifdef CONFIG_ARCH_OMAP1
1192 807
1193/* MPUIO uses the always-on 32k clock */
1194
1195static void mpuio_ack_irq(struct irq_data *d)
1196{
1197 /* The ISR is reset automatically, so do nothing here. */
1198}
1199
1200static void mpuio_mask_irq(struct irq_data *d)
1201{
1202 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1203 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1204
1205 _set_gpio_irqenable(bank, gpio, 0);
1206}
1207
1208static void mpuio_unmask_irq(struct irq_data *d)
1209{
1210 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1211 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1212
1213 _set_gpio_irqenable(bank, gpio, 1);
1214}
1215
1216static struct irq_chip mpuio_irq_chip = {
1217 .name = "MPUIO",
1218 .irq_ack = mpuio_ack_irq,
1219 .irq_mask = mpuio_mask_irq,
1220 .irq_unmask = mpuio_unmask_irq,
1221 .irq_set_type = gpio_irq_type,
1222#ifdef CONFIG_ARCH_OMAP16XX
1223 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1224 .irq_set_wake = gpio_wake_enable,
1225#endif
1226};
1227
1228
1229#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) 808#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1230 809
1231
1232#ifdef CONFIG_ARCH_OMAP16XX 810#ifdef CONFIG_ARCH_OMAP16XX
1233 811
1234#include <linux/platform_device.h> 812#include <linux/platform_device.h>
@@ -1288,7 +866,7 @@ static struct platform_device omap_mpuio_device = {
1288 866
1289static inline void mpuio_init(void) 867static inline void mpuio_init(void)
1290{ 868{
1291 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0)); 869 struct gpio_bank *bank = &gpio_bank[0];
1292 platform_set_drvdata(&omap_mpuio_device, bank); 870 platform_set_drvdata(&omap_mpuio_device, bank);
1293 871
1294 if (platform_driver_register(&omap_mpuio_driver) == 0) 872 if (platform_driver_register(&omap_mpuio_driver) == 0)
@@ -1301,8 +879,6 @@ static inline void mpuio_init(void) {}
1301 879
1302#else 880#else
1303 881
1304extern struct irq_chip mpuio_irq_chip;
1305
1306#define bank_is_mpuio(bank) 0 882#define bank_is_mpuio(bank) 0
1307static inline void mpuio_init(void) {} 883static inline void mpuio_init(void) {}
1308 884
@@ -1328,31 +904,8 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset)
1328 904
1329static int gpio_is_input(struct gpio_bank *bank, int mask) 905static int gpio_is_input(struct gpio_bank *bank, int mask)
1330{ 906{
1331 void __iomem *reg = bank->base; 907 void __iomem *reg = bank->base + bank->regs->direction;
1332 908
1333 switch (bank->method) {
1334 case METHOD_MPUIO:
1335 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1336 break;
1337 case METHOD_GPIO_1510:
1338 reg += OMAP1510_GPIO_DIR_CONTROL;
1339 break;
1340 case METHOD_GPIO_1610:
1341 reg += OMAP1610_GPIO_DIRECTION;
1342 break;
1343 case METHOD_GPIO_7XX:
1344 reg += OMAP7XX_GPIO_DIR_CONTROL;
1345 break;
1346 case METHOD_GPIO_24XX:
1347 reg += OMAP24XX_GPIO_OE;
1348 break;
1349 case METHOD_GPIO_44XX:
1350 reg += OMAP4_GPIO_OE;
1351 break;
1352 default:
1353 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1354 return -EINVAL;
1355 }
1356 return __raw_readl(reg) & mask; 909 return __raw_readl(reg) & mask;
1357} 910}
1358 911
@@ -1364,9 +917,9 @@ static int gpio_get(struct gpio_chip *chip, unsigned offset)
1364 u32 mask; 917 u32 mask;
1365 918
1366 gpio = chip->base + offset; 919 gpio = chip->base + offset;
1367 bank = get_gpio_bank(gpio); 920 bank = container_of(chip, struct gpio_bank, chip);
1368 reg = bank->base; 921 reg = bank->base;
1369 mask = 1 << get_gpio_index(gpio); 922 mask = GPIO_BIT(bank, gpio);
1370 923
1371 if (gpio_is_input(bank, mask)) 924 if (gpio_is_input(bank, mask))
1372 return _get_gpio_datain(bank, gpio); 925 return _get_gpio_datain(bank, gpio);
@@ -1381,7 +934,7 @@ static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1381 934
1382 bank = container_of(chip, struct gpio_bank, chip); 935 bank = container_of(chip, struct gpio_bank, chip);
1383 spin_lock_irqsave(&bank->lock, flags); 936 spin_lock_irqsave(&bank->lock, flags);
1384 _set_gpio_dataout(bank, offset, value); 937 bank->set_dataout(bank, offset, value);
1385 _set_gpio_direction(bank, offset, 0); 938 _set_gpio_direction(bank, offset, 0);
1386 spin_unlock_irqrestore(&bank->lock, flags); 939 spin_unlock_irqrestore(&bank->lock, flags);
1387 return 0; 940 return 0;
@@ -1415,7 +968,7 @@ static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1415 968
1416 bank = container_of(chip, struct gpio_bank, chip); 969 bank = container_of(chip, struct gpio_bank, chip);
1417 spin_lock_irqsave(&bank->lock, flags); 970 spin_lock_irqsave(&bank->lock, flags);
1418 _set_gpio_dataout(bank, offset, value); 971 bank->set_dataout(bank, offset, value);
1419 spin_unlock_irqrestore(&bank->lock, flags); 972 spin_unlock_irqrestore(&bank->lock, flags);
1420} 973}
1421 974
@@ -1431,19 +984,17 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1431 984
1432static void __init omap_gpio_show_rev(struct gpio_bank *bank) 985static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1433{ 986{
987 static bool called;
1434 u32 rev; 988 u32 rev;
1435 989
1436 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO)) 990 if (called || bank->regs->revision == USHRT_MAX)
1437 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1438 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1439 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1440 else if (cpu_is_omap44xx())
1441 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1442 else
1443 return; 991 return;
1444 992
1445 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", 993 rev = __raw_readw(bank->base + bank->regs->revision);
994 pr_info("OMAP GPIO hardware version %d.%d\n",
1446 (rev >> 4) & 0x0f, rev & 0x0f); 995 (rev >> 4) & 0x0f, rev & 0x0f);
996
997 called = true;
1447} 998}
1448 999
1449/* This lock class tells lockdep that GPIO irqs are in a different 1000/* This lock class tells lockdep that GPIO irqs are in a different
@@ -1525,6 +1076,30 @@ static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1525 } 1076 }
1526} 1077}
1527 1078
1079static __init void
1080omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1081 unsigned int num)
1082{
1083 struct irq_chip_generic *gc;
1084 struct irq_chip_type *ct;
1085
1086 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1087 handle_simple_irq);
1088 ct = gc->chip_types;
1089
1090 /* NOTE: No ack required, reading IRQ status clears it. */
1091 ct->chip.irq_mask = irq_gc_mask_set_bit;
1092 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1093 ct->chip.irq_set_type = gpio_irq_type;
1094 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1095 if (cpu_is_omap16xx())
1096 ct->chip.irq_set_wake = gpio_wake_enable,
1097
1098 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1099 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1100 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1101}
1102
1528static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) 1103static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1529{ 1104{
1530 int j; 1105 int j;
@@ -1552,22 +1127,23 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1552 } else { 1127 } else {
1553 bank->chip.label = "gpio"; 1128 bank->chip.label = "gpio";
1554 bank->chip.base = gpio; 1129 bank->chip.base = gpio;
1555 gpio += bank_width; 1130 gpio += bank->width;
1556 } 1131 }
1557 bank->chip.ngpio = bank_width; 1132 bank->chip.ngpio = bank->width;
1558 1133
1559 gpiochip_add(&bank->chip); 1134 gpiochip_add(&bank->chip);
1560 1135
1561 for (j = bank->virtual_irq_start; 1136 for (j = bank->virtual_irq_start;
1562 j < bank->virtual_irq_start + bank_width; j++) { 1137 j < bank->virtual_irq_start + bank->width; j++) {
1563 irq_set_lockdep_class(j, &gpio_lock_class); 1138 irq_set_lockdep_class(j, &gpio_lock_class);
1564 irq_set_chip_data(j, bank); 1139 irq_set_chip_data(j, bank);
1565 if (bank_is_mpuio(bank)) 1140 if (bank_is_mpuio(bank)) {
1566 irq_set_chip(j, &mpuio_irq_chip); 1141 omap_mpuio_alloc_gc(bank, j, bank->width);
1567 else 1142 } else {
1568 irq_set_chip(j, &gpio_irq_chip); 1143 irq_set_chip(j, &gpio_irq_chip);
1569 irq_set_handler(j, handle_simple_irq); 1144 irq_set_handler(j, handle_simple_irq);
1570 set_irq_flags(j, IRQF_VALID); 1145 set_irq_flags(j, IRQF_VALID);
1146 }
1571 } 1147 }
1572 irq_set_chained_handler(bank->irq, gpio_irq_handler); 1148 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1573 irq_set_handler_data(bank->irq, bank); 1149 irq_set_handler_data(bank->irq, bank);
@@ -1609,7 +1185,14 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
1609 bank->dev = &pdev->dev; 1185 bank->dev = &pdev->dev;
1610 bank->dbck_flag = pdata->dbck_flag; 1186 bank->dbck_flag = pdata->dbck_flag;
1611 bank->stride = pdata->bank_stride; 1187 bank->stride = pdata->bank_stride;
1612 bank_width = pdata->bank_width; 1188 bank->width = pdata->bank_width;
1189
1190 bank->regs = pdata->regs;
1191
1192 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1193 bank->set_dataout = _set_gpio_dataout_reg;
1194 else
1195 bank->set_dataout = _set_gpio_dataout_mask;
1613 1196
1614 spin_lock_init(&bank->lock); 1197 spin_lock_init(&bank->lock);
1615 1198
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 07:33:52 -0500