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authorLinus Torvalds <torvalds@linux-foundation.org>2015-04-22 12:24:55 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-04-22 12:24:55 -0400
commit8b3c8ba3d8c2680dab5363a80c024965cac08b1e (patch)
tree18150efb36891e6e76e2cad89c1b2fcc5faeae93
parentd34dc4f9e88e4b6beefb819e4e743fd6160a9b75 (diff)
parent48c1078509b47b38802329028ccfd77783bcff99 (diff)
Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late changes from Olof Johansson: "We were expecting to sit on this branch through most of the merge window since the contents was merged into our tree late, but we ended up sitting on all of our contents so it can go in with the rest. The contents here is: - a large branch of cleanups of the CM/PRM blocks on OMAP. - a couple of patches plumbing up CM/PRM on OMAP5 and DRA7. - a branch with DT updates for Freescale i.MX. including some shuffling from .dts to .dtsi (include) files that causes a little churn" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (78 commits) ARM: OMAP2+: Fix booting with configs that don't have MFD_SYSCON ARM: OMAP4+: control: add support for initializing control module via DT ARM: dts: dra7: add minimal l4 bus layout with control module support ARM: dts: omap5: add minimal l4 bus layout with control module support ARM: OMAP4+: control: remove support for legacy pad read/write ARM: OMAP4: display: convert display to use syscon for dsi muxing ARM: dts: omap4: add minimal l4 bus layout with control module support ARM: dts: am4372: add minimal l4 bus layout with control module support ARM: dts: am43xx-epos-evm: fix pinmux node layout ARM: dts: am33xx: add minimal l4 bus layout with control module support ARM: dts: omap3: add minimal l4 bus layout with control module support ARM: dts: omap24xx: add minimal l4 bus layout with control module support ARM: OMAP2+: control: add syscon support for register accesses ARM: OMAP2+: id: cache omap_type value ARM: OMAP2+: control: remove API for getting control module base address ARM: OMAP2+: clock: add low-level support for regmap ARM: OMAP4+: PRM: get rid of cpu_is_omap44xx calls from interrupt init ARM: OMAP4+: PRM: setup prm_features from the PRM init time flags ARM: OMAP2+: CM: move SoC specific init calls within a generic API ARM: OMAP4+: PRM: determine prm_device_inst based on DT compatibility ...
-rw-r--r--Documentation/devicetree/bindings/arm/omap/ctrl.txt79
-rw-r--r--Documentation/devicetree/bindings/arm/omap/l4.txt26
-rw-r--r--Documentation/devicetree/bindings/arm/omap/prcm.txt6
-rw-r--r--arch/arm/boot/dts/Makefile4
-rw-r--r--arch/arm/boot/dts/am33xx-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi87
-rw-r--r--arch/arm/boot/dts/am3517.dtsi2
-rw-r--r--arch/arm/boot/dts/am35xx-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/am4372.dtsi85
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts84
-rw-r--r--arch/arm/boot/dts/am43xx-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/dra7.dtsi156
-rw-r--r--arch/arm/boot/dts/imx25-pdk.dts58
-rw-r--r--arch/arm/boot/dts/imx25-pinfunc.h86
-rw-r--r--arch/arm/boot/dts/imx27.dtsi2
-rw-r--r--arch/arm/boot/dts/imx28-apf28.dts2
-rw-r--r--arch/arm/boot/dts/imx28-apf28dev.dts30
-rw-r--r--arch/arm/boot/dts/imx28.dtsi14
-rw-r--r--arch/arm/boot/dts/imx35.dtsi1
-rw-r--r--arch/arm/boot/dts/imx50.dtsi3
-rw-r--r--arch/arm/boot/dts/imx51.dtsi3
-rw-r--r--arch/arm/boot/dts/imx53.dtsi3
-rw-r--r--arch/arm/boot/dts/imx6dl-aristainetos_4.dts4
-rw-r--r--arch/arm/boot/dts/imx6dl-aristainetos_7.dts4
-rw-r--r--arch/arm/boot/dts/imx6dl-cubox-i.dts38
-rw-r--r--arch/arm/boot/dts/imx6dl-hummingboard.dts38
-rw-r--r--arch/arm/boot/dts/imx6q-cubox-i.dts38
-rw-r--r--arch/arm/boot/dts/imx6q-hummingboard.dts38
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi20
-rw-r--r--arch/arm/boot/dts/imx6qdl-cubox-i.dtsi62
-rw-r--r--arch/arm/boot/dts/imx6qdl-hummingboard.dtsi101
-rw-r--r--arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi38
-rw-r--r--arch/arm/boot/dts/imx6qdl-microsom.dtsi38
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi35
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi49
-rw-r--r--arch/arm/boot/dts/imx6sl-warp.dts262
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi13
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb-reva.dts143
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dts603
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dtsi562
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi9
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi80
-rw-r--r--arch/arm/boot/dts/omap2430-clocks.dtsi8
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi107
-rw-r--r--arch/arm/boot/dts/omap24xx-clocks.dtsi6
-rw-r--r--arch/arm/boot/dts/omap3.dtsi96
-rw-r--r--arch/arm/boot/dts/omap34xx.dtsi2
-rw-r--r--arch/arm/boot/dts/omap36xx.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3xxx-clocks.dtsi13
-rw-r--r--arch/arm/boot/dts/omap4.dtsi200
-rw-r--r--arch/arm/boot/dts/omap5.dtsi182
-rw-r--r--arch/arm/boot/dts/vf-colibri-eval-v3.dtsi31
-rw-r--r--arch/arm/boot/dts/vf-colibri.dtsi15
-rw-r--r--arch/arm/boot/dts/vf500.dtsi137
-rw-r--r--arch/arm/boot/dts/vfxxx.dtsi64
-rw-r--r--arch/arm/mach-imx/common.h2
-rw-r--r--arch/arm/mach-imx/gpc.c140
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c2
-rw-r--r--arch/arm/mach-imx/mach-imx6sl.c2
-rw-r--r--arch/arm/mach-imx/mach-imx6sx.c2
-rw-r--r--arch/arm/mach-imx/pm-imx6.c6
-rw-r--r--arch/arm/mach-omap2/Kconfig1
-rw-r--r--arch/arm/mach-omap2/clock.c111
-rw-r--r--arch/arm/mach-omap2/clock.h8
-rw-r--r--arch/arm/mach-omap2/cm.h2
-rw-r--r--arch/arm/mach-omap2/cm2xxx.c2
-rw-r--r--arch/arm/mach-omap2/cm2xxx.h2
-rw-r--r--arch/arm/mach-omap2/cm33xx.c2
-rw-r--r--arch/arm/mach-omap2/cm33xx.h3
-rw-r--r--arch/arm/mach-omap2/cm3xxx.c3
-rw-r--r--arch/arm/mach-omap2/cm3xxx.h2
-rw-r--r--arch/arm/mach-omap2/cm44xx.h3
-rw-r--r--arch/arm/mach-omap2/cm_common.c156
-rw-r--r--arch/arm/mach-omap2/cminst44xx.c6
-rw-r--r--arch/arm/mach-omap2/control.c201
-rw-r--r--arch/arm/mach-omap2/control.h10
-rw-r--r--arch/arm/mach-omap2/display.c15
-rw-r--r--arch/arm/mach-omap2/id.c5
-rw-r--r--arch/arm/mach-omap2/io.c112
-rw-r--r--arch/arm/mach-omap2/pm24xx.c24
-rw-r--r--arch/arm/mach-omap2/pm34xx.c18
-rw-r--r--arch/arm/mach-omap2/prcm-common.h20
-rw-r--r--arch/arm/mach-omap2/prm.h27
-rw-r--r--arch/arm/mach-omap2/prm2xxx.c6
-rw-r--r--arch/arm/mach-omap2/prm2xxx.h4
-rw-r--r--arch/arm/mach-omap2/prm33xx.c2
-rw-r--r--arch/arm/mach-omap2/prm33xx.h2
-rw-r--r--arch/arm/mach-omap2/prm3xxx.c20
-rw-r--r--arch/arm/mach-omap2/prm3xxx.h7
-rw-r--r--arch/arm/mach-omap2/prm44xx.c70
-rw-r--r--arch/arm/mach-omap2/prm44xx.h1
-rw-r--r--arch/arm/mach-omap2/prm44xx_54xx.h8
-rw-r--r--arch/arm/mach-omap2/prm54xx.h1
-rw-r--r--arch/arm/mach-omap2/prm7xx.h2
-rw-r--r--arch/arm/mach-omap2/prm_common.c258
-rw-r--r--arch/arm/mach-omap2/prminst44xx.c18
-rw-r--r--arch/arm/mach-omap2/prminst44xx.h1
-rw-r--r--arch/arm/mach-omap2/vp.h9
-rw-r--r--arch/arm/mach-omap2/vp3xxx_data.c4
-rw-r--r--arch/arm/mach-omap2/vp44xx_data.c4
-rw-r--r--include/linux/clk/ti.h6
101 files changed, 3510 insertions, 1575 deletions
diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
new file mode 100644
index 000000000000..3a4e5901ce31
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
@@ -0,0 +1,79 @@
1OMAP Control Module bindings
2
3Control Module contains miscellaneous features under it based on SoC type.
4Pincontrol is one common feature, and it has a specialized support
5described in [1]. Typically some clock nodes are also under control module.
6Syscon is used to share register level access to drivers external to
7control module driver itself.
8
9See [2] for documentation about clock/clockdomain nodes.
10
11[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
12[2] Documentation/devicetree/bindings/clock/ti/*
13
14Required properties:
15- compatible: Must be one of:
16 "ti,am3-scm"
17 "ti,am4-scm"
18 "ti,dm814-scrm"
19 "ti,dm816-scrm"
20 "ti,omap2-scm"
21 "ti,omap3-scm"
22 "ti,omap4-scm-core"
23 "ti,omap4-scm-padconf-core"
24 "ti,omap5-scm-core"
25 "ti,omap5-scm-padconf-core"
26 "ti,dra7-scm-core"
27- reg: Contains Control Module register address range
28 (base address and length)
29
30Optional properties:
31- clocks: clocks for this module
32- clockdomains: clockdomains for this module
33
34Examples:
35
36scm: scm@2000 {
37 compatible = "ti,omap3-scm", "simple-bus";
38 reg = <0x2000 0x2000>;
39 #address-cells = <1>;
40 #size-cells = <1>;
41 ranges = <0 0x2000 0x2000>;
42
43 omap3_pmx_core: pinmux@30 {
44 compatible = "ti,omap3-padconf",
45 "pinctrl-single";
46 reg = <0x30 0x230>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49 #interrupt-cells = <1>;
50 interrupt-controller;
51 pinctrl-single,register-width = <16>;
52 pinctrl-single,function-mask = <0xff1f>;
53 };
54
55 scm_conf: scm_conf@270 {
56 compatible = "syscon";
57 reg = <0x270 0x330>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60
61 scm_clocks: clocks {
62 #address-cells = <1>;
63 #size-cells = <0>;
64 };
65 };
66
67 scm_clockdomains: clockdomains {
68 };
69}
70
71&scm_clocks {
72 mcbsp5_mux_fck: mcbsp5_mux_fck {
73 #clock-cells = <0>;
74 compatible = "ti,composite-mux-clock";
75 clocks = <&core_96m_fck>, <&mcbsp_clks>;
76 ti,bit-shift = <4>;
77 reg = <0x02d8>;
78 };
79};
diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt b/Documentation/devicetree/bindings/arm/omap/l4.txt
new file mode 100644
index 000000000000..b4f8a16e7e3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/l4.txt
@@ -0,0 +1,26 @@
1L4 interconnect bindings
2
3These bindings describe the OMAP SoCs L4 interconnect bus.
4
5Required properties:
6- compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
7 Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
8 Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
9 Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
10 Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
11 Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
12 Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
13 Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus
14 Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus
15 Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus
16 Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus
17- ranges : contains the IO map range for the bus
18
19Examples:
20
21l4: l4@48000000 {
22 compatible "ti,omap2-l4", "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges = <0 0x48000000 0x100000>;
26};
diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt
index 79074dac684a..3eb6d7afff14 100644
--- a/Documentation/devicetree/bindings/arm/omap/prcm.txt
+++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt
@@ -10,14 +10,10 @@ documentation about the individual clock/clockdomain nodes.
10Required properties: 10Required properties:
11- compatible: Must be one of: 11- compatible: Must be one of:
12 "ti,am3-prcm" 12 "ti,am3-prcm"
13 "ti,am3-scrm"
14 "ti,am4-prcm" 13 "ti,am4-prcm"
15 "ti,am4-scrm"
16 "ti,omap2-prcm" 14 "ti,omap2-prcm"
17 "ti,omap2-scrm"
18 "ti,omap3-prm" 15 "ti,omap3-prm"
19 "ti,omap3-cm" 16 "ti,omap3-cm"
20 "ti,omap3-scrm"
21 "ti,omap4-cm1" 17 "ti,omap4-cm1"
22 "ti,omap4-prm" 18 "ti,omap4-prm"
23 "ti,omap4-cm2" 19 "ti,omap4-cm2"
@@ -29,6 +25,8 @@ Required properties:
29 "ti,dra7-prm" 25 "ti,dra7-prm"
30 "ti,dra7-cm-core-aon" 26 "ti,dra7-cm-core-aon"
31 "ti,dra7-cm-core" 27 "ti,dra7-cm-core"
28 "ti,dm814-prcm"
29 "ti,dm816-prcm"
32- reg: Contains PRCM module register address range 30- reg: Contains PRCM module register address range
33 (base address and length) 31 (base address and length)
34- clocks: clocks for this module 32- clocks: clocks for this module
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a384cce5c31d..86217db2937a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -307,9 +307,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
307 imx6q-wandboard.dtb \ 307 imx6q-wandboard.dtb \
308 imx6q-wandboard-revb1.dtb 308 imx6q-wandboard-revb1.dtb
309dtb-$(CONFIG_SOC_IMX6SL) += \ 309dtb-$(CONFIG_SOC_IMX6SL) += \
310 imx6sl-evk.dtb 310 imx6sl-evk.dtb \
311 imx6sl-warp.dtb
311dtb-$(CONFIG_SOC_IMX6SX) += \ 312dtb-$(CONFIG_SOC_IMX6SX) += \
312 imx6sx-sabreauto.dtb \ 313 imx6sx-sabreauto.dtb \
314 imx6sx-sdb-reva.dtb \
313 imx6sx-sdb.dtb 315 imx6sx-sdb.dtb
314dtb-$(CONFIG_SOC_LS1021A) += \ 316dtb-$(CONFIG_SOC_LS1021A) += \
315 ls1021a-qds.dtb \ 317 ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 071b56aa0c7e..afb4b3a7bab4 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -7,7 +7,7 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10&scrm_clocks { 10&scm_clocks {
11 sys_clkin_ck: sys_clkin_ck { 11 sys_clkin_ck: sys_clkin_ck {
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 compatible = "ti,mux-clock"; 13 compatible = "ti,mux-clock";
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index acd37057bca9..21fcc440fc1a 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -83,20 +83,6 @@
83 }; 83 };
84 }; 84 };
85 85
86 am33xx_control_module: control_module@4a002000 {
87 compatible = "syscon";
88 reg = <0x44e10000 0x7fc>;
89 };
90
91 am33xx_pinmux: pinmux@44e10800 {
92 compatible = "pinctrl-single";
93 reg = <0x44e10800 0x0238>;
94 #address-cells = <1>;
95 #size-cells = <0>;
96 pinctrl-single,register-width = <32>;
97 pinctrl-single,function-mask = <0x7f>;
98 };
99
100 /* 86 /*
101 * XXX: Use a flat representation of the AM33XX interconnect. 87 * XXX: Use a flat representation of the AM33XX interconnect.
102 * The real AM33XX interconnect network is quite complex. Since 88 * The real AM33XX interconnect network is quite complex. Since
@@ -111,37 +97,58 @@
111 ranges; 97 ranges;
112 ti,hwmods = "l3_main"; 98 ti,hwmods = "l3_main";
113 99
114 prcm: prcm@44e00000 { 100 l4_wkup: l4_wkup@44c00000 {
115 compatible = "ti,am3-prcm"; 101 compatible = "ti,am3-l4-wkup", "simple-bus";
116 reg = <0x44e00000 0x4000>; 102 #address-cells = <1>;
117 103 #size-cells = <1>;
118 prcm_clocks: clocks { 104 ranges = <0 0x44c00000 0x280000>;
119 #address-cells = <1>;
120 #size-cells = <0>;
121 };
122 105
123 prcm_clockdomains: clockdomains { 106 prcm: prcm@200000 {
124 }; 107 compatible = "ti,am3-prcm";
125 }; 108 reg = <0x200000 0x4000>;
126 109
127 scrm: scrm@44e10000 { 110 prcm_clocks: clocks {
128 compatible = "ti,am3-scrm"; 111 #address-cells = <1>;
129 reg = <0x44e10000 0x2000>; 112 #size-cells = <0>;
113 };
130 114
131 scrm_clocks: clocks { 115 prcm_clockdomains: clockdomains {
132 #address-cells = <1>; 116 };
133 #size-cells = <0>;
134 }; 117 };
135 118
136 scrm_clockdomains: clockdomains { 119 scm: scm@210000 {
120 compatible = "ti,am3-scm", "simple-bus";
121 reg = <0x210000 0x2000>;
122 #address-cells = <1>;
123 #size-cells = <1>;
124 ranges = <0 0x210000 0x2000>;
125
126 am33xx_pinmux: pinmux@800 {
127 compatible = "pinctrl-single";
128 reg = <0x800 0x238>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 pinctrl-single,register-width = <32>;
132 pinctrl-single,function-mask = <0x7f>;
133 };
134
135 scm_conf: scm_conf@0 {
136 compatible = "syscon";
137 reg = <0x0 0x800>;
138 #address-cells = <1>;
139 #size-cells = <1>;
140
141 scm_clocks: clocks {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 };
145 };
146
147 scm_clockdomains: clockdomains {
148 };
137 }; 149 };
138 }; 150 };
139 151
140 cm: syscon@44e10000 {
141 compatible = "ti,am33xx-controlmodule", "syscon";
142 reg = <0x44e10000 0x800>;
143 };
144
145 intc: interrupt-controller@48200000 { 152 intc: interrupt-controller@48200000 {
146 compatible = "ti,am33xx-intc"; 153 compatible = "ti,am33xx-intc";
147 interrupt-controller; 154 interrupt-controller;
@@ -350,7 +357,7 @@
350 reg = <0x481cc000 0x2000>; 357 reg = <0x481cc000 0x2000>;
351 clocks = <&dcan0_fck>; 358 clocks = <&dcan0_fck>;
352 clock-names = "fck"; 359 clock-names = "fck";
353 syscon-raminit = <&am33xx_control_module 0x644 0>; 360 syscon-raminit = <&scm_conf 0x644 0>;
354 interrupts = <52>; 361 interrupts = <52>;
355 status = "disabled"; 362 status = "disabled";
356 }; 363 };
@@ -361,7 +368,7 @@
361 reg = <0x481d0000 0x2000>; 368 reg = <0x481d0000 0x2000>;
362 clocks = <&dcan1_fck>; 369 clocks = <&dcan1_fck>;
363 clock-names = "fck"; 370 clock-names = "fck";
364 syscon-raminit = <&am33xx_control_module 0x644 1>; 371 syscon-raminit = <&scm_conf 0x644 1>;
365 interrupts = <55>; 372 interrupts = <55>;
366 status = "disabled"; 373 status = "disabled";
367 }; 374 };
@@ -720,7 +727,7 @@
720 */ 727 */
721 interrupts = <40 41 42 43>; 728 interrupts = <40 41 42 43>;
722 ranges; 729 ranges;
723 syscon = <&cm>; 730 syscon = <&scm_conf>;
724 status = "disabled"; 731 status = "disabled";
725 732
726 davinci_mdio: mdio@4a101000 { 733 davinci_mdio: mdio@4a101000 {
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index c90724bded10..f164dce08755 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -31,7 +31,7 @@
31 status = "disabled"; 31 status = "disabled";
32 reg = <0x5c000000 0x30000>; 32 reg = <0x5c000000 0x30000>;
33 interrupts = <67 68 69 70>; 33 interrupts = <67 68 69 70>;
34 syscon = <&omap3_scm_general>; 34 syscon = <&scm_conf>;
35 ti,davinci-ctrl-reg-offset = <0x10000>; 35 ti,davinci-ctrl-reg-offset = <0x10000>;
36 ti,davinci-ctrl-mod-reg-offset = <0>; 36 ti,davinci-ctrl-mod-reg-offset = <0>;
37 ti,davinci-ctrl-ram-offset = <0x20000>; 37 ti,davinci-ctrl-ram-offset = <0x20000>;
diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
index df489d310b50..518b8fde88b0 100644
--- a/arch/arm/boot/dts/am35xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -7,7 +7,7 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10&scrm_clocks { 10&scm_clocks {
11 emac_ick: emac_ick { 11 emac_ick: emac_ick {
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 compatible = "ti,am35xx-gate-clock"; 13 compatible = "ti,am35xx-gate-clock";
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 1b7bda8c14b1..c80a3e233792 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -66,22 +66,6 @@
66 cache-level = <2>; 66 cache-level = <2>;
67 }; 67 };
68 68
69 am43xx_control_module: control_module@4a002000 {
70 compatible = "syscon";
71 reg = <0x44e10000 0x7f4>;
72 };
73
74 am43xx_pinmux: pinmux@44e10800 {
75 compatible = "ti,am437-padconf", "pinctrl-single";
76 reg = <0x44e10800 0x31c>;
77 #address-cells = <1>;
78 #size-cells = <0>;
79 #interrupt-cells = <1>;
80 interrupt-controller;
81 pinctrl-single,register-width = <32>;
82 pinctrl-single,function-mask = <0xffffffff>;
83 };
84
85 ocp { 69 ocp {
86 compatible = "ti,am4372-l3-noc", "simple-bus"; 70 compatible = "ti,am4372-l3-noc", "simple-bus";
87 #address-cells = <1>; 71 #address-cells = <1>;
@@ -93,29 +77,58 @@
93 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 77 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 78 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
95 79
96 prcm: prcm@44df0000 { 80 l4_wkup: l4_wkup@44c00000 {
97 compatible = "ti,am4-prcm"; 81 compatible = "ti,am4-l4-wkup", "simple-bus";
98 reg = <0x44df0000 0x11000>; 82 #address-cells = <1>;
99 83 #size-cells = <1>;
100 prcm_clocks: clocks { 84 ranges = <0 0x44c00000 0x287000>;
101 #address-cells = <1>;
102 #size-cells = <0>;
103 };
104 85
105 prcm_clockdomains: clockdomains { 86 prcm: prcm@1f0000 {
106 }; 87 compatible = "ti,am4-prcm";
107 }; 88 reg = <0x1f0000 0x11000>;
108 89
109 scrm: scrm@44e10000 { 90 prcm_clocks: clocks {
110 compatible = "ti,am4-scrm"; 91 #address-cells = <1>;
111 reg = <0x44e10000 0x2000>; 92 #size-cells = <0>;
93 };
112 94
113 scrm_clocks: clocks { 95 prcm_clockdomains: clockdomains {
114 #address-cells = <1>; 96 };
115 #size-cells = <0>;
116 }; 97 };
117 98
118 scrm_clockdomains: clockdomains { 99 scm: scm@210000 {
100 compatible = "ti,am4-scm", "simple-bus";
101 reg = <0x210000 0x4000>;
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 0x210000 0x4000>;
105
106 am43xx_pinmux: pinmux@800 {
107 compatible = "ti,am437-padconf",
108 "pinctrl-single";
109 reg = <0x800 0x31c>;
110 #address-cells = <1>;
111 #size-cells = <0>;
112 #interrupt-cells = <1>;
113 interrupt-controller;
114 pinctrl-single,register-width = <32>;
115 pinctrl-single,function-mask = <0xffffffff>;
116 };
117
118 scm_conf: scm_conf@0 {
119 compatible = "syscon";
120 reg = <0x0 0x800>;
121 #address-cells = <1>;
122 #size-cells = <1>;
123
124 scm_clocks: clocks {
125 #address-cells = <1>;
126 #size-cells = <0>;
127 };
128 };
129
130 scm_clockdomains: clockdomains {
131 };
119 }; 132 };
120 }; 133 };
121 134
@@ -942,7 +955,7 @@
942 clocks = <&dcan0_fck>; 955 clocks = <&dcan0_fck>;
943 clock-names = "fck"; 956 clock-names = "fck";
944 reg = <0x481cc000 0x2000>; 957 reg = <0x481cc000 0x2000>;
945 syscon-raminit = <&am43xx_control_module 0x644 0>; 958 syscon-raminit = <&scm_conf 0x644 0>;
946 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 959 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
947 status = "disabled"; 960 status = "disabled";
948 }; 961 };
@@ -953,7 +966,7 @@
953 clocks = <&dcan1_fck>; 966 clocks = <&dcan1_fck>;
954 clock-names = "fck"; 967 clock-names = "fck";
955 reg = <0x481d0000 0x2000>; 968 reg = <0x481d0000 0x2000>;
956 syscon-raminit = <&am43xx_control_module 0x644 1>; 969 syscon-raminit = <&scm_conf 0x644 1>;
957 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 970 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
958 status = "disabled"; 971 status = "disabled";
959 }; 972 };
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 1d7109196872..795d68af6df9 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -69,7 +69,48 @@
69 }; 69 };
70 }; 70 };
71 71
72 am43xx_pinmux: pinmux@44e10800 { 72 matrix_keypad: matrix_keypad@0 {
73 compatible = "gpio-matrix-keypad";
74 debounce-delay-ms = <5>;
75 col-scan-delay-us = <2>;
76
77 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
78 &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
79 &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
80 &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
81
82 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
83 &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
84 &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
85 &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
86
87 linux,keymap = <0x00000201 /* P1 */
88 0x01000204 /* P4 */
89 0x02000207 /* P7 */
90 0x0300020a /* NUMERIC_STAR */
91 0x00010202 /* P2 */
92 0x01010205 /* P5 */
93 0x02010208 /* P8 */
94 0x03010200 /* P0 */
95 0x00020203 /* P3 */
96 0x01020206 /* P6 */
97 0x02020209 /* P9 */
98 0x0302020b /* NUMERIC_POUND */
99 0x00030067 /* UP */
100 0x0103006a /* RIGHT */
101 0x0203006c /* DOWN */
102 0x03030069>; /* LEFT */
103 };
104
105 backlight {
106 compatible = "pwm-backlight";
107 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
108 brightness-levels = <0 51 53 56 62 75 101 152 255>;
109 default-brightness-level = <8>;
110 };
111};
112
113&am43xx_pinmux {
73 cpsw_default: cpsw_default { 114 cpsw_default: cpsw_default {
74 pinctrl-single,pins = < 115 pinctrl-single,pins = <
75 /* Slave 1 */ 116 /* Slave 1 */
@@ -279,47 +320,6 @@
279 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 320 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
280 >; 321 >;
281 }; 322 };
282 };
283
284 matrix_keypad: matrix_keypad@0 {
285 compatible = "gpio-matrix-keypad";
286 debounce-delay-ms = <5>;
287 col-scan-delay-us = <2>;
288
289 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
290 &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
291 &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
292 &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
293
294 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
295 &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
296 &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
297 &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
298
299 linux,keymap = <0x00000201 /* P1 */
300 0x01000204 /* P4 */
301 0x02000207 /* P7 */
302 0x0300020a /* NUMERIC_STAR */
303 0x00010202 /* P2 */
304 0x01010205 /* P5 */
305 0x02010208 /* P8 */
306 0x03010200 /* P0 */
307 0x00020203 /* P3 */
308 0x01020206 /* P6 */
309 0x02020209 /* P9 */
310 0x0302020b /* NUMERIC_POUND */
311 0x00030067 /* UP */
312 0x0103006a /* RIGHT */
313 0x0203006c /* DOWN */
314 0x03030069>; /* LEFT */
315 };
316
317 backlight {
318 compatible = "pwm-backlight";
319 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
320 brightness-levels = <0 51 53 56 62 75 101 152 255>;
321 default-brightness-level = <8>;
322 };
323}; 323};
324 324
325&mmc1 { 325&mmc1 {
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index cfb49686ab6a..d0c0dfa4ec48 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -7,7 +7,7 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10&scrm_clocks { 10&scm_clocks {
11 sys_clkin_ck: sys_clkin_ck { 11 sys_clkin_ck: sys_clkin_ck {
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 compatible = "ti,mux-clock"; 13 compatible = "ti,mux-clock";
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 082882c616e8..5332b57b4950 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -102,17 +102,101 @@
102 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 102 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
103 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 103 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
104 104
105 prm: prm@4ae06000 { 105 l4_cfg: l4@4a000000 {
106 compatible = "ti,dra7-prm"; 106 compatible = "ti,dra7-l4-cfg", "simple-bus";
107 reg = <0x4ae06000 0x3000>; 107 #address-cells = <1>;
108 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 108 #size-cells = <1>;
109 ranges = <0 0x4a000000 0x22c000>;
109 110
110 prm_clocks: clocks { 111 scm: scm@2000 {
112 compatible = "ti,dra7-scm-core", "simple-bus";
113 reg = <0x2000 0x2000>;
111 #address-cells = <1>; 114 #address-cells = <1>;
112 #size-cells = <0>; 115 #size-cells = <1>;
116 ranges = <0 0x2000 0x2000>;
117
118 scm_conf: scm_conf@0 {
119 compatible = "syscon";
120 reg = <0x0 0x1400>;
121 #address-cells = <1>;
122 #size-cells = <1>;
123
124 pbias_regulator: pbias_regulator {
125 compatible = "ti,pbias-omap";
126 reg = <0xe00 0x4>;
127 syscon = <&scm_conf>;
128 pbias_mmc_reg: pbias_mmc_omap5 {
129 regulator-name = "pbias_mmc_omap5";
130 regulator-min-microvolt = <1800000>;
131 regulator-max-microvolt = <3000000>;
132 };
133 };
134 };
135
136 dra7_pmx_core: pinmux@1400 {
137 compatible = "ti,dra7-padconf",
138 "pinctrl-single";
139 reg = <0x1400 0x0464>;
140 #address-cells = <1>;
141 #size-cells = <0>;
142 #interrupt-cells = <1>;
143 interrupt-controller;
144 pinctrl-single,register-width = <32>;
145 pinctrl-single,function-mask = <0x3fffffff>;
146 };
147 };
148
149 cm_core_aon: cm_core_aon@5000 {
150 compatible = "ti,dra7-cm-core-aon";
151 reg = <0x5000 0x2000>;
152
153 cm_core_aon_clocks: clocks {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 };
157
158 cm_core_aon_clockdomains: clockdomains {
159 };
113 }; 160 };
114 161
115 prm_clockdomains: clockdomains { 162 cm_core: cm_core@8000 {
163 compatible = "ti,dra7-cm-core";
164 reg = <0x8000 0x3000>;
165
166 cm_core_clocks: clocks {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 };
170
171 cm_core_clockdomains: clockdomains {
172 };
173 };
174 };
175
176 l4_wkup: l4@4ae00000 {
177 compatible = "ti,dra7-l4-wkup", "simple-bus";
178 #address-cells = <1>;
179 #size-cells = <1>;
180 ranges = <0 0x4ae00000 0x3f000>;
181
182 counter32k: counter@4000 {
183 compatible = "ti,omap-counter32k";
184 reg = <0x4000 0x40>;
185 ti,hwmods = "counter_32k";
186 };
187
188 prm: prm@6000 {
189 compatible = "ti,dra7-prm";
190 reg = <0x6000 0x3000>;
191 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
192
193 prm_clocks: clocks {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 };
197
198 prm_clockdomains: clockdomains {
199 };
116 }; 200 };
117 }; 201 };
118 202
@@ -197,38 +281,6 @@
197 #thermal-sensor-cells = <1>; 281 #thermal-sensor-cells = <1>;
198 }; 282 };
199 283
200 cm_core_aon: cm_core_aon@4a005000 {
201 compatible = "ti,dra7-cm-core-aon";
202 reg = <0x4a005000 0x2000>;
203
204 cm_core_aon_clocks: clocks {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 };
208
209 cm_core_aon_clockdomains: clockdomains {
210 };
211 };
212
213 cm_core: cm_core@4a008000 {
214 compatible = "ti,dra7-cm-core";
215 reg = <0x4a008000 0x3000>;
216
217 cm_core_clocks: clocks {
218 #address-cells = <1>;
219 #size-cells = <0>;
220 };
221
222 cm_core_clockdomains: clockdomains {
223 };
224 };
225
226 counter32k: counter@4ae04000 {
227 compatible = "ti,omap-counter32k";
228 reg = <0x4ae04000 0x40>;
229 ti,hwmods = "counter_32k";
230 };
231
232 dra7_ctrl_core: ctrl_core@4a002000 { 284 dra7_ctrl_core: ctrl_core@4a002000 {
233 compatible = "syscon"; 285 compatible = "syscon";
234 reg = <0x4a002000 0x6d0>; 286 reg = <0x4a002000 0x6d0>;
@@ -239,28 +291,6 @@
239 reg = <0x4a002e00 0x7c>; 291 reg = <0x4a002e00 0x7c>;
240 }; 292 };
241 293
242 pbias_regulator: pbias_regulator {
243 compatible = "ti,pbias-omap";
244 reg = <0 0x4>;
245 syscon = <&dra7_ctrl_general>;
246 pbias_mmc_reg: pbias_mmc_omap5 {
247 regulator-name = "pbias_mmc_omap5";
248 regulator-min-microvolt = <1800000>;
249 regulator-max-microvolt = <3000000>;
250 };
251 };
252
253 dra7_pmx_core: pinmux@4a003400 {
254 compatible = "ti,dra7-padconf", "pinctrl-single";
255 reg = <0x4a003400 0x0464>;
256 #address-cells = <1>;
257 #size-cells = <0>;
258 #interrupt-cells = <1>;
259 interrupt-controller;
260 pinctrl-single,register-width = <32>;
261 pinctrl-single,function-mask = <0x3fffffff>;
262 };
263
264 sdma: dma-controller@4a056000 { 294 sdma: dma-controller@4a056000 {
265 compatible = "ti,omap4430-sdma"; 295 compatible = "ti,omap4430-sdma";
266 reg = <0x4a056000 0x1000>; 296 reg = <0x4a056000 0x1000>;
@@ -1424,7 +1454,7 @@
1424 compatible = "ti,dra7-d_can"; 1454 compatible = "ti,dra7-d_can";
1425 ti,hwmods = "dcan1"; 1455 ti,hwmods = "dcan1";
1426 reg = <0x4ae3c000 0x2000>; 1456 reg = <0x4ae3c000 0x2000>;
1427 syscon-raminit = <&dra7_ctrl_core 0x558 0>; 1457 syscon-raminit = <&scm_conf 0x558 0>;
1428 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1458 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&dcan1_sys_clk_mux>; 1459 clocks = <&dcan1_sys_clk_mux>;
1430 status = "disabled"; 1460 status = "disabled";
@@ -1434,7 +1464,7 @@
1434 compatible = "ti,dra7-d_can"; 1464 compatible = "ti,dra7-d_can";
1435 ti,hwmods = "dcan2"; 1465 ti,hwmods = "dcan2";
1436 reg = <0x48480000 0x2000>; 1466 reg = <0x48480000 0x2000>;
1437 syscon-raminit = <&dra7_ctrl_core 0x558 1>; 1467 syscon-raminit = <&scm_conf 0x558 1>;
1438 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1468 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1439 clocks = <&sys_clkin1>; 1469 clocks = <&sys_clkin1>;
1440 status = "disabled"; 1470 status = "disabled";
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 9c21b1583762..dd45e6971bc3 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -75,6 +75,27 @@
75 mux-int-port = <1>; 75 mux-int-port = <1>;
76 mux-ext-port = <4>; 76 mux-ext-port = <4>;
77 }; 77 };
78
79 wvga: display {
80 model = "CLAA057VC01CW";
81 bits-per-pixel = <16>;
82 fsl,pcr = <0xfa208b80>;
83 bus-width = <18>;
84 native-mode = <&wvga_timings>;
85 display-timings {
86 wvga_timings: 640x480 {
87 hactive = <640>;
88 vactive = <480>;
89 hback-porch = <45>;
90 hfront-porch = <114>;
91 hsync-len = <1>;
92 vback-porch = <33>;
93 vfront-porch = <11>;
94 vsync-len = <1>;
95 clock-frequency = <25200000>;
96 };
97 };
98 };
78}; 99};
79 100
80&audmux { 101&audmux {
@@ -190,6 +211,33 @@
190 >; 211 >;
191 }; 212 };
192 213
214 pinctrl_lcd: lcdgrp {
215 fsl,pins = <
216 MX25_PAD_LD0__LD0 0xe0
217 MX25_PAD_LD1__LD1 0xe0
218 MX25_PAD_LD2__LD2 0xe0
219 MX25_PAD_LD3__LD3 0xe0
220 MX25_PAD_LD4__LD4 0xe0
221 MX25_PAD_LD5__LD5 0xe0
222 MX25_PAD_LD6__LD6 0xe0
223 MX25_PAD_LD7__LD7 0xe0
224 MX25_PAD_LD8__LD8 0xe0
225 MX25_PAD_LD9__LD9 0xe0
226 MX25_PAD_LD10__LD10 0xe0
227 MX25_PAD_LD11__LD11 0xe0
228 MX25_PAD_LD12__LD12 0xe0
229 MX25_PAD_LD13__LD13 0xe0
230 MX25_PAD_LD14__LD14 0xe0
231 MX25_PAD_LD15__LD15 0xe0
232 MX25_PAD_GPIO_E__LD16 0xe0
233 MX25_PAD_GPIO_F__LD17 0xe0
234 MX25_PAD_HSYNC__HSYNC 0xe0
235 MX25_PAD_VSYNC__VSYNC 0xe0
236 MX25_PAD_LSCLK__LSCLK 0xe0
237 MX25_PAD_OE_ACD__OE_ACD 0xe0
238 MX25_PAD_CONTRAST__CONTRAST 0xe0
239 >;
240 };
193 241
194 pinctrl_uart1: uart1grp { 242 pinctrl_uart1: uart1grp {
195 fsl,pins = < 243 fsl,pins = <
@@ -202,6 +250,16 @@
202 }; 250 };
203}; 251};
204 252
253&lcdc {
254 display = <&wvga>;
255 fsl,lpccr = <0x00a903ff>;
256 fsl,lscr1 = <0x00120300>;
257 fsl,dmacr = <0x00020010>;
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_lcd>;
260 status = "okay";
261};
262
205&nfc { 263&nfc {
206 nand-on-flash-bbt; 264 nand-on-flash-bbt;
207 status = "okay"; 265 status = "okay";
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
index 88eebb15da6a..7c4b9f2f9aad 100644
--- a/arch/arm/boot/dts/imx25-pinfunc.h
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -17,48 +17,69 @@
17 * <mux_reg conf_reg input_reg mux_mode input_val> 17 * <mux_reg conf_reg input_reg mux_mode input_val>
18 */ 18 */
19 19
20#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000
21
20#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 22#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
21#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 23#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
22 24
23#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 25#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
24#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 26#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
27#define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
25 28
26#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000 29#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000
27#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000 30#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000
31#define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x16 0x000
32#define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x17 0x000
28 33
29#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000 34#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000
30#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000 35#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000
36#define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x16 0x000
37#define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x17 0x000
31 38
32#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000 39#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000
33#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000 40#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000
41#define MX25_PAD_A16__SIM1_VEN1 0x018 0x000 0x000 0x16 0x000
42#define MX25_PAD_A16__LCDC_REV 0x018 0x000 0x000 0x17 0x000
34 43
35#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000 44#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000
36#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000 45#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000
46#define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x16 0x000
47#define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x17 0x000
37 48
38#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000 49#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000
39#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000 50#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000
51#define MX25_PAD_A18__SIM1_PD1 0x020 0x23c 0x550 0x16 0x000
40#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000 52#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000
41 53
42#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000 54#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000
43#define MX25_PAD_A19__FEC_RX_ER 0x024 0x240 0x518 0x17 0x000
44#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000 55#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000
56#define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x16 0x000
57#define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x17 0x000
45 58
46#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000 59#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000
47#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000 60#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000
61#define MX25_PAD_A20__SIM2_CLK1 0x028 0x244 0x000 0x16 0x000
48#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000 62#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000
49 63
50#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000 64#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000
51#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000 65#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000
66#define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x16 0x000
52#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000 67#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000
53 68
54#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000 69#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000
55#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000 70#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000
71#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000
72#define MX25_PAD_A22__SIM2_VEN1 0x030 0x000 0x000 0x16 0x000
73#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000
56 74
57#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000 75#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000
58#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000 76#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000
77#define MX25_PAD_A23__SIM2_TX1 0x034 0x24c 0x560 0x16 0x000
78#define MX25_PAD_A23__FEC_TDATA3 0x034 0x24c 0x000 0x17 0x000
59 79
60#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000 80#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000
61#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000 81#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000
82#define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x16 0x000
62#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000 83#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000
63 84
64#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000 85#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000
@@ -133,20 +154,25 @@
133#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000 154#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000
134#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000 155#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000
135#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000 156#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000
157#define MX25_PAD_D15__SDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000
136 158
137#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000 159#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000
138#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000 160#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000
139#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000 161#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000
162#define MX25_PAD_D14__SDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000
140 163
141#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000 164#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000
142#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000 165#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000
143#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000 166#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000
167#define MX25_PAD_D13__SDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000
144 168
145#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000 169#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000
146#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000 170#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000
171#define MX25_PAD_D12__SDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000
147 172
148#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000 173#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000
149#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000 174#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000
175#define MX25_PAD_D11__USBOTG_PWR 0x098 0x290 0x000 0x06 0x000
150 176
151#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000 177#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000
152#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000 178#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000
@@ -212,26 +238,33 @@
212 238
213#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000 239#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000
214#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000 240#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000
241#define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000
215 242
216#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000 243#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000
217#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001 244#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001
245#define MX25_PAD_LD9__SDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000
218 246
219#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000 247#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000
220#define MX25_PAD_LD10__FEC_RX_ER 0x0f0 0x2e8 0x518 0x15 0x001 248#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x15 0x001
221 249
222#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000 250#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000
223#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001 251#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001
252#define MX25_PAD_LD11__SDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000
224 253
225#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000 254#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000
255#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000
226#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001 256#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001
227 257
228#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000 258#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000
259#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000
229#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000 260#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000
230 261
231#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000 262#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000
263#define MX25_PAD_LD14__CSPI2_SCLK 0x100 0x2f8 0x494 0x02 0x000
232#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000 264#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000
233 265
234#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000 266#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000
267#define MX25_PAD_LD15__CSPI2_RDY 0x104 0x2fc 0x498 0x02 0x000
235#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001 268#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001
236 269
237#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000 270#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000
@@ -244,6 +277,7 @@
244#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000 277#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000
245 278
246#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000 279#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000
280#define MX25_PAD_OE_ACD__CSPI2_SS0 0x114 0x30c 0x4a4 0x02 0x000
247#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000 281#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000
248 282
249#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000 283#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000
@@ -257,26 +291,31 @@
257 291
258#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000 292#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000
259#define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001 293#define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001
294#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000
260#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000 295#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000
261#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000 296#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
262 297
263#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000 298#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
264#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000 299#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000
300#define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000
265#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000 301#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
266#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001 302#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
267 303
268#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000 304#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000
269#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001 305#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001
306#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000
270#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000 307#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000
271#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000 308#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
272 309
273#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000 310#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
274#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x001 311#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x000
312#define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000
275#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000 313#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000
276#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000 314#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000
277 315
278#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000 316#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000
279#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001 317#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
318#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000
280#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000 319#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000
281 320
282#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000 321#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000
@@ -284,32 +323,32 @@
284#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000 323#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000
285 324
286#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000 325#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000
287#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x001 326#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x000
288#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000 327#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000
289#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000 328#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000
290 329
291#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000 330#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000
292#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x001 331#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x000
293#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000 332#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000
294#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000 333#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000
295 334
296#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000 335#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000
297#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x001 336#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x000
298#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001 337#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001
299#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000 338#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000
300 339
301#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000 340#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000
302#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x001 341#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x000
303#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001 342#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001
304#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000 343#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000
305 344
306#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000 345#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000
307#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x001 346#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x000
308#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001 347#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001
309#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000 348#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000
310 349
311#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000 350#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000
312#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x001 351#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x000
313#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001 352#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001
314#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000 353#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000
315 354
@@ -369,8 +408,8 @@
369#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000 408#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000
370#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000 409#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
371 410
372#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002
373#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000 411#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000
412#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x12 0x002
374#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000 413#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000
375 414
376#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000 415#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
@@ -392,11 +431,11 @@
392#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000 431#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000
393 432
394#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000 433#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000
395#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x15 0x002 434#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x12 0x002
396#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000 435#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000
397 436
398#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000 437#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000
399#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x10 0x002 438#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x12 0x002
400#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000 439#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000
401 440
402#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000 441#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000
@@ -410,7 +449,7 @@
410#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000 449#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000
411 450
412#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000 451#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000
413#define MX25_PAD_KPP_ROW3__CSI_LD1 0x1b4 0x3ac 0x48c 0x13 0x002 452#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x13 0x002
414#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000 453#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000
415 454
416#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000 455#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000
@@ -455,9 +494,18 @@
455#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000 494#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000
456 495
457#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000 496#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000
497/*
498 * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
499 * 01/2011) this is CAN1_TX but that's wrong.
500 */
501#define MX25_PAD_FEC_RDATA1__CAN2_TX 0x1e0 0x3d8 0x000 0x14 0x000
458#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000 502#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000
459 503
460#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000 504#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000
505/*
506 * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
507 * 01/2011) this is CAN1_RX but that's wrong.
508 */
461#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000 509#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000
462#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000 510#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000
463 511
@@ -471,30 +519,34 @@
471#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000 519#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000
472#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000 520#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000
473 521
474#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000
475
476#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000 522#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000
477#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000 523#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000
478#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000 524#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000
479 525
480#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000 526#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000
481#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001
482#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001 527#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001
528#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001
483 529
484#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000 530#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000
531#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x11 0x000
532#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x12 0x001
533#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x13 0x001
485#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000 534#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000
486 535
487#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000 536#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000
537#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x12 0x001
488#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001 538#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001
489 539
490#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000 540#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000
491#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002 541#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002
492#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000 542#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000
493#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000 543#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000
544#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x16 0x002
494 545
495#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000 546#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000
496#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000 547#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000
497#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000 548#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000
549#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x16 0x000
498 550
499#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000 551#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000
500#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000 552#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000
@@ -505,6 +557,7 @@
505#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000 557#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000
506#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000 558#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000
507#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000 559#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000
560
508#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000 561#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000
509#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000 562#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000
510 563
@@ -517,6 +570,7 @@
517 570
518#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000 571#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000
519#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000 572#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000
573
520#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000 574#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000
521#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000 575#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000
522 576
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 4b063b68db44..6951b66d1ab7 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -488,6 +488,7 @@
488 interrupts = <54>; 488 interrupts = <54>;
489 clocks = <&clks IMX27_CLK_USB_IPG_GATE>; 489 clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
490 fsl,usbmisc = <&usbmisc 1>; 490 fsl,usbmisc = <&usbmisc 1>;
491 dr_mode = "host";
491 status = "disabled"; 492 status = "disabled";
492 }; 493 };
493 494
@@ -497,6 +498,7 @@
497 interrupts = <55>; 498 interrupts = <55>;
498 clocks = <&clks IMX27_CLK_USB_IPG_GATE>; 499 clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
499 fsl,usbmisc = <&usbmisc 2>; 500 fsl,usbmisc = <&usbmisc 2>;
501 dr_mode = "host";
500 status = "disabled"; 502 status = "disabled";
501 }; 503 };
502 504
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
index 7198fe3798c6..070e59cbdd8b 100644
--- a/arch/arm/boot/dts/imx28-apf28.dts
+++ b/arch/arm/boot/dts/imx28-apf28.dts
@@ -78,7 +78,7 @@
78 phy-mode = "rmii"; 78 phy-mode = "rmii";
79 pinctrl-names = "default"; 79 pinctrl-names = "default";
80 pinctrl-0 = <&mac0_pins_a>; 80 pinctrl-0 = <&mac0_pins_a>;
81 phy-reset-gpios = <&gpio4 13 0>; 81 phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
82 status = "okay"; 82 status = "okay";
83 }; 83 };
84 }; 84 };
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index 1f38a052ad4b..7ac4f1af16ac 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -110,6 +110,13 @@
110 }; 110 };
111 }; 111 };
112 }; 112 };
113
114 can0: can@80032000 {
115 pinctrl-names = "default";
116 pinctrl-0 = <&can0_pins_a>;
117 xceiver-supply = <&reg_can0_vcc>;
118 status = "okay";
119 };
113 }; 120 };
114 121
115 apbx@80040000 { 122 apbx@80040000 {
@@ -130,6 +137,13 @@
130 status = "okay"; 137 status = "okay";
131 }; 138 };
132 139
140 auart0: serial@8006a000 {
141 pinctrl-names = "default";
142 pinctrl-0 = <&auart0_pins_a>;
143 fsl,uart-has-rtscts;
144 status = "okay";
145 };
146
133 usbphy0: usbphy@8007c000 { 147 usbphy0: usbphy@8007c000 {
134 status = "okay"; 148 status = "okay";
135 }; 149 };
@@ -143,7 +157,8 @@
143 ahb@80080000 { 157 ahb@80080000 {
144 usb0: usb@80080000 { 158 usb0: usb@80080000 {
145 pinctrl-names = "default"; 159 pinctrl-names = "default";
146 pinctrl-0 = <&usb0_otg_apf28dev>; 160 pinctrl-0 = <&usb0_otg_apf28dev
161 &usb0_id_pins_b>;
147 vbus-supply = <&reg_usb0_vbus>; 162 vbus-supply = <&reg_usb0_vbus>;
148 status = "okay"; 163 status = "okay";
149 }; 164 };
@@ -156,7 +171,7 @@
156 phy-mode = "rmii"; 171 phy-mode = "rmii";
157 pinctrl-names = "default"; 172 pinctrl-names = "default";
158 pinctrl-0 = <&mac1_pins_a>; 173 pinctrl-0 = <&mac1_pins_a>;
159 phy-reset-gpios = <&gpio0 23 0>; 174 phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
160 status = "okay"; 175 status = "okay";
161 }; 176 };
162 }; 177 };
@@ -175,6 +190,14 @@
175 gpio = <&gpio1 23 1>; 190 gpio = <&gpio1 23 1>;
176 enable-active-high; 191 enable-active-high;
177 }; 192 };
193
194 reg_can0_vcc: regulator@1 {
195 compatible = "regulator-fixed";
196 reg = <1>;
197 regulator-name = "can0_vcc";
198 regulator-min-microvolt = <5000000>;
199 regulator-max-microvolt = <5000000>;
200 };
178 }; 201 };
179 202
180 leds { 203 leds {
@@ -200,8 +223,9 @@
200 223
201 user-button { 224 user-button {
202 label = "User button"; 225 label = "User button";
203 gpios = <&gpio0 17 0>; 226 gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
204 linux,code = <0x100>; 227 linux,code = <0x100>;
228 gpio-key,wakeup;
205 }; 229 };
206 }; 230 };
207}; 231};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 47f68ac868d4..25e25f82fbae 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -829,6 +829,19 @@
829 fsl,pull-up = <MXS_PULL_DISABLE>; 829 fsl,pull-up = <MXS_PULL_DISABLE>;
830 }; 830 };
831 831
832 spi3_pins_b: spi3@1 {
833 reg = <1>;
834 fsl,pinmux-ids = <
835 MX28_PAD_SSP3_SCK__SSP3_SCK
836 MX28_PAD_SSP3_MOSI__SSP3_CMD
837 MX28_PAD_SSP3_MISO__SSP3_D0
838 MX28_PAD_SSP3_SS0__SSP3_D3
839 >;
840 fsl,drive-strength = <MXS_DRIVE_8mA>;
841 fsl,voltage = <MXS_VOLTAGE_HIGH>;
842 fsl,pull-up = <MXS_PULL_ENABLE>;
843 };
844
832 usb0_pins_a: usb0@0 { 845 usb0_pins_a: usb0@0 {
833 reg = <0>; 846 reg = <0>;
834 fsl,pinmux-ids = < 847 fsl,pinmux-ids = <
@@ -1197,6 +1210,7 @@
1197 interrupts = <92>; 1210 interrupts = <92>;
1198 clocks = <&clks 61>; 1211 clocks = <&clks 61>;
1199 fsl,usbphy = <&usbphy1>; 1212 fsl,usbphy = <&usbphy1>;
1213 dr_mode = "host";
1200 status = "disabled"; 1214 status = "disabled";
1201 }; 1215 };
1202 1216
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 6932928f3b45..b6478e97d6a7 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -318,6 +318,7 @@
318 clocks = <&clks 73>; 318 clocks = <&clks 73>;
319 fsl,usbmisc = <&usbmisc 1>; 319 fsl,usbmisc = <&usbmisc 1>;
320 fsl,usbphy = <&usbphy1>; 320 fsl,usbphy = <&usbphy1>;
321 dr_mode = "host";
321 status = "disabled"; 322 status = "disabled";
322 }; 323 };
323 324
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 620b0f030591..e2457138311f 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -197,6 +197,7 @@
197 reg = <0x53f80200 0x0200>; 197 reg = <0x53f80200 0x0200>;
198 interrupts = <14>; 198 interrupts = <14>;
199 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; 199 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
200 dr_mode = "host";
200 status = "disabled"; 201 status = "disabled";
201 }; 202 };
202 203
@@ -205,6 +206,7 @@
205 reg = <0x53f80400 0x0200>; 206 reg = <0x53f80400 0x0200>;
206 interrupts = <16>; 207 interrupts = <16>;
207 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 208 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
209 dr_mode = "host";
208 status = "disabled"; 210 status = "disabled";
209 }; 211 };
210 212
@@ -213,6 +215,7 @@
213 reg = <0x53f80600 0x0200>; 215 reg = <0x53f80600 0x0200>;
214 interrupts = <17>; 216 interrupts = <17>;
215 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 217 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
218 dr_mode = "host";
216 status = "disabled"; 219 status = "disabled";
217 }; 220 };
218 221
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index c0116cffc513..f46fe9bf0bcb 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -265,6 +265,7 @@
265 interrupts = <14>; 265 interrupts = <14>;
266 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 266 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
267 fsl,usbmisc = <&usbmisc 1>; 267 fsl,usbmisc = <&usbmisc 1>;
268 dr_mode = "host";
268 status = "disabled"; 269 status = "disabled";
269 }; 270 };
270 271
@@ -274,6 +275,7 @@
274 interrupts = <16>; 275 interrupts = <16>;
275 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 276 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
276 fsl,usbmisc = <&usbmisc 2>; 277 fsl,usbmisc = <&usbmisc 2>;
278 dr_mode = "host";
277 status = "disabled"; 279 status = "disabled";
278 }; 280 };
279 281
@@ -283,6 +285,7 @@
283 interrupts = <17>; 285 interrupts = <17>;
284 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 286 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
285 fsl,usbmisc = <&usbmisc 3>; 287 fsl,usbmisc = <&usbmisc 3>;
288 dr_mode = "host";
286 status = "disabled"; 289 status = "disabled";
287 }; 290 };
288 291
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index ff4fa7ecacd8..c3e3ca9362fb 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -309,6 +309,7 @@
309 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 309 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
310 fsl,usbmisc = <&usbmisc 1>; 310 fsl,usbmisc = <&usbmisc 1>;
311 fsl,usbphy = <&usbphy1>; 311 fsl,usbphy = <&usbphy1>;
312 dr_mode = "host";
312 status = "disabled"; 313 status = "disabled";
313 }; 314 };
314 315
@@ -318,6 +319,7 @@
318 interrupts = <16>; 319 interrupts = <16>;
319 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 320 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
320 fsl,usbmisc = <&usbmisc 2>; 321 fsl,usbmisc = <&usbmisc 2>;
322 dr_mode = "host";
321 status = "disabled"; 323 status = "disabled";
322 }; 324 };
323 325
@@ -327,6 +329,7 @@
327 interrupts = <17>; 329 interrupts = <17>;
328 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 330 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
329 fsl,usbmisc = <&usbmisc 3>; 331 fsl,usbmisc = <&usbmisc 3>;
332 dr_mode = "host";
330 status = "disabled"; 333 status = "disabled";
331 }; 334 };
332 335
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
index 9cd06e5e59f0..d4c4a22db488 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
@@ -83,3 +83,7 @@
83&ipu1_di0_disp0 { 83&ipu1_di0_disp0 {
84 remote-endpoint = <&display0_in>; 84 remote-endpoint = <&display0_in>;
85}; 85};
86
87&pwm1 {
88 status = "okay";
89};
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
index b413e24288dc..15203f0e9725 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
@@ -72,3 +72,7 @@
72&ipu1_di0_disp0 { 72&ipu1_di0_disp0 {
73 remote-endpoint = <&display0_in>; 73 remote-endpoint = <&display0_in>;
74}; 74};
75
76&pwm3 {
77 status = "okay";
78};
diff --git a/arch/arm/boot/dts/imx6dl-cubox-i.dts b/arch/arm/boot/dts/imx6dl-cubox-i.dts
index 58aa8f2b0f26..e0b7fe8e18f8 100644
--- a/arch/arm/boot/dts/imx6dl-cubox-i.dts
+++ b/arch/arm/boot/dts/imx6dl-cubox-i.dts
@@ -1,5 +1,43 @@
1/* 1/*
2 * Copyright (C) 2014 Russell King 2 * Copyright (C) 2014 Russell King
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License.
13 *
14 * This file is distributed in the hope that it will be useful
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
3 */ 41 */
4/dts-v1/; 42/dts-v1/;
5 43
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index 44a0e6736bb1..7369d2d7da3e 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -1,6 +1,44 @@
1/* 1/*
2 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) 2 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
3 * Based on dt work by Russell King 3 * Based on dt work by Russell King
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License.
14 *
15 * This file is distributed in the hope that it will be useful
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
4 */ 42 */
5/dts-v1/; 43/dts-v1/;
6 44
diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/imx6q-cubox-i.dts
index 9efd8b0c8011..670bd8c4c847 100644
--- a/arch/arm/boot/dts/imx6q-cubox-i.dts
+++ b/arch/arm/boot/dts/imx6q-cubox-i.dts
@@ -1,5 +1,43 @@
1/* 1/*
2 * Copyright (C) 2014 Russell King 2 * Copyright (C) 2014 Russell King
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License.
13 *
14 * This file is distributed in the hope that it will be useful
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
3 */ 41 */
4/dts-v1/; 42/dts-v1/;
5 43
diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts
index c2bf8476ce45..0f6044553a24 100644
--- a/arch/arm/boot/dts/imx6q-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6q-hummingboard.dts
@@ -1,6 +1,44 @@
1/* 1/*
2 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) 2 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
3 * Based on dt work by Russell King 3 * Based on dt work by Russell King
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License.
14 *
15 * This file is distributed in the hope that it will be useful
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
4 */ 42 */
5/dts-v1/; 43/dts-v1/;
6 44
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 93ec79bb6b35..399103b8e2c9 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -294,19 +294,21 @@
294}; 294};
295 295
296&mipi_dsi { 296&mipi_dsi {
297 port@2 { 297 ports {
298 reg = <2>; 298 port@2 {
299 reg = <2>;
299 300
300 mipi_mux_2: endpoint { 301 mipi_mux_2: endpoint {
301 remote-endpoint = <&ipu2_di0_mipi>; 302 remote-endpoint = <&ipu2_di0_mipi>;
303 };
302 }; 304 };
303 };
304 305
305 port@3 { 306 port@3 {
306 reg = <3>; 307 reg = <3>;
307 308
308 mipi_mux_3: endpoint { 309 mipi_mux_3: endpoint {
309 remote-endpoint = <&ipu2_di1_mipi>; 310 remote-endpoint = <&ipu2_di1_mipi>;
311 };
310 }; 312 };
311 }; 313 };
312}; 314};
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index 6a524ca011e7..d033bb182060 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -1,8 +1,48 @@
1/* 1/*
2 * Copyright (C) 2014 Russell King 2 * Copyright (C) 2014 Russell King
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License.
13 *
14 * This file is distributed in the hope that it will be useful
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
3 */ 41 */
4#include "imx6qdl-microsom.dtsi" 42#include "imx6qdl-microsom.dtsi"
5#include "imx6qdl-microsom-ar8035.dtsi" 43#include "imx6qdl-microsom-ar8035.dtsi"
44#include <dt-bindings/input/input.h>
45#include <dt-bindings/gpio/gpio.h>
6 46
7/ { 47/ {
8 ir_recv: ir-receiver { 48 ir_recv: ir-receiver {
@@ -66,6 +106,18 @@
66 spdif-controller = <&spdif>; 106 spdif-controller = <&spdif>;
67 spdif-out; 107 spdif-out;
68 }; 108 };
109
110 gpio-keys {
111 compatible = "gpio-keys";
112 pinctrl-0 = <&pinctrl_gpio_key>;
113 pinctrl-names = "default";
114
115 button_0 {
116 label = "Button 0";
117 gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
118 linux,code = <BTN_0>;
119 };
120 };
69}; 121};
70 122
71&hdmi { 123&hdmi {
@@ -170,9 +222,19 @@
170 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 222 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
171 >; 223 >;
172 }; 224 };
225
226 pinctrl_gpio_key: gpio-key {
227 fsl,pins = <
228 MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059
229 >;
230 };
173 }; 231 };
174}; 232};
175 233
234&pwm1 {
235 status = "okay";
236};
237
176&spdif { 238&spdif {
177 pinctrl-names = "default"; 239 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_cubox_i_spdif>; 240 pinctrl-0 = <&pinctrl_cubox_i_spdif>;
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
index 62841e85a91e..151a3db2aea9 100644
--- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
@@ -1,5 +1,43 @@
1/* 1/*
2 * Copyright (C) 2013,2014 Russell King 2 * Copyright (C) 2013,2014 Russell King
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License.
13 *
14 * This file is distributed in the hope that it will be useful
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
3 */ 41 */
4#include "imx6qdl-microsom.dtsi" 42#include "imx6qdl-microsom.dtsi"
5#include "imx6qdl-microsom-ar8035.dtsi" 43#include "imx6qdl-microsom-ar8035.dtsi"
@@ -50,6 +88,19 @@
50 }; 88 };
51 }; 89 };
52 90
91 sound-sgtl5000 {
92 audio-codec = <&sgtl5000>;
93 audio-routing =
94 "MIC_IN", "Mic Jack",
95 "Mic Jack", "Mic Bias",
96 "Headphone Jack", "HP_OUT";
97 compatible = "fsl,imx-audio-sgtl5000";
98 model = "On-board Codec";
99 mux-ext-port = <5>;
100 mux-int-port = <1>;
101 ssi-controller = <&ssi1>;
102 };
103
53 sound-spdif { 104 sound-spdif {
54 compatible = "fsl,imx-audio-spdif"; 105 compatible = "fsl,imx-audio-spdif";
55 model = "On-board SPDIF"; 106 model = "On-board SPDIF";
@@ -59,6 +110,10 @@
59 }; 110 };
60}; 111};
61 112
113&audmux {
114 status = "okay";
115};
116
62&can1 { 117&can1 {
63 pinctrl-names = "default"; 118 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; 119 pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
@@ -75,16 +130,24 @@
75&i2c1 { 130&i2c1 {
76 pinctrl-names = "default"; 131 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_hummingboard_i2c1>; 132 pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
78
79 /*
80 * Not fitted on Carrier-1 board... yet
81 status = "okay"; 133 status = "okay";
82 134
135 /* Pro baseboard model */
83 rtc: pcf8523@68 { 136 rtc: pcf8523@68 {
84 compatible = "nxp,pcf8523"; 137 compatible = "nxp,pcf8523";
85 reg = <0x68>; 138 reg = <0x68>;
86 }; 139 };
87 */ 140
141 /* Pro baseboard model */
142 sgtl5000: sgtl5000@0a {
143 clocks = <&clks IMX6QDL_CLK_CKO>;
144 compatible = "fsl,sgtl5000";
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>;
147 reg = <0x0a>;
148 VDDA-supply = <&reg_3p3v>;
149 VDDIO-supply = <&reg_3p3v>;
150 };
88}; 151};
89 152
90&i2c2 { 153&i2c2 {
@@ -129,6 +192,20 @@
129 >; 192 >;
130 }; 193 };
131 194
195 pinctrl_hummingboard_pwm1: pwm1grp {
196 fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1>;
197 };
198
199 pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 {
200 fsl,pins = <
201 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
202 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
203 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0
204 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
205 MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
206 >;
207 };
208
132 pinctrl_hummingboard_spdif: hummingboard-spdif { 209 pinctrl_hummingboard_spdif: hummingboard-spdif {
133 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; 210 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
134 }; 211 };
@@ -168,12 +245,28 @@
168 }; 245 };
169}; 246};
170 247
248&pwm1 {
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_hummingboard_pwm1>;
251 status = "okay";
252};
253
254&pwm2 {
255 pinctrl-names = "default";
256 status = "okay";
257};
258
171&spdif { 259&spdif {
172 pinctrl-names = "default"; 260 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_hummingboard_spdif>; 261 pinctrl-0 = <&pinctrl_hummingboard_spdif>;
174 status = "okay"; 262 status = "okay";
175}; 263};
176 264
265&ssi1 {
266 fsl,mode = "i2s-slave";
267 status = "okay";
268};
269
177&usbh1 { 270&usbh1 {
178 disable-over-current; 271 disable-over-current;
179 vbus-supply = <&reg_usbh1_vbus>; 272 vbus-supply = <&reg_usbh1_vbus>;
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
index db9f45b2c573..4a1820309cdb 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -3,6 +3,44 @@
3 * 3 *
4 * This describes the hookup for an AR8035 to the iMX6 on the SolidRun 4 * This describes the hookup for an AR8035 to the iMX6 on the SolidRun
5 * MicroSOM. 5 * MicroSOM.
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License.
16 *
17 * This file is distributed in the hope that it will be useful
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
6 */ 44 */
7&fec { 45&fec {
8 pinctrl-names = "default"; 46 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
index 79eac6849d4c..349f82be816e 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
@@ -1,5 +1,43 @@
1/* 1/*
2 * Copyright (C) 2013,2014 Russell King 2 * Copyright (C) 2013,2014 Russell King
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License.
13 *
14 * This file is distributed in the hope that it will be useful
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
3 */ 41 */
4 42
5&iomuxc { 43&iomuxc {
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 009abd69385d..46b2fed7c319 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -182,6 +182,34 @@
182 }; 182 };
183}; 183};
184 184
185&i2c3 {
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_i2c3>;
188 pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
189 status = "okay";
190
191 max7310_a: gpio@30 {
192 compatible = "maxim,max7310";
193 reg = <0x30>;
194 gpio-controller;
195 #gpio-cells = <2>;
196 };
197
198 max7310_b: gpio@32 {
199 compatible = "maxim,max7310";
200 reg = <0x32>;
201 gpio-controller;
202 #gpio-cells = <2>;
203 };
204
205 max7310_c: gpio@34 {
206 compatible = "maxim,max7310";
207 reg = <0x34>;
208 gpio-controller;
209 #gpio-cells = <2>;
210 };
211};
212
185&iomuxc { 213&iomuxc {
186 pinctrl-names = "default"; 214 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_hog>; 215 pinctrl-0 = <&pinctrl_hog>;
@@ -265,6 +293,13 @@
265 >; 293 >;
266 }; 294 };
267 295
296 pinctrl_i2c3: i2c3grp {
297 fsl,pins = <
298 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
299 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
300 >;
301 };
302
268 pinctrl_pwm3: pwm1grp { 303 pinctrl_pwm3: pwm1grp {
269 fsl,pins = < 304 fsl,pins = <
270 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 305 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index d6c69ec44314..f74a8ded515f 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -53,6 +53,7 @@
53 interrupt-controller; 53 interrupt-controller;
54 reg = <0x00a01000 0x1000>, 54 reg = <0x00a01000 0x1000>,
55 <0x00a00100 0x100>; 55 <0x00a00100 0x100>;
56 interrupt-parent = <&intc>;
56 }; 57 };
57 58
58 clocks { 59 clocks {
@@ -82,7 +83,7 @@
82 #address-cells = <1>; 83 #address-cells = <1>;
83 #size-cells = <1>; 84 #size-cells = <1>;
84 compatible = "simple-bus"; 85 compatible = "simple-bus";
85 interrupt-parent = <&intc>; 86 interrupt-parent = <&gpc>;
86 ranges; 87 ranges;
87 88
88 dma_apbh: dma-apbh@00110000 { 89 dma_apbh: dma-apbh@00110000 {
@@ -122,6 +123,7 @@
122 compatible = "arm,cortex-a9-twd-timer"; 123 compatible = "arm,cortex-a9-twd-timer";
123 reg = <0x00a00600 0x20>; 124 reg = <0x00a00600 0x20>;
124 interrupts = <1 13 0xf01>; 125 interrupts = <1 13 0xf01>;
126 interrupt-parent = <&intc>;
125 clocks = <&clks IMX6QDL_CLK_TWD>; 127 clocks = <&clks IMX6QDL_CLK_TWD>;
126 }; 128 };
127 129
@@ -357,6 +359,7 @@
357 clocks = <&clks IMX6QDL_CLK_IPG>, 359 clocks = <&clks IMX6QDL_CLK_IPG>,
358 <&clks IMX6QDL_CLK_PWM1>; 360 <&clks IMX6QDL_CLK_PWM1>;
359 clock-names = "ipg", "per"; 361 clock-names = "ipg", "per";
362 status = "disabled";
360 }; 363 };
361 364
362 pwm2: pwm@02084000 { 365 pwm2: pwm@02084000 {
@@ -367,6 +370,7 @@
367 clocks = <&clks IMX6QDL_CLK_IPG>, 370 clocks = <&clks IMX6QDL_CLK_IPG>,
368 <&clks IMX6QDL_CLK_PWM2>; 371 <&clks IMX6QDL_CLK_PWM2>;
369 clock-names = "ipg", "per"; 372 clock-names = "ipg", "per";
373 status = "disabled";
370 }; 374 };
371 375
372 pwm3: pwm@02088000 { 376 pwm3: pwm@02088000 {
@@ -377,6 +381,7 @@
377 clocks = <&clks IMX6QDL_CLK_IPG>, 381 clocks = <&clks IMX6QDL_CLK_IPG>,
378 <&clks IMX6QDL_CLK_PWM3>; 382 <&clks IMX6QDL_CLK_PWM3>;
379 clock-names = "ipg", "per"; 383 clock-names = "ipg", "per";
384 status = "disabled";
380 }; 385 };
381 386
382 pwm4: pwm@0208c000 { 387 pwm4: pwm@0208c000 {
@@ -387,6 +392,7 @@
387 clocks = <&clks IMX6QDL_CLK_IPG>, 392 clocks = <&clks IMX6QDL_CLK_IPG>,
388 <&clks IMX6QDL_CLK_PWM4>; 393 <&clks IMX6QDL_CLK_PWM4>;
389 clock-names = "ipg", "per"; 394 clock-names = "ipg", "per";
395 status = "disabled";
390 }; 396 };
391 397
392 can1: flexcan@02090000 { 398 can1: flexcan@02090000 {
@@ -598,7 +604,7 @@
598 regulator-name = "vddpu"; 604 regulator-name = "vddpu";
599 regulator-min-microvolt = <725000>; 605 regulator-min-microvolt = <725000>;
600 regulator-max-microvolt = <1450000>; 606 regulator-max-microvolt = <1450000>;
601 regulator-always-on; 607 regulator-enable-ramp-delay = <150>;
602 anatop-reg-offset = <0x140>; 608 anatop-reg-offset = <0x140>;
603 anatop-vol-bit-shift = <9>; 609 anatop-vol-bit-shift = <9>;
604 anatop-vol-bit-width = <5>; 610 anatop-vol-bit-width = <5>;
@@ -658,7 +664,7 @@
658 #size-cells = <1>; 664 #size-cells = <1>;
659 ranges = <0 0x020cc000 0x4000>; 665 ranges = <0 0x020cc000 0x4000>;
660 666
661 snvs-rtc-lp@34 { 667 snvs_rtc: snvs-rtc-lp@34 {
662 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 668 compatible = "fsl,sec-v4.0-mon-rtc-lp";
663 reg = <0x34 0x58>; 669 reg = <0x34 0x58>;
664 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 670 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
@@ -693,8 +699,19 @@
693 gpc: gpc@020dc000 { 699 gpc: gpc@020dc000 {
694 compatible = "fsl,imx6q-gpc"; 700 compatible = "fsl,imx6q-gpc";
695 reg = <0x020dc000 0x4000>; 701 reg = <0x020dc000 0x4000>;
702 interrupt-controller;
703 #interrupt-cells = <3>;
696 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, 704 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
697 <0 90 IRQ_TYPE_LEVEL_HIGH>; 705 <0 90 IRQ_TYPE_LEVEL_HIGH>;
706 interrupt-parent = <&intc>;
707 pu-supply = <&reg_pu>;
708 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
709 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
710 <&clks IMX6QDL_CLK_GPU2D_CORE>,
711 <&clks IMX6QDL_CLK_GPU2D_AXI>,
712 <&clks IMX6QDL_CLK_OPENVG_AXI>,
713 <&clks IMX6QDL_CLK_VPU_AXI>;
714 #power-domain-cells = <1>;
698 }; 715 };
699 716
700 gpr: iomuxc-gpr@020e0000 { 717 gpr: iomuxc-gpr@020e0000 {
@@ -845,6 +862,7 @@
845 clocks = <&clks IMX6QDL_CLK_USBOH3>; 862 clocks = <&clks IMX6QDL_CLK_USBOH3>;
846 fsl,usbphy = <&usbphy2>; 863 fsl,usbphy = <&usbphy2>;
847 fsl,usbmisc = <&usbmisc 1>; 864 fsl,usbmisc = <&usbmisc 1>;
865 dr_mode = "host";
848 status = "disabled"; 866 status = "disabled";
849 }; 867 };
850 868
@@ -854,6 +872,7 @@
854 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; 872 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&clks IMX6QDL_CLK_USBOH3>; 873 clocks = <&clks IMX6QDL_CLK_USBOH3>;
856 fsl,usbmisc = <&usbmisc 2>; 874 fsl,usbmisc = <&usbmisc 2>;
875 dr_mode = "host";
857 status = "disabled"; 876 status = "disabled";
858 }; 877 };
859 878
@@ -863,6 +882,7 @@
863 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; 882 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
864 clocks = <&clks IMX6QDL_CLK_USBOH3>; 883 clocks = <&clks IMX6QDL_CLK_USBOH3>;
865 fsl,usbmisc = <&usbmisc 3>; 884 fsl,usbmisc = <&usbmisc 3>;
885 dr_mode = "host";
866 status = "disabled"; 886 status = "disabled";
867 }; 887 };
868 888
@@ -1022,19 +1042,24 @@
1022 reg = <0x021e0000 0x4000>; 1042 reg = <0x021e0000 0x4000>;
1023 status = "disabled"; 1043 status = "disabled";
1024 1044
1025 port@0 { 1045 ports {
1026 reg = <0>; 1046 #address-cells = <1>;
1047 #size-cells = <0>;
1048
1049 port@0 {
1050 reg = <0>;
1027 1051
1028 mipi_mux_0: endpoint { 1052 mipi_mux_0: endpoint {
1029 remote-endpoint = <&ipu1_di0_mipi>; 1053 remote-endpoint = <&ipu1_di0_mipi>;
1054 };
1030 }; 1055 };
1031 };
1032 1056
1033 port@1 { 1057 port@1 {
1034 reg = <1>; 1058 reg = <1>;
1035 1059
1036 mipi_mux_1: endpoint { 1060 mipi_mux_1: endpoint {
1037 remote-endpoint = <&ipu1_di1_mipi>; 1061 remote-endpoint = <&ipu1_di1_mipi>;
1062 };
1038 }; 1063 };
1039 }; 1064 };
1040 }; 1065 };
diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts
new file mode 100644
index 000000000000..64f7decf1fdc
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-warp.dts
@@ -0,0 +1,262 @@
1/*
2 * Copyright 2014, 2015 O.S. Systems Software LTDA.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49
50#include <dt-bindings/gpio/gpio.h>
51#include "imx6sl.dtsi"
52
53/ {
54 model = "WaRP Board";
55 compatible = "warp,imx6sl-warp", "fsl,imx6sl";
56
57 memory {
58 reg = <0x80000000 0x20000000>;
59 };
60
61 regulators {
62 compatible = "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <0>;
65
66 reg_usb_otg1_vbus: regulator@0 {
67 compatible = "regulator-fixed";
68 reg = <0>;
69 regulator-name = "usb_otg1_vbus";
70 regulator-min-microvolt = <5000000>;
71 regulator-max-microvolt = <5000000>;
72 gpio = <&gpio4 0 0>;
73 enable-active-high;
74 };
75
76 reg_usb_otg2_vbus: regulator@1 {
77 compatible = "regulator-fixed";
78 reg = <1>;
79 regulator-name = "usb_otg2_vbus";
80 regulator-min-microvolt = <5000000>;
81 regulator-max-microvolt = <5000000>;
82 gpio = <&gpio4 2 0>;
83 enable-active-high;
84 };
85
86 reg_1p8v: regulator@2 {
87 compatible = "regulator-fixed";
88 reg = <2>;
89 regulator-name = "1P8V";
90 regulator-min-microvolt = <1800000>;
91 regulator-max-microvolt = <1800000>;
92 };
93 };
94
95 usdhc3_pwrseq: usdhc3_pwrseq {
96 compatible = "mmc-pwrseq-simple";
97 reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
98 <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */
99 <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */
100 <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */
101 };
102};
103
104&uart1 {
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_uart1>;
107 status = "okay";
108};
109
110&uart2 {
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_uart2>;
113 fsl,uart-has-rtscts;
114 status = "okay";
115};
116
117&uart3 {
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_uart3>;
120 status = "okay";
121};
122
123&usbotg1 {
124 vbus-supply = <&reg_usb_otg1_vbus>;
125 dr_mode = "host";
126 disable-over-current;
127 status = "okay";
128};
129
130&usbotg2 {
131 vbus-supply = <&reg_usb_otg2_vbus>;
132 disable-over-current;
133 status = "okay";
134};
135
136&usdhc2 {
137 pinctrl-names = "default", "state_100mhz", "state_200mhz";
138 pinctrl-0 = <&pinctrl_usdhc2>;
139 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
140 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
141 bus-width = <8>;
142 non-removable;
143 status = "okay";
144};
145
146&usdhc3 {
147 pinctrl-names = "default", "state_100mhz", "state_200mhz";
148 pinctrl-0 = <&pinctrl_usdhc3>;
149 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
150 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
151 bus-width = <4>;
152 non-removable;
153 keep-power-in-suspend;
154 enable-sdio-wakeup;
155 mmc-pwrseq = <&usdhc3_pwrseq>;
156 status = "okay";
157};
158
159&iomuxc {
160 imx6sl-warp {
161 pinctrl_uart1: uart1grp {
162 fsl,pins = <
163 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1
164 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1
165 >;
166 };
167
168 pinctrl_uart2: uart2grp {
169 fsl,pins = <
170 MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x41b0b1
171 MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x41b0b1
172 MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x4130B1
173 MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x4130B1
174 >;
175 };
176
177 pinctrl_uart3: uart3grp {
178 fsl,pins = <
179 MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1
180 MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1
181 >;
182 };
183
184 pinctrl_usdhc2: usdhc2grp {
185 fsl,pins = <
186 MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059
187 MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059
188 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059
189 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059
190 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059
191 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059
192 MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059
193 MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059
194 MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059
195 MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059
196 >;
197 };
198
199 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
200 fsl,pins = <
201 MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9
202 MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9
203 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9
204 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9
205 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9
206 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9
207 MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9
208 MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9
209 MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9
210 MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9
211 >;
212 };
213
214 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
215 fsl,pins = <
216 MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9
217 MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9
218 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9
219 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9
220 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9
221 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9
222 MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9
223 MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9
224 MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9
225 MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9
226 >;
227 };
228
229 pinctrl_usdhc3: usdhc3grp {
230 fsl,pins = <
231 MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059
232 MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059
233 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059
234 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059
235 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059
236 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059
237 >;
238 };
239
240 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
241 fsl,pins = <
242 MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9
243 MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9
244 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9
245 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9
246 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9
247 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9
248 >;
249 };
250
251 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
252 fsl,pins = <
253 MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9
254 MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9
255 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9
256 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9
257 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9
258 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9
259 >;
260 };
261 };
262};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 36ab8e054cee..a78e715e3982 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -72,6 +72,7 @@
72 interrupt-controller; 72 interrupt-controller;
73 reg = <0x00a01000 0x1000>, 73 reg = <0x00a01000 0x1000>,
74 <0x00a00100 0x100>; 74 <0x00a00100 0x100>;
75 interrupt-parent = <&intc>;
75 }; 76 };
76 77
77 clocks { 78 clocks {
@@ -95,7 +96,7 @@
95 #address-cells = <1>; 96 #address-cells = <1>;
96 #size-cells = <1>; 97 #size-cells = <1>;
97 compatible = "simple-bus"; 98 compatible = "simple-bus";
98 interrupt-parent = <&intc>; 99 interrupt-parent = <&gpc>;
99 ranges; 100 ranges;
100 101
101 ocram: sram@00900000 { 102 ocram: sram@00900000 {
@@ -568,7 +569,7 @@
568 #size-cells = <1>; 569 #size-cells = <1>;
569 ranges = <0 0x020cc000 0x4000>; 570 ranges = <0 0x020cc000 0x4000>;
570 571
571 snvs-rtc-lp@34 { 572 snvs_rtc: snvs-rtc-lp@34 {
572 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 573 compatible = "fsl,sec-v4.0-mon-rtc-lp";
573 reg = <0x34 0x58>; 574 reg = <0x34 0x58>;
574 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 575 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
@@ -603,7 +604,14 @@
603 gpc: gpc@020dc000 { 604 gpc: gpc@020dc000 {
604 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; 605 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
605 reg = <0x020dc000 0x4000>; 606 reg = <0x020dc000 0x4000>;
607 interrupt-controller;
608 #interrupt-cells = <3>;
606 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 609 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
610 interrupt-parent = <&intc>;
611 pu-supply = <&reg_pu>;
612 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
613 <&clks IMX6SL_CLK_GPU2D_PODF>;
614 #power-domain-cells = <1>;
607 }; 615 };
608 616
609 gpr: iomuxc-gpr@020e0000 { 617 gpr: iomuxc-gpr@020e0000 {
@@ -699,6 +707,7 @@
699 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; 707 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&clks IMX6SL_CLK_USBOH3>; 708 clocks = <&clks IMX6SL_CLK_USBOH3>;
701 fsl,usbmisc = <&usbmisc 2>; 709 fsl,usbmisc = <&usbmisc 2>;
710 dr_mode = "host";
702 status = "disabled"; 711 status = "disabled";
703 }; 712 };
704 713
diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
new file mode 100644
index 000000000000..c76b87cba275
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
@@ -0,0 +1,143 @@
1/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "imx6sx-sdb.dtsi"
10
11/ {
12 model = "Freescale i.MX6 SoloX SDB RevA Board";
13};
14
15&i2c1 {
16 clock-frequency = <100000>;
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_i2c1>;
19 status = "okay";
20
21 pmic: pfuze100@08 {
22 compatible = "fsl,pfuze100";
23 reg = <0x08>;
24
25 regulators {
26 sw1a_reg: sw1ab {
27 regulator-min-microvolt = <300000>;
28 regulator-max-microvolt = <1875000>;
29 regulator-boot-on;
30 regulator-always-on;
31 regulator-ramp-delay = <6250>;
32 };
33
34 sw1c_reg: sw1c {
35 regulator-min-microvolt = <300000>;
36 regulator-max-microvolt = <1875000>;
37 regulator-boot-on;
38 regulator-always-on;
39 regulator-ramp-delay = <6250>;
40 };
41
42 sw2_reg: sw2 {
43 regulator-min-microvolt = <800000>;
44 regulator-max-microvolt = <3300000>;
45 regulator-boot-on;
46 regulator-always-on;
47 };
48
49 sw3a_reg: sw3a {
50 regulator-min-microvolt = <400000>;
51 regulator-max-microvolt = <1975000>;
52 regulator-boot-on;
53 regulator-always-on;
54 };
55
56 sw3b_reg: sw3b {
57 regulator-min-microvolt = <400000>;
58 regulator-max-microvolt = <1975000>;
59 regulator-boot-on;
60 regulator-always-on;
61 };
62
63 sw4_reg: sw4 {
64 regulator-min-microvolt = <800000>;
65 regulator-max-microvolt = <3300000>;
66 };
67
68 swbst_reg: swbst {
69 regulator-min-microvolt = <5000000>;
70 regulator-max-microvolt = <5150000>;
71 };
72
73 snvs_reg: vsnvs {
74 regulator-min-microvolt = <1000000>;
75 regulator-max-microvolt = <3000000>;
76 regulator-boot-on;
77 regulator-always-on;
78 };
79
80 vref_reg: vrefddr {
81 regulator-boot-on;
82 regulator-always-on;
83 };
84
85 vgen1_reg: vgen1 {
86 regulator-min-microvolt = <800000>;
87 regulator-max-microvolt = <1550000>;
88 regulator-always-on;
89 };
90
91 vgen2_reg: vgen2 {
92 regulator-min-microvolt = <800000>;
93 regulator-max-microvolt = <1550000>;
94 };
95
96 vgen3_reg: vgen3 {
97 regulator-min-microvolt = <1800000>;
98 regulator-max-microvolt = <3300000>;
99 regulator-always-on;
100 };
101
102 vgen4_reg: vgen4 {
103 regulator-min-microvolt = <1800000>;
104 regulator-max-microvolt = <3300000>;
105 regulator-always-on;
106 };
107
108 vgen5_reg: vgen5 {
109 regulator-min-microvolt = <1800000>;
110 regulator-max-microvolt = <3300000>;
111 regulator-always-on;
112 };
113
114 vgen6_reg: vgen6 {
115 regulator-min-microvolt = <1800000>;
116 regulator-max-microvolt = <3300000>;
117 regulator-always-on;
118 };
119 };
120 };
121};
122
123&qspi2 {
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_qspi2>;
126 status = "okay";
127
128 flash0: s25fl128s@0 {
129 reg = <0>;
130 #address-cells = <1>;
131 #size-cells = <1>;
132 compatible = "spansion,s25fl128s";
133 spi-max-frequency = <66000000>;
134 };
135
136 flash1: s25fl128s@1 {
137 reg = <1>;
138 #address-cells = <1>;
139 #size-cells = <1>;
140 compatible = "spansion,s25fl128s";
141 spi-max-frequency = <66000000>;
142 };
143};
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 32f07d6b4042..0bfc4e7865b2 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -1,197 +1,40 @@
1/* 1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc. 2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9/dts-v1/; 9#include "imx6sx-sdb.dtsi"
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include "imx6sx.dtsi"
14 10
15/ { 11/ {
16 model = "Freescale i.MX6 SoloX SDB Board"; 12 model = "Freescale i.MX6 SoloX SDB RevB Board";
17 compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
18
19 chosen {
20 stdout-path = &uart1;
21 };
22
23 memory {
24 reg = <0x80000000 0x40000000>;
25 };
26
27 backlight {
28 compatible = "pwm-backlight";
29 pwms = <&pwm3 0 5000000>;
30 brightness-levels = <0 4 8 16 32 64 128 255>;
31 default-brightness-level = <6>;
32 };
33
34 gpio-keys {
35 compatible = "gpio-keys";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_gpio_keys>;
38
39 volume-up {
40 label = "Volume Up";
41 gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_VOLUMEUP>;
43 };
44
45 volume-down {
46 label = "Volume Down";
47 gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
48 linux,code = <KEY_VOLUMEDOWN>;
49 };
50 };
51
52 regulators {
53 compatible = "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 vcc_sd3: regulator@0 {
58 compatible = "regulator-fixed";
59 reg = <0>;
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_vcc_sd3>;
62 regulator-name = "VCC_SD3";
63 regulator-min-microvolt = <3000000>;
64 regulator-max-microvolt = <3000000>;
65 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
66 enable-active-high;
67 };
68
69 reg_usb_otg1_vbus: regulator@1 {
70 compatible = "regulator-fixed";
71 reg = <1>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_usb_otg1>;
74 regulator-name = "usb_otg1_vbus";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
77 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
78 enable-active-high;
79 };
80
81 reg_usb_otg2_vbus: regulator@2 {
82 compatible = "regulator-fixed";
83 reg = <2>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_usb_otg2>;
86 regulator-name = "usb_otg2_vbus";
87 regulator-min-microvolt = <5000000>;
88 regulator-max-microvolt = <5000000>;
89 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
90 enable-active-high;
91 };
92
93 reg_psu_5v: regulator@3 {
94 compatible = "regulator-fixed";
95 reg = <3>;
96 regulator-name = "PSU-5V0";
97 regulator-min-microvolt = <5000000>;
98 regulator-max-microvolt = <5000000>;
99 };
100
101 reg_lcd_3v3: regulator@4 {
102 compatible = "regulator-fixed";
103 reg = <4>;
104 regulator-name = "lcd-3v3";
105 gpio = <&gpio3 27 0>;
106 enable-active-high;
107 };
108
109 reg_peri_3v3: regulator@5 {
110 compatible = "regulator-fixed";
111 reg = <5>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_peri_3v3>;
114 regulator-name = "peri_3v3";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
118 enable-active-high;
119 regulator-always-on;
120 };
121
122 reg_enet_3v3: regulator@6 {
123 compatible = "regulator-fixed";
124 reg = <6>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_enet_3v3>;
127 regulator-name = "enet_3v3";
128 regulator-min-microvolt = <3300000>;
129 regulator-max-microvolt = <3300000>;
130 gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
131 };
132 };
133
134 sound {
135 compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
136 model = "wm8962-audio";
137 ssi-controller = <&ssi2>;
138 audio-codec = <&codec>;
139 audio-routing =
140 "Headphone Jack", "HPOUTL",
141 "Headphone Jack", "HPOUTR",
142 "Ext Spk", "SPKOUTL",
143 "Ext Spk", "SPKOUTR",
144 "AMIC", "MICBIAS",
145 "IN3R", "AMIC";
146 mux-int-port = <2>;
147 mux-ext-port = <6>;
148 };
149};
150
151&audmux {
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_audmux>;
154 status = "okay";
155}; 13};
156 14
157&fec1 { 15&cpu0 {
158 pinctrl-names = "default"; 16 operating-points = <
159 pinctrl-0 = <&pinctrl_enet1>; 17 /* kHz uV */
160 phy-supply = <&reg_enet_3v3>; 18 996000 1250000
161 phy-mode = "rgmii"; 19 792000 1175000
162 phy-handle = <&ethphy1>; 20 396000 1175000
163 status = "okay"; 21 >;
164 22 fsl,soc-operating-points = <
165 mdio { 23 /* ARM kHz SOC uV */
166 #address-cells = <1>; 24 996000 1250000
167 #size-cells = <0>; 25 792000 1175000
168 26 396000 1175000
169 ethphy1: ethernet-phy@1 { 27 >;
170 reg = <1>;
171 };
172
173 ethphy2: ethernet-phy@2 {
174 reg = <2>;
175 };
176 };
177}; 28};
178 29
179&fec2 { 30&i2c1 {
31 clock-frequency = <100000>;
180 pinctrl-names = "default"; 32 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_enet2>; 33 pinctrl-0 = <&pinctrl_i2c1>;
182 phy-mode = "rgmii";
183 phy-handle = <&ethphy2>;
184 status = "okay"; 34 status = "okay";
185};
186
187&i2c1 {
188 clock-frequency = <100000>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_i2c1>;
191 status = "okay";
192 35
193 pmic: pfuze100@08 { 36 pmic: pfuze100@08 {
194 compatible = "fsl,pfuze100"; 37 compatible = "fsl,pfuze200";
195 reg = <0x08>; 38 reg = <0x08>;
196 39
197 regulators { 40 regulators {
@@ -203,14 +46,6 @@
203 regulator-ramp-delay = <6250>; 46 regulator-ramp-delay = <6250>;
204 }; 47 };
205 48
206 sw1c_reg: sw1c {
207 regulator-min-microvolt = <300000>;
208 regulator-max-microvolt = <1875000>;
209 regulator-boot-on;
210 regulator-always-on;
211 regulator-ramp-delay = <6250>;
212 };
213
214 sw2_reg: sw2 { 49 sw2_reg: sw2 {
215 regulator-min-microvolt = <800000>; 50 regulator-min-microvolt = <800000>;
216 regulator-max-microvolt = <3300000>; 51 regulator-max-microvolt = <3300000>;
@@ -232,11 +67,6 @@
232 regulator-always-on; 67 regulator-always-on;
233 }; 68 };
234 69
235 sw4_reg: sw4 {
236 regulator-min-microvolt = <800000>;
237 regulator-max-microvolt = <3300000>;
238 };
239
240 swbst_reg: swbst { 70 swbst_reg: swbst {
241 regulator-min-microvolt = <5000000>; 71 regulator-min-microvolt = <5000000>;
242 regulator-max-microvolt = <5150000>; 72 regulator-max-microvolt = <5150000>;
@@ -292,401 +122,24 @@
292 }; 122 };
293}; 123};
294 124
295&i2c4 {
296 clock-frequency = <100000>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_i2c4>;
299 status = "okay";
300
301 codec: wm8962@1a {
302 compatible = "wlf,wm8962";
303 reg = <0x1a>;
304 clocks = <&clks IMX6SX_CLK_AUDIO>;
305 DCVDD-supply = <&vgen4_reg>;
306 DBVDD-supply = <&vgen4_reg>;
307 AVDD-supply = <&vgen4_reg>;
308 CPVDD-supply = <&vgen4_reg>;
309 MICVDD-supply = <&vgen3_reg>;
310 PLLVDD-supply = <&vgen4_reg>;
311 SPKVDD1-supply = <&reg_psu_5v>;
312 SPKVDD2-supply = <&reg_psu_5v>;
313 };
314};
315
316&lcdif1 {
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_lcd>;
319 lcd-supply = <&reg_lcd_3v3>;
320 display = <&display0>;
321 status = "okay";
322
323 display0: display0 {
324 bits-per-pixel = <16>;
325 bus-width = <24>;
326
327 display-timings {
328 native-mode = <&timing0>;
329 timing0: timing0 {
330 clock-frequency = <33500000>;
331 hactive = <800>;
332 vactive = <480>;
333 hback-porch = <89>;
334 hfront-porch = <164>;
335 vback-porch = <23>;
336 vfront-porch = <10>;
337 hsync-len = <10>;
338 vsync-len = <10>;
339 hsync-active = <0>;
340 vsync-active = <0>;
341 de-active = <1>;
342 pixelclk-active = <0>;
343 };
344 };
345 };
346};
347
348&pwm3 {
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_pwm3>;
351 status = "okay";
352};
353
354&snvs_poweroff {
355 status = "okay";
356};
357
358&qspi2 { 125&qspi2 {
359 pinctrl-names = "default"; 126 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_qspi2>; 127 pinctrl-0 = <&pinctrl_qspi2>;
361 status = "okay"; 128 status = "okay";
362 129
363 flash0: s25fl128s@0 { 130 flash0: n25q256a@0 {
364 reg = <0>;
365 #address-cells = <1>; 131 #address-cells = <1>;
366 #size-cells = <1>; 132 #size-cells = <1>;
367 compatible = "spansion,s25fl128s"; 133 compatible = "micron,n25q256a";
368 spi-max-frequency = <66000000>; 134 spi-max-frequency = <29000000>;
135 reg = <0>;
369 }; 136 };
370 137
371 flash1: s25fl128s@1 { 138 flash1: n25q256a@1 {
372 reg = <1>;
373 #address-cells = <1>; 139 #address-cells = <1>;
374 #size-cells = <1>; 140 #size-cells = <1>;
375 compatible = "spansion,s25fl128s"; 141 compatible = "micron,n25q256a";
376 spi-max-frequency = <66000000>; 142 spi-max-frequency = <29000000>;
377 }; 143 reg = <1>;
378};
379
380&ssi2 {
381 status = "okay";
382};
383
384&uart1 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_uart1>;
387 status = "okay";
388};
389
390&uart5 { /* for bluetooth */
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_uart5>;
393 fsl,uart-has-rtscts;
394 status = "okay";
395};
396
397&usbotg1 {
398 vbus-supply = <&reg_usb_otg1_vbus>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_usb_otg1_id>;
401 status = "okay";
402};
403
404&usbotg2 {
405 vbus-supply = <&reg_usb_otg2_vbus>;
406 dr_mode = "host";
407 status = "okay";
408};
409
410&usdhc2 {
411 pinctrl-names = "default";
412 pinctrl-0 = <&pinctrl_usdhc2>;
413 non-removable;
414 no-1-8-v;
415 keep-power-in-suspend;
416 enable-sdio-wakeup;
417 status = "okay";
418};
419
420&usdhc3 {
421 pinctrl-names = "default", "state_100mhz", "state_200mhz";
422 pinctrl-0 = <&pinctrl_usdhc3>;
423 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
424 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
425 bus-width = <8>;
426 cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
427 wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
428 keep-power-in-suspend;
429 enable-sdio-wakeup;
430 vmmc-supply = <&vcc_sd3>;
431 status = "okay";
432};
433
434&usdhc4 {
435 pinctrl-names = "default";
436 pinctrl-0 = <&pinctrl_usdhc4>;
437 cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
438 wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
439 status = "okay";
440};
441
442&iomuxc {
443 imx6x-sdb {
444 pinctrl_audmux: audmuxgrp {
445 fsl,pins = <
446 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
447 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
448 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
449 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
450 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
451 >;
452 };
453
454 pinctrl_enet1: enet1grp {
455 fsl,pins = <
456 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
457 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
458 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
459 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
460 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
461 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
462 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
463 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
464 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
465 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
466 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
467 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
468 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
469 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
470 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
471 >;
472 };
473
474 pinctrl_enet_3v3: enet3v3grp {
475 fsl,pins = <
476 MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
477 >;
478 };
479
480 pinctrl_enet2: enet2grp {
481 fsl,pins = <
482 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
483 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
484 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
485 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
486 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
487 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
488 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
489 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
490 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
491 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
492 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
493 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
494 >;
495 };
496
497 pinctrl_gpio_keys: gpio_keysgrp {
498 fsl,pins = <
499 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
500 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
501 >;
502 };
503
504 pinctrl_i2c1: i2c1grp {
505 fsl,pins = <
506 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
507 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
508 >;
509 };
510
511 pinctrl_i2c4: i2c4grp {
512 fsl,pins = <
513 MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
514 MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
515 >;
516 };
517
518 pinctrl_lcd: lcdgrp {
519 fsl,pins = <
520 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
521 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
522 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
523 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
524 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
525 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
526 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
527 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
528 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
529 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
530 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
531 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
532 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
533 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
534 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
535 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
536 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
537 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
538 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
539 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
540 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
541 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
542 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
543 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
544 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
545 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
546 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
547 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
548 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
549 >;
550 };
551
552 pinctrl_peri_3v3: peri3v3grp {
553 fsl,pins = <
554 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
555 >;
556 };
557
558 pinctrl_pwm3: pwm3grp-1 {
559 fsl,pins = <
560 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
561 >;
562 };
563
564 pinctrl_qspi2: qspi2grp {
565 fsl,pins = <
566 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
567 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
568 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
569 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
570 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
571 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
572 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
573 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
574 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
575 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
576 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
577 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
578 >;
579 };
580
581 pinctrl_vcc_sd3: vccsd3grp {
582 fsl,pins = <
583 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
584 >;
585 };
586
587 pinctrl_uart1: uart1grp {
588 fsl,pins = <
589 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
590 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
591 >;
592 };
593
594 pinctrl_uart5: uart5grp {
595 fsl,pins = <
596 MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
597 MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
598 MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
599 MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
600 >;
601 };
602
603 pinctrl_usb_otg1: usbotg1grp {
604 fsl,pins = <
605 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
606 >;
607 };
608
609 pinctrl_usb_otg1_id: usbotg1idgrp {
610 fsl,pins = <
611 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
612 >;
613 };
614
615 pinctrl_usb_otg2: usbot2ggrp {
616 fsl,pins = <
617 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
618 >;
619 };
620
621 pinctrl_usdhc2: usdhc2grp {
622 fsl,pins = <
623 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
624 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
625 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
626 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
627 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
628 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
629 >;
630 };
631
632 pinctrl_usdhc3: usdhc3grp {
633 fsl,pins = <
634 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
635 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
636 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
637 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
638 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
639 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
640 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
641 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
642 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
643 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
644 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
645 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
646 >;
647 };
648
649 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
650 fsl,pins = <
651 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
652 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
653 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
654 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
655 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
656 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
657 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
658 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
659 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
660 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
661 >;
662 };
663
664 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
665 fsl,pins = <
666 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
667 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
668 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
669 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
670 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
671 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
672 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
673 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
674 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
675 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
676 >;
677 };
678
679 pinctrl_usdhc4: usdhc4grp {
680 fsl,pins = <
681 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
682 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
683 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
684 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
685 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
686 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
687 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
688 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
689 >;
690 };
691 }; 144 };
692}; 145};
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
new file mode 100644
index 000000000000..cef04cef3a80
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -0,0 +1,562 @@
1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include "imx6sx.dtsi"
14
15/ {
16 model = "Freescale i.MX6 SoloX SDB Board";
17 compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
18
19 chosen {
20 stdout-path = &uart1;
21 };
22
23 memory {
24 reg = <0x80000000 0x40000000>;
25 };
26
27 backlight {
28 compatible = "pwm-backlight";
29 pwms = <&pwm3 0 5000000>;
30 brightness-levels = <0 4 8 16 32 64 128 255>;
31 default-brightness-level = <6>;
32 };
33
34 gpio-keys {
35 compatible = "gpio-keys";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_gpio_keys>;
38
39 volume-up {
40 label = "Volume Up";
41 gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_VOLUMEUP>;
43 };
44
45 volume-down {
46 label = "Volume Down";
47 gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
48 linux,code = <KEY_VOLUMEDOWN>;
49 };
50 };
51
52 regulators {
53 compatible = "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 vcc_sd3: regulator@0 {
58 compatible = "regulator-fixed";
59 reg = <0>;
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_vcc_sd3>;
62 regulator-name = "VCC_SD3";
63 regulator-min-microvolt = <3000000>;
64 regulator-max-microvolt = <3000000>;
65 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
66 enable-active-high;
67 };
68
69 reg_usb_otg1_vbus: regulator@1 {
70 compatible = "regulator-fixed";
71 reg = <1>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_usb_otg1>;
74 regulator-name = "usb_otg1_vbus";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
77 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
78 enable-active-high;
79 };
80
81 reg_usb_otg2_vbus: regulator@2 {
82 compatible = "regulator-fixed";
83 reg = <2>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_usb_otg2>;
86 regulator-name = "usb_otg2_vbus";
87 regulator-min-microvolt = <5000000>;
88 regulator-max-microvolt = <5000000>;
89 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
90 enable-active-high;
91 };
92
93 reg_psu_5v: regulator@3 {
94 compatible = "regulator-fixed";
95 reg = <3>;
96 regulator-name = "PSU-5V0";
97 regulator-min-microvolt = <5000000>;
98 regulator-max-microvolt = <5000000>;
99 };
100
101 reg_lcd_3v3: regulator@4 {
102 compatible = "regulator-fixed";
103 reg = <4>;
104 regulator-name = "lcd-3v3";
105 gpio = <&gpio3 27 0>;
106 enable-active-high;
107 };
108
109 reg_peri_3v3: regulator@5 {
110 compatible = "regulator-fixed";
111 reg = <5>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_peri_3v3>;
114 regulator-name = "peri_3v3";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
118 enable-active-high;
119 regulator-always-on;
120 };
121
122 reg_enet_3v3: regulator@6 {
123 compatible = "regulator-fixed";
124 reg = <6>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_enet_3v3>;
127 regulator-name = "enet_3v3";
128 regulator-min-microvolt = <3300000>;
129 regulator-max-microvolt = <3300000>;
130 gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
131 };
132 };
133
134 sound {
135 compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
136 model = "wm8962-audio";
137 ssi-controller = <&ssi2>;
138 audio-codec = <&codec>;
139 audio-routing =
140 "Headphone Jack", "HPOUTL",
141 "Headphone Jack", "HPOUTR",
142 "Ext Spk", "SPKOUTL",
143 "Ext Spk", "SPKOUTR",
144 "AMIC", "MICBIAS",
145 "IN3R", "AMIC";
146 mux-int-port = <2>;
147 mux-ext-port = <6>;
148 };
149};
150
151&audmux {
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_audmux>;
154 status = "okay";
155};
156
157&fec1 {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_enet1>;
160 phy-supply = <&reg_enet_3v3>;
161 phy-mode = "rgmii";
162 phy-handle = <&ethphy1>;
163 status = "okay";
164
165 mdio {
166 #address-cells = <1>;
167 #size-cells = <0>;
168
169 ethphy1: ethernet-phy@1 {
170 reg = <1>;
171 };
172
173 ethphy2: ethernet-phy@2 {
174 reg = <2>;
175 };
176 };
177};
178
179&fec2 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_enet2>;
182 phy-mode = "rgmii";
183 phy-handle = <&ethphy2>;
184 status = "okay";
185};
186
187&i2c4 {
188 clock-frequency = <100000>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_i2c4>;
191 status = "okay";
192
193 codec: wm8962@1a {
194 compatible = "wlf,wm8962";
195 reg = <0x1a>;
196 clocks = <&clks IMX6SX_CLK_AUDIO>;
197 DCVDD-supply = <&vgen4_reg>;
198 DBVDD-supply = <&vgen4_reg>;
199 AVDD-supply = <&vgen4_reg>;
200 CPVDD-supply = <&vgen4_reg>;
201 MICVDD-supply = <&vgen3_reg>;
202 PLLVDD-supply = <&vgen4_reg>;
203 SPKVDD1-supply = <&reg_psu_5v>;
204 SPKVDD2-supply = <&reg_psu_5v>;
205 };
206};
207
208&lcdif1 {
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_lcd>;
211 lcd-supply = <&reg_lcd_3v3>;
212 display = <&display0>;
213 status = "okay";
214
215 display0: display0 {
216 bits-per-pixel = <16>;
217 bus-width = <24>;
218
219 display-timings {
220 native-mode = <&timing0>;
221 timing0: timing0 {
222 clock-frequency = <33500000>;
223 hactive = <800>;
224 vactive = <480>;
225 hback-porch = <89>;
226 hfront-porch = <164>;
227 vback-porch = <23>;
228 vfront-porch = <10>;
229 hsync-len = <10>;
230 vsync-len = <10>;
231 hsync-active = <0>;
232 vsync-active = <0>;
233 de-active = <1>;
234 pixelclk-active = <0>;
235 };
236 };
237 };
238};
239
240&pwm3 {
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_pwm3>;
243 status = "okay";
244};
245
246&snvs_poweroff {
247 status = "okay";
248};
249
250&ssi2 {
251 status = "okay";
252};
253
254&uart1 {
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_uart1>;
257 status = "okay";
258};
259
260&uart5 { /* for bluetooth */
261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_uart5>;
263 fsl,uart-has-rtscts;
264 status = "okay";
265};
266
267&usbotg1 {
268 vbus-supply = <&reg_usb_otg1_vbus>;
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_usb_otg1_id>;
271 status = "okay";
272};
273
274&usbotg2 {
275 vbus-supply = <&reg_usb_otg2_vbus>;
276 dr_mode = "host";
277 status = "okay";
278};
279
280&usdhc2 {
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_usdhc2>;
283 non-removable;
284 no-1-8-v;
285 keep-power-in-suspend;
286 enable-sdio-wakeup;
287 status = "okay";
288};
289
290&usdhc3 {
291 pinctrl-names = "default", "state_100mhz", "state_200mhz";
292 pinctrl-0 = <&pinctrl_usdhc3>;
293 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
294 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
295 bus-width = <8>;
296 cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
297 wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
298 keep-power-in-suspend;
299 enable-sdio-wakeup;
300 vmmc-supply = <&vcc_sd3>;
301 status = "okay";
302};
303
304&usdhc4 {
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_usdhc4>;
307 cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
308 wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
309 status = "okay";
310};
311
312&iomuxc {
313 imx6x-sdb {
314 pinctrl_audmux: audmuxgrp {
315 fsl,pins = <
316 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
317 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
318 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
319 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
320 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
321 >;
322 };
323
324 pinctrl_enet1: enet1grp {
325 fsl,pins = <
326 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
327 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
328 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
329 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
330 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
331 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
332 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
333 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
334 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
335 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
336 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
337 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
338 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
339 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
340 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
341 >;
342 };
343
344 pinctrl_enet_3v3: enet3v3grp {
345 fsl,pins = <
346 MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
347 >;
348 };
349
350 pinctrl_enet2: enet2grp {
351 fsl,pins = <
352 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
353 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
354 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
355 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
356 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
357 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
358 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
359 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
360 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
361 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
362 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
363 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
364 >;
365 };
366
367 pinctrl_gpio_keys: gpio_keysgrp {
368 fsl,pins = <
369 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
370 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
371 >;
372 };
373
374 pinctrl_i2c1: i2c1grp {
375 fsl,pins = <
376 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
377 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
378 >;
379 };
380
381 pinctrl_i2c4: i2c4grp {
382 fsl,pins = <
383 MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
384 MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
385 >;
386 };
387
388 pinctrl_lcd: lcdgrp {
389 fsl,pins = <
390 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
391 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
392 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
393 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
394 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
395 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
396 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
397 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
398 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
399 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
400 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
401 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
402 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
403 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
404 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
405 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
406 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
407 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
408 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
409 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
410 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
411 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
412 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
413 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
414 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
415 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
416 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
417 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
418 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
419 >;
420 };
421
422 pinctrl_peri_3v3: peri3v3grp {
423 fsl,pins = <
424 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
425 >;
426 };
427
428 pinctrl_pwm3: pwm3grp-1 {
429 fsl,pins = <
430 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
431 >;
432 };
433
434 pinctrl_qspi2: qspi2grp {
435 fsl,pins = <
436 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
437 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
438 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
439 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
440 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
441 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
442 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
443 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
444 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
445 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
446 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
447 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
448 >;
449 };
450
451 pinctrl_vcc_sd3: vccsd3grp {
452 fsl,pins = <
453 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
454 >;
455 };
456
457 pinctrl_uart1: uart1grp {
458 fsl,pins = <
459 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
460 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
461 >;
462 };
463
464 pinctrl_uart5: uart5grp {
465 fsl,pins = <
466 MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
467 MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
468 MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
469 MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
470 >;
471 };
472
473 pinctrl_usb_otg1: usbotg1grp {
474 fsl,pins = <
475 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
476 >;
477 };
478
479 pinctrl_usb_otg1_id: usbotg1idgrp {
480 fsl,pins = <
481 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
482 >;
483 };
484
485 pinctrl_usb_otg2: usbot2ggrp {
486 fsl,pins = <
487 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
488 >;
489 };
490
491 pinctrl_usdhc2: usdhc2grp {
492 fsl,pins = <
493 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
494 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
495 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
496 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
497 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
498 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
499 >;
500 };
501
502 pinctrl_usdhc3: usdhc3grp {
503 fsl,pins = <
504 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
505 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
506 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
507 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
508 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
509 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
510 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
511 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
512 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
513 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
514 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
515 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
516 >;
517 };
518
519 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
520 fsl,pins = <
521 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
522 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
523 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
524 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
525 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
526 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
527 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
528 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
529 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
530 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
531 >;
532 };
533
534 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
535 fsl,pins = <
536 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
537 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
538 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
539 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
540 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
541 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
542 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
543 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
544 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
545 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
546 >;
547 };
548
549 pinctrl_usdhc4: usdhc4grp {
550 fsl,pins = <
551 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
552 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
553 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
554 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
555 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
556 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
557 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
558 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
559 >;
560 };
561 };
562};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 7a24fee1e7ae..708175d59b9c 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -88,6 +88,7 @@
88 interrupt-controller; 88 interrupt-controller;
89 reg = <0x00a01000 0x1000>, 89 reg = <0x00a01000 0x1000>,
90 <0x00a00100 0x100>; 90 <0x00a00100 0x100>;
91 interrupt-parent = <&intc>;
91 }; 92 };
92 93
93 clocks { 94 clocks {
@@ -131,7 +132,7 @@
131 #address-cells = <1>; 132 #address-cells = <1>;
132 #size-cells = <1>; 133 #size-cells = <1>;
133 compatible = "simple-bus"; 134 compatible = "simple-bus";
134 interrupt-parent = <&intc>; 135 interrupt-parent = <&gpc>;
135 ranges; 136 ranges;
136 137
137 pmu { 138 pmu {
@@ -666,7 +667,7 @@
666 #size-cells = <1>; 667 #size-cells = <1>;
667 ranges = <0 0x020cc000 0x4000>; 668 ranges = <0 0x020cc000 0x4000>;
668 669
669 snvs-rtc-lp@34 { 670 snvs_rtc: snvs-rtc-lp@34 {
670 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 671 compatible = "fsl,sec-v4.0-mon-rtc-lp";
671 reg = <0x34 0x58>; 672 reg = <0x34 0x58>;
672 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 673 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -700,7 +701,10 @@
700 gpc: gpc@020dc000 { 701 gpc: gpc@020dc000 {
701 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; 702 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
702 reg = <0x020dc000 0x4000>; 703 reg = <0x020dc000 0x4000>;
704 interrupt-controller;
705 #interrupt-cells = <3>;
703 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 706 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
707 interrupt-parent = <&intc>;
704 }; 708 };
705 709
706 iomuxc: iomuxc@020e0000 { 710 iomuxc: iomuxc@020e0000 {
@@ -763,6 +767,7 @@
763 fsl,usbmisc = <&usbmisc 2>; 767 fsl,usbmisc = <&usbmisc 2>;
764 phy_type = "hsic"; 768 phy_type = "hsic";
765 fsl,anatop = <&anatop>; 769 fsl,anatop = <&anatop>;
770 dr_mode = "host";
766 status = "disabled"; 771 status = "disabled";
767 }; 772 };
768 773
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index e2b2e93d7b61..5b9a376cc31e 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -14,47 +14,65 @@
14 compatible = "ti,omap2420", "ti,omap2"; 14 compatible = "ti,omap2420", "ti,omap2";
15 15
16 ocp { 16 ocp {
17 prcm: prcm@48008000 { 17 l4: l4@48000000 {
18 compatible = "ti,omap2-prcm"; 18 compatible = "ti,omap2-l4", "simple-bus";
19 reg = <0x48008000 0x1000>; 19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges = <0 0x48000000 0x100000>;
20 22
21 prcm_clocks: clocks { 23 prcm: prcm@8000 {
22 #address-cells = <1>; 24 compatible = "ti,omap2-prcm";
23 #size-cells = <0>; 25 reg = <0x8000 0x1000>;
24 };
25 26
26 prcm_clockdomains: clockdomains { 27 prcm_clocks: clocks {
27 }; 28 #address-cells = <1>;
28 }; 29 #size-cells = <0>;
30 };
29 31
30 scrm: scrm@48000000 { 32 prcm_clockdomains: clockdomains {
31 compatible = "ti,omap2-scrm"; 33 };
32 reg = <0x48000000 0x1000>; 34 };
33 35
34 scrm_clocks: clocks { 36 scm: scm@0 {
37 compatible = "ti,omap2-scm", "simple-bus";
38 reg = <0x0 0x1000>;
35 #address-cells = <1>; 39 #address-cells = <1>;
36 #size-cells = <0>; 40 #size-cells = <1>;
41 ranges = <0 0x0 0x1000>;
42
43 omap2420_pmx: pinmux@30 {
44 compatible = "ti,omap2420-padconf",
45 "pinctrl-single";
46 reg = <0x30 0x0113>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49 pinctrl-single,register-width = <8>;
50 pinctrl-single,function-mask = <0x3f>;
51 };
52
53 scm_conf: scm_conf@270 {
54 compatible = "syscon";
55 reg = <0x270 0x100>;
56 #address-cells = <1>;
57 #size-cells = <1>;
58
59 scm_clocks: clocks {
60 #address-cells = <1>;
61 #size-cells = <0>;
62 };
63 };
64
65 scm_clockdomains: clockdomains {
66 };
37 }; 67 };
38 68
39 scrm_clockdomains: clockdomains { 69 counter32k: counter@4000 {
70 compatible = "ti,omap-counter32k";
71 reg = <0x4000 0x20>;
72 ti,hwmods = "counter_32k";
40 }; 73 };
41 }; 74 };
42 75
43 counter32k: counter@48004000 {
44 compatible = "ti,omap-counter32k";
45 reg = <0x48004000 0x20>;
46 ti,hwmods = "counter_32k";
47 };
48
49 omap2420_pmx: pinmux@48000030 {
50 compatible = "ti,omap2420-padconf", "pinctrl-single";
51 reg = <0x48000030 0x0113>;
52 #address-cells = <1>;
53 #size-cells = <0>;
54 pinctrl-single,register-width = <8>;
55 pinctrl-single,function-mask = <0x3f>;
56 };
57
58 gpio1: gpio@48018000 { 76 gpio1: gpio@48018000 {
59 compatible = "ti,omap2-gpio"; 77 compatible = "ti,omap2-gpio";
60 reg = <0x48018000 0x200>; 78 reg = <0x48018000 0x200>;
diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi
index 805f75df1cf2..93fed68839b9 100644
--- a/arch/arm/boot/dts/omap2430-clocks.dtsi
+++ b/arch/arm/boot/dts/omap2430-clocks.dtsi
@@ -8,12 +8,12 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11&scrm_clocks { 11&scm_clocks {
12 mcbsp3_mux_fck: mcbsp3_mux_fck { 12 mcbsp3_mux_fck: mcbsp3_mux_fck {
13 #clock-cells = <0>; 13 #clock-cells = <0>;
14 compatible = "ti,composite-mux-clock"; 14 compatible = "ti,composite-mux-clock";
15 clocks = <&func_96m_ck>, <&mcbsp_clks>; 15 clocks = <&func_96m_ck>, <&mcbsp_clks>;
16 reg = <0x02e8>; 16 reg = <0x78>;
17 }; 17 };
18 18
19 mcbsp3_fck: mcbsp3_fck { 19 mcbsp3_fck: mcbsp3_fck {
@@ -27,7 +27,7 @@
27 compatible = "ti,composite-mux-clock"; 27 compatible = "ti,composite-mux-clock";
28 clocks = <&func_96m_ck>, <&mcbsp_clks>; 28 clocks = <&func_96m_ck>, <&mcbsp_clks>;
29 ti,bit-shift = <2>; 29 ti,bit-shift = <2>;
30 reg = <0x02e8>; 30 reg = <0x78>;
31 }; 31 };
32 32
33 mcbsp4_fck: mcbsp4_fck { 33 mcbsp4_fck: mcbsp4_fck {
@@ -41,7 +41,7 @@
41 compatible = "ti,composite-mux-clock"; 41 compatible = "ti,composite-mux-clock";
42 clocks = <&func_96m_ck>, <&mcbsp_clks>; 42 clocks = <&func_96m_ck>, <&mcbsp_clks>;
43 ti,bit-shift = <4>; 43 ti,bit-shift = <4>;
44 reg = <0x02e8>; 44 reg = <0x78>;
45 }; 45 };
46 46
47 mcbsp5_fck: mcbsp5_fck { 47 mcbsp5_fck: mcbsp5_fck {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 0dc8de2782b1..11a7963be003 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -14,60 +14,73 @@
14 compatible = "ti,omap2430", "ti,omap2"; 14 compatible = "ti,omap2430", "ti,omap2";
15 15
16 ocp { 16 ocp {
17 prcm: prcm@49006000 { 17 l4_wkup: l4_wkup@49000000 {
18 compatible = "ti,omap2-prcm"; 18 compatible = "ti,omap2-l4-wkup", "simple-bus";
19 reg = <0x49006000 0x1000>; 19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges = <0 0x49000000 0x31000>;
20 22
21 prcm_clocks: clocks { 23 prcm: prcm@6000 {
22 #address-cells = <1>; 24 compatible = "ti,omap2-prcm";
23 #size-cells = <0>; 25 reg = <0x6000 0x1000>;
24 };
25 26
26 prcm_clockdomains: clockdomains { 27 prcm_clocks: clocks {
27 }; 28 #address-cells = <1>;
28 }; 29 #size-cells = <0>;
29 30 };
30 scrm: scrm@49002000 {
31 compatible = "ti,omap2-scrm";
32 reg = <0x49002000 0x1000>;
33 31
34 scrm_clocks: clocks { 32 prcm_clockdomains: clockdomains {
35 #address-cells = <1>; 33 };
36 #size-cells = <0>;
37 }; 34 };
38 35
39 scrm_clockdomains: clockdomains { 36 scm: scm@2000 {
37 compatible = "ti,omap2-scm", "simple-bus";
38 reg = <0x2000 0x1000>;
39 #address-cells = <1>;
40 #size-cells = <1>;
41 ranges = <0 0x2000 0x1000>;
42
43 omap2430_pmx: pinmux@30 {
44 compatible = "ti,omap2430-padconf",
45 "pinctrl-single";
46 reg = <0x30 0x0154>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49 pinctrl-single,register-width = <8>;
50 pinctrl-single,function-mask = <0x3f>;
51 };
52
53 scm_conf: scm_conf@270 {
54 compatible = "syscon";
55 reg = <0x270 0x240>;
56 #address-cells = <1>;
57 #size-cells = <1>;
58
59 scm_clocks: clocks {
60 #address-cells = <1>;
61 #size-cells = <0>;
62 };
63
64 pbias_regulator: pbias_regulator {
65 compatible = "ti,pbias-omap";
66 reg = <0x230 0x4>;
67 syscon = <&scm_conf>;
68 pbias_mmc_reg: pbias_mmc_omap2430 {
69 regulator-name = "pbias_mmc_omap2430";
70 regulator-min-microvolt = <1800000>;
71 regulator-max-microvolt = <3000000>;
72 };
73 };
74 };
75
76 scm_clockdomains: clockdomains {
77 };
40 }; 78 };
41 };
42
43 counter32k: counter@49020000 {
44 compatible = "ti,omap-counter32k";
45 reg = <0x49020000 0x20>;
46 ti,hwmods = "counter_32k";
47 };
48
49 omap2430_pmx: pinmux@49002030 {
50 compatible = "ti,omap2430-padconf", "pinctrl-single";
51 reg = <0x49002030 0x0154>;
52 #address-cells = <1>;
53 #size-cells = <0>;
54 pinctrl-single,register-width = <8>;
55 pinctrl-single,function-mask = <0x3f>;
56 };
57
58 omap2_scm_general: tisyscon@49002270 {
59 compatible = "syscon";
60 reg = <0x49002270 0x240>;
61 };
62 79
63 pbias_regulator: pbias_regulator { 80 counter32k: counter@20000 {
64 compatible = "ti,pbias-omap"; 81 compatible = "ti,omap-counter32k";
65 reg = <0x230 0x4>; 82 reg = <0x20000 0x20>;
66 syscon = <&omap2_scm_general>; 83 ti,hwmods = "counter_32k";
67 pbias_mmc_reg: pbias_mmc_omap2430 {
68 regulator-name = "pbias_mmc_omap2430";
69 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <3000000>;
71 }; 84 };
72 }; 85 };
73 86
diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi
index a1365ca926eb..63965b876973 100644
--- a/arch/arm/boot/dts/omap24xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi
@@ -7,13 +7,13 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10&scrm_clocks { 10&scm_clocks {
11 mcbsp1_mux_fck: mcbsp1_mux_fck { 11 mcbsp1_mux_fck: mcbsp1_mux_fck {
12 #clock-cells = <0>; 12 #clock-cells = <0>;
13 compatible = "ti,composite-mux-clock"; 13 compatible = "ti,composite-mux-clock";
14 clocks = <&func_96m_ck>, <&mcbsp_clks>; 14 clocks = <&func_96m_ck>, <&mcbsp_clks>;
15 ti,bit-shift = <2>; 15 ti,bit-shift = <2>;
16 reg = <0x0274>; 16 reg = <0x4>;
17 }; 17 };
18 18
19 mcbsp1_fck: mcbsp1_fck { 19 mcbsp1_fck: mcbsp1_fck {
@@ -27,7 +27,7 @@
27 compatible = "ti,composite-mux-clock"; 27 compatible = "ti,composite-mux-clock";
28 clocks = <&func_96m_ck>, <&mcbsp_clks>; 28 clocks = <&func_96m_ck>, <&mcbsp_clks>;
29 ti,bit-shift = <6>; 29 ti,bit-shift = <6>;
30 reg = <0x0274>; 30 reg = <0x4>;
31 }; 31 };
32 32
33 mcbsp2_fck: mcbsp2_fck { 33 mcbsp2_fck: mcbsp2_fck {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 3fdc84fddb70..d18a90f5eca3 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -87,6 +87,60 @@
87 ranges; 87 ranges;
88 ti,hwmods = "l3_main"; 88 ti,hwmods = "l3_main";
89 89
90 l4_core: l4@48000000 {
91 compatible = "ti,omap3-l4-core", "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges = <0 0x48000000 0x1000000>;
95
96 scm: scm@2000 {
97 compatible = "ti,omap3-scm", "simple-bus";
98 reg = <0x2000 0x2000>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges = <0 0x2000 0x2000>;
102
103 omap3_pmx_core: pinmux@30 {
104 compatible = "ti,omap3-padconf",
105 "pinctrl-single";
106 reg = <0x30 0x238>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109 #interrupt-cells = <1>;
110 interrupt-controller;
111 pinctrl-single,register-width = <16>;
112 pinctrl-single,function-mask = <0xff1f>;
113 };
114
115 scm_conf: scm_conf@270 {
116 compatible = "syscon";
117 reg = <0x270 0x330>;
118 #address-cells = <1>;
119 #size-cells = <1>;
120
121 scm_clocks: clocks {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 };
125 };
126
127 scm_clockdomains: clockdomains {
128 };
129
130 omap3_pmx_wkup: pinmux@a00 {
131 compatible = "ti,omap3-padconf",
132 "pinctrl-single";
133 reg = <0xa00 0x5c>;
134 #address-cells = <1>;
135 #size-cells = <0>;
136 #interrupt-cells = <1>;
137 interrupt-controller;
138 pinctrl-single,register-width = <16>;
139 pinctrl-single,function-mask = <0xff1f>;
140 };
141 };
142 };
143
90 aes: aes@480c5000 { 144 aes: aes@480c5000 {
91 compatible = "ti,omap3-aes"; 145 compatible = "ti,omap3-aes";
92 ti,hwmods = "aes"; 146 ti,hwmods = "aes";
@@ -123,19 +177,6 @@
123 }; 177 };
124 }; 178 };
125 179
126 scrm: scrm@48002000 {
127 compatible = "ti,omap3-scrm";
128 reg = <0x48002000 0x2000>;
129
130 scrm_clocks: clocks {
131 #address-cells = <1>;
132 #size-cells = <0>;
133 };
134
135 scrm_clockdomains: clockdomains {
136 };
137 };
138
139 counter32k: counter@48320000 { 180 counter32k: counter@48320000 {
140 compatible = "ti,omap-counter32k"; 181 compatible = "ti,omap-counter32k";
141 reg = <0x48320000 0x20>; 182 reg = <0x48320000 0x20>;
@@ -161,37 +202,10 @@
161 dma-requests = <96>; 202 dma-requests = <96>;
162 }; 203 };
163 204
164 omap3_pmx_core: pinmux@48002030 {
165 compatible = "ti,omap3-padconf", "pinctrl-single";
166 reg = <0x48002030 0x0238>;
167 #address-cells = <1>;
168 #size-cells = <0>;
169 #interrupt-cells = <1>;
170 interrupt-controller;
171 pinctrl-single,register-width = <16>;
172 pinctrl-single,function-mask = <0xff1f>;
173 };
174
175 omap3_pmx_wkup: pinmux@48002a00 {
176 compatible = "ti,omap3-padconf", "pinctrl-single";
177 reg = <0x48002a00 0x5c>;
178 #address-cells = <1>;
179 #size-cells = <0>;
180 #interrupt-cells = <1>;
181 interrupt-controller;
182 pinctrl-single,register-width = <16>;
183 pinctrl-single,function-mask = <0xff1f>;
184 };
185
186 omap3_scm_general: tisyscon@48002270 {
187 compatible = "syscon";
188 reg = <0x48002270 0x2f0>;
189 };
190
191 pbias_regulator: pbias_regulator { 205 pbias_regulator: pbias_regulator {
192 compatible = "ti,pbias-omap"; 206 compatible = "ti,pbias-omap";
193 reg = <0x2b0 0x4>; 207 reg = <0x2b0 0x4>;
194 syscon = <&omap3_scm_general>; 208 syscon = <&scm_conf>;
195 pbias_mmc_reg: pbias_mmc_omap2430 { 209 pbias_mmc_reg: pbias_mmc_omap2430 {
196 regulator-name = "pbias_mmc_omap2430"; 210 regulator-name = "pbias_mmc_omap2430";
197 regulator-min-microvolt = <1800000>; 211 regulator-min-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 7bc8c0f72ddb..4f6b2d5b1902 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -46,7 +46,7 @@
46 0x480bd800 0x017c>; 46 0x480bd800 0x017c>;
47 interrupts = <24>; 47 interrupts = <24>;
48 iommus = <&mmu_isp>; 48 iommus = <&mmu_isp>;
49 syscon = <&omap3_scm_general 0xdc>; 49 syscon = <&scm_conf 0xdc>;
50 ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>; 50 ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
51 #clock-cells = <1>; 51 #clock-cells = <1>;
52 ports { 52 ports {
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 3502fe00ec7d..86253de5a97a 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -78,7 +78,7 @@
78 0x480bd800 0x0600>; 78 0x480bd800 0x0600>;
79 interrupts = <24>; 79 interrupts = <24>;
80 iommus = <&mmu_isp>; 80 iommus = <&mmu_isp>;
81 syscon = <&omap3_scm_general 0x2f0>; 81 syscon = <&scm_conf 0x2f0>;
82 ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>; 82 ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
83 #clock-cells = <1>; 83 #clock-cells = <1>;
84 ports { 84 ports {
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index 5c375003bad1..bbba5bdc4bc9 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -79,13 +79,14 @@
79 clock-div = <1>; 79 clock-div = <1>;
80 }; 80 };
81}; 81};
82&scrm_clocks { 82
83&scm_clocks {
83 mcbsp5_mux_fck: mcbsp5_mux_fck { 84 mcbsp5_mux_fck: mcbsp5_mux_fck {
84 #clock-cells = <0>; 85 #clock-cells = <0>;
85 compatible = "ti,composite-mux-clock"; 86 compatible = "ti,composite-mux-clock";
86 clocks = <&core_96m_fck>, <&mcbsp_clks>; 87 clocks = <&core_96m_fck>, <&mcbsp_clks>;
87 ti,bit-shift = <4>; 88 ti,bit-shift = <4>;
88 reg = <0x02d8>; 89 reg = <0x68>;
89 }; 90 };
90 91
91 mcbsp5_fck: mcbsp5_fck { 92 mcbsp5_fck: mcbsp5_fck {
@@ -99,7 +100,7 @@
99 compatible = "ti,composite-mux-clock"; 100 compatible = "ti,composite-mux-clock";
100 clocks = <&core_96m_fck>, <&mcbsp_clks>; 101 clocks = <&core_96m_fck>, <&mcbsp_clks>;
101 ti,bit-shift = <2>; 102 ti,bit-shift = <2>;
102 reg = <0x0274>; 103 reg = <0x04>;
103 }; 104 };
104 105
105 mcbsp1_fck: mcbsp1_fck { 106 mcbsp1_fck: mcbsp1_fck {
@@ -113,7 +114,7 @@
113 compatible = "ti,composite-mux-clock"; 114 compatible = "ti,composite-mux-clock";
114 clocks = <&per_96m_fck>, <&mcbsp_clks>; 115 clocks = <&per_96m_fck>, <&mcbsp_clks>;
115 ti,bit-shift = <6>; 116 ti,bit-shift = <6>;
116 reg = <0x0274>; 117 reg = <0x04>;
117 }; 118 };
118 119
119 mcbsp2_fck: mcbsp2_fck { 120 mcbsp2_fck: mcbsp2_fck {
@@ -126,7 +127,7 @@
126 #clock-cells = <0>; 127 #clock-cells = <0>;
127 compatible = "ti,composite-mux-clock"; 128 compatible = "ti,composite-mux-clock";
128 clocks = <&per_96m_fck>, <&mcbsp_clks>; 129 clocks = <&per_96m_fck>, <&mcbsp_clks>;
129 reg = <0x02d8>; 130 reg = <0x68>;
130 }; 131 };
131 132
132 mcbsp3_fck: mcbsp3_fck { 133 mcbsp3_fck: mcbsp3_fck {
@@ -140,7 +141,7 @@
140 compatible = "ti,composite-mux-clock"; 141 compatible = "ti,composite-mux-clock";
141 clocks = <&per_96m_fck>, <&mcbsp_clks>; 142 clocks = <&per_96m_fck>, <&mcbsp_clks>;
142 ti,bit-shift = <2>; 143 ti,bit-shift = <2>;
143 reg = <0x02d8>; 144 reg = <0x68>;
144 }; 145 };
145 146
146 mcbsp4_fck: mcbsp4_fck { 147 mcbsp4_fck: mcbsp4_fck {
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index f2091d1c9c36..f884d6adb71e 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -124,99 +124,141 @@
124 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 124 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 125 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
126 126
127 cm1: cm1@4a004000 { 127 l4_cfg: l4@4a000000 {
128 compatible = "ti,omap4-cm1"; 128 compatible = "ti,omap4-l4-cfg", "simple-bus";
129 reg = <0x4a004000 0x2000>; 129 #address-cells = <1>;
130 130 #size-cells = <1>;
131 cm1_clocks: clocks { 131 ranges = <0 0x4a000000 0x1000000>;
132 #address-cells = <1>;
133 #size-cells = <0>;
134 };
135 132
136 cm1_clockdomains: clockdomains { 133 cm1: cm1@4000 {
137 }; 134 compatible = "ti,omap4-cm1";
138 }; 135 reg = <0x4000 0x2000>;
139 136
140 prm: prm@4a306000 { 137 cm1_clocks: clocks {
141 compatible = "ti,omap4-prm"; 138 #address-cells = <1>;
142 reg = <0x4a306000 0x3000>; 139 #size-cells = <0>;
143 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 140 };
144 141
145 prm_clocks: clocks { 142 cm1_clockdomains: clockdomains {
146 #address-cells = <1>; 143 };
147 #size-cells = <0>;
148 }; 144 };
149 145
150 prm_clockdomains: clockdomains { 146 cm2: cm2@8000 {
151 }; 147 compatible = "ti,omap4-cm2";
152 }; 148 reg = <0x8000 0x3000>;
153 149
154 cm2: cm2@4a008000 { 150 cm2_clocks: clocks {
155 compatible = "ti,omap4-cm2"; 151 #address-cells = <1>;
156 reg = <0x4a008000 0x3000>; 152 #size-cells = <0>;
153 };
157 154
158 cm2_clocks: clocks { 155 cm2_clockdomains: clockdomains {
159 #address-cells = <1>; 156 };
160 #size-cells = <0>;
161 }; 157 };
162 158
163 cm2_clockdomains: clockdomains { 159 omap4_scm_core: scm@2000 {
160 compatible = "ti,omap4-scm-core", "simple-bus";
161 reg = <0x2000 0x1000>;
162 #address-cells = <1>;
163 #size-cells = <1>;
164 ranges = <0 0x2000 0x1000>;
165
166 scm_conf: scm_conf@0 {
167 compatible = "syscon";
168 reg = <0x0 0x800>;
169 #address-cells = <1>;
170 #size-cells = <1>;
171 };
164 }; 172 };
165 };
166
167 scrm: scrm@4a30a000 {
168 compatible = "ti,omap4-scrm";
169 reg = <0x4a30a000 0x2000>;
170 173
171 scrm_clocks: clocks { 174 omap4_padconf_core: scm@100000 {
175 compatible = "ti,omap4-scm-padconf-core",
176 "simple-bus";
172 #address-cells = <1>; 177 #address-cells = <1>;
173 #size-cells = <0>; 178 #size-cells = <1>;
179 ranges = <0 0x100000 0x1000>;
180
181 omap4_pmx_core: pinmux@40 {
182 compatible = "ti,omap4-padconf",
183 "pinctrl-single";
184 reg = <0x40 0x0196>;
185 #address-cells = <1>;
186 #size-cells = <0>;
187 #interrupt-cells = <1>;
188 interrupt-controller;
189 pinctrl-single,register-width = <16>;
190 pinctrl-single,function-mask = <0x7fff>;
191 };
192
193 omap4_padconf_global: omap4_padconf_global@5a0 {
194 compatible = "syscon";
195 reg = <0x5a0 0x170>;
196 #address-cells = <1>;
197 #size-cells = <1>;
198
199 pbias_regulator: pbias_regulator {
200 compatible = "ti,pbias-omap";
201 reg = <0x60 0x4>;
202 syscon = <&omap4_padconf_global>;
203 pbias_mmc_reg: pbias_mmc_omap4 {
204 regulator-name = "pbias_mmc_omap4";
205 regulator-min-microvolt = <1800000>;
206 regulator-max-microvolt = <3000000>;
207 };
208 };
209 };
174 }; 210 };
175 211
176 scrm_clockdomains: clockdomains { 212 l4_wkup: l4@300000 {
177 }; 213 compatible = "ti,omap4-l4-wkup", "simple-bus";
178 }; 214 #address-cells = <1>;
179 215 #size-cells = <1>;
180 counter32k: counter@4a304000 { 216 ranges = <0 0x300000 0x40000>;
181 compatible = "ti,omap-counter32k"; 217
182 reg = <0x4a304000 0x20>; 218 counter32k: counter@4000 {
183 ti,hwmods = "counter_32k"; 219 compatible = "ti,omap-counter32k";
184 }; 220 reg = <0x4000 0x20>;
185 221 ti,hwmods = "counter_32k";
186 omap4_pmx_core: pinmux@4a100040 { 222 };
187 compatible = "ti,omap4-padconf", "pinctrl-single"; 223
188 reg = <0x4a100040 0x0196>; 224 prm: prm@6000 {
189 #address-cells = <1>; 225 compatible = "ti,omap4-prm";
190 #size-cells = <0>; 226 reg = <0x6000 0x3000>;
191 #interrupt-cells = <1>; 227 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
192 interrupt-controller; 228
193 pinctrl-single,register-width = <16>; 229 prm_clocks: clocks {
194 pinctrl-single,function-mask = <0x7fff>; 230 #address-cells = <1>;
195 }; 231 #size-cells = <0>;
196 omap4_pmx_wkup: pinmux@4a31e040 { 232 };
197 compatible = "ti,omap4-padconf", "pinctrl-single"; 233
198 reg = <0x4a31e040 0x0038>; 234 prm_clockdomains: clockdomains {
199 #address-cells = <1>; 235 };
200 #size-cells = <0>; 236 };
201 #interrupt-cells = <1>; 237
202 interrupt-controller; 238 scrm: scrm@a000 {
203 pinctrl-single,register-width = <16>; 239 compatible = "ti,omap4-scrm";
204 pinctrl-single,function-mask = <0x7fff>; 240 reg = <0xa000 0x2000>;
205 }; 241
206 242 scrm_clocks: clocks {
207 omap4_padconf_global: tisyscon@4a1005a0 { 243 #address-cells = <1>;
208 compatible = "syscon"; 244 #size-cells = <0>;
209 reg = <0x4a1005a0 0x170>; 245 };
210 }; 246
211 247 scrm_clockdomains: clockdomains {
212 pbias_regulator: pbias_regulator { 248 };
213 compatible = "ti,pbias-omap"; 249 };
214 reg = <0x60 0x4>; 250
215 syscon = <&omap4_padconf_global>; 251 omap4_pmx_wkup: pinmux@1e040 {
216 pbias_mmc_reg: pbias_mmc_omap4 { 252 compatible = "ti,omap4-padconf",
217 regulator-name = "pbias_mmc_omap4"; 253 "pinctrl-single";
218 regulator-min-microvolt = <1800000>; 254 reg = <0x1e040 0x0038>;
219 regulator-max-microvolt = <3000000>; 255 #address-cells = <1>;
256 #size-cells = <0>;
257 #interrupt-cells = <1>;
258 interrupt-controller;
259 pinctrl-single,register-width = <16>;
260 pinctrl-single,function-mask = <0x7fff>;
261 };
220 }; 262 };
221 }; 263 };
222 264
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 77b5f70d0ebc..efe5f737f39b 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -139,99 +139,141 @@
139 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 139 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 140 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
141 141
142 prm: prm@4ae06000 { 142 l4_cfg: l4@4a000000 {
143 compatible = "ti,omap5-prm"; 143 compatible = "ti,omap5-l4-cfg", "simple-bus";
144 reg = <0x4ae06000 0x3000>; 144 #address-cells = <1>;
145 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 145 #size-cells = <1>;
146 ranges = <0 0x4a000000 0x22a000>;
146 147
147 prm_clocks: clocks { 148 scm_core: scm@2000 {
149 compatible = "ti,omap5-scm-core", "simple-bus";
150 reg = <0x2000 0x1000>;
148 #address-cells = <1>; 151 #address-cells = <1>;
149 #size-cells = <0>; 152 #size-cells = <1>;
153 ranges = <0 0x2000 0x800>;
154
155 scm_conf: scm_conf@0 {
156 compatible = "syscon";
157 reg = <0x0 0x800>;
158 #address-cells = <1>;
159 #size-cells = <1>;
160 };
150 }; 161 };
151 162
152 prm_clockdomains: clockdomains { 163 scm_padconf_core: scm@2800 {
164 compatible = "ti,omap5-scm-padconf-core",
165 "simple-bus";
166 #address-cells = <1>;
167 #size-cells = <1>;
168 ranges = <0 0x2800 0x800>;
169
170 omap5_pmx_core: pinmux@40 {
171 compatible = "ti,omap5-padconf",
172 "pinctrl-single";
173 reg = <0x40 0x01b6>;
174 #address-cells = <1>;
175 #size-cells = <0>;
176 #interrupt-cells = <1>;
177 interrupt-controller;
178 pinctrl-single,register-width = <16>;
179 pinctrl-single,function-mask = <0x7fff>;
180 };
181
182 omap5_padconf_global: omap5_padconf_global@5a0 {
183 compatible = "syscon";
184 reg = <0x5a0 0xec>;
185 #address-cells = <1>;
186 #size-cells = <1>;
187
188 pbias_regulator: pbias_regulator {
189 compatible = "ti,pbias-omap";
190 reg = <0x60 0x4>;
191 syscon = <&omap5_padconf_global>;
192 pbias_mmc_reg: pbias_mmc_omap5 {
193 regulator-name = "pbias_mmc_omap5";
194 regulator-min-microvolt = <1800000>;
195 regulator-max-microvolt = <3000000>;
196 };
197 };
198 };
153 }; 199 };
154 };
155 200
156 cm_core_aon: cm_core_aon@4a004000 { 201 cm_core_aon: cm_core_aon@4000 {
157 compatible = "ti,omap5-cm-core-aon"; 202 compatible = "ti,omap5-cm-core-aon";
158 reg = <0x4a004000 0x2000>; 203 reg = <0x4000 0x2000>;
159 204
160 cm_core_aon_clocks: clocks { 205 cm_core_aon_clocks: clocks {
161 #address-cells = <1>; 206 #address-cells = <1>;
162 #size-cells = <0>; 207 #size-cells = <0>;
163 }; 208 };
164 209
165 cm_core_aon_clockdomains: clockdomains { 210 cm_core_aon_clockdomains: clockdomains {
211 };
166 }; 212 };
167 };
168 213
169 scrm: scrm@4ae0a000 { 214 cm_core: cm_core@8000 {
170 compatible = "ti,omap5-scrm"; 215 compatible = "ti,omap5-cm-core";
171 reg = <0x4ae0a000 0x2000>; 216 reg = <0x8000 0x3000>;
172 217
173 scrm_clocks: clocks { 218 cm_core_clocks: clocks {
174 #address-cells = <1>; 219 #address-cells = <1>;
175 #size-cells = <0>; 220 #size-cells = <0>;
176 }; 221 };
177 222
178 scrm_clockdomains: clockdomains { 223 cm_core_clockdomains: clockdomains {
224 };
179 }; 225 };
180 }; 226 };
181 227
182 cm_core: cm_core@4a008000 { 228 l4_wkup: l4@4ae00000 {
183 compatible = "ti,omap5-cm-core"; 229 compatible = "ti,omap5-l4-wkup", "simple-bus";
184 reg = <0x4a008000 0x3000>; 230 #address-cells = <1>;
231 #size-cells = <1>;
232 ranges = <0 0x4ae00000 0x2b000>;
185 233
186 cm_core_clocks: clocks { 234 counter32k: counter@4000 {
187 #address-cells = <1>; 235 compatible = "ti,omap-counter32k";
188 #size-cells = <0>; 236 reg = <0x4000 0x40>;
237 ti,hwmods = "counter_32k";
189 }; 238 };
190 239
191 cm_core_clockdomains: clockdomains { 240 prm: prm@6000 {
241 compatible = "ti,omap5-prm";
242 reg = <0x6000 0x3000>;
243 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
244
245 prm_clocks: clocks {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 };
249
250 prm_clockdomains: clockdomains {
251 };
192 }; 252 };
193 };
194 253
195 counter32k: counter@4ae04000 { 254 scrm: scrm@a000 {
196 compatible = "ti,omap-counter32k"; 255 compatible = "ti,omap5-scrm";
197 reg = <0x4ae04000 0x40>; 256 reg = <0xa000 0x2000>;
198 ti,hwmods = "counter_32k";
199 };
200 257
201 omap5_pmx_core: pinmux@4a002840 { 258 scrm_clocks: clocks {
202 compatible = "ti,omap5-padconf", "pinctrl-single"; 259 #address-cells = <1>;
203 reg = <0x4a002840 0x01b6>; 260 #size-cells = <0>;
204 #address-cells = <1>; 261 };
205 #size-cells = <0>;
206 #interrupt-cells = <1>;
207 interrupt-controller;
208 pinctrl-single,register-width = <16>;
209 pinctrl-single,function-mask = <0x7fff>;
210 };
211 omap5_pmx_wkup: pinmux@4ae0c840 {
212 compatible = "ti,omap5-padconf", "pinctrl-single";
213 reg = <0x4ae0c840 0x0038>;
214 #address-cells = <1>;
215 #size-cells = <0>;
216 #interrupt-cells = <1>;
217 interrupt-controller;
218 pinctrl-single,register-width = <16>;
219 pinctrl-single,function-mask = <0x7fff>;
220 };
221 262
222 omap5_padconf_global: tisyscon@4a002da0 { 263 scrm_clockdomains: clockdomains {
223 compatible = "syscon"; 264 };
224 reg = <0x4A002da0 0xec>; 265 };
225 };
226 266
227 pbias_regulator: pbias_regulator { 267 omap5_pmx_wkup: pinmux@c840 {
228 compatible = "ti,pbias-omap"; 268 compatible = "ti,omap5-padconf",
229 reg = <0x60 0x4>; 269 "pinctrl-single";
230 syscon = <&omap5_padconf_global>; 270 reg = <0xc840 0x0038>;
231 pbias_mmc_reg: pbias_mmc_omap5 { 271 #address-cells = <1>;
232 regulator-name = "pbias_mmc_omap5"; 272 #size-cells = <0>;
233 regulator-min-microvolt = <1800000>; 273 #interrupt-cells = <1>;
234 regulator-max-microvolt = <3000000>; 274 interrupt-controller;
275 pinctrl-single,register-width = <16>;
276 pinctrl-single,function-mask = <0x7fff>;
235 }; 277 };
236 }; 278 };
237 279
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index 36cafbfa1bfa..606753eb72c8 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -12,6 +12,12 @@
12 bootargs = "console=ttyLP0,115200"; 12 bootargs = "console=ttyLP0,115200";
13 }; 13 };
14 14
15 clk16m: clk16m {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <16000000>;
19 };
20
15 regulators { 21 regulators {
16 compatible = "simple-bus"; 22 compatible = "simple-bus";
17 #address-cells = <1>; 23 #address-cells = <1>;
@@ -47,6 +53,21 @@
47 status = "okay"; 53 status = "okay";
48}; 54};
49 55
56&dspi1 {
57 status = "okay";
58
59 mcp2515can: can@0 {
60 compatible = "microchip,mcp2515";
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_can_int>;
63 reg = <0>;
64 clocks = <&clk16m>;
65 spi-max-frequency = <10000000>;
66 interrupt-parent = <&gpio1>;
67 interrupts = <11 GPIO_ACTIVE_LOW>;
68 };
69};
70
50&esdhc1 { 71&esdhc1 {
51 pinctrl-names = "default"; 72 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_esdhc1>; 73 pinctrl-0 = <&pinctrl_esdhc1>;
@@ -94,3 +115,13 @@
94&usbh1 { 115&usbh1 {
95 vbus-supply = <&usbh_vbus_reg>; 116 vbus-supply = <&usbh_vbus_reg>;
96}; 117};
118
119&iomuxc {
120 vf610-colibri {
121 pinctrl_can_int: can_int {
122 fsl,pins = <
123 VF610_PAD_PTB21__GPIO_43 0x22ed
124 >;
125 };
126 };
127};
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index 5c2b7320856d..fbef0828e930 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -23,6 +23,12 @@
23 status = "okay"; 23 status = "okay";
24}; 24};
25 25
26&dspi1 {
27 bus-num = <1>;
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_dspi1>;
30};
31
26&edma0 { 32&edma0 {
27 status = "okay"; 33 status = "okay";
28}; 34};
@@ -107,6 +113,15 @@
107 >; 113 >;
108 }; 114 };
109 115
116 pinctrl_dspi1: dspi1grp {
117 fsl,pins = <
118 VF610_PAD_PTD5__DSPI1_CS0 0x33e2
119 VF610_PAD_PTD6__DSPI1_SIN 0x33e1
120 VF610_PAD_PTD7__DSPI1_SOUT 0x33e2
121 VF610_PAD_PTD8__DSPI1_SCK 0x33e2
122 >;
123 };
124
110 pinctrl_esdhc1: esdhc1grp { 125 pinctrl_esdhc1: esdhc1grp {
111 fsl,pins = < 126 fsl,pins = <
112 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef 127 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index 1dbf8d2d1ddf..e976d2fa1527 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -24,14 +24,13 @@
24 }; 24 };
25 25
26 soc { 26 soc {
27 interrupt-parent = <&intc>;
28
29 aips-bus@40000000 { 27 aips-bus@40000000 {
30 28
31 intc: interrupt-controller@40002000 { 29 intc: interrupt-controller@40002000 {
32 compatible = "arm,cortex-a9-gic"; 30 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>; 31 #interrupt-cells = <3>;
34 interrupt-controller; 32 interrupt-controller;
33 interrupt-parent = <&intc>;
35 reg = <0x40003000 0x1000>, 34 reg = <0x40003000 0x1000>,
36 <0x40002100 0x100>; 35 <0x40002100 0x100>;
37 }; 36 };
@@ -40,145 +39,17 @@
40 compatible = "arm,cortex-a9-global-timer"; 39 compatible = "arm,cortex-a9-global-timer";
41 reg = <0x40002200 0x20>; 40 reg = <0x40002200 0x20>;
42 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 41 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
42 interrupt-parent = <&intc>;
43 clocks = <&clks VF610_CLK_PLATFORM_BUS>; 43 clocks = <&clks VF610_CLK_PLATFORM_BUS>;
44 }; 44 };
45 }; 45 };
46 }; 46 };
47}; 47};
48 48
49&adc0 { 49&mscm_ir {
50 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 50 interrupt-parent = <&intc>;
51};
52
53&adc1 {
54 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
55};
56
57&can0 {
58 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
59};
60
61&can1 {
62 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
63};
64
65&dspi0 {
66 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
67};
68
69&edma0 {
70 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
72 interrupt-names = "edma-tx", "edma-err";
73};
74
75&edma1 {
76 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
78 interrupt-names = "edma-tx", "edma-err";
79};
80
81&esdhc1 {
82 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
83};
84
85&fec0 {
86 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
87};
88
89&fec1 {
90 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
91};
92
93&ftm {
94 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
95};
96
97&gpio0 {
98 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
99};
100
101&gpio1 {
102 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
103};
104
105&gpio2 {
106 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
107};
108
109&gpio3 {
110 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
111};
112
113&gpio4 {
114 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
115};
116
117&i2c0 {
118 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
119};
120
121&pit {
122 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
123};
124
125&qspi0 {
126 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
127};
128
129&sai2 {
130 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
131};
132
133&snvsrtc {
134 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
135};
136
137&src {
138 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
139};
140
141&uart0 {
142 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
143};
144
145&uart1 {
146 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
147};
148
149&uart2 {
150 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
151};
152
153&uart3 {
154 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
155};
156
157&uart4 {
158 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
159};
160
161&uart5 {
162 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
163};
164
165&usbdev0 {
166 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
167};
168
169&usbh1 {
170 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
171};
172
173&usbphy0 {
174 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
175};
176
177&usbphy1 {
178 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
179}; 51};
180 52
181&wdoga5 { 53&wdoga5 {
182 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
183 status = "okay"; 54 status = "okay";
184}; 55};
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index a29c7ce15eaf..4aa335166be7 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -54,6 +54,7 @@
54 #address-cells = <1>; 54 #address-cells = <1>;
55 #size-cells = <1>; 55 #size-cells = <1>;
56 compatible = "simple-bus"; 56 compatible = "simple-bus";
57 interrupt-parent = <&mscm_ir>;
57 ranges; 58 ranges;
58 59
59 aips0: aips-bus@40000000 { 60 aips0: aips-bus@40000000 {
@@ -62,6 +63,19 @@
62 #size-cells = <1>; 63 #size-cells = <1>;
63 ranges; 64 ranges;
64 65
66 mscm_cpucfg: cpucfg@40001000 {
67 compatible = "fsl,vf610-mscm-cpucfg", "syscon";
68 reg = <0x40001000 0x800>;
69 };
70
71 mscm_ir: interrupt-controller@40001800 {
72 compatible = "fsl,vf610-mscm-ir";
73 reg = <0x40001800 0x400>;
74 fsl,cpucfg = <&mscm_cpucfg>;
75 interrupt-controller;
76 #interrupt-cells = <2>;
77 };
78
65 edma0: dma-controller@40018000 { 79 edma0: dma-controller@40018000 {
66 #dma-cells = <2>; 80 #dma-cells = <2>;
67 compatible = "fsl,vf610-edma"; 81 compatible = "fsl,vf610-edma";
@@ -69,6 +83,9 @@
69 <0x40024000 0x1000>, 83 <0x40024000 0x1000>,
70 <0x40025000 0x1000>; 84 <0x40025000 0x1000>;
71 dma-channels = <32>; 85 dma-channels = <32>;
86 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
87 <9 IRQ_TYPE_LEVEL_HIGH>;
88 interrupt-names = "edma-tx", "edma-err";
72 clock-names = "dmamux0", "dmamux1"; 89 clock-names = "dmamux0", "dmamux1";
73 clocks = <&clks VF610_CLK_DMAMUX0>, 90 clocks = <&clks VF610_CLK_DMAMUX0>,
74 <&clks VF610_CLK_DMAMUX1>; 91 <&clks VF610_CLK_DMAMUX1>;
@@ -78,6 +95,7 @@
78 can0: flexcan@40020000 { 95 can0: flexcan@40020000 {
79 compatible = "fsl,vf610-flexcan"; 96 compatible = "fsl,vf610-flexcan";
80 reg = <0x40020000 0x4000>; 97 reg = <0x40020000 0x4000>;
98 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
81 clocks = <&clks VF610_CLK_FLEXCAN0>, 99 clocks = <&clks VF610_CLK_FLEXCAN0>,
82 <&clks VF610_CLK_FLEXCAN0>; 100 <&clks VF610_CLK_FLEXCAN0>;
83 clock-names = "ipg", "per"; 101 clock-names = "ipg", "per";
@@ -87,6 +105,7 @@
87 uart0: serial@40027000 { 105 uart0: serial@40027000 {
88 compatible = "fsl,vf610-lpuart"; 106 compatible = "fsl,vf610-lpuart";
89 reg = <0x40027000 0x1000>; 107 reg = <0x40027000 0x1000>;
108 interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&clks VF610_CLK_UART0>; 109 clocks = <&clks VF610_CLK_UART0>;
91 clock-names = "ipg"; 110 clock-names = "ipg";
92 dmas = <&edma0 0 2>, 111 dmas = <&edma0 0 2>,
@@ -98,6 +117,7 @@
98 uart1: serial@40028000 { 117 uart1: serial@40028000 {
99 compatible = "fsl,vf610-lpuart"; 118 compatible = "fsl,vf610-lpuart";
100 reg = <0x40028000 0x1000>; 119 reg = <0x40028000 0x1000>;
120 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&clks VF610_CLK_UART1>; 121 clocks = <&clks VF610_CLK_UART1>;
102 clock-names = "ipg"; 122 clock-names = "ipg";
103 dmas = <&edma0 0 4>, 123 dmas = <&edma0 0 4>,
@@ -109,6 +129,7 @@
109 uart2: serial@40029000 { 129 uart2: serial@40029000 {
110 compatible = "fsl,vf610-lpuart"; 130 compatible = "fsl,vf610-lpuart";
111 reg = <0x40029000 0x1000>; 131 reg = <0x40029000 0x1000>;
132 interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&clks VF610_CLK_UART2>; 133 clocks = <&clks VF610_CLK_UART2>;
113 clock-names = "ipg"; 134 clock-names = "ipg";
114 dmas = <&edma0 0 6>, 135 dmas = <&edma0 0 6>,
@@ -120,6 +141,7 @@
120 uart3: serial@4002a000 { 141 uart3: serial@4002a000 {
121 compatible = "fsl,vf610-lpuart"; 142 compatible = "fsl,vf610-lpuart";
122 reg = <0x4002a000 0x1000>; 143 reg = <0x4002a000 0x1000>;
144 interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&clks VF610_CLK_UART3>; 145 clocks = <&clks VF610_CLK_UART3>;
124 clock-names = "ipg"; 146 clock-names = "ipg";
125 dmas = <&edma0 0 8>, 147 dmas = <&edma0 0 8>,
@@ -133,15 +155,29 @@
133 #size-cells = <0>; 155 #size-cells = <0>;
134 compatible = "fsl,vf610-dspi"; 156 compatible = "fsl,vf610-dspi";
135 reg = <0x4002c000 0x1000>; 157 reg = <0x4002c000 0x1000>;
158 interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&clks VF610_CLK_DSPI0>; 159 clocks = <&clks VF610_CLK_DSPI0>;
137 clock-names = "dspi"; 160 clock-names = "dspi";
138 spi-num-chipselects = <5>; 161 spi-num-chipselects = <5>;
139 status = "disabled"; 162 status = "disabled";
140 }; 163 };
141 164
165 dspi1: dspi1@4002d000 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,vf610-dspi";
169 reg = <0x4002d000 0x1000>;
170 interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&clks VF610_CLK_DSPI1>;
172 clock-names = "dspi";
173 spi-num-chipselects = <5>;
174 status = "disabled";
175 };
176
142 sai2: sai@40031000 { 177 sai2: sai@40031000 {
143 compatible = "fsl,vf610-sai"; 178 compatible = "fsl,vf610-sai";
144 reg = <0x40031000 0x1000>; 179 reg = <0x40031000 0x1000>;
180 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&clks VF610_CLK_SAI2>; 181 clocks = <&clks VF610_CLK_SAI2>;
146 clock-names = "sai"; 182 clock-names = "sai";
147 dma-names = "tx", "rx"; 183 dma-names = "tx", "rx";
@@ -153,6 +189,7 @@
153 pit: pit@40037000 { 189 pit: pit@40037000 {
154 compatible = "fsl,vf610-pit"; 190 compatible = "fsl,vf610-pit";
155 reg = <0x40037000 0x1000>; 191 reg = <0x40037000 0x1000>;
192 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&clks VF610_CLK_PIT>; 193 clocks = <&clks VF610_CLK_PIT>;
157 clock-names = "pit"; 194 clock-names = "pit";
158 }; 195 };
@@ -186,6 +223,7 @@
186 adc0: adc@4003b000 { 223 adc0: adc@4003b000 {
187 compatible = "fsl,vf610-adc"; 224 compatible = "fsl,vf610-adc";
188 reg = <0x4003b000 0x1000>; 225 reg = <0x4003b000 0x1000>;
226 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&clks VF610_CLK_ADC0>; 227 clocks = <&clks VF610_CLK_ADC0>;
190 clock-names = "adc"; 228 clock-names = "adc";
191 status = "disabled"; 229 status = "disabled";
@@ -194,6 +232,7 @@
194 wdoga5: wdog@4003e000 { 232 wdoga5: wdog@4003e000 {
195 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; 233 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
196 reg = <0x4003e000 0x1000>; 234 reg = <0x4003e000 0x1000>;
235 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clks VF610_CLK_WDT>; 236 clocks = <&clks VF610_CLK_WDT>;
198 clock-names = "wdog"; 237 clock-names = "wdog";
199 status = "disabled"; 238 status = "disabled";
@@ -204,6 +243,7 @@
204 #size-cells = <0>; 243 #size-cells = <0>;
205 compatible = "fsl,vf610-qspi"; 244 compatible = "fsl,vf610-qspi";
206 reg = <0x40044000 0x1000>; 245 reg = <0x40044000 0x1000>;
246 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&clks VF610_CLK_QSPI0_EN>, 247 clocks = <&clks VF610_CLK_QSPI0_EN>,
208 <&clks VF610_CLK_QSPI0>; 248 <&clks VF610_CLK_QSPI0>;
209 clock-names = "qspi_en", "qspi"; 249 clock-names = "qspi_en", "qspi";
@@ -213,7 +253,6 @@
213 iomuxc: iomuxc@40048000 { 253 iomuxc: iomuxc@40048000 {
214 compatible = "fsl,vf610-iomuxc"; 254 compatible = "fsl,vf610-iomuxc";
215 reg = <0x40048000 0x1000>; 255 reg = <0x40048000 0x1000>;
216 #gpio-range-cells = <3>;
217 }; 256 };
218 257
219 gpio0: gpio@40049000 { 258 gpio0: gpio@40049000 {
@@ -221,6 +260,7 @@
221 reg = <0x40049000 0x1000 0x400ff000 0x40>; 260 reg = <0x40049000 0x1000 0x400ff000 0x40>;
222 gpio-controller; 261 gpio-controller;
223 #gpio-cells = <2>; 262 #gpio-cells = <2>;
263 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
224 interrupt-controller; 264 interrupt-controller;
225 #interrupt-cells = <2>; 265 #interrupt-cells = <2>;
226 gpio-ranges = <&iomuxc 0 0 32>; 266 gpio-ranges = <&iomuxc 0 0 32>;
@@ -231,6 +271,7 @@
231 reg = <0x4004a000 0x1000 0x400ff040 0x40>; 271 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
232 gpio-controller; 272 gpio-controller;
233 #gpio-cells = <2>; 273 #gpio-cells = <2>;
274 interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
234 interrupt-controller; 275 interrupt-controller;
235 #interrupt-cells = <2>; 276 #interrupt-cells = <2>;
236 gpio-ranges = <&iomuxc 0 32 32>; 277 gpio-ranges = <&iomuxc 0 32 32>;
@@ -241,6 +282,7 @@
241 reg = <0x4004b000 0x1000 0x400ff080 0x40>; 282 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
242 gpio-controller; 283 gpio-controller;
243 #gpio-cells = <2>; 284 #gpio-cells = <2>;
285 interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
244 interrupt-controller; 286 interrupt-controller;
245 #interrupt-cells = <2>; 287 #interrupt-cells = <2>;
246 gpio-ranges = <&iomuxc 0 64 32>; 288 gpio-ranges = <&iomuxc 0 64 32>;
@@ -251,6 +293,7 @@
251 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; 293 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
252 gpio-controller; 294 gpio-controller;
253 #gpio-cells = <2>; 295 #gpio-cells = <2>;
296 interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
254 interrupt-controller; 297 interrupt-controller;
255 #interrupt-cells = <2>; 298 #interrupt-cells = <2>;
256 gpio-ranges = <&iomuxc 0 96 32>; 299 gpio-ranges = <&iomuxc 0 96 32>;
@@ -261,6 +304,7 @@
261 reg = <0x4004d000 0x1000 0x400ff100 0x40>; 304 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
262 gpio-controller; 305 gpio-controller;
263 #gpio-cells = <2>; 306 #gpio-cells = <2>;
307 interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
264 interrupt-controller; 308 interrupt-controller;
265 #interrupt-cells = <2>; 309 #interrupt-cells = <2>;
266 gpio-ranges = <&iomuxc 0 128 7>; 310 gpio-ranges = <&iomuxc 0 128 7>;
@@ -274,6 +318,7 @@
274 usbphy0: usbphy@40050800 { 318 usbphy0: usbphy@40050800 {
275 compatible = "fsl,vf610-usbphy"; 319 compatible = "fsl,vf610-usbphy";
276 reg = <0x40050800 0x400>; 320 reg = <0x40050800 0x400>;
321 interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&clks VF610_CLK_USBPHY0>; 322 clocks = <&clks VF610_CLK_USBPHY0>;
278 fsl,anatop = <&anatop>; 323 fsl,anatop = <&anatop>;
279 status = "disabled"; 324 status = "disabled";
@@ -282,6 +327,7 @@
282 usbphy1: usbphy@40050c00 { 327 usbphy1: usbphy@40050c00 {
283 compatible = "fsl,vf610-usbphy"; 328 compatible = "fsl,vf610-usbphy";
284 reg = <0x40050c00 0x400>; 329 reg = <0x40050c00 0x400>;
330 interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&clks VF610_CLK_USBPHY1>; 331 clocks = <&clks VF610_CLK_USBPHY1>;
286 fsl,anatop = <&anatop>; 332 fsl,anatop = <&anatop>;
287 status = "disabled"; 333 status = "disabled";
@@ -292,6 +338,7 @@
292 #size-cells = <0>; 338 #size-cells = <0>;
293 compatible = "fsl,vf610-i2c"; 339 compatible = "fsl,vf610-i2c";
294 reg = <0x40066000 0x1000>; 340 reg = <0x40066000 0x1000>;
341 interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clks VF610_CLK_I2C0>; 342 clocks = <&clks VF610_CLK_I2C0>;
296 clock-names = "ipg"; 343 clock-names = "ipg";
297 dmas = <&edma0 0 50>, 344 dmas = <&edma0 0 50>,
@@ -311,6 +358,7 @@
311 usbdev0: usb@40034000 { 358 usbdev0: usb@40034000 {
312 compatible = "fsl,vf610-usb", "fsl,imx27-usb"; 359 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
313 reg = <0x40034000 0x800>; 360 reg = <0x40034000 0x800>;
361 interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&clks VF610_CLK_USBC0>; 362 clocks = <&clks VF610_CLK_USBC0>;
315 fsl,usbphy = <&usbphy0>; 363 fsl,usbphy = <&usbphy0>;
316 fsl,usbmisc = <&usbmisc0 0>; 364 fsl,usbmisc = <&usbmisc0 0>;
@@ -329,6 +377,7 @@
329 src: src@4006e000 { 377 src: src@4006e000 {
330 compatible = "fsl,vf610-src", "syscon"; 378 compatible = "fsl,vf610-src", "syscon";
331 reg = <0x4006e000 0x1000>; 379 reg = <0x4006e000 0x1000>;
380 interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
332 }; 381 };
333 }; 382 };
334 383
@@ -345,6 +394,9 @@
345 <0x400a1000 0x1000>, 394 <0x400a1000 0x1000>,
346 <0x400a2000 0x1000>; 395 <0x400a2000 0x1000>;
347 dma-channels = <32>; 396 dma-channels = <32>;
397 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
398 <11 IRQ_TYPE_LEVEL_HIGH>;
399 interrupt-names = "edma-tx", "edma-err";
348 clock-names = "dmamux0", "dmamux1"; 400 clock-names = "dmamux0", "dmamux1";
349 clocks = <&clks VF610_CLK_DMAMUX2>, 401 clocks = <&clks VF610_CLK_DMAMUX2>,
350 <&clks VF610_CLK_DMAMUX3>; 402 <&clks VF610_CLK_DMAMUX3>;
@@ -360,6 +412,7 @@
360 snvsrtc: snvs-rtc-lp@34 { 412 snvsrtc: snvs-rtc-lp@34 {
361 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 413 compatible = "fsl,sec-v4.0-mon-rtc-lp";
362 reg = <0x34 0x58>; 414 reg = <0x34 0x58>;
415 interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&clks VF610_CLK_SNVS>; 416 clocks = <&clks VF610_CLK_SNVS>;
364 clock-names = "snvs-rtc"; 417 clock-names = "snvs-rtc";
365 }; 418 };
@@ -368,6 +421,7 @@
368 uart4: serial@400a9000 { 421 uart4: serial@400a9000 {
369 compatible = "fsl,vf610-lpuart"; 422 compatible = "fsl,vf610-lpuart";
370 reg = <0x400a9000 0x1000>; 423 reg = <0x400a9000 0x1000>;
424 interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clks VF610_CLK_UART4>; 425 clocks = <&clks VF610_CLK_UART4>;
372 clock-names = "ipg"; 426 clock-names = "ipg";
373 status = "disabled"; 427 status = "disabled";
@@ -376,6 +430,7 @@
376 uart5: serial@400aa000 { 430 uart5: serial@400aa000 {
377 compatible = "fsl,vf610-lpuart"; 431 compatible = "fsl,vf610-lpuart";
378 reg = <0x400aa000 0x1000>; 432 reg = <0x400aa000 0x1000>;
433 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clks VF610_CLK_UART5>; 434 clocks = <&clks VF610_CLK_UART5>;
380 clock-names = "ipg"; 435 clock-names = "ipg";
381 status = "disabled"; 436 status = "disabled";
@@ -384,6 +439,7 @@
384 adc1: adc@400bb000 { 439 adc1: adc@400bb000 {
385 compatible = "fsl,vf610-adc"; 440 compatible = "fsl,vf610-adc";
386 reg = <0x400bb000 0x1000>; 441 reg = <0x400bb000 0x1000>;
442 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks VF610_CLK_ADC1>; 443 clocks = <&clks VF610_CLK_ADC1>;
388 clock-names = "adc"; 444 clock-names = "adc";
389 status = "disabled"; 445 status = "disabled";
@@ -392,6 +448,7 @@
392 esdhc1: esdhc@400b2000 { 448 esdhc1: esdhc@400b2000 {
393 compatible = "fsl,imx53-esdhc"; 449 compatible = "fsl,imx53-esdhc";
394 reg = <0x400b2000 0x1000>; 450 reg = <0x400b2000 0x1000>;
451 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&clks VF610_CLK_IPG_BUS>, 452 clocks = <&clks VF610_CLK_IPG_BUS>,
396 <&clks VF610_CLK_PLATFORM_BUS>, 453 <&clks VF610_CLK_PLATFORM_BUS>,
397 <&clks VF610_CLK_ESDHC1>; 454 <&clks VF610_CLK_ESDHC1>;
@@ -402,6 +459,7 @@
402 usbh1: usb@400b4000 { 459 usbh1: usb@400b4000 {
403 compatible = "fsl,vf610-usb", "fsl,imx27-usb"; 460 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
404 reg = <0x400b4000 0x800>; 461 reg = <0x400b4000 0x800>;
462 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clks VF610_CLK_USBC1>; 463 clocks = <&clks VF610_CLK_USBC1>;
406 fsl,usbphy = <&usbphy1>; 464 fsl,usbphy = <&usbphy1>;
407 fsl,usbmisc = <&usbmisc1 0>; 465 fsl,usbmisc = <&usbmisc1 0>;
@@ -420,6 +478,7 @@
420 ftm: ftm@400b8000 { 478 ftm: ftm@400b8000 {
421 compatible = "fsl,ftm-timer"; 479 compatible = "fsl,ftm-timer";
422 reg = <0x400b8000 0x1000 0x400b9000 0x1000>; 480 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
481 interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
423 clock-names = "ftm-evt", "ftm-src", 482 clock-names = "ftm-evt", "ftm-src",
424 "ftm-evt-counter-en", "ftm-src-counter-en"; 483 "ftm-evt-counter-en", "ftm-src-counter-en";
425 clocks = <&clks VF610_CLK_FTM2>, 484 clocks = <&clks VF610_CLK_FTM2>,
@@ -432,6 +491,7 @@
432 fec0: ethernet@400d0000 { 491 fec0: ethernet@400d0000 {
433 compatible = "fsl,mvf600-fec"; 492 compatible = "fsl,mvf600-fec";
434 reg = <0x400d0000 0x1000>; 493 reg = <0x400d0000 0x1000>;
494 interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&clks VF610_CLK_ENET0>, 495 clocks = <&clks VF610_CLK_ENET0>,
436 <&clks VF610_CLK_ENET0>, 496 <&clks VF610_CLK_ENET0>,
437 <&clks VF610_CLK_ENET>; 497 <&clks VF610_CLK_ENET>;
@@ -442,6 +502,7 @@
442 fec1: ethernet@400d1000 { 502 fec1: ethernet@400d1000 {
443 compatible = "fsl,mvf600-fec"; 503 compatible = "fsl,mvf600-fec";
444 reg = <0x400d1000 0x1000>; 504 reg = <0x400d1000 0x1000>;
505 interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&clks VF610_CLK_ENET1>, 506 clocks = <&clks VF610_CLK_ENET1>,
446 <&clks VF610_CLK_ENET1>, 507 <&clks VF610_CLK_ENET1>,
447 <&clks VF610_CLK_ENET>; 508 <&clks VF610_CLK_ENET>;
@@ -452,6 +513,7 @@
452 can1: flexcan@400d4000 { 513 can1: flexcan@400d4000 {
453 compatible = "fsl,vf610-flexcan"; 514 compatible = "fsl,vf610-flexcan";
454 reg = <0x400d4000 0x4000>; 515 reg = <0x400d4000 0x4000>;
516 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&clks VF610_CLK_FLEXCAN1>, 517 clocks = <&clks VF610_CLK_FLEXCAN1>,
456 <&clks VF610_CLK_FLEXCAN1>; 518 <&clks VF610_CLK_FLEXCAN1>;
457 clock-names = "ipg", "per"; 519 clock-names = "ipg", "per";
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 771ecfe96c14..0f04e30b726d 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -66,6 +66,7 @@ unsigned int imx_get_soc_revision(void);
66void imx_init_revision_from_anatop(void); 66void imx_init_revision_from_anatop(void);
67struct device *imx_soc_device_init(void); 67struct device *imx_soc_device_init(void);
68void imx6_enable_rbc(bool enable); 68void imx6_enable_rbc(bool enable);
69void imx_gpc_check_dt(void);
69void imx_gpc_set_arm_power_in_lpm(bool power_off); 70void imx_gpc_set_arm_power_in_lpm(bool power_off);
70void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw); 71void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
71void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw); 72void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
@@ -101,7 +102,6 @@ static inline void imx_scu_map_io(void) {}
101static inline void imx_smp_prepare(void) {} 102static inline void imx_smp_prepare(void) {}
102#endif 103#endif
103void imx_src_init(void); 104void imx_src_init(void);
104void imx_gpc_init(void);
105void imx_gpc_pre_suspend(bool arm_power_off); 105void imx_gpc_pre_suspend(bool arm_power_off);
106void imx_gpc_post_resume(void); 106void imx_gpc_post_resume(void);
107void imx_gpc_mask_all(void); 107void imx_gpc_mask_all(void);
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 029f59ce2712..4d60005e9277 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -36,6 +36,7 @@
36#define GPC_PGC_SW_SHIFT 0x0 36#define GPC_PGC_SW_SHIFT 0x0
37 37
38#define IMR_NUM 4 38#define IMR_NUM 4
39#define GPC_MAX_IRQS (IMR_NUM * 32)
39 40
40#define GPU_VPU_PUP_REQ BIT(1) 41#define GPU_VPU_PUP_REQ BIT(1)
41#define GPU_VPU_PDN_REQ BIT(0) 42#define GPU_VPU_PDN_REQ BIT(0)
@@ -99,17 +100,17 @@ void imx_gpc_post_resume(void)
99 100
100static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on) 101static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
101{ 102{
102 unsigned int idx = d->hwirq / 32 - 1; 103 unsigned int idx = d->hwirq / 32;
103 u32 mask; 104 u32 mask;
104 105
105 /* Sanity check for SPI irq */
106 if (d->hwirq < 32)
107 return -EINVAL;
108
109 mask = 1 << d->hwirq % 32; 106 mask = 1 << d->hwirq % 32;
110 gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask : 107 gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
111 gpc_wake_irqs[idx] & ~mask; 108 gpc_wake_irqs[idx] & ~mask;
112 109
110 /*
111 * Do *not* call into the parent, as the GIC doesn't have any
112 * wake-up facility...
113 */
113 return 0; 114 return 0;
114} 115}
115 116
@@ -139,7 +140,7 @@ void imx_gpc_hwirq_unmask(unsigned int hwirq)
139 void __iomem *reg; 140 void __iomem *reg;
140 u32 val; 141 u32 val;
141 142
142 reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4; 143 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
143 val = readl_relaxed(reg); 144 val = readl_relaxed(reg);
144 val &= ~(1 << hwirq % 32); 145 val &= ~(1 << hwirq % 32);
145 writel_relaxed(val, reg); 146 writel_relaxed(val, reg);
@@ -150,7 +151,7 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
150 void __iomem *reg; 151 void __iomem *reg;
151 u32 val; 152 u32 val;
152 153
153 reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4; 154 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
154 val = readl_relaxed(reg); 155 val = readl_relaxed(reg);
155 val |= 1 << (hwirq % 32); 156 val |= 1 << (hwirq % 32);
156 writel_relaxed(val, reg); 157 writel_relaxed(val, reg);
@@ -158,39 +159,130 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
158 159
159static void imx_gpc_irq_unmask(struct irq_data *d) 160static void imx_gpc_irq_unmask(struct irq_data *d)
160{ 161{
161 /* Sanity check for SPI irq */
162 if (d->hwirq < 32)
163 return;
164
165 imx_gpc_hwirq_unmask(d->hwirq); 162 imx_gpc_hwirq_unmask(d->hwirq);
163 irq_chip_unmask_parent(d);
166} 164}
167 165
168static void imx_gpc_irq_mask(struct irq_data *d) 166static void imx_gpc_irq_mask(struct irq_data *d)
169{ 167{
170 /* Sanity check for SPI irq */
171 if (d->hwirq < 32)
172 return;
173
174 imx_gpc_hwirq_mask(d->hwirq); 168 imx_gpc_hwirq_mask(d->hwirq);
169 irq_chip_mask_parent(d);
170}
171
172static struct irq_chip imx_gpc_chip = {
173 .name = "GPC",
174 .irq_eoi = irq_chip_eoi_parent,
175 .irq_mask = imx_gpc_irq_mask,
176 .irq_unmask = imx_gpc_irq_unmask,
177 .irq_retrigger = irq_chip_retrigger_hierarchy,
178 .irq_set_wake = imx_gpc_irq_set_wake,
179#ifdef CONFIG_SMP
180 .irq_set_affinity = irq_chip_set_affinity_parent,
181#endif
182};
183
184static int imx_gpc_domain_xlate(struct irq_domain *domain,
185 struct device_node *controller,
186 const u32 *intspec,
187 unsigned int intsize,
188 unsigned long *out_hwirq,
189 unsigned int *out_type)
190{
191 if (domain->of_node != controller)
192 return -EINVAL; /* Shouldn't happen, really... */
193 if (intsize != 3)
194 return -EINVAL; /* Not GIC compliant */
195 if (intspec[0] != 0)
196 return -EINVAL; /* No PPI should point to this domain */
197
198 *out_hwirq = intspec[1];
199 *out_type = intspec[2];
200 return 0;
175} 201}
176 202
177void __init imx_gpc_init(void) 203static int imx_gpc_domain_alloc(struct irq_domain *domain,
204 unsigned int irq,
205 unsigned int nr_irqs, void *data)
178{ 206{
179 struct device_node *np; 207 struct of_phandle_args *args = data;
208 struct of_phandle_args parent_args;
209 irq_hw_number_t hwirq;
180 int i; 210 int i;
181 211
182 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); 212 if (args->args_count != 3)
183 gpc_base = of_iomap(np, 0); 213 return -EINVAL; /* Not GIC compliant */
184 WARN_ON(!gpc_base); 214 if (args->args[0] != 0)
215 return -EINVAL; /* No PPI should point to this domain */
216
217 hwirq = args->args[1];
218 if (hwirq >= GPC_MAX_IRQS)
219 return -EINVAL; /* Can't deal with this */
220
221 for (i = 0; i < nr_irqs; i++)
222 irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
223 &imx_gpc_chip, NULL);
224
225 parent_args = *args;
226 parent_args.np = domain->parent->of_node;
227 return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, &parent_args);
228}
229
230static struct irq_domain_ops imx_gpc_domain_ops = {
231 .xlate = imx_gpc_domain_xlate,
232 .alloc = imx_gpc_domain_alloc,
233 .free = irq_domain_free_irqs_common,
234};
235
236static int __init imx_gpc_init(struct device_node *node,
237 struct device_node *parent)
238{
239 struct irq_domain *parent_domain, *domain;
240 int i;
241
242 if (!parent) {
243 pr_err("%s: no parent, giving up\n", node->full_name);
244 return -ENODEV;
245 }
246
247 parent_domain = irq_find_host(parent);
248 if (!parent_domain) {
249 pr_err("%s: unable to obtain parent domain\n", node->full_name);
250 return -ENXIO;
251 }
252
253 gpc_base = of_iomap(node, 0);
254 if (WARN_ON(!gpc_base))
255 return -ENOMEM;
256
257 domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
258 node, &imx_gpc_domain_ops,
259 NULL);
260 if (!domain) {
261 iounmap(gpc_base);
262 return -ENOMEM;
263 }
185 264
186 /* Initially mask all interrupts */ 265 /* Initially mask all interrupts */
187 for (i = 0; i < IMR_NUM; i++) 266 for (i = 0; i < IMR_NUM; i++)
188 writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4); 267 writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
189 268
190 /* Register GPC as the secondary interrupt controller behind GIC */ 269 return 0;
191 gic_arch_extn.irq_mask = imx_gpc_irq_mask; 270}
192 gic_arch_extn.irq_unmask = imx_gpc_irq_unmask; 271
193 gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake; 272/*
273 * We cannot use the IRQCHIP_DECLARE macro that lives in
274 * drivers/irqchip, so we're forced to roll our own. Not very nice.
275 */
276OF_DECLARE_2(irqchip, imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
277
278void __init imx_gpc_check_dt(void)
279{
280 struct device_node *np;
281
282 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
283 if (WARN_ON(!np ||
284 !of_find_property(np, "interrupt-controller", NULL)))
285 pr_warn("Outdated DT detected, system is about to crash!!!\n");
194} 286}
195 287
196#ifdef CONFIG_PM_GENERIC_DOMAINS 288#ifdef CONFIG_PM_GENERIC_DOMAINS
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 9de3412af406..3ab61549ce0f 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -388,10 +388,10 @@ static void __init imx6q_map_io(void)
388 388
389static void __init imx6q_init_irq(void) 389static void __init imx6q_init_irq(void)
390{ 390{
391 imx_gpc_check_dt();
391 imx_init_revision_from_anatop(); 392 imx_init_revision_from_anatop();
392 imx_init_l2cache(); 393 imx_init_l2cache();
393 imx_src_init(); 394 imx_src_init();
394 imx_gpc_init();
395 irqchip_init(); 395 irqchip_init();
396} 396}
397 397
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 24bfaaf944c8..12a1b098fc6a 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -61,10 +61,10 @@ static void __init imx6sl_init_machine(void)
61 61
62static void __init imx6sl_init_irq(void) 62static void __init imx6sl_init_irq(void)
63{ 63{
64 imx_gpc_check_dt();
64 imx_init_revision_from_anatop(); 65 imx_init_revision_from_anatop();
65 imx_init_l2cache(); 66 imx_init_l2cache();
66 imx_src_init(); 67 imx_src_init();
67 imx_gpc_init();
68 irqchip_init(); 68 irqchip_init();
69} 69}
70 70
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index 66988eb6a3a4..f17b7004c24b 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -81,10 +81,10 @@ static void __init imx6sx_init_machine(void)
81 81
82static void __init imx6sx_init_irq(void) 82static void __init imx6sx_init_irq(void)
83{ 83{
84 imx_gpc_check_dt();
84 imx_init_revision_from_anatop(); 85 imx_init_revision_from_anatop();
85 imx_init_l2cache(); 86 imx_init_l2cache();
86 imx_src_init(); 87 imx_src_init();
87 imx_gpc_init();
88 irqchip_init(); 88 irqchip_init();
89} 89}
90 90
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 46fd695203c7..6a7c6fc780cc 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -310,10 +310,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
310 * Low-Power mode. 310 * Low-Power mode.
311 * 3) Software should mask IRQ #32 right after CCM Low-Power mode 311 * 3) Software should mask IRQ #32 right after CCM Low-Power mode
312 * is set (set bits 0-1 of CCM_CLPCR). 312 * is set (set bits 0-1 of CCM_CLPCR).
313 *
314 * Note that IRQ #32 is GIC SPI #0.
313 */ 315 */
314 imx_gpc_hwirq_unmask(32); 316 imx_gpc_hwirq_unmask(0);
315 writel_relaxed(val, ccm_base + CLPCR); 317 writel_relaxed(val, ccm_base + CLPCR);
316 imx_gpc_hwirq_mask(32); 318 imx_gpc_hwirq_mask(0);
317 319
318 return 0; 320 return 0;
319} 321}
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 3e4b4ae8c75b..6468f15f060c 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -81,6 +81,7 @@ config ARCH_OMAP2PLUS
81 select GENERIC_IRQ_CHIP 81 select GENERIC_IRQ_CHIP
82 select MACH_OMAP_GENERIC 82 select MACH_OMAP_GENERIC
83 select MEMORY 83 select MEMORY
84 select MFD_SYSCON
84 select OMAP_DM_TIMER 85 select OMAP_DM_TIMER
85 select OMAP_GPMC 86 select OMAP_GPMC
86 select PINCTRL 87 select PINCTRL
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 6124db5c37ae..a699d7169307 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -23,6 +23,9 @@
23#include <linux/clk-provider.h> 23#include <linux/clk-provider.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/bitops.h> 25#include <linux/bitops.h>
26#include <linux/regmap.h>
27#include <linux/of_address.h>
28#include <linux/bootmem.h>
26#include <asm/cpu.h> 29#include <asm/cpu.h>
27 30
28#include <trace/events/power.h> 31#include <trace/events/power.h>
@@ -72,30 +75,110 @@ struct ti_clk_features ti_clk_features;
72static bool clkdm_control = true; 75static bool clkdm_control = true;
73 76
74static LIST_HEAD(clk_hw_omap_clocks); 77static LIST_HEAD(clk_hw_omap_clocks);
75void __iomem *clk_memmaps[CLK_MAX_MEMMAPS]; 78
79struct clk_iomap {
80 struct regmap *regmap;
81 void __iomem *mem;
82};
83
84static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS];
85
86static void clk_memmap_writel(u32 val, void __iomem *reg)
87{
88 struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
89 struct clk_iomap *io = clk_memmaps[r->index];
90
91 if (io->regmap)
92 regmap_write(io->regmap, r->offset, val);
93 else
94 writel_relaxed(val, io->mem + r->offset);
95}
96
97static u32 clk_memmap_readl(void __iomem *reg)
98{
99 u32 val;
100 struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
101 struct clk_iomap *io = clk_memmaps[r->index];
102
103 if (io->regmap)
104 regmap_read(io->regmap, r->offset, &val);
105 else
106 val = readl_relaxed(io->mem + r->offset);
107
108 return val;
109}
76 110
77void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) 111void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
78{ 112{
79 if (clk->flags & MEMMAP_ADDRESSING) { 113 if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
80 struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
81 writel_relaxed(val, clk_memmaps[r->index] + r->offset);
82 } else {
83 writel_relaxed(val, reg); 114 writel_relaxed(val, reg);
84 } 115 else
116 clk_memmap_writel(val, reg);
85} 117}
86 118
87u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) 119u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
88{ 120{
89 u32 val; 121 if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
122 return readl_relaxed(reg);
123 else
124 return clk_memmap_readl(reg);
125}
90 126
91 if (clk->flags & MEMMAP_ADDRESSING) { 127static struct ti_clk_ll_ops omap_clk_ll_ops = {
92 struct clk_omap_reg *r = (struct clk_omap_reg *)&reg; 128 .clk_readl = clk_memmap_readl,
93 val = readl_relaxed(clk_memmaps[r->index] + r->offset); 129 .clk_writel = clk_memmap_writel,
94 } else { 130};
95 val = readl_relaxed(reg);
96 }
97 131
98 return val; 132/**
133 * omap2_clk_provider_init - initialize a clock provider
134 * @match_table: DT device table to match for devices to init
135 * @np: device node pointer for the this clock provider
136 * @index: index for the clock provider
137 + @syscon: syscon regmap pointer
138 * @mem: iomem pointer for the clock provider memory area, only used if
139 * syscon is not provided
140 *
141 * Initializes a clock provider module (CM/PRM etc.), registering
142 * the memory mapping at specified index and initializing the
143 * low level driver infrastructure. Returns 0 in success.
144 */
145int __init omap2_clk_provider_init(struct device_node *np, int index,
146 struct regmap *syscon, void __iomem *mem)
147{
148 struct clk_iomap *io;
149
150 ti_clk_ll_ops = &omap_clk_ll_ops;
151
152 io = kzalloc(sizeof(*io), GFP_KERNEL);
153
154 io->regmap = syscon;
155 io->mem = mem;
156
157 clk_memmaps[index] = io;
158
159 ti_dt_clk_init_provider(np, index);
160
161 return 0;
162}
163
164/**
165 * omap2_clk_legacy_provider_init - initialize a legacy clock provider
166 * @index: index for the clock provider
167 * @mem: iomem pointer for the clock provider memory area
168 *
169 * Initializes a legacy clock provider memory mapping.
170 */
171void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem)
172{
173 struct clk_iomap *io;
174
175 ti_clk_ll_ops = &omap_clk_ll_ops;
176
177 io = memblock_virt_alloc(sizeof(*io), 0);
178
179 io->mem = mem;
180
181 clk_memmaps[index] = io;
99} 182}
100 183
101/* 184/*
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index a56742f96000..652ed0ab86ec 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -271,10 +271,14 @@ extern const struct clksel_rate div_1_3_rates[];
271extern const struct clksel_rate div_1_4_rates[]; 271extern const struct clksel_rate div_1_4_rates[];
272extern const struct clksel_rate div31_1to31_rates[]; 272extern const struct clksel_rate div31_1to31_rates[];
273 273
274extern void __iomem *clk_memmaps[];
275
276extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); 274extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
277extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); 275extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
278 276
277struct regmap;
278
279int __init omap2_clk_provider_init(struct device_node *np, int index,
280 struct regmap *syscon, void __iomem *mem);
281void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem);
282
279void __init ti_clk_init_features(void); 283void __init ti_clk_init_features(void);
280#endif 284#endif
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 6222e87a79b6..1fe3e6b833d2 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -70,6 +70,8 @@ int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
70int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs); 70int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
71extern int cm_register(struct cm_ll_data *cld); 71extern int cm_register(struct cm_ll_data *cld);
72extern int cm_unregister(struct cm_ll_data *cld); 72extern int cm_unregister(struct cm_ll_data *cld);
73int omap_cm_init(void);
74int omap2_cm_base_init(void);
73 75
74# endif 76# endif
75 77
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index ef62ac9dcd05..3e5fd3587eb1 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -393,7 +393,7 @@ static struct cm_ll_data omap2xxx_cm_ll_data = {
393 .wait_module_ready = &omap2xxx_cm_wait_module_ready, 393 .wait_module_ready = &omap2xxx_cm_wait_module_ready,
394}; 394};
395 395
396int __init omap2xxx_cm_init(void) 396int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data)
397{ 397{
398 return cm_register(&omap2xxx_cm_ll_data); 398 return cm_register(&omap2xxx_cm_ll_data);
399} 399}
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index 83b6c597b0e1..7b8c79c0ce27 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -63,7 +63,7 @@ extern u32 omap2xxx_cm_get_core_pll_config(void);
63extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, 63extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
64 u32 mdm); 64 u32 mdm);
65 65
66extern int __init omap2xxx_cm_init(void); 66int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data);
67 67
68#endif 68#endif
69 69
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index cc5aac784278..7b181f929525 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -352,7 +352,7 @@ static struct cm_ll_data am33xx_cm_ll_data = {
352 .module_disable = &am33xx_cm_module_disable, 352 .module_disable = &am33xx_cm_module_disable,
353}; 353};
354 354
355int __init am33xx_cm_init(void) 355int __init am33xx_cm_init(const struct omap_prcm_init_data *data)
356{ 356{
357 return cm_register(&am33xx_cm_ll_data); 357 return cm_register(&am33xx_cm_ll_data);
358} 358}
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 046b4b2bc9d9..a91f7d282455 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -19,6 +19,7 @@
19 19
20#include "cm.h" 20#include "cm.h"
21#include "cm-regbits-33xx.h" 21#include "cm-regbits-33xx.h"
22#include "prcm-common.h"
22 23
23/* CM base address */ 24/* CM base address */
24#define AM33XX_CM_BASE 0x44e00000 25#define AM33XX_CM_BASE 0x44e00000
@@ -374,6 +375,6 @@
374 375
375 376
376#ifndef __ASSEMBLER__ 377#ifndef __ASSEMBLER__
377int am33xx_cm_init(void); 378int am33xx_cm_init(const struct omap_prcm_init_data *data);
378#endif /* ASSEMBLER */ 379#endif /* ASSEMBLER */
379#endif 380#endif
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index ebead8f035f9..187fa4386718 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -671,8 +671,9 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
671 .wait_module_ready = &omap3xxx_cm_wait_module_ready, 671 .wait_module_ready = &omap3xxx_cm_wait_module_ready,
672}; 672};
673 673
674int __init omap3xxx_cm_init(void) 674int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
675{ 675{
676 omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD);
676 return cm_register(&omap3xxx_cm_ll_data); 677 return cm_register(&omap3xxx_cm_ll_data);
677} 678}
678 679
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 734a8581c0c4..bc444e2080a1 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -72,7 +72,7 @@ extern void omap3_cm_save_context(void);
72extern void omap3_cm_restore_context(void); 72extern void omap3_cm_restore_context(void);
73extern void omap3_cm_save_scratchpad_contents(u32 *ptr); 73extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
74 74
75extern int __init omap3xxx_cm_init(void); 75int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data);
76 76
77#endif 77#endif
78 78
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 728d06a4af19..309a4c913448 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -23,7 +23,6 @@
23#define OMAP4_CM_CLKSTCTRL 0x0000 23#define OMAP4_CM_CLKSTCTRL 0x0000
24#define OMAP4_CM_STATICDEP 0x0004 24#define OMAP4_CM_STATICDEP 0x0004
25 25
26void omap_cm_base_init(void); 26int omap4_cm_init(const struct omap_prcm_init_data *data);
27int omap4_cm_init(void);
28 27
29#endif 28#endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 8fe02fcedc48..23e8bcec34e3 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -15,10 +15,14 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/errno.h> 16#include <linux/errno.h>
17#include <linux/bug.h> 17#include <linux/bug.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
18 20
19#include "cm2xxx.h" 21#include "cm2xxx.h"
20#include "cm3xxx.h" 22#include "cm3xxx.h"
23#include "cm33xx.h"
21#include "cm44xx.h" 24#include "cm44xx.h"
25#include "clock.h"
22 26
23/* 27/*
24 * cm_ll_data: function pointers to SoC-specific implementations of 28 * cm_ll_data: function pointers to SoC-specific implementations of
@@ -33,6 +37,9 @@ void __iomem *cm_base;
33/* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */ 37/* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
34void __iomem *cm2_base; 38void __iomem *cm2_base;
35 39
40#define CM_NO_CLOCKS 0x1
41#define CM_SINGLE_INSTANCE 0x2
42
36/** 43/**
37 * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use) 44 * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use)
38 * @cm: CM base virtual address 45 * @cm: CM base virtual address
@@ -212,3 +219,152 @@ int cm_unregister(struct cm_ll_data *cld)
212 219
213 return 0; 220 return 0;
214} 221}
222
223#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
224 defined(CONFIG_SOC_DRA7XX)
225static struct omap_prcm_init_data cm_data __initdata = {
226 .index = TI_CLKM_CM,
227 .init = omap4_cm_init,
228};
229
230static struct omap_prcm_init_data cm2_data __initdata = {
231 .index = TI_CLKM_CM2,
232 .init = omap4_cm_init,
233};
234#endif
235
236#ifdef CONFIG_ARCH_OMAP2
237static struct omap_prcm_init_data omap2_prcm_data __initdata = {
238 .index = TI_CLKM_CM,
239 .init = omap2xxx_cm_init,
240 .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
241};
242#endif
243
244#ifdef CONFIG_ARCH_OMAP3
245static struct omap_prcm_init_data omap3_cm_data __initdata = {
246 .index = TI_CLKM_CM,
247 .init = omap3xxx_cm_init,
248 .flags = CM_SINGLE_INSTANCE,
249
250 /*
251 * IVA2 offset is a negative value, must offset the cm_base address
252 * by this to get it to positive side on the iomap
253 */
254 .offset = -OMAP3430_IVA2_MOD,
255};
256#endif
257
258#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
259static struct omap_prcm_init_data am3_prcm_data __initdata = {
260 .index = TI_CLKM_CM,
261 .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
262 .init = am33xx_cm_init,
263};
264#endif
265
266#ifdef CONFIG_SOC_AM43XX
267static struct omap_prcm_init_data am4_prcm_data __initdata = {
268 .index = TI_CLKM_CM,
269 .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
270 .init = omap4_cm_init,
271};
272#endif
273
274static const struct of_device_id omap_cm_dt_match_table[] __initconst = {
275#ifdef CONFIG_ARCH_OMAP2
276 { .compatible = "ti,omap2-prcm", .data = &omap2_prcm_data },
277#endif
278#ifdef CONFIG_ARCH_OMAP3
279 { .compatible = "ti,omap3-cm", .data = &omap3_cm_data },
280#endif
281#ifdef CONFIG_ARCH_OMAP4
282 { .compatible = "ti,omap4-cm1", .data = &cm_data },
283 { .compatible = "ti,omap4-cm2", .data = &cm2_data },
284#endif
285#ifdef CONFIG_SOC_OMAP5
286 { .compatible = "ti,omap5-cm-core-aon", .data = &cm_data },
287 { .compatible = "ti,omap5-cm-core", .data = &cm2_data },
288#endif
289#ifdef CONFIG_SOC_DRA7XX
290 { .compatible = "ti,dra7-cm-core-aon", .data = &cm_data },
291 { .compatible = "ti,dra7-cm-core", .data = &cm2_data },
292#endif
293#ifdef CONFIG_SOC_AM33XX
294 { .compatible = "ti,am3-prcm", .data = &am3_prcm_data },
295#endif
296#ifdef CONFIG_SOC_AM43XX
297 { .compatible = "ti,am4-prcm", .data = &am4_prcm_data },
298#endif
299#ifdef CONFIG_SOC_TI81XX
300 { .compatible = "ti,dm814-prcm", .data = &am3_prcm_data },
301 { .compatible = "ti,dm816-prcm", .data = &am3_prcm_data },
302#endif
303 { }
304};
305
306/**
307 * omap2_cm_base_init - initialize iomappings for the CM drivers
308 *
309 * Detects and initializes the iomappings for the CM driver, based
310 * on the DT data. Returns 0 in success, negative error value
311 * otherwise.
312 */
313int __init omap2_cm_base_init(void)
314{
315 struct device_node *np;
316 const struct of_device_id *match;
317 struct omap_prcm_init_data *data;
318 void __iomem *mem;
319
320 for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
321 data = (struct omap_prcm_init_data *)match->data;
322
323 mem = of_iomap(np, 0);
324 if (!mem)
325 return -ENOMEM;
326
327 if (data->index == TI_CLKM_CM)
328 cm_base = mem + data->offset;
329
330 if (data->index == TI_CLKM_CM2)
331 cm2_base = mem + data->offset;
332
333 data->mem = mem;
334
335 data->np = np;
336
337 if (data->init && (data->flags & CM_SINGLE_INSTANCE ||
338 (cm_base && cm2_base)))
339 data->init(data);
340 }
341
342 return 0;
343}
344
345/**
346 * omap_cm_init - low level init for the CM drivers
347 *
348 * Initializes the low level clock infrastructure for CM drivers.
349 * Returns 0 in success, negative error value in failure.
350 */
351int __init omap_cm_init(void)
352{
353 struct device_node *np;
354 const struct of_device_id *match;
355 const struct omap_prcm_init_data *data;
356 int ret;
357
358 for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
359 data = match->data;
360
361 if (data->flags & CM_NO_CLOCKS)
362 continue;
363
364 ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
365 if (ret)
366 return ret;
367 }
368
369 return 0;
370}
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 95a8cff66aff..2c0e07ed6b99 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -63,7 +63,7 @@ static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
63 * Populates the base addresses of the _cm_bases 63 * Populates the base addresses of the _cm_bases
64 * array used for read/write of cm module registers. 64 * array used for read/write of cm module registers.
65 */ 65 */
66void omap_cm_base_init(void) 66static void omap_cm_base_init(void)
67{ 67{
68 _cm_bases[OMAP4430_PRM_PARTITION] = prm_base; 68 _cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
69 _cm_bases[OMAP4430_CM1_PARTITION] = cm_base; 69 _cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
@@ -514,8 +514,10 @@ static struct cm_ll_data omap4xxx_cm_ll_data = {
514 .module_disable = &omap4_cminst_module_disable, 514 .module_disable = &omap4_cminst_module_disable,
515}; 515};
516 516
517int __init omap4_cm_init(void) 517int __init omap4_cm_init(const struct omap_prcm_init_data *data)
518{ 518{
519 omap_cm_base_init();
520
519 return cm_register(&omap4xxx_cm_ll_data); 521 return cm_register(&omap4xxx_cm_ll_data);
520} 522}
521 523
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index da041b4ab29c..af95a624fe71 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -14,6 +14,9 @@
14 14
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/of_address.h>
18#include <linux/regmap.h>
19#include <linux/mfd/syscon.h>
17 20
18#include "soc.h" 21#include "soc.h"
19#include "iomap.h" 22#include "iomap.h"
@@ -25,13 +28,15 @@
25#include "sdrc.h" 28#include "sdrc.h"
26#include "pm.h" 29#include "pm.h"
27#include "control.h" 30#include "control.h"
31#include "clock.h"
28 32
29/* Used by omap3_ctrl_save_padconf() */ 33/* Used by omap3_ctrl_save_padconf() */
30#define START_PADCONF_SAVE 0x2 34#define START_PADCONF_SAVE 0x2
31#define PADCONF_SAVE_DONE 0x1 35#define PADCONF_SAVE_DONE 0x1
32 36
33static void __iomem *omap2_ctrl_base; 37static void __iomem *omap2_ctrl_base;
34static void __iomem *omap4_ctrl_pad_base; 38static s16 omap2_ctrl_offset;
39static struct regmap *omap2_ctrl_syscon;
35 40
36#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 41#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
37struct omap3_scratchpad { 42struct omap3_scratchpad {
@@ -133,66 +138,79 @@ struct omap3_control_regs {
133static struct omap3_control_regs control_context; 138static struct omap3_control_regs control_context;
134#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 139#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
135 140
136#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) 141void __init omap2_set_globals_control(void __iomem *ctrl)
137#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg))
138
139void __init omap2_set_globals_control(void __iomem *ctrl,
140 void __iomem *ctrl_pad)
141{ 142{
142 omap2_ctrl_base = ctrl; 143 omap2_ctrl_base = ctrl;
143 omap4_ctrl_pad_base = ctrl_pad;
144}
145
146void __iomem *omap_ctrl_base_get(void)
147{
148 return omap2_ctrl_base;
149} 144}
150 145
151u8 omap_ctrl_readb(u16 offset) 146u8 omap_ctrl_readb(u16 offset)
152{ 147{
153 return readb_relaxed(OMAP_CTRL_REGADDR(offset)); 148 u32 val;
149 u8 byte_offset = offset & 0x3;
150
151 val = omap_ctrl_readl(offset);
152
153 return (val >> (byte_offset * 8)) & 0xff;
154} 154}
155 155
156u16 omap_ctrl_readw(u16 offset) 156u16 omap_ctrl_readw(u16 offset)
157{ 157{
158 return readw_relaxed(OMAP_CTRL_REGADDR(offset)); 158 u32 val;
159 u16 byte_offset = offset & 0x2;
160
161 val = omap_ctrl_readl(offset);
162
163 return (val >> (byte_offset * 8)) & 0xffff;
159} 164}
160 165
161u32 omap_ctrl_readl(u16 offset) 166u32 omap_ctrl_readl(u16 offset)
162{ 167{
163 return readl_relaxed(OMAP_CTRL_REGADDR(offset)); 168 u32 val;
169
170 offset &= 0xfffc;
171 if (!omap2_ctrl_syscon)
172 val = readl_relaxed(omap2_ctrl_base + offset);
173 else
174 regmap_read(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
175 &val);
176
177 return val;
164} 178}
165 179
166void omap_ctrl_writeb(u8 val, u16 offset) 180void omap_ctrl_writeb(u8 val, u16 offset)
167{ 181{
168 writeb_relaxed(val, OMAP_CTRL_REGADDR(offset)); 182 u32 tmp;
183 u8 byte_offset = offset & 0x3;
184
185 tmp = omap_ctrl_readl(offset);
186
187 tmp &= 0xffffffff ^ (0xff << (byte_offset * 8));
188 tmp |= val << (byte_offset * 8);
189
190 omap_ctrl_writel(tmp, offset);
169} 191}
170 192
171void omap_ctrl_writew(u16 val, u16 offset) 193void omap_ctrl_writew(u16 val, u16 offset)
172{ 194{
173 writew_relaxed(val, OMAP_CTRL_REGADDR(offset)); 195 u32 tmp;
174} 196 u8 byte_offset = offset & 0x2;
175 197
176void omap_ctrl_writel(u32 val, u16 offset) 198 tmp = omap_ctrl_readl(offset);
177{
178 writel_relaxed(val, OMAP_CTRL_REGADDR(offset));
179}
180 199
181/* 200 tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8));
182 * On OMAP4 control pad are not addressable from control 201 tmp |= val << (byte_offset * 8);
183 * core base. So the common omap_ctrl_read/write APIs breaks
184 * Hence export separate APIs to manage the omap4 pad control
185 * registers. This APIs will work only for OMAP4
186 */
187 202
188u32 omap4_ctrl_pad_readl(u16 offset) 203 omap_ctrl_writel(tmp, offset);
189{
190 return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
191} 204}
192 205
193void omap4_ctrl_pad_writel(u32 val, u16 offset) 206void omap_ctrl_writel(u32 val, u16 offset)
194{ 207{
195 writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset)); 208 offset &= 0xfffc;
209 if (!omap2_ctrl_syscon)
210 writel_relaxed(val, omap2_ctrl_base + offset);
211 else
212 regmap_write(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
213 val);
196} 214}
197 215
198#ifdef CONFIG_ARCH_OMAP3 216#ifdef CONFIG_ARCH_OMAP3
@@ -611,3 +629,120 @@ void __init omap3_ctrl_init(void)
611 omap3_ctrl_setup_d2d_padconf(); 629 omap3_ctrl_setup_d2d_padconf();
612} 630}
613#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 631#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
632
633struct control_init_data {
634 int index;
635 s16 offset;
636};
637
638static struct control_init_data ctrl_data = {
639 .index = TI_CLKM_CTRL,
640};
641
642static const struct control_init_data omap2_ctrl_data = {
643 .index = TI_CLKM_CTRL,
644 .offset = -OMAP2_CONTROL_GENERAL,
645};
646
647static const struct of_device_id omap_scrm_dt_match_table[] = {
648 { .compatible = "ti,am3-scm", .data = &ctrl_data },
649 { .compatible = "ti,am4-scm", .data = &ctrl_data },
650 { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
651 { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
652 { .compatible = "ti,dm816-scrm", .data = &ctrl_data },
653 { .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
654 { .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
655 { .compatible = "ti,dra7-scm-core", .data = &ctrl_data },
656 { }
657};
658
659/**
660 * omap2_control_base_init - initialize iomappings for the control driver
661 *
662 * Detects and initializes the iomappings for the control driver, based
663 * on the DT data. Returns 0 in success, negative error value
664 * otherwise.
665 */
666int __init omap2_control_base_init(void)
667{
668 struct device_node *np;
669 const struct of_device_id *match;
670 struct control_init_data *data;
671
672 for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
673 data = (struct control_init_data *)match->data;
674
675 omap2_ctrl_base = of_iomap(np, 0);
676 if (!omap2_ctrl_base)
677 return -ENOMEM;
678
679 omap2_ctrl_offset = data->offset;
680 }
681
682 return 0;
683}
684
685/**
686 * omap_control_init - low level init for the control driver
687 *
688 * Initializes the low level clock infrastructure for control driver.
689 * Returns 0 in success, negative error value in failure.
690 */
691int __init omap_control_init(void)
692{
693 struct device_node *np, *scm_conf;
694 const struct of_device_id *match;
695 const struct omap_prcm_init_data *data;
696 int ret;
697 struct regmap *syscon;
698
699 for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
700 data = match->data;
701
702 /*
703 * Check if we have scm_conf node, if yes, use this to
704 * access clock registers.
705 */
706 scm_conf = of_get_child_by_name(np, "scm_conf");
707
708 if (scm_conf) {
709 syscon = syscon_node_to_regmap(scm_conf);
710
711 if (IS_ERR(syscon))
712 return PTR_ERR(syscon);
713
714 omap2_ctrl_syscon = syscon;
715
716 if (of_get_child_by_name(scm_conf, "clocks")) {
717 ret = omap2_clk_provider_init(scm_conf,
718 data->index,
719 syscon, NULL);
720 if (ret)
721 return ret;
722 }
723
724 iounmap(omap2_ctrl_base);
725 omap2_ctrl_base = NULL;
726 } else {
727 /* No scm_conf found, direct access */
728 ret = omap2_clk_provider_init(np, data->index, NULL,
729 omap2_ctrl_base);
730 if (ret)
731 return ret;
732 }
733 }
734
735 return 0;
736}
737
738/**
739 * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
740 *
741 * Legacy iomap init for clock provider. Needed only by legacy boot mode,
742 * where the base addresses are not parsed from DT, but still required
743 * by the clock driver to be setup properly.
744 */
745void __init omap3_control_legacy_iomap_init(void)
746{
747 omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
748}
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b8a487181210..80d2b7d8e36e 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -440,15 +440,12 @@
440 440
441#ifndef __ASSEMBLY__ 441#ifndef __ASSEMBLY__
442#ifdef CONFIG_ARCH_OMAP2PLUS 442#ifdef CONFIG_ARCH_OMAP2PLUS
443extern void __iomem *omap_ctrl_base_get(void);
444extern u8 omap_ctrl_readb(u16 offset); 443extern u8 omap_ctrl_readb(u16 offset);
445extern u16 omap_ctrl_readw(u16 offset); 444extern u16 omap_ctrl_readw(u16 offset);
446extern u32 omap_ctrl_readl(u16 offset); 445extern u32 omap_ctrl_readl(u16 offset);
447extern u32 omap4_ctrl_pad_readl(u16 offset);
448extern void omap_ctrl_writeb(u8 val, u16 offset); 446extern void omap_ctrl_writeb(u8 val, u16 offset);
449extern void omap_ctrl_writew(u16 val, u16 offset); 447extern void omap_ctrl_writew(u16 val, u16 offset);
450extern void omap_ctrl_writel(u32 val, u16 offset); 448extern void omap_ctrl_writel(u32 val, u16 offset);
451extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
452 449
453extern void omap3_save_scratchpad_contents(void); 450extern void omap3_save_scratchpad_contents(void);
454extern void omap3_clear_scratchpad_contents(void); 451extern void omap3_clear_scratchpad_contents(void);
@@ -464,10 +461,11 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
464extern void omap3630_ctrl_disable_rta(void); 461extern void omap3630_ctrl_disable_rta(void);
465extern int omap3_ctrl_save_padconf(void); 462extern int omap3_ctrl_save_padconf(void);
466void omap3_ctrl_init(void); 463void omap3_ctrl_init(void);
467extern void omap2_set_globals_control(void __iomem *ctrl, 464int omap2_control_base_init(void);
468 void __iomem *ctrl_pad); 465int omap_control_init(void);
466void omap2_set_globals_control(void __iomem *ctrl);
467void __init omap3_control_legacy_iomap_init(void);
469#else 468#else
470#define omap_ctrl_base_get() 0
471#define omap_ctrl_readb(x) 0 469#define omap_ctrl_readb(x) 0
472#define omap_ctrl_readw(x) 0 470#define omap_ctrl_readw(x) 0
473#define omap_ctrl_readl(x) 0 471#define omap_ctrl_readl(x) 0
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 7a050f9c37ff..f492ae147c6a 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -26,6 +26,8 @@
26#include <linux/of.h> 26#include <linux/of.h>
27#include <linux/of_platform.h> 27#include <linux/of_platform.h>
28#include <linux/slab.h> 28#include <linux/slab.h>
29#include <linux/mfd/syscon.h>
30#include <linux/regmap.h>
29 31
30#include <video/omapdss.h> 32#include <video/omapdss.h>
31#include "omap_hwmod.h" 33#include "omap_hwmod.h"
@@ -104,6 +106,10 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
104 { "dss_hdmi", "omapdss_hdmi", -1 }, 106 { "dss_hdmi", "omapdss_hdmi", -1 },
105}; 107};
106 108
109#define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
110
111static struct regmap *omap4_dsi_mux_syscon;
112
107static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) 113static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
108{ 114{
109 u32 enable_mask, enable_shift; 115 u32 enable_mask, enable_shift;
@@ -124,7 +130,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
124 return -ENODEV; 130 return -ENODEV;
125 } 131 }
126 132
127 reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); 133 regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, &reg);
128 134
129 reg &= ~enable_mask; 135 reg &= ~enable_mask;
130 reg &= ~pipd_mask; 136 reg &= ~pipd_mask;
@@ -132,7 +138,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
132 reg |= (lanes << enable_shift) & enable_mask; 138 reg |= (lanes << enable_shift) & enable_mask;
133 reg |= (lanes << pipd_shift) & pipd_mask; 139 reg |= (lanes << pipd_shift) & pipd_mask;
134 140
135 omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); 141 regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
136 142
137 return 0; 143 return 0;
138} 144}
@@ -665,5 +671,10 @@ int __init omapdss_init_of(void)
665 return r; 671 return r;
666 } 672 }
667 673
674 /* add DSI info for omap4 */
675 node = of_find_node_by_name(NULL, "omap4_padconf_global");
676 if (node)
677 omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
678
668 return 0; 679 return 0;
669} 680}
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 25f1beea453e..e3f713ffb06b 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -52,7 +52,10 @@ EXPORT_SYMBOL(omap_rev);
52 52
53int omap_type(void) 53int omap_type(void)
54{ 54{
55 u32 val = 0; 55 static u32 val = OMAP2_DEVICETYPE_MASK;
56
57 if (val < OMAP2_DEVICETYPE_MASK)
58 return val;
56 59
57 if (cpu_is_omap24xx()) { 60 if (cpu_is_omap24xx()) {
58 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); 61 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 1eeff6be260d..820dde8b5b04 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -382,13 +382,9 @@ void __init omap2420_init_early(void)
382 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); 382 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
383 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), 383 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
384 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); 384 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
385 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE), 385 omap2_control_base_init();
386 NULL);
387 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
388 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
389 omap2xxx_check_revision(); 386 omap2xxx_check_revision();
390 omap2xxx_prm_init(); 387 omap2_prcm_base_init();
391 omap2xxx_cm_init();
392 omap2xxx_voltagedomains_init(); 388 omap2xxx_voltagedomains_init();
393 omap242x_powerdomains_init(); 389 omap242x_powerdomains_init();
394 omap242x_clockdomains_init(); 390 omap242x_clockdomains_init();
@@ -412,13 +408,9 @@ void __init omap2430_init_early(void)
412 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); 408 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
413 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), 409 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
414 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); 410 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
415 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), 411 omap2_control_base_init();
416 NULL);
417 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
418 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
419 omap2xxx_check_revision(); 412 omap2xxx_check_revision();
420 omap2xxx_prm_init(); 413 omap2_prcm_base_init();
421 omap2xxx_cm_init();
422 omap2xxx_voltagedomains_init(); 414 omap2xxx_voltagedomains_init();
423 omap243x_powerdomains_init(); 415 omap243x_powerdomains_init();
424 omap243x_clockdomains_init(); 416 omap243x_clockdomains_init();
@@ -446,21 +438,30 @@ void __init omap3_init_early(void)
446 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); 438 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
447 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), 439 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
448 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); 440 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
449 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), 441 /* XXX: remove these once OMAP3 is DT only */
450 NULL); 442 if (!of_have_populated_dt()) {
451 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); 443 omap2_set_globals_control(
452 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); 444 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
445 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
446 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
447 NULL);
448 }
449 omap2_control_base_init();
453 omap3xxx_check_revision(); 450 omap3xxx_check_revision();
454 omap3xxx_check_features(); 451 omap3xxx_check_features();
455 omap3xxx_prm_init(); 452 omap2_prcm_base_init();
456 omap3xxx_cm_init(); 453 /* XXX: remove these once OMAP3 is DT only */
454 if (!of_have_populated_dt()) {
455 omap3xxx_prm_init(NULL);
456 omap3xxx_cm_init(NULL);
457 }
457 omap3xxx_voltagedomains_init(); 458 omap3xxx_voltagedomains_init();
458 omap3xxx_powerdomains_init(); 459 omap3xxx_powerdomains_init();
459 omap3xxx_clockdomains_init(); 460 omap3xxx_clockdomains_init();
460 omap3xxx_hwmod_init(); 461 omap3xxx_hwmod_init();
461 omap_hwmod_init_postsetup(); 462 omap_hwmod_init_postsetup();
462 if (!of_have_populated_dt()) { 463 if (!of_have_populated_dt()) {
463 omap3_prcm_legacy_iomaps_init(); 464 omap3_control_legacy_iomap_init();
464 if (soc_is_am35xx()) 465 if (soc_is_am35xx())
465 omap_clk_soc_init = am35xx_clk_legacy_init; 466 omap_clk_soc_init = am35xx_clk_legacy_init;
466 else if (cpu_is_omap3630()) 467 else if (cpu_is_omap3630())
@@ -547,14 +548,10 @@ void __init ti814x_init_early(void)
547{ 548{
548 omap2_set_globals_tap(TI814X_CLASS, 549 omap2_set_globals_tap(TI814X_CLASS,
549 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); 550 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
550 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), 551 omap2_control_base_init();
551 NULL);
552 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
553 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
554 omap3xxx_check_revision(); 552 omap3xxx_check_revision();
555 ti81xx_check_features(); 553 ti81xx_check_features();
556 am33xx_prm_init(); 554 omap2_prcm_base_init();
557 am33xx_cm_init();
558 omap3xxx_voltagedomains_init(); 555 omap3xxx_voltagedomains_init();
559 omap3xxx_powerdomains_init(); 556 omap3xxx_powerdomains_init();
560 ti81xx_clockdomains_init(); 557 ti81xx_clockdomains_init();
@@ -568,14 +565,10 @@ void __init ti816x_init_early(void)
568{ 565{
569 omap2_set_globals_tap(TI816X_CLASS, 566 omap2_set_globals_tap(TI816X_CLASS,
570 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); 567 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
571 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), 568 omap2_control_base_init();
572 NULL);
573 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
574 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
575 omap3xxx_check_revision(); 569 omap3xxx_check_revision();
576 ti81xx_check_features(); 570 ti81xx_check_features();
577 am33xx_prm_init(); 571 omap2_prcm_base_init();
578 am33xx_cm_init();
579 omap3xxx_voltagedomains_init(); 572 omap3xxx_voltagedomains_init();
580 omap3xxx_powerdomains_init(); 573 omap3xxx_powerdomains_init();
581 ti81xx_clockdomains_init(); 574 ti81xx_clockdomains_init();
@@ -591,14 +584,10 @@ void __init am33xx_init_early(void)
591{ 584{
592 omap2_set_globals_tap(AM335X_CLASS, 585 omap2_set_globals_tap(AM335X_CLASS,
593 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 586 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
594 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), 587 omap2_control_base_init();
595 NULL);
596 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
597 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
598 omap3xxx_check_revision(); 588 omap3xxx_check_revision();
599 am33xx_check_features(); 589 am33xx_check_features();
600 am33xx_prm_init(); 590 omap2_prcm_base_init();
601 am33xx_cm_init();
602 am33xx_powerdomains_init(); 591 am33xx_powerdomains_init();
603 am33xx_clockdomains_init(); 592 am33xx_clockdomains_init();
604 am33xx_hwmod_init(); 593 am33xx_hwmod_init();
@@ -617,16 +606,10 @@ void __init am43xx_init_early(void)
617{ 606{
618 omap2_set_globals_tap(AM335X_CLASS, 607 omap2_set_globals_tap(AM335X_CLASS,
619 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 608 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
620 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), 609 omap2_control_base_init();
621 NULL);
622 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
623 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
624 omap_prm_base_init();
625 omap_cm_base_init();
626 omap3xxx_check_revision(); 610 omap3xxx_check_revision();
627 am33xx_check_features(); 611 am33xx_check_features();
628 omap44xx_prm_init(); 612 omap2_prcm_base_init();
629 omap4_cm_init();
630 am43xx_powerdomains_init(); 613 am43xx_powerdomains_init();
631 am43xx_clockdomains_init(); 614 am43xx_clockdomains_init();
632 am43xx_hwmod_init(); 615 am43xx_hwmod_init();
@@ -646,19 +629,12 @@ void __init omap4430_init_early(void)
646{ 629{
647 omap2_set_globals_tap(OMAP443X_CLASS, 630 omap2_set_globals_tap(OMAP443X_CLASS,
648 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); 631 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
649 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
650 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
651 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
652 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
653 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
654 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); 632 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
655 omap_prm_base_init(); 633 omap2_control_base_init();
656 omap_cm_base_init();
657 omap4xxx_check_revision(); 634 omap4xxx_check_revision();
658 omap4xxx_check_features(); 635 omap4xxx_check_features();
659 omap4_cm_init(); 636 omap2_prcm_base_init();
660 omap4_pm_init_early(); 637 omap4_pm_init_early();
661 omap44xx_prm_init();
662 omap44xx_voltagedomains_init(); 638 omap44xx_voltagedomains_init();
663 omap44xx_powerdomains_init(); 639 omap44xx_powerdomains_init();
664 omap44xx_clockdomains_init(); 640 omap44xx_clockdomains_init();
@@ -681,18 +657,11 @@ void __init omap5_init_early(void)
681{ 657{
682 omap2_set_globals_tap(OMAP54XX_CLASS, 658 omap2_set_globals_tap(OMAP54XX_CLASS,
683 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); 659 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
684 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
685 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
686 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
687 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
688 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
689 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 660 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
661 omap2_control_base_init();
690 omap4_pm_init_early(); 662 omap4_pm_init_early();
691 omap_prm_base_init(); 663 omap2_prcm_base_init();
692 omap_cm_base_init();
693 omap44xx_prm_init();
694 omap5xxx_check_revision(); 664 omap5xxx_check_revision();
695 omap4_cm_init();
696 omap54xx_voltagedomains_init(); 665 omap54xx_voltagedomains_init();
697 omap54xx_powerdomains_init(); 666 omap54xx_powerdomains_init();
698 omap54xx_clockdomains_init(); 667 omap54xx_clockdomains_init();
@@ -713,18 +682,11 @@ void __init omap5_init_late(void)
713void __init dra7xx_init_early(void) 682void __init dra7xx_init_early(void)
714{ 683{
715 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); 684 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
716 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
717 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
718 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
719 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
720 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
721 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 685 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
686 omap2_control_base_init();
722 omap4_pm_init_early(); 687 omap4_pm_init_early();
723 omap_prm_base_init(); 688 omap2_prcm_base_init();
724 omap_cm_base_init();
725 omap44xx_prm_init();
726 dra7xxx_check_revision(); 689 dra7xxx_check_revision();
727 omap4_cm_init();
728 dra7xx_powerdomains_init(); 690 dra7xx_powerdomains_init();
729 dra7xx_clockdomains_init(); 691 dra7xx_clockdomains_init();
730 dra7xx_hwmod_init(); 692 dra7xx_hwmod_init();
@@ -762,7 +724,11 @@ int __init omap_clk_init(void)
762 ti_clk_init_features(); 724 ti_clk_init_features();
763 725
764 if (of_have_populated_dt()) { 726 if (of_have_populated_dt()) {
765 ret = of_prcm_init(); 727 ret = omap_control_init();
728 if (ret)
729 return ret;
730
731 ret = omap_prcm_init();
766 if (ret) 732 if (ret)
767 return ret; 733 return ret;
768 734
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index fe01c5a03aa2..b1aad7e1426c 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void)
75 75
76 /* Clear old wake-up events */ 76 /* Clear old wake-up events */
77 /* REVISIT: These write to reserved bits? */ 77 /* REVISIT: These write to reserved bits? */
78 omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); 78 omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
79 omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); 79 omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
80 omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0); 80 omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
81 81
82 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); 82 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
83 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); 83 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
@@ -104,18 +104,16 @@ no_sleep:
104 clk_enable(osc_ck); 104 clk_enable(osc_ck);
105 105
106 /* clear CORE wake-up events */ 106 /* clear CORE wake-up events */
107 omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); 107 omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
108 omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); 108 omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
109 109
110 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ 110 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
111 omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1); 111 omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
112 112
113 /* MPU domain wake events */ 113 /* MPU domain wake events */
114 omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 114 omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x1);
115 0x1);
116 115
117 omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 116 omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x20);
118 0x20);
119 117
120 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 118 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
121 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON); 119 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
@@ -143,9 +141,9 @@ static void omap2_enter_mpu_retention(void)
143 * it is in retention mode. */ 141 * it is in retention mode. */
144 if (omap2_allow_mpu_retention()) { 142 if (omap2_allow_mpu_retention()) {
145 /* REVISIT: These write to reserved bits? */ 143 /* REVISIT: These write to reserved bits? */
146 omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); 144 omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
147 omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); 145 omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
148 omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0); 146 omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
149 147
150 /* Try to enter MPU retention */ 148 /* Try to enter MPU retention */
151 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); 149 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 88721df6001d..87b98bf92366 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -137,9 +137,8 @@ static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
137{ 137{
138 int c; 138 int c;
139 139
140 c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1, 140 c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
141 ~(OMAP3430_ST_IO_MASK | 141 OMAP3430_ST_IO_CHAIN_MASK);
142 OMAP3430_ST_IO_CHAIN_MASK));
143 142
144 return c ? IRQ_HANDLED : IRQ_NONE; 143 return c ? IRQ_HANDLED : IRQ_NONE;
145} 144}
@@ -153,14 +152,13 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
153 * these are handled in a separate handler to avoid acking 152 * these are handled in a separate handler to avoid acking
154 * IO events before parsing in mux code 153 * IO events before parsing in mux code
155 */ 154 */
156 c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1, 155 c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
157 OMAP3430_ST_IO_MASK | 156 OMAP3430_ST_IO_CHAIN_MASK));
158 OMAP3430_ST_IO_CHAIN_MASK); 157 c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
159 c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, 0); 158 c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
160 c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
161 if (omap_rev() > OMAP3430_REV_ES1_0) { 159 if (omap_rev() > OMAP3430_REV_ES1_0) {
162 c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, 0); 160 c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
163 c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); 161 c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
164 } 162 }
165 163
166 return c ? IRQ_HANDLED : IRQ_NONE; 164 return c ? IRQ_HANDLED : IRQ_NONE;
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 6163d66102a3..6ae0b3a1781e 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -518,6 +518,26 @@ struct omap_prcm_irq_setup {
518 .priority = _priority \ 518 .priority = _priority \
519 } 519 }
520 520
521/**
522 * struct omap_prcm_init_data - PRCM driver init data
523 * @index: clock memory mapping index to be used
524 * @mem: IO mem pointer for this module
525 * @offset: module base address offset from the IO base
526 * @flags: PRCM module init flags
527 * @device_inst_offset: device instance offset within the module address space
528 * @init: low level PRCM init function for this module
529 * @np: device node for this PRCM module
530 */
531struct omap_prcm_init_data {
532 int index;
533 void __iomem *mem;
534 s16 offset;
535 u16 flags;
536 s32 device_inst_offset;
537 int (*init)(const struct omap_prcm_init_data *data);
538 struct device_node *np;
539};
540
521extern void omap_prcm_irq_cleanup(void); 541extern void omap_prcm_irq_cleanup(void);
522extern int omap_prcm_register_chain_handler( 542extern int omap_prcm_register_chain_handler(
523 struct omap_prcm_irq_setup *irq_setup); 543 struct omap_prcm_irq_setup *irq_setup);
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index b9061a6a2db8..233bc84fbc0e 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -19,8 +19,9 @@
19extern void __iomem *prm_base; 19extern void __iomem *prm_base;
20extern u16 prm_features; 20extern u16 prm_features;
21extern void omap2_set_globals_prm(void __iomem *prm); 21extern void omap2_set_globals_prm(void __iomem *prm);
22int of_prcm_init(void); 22int omap_prcm_init(void);
23void omap3_prcm_legacy_iomaps_init(void); 23int omap2_prm_base_init(void);
24int omap2_prcm_base_init(void);
24# endif 25# endif
25 26
26/* 27/*
@@ -28,9 +29,11 @@ void omap3_prcm_legacy_iomaps_init(void);
28 * 29 *
29 * PRM_HAS_IO_WAKEUP: has IO wakeup capability 30 * PRM_HAS_IO_WAKEUP: has IO wakeup capability
30 * PRM_HAS_VOLTAGE: has voltage domains 31 * PRM_HAS_VOLTAGE: has voltage domains
32 * PRM_IRQ_DEFAULT: use default irq number for PRM irq
31 */ 33 */
32#define PRM_HAS_IO_WAKEUP (1 << 0) 34#define PRM_HAS_IO_WAKEUP BIT(0)
33#define PRM_HAS_VOLTAGE (1 << 1) 35#define PRM_HAS_VOLTAGE BIT(1)
36#define PRM_IRQ_DEFAULT BIT(2)
34 37
35/* 38/*
36 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP 39 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
@@ -146,6 +149,9 @@ struct prm_ll_data {
146 int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod, 149 int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod,
147 u16 offset); 150 u16 offset);
148 void (*reset_system)(void); 151 void (*reset_system)(void);
152 int (*clear_mod_irqs)(s16 module, u8 regs, u32 wkst_mask);
153 u32 (*vp_check_txdone)(u8 vp_id);
154 void (*vp_clear_txdone)(u8 vp_id);
149}; 155};
150 156
151extern int prm_register(struct prm_ll_data *pld); 157extern int prm_register(struct prm_ll_data *pld);
@@ -161,6 +167,19 @@ extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
161void omap_prm_reset_system(void); 167void omap_prm_reset_system(void);
162 168
163void omap_prm_reconfigure_io_chain(void); 169void omap_prm_reconfigure_io_chain(void);
170int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
171
172/*
173 * Voltage Processor (VP) identifiers
174 */
175#define OMAP3_VP_VDD_MPU_ID 0
176#define OMAP3_VP_VDD_CORE_ID 1
177#define OMAP4_VP_VDD_CORE_ID 0
178#define OMAP4_VP_VDD_IVA_ID 1
179#define OMAP4_VP_VDD_MPU_ID 2
180
181u32 omap_prm_vp_check_txdone(u8 vp_id);
182void omap_prm_vp_clear_txdone(u8 vp_id);
164 183
165#endif 184#endif
166 185
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index af0f15278fc2..752018ce129c 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -123,13 +123,14 @@ static void omap2xxx_prm_dpll_reset(void)
123 * Clears wakeup status bits for a given module, so that the device can 123 * Clears wakeup status bits for a given module, so that the device can
124 * re-enter idle. 124 * re-enter idle.
125 */ 125 */
126void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask) 126static int omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
127{ 127{
128 u32 wkst; 128 u32 wkst;
129 129
130 wkst = omap2_prm_read_mod_reg(module, regs); 130 wkst = omap2_prm_read_mod_reg(module, regs);
131 wkst &= wkst_mask; 131 wkst &= wkst_mask;
132 omap2_prm_write_mod_reg(wkst, module, regs); 132 omap2_prm_write_mod_reg(wkst, module, regs);
133 return 0;
133} 134}
134 135
135int omap2xxx_clkdm_sleep(struct clockdomain *clkdm) 136int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
@@ -216,9 +217,10 @@ static struct prm_ll_data omap2xxx_prm_ll_data = {
216 .deassert_hardreset = &omap2_prm_deassert_hardreset, 217 .deassert_hardreset = &omap2_prm_deassert_hardreset,
217 .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted, 218 .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
218 .reset_system = &omap2xxx_prm_dpll_reset, 219 .reset_system = &omap2xxx_prm_dpll_reset,
220 .clear_mod_irqs = &omap2xxx_prm_clear_mod_irqs,
219}; 221};
220 222
221int __init omap2xxx_prm_init(void) 223int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data)
222{ 224{
223 return prm_register(&omap2xxx_prm_ll_data); 225 return prm_register(&omap2xxx_prm_ll_data);
224} 226}
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index 1d51643062f7..9008a9e55a1a 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -124,9 +124,7 @@
124extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm); 124extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
125extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm); 125extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
126 126
127void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask); 127int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data);
128
129extern int __init omap2xxx_prm_init(void);
130 128
131#endif 129#endif
132 130
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 02f628601b09..dcb5001d77da 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -378,7 +378,7 @@ static struct prm_ll_data am33xx_prm_ll_data = {
378 .reset_system = am33xx_prm_global_warm_sw_reset, 378 .reset_system = am33xx_prm_global_warm_sw_reset,
379}; 379};
380 380
381int __init am33xx_prm_init(void) 381int __init am33xx_prm_init(const struct omap_prcm_init_data *data)
382{ 382{
383 return prm_register(&am33xx_prm_ll_data); 383 return prm_register(&am33xx_prm_ll_data);
384} 384}
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 98ac41f271da..2bc4ec52ba78 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -118,7 +118,7 @@
118#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004) 118#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
119 119
120#ifndef __ASSEMBLER__ 120#ifndef __ASSEMBLER__
121int am33xx_prm_init(void); 121int am33xx_prm_init(const struct omap_prcm_init_data *data);
122 122
123#endif /* ASSEMBLER */ 123#endif /* ASSEMBLER */
124#endif 124#endif
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 5713bbdf83bc..62680aad2126 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -29,6 +29,7 @@
29#include "prm-regbits-34xx.h" 29#include "prm-regbits-34xx.h"
30#include "cm3xxx.h" 30#include "cm3xxx.h"
31#include "cm-regbits-34xx.h" 31#include "cm-regbits-34xx.h"
32#include "clock.h"
32 33
33static void omap3xxx_prm_read_pending_irqs(unsigned long *events); 34static void omap3xxx_prm_read_pending_irqs(unsigned long *events);
34static void omap3xxx_prm_ocp_barrier(void); 35static void omap3xxx_prm_ocp_barrier(void);
@@ -96,7 +97,7 @@ static struct omap3_vp omap3_vp[] = {
96 97
97#define MAX_VP_ID ARRAY_SIZE(omap3_vp); 98#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
98 99
99u32 omap3_prm_vp_check_txdone(u8 vp_id) 100static u32 omap3_prm_vp_check_txdone(u8 vp_id)
100{ 101{
101 struct omap3_vp *vp = &omap3_vp[vp_id]; 102 struct omap3_vp *vp = &omap3_vp[vp_id];
102 u32 irqstatus; 103 u32 irqstatus;
@@ -106,7 +107,7 @@ u32 omap3_prm_vp_check_txdone(u8 vp_id)
106 return irqstatus & vp->tranxdone_status; 107 return irqstatus & vp->tranxdone_status;
107} 108}
108 109
109void omap3_prm_vp_clear_txdone(u8 vp_id) 110static void omap3_prm_vp_clear_txdone(u8 vp_id)
110{ 111{
111 struct omap3_vp *vp = &omap3_vp[vp_id]; 112 struct omap3_vp *vp = &omap3_vp[vp_id];
112 113
@@ -217,7 +218,7 @@ static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
217 * omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt 218 * omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
218 * @module: PRM module to clear wakeups from 219 * @module: PRM module to clear wakeups from
219 * @regs: register set to clear, 1 or 3 220 * @regs: register set to clear, 1 or 3
220 * @ignore_bits: wakeup status bits to ignore 221 * @wkst_mask: wkst bits to clear
221 * 222 *
222 * The purpose of this function is to clear any wake-up events latched 223 * The purpose of this function is to clear any wake-up events latched
223 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 224 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
@@ -226,7 +227,7 @@ static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
226 * that any peripheral wake-up events occurring while attempting to 227 * that any peripheral wake-up events occurring while attempting to
227 * clear the PM_WKST_x are detected and cleared. 228 * clear the PM_WKST_x are detected and cleared.
228 */ 229 */
229int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits) 230static int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
230{ 231{
231 u32 wkst, fclk, iclk, clken; 232 u32 wkst, fclk, iclk, clken;
232 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 233 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
@@ -238,7 +239,7 @@ int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
238 239
239 wkst = omap2_prm_read_mod_reg(module, wkst_off); 240 wkst = omap2_prm_read_mod_reg(module, wkst_off);
240 wkst &= omap2_prm_read_mod_reg(module, grpsel_off); 241 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
241 wkst &= ~ignore_bits; 242 wkst &= wkst_mask;
242 if (wkst) { 243 if (wkst) {
243 iclk = omap2_cm_read_mod_reg(module, iclk_off); 244 iclk = omap2_cm_read_mod_reg(module, iclk_off);
244 fclk = omap2_cm_read_mod_reg(module, fclk_off); 245 fclk = omap2_cm_read_mod_reg(module, fclk_off);
@@ -254,7 +255,7 @@ int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
254 omap2_cm_set_mod_reg_bits(clken, module, fclk_off); 255 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
255 omap2_prm_write_mod_reg(wkst, module, wkst_off); 256 omap2_prm_write_mod_reg(wkst, module, wkst_off);
256 wkst = omap2_prm_read_mod_reg(module, wkst_off); 257 wkst = omap2_prm_read_mod_reg(module, wkst_off);
257 wkst &= ~ignore_bits; 258 wkst &= wkst_mask;
258 c++; 259 c++;
259 } 260 }
260 omap2_cm_write_mod_reg(iclk, module, iclk_off); 261 omap2_cm_write_mod_reg(iclk, module, iclk_off);
@@ -664,10 +665,15 @@ static struct prm_ll_data omap3xxx_prm_ll_data = {
664 .deassert_hardreset = &omap2_prm_deassert_hardreset, 665 .deassert_hardreset = &omap2_prm_deassert_hardreset,
665 .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted, 666 .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
666 .reset_system = &omap3xxx_prm_dpll3_reset, 667 .reset_system = &omap3xxx_prm_dpll3_reset,
668 .clear_mod_irqs = &omap3xxx_prm_clear_mod_irqs,
669 .vp_check_txdone = &omap3_prm_vp_check_txdone,
670 .vp_clear_txdone = &omap3_prm_vp_clear_txdone,
667}; 671};
668 672
669int __init omap3xxx_prm_init(void) 673int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data)
670{ 674{
675 omap2_clk_legacy_provider_init(TI_CLKM_PRM,
676 prm_base + OMAP3430_IVA2_MOD);
671 if (omap3_has_io_wakeup()) 677 if (omap3_has_io_wakeup())
672 prm_features |= PRM_HAS_IO_WAKEUP; 678 prm_features |= PRM_HAS_IO_WAKEUP;
673 679
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index ed8a3d8b739a..5f095eec339c 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -132,10 +132,6 @@
132 132
133#ifndef __ASSEMBLER__ 133#ifndef __ASSEMBLER__
134 134
135/* OMAP3-specific VP functions */
136u32 omap3_prm_vp_check_txdone(u8 vp_id);
137void omap3_prm_vp_clear_txdone(u8 vp_id);
138
139/* 135/*
140 * OMAP3 access functions for voltage controller (VC) and 136 * OMAP3 access functions for voltage controller (VC) and
141 * voltage proccessor (VP) in the PRM. 137 * voltage proccessor (VP) in the PRM.
@@ -144,8 +140,7 @@ extern u32 omap3_prm_vcvp_read(u8 offset);
144extern void omap3_prm_vcvp_write(u32 val, u8 offset); 140extern void omap3_prm_vcvp_write(u32 val, u8 offset);
145extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); 141extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
146 142
147extern int __init omap3xxx_prm_init(void); 143int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data);
148int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
149void omap3xxx_prm_iva_idle(void); 144void omap3xxx_prm_iva_idle(void);
150void omap3_prm_reset_modem(void); 145void omap3_prm_reset_modem(void);
151int omap3xxx_prm_clear_global_cold_reset(void); 146int omap3xxx_prm_clear_global_cold_reset(void);
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index d6d6bc39e05c..4541700f743a 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -138,7 +138,7 @@ static struct omap4_vp omap4_vp[] = {
138 }, 138 },
139}; 139};
140 140
141u32 omap4_prm_vp_check_txdone(u8 vp_id) 141static u32 omap4_prm_vp_check_txdone(u8 vp_id)
142{ 142{
143 struct omap4_vp *vp = &omap4_vp[vp_id]; 143 struct omap4_vp *vp = &omap4_vp[vp_id];
144 u32 irqstatus; 144 u32 irqstatus;
@@ -149,7 +149,7 @@ u32 omap4_prm_vp_check_txdone(u8 vp_id)
149 return irqstatus & vp->tranxdone_status; 149 return irqstatus & vp->tranxdone_status;
150} 150}
151 151
152void omap4_prm_vp_clear_txdone(u8 vp_id) 152static void omap4_prm_vp_clear_txdone(u8 vp_id)
153{ 153{
154 struct omap4_vp *vp = &omap4_vp[vp_id]; 154 struct omap4_vp *vp = &omap4_vp[vp_id];
155 155
@@ -699,29 +699,31 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
699 .deassert_hardreset = omap4_prminst_deassert_hardreset, 699 .deassert_hardreset = omap4_prminst_deassert_hardreset,
700 .is_hardreset_asserted = omap4_prminst_is_hardreset_asserted, 700 .is_hardreset_asserted = omap4_prminst_is_hardreset_asserted,
701 .reset_system = omap4_prminst_global_warm_sw_reset, 701 .reset_system = omap4_prminst_global_warm_sw_reset,
702 .vp_check_txdone = omap4_prm_vp_check_txdone,
703 .vp_clear_txdone = omap4_prm_vp_clear_txdone,
702}; 704};
703 705
704int __init omap44xx_prm_init(void) 706static const struct omap_prcm_init_data *prm_init_data;
707
708int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
705{ 709{
706 if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) 710 omap_prm_base_init();
711
712 prm_init_data = data;
713
714 if (data->flags & PRM_HAS_IO_WAKEUP)
707 prm_features |= PRM_HAS_IO_WAKEUP; 715 prm_features |= PRM_HAS_IO_WAKEUP;
708 716
709 if (!soc_is_dra7xx()) 717 if (data->flags & PRM_HAS_VOLTAGE)
710 prm_features |= PRM_HAS_VOLTAGE; 718 prm_features |= PRM_HAS_VOLTAGE;
711 719
720 omap4_prminst_set_prm_dev_inst(data->device_inst_offset);
721
712 return prm_register(&omap44xx_prm_ll_data); 722 return prm_register(&omap44xx_prm_ll_data);
713} 723}
714 724
715static const struct of_device_id omap_prm_dt_match_table[] = {
716 { .compatible = "ti,omap4-prm" },
717 { .compatible = "ti,omap5-prm" },
718 { .compatible = "ti,dra7-prm" },
719 { }
720};
721
722static int omap44xx_prm_late_init(void) 725static int omap44xx_prm_late_init(void)
723{ 726{
724 struct device_node *np;
725 int irq_num; 727 int irq_num;
726 728
727 if (!(prm_features & PRM_HAS_IO_WAKEUP)) 729 if (!(prm_features & PRM_HAS_IO_WAKEUP))
@@ -731,31 +733,23 @@ static int omap44xx_prm_late_init(void)
731 if (!of_have_populated_dt()) 733 if (!of_have_populated_dt())
732 return 0; 734 return 0;
733 735
734 np = of_find_matching_node(NULL, omap_prm_dt_match_table); 736 irq_num = of_irq_get(prm_init_data->np, 0);
735 737 /*
736 if (!np) { 738 * Already have OMAP4 IRQ num. For all other platforms, we need
737 /* Default loaded up with OMAP4 values */ 739 * IRQ numbers from DT
738 if (!cpu_is_omap44xx()) 740 */
739 return 0; 741 if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
740 } else { 742 if (irq_num == -EPROBE_DEFER)
741 irq_num = of_irq_get(np, 0); 743 return irq_num;
742 /* 744
743 * Already have OMAP4 IRQ num. For all other platforms, we need 745 /* Have nothing to do */
744 * IRQ numbers from DT 746 return 0;
745 */ 747 }
746 if (irq_num < 0 && !cpu_is_omap44xx()) { 748
747 if (irq_num == -EPROBE_DEFER) 749 /* Once OMAP4 DT is filled as well */
748 return irq_num; 750 if (irq_num >= 0) {
749 751 omap4_prcm_irq_setup.irq = irq_num;
750 /* Have nothing to do */ 752 omap4_prcm_irq_setup.xlate_irq = NULL;
751 return 0;
752 }
753
754 /* Once OMAP4 DT is filled as well */
755 if (irq_num >= 0) {
756 omap4_prcm_irq_setup.irq = irq_num;
757 omap4_prcm_irq_setup.xlate_irq = NULL;
758 }
759 } 753 }
760 754
761 omap44xx_prm_enable_io_wakeup(); 755 omap44xx_prm_enable_io_wakeup();
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 7db2422faa16..efd6035d0871 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -26,7 +26,6 @@
26#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H 26#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
27 27
28#include "prm44xx_54xx.h" 28#include "prm44xx_54xx.h"
29#include "prcm-common.h"
30#include "prm.h" 29#include "prm.h"
31 30
32#define OMAP4430_PRM_BASE 0x4a306000 31#define OMAP4430_PRM_BASE 0x4a306000
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
index 714329565b90..3f139ebc8398 100644
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -23,13 +23,11 @@
23#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H 23#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
24#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H 24#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
25 25
26#include "prcm-common.h"
27
26/* Function prototypes */ 28/* Function prototypes */
27#ifndef __ASSEMBLER__ 29#ifndef __ASSEMBLER__
28 30
29/* OMAP4/OMAP5-specific VP functions */
30u32 omap4_prm_vp_check_txdone(u8 vp_id);
31void omap4_prm_vp_clear_txdone(u8 vp_id);
32
33/* 31/*
34 * OMAP4/OMAP5 access functions for voltage controller (VC) and 32 * OMAP4/OMAP5 access functions for voltage controller (VC) and
35 * voltage proccessor (VP) in the PRM. 33 * voltage proccessor (VP) in the PRM.
@@ -38,7 +36,7 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
38extern void omap4_prm_vcvp_write(u32 val, u8 offset); 36extern void omap4_prm_vcvp_write(u32 val, u8 offset);
39extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); 37extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
40 38
41extern int __init omap44xx_prm_init(void); 39int __init omap44xx_prm_init(const struct omap_prcm_init_data *data);
42 40
43#endif 41#endif
44 42
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
index e4411010309c..1eb22ff087dc 100644
--- a/arch/arm/mach-omap2/prm54xx.h
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -22,7 +22,6 @@
22#define __ARCH_ARM_MACH_OMAP2_PRM54XX_H 22#define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
23 23
24#include "prm44xx_54xx.h" 24#include "prm44xx_54xx.h"
25#include "prcm-common.h"
26#include "prm.h" 25#include "prm.h"
27 26
28#define OMAP54XX_PRM_BASE 0x4ae06000 27#define OMAP54XX_PRM_BASE 0x4ae06000
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index 4bb50fbf29be..cc1e6a2b97f6 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -22,8 +22,8 @@
22#ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H 22#ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
23#define __ARCH_ARM_MACH_OMAP2_PRM7XX_H 23#define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
24 24
25#include "prm44xx_54xx.h"
26#include "prcm-common.h" 25#include "prcm-common.h"
26#include "prm44xx_54xx.h"
27#include "prm.h" 27#include "prm.h"
28 28
29#define DRA7XX_PRM_BASE 0x4ae06000 29#define DRA7XX_PRM_BASE 0x4ae06000
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index bfaa7ba595cc..7add7994dbfc 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -32,7 +32,11 @@
32#include "prm2xxx_3xxx.h" 32#include "prm2xxx_3xxx.h"
33#include "prm2xxx.h" 33#include "prm2xxx.h"
34#include "prm3xxx.h" 34#include "prm3xxx.h"
35#include "prm33xx.h"
35#include "prm44xx.h" 36#include "prm44xx.h"
37#include "prm54xx.h"
38#include "prm7xx.h"
39#include "prcm43xx.h"
36#include "common.h" 40#include "common.h"
37#include "clock.h" 41#include "clock.h"
38#include "cm.h" 42#include "cm.h"
@@ -534,6 +538,61 @@ void omap_prm_reset_system(void)
534} 538}
535 539
536/** 540/**
541 * omap_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
542 * @module: PRM module to clear wakeups from
543 * @regs: register to clear
544 * @wkst_mask: wkst bits to clear
545 *
546 * Clears any wakeup events for the module and register set defined.
547 * Uses SoC specific implementation to do the actual wakeup status
548 * clearing.
549 */
550int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
551{
552 if (!prm_ll_data->clear_mod_irqs) {
553 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
554 __func__);
555 return -EINVAL;
556 }
557
558 return prm_ll_data->clear_mod_irqs(module, regs, wkst_mask);
559}
560
561/**
562 * omap_prm_vp_check_txdone - check voltage processor TX done status
563 *
564 * Checks if voltage processor transmission has been completed.
565 * Returns non-zero if a transmission has completed, 0 otherwise.
566 */
567u32 omap_prm_vp_check_txdone(u8 vp_id)
568{
569 if (!prm_ll_data->vp_check_txdone) {
570 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
571 __func__);
572 return 0;
573 }
574
575 return prm_ll_data->vp_check_txdone(vp_id);
576}
577
578/**
579 * omap_prm_vp_clear_txdone - clears voltage processor TX done status
580 *
581 * Clears the status bit for completed voltage processor transmission
582 * returned by prm_vp_check_txdone.
583 */
584void omap_prm_vp_clear_txdone(u8 vp_id)
585{
586 if (!prm_ll_data->vp_clear_txdone) {
587 WARN_ONCE(1, "prm: %s: no mapping function defined\n",
588 __func__);
589 return;
590 }
591
592 prm_ll_data->vp_clear_txdone(vp_id);
593}
594
595/**
537 * prm_register - register per-SoC low-level data with the PRM 596 * prm_register - register per-SoC low-level data with the PRM
538 * @pld: low-level per-SoC OMAP PRM data & function pointers to register 597 * @pld: low-level per-SoC OMAP PRM data & function pointers to register
539 * 598 *
@@ -578,78 +637,175 @@ int prm_unregister(struct prm_ll_data *pld)
578 return 0; 637 return 0;
579} 638}
580 639
581static const struct of_device_id omap_prcm_dt_match_table[] = { 640#ifdef CONFIG_ARCH_OMAP2
582 { .compatible = "ti,am3-prcm" }, 641static struct omap_prcm_init_data omap2_prm_data __initdata = {
583 { .compatible = "ti,am3-scrm" }, 642 .index = TI_CLKM_PRM,
584 { .compatible = "ti,am4-prcm" }, 643 .init = omap2xxx_prm_init,
585 { .compatible = "ti,am4-scrm" },
586 { .compatible = "ti,dm814-prcm" },
587 { .compatible = "ti,dm814-scrm" },
588 { .compatible = "ti,dm816-prcm" },
589 { .compatible = "ti,dm816-scrm" },
590 { .compatible = "ti,omap2-prcm" },
591 { .compatible = "ti,omap2-scrm" },
592 { .compatible = "ti,omap3-prm" },
593 { .compatible = "ti,omap3-cm" },
594 { .compatible = "ti,omap3-scrm" },
595 { .compatible = "ti,omap4-cm1" },
596 { .compatible = "ti,omap4-prm" },
597 { .compatible = "ti,omap4-cm2" },
598 { .compatible = "ti,omap4-scrm" },
599 { .compatible = "ti,omap5-prm" },
600 { .compatible = "ti,omap5-cm-core-aon" },
601 { .compatible = "ti,omap5-scrm" },
602 { .compatible = "ti,omap5-cm-core" },
603 { .compatible = "ti,dra7-prm" },
604 { .compatible = "ti,dra7-cm-core-aon" },
605 { .compatible = "ti,dra7-cm-core" },
606 { }
607}; 644};
645#endif
646
647#ifdef CONFIG_ARCH_OMAP3
648static struct omap_prcm_init_data omap3_prm_data __initdata = {
649 .index = TI_CLKM_PRM,
650 .init = omap3xxx_prm_init,
608 651
609static struct clk_hw_omap memmap_dummy_ck = { 652 /*
610 .flags = MEMMAP_ADDRESSING, 653 * IVA2 offset is a negative value, must offset the prm_base
654 * address by this to get it to positive
655 */
656 .offset = -OMAP3430_IVA2_MOD,
611}; 657};
658#endif
612 659
613static u32 prm_clk_readl(void __iomem *reg) 660#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
614{ 661static struct omap_prcm_init_data am3_prm_data __initdata = {
615 return omap2_clk_readl(&memmap_dummy_ck, reg); 662 .index = TI_CLKM_PRM,
616} 663 .init = am33xx_prm_init,
664};
665#endif
666
667#ifdef CONFIG_ARCH_OMAP4
668static struct omap_prcm_init_data omap4_prm_data __initdata = {
669 .index = TI_CLKM_PRM,
670 .init = omap44xx_prm_init,
671 .device_inst_offset = OMAP4430_PRM_DEVICE_INST,
672 .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE | PRM_IRQ_DEFAULT,
673};
674#endif
675
676#ifdef CONFIG_SOC_OMAP5
677static struct omap_prcm_init_data omap5_prm_data __initdata = {
678 .index = TI_CLKM_PRM,
679 .init = omap44xx_prm_init,
680 .device_inst_offset = OMAP54XX_PRM_DEVICE_INST,
681 .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE,
682};
683#endif
684
685#ifdef CONFIG_SOC_DRA7XX
686static struct omap_prcm_init_data dra7_prm_data __initdata = {
687 .index = TI_CLKM_PRM,
688 .init = omap44xx_prm_init,
689 .device_inst_offset = DRA7XX_PRM_DEVICE_INST,
690 .flags = PRM_HAS_IO_WAKEUP,
691};
692#endif
617 693
618static void prm_clk_writel(u32 val, void __iomem *reg) 694#ifdef CONFIG_SOC_AM43XX
619{ 695static struct omap_prcm_init_data am4_prm_data __initdata = {
620 omap2_clk_writel(val, &memmap_dummy_ck, reg); 696 .index = TI_CLKM_PRM,
621} 697 .init = omap44xx_prm_init,
698 .device_inst_offset = AM43XX_PRM_DEVICE_INST,
699};
700#endif
622 701
623static struct ti_clk_ll_ops omap_clk_ll_ops = { 702#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
624 .clk_readl = prm_clk_readl, 703static struct omap_prcm_init_data scrm_data __initdata = {
625 .clk_writel = prm_clk_writel, 704 .index = TI_CLKM_SCRM,
705};
706#endif
707
708static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
709#ifdef CONFIG_SOC_AM33XX
710 { .compatible = "ti,am3-prcm", .data = &am3_prm_data },
711#endif
712#ifdef CONFIG_SOC_AM43XX
713 { .compatible = "ti,am4-prcm", .data = &am4_prm_data },
714#endif
715#ifdef CONFIG_SOC_TI81XX
716 { .compatible = "ti,dm814-prcm", .data = &am3_prm_data },
717 { .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
718#endif
719#ifdef CONFIG_ARCH_OMAP2
720 { .compatible = "ti,omap2-prcm", .data = &omap2_prm_data },
721#endif
722#ifdef CONFIG_ARCH_OMAP3
723 { .compatible = "ti,omap3-prm", .data = &omap3_prm_data },
724#endif
725#ifdef CONFIG_ARCH_OMAP4
726 { .compatible = "ti,omap4-prm", .data = &omap4_prm_data },
727 { .compatible = "ti,omap4-scrm", .data = &scrm_data },
728#endif
729#ifdef CONFIG_SOC_OMAP5
730 { .compatible = "ti,omap5-prm", .data = &omap5_prm_data },
731 { .compatible = "ti,omap5-scrm", .data = &scrm_data },
732#endif
733#ifdef CONFIG_SOC_DRA7XX
734 { .compatible = "ti,dra7-prm", .data = &dra7_prm_data },
735#endif
736 { }
626}; 737};
627 738
628int __init of_prcm_init(void) 739/**
740 * omap2_prm_base_init - initialize iomappings for the PRM driver
741 *
742 * Detects and initializes the iomappings for the PRM driver, based
743 * on the DT data. Returns 0 in success, negative error value
744 * otherwise.
745 */
746int __init omap2_prm_base_init(void)
629{ 747{
630 struct device_node *np; 748 struct device_node *np;
749 const struct of_device_id *match;
750 struct omap_prcm_init_data *data;
631 void __iomem *mem; 751 void __iomem *mem;
632 int memmap_index = 0;
633 752
634 ti_clk_ll_ops = &omap_clk_ll_ops; 753 for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
754 data = (struct omap_prcm_init_data *)match->data;
635 755
636 for_each_matching_node(np, omap_prcm_dt_match_table) {
637 mem = of_iomap(np, 0); 756 mem = of_iomap(np, 0);
638 clk_memmaps[memmap_index] = mem; 757 if (!mem)
639 ti_dt_clk_init_provider(np, memmap_index); 758 return -ENOMEM;
640 memmap_index++; 759
760 if (data->index == TI_CLKM_PRM)
761 prm_base = mem + data->offset;
762
763 data->mem = mem;
764
765 data->np = np;
766
767 if (data->init)
768 data->init(data);
641 } 769 }
642 770
643 return 0; 771 return 0;
644} 772}
645 773
646void __init omap3_prcm_legacy_iomaps_init(void) 774int __init omap2_prcm_base_init(void)
647{ 775{
648 ti_clk_ll_ops = &omap_clk_ll_ops; 776 int ret;
649 777
650 clk_memmaps[TI_CLKM_CM] = cm_base + OMAP3430_IVA2_MOD; 778 ret = omap2_prm_base_init();
651 clk_memmaps[TI_CLKM_PRM] = prm_base + OMAP3430_IVA2_MOD; 779 if (ret)
652 clk_memmaps[TI_CLKM_SCRM] = omap_ctrl_base_get(); 780 return ret;
781
782 return omap2_cm_base_init();
783}
784
785/**
786 * omap_prcm_init - low level init for the PRCM drivers
787 *
788 * Initializes the low level clock infrastructure for PRCM drivers.
789 * Returns 0 in success, negative error value in failure.
790 */
791int __init omap_prcm_init(void)
792{
793 struct device_node *np;
794 const struct of_device_id *match;
795 const struct omap_prcm_init_data *data;
796 int ret;
797
798 for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
799 data = match->data;
800
801 ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
802 if (ret)
803 return ret;
804 }
805
806 omap_cm_init();
807
808 return 0;
653} 809}
654 810
655static int __init prm_late_init(void) 811static int __init prm_late_init(void)
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 8adf7b1a1dce..c4859c4d3646 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -47,22 +47,14 @@ void omap_prm_base_init(void)
47 47
48s32 omap4_prmst_get_prm_dev_inst(void) 48s32 omap4_prmst_get_prm_dev_inst(void)
49{ 49{
50 if (prm_dev_inst != PRM_INSTANCE_UNKNOWN)
51 return prm_dev_inst;
52
53 /* This cannot be done way early at boot.. as things are not setup */
54 if (cpu_is_omap44xx())
55 prm_dev_inst = OMAP4430_PRM_DEVICE_INST;
56 else if (soc_is_omap54xx())
57 prm_dev_inst = OMAP54XX_PRM_DEVICE_INST;
58 else if (soc_is_dra7xx())
59 prm_dev_inst = DRA7XX_PRM_DEVICE_INST;
60 else if (soc_is_am43xx())
61 prm_dev_inst = AM43XX_PRM_DEVICE_INST;
62
63 return prm_dev_inst; 50 return prm_dev_inst;
64} 51}
65 52
53void omap4_prminst_set_prm_dev_inst(s32 dev_inst)
54{
55 prm_dev_inst = dev_inst;
56}
57
66/* Read a register in a PRM instance */ 58/* Read a register in a PRM instance */
67u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) 59u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
68{ 60{
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
index fb1c9d7a2f9d..0c03d0731d7f 100644
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -14,6 +14,7 @@
14 14
15#define PRM_INSTANCE_UNKNOWN -1 15#define PRM_INSTANCE_UNKNOWN -1
16extern s32 omap4_prmst_get_prm_dev_inst(void); 16extern s32 omap4_prmst_get_prm_dev_inst(void);
17void omap4_prminst_set_prm_dev_inst(s32 dev_inst);
17 18
18/* 19/*
19 * In an ideal world, we would not export these low-level functions, 20 * In an ideal world, we would not export these low-level functions,
diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
index 0fdf7080e4a6..7e0829682bd0 100644
--- a/arch/arm/mach-omap2/vp.h
+++ b/arch/arm/mach-omap2/vp.h
@@ -21,15 +21,6 @@
21 21
22struct voltagedomain; 22struct voltagedomain;
23 23
24/*
25 * Voltage Processor (VP) identifiers
26 */
27#define OMAP3_VP_VDD_MPU_ID 0
28#define OMAP3_VP_VDD_CORE_ID 1
29#define OMAP4_VP_VDD_CORE_ID 0
30#define OMAP4_VP_VDD_IVA_ID 1
31#define OMAP4_VP_VDD_MPU_ID 2
32
33/* XXX document */ 24/* XXX document */
34#define VP_IDLE_TIMEOUT 200 25#define VP_IDLE_TIMEOUT 200
35#define VP_TRANXDONE_TIMEOUT 300 26#define VP_TRANXDONE_TIMEOUT 300
diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
index 1914e026245e..b0590fe6ab01 100644
--- a/arch/arm/mach-omap2/vp3xxx_data.c
+++ b/arch/arm/mach-omap2/vp3xxx_data.c
@@ -28,8 +28,8 @@
28#include "prm2xxx_3xxx.h" 28#include "prm2xxx_3xxx.h"
29 29
30static const struct omap_vp_ops omap3_vp_ops = { 30static const struct omap_vp_ops omap3_vp_ops = {
31 .check_txdone = omap3_prm_vp_check_txdone, 31 .check_txdone = omap_prm_vp_check_txdone,
32 .clear_txdone = omap3_prm_vp_clear_txdone, 32 .clear_txdone = omap_prm_vp_clear_txdone,
33}; 33};
34 34
35/* 35/*
diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
index e62f6b018beb..2448bb9a8716 100644
--- a/arch/arm/mach-omap2/vp44xx_data.c
+++ b/arch/arm/mach-omap2/vp44xx_data.c
@@ -28,8 +28,8 @@
28#include "vp.h" 28#include "vp.h"
29 29
30static const struct omap_vp_ops omap4_vp_ops = { 30static const struct omap_vp_ops omap4_vp_ops = {
31 .check_txdone = omap4_prm_vp_check_txdone, 31 .check_txdone = omap_prm_vp_check_txdone,
32 .clear_txdone = omap4_prm_vp_clear_txdone, 32 .clear_txdone = omap_prm_vp_clear_txdone,
33}; 33};
34 34
35/* 35/*
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 67844003493d..79b76e13d904 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -215,14 +215,14 @@ struct ti_dt_clk {
215 .node_name = name, \ 215 .node_name = name, \
216 } 216 }
217 217
218/* Maximum number of clock memmaps */
219#define CLK_MAX_MEMMAPS 4
220
221/* Static memmap indices */ 218/* Static memmap indices */
222enum { 219enum {
223 TI_CLKM_CM = 0, 220 TI_CLKM_CM = 0,
221 TI_CLKM_CM2,
224 TI_CLKM_PRM, 222 TI_CLKM_PRM,
225 TI_CLKM_SCRM, 223 TI_CLKM_SCRM,
224 TI_CLKM_CTRL,
225 CLK_MAX_MEMMAPS
226}; 226};
227 227
228typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *); 228typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);