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authorDoug Anderson <dianders@chromium.org>2014-10-06 13:15:27 -0400
committerHeiko Stuebner <heiko@sntech.de>2014-10-20 06:00:55 -0400
commit61e309f322f264917e5dcbd7ea773df1db53629a (patch)
treed55dab986305b137b5de86dc8c0a51dbf3130b69
parentde7d6c3eebbe6da47c07f048ca689e10f194b842 (diff)
clk: rockchip: Add CLK_SET_RATE_PARENT to aclk_cpu_pre
We'd like to be able to call clk_set_rate() on aclk_cpu (a gate) at bootup. In order for this to have any effect we need its parent (aclk_cpu_pre) to percolate the rate change to _its_ parent (aclk_cpu_src). Add CLK_SET_RATE_PARENT to make this happen. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index e41ae1f4cd29..4670bd8335a1 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -279,7 +279,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
279 RK3288_CLKGATE_CON(0), 11, GFLAGS), 279 RK3288_CLKGATE_CON(0), 11, GFLAGS),
280 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0, 280 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
281 RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS), 281 RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
282 DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0, 282 DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
283 RK3288_CLKSEL_CON(1), 0, 3, DFLAGS), 283 RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
284 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, 284 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
285 RK3288_CLKGATE_CON(0), 3, GFLAGS), 285 RK3288_CLKGATE_CON(0), 3, GFLAGS),