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authorDong Aisheng <dong.aisheng@linaro.org>2012-07-06 05:09:23 -0400
committerLinus Walleij <linus.walleij@linaro.org>2012-07-14 16:32:10 -0400
commit4a5f7eff8b0b34354e5c63272835e5e2dfe1c933 (patch)
tree9524d7c94277d1f6a119092d66724459d5462c27
parenta6e7360b22f2360d7640f99051415d49cebeb908 (diff)
pinctrl: pinctrl-imx6q: add missed mux function for USBOTG_ID
The original pin registers table is derived from u-boot mainline, but somehow it was found missing some mux functions for USBOTG_ID. We added it at the bottom by following the exist pin function ids, then it will not break the exist using of pin function id in dts file. Reported-by: Richard Zhao <richard.zhao@freescale.com> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt2
-rw-r--r--drivers/pinctrl/pinctrl-imx6q.c2
2 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
index 82b43f915857..a4119f6422d9 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
@@ -1626,3 +1626,5 @@ MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 1587
1626MX6Q_PAD_SD2_DAT3__GPIO_1_12 1588 1626MX6Q_PAD_SD2_DAT3__GPIO_1_12 1588
1627MX6Q_PAD_SD2_DAT3__SJC_DONE 1589 1627MX6Q_PAD_SD2_DAT3__SJC_DONE 1589
1628MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 1590 1628MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 1590
1629MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID 1591
1630MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID 1592
diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/pinctrl-imx6q.c
index 7737d4d71a3c..e9bf71fbedca 100644
--- a/drivers/pinctrl/pinctrl-imx6q.c
+++ b/drivers/pinctrl/pinctrl-imx6q.c
@@ -1950,6 +1950,8 @@ static struct imx_pin_reg imx6q_pin_regs[] = {
1950 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */ 1950 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */
1951 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */ 1951 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */
1952 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */ 1952 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */
1953 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID */
1954 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
1953}; 1955};
1954 1956
1955/* Pad names for the pinmux subsystem */ 1957/* Pad names for the pinmux subsystem */