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authorVinod Koul <vinod.koul@intel.com>2011-10-10 03:03:59 -0400
committerVinod Koul <vinod.koul@linux.intel.com>2011-10-16 07:46:45 -0400
commit4598fc2c94b68740e0269db03c98a1e7ad5af773 (patch)
treec70d3208052b636ab299f2f0b18af3d52bffda9f
parent2389d674bfd42aa26cbbf6064ed48ee9a87a5c7e (diff)
dmaengine: mid_dma: mask_peripheral_interrupt only when dmac is idle
The mask_peripheral_interrupt is called when channel wants to mask the interrupt. Move this to suspend as this masking affects other channels as well. Not touching unmask here and unmask would still be done of first channel use Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
-rw-r--r--drivers/dma/intel_mid_dma.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index cf74a664c5e0..9e96c43a846a 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -115,16 +115,15 @@ DMAC1 interrupt Functions*/
115 115
116/** 116/**
117 * dmac1_mask_periphral_intr - mask the periphral interrupt 117 * dmac1_mask_periphral_intr - mask the periphral interrupt
118 * @midc: dma channel for which masking is required 118 * @mid: dma device for which masking is required
119 * 119 *
120 * Masks the DMA periphral interrupt 120 * Masks the DMA periphral interrupt
121 * this is valid for DMAC1 family controllers only 121 * this is valid for DMAC1 family controllers only
122 * This controller should have periphral mask registers already mapped 122 * This controller should have periphral mask registers already mapped
123 */ 123 */
124static void dmac1_mask_periphral_intr(struct intel_mid_dma_chan *midc) 124static void dmac1_mask_periphral_intr(struct middma_device *mid)
125{ 125{
126 u32 pimr; 126 u32 pimr;
127 struct middma_device *mid = to_middma_device(midc->chan.device);
128 127
129 if (mid->pimr_mask) { 128 if (mid->pimr_mask) {
130 pimr = readl(mid->mask_reg + LNW_PERIPHRAL_MASK); 129 pimr = readl(mid->mask_reg + LNW_PERIPHRAL_MASK);
@@ -184,7 +183,6 @@ static void enable_dma_interrupt(struct intel_mid_dma_chan *midc)
184static void disable_dma_interrupt(struct intel_mid_dma_chan *midc) 183static void disable_dma_interrupt(struct intel_mid_dma_chan *midc)
185{ 184{
186 /*Check LPE PISR, make sure fwd is disabled*/ 185 /*Check LPE PISR, make sure fwd is disabled*/
187 dmac1_mask_periphral_intr(midc);
188 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_BLOCK); 186 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_BLOCK);
189 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_TFR); 187 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_TFR);
190 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_ERR); 188 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_ERR);
@@ -1348,6 +1346,7 @@ int dma_suspend(struct pci_dev *pci, pm_message_t state)
1348 if (device->ch[i].in_use) 1346 if (device->ch[i].in_use)
1349 return -EAGAIN; 1347 return -EAGAIN;
1350 } 1348 }
1349 dmac1_mask_periphral_intr(device);
1351 device->state = SUSPENDED; 1350 device->state = SUSPENDED;
1352 pci_save_state(pci); 1351 pci_save_state(pci);
1353 pci_disable_device(pci); 1352 pci_disable_device(pci);