FRV: arrange things such that BRA can reach from the trap table

Arrange the sections in the FRV arch so that a BRA instruction with a
16-bit displacement can always reach from the trap table to entry.S,
tlb-miss.S and break.S.

The problem otherwise is that the linker can insert sufficient code between
the slots in the trap table and the targets of the branch instructions in
those slots that the displacement field in the instruction isn't
sufficiently large.  This is because the branch targets were in the .text
section along with most of the other code in the kernel.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

4 files changed, 18 insertions, 15 deletions

diff --git a/arch/frv/kernel/break.S b/arch/frv/kernel/break.S
index dac4a5f68c2e..bd0bdf908d93 100644
--- a/arch/frv/kernel/break.S
+++ b/arch/frv/kernel/break.S
@@ -63,7 +63,7 @@ __break_trace_through_exceptions:
 # entry point for Break Exceptions/Interrupts
 #
 ###############################################################################
-        .text
+        .section        .text.break
         .balign         4
         .globl          __entry_break
 __entry_break:
diff --git a/arch/frv/kernel/entry.S b/arch/frv/kernel/entry.S
index 1e74f3c5cee2..f926c7094776 100644
--- a/arch/frv/kernel/entry.S
+++ b/arch/frv/kernel/entry.S
@@ -38,7 +38,7 @@
 
 #define nr_syscalls ((syscall_table_size)/4)
 
-        .text
+        .section        .text.entry
         .balign         4
 
 .macro LEDS val
diff --git a/arch/frv/kernel/vmlinux.lds.S b/arch/frv/kernel/vmlinux.lds.S
index 3b71e0c86399..a17a81d58bf6 100644
--- a/arch/frv/kernel/vmlinux.lds.S
+++ b/arch/frv/kernel/vmlinux.lds.S
@@ -76,6 +76,12 @@ SECTIONS
           *(.data.init_task)
   }
 
+  . = ALIGN(4096);
+  .data.page_aligned : { *(.data.idt) }
+
+  . = ALIGN(L1_CACHE_BYTES);
+  .data.cacheline_aligned : { *(.data.cacheline_aligned) }
+
   .trap : {
         /* trap table management - read entry-table.S before modifying */
         . = ALIGN(8192);
@@ -86,28 +92,25 @@ SECTIONS
         *(.trap.break)
   }
 
-  . = ALIGN(4096);
-  .data.page_aligned : { *(.data.idt) }
-
-  . = ALIGN(L1_CACHE_BYTES);
-  .data.cacheline_aligned : { *(.data.cacheline_aligned) }
-
   /* Text and read-only data */
   . = ALIGN(4);
   _text = .;
   _stext = .;
   .text : {
-        *(
-                .text.start .text.*
+        *(.text.start)
+        *(.text.entry)
+        *(.text.break)
+        *(.text.tlbmiss)
+        TEXT_TEXT
+        SCHED_TEXT
+        LOCK_TEXT
 #ifdef CONFIG_DEBUG_INFO
+        *(
         .init.text
         .exit.text
         .exitcall.exit
-#endif
         )
-        TEXT_TEXT
-        SCHED_TEXT
-        LOCK_TEXT
+#endif
         *(.fixup)
         *(.gnu.warning)
         *(.exitcall.exit)
diff --git a/arch/frv/mm/tlb-miss.S b/arch/frv/mm/tlb-miss.S
index 04da67468378..07643482cad2 100644
--- a/arch/frv/mm/tlb-miss.S
+++ b/arch/frv/mm/tlb-miss.S
@@ -16,7 +16,7 @@
 #include <asm/highmem.h>
 #include <asm/spr-regs.h>
 
-        .section        .text
+        .section        .text.tlbmiss
         .balign         4
 
         .globl          __entry_insn_mmu_miss