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authorSylwester Nawrocki <s.nawrocki@samsung.com>2013-04-04 00:32:33 -0400
committerKukjin Kim <kgene.kim@samsung.com>2013-04-04 02:51:07 -0400
commit36fc09722d49077c6a602e8c07b06d21e798b75a (patch)
tree525a21d163aa64863af39c46efd39fac617180b3
parent5e2e0195ec89d8e266a2530ffec335c483c64899 (diff)
clk: exynos4: Correct sclk_mfc clock definition
This clock must be exported to allow lookup using device tree. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
-rw-r--r--Documentation/devicetree/bindings/clock/exynos4-clock.txt2
-rw-r--r--drivers/clk/samsung/clk-exynos4.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index e874add25131..8b58232f3fb5 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -91,7 +91,7 @@ Exynos4 SoC and this is specified where applicable.
91 sclk_i2s1 167 91 sclk_i2s1 167
92 sclk_i2s2 168 92 sclk_i2s2 168
93 sclk_mipihsi 169 Exynos4412 93 sclk_mipihsi 169 Exynos4412
94 94 sclk_mfc 170
95 95
96 [Peripheral Clock Gates] 96 [Peripheral Clock Gates]
97 97
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index e1bb81a1c264..44a99b58c981 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -122,7 +122,7 @@ enum exynos4_clks {
122 sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4, 122 sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
123 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, 123 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
124 sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1, 124 sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
125 sclk_i2s2, sclk_mipihsi, 125 sclk_i2s2, sclk_mipihsi, sclk_mfc,
126 126
127 /* gate clocks */ 127 /* gate clocks */
128 fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0, 128 fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
@@ -355,7 +355,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
355 DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), 355 DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
356 DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), 356 DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
357 DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), 357 DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
358 DIV(none, "div_mfc", "mout_mfc", DIV_MFC, 0, 4), 358 DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
359 DIV(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4), 359 DIV(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
360 DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), 360 DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
361 DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), 361 DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),