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authorRafał Miłecki <zajec5@gmail.com>2014-09-03 16:59:45 -0400
committerRalf Baechle <ralf@linux-mips.org>2014-11-24 01:44:59 -0500
commit21400f252a97755579b43a4dc95dd02cd7f0ca75 (patch)
tree54b4dad7d552e2f2840ca5f8c0ec88ee9747368d
parent8d602dd0f984e8488ab891344ebdb6e1f3128c4a (diff)
MIPS: BCM47XX: Make ssb init NVRAM instead of bcm47xx polling it
This makes NVRAM code less bcm47xx/ssb specific allowing it to become a standalone driver in the future. A similar patch for bcma will follow when it's ready. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7612/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/bcm47xx/nvram.c30
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h1
-rw-r--r--drivers/ssb/driver_mipscore.c14
3 files changed, 23 insertions, 22 deletions
diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
index e07976bbb739..fecc5aeddd46 100644
--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@ -98,7 +98,14 @@ found:
98 return 0; 98 return 0;
99} 99}
100 100
101static int bcm47xx_nvram_init_from_mem(u32 base, u32 lim) 101/*
102 * On bcm47xx we need access to the NVRAM very early, so we can't use mtd
103 * subsystem to access flash. We can't even use platform device / driver to
104 * store memory offset.
105 * To handle this we provide following symbol. It's supposed to be called as
106 * soon as we get info about flash device, before any NVRAM entry is needed.
107 */
108int bcm47xx_nvram_init_from_mem(u32 base, u32 lim)
102{ 109{
103 void __iomem *iobase; 110 void __iomem *iobase;
104 int err; 111 int err;
@@ -114,25 +121,6 @@ static int bcm47xx_nvram_init_from_mem(u32 base, u32 lim)
114 return err; 121 return err;
115} 122}
116 123
117#ifdef CONFIG_BCM47XX_SSB
118static int nvram_init_ssb(void)
119{
120 struct ssb_mipscore *mcore = &bcm47xx_bus.ssb.mipscore;
121 u32 base;
122 u32 lim;
123
124 if (mcore->pflash.present) {
125 base = mcore->pflash.window;
126 lim = mcore->pflash.window_size;
127 } else {
128 pr_err("Couldn't find supported flash memory\n");
129 return -ENXIO;
130 }
131
132 return bcm47xx_nvram_init_from_mem(base, lim);
133}
134#endif
135
136#ifdef CONFIG_BCM47XX_BCMA 124#ifdef CONFIG_BCM47XX_BCMA
137static int nvram_init_bcma(void) 125static int nvram_init_bcma(void)
138{ 126{
@@ -168,7 +156,7 @@ static int nvram_init(void)
168 switch (bcm47xx_bus_type) { 156 switch (bcm47xx_bus_type) {
169#ifdef CONFIG_BCM47XX_SSB 157#ifdef CONFIG_BCM47XX_SSB
170 case BCM47XX_BUS_TYPE_SSB: 158 case BCM47XX_BUS_TYPE_SSB:
171 return nvram_init_ssb(); 159 break;
172#endif 160#endif
173#ifdef CONFIG_BCM47XX_BCMA 161#ifdef CONFIG_BCM47XX_BCMA
174 case BCM47XX_BUS_TYPE_BCMA: 162 case BCM47XX_BUS_TYPE_BCMA:
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
index 36a3fc1aa3ae..676be22bcab3 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
@@ -32,6 +32,7 @@ struct nvram_header {
32#define NVRAM_MAX_VALUE_LEN 255 32#define NVRAM_MAX_VALUE_LEN 255
33#define NVRAM_MAX_PARAM_LEN 64 33#define NVRAM_MAX_PARAM_LEN 64
34 34
35int bcm47xx_nvram_init_from_mem(u32 base, u32 lim);
35extern int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len); 36extern int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len);
36 37
37static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6]) 38static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6])
diff --git a/drivers/ssb/driver_mipscore.c b/drivers/ssb/driver_mipscore.c
index 09077067b0c8..7b986f9f213f 100644
--- a/drivers/ssb/driver_mipscore.c
+++ b/drivers/ssb/driver_mipscore.c
@@ -15,6 +15,9 @@
15#include <linux/serial_core.h> 15#include <linux/serial_core.h>
16#include <linux/serial_reg.h> 16#include <linux/serial_reg.h>
17#include <linux/time.h> 17#include <linux/time.h>
18#ifdef CONFIG_BCM47XX
19#include <bcm47xx_nvram.h>
20#endif
18 21
19#include "ssb_private.h" 22#include "ssb_private.h"
20 23
@@ -210,6 +213,7 @@ static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
210static void ssb_mips_flash_detect(struct ssb_mipscore *mcore) 213static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
211{ 214{
212 struct ssb_bus *bus = mcore->dev->bus; 215 struct ssb_bus *bus = mcore->dev->bus;
216 struct ssb_sflash *sflash = &mcore->sflash;
213 struct ssb_pflash *pflash = &mcore->pflash; 217 struct ssb_pflash *pflash = &mcore->pflash;
214 218
215 /* When there is no chipcommon on the bus there is 4MB flash */ 219 /* When there is no chipcommon on the bus there is 4MB flash */
@@ -242,7 +246,15 @@ static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
242 } 246 }
243 247
244ssb_pflash: 248ssb_pflash:
245 if (pflash->present) { 249 if (sflash->present) {
250#ifdef CONFIG_BCM47XX
251 bcm47xx_nvram_init_from_mem(sflash->window, sflash->size);
252#endif
253 } else if (pflash->present) {
254#ifdef CONFIG_BCM47XX
255 bcm47xx_nvram_init_from_mem(pflash->window, pflash->window_size);
256#endif
257
246 ssb_pflash_data.width = pflash->buswidth; 258 ssb_pflash_data.width = pflash->buswidth;
247 ssb_pflash_resource.start = pflash->window; 259 ssb_pflash_resource.start = pflash->window;
248 ssb_pflash_resource.end = pflash->window + pflash->window_size; 260 ssb_pflash_resource.end = pflash->window + pflash->window_size;