aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2013-06-01 06:55:26 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-06-01 06:55:26 -0400
commit0f7dafd44e2de131f67fca87378e30ca86bc00d5 (patch)
treeaf28ce75d6e09bb09c89aa1dc01bff341d5f7bfa
parentc361cb59acbb503c033971e8be8c029bbfd67f18 (diff)
parentd68c380590c390a488fe214e5ebf9439216ac3ba (diff)
Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux
Pull clock subsystem fixes from Mike Turquette: "A mix of small fixes affecting mostly ARM platforms as well as a discrete clock expander chip. Most fixes are corrections to lousy clock data of one form or another." * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux: clk: mxs: Include clk mxs header file clk: vt8500: Fix unbalanced spinlock in vt8500_dclk_set_rate() clk: si5351: Set initial clkout rate when defined in platform data. clk: si5351: Fix clkout rate computation. clk: samsung: Add CLK_IGNORE_UNUSED flag for the sysreg clocks clk: ux500: clk-sysctrl: handle clocks with no parents clk: ux500: Provide device enumeration number suffix for SMSC911x
-rw-r--r--drivers/clk/clk-si5351.c12
-rw-r--r--drivers/clk/clk-vt8500.c2
-rw-r--r--drivers/clk/mxs/clk-imx28.c1
-rw-r--r--drivers/clk/samsung/clk-exynos4.c6
-rw-r--r--drivers/clk/ux500/clk-sysctrl.c8
-rw-r--r--drivers/clk/ux500/u8500_clk.c2
6 files changed, 25 insertions, 6 deletions
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 892728412e9d..24f553673b72 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -932,7 +932,7 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
932 unsigned char reg; 932 unsigned char reg;
933 unsigned char rdiv; 933 unsigned char rdiv;
934 934
935 if (hwdata->num > 5) 935 if (hwdata->num <= 5)
936 reg = si5351_msynth_params_address(hwdata->num) + 2; 936 reg = si5351_msynth_params_address(hwdata->num) + 2;
937 else 937 else
938 reg = SI5351_CLK6_7_OUTPUT_DIVIDER; 938 reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
@@ -1477,6 +1477,16 @@ static int si5351_i2c_probe(struct i2c_client *client,
1477 return -EINVAL; 1477 return -EINVAL;
1478 } 1478 }
1479 drvdata->onecell.clks[n] = clk; 1479 drvdata->onecell.clks[n] = clk;
1480
1481 /* set initial clkout rate */
1482 if (pdata->clkout[n].rate != 0) {
1483 int ret;
1484 ret = clk_set_rate(clk, pdata->clkout[n].rate);
1485 if (ret != 0) {
1486 dev_err(&client->dev, "Cannot set rate : %d\n",
1487 ret);
1488 }
1489 }
1480 } 1490 }
1481 1491
1482 ret = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get, 1492 ret = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get,
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index debf688afa8e..553ac35bcc91 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -183,7 +183,7 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
183 writel(divisor, cdev->div_reg); 183 writel(divisor, cdev->div_reg);
184 vt8500_pmc_wait_busy(); 184 vt8500_pmc_wait_busy();
185 185
186 spin_lock_irqsave(cdev->lock, flags); 186 spin_unlock_irqrestore(cdev->lock, flags);
187 187
188 return 0; 188 return 0;
189} 189}
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index d0e5eed146de..4faf0afc44cd 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#include <linux/clk.h> 12#include <linux/clk.h>
13#include <linux/clk/mxs.h>
13#include <linux/clkdev.h> 14#include <linux/clkdev.h>
14#include <linux/err.h> 15#include <linux/err.h>
15#include <linux/init.h> 16#include <linux/init.h>
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index d0940e69d034..3c1f88868f29 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -791,7 +791,8 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
791 GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), 791 GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
792 GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), 792 GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
793 GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), 793 GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
794 GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), 794 GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
795 CLK_IGNORE_UNUSED, 0),
795 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0), 796 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0),
796 GATE(smmu_rotator, "smmu_rotator", "aclk200", 797 GATE(smmu_rotator, "smmu_rotator", "aclk200",
797 E4210_GATE_IP_IMAGE, 4, 0, 0), 798 E4210_GATE_IP_IMAGE, 4, 0, 0),
@@ -819,7 +820,8 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
819 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0), 820 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),
820 GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), 821 GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
821 GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), 822 GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
822 GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0), 823 GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
824 CLK_IGNORE_UNUSED, 0),
823 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0), 825 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),
824 GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0", 826 GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",
825 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), 827 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c
index bc7e9bde792b..e364c9d4aa60 100644
--- a/drivers/clk/ux500/clk-sysctrl.c
+++ b/drivers/clk/ux500/clk-sysctrl.c
@@ -145,7 +145,13 @@ static struct clk *clk_reg_sysctrl(struct device *dev,
145 return ERR_PTR(-ENOMEM); 145 return ERR_PTR(-ENOMEM);
146 } 146 }
147 147
148 for (i = 0; i < num_parents; i++) { 148 /* set main clock registers */
149 clk->reg_sel[0] = reg_sel[0];
150 clk->reg_bits[0] = reg_bits[0];
151 clk->reg_mask[0] = reg_mask[0];
152
153 /* handle clocks with more than one parent */
154 for (i = 1; i < num_parents; i++) {
149 clk->reg_sel[i] = reg_sel[i]; 155 clk->reg_sel[i] = reg_sel[i];
150 clk->reg_bits[i] = reg_bits[i]; 156 clk->reg_bits[i] = reg_bits[i];
151 clk->reg_mask[i] = reg_mask[i]; 157 clk->reg_mask[i] = reg_mask[i];
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index 0b4f35a5ffc2..80069c370a47 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -325,7 +325,7 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
325 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base, 325 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
326 BIT(0), 0); 326 BIT(0), 0);
327 clk_register_clkdev(clk, "fsmc", NULL); 327 clk_register_clkdev(clk, "fsmc", NULL);
328 clk_register_clkdev(clk, NULL, "smsc911x"); 328 clk_register_clkdev(clk, NULL, "smsc911x.0");
329 329
330 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base, 330 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
331 BIT(1), 0); 331 BIT(1), 0);