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authorAdam Jackson <ajax@redhat.com>2009-12-03 17:14:42 -0500
committerEric Anholt <eric@anholt.net>2009-12-07 17:55:56 -0500
commitf2b115e69d46344ae7afcaad5823496d2a0d8650 (patch)
tree8bf56f7d43e3462a26088317bad04f04b676d26c
parent107f517b8f2a9d5858e640bc046606b1cff14bb5 (diff)
drm/i915: Fix product names and #defines
IGD* isn't a useful name. Replace with the codenames, as sourced from pci.ids. Signed-off-by: Adam Jackson <ajax@redhat.com> [anholt: Fixed up for merge with pineview/ironlake changes] Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c2
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c8
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h44
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c2
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c4
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c50
-rw-r--r--drivers/gpu/drm/i915/i915_opregion.c2
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h40
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c60
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c2
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c18
-rw-r--r--drivers/gpu/drm/i915/intel_display.c408
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c20
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c4
-rw-r--r--drivers/gpu/drm/i915/intel_i2c.c4
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c26
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c2
17 files changed, 347 insertions, 349 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d7aada51a3be..eeed4e34c757 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -161,7 +161,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
161 struct drm_device *dev = node->minor->dev; 161 struct drm_device *dev = node->minor->dev;
162 drm_i915_private_t *dev_priv = dev->dev_private; 162 drm_i915_private_t *dev_priv = dev->dev_private;
163 163
164 if (!IS_IGDNG(dev)) { 164 if (!IS_IRONLAKE(dev)) {
165 seq_printf(m, "Interrupt enable: %08x\n", 165 seq_printf(m, "Interrupt enable: %08x\n",
166 I915_READ(IER)); 166 I915_READ(IER));
167 seq_printf(m, "Interrupt identity: %08x\n", 167 seq_printf(m, "Interrupt identity: %08x\n",
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index fe89d0c723e6..701bfeac7f57 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -968,7 +968,7 @@ static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
968 * Some of the preallocated space is taken by the GTT 968 * Some of the preallocated space is taken by the GTT
969 * and popup. GTT is 1K per MB of aperture size, and popup is 4K. 969 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
970 */ 970 */
971 if (IS_G4X(dev) || IS_IGD(dev) || IS_IGDNG(dev)) 971 if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev))
972 overhead = 4096; 972 overhead = 4096;
973 else 973 else
974 overhead = (*aperture_size / 1024) + 4096; 974 overhead = (*aperture_size / 1024) + 4096;
@@ -1054,7 +1054,7 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1054 int gtt_offset, gtt_size; 1054 int gtt_offset, gtt_size;
1055 1055
1056 if (IS_I965G(dev)) { 1056 if (IS_I965G(dev)) {
1057 if (IS_G4X(dev) || IS_IGDNG(dev)) { 1057 if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
1058 gtt_offset = 2*1024*1024; 1058 gtt_offset = 2*1024*1024;
1059 gtt_size = 2*1024*1024; 1059 gtt_size = 2*1024*1024;
1060 } else { 1060 } else {
@@ -1312,7 +1312,7 @@ static void i915_get_mem_freq(struct drm_device *dev)
1312 drm_i915_private_t *dev_priv = dev->dev_private; 1312 drm_i915_private_t *dev_priv = dev->dev_private;
1313 u32 tmp; 1313 u32 tmp;
1314 1314
1315 if (!IS_IGD(dev)) 1315 if (!IS_PINEVIEW(dev))
1316 return; 1316 return;
1317 1317
1318 tmp = I915_READ(CLKCFG); 1318 tmp = I915_READ(CLKCFG);
@@ -1440,7 +1440,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1440 1440
1441 dev->driver->get_vblank_counter = i915_get_vblank_counter; 1441 dev->driver->get_vblank_counter = i915_get_vblank_counter;
1442 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 1442 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1443 if (IS_G4X(dev) || IS_IGDNG(dev)) { 1443 if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
1444 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 1444 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1445 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 1445 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1446 } 1446 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ca1ba42af566..e28d6c9a0ae9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -209,7 +209,7 @@ typedef struct drm_i915_private {
209 /** Cached value of IMR to avoid reads in updating the bitfield */ 209 /** Cached value of IMR to avoid reads in updating the bitfield */
210 u32 irq_mask_reg; 210 u32 irq_mask_reg;
211 u32 pipestat[2]; 211 u32 pipestat[2];
212 /** splitted irq regs for graphics and display engine on IGDNG, 212 /** splitted irq regs for graphics and display engine on Ironlake,
213 irq_mask_reg is still used for display irq. */ 213 irq_mask_reg is still used for display irq. */
214 u32 gt_irq_mask_reg; 214 u32 gt_irq_mask_reg;
215 u32 gt_irq_enable_reg; 215 u32 gt_irq_enable_reg;
@@ -1010,51 +1010,51 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1010 (dev)->pci_device == 0x2E42 || \ 1010 (dev)->pci_device == 0x2E42 || \
1011 IS_GM45(dev)) 1011 IS_GM45(dev))
1012 1012
1013#define IS_IGDG(dev) ((dev)->pci_device == 0xa001) 1013#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1014#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011) 1014#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1015#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) 1015#define IS_PINEVIEW(dev) (IS_PINEVIEW_G(dev) || IS_PINEVIEW_M(dev))
1016 1016
1017#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ 1017#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
1018 (dev)->pci_device == 0x29B2 || \ 1018 (dev)->pci_device == 0x29B2 || \
1019 (dev)->pci_device == 0x29D2 || \ 1019 (dev)->pci_device == 0x29D2 || \
1020 (IS_IGD(dev))) 1020 (IS_PINEVIEW(dev)))
1021 1021
1022#define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042) 1022#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1023#define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046) 1023#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1024#define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev)) 1024#define IS_IRONLAKE(dev) (IS_IRONLAKE_D(dev) || IS_IRONLAKE_M(dev))
1025 1025
1026#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 1026#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
1027 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \ 1027 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
1028 IS_IGDNG(dev)) 1028 IS_IRONLAKE(dev))
1029 1029
1030#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 1030#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1031 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \ 1031 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
1032 IS_IGD(dev) || IS_IGDNG_M(dev)) 1032 IS_PINEVIEW(dev) || IS_IRONLAKE_M(dev))
1033 1033
1034#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \ 1034#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
1035 IS_IGDNG(dev)) 1035 IS_IRONLAKE(dev))
1036/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1036/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1037 * rows, which changed the alignment requirements and fence programming. 1037 * rows, which changed the alignment requirements and fence programming.
1038 */ 1038 */
1039#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ 1039#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1040 IS_I915GM(dev))) 1040 IS_I915GM(dev)))
1041#define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_IGD(dev)) 1041#define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1042#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev)) 1042#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1043#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev)) 1043#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1044#define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev)) 1044#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1045#define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \ 1045#define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1046 !IS_IGDNG(dev) && !IS_IGD(dev)) 1046 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev))
1047#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev)) 1047#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
1048/* dsparb controlled by hw only */ 1048/* dsparb controlled by hw only */
1049#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev)) 1049#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1050 1050
1051#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev)) 1051#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1052#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev)) 1052#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1053#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \ 1053#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \
1054 (IS_I9XX(dev) || IS_GM45(dev)) && \ 1054 (IS_I9XX(dev) || IS_GM45(dev)) && \
1055 !IS_IGD(dev) && \ 1055 !IS_PINEVIEW(dev) && \
1056 !IS_IGDNG(dev)) 1056 !IS_IRONLAKE(dev))
1057#define I915_HAS_RC6(dev) (IS_I965GM(dev) || IS_GM45(dev) || IS_IGDNG_M(dev)) 1057#define I915_HAS_RC6(dev) (IS_I965GM(dev) || IS_GM45(dev) || IS_IRONLAKE_M(dev))
1058 1058
1059#define PRIMARY_RINGBUFFER_SIZE (128*1024) 1059#define PRIMARY_RINGBUFFER_SIZE (128*1024)
1060 1060
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fd5363995044..5b46623d62d4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1833,7 +1833,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
1833 return -EIO; 1833 return -EIO;
1834 1834
1835 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) { 1835 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1836 if (IS_IGDNG(dev)) 1836 if (IS_IRONLAKE(dev))
1837 ier = I915_READ(DEIER) | I915_READ(GTIER); 1837 ier = I915_READ(DEIER) | I915_READ(GTIER);
1838 else 1838 else
1839 ier = I915_READ(IER); 1839 ier = I915_READ(IER);
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 0c8df96a1ef8..30d6af6c09bb 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -209,8 +209,8 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
209 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 209 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
210 bool need_disable; 210 bool need_disable;
211 211
212 if (IS_IGDNG(dev)) { 212 if (IS_IRONLAKE(dev)) {
213 /* On IGDNG whatever DRAM config, GPU always do 213 /* On Ironlake whatever DRAM config, GPU always do
214 * same swizzling setup. 214 * same swizzling setup.
215 */ 215 */
216 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 216 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e2d01b3fa171..a31c9d5e29f3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -64,7 +64,7 @@
64 DRM_I915_VBLANK_PIPE_B) 64 DRM_I915_VBLANK_PIPE_B)
65 65
66void 66void
67igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) 67ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
68{ 68{
69 if ((dev_priv->gt_irq_mask_reg & mask) != 0) { 69 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
70 dev_priv->gt_irq_mask_reg &= ~mask; 70 dev_priv->gt_irq_mask_reg &= ~mask;
@@ -74,7 +74,7 @@ igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
74} 74}
75 75
76static inline void 76static inline void
77igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) 77ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
78{ 78{
79 if ((dev_priv->gt_irq_mask_reg & mask) != mask) { 79 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
80 dev_priv->gt_irq_mask_reg |= mask; 80 dev_priv->gt_irq_mask_reg |= mask;
@@ -85,7 +85,7 @@ igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
85 85
86/* For display hotplug interrupt */ 86/* For display hotplug interrupt */
87void 87void
88igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 88ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
89{ 89{
90 if ((dev_priv->irq_mask_reg & mask) != 0) { 90 if ((dev_priv->irq_mask_reg & mask) != 0) {
91 dev_priv->irq_mask_reg &= ~mask; 91 dev_priv->irq_mask_reg &= ~mask;
@@ -95,7 +95,7 @@ igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
95} 95}
96 96
97static inline void 97static inline void
98igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 98ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
99{ 99{
100 if ((dev_priv->irq_mask_reg & mask) != mask) { 100 if ((dev_priv->irq_mask_reg & mask) != mask) {
101 dev_priv->irq_mask_reg |= mask; 101 dev_priv->irq_mask_reg |= mask;
@@ -166,8 +166,8 @@ void intel_enable_asle (struct drm_device *dev)
166{ 166{
167 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 167 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
168 168
169 if (IS_IGDNG(dev)) 169 if (IS_IRONLAKE(dev))
170 igdng_enable_display_irq(dev_priv, DE_GSE); 170 ironlake_enable_display_irq(dev_priv, DE_GSE);
171 else 171 else
172 i915_enable_pipestat(dev_priv, 1, 172 i915_enable_pipestat(dev_priv, 1,
173 I915_LEGACY_BLC_EVENT_ENABLE); 173 I915_LEGACY_BLC_EVENT_ENABLE);
@@ -269,7 +269,7 @@ static void i915_hotplug_work_func(struct work_struct *work)
269 drm_sysfs_hotplug_event(dev); 269 drm_sysfs_hotplug_event(dev);
270} 270}
271 271
272irqreturn_t igdng_irq_handler(struct drm_device *dev) 272irqreturn_t ironlake_irq_handler(struct drm_device *dev)
273{ 273{
274 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 274 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
275 int ret = IRQ_NONE; 275 int ret = IRQ_NONE;
@@ -561,8 +561,8 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
561 561
562 atomic_inc(&dev_priv->irq_received); 562 atomic_inc(&dev_priv->irq_received);
563 563
564 if (IS_IGDNG(dev)) 564 if (IS_IRONLAKE(dev))
565 return igdng_irq_handler(dev); 565 return ironlake_irq_handler(dev);
566 566
567 iir = I915_READ(IIR); 567 iir = I915_READ(IIR);
568 568
@@ -722,8 +722,8 @@ void i915_user_irq_get(struct drm_device *dev)
722 722
723 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 723 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
724 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { 724 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
725 if (IS_IGDNG(dev)) 725 if (IS_IRONLAKE(dev))
726 igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); 726 ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
727 else 727 else
728 i915_enable_irq(dev_priv, I915_USER_INTERRUPT); 728 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
729 } 729 }
@@ -738,8 +738,8 @@ void i915_user_irq_put(struct drm_device *dev)
738 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 738 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
739 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); 739 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
740 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { 740 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
741 if (IS_IGDNG(dev)) 741 if (IS_IRONLAKE(dev))
742 igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); 742 ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
743 else 743 else
744 i915_disable_irq(dev_priv, I915_USER_INTERRUPT); 744 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
745 } 745 }
@@ -845,7 +845,7 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
845 if (!(pipeconf & PIPEACONF_ENABLE)) 845 if (!(pipeconf & PIPEACONF_ENABLE))
846 return -EINVAL; 846 return -EINVAL;
847 847
848 if (IS_IGDNG(dev)) 848 if (IS_IRONLAKE(dev))
849 return 0; 849 return 0;
850 850
851 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 851 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
@@ -867,7 +867,7 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
867 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 867 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
868 unsigned long irqflags; 868 unsigned long irqflags;
869 869
870 if (IS_IGDNG(dev)) 870 if (IS_IRONLAKE(dev))
871 return; 871 return;
872 872
873 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 873 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
@@ -881,7 +881,7 @@ void i915_enable_interrupt (struct drm_device *dev)
881{ 881{
882 struct drm_i915_private *dev_priv = dev->dev_private; 882 struct drm_i915_private *dev_priv = dev->dev_private;
883 883
884 if (!IS_IGDNG(dev)) 884 if (!IS_IRONLAKE(dev))
885 opregion_enable_asle(dev); 885 opregion_enable_asle(dev);
886 dev_priv->irq_enabled = 1; 886 dev_priv->irq_enabled = 1;
887} 887}
@@ -989,7 +989,7 @@ void i915_hangcheck_elapsed(unsigned long data)
989 989
990/* drm_dma.h hooks 990/* drm_dma.h hooks
991*/ 991*/
992static void igdng_irq_preinstall(struct drm_device *dev) 992static void ironlake_irq_preinstall(struct drm_device *dev)
993{ 993{
994 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 994 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
995 995
@@ -1012,7 +1012,7 @@ static void igdng_irq_preinstall(struct drm_device *dev)
1012 (void) I915_READ(SDEIER); 1012 (void) I915_READ(SDEIER);
1013} 1013}
1014 1014
1015static int igdng_irq_postinstall(struct drm_device *dev) 1015static int ironlake_irq_postinstall(struct drm_device *dev)
1016{ 1016{
1017 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1017 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1018 /* enable kind of interrupts always enabled */ 1018 /* enable kind of interrupts always enabled */
@@ -1059,8 +1059,8 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
1059 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 1059 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1060 INIT_WORK(&dev_priv->error_work, i915_error_work_func); 1060 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1061 1061
1062 if (IS_IGDNG(dev)) { 1062 if (IS_IRONLAKE(dev)) {
1063 igdng_irq_preinstall(dev); 1063 ironlake_irq_preinstall(dev);
1064 return; 1064 return;
1065 } 1065 }
1066 1066
@@ -1087,8 +1087,8 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
1087 1087
1088 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1088 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1089 1089
1090 if (IS_IGDNG(dev)) 1090 if (IS_IRONLAKE(dev))
1091 return igdng_irq_postinstall(dev); 1091 return ironlake_irq_postinstall(dev);
1092 1092
1093 /* Unmask the interrupts that we always want on. */ 1093 /* Unmask the interrupts that we always want on. */
1094 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; 1094 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
@@ -1148,7 +1148,7 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
1148 return 0; 1148 return 0;
1149} 1149}
1150 1150
1151static void igdng_irq_uninstall(struct drm_device *dev) 1151static void ironlake_irq_uninstall(struct drm_device *dev)
1152{ 1152{
1153 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1153 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1154 I915_WRITE(HWSTAM, 0xffffffff); 1154 I915_WRITE(HWSTAM, 0xffffffff);
@@ -1171,8 +1171,8 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
1171 1171
1172 dev_priv->vblank_pipe = 0; 1172 dev_priv->vblank_pipe = 0;
1173 1173
1174 if (IS_IGDNG(dev)) { 1174 if (IS_IRONLAKE(dev)) {
1175 igdng_irq_uninstall(dev); 1175 ironlake_irq_uninstall(dev);
1176 return; 1176 return;
1177 } 1177 }
1178 1178
diff --git a/drivers/gpu/drm/i915/i915_opregion.c b/drivers/gpu/drm/i915/i915_opregion.c
index 313a1a11afab..7cc8410239cb 100644
--- a/drivers/gpu/drm/i915/i915_opregion.c
+++ b/drivers/gpu/drm/i915/i915_opregion.c
@@ -167,7 +167,7 @@ static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
167 if (IS_I965G(dev) && (blc_pwm_ctl2 & BLM_COMBINATION_MODE)) 167 if (IS_I965G(dev) && (blc_pwm_ctl2 & BLM_COMBINATION_MODE))
168 pci_write_config_dword(dev->pdev, PCI_LBPC, bclp); 168 pci_write_config_dword(dev->pdev, PCI_LBPC, bclp);
169 else { 169 else {
170 if (IS_IGD(dev)) { 170 if (IS_PINEVIEW(dev)) {
171 blc_pwm_ctl &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1); 171 blc_pwm_ctl &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
172 max_backlight = (blc_pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK) >> 172 max_backlight = (blc_pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK) >>
173 BACKLIGHT_MODULATION_FREQ_SHIFT; 173 BACKLIGHT_MODULATION_FREQ_SHIFT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c4a273513b2f..974b3cf70618 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -451,7 +451,7 @@
451#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 451#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
452#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 452#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
453#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 453#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
454#define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */ 454#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
455 455
456#define I915_FIFO_UNDERRUN_STATUS (1UL<<31) 456#define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
457#define I915_CRC_ERROR_ENABLE (1UL<<29) 457#define I915_CRC_ERROR_ENABLE (1UL<<29)
@@ -528,7 +528,7 @@
528 */ 528 */
529#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 529#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
530#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 530#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
531#define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15 531#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
532/* i830, required in DVO non-gang */ 532/* i830, required in DVO non-gang */
533#define PLL_P2_DIVIDE_BY_4 (1 << 23) 533#define PLL_P2_DIVIDE_BY_4 (1 << 23)
534#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 534#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
@@ -538,7 +538,7 @@
538#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 538#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
539#define PLL_REF_INPUT_MASK (3 << 13) 539#define PLL_REF_INPUT_MASK (3 << 13)
540#define PLL_LOAD_PULSE_PHASE_SHIFT 9 540#define PLL_LOAD_PULSE_PHASE_SHIFT 9
541/* IGDNG */ 541/* Ironlake */
542# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 542# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
543# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 543# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
544# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 544# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
@@ -602,12 +602,12 @@
602#define FPB0 0x06048 602#define FPB0 0x06048
603#define FPB1 0x0604c 603#define FPB1 0x0604c
604#define FP_N_DIV_MASK 0x003f0000 604#define FP_N_DIV_MASK 0x003f0000
605#define FP_N_IGD_DIV_MASK 0x00ff0000 605#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
606#define FP_N_DIV_SHIFT 16 606#define FP_N_DIV_SHIFT 16
607#define FP_M1_DIV_MASK 0x00003f00 607#define FP_M1_DIV_MASK 0x00003f00
608#define FP_M1_DIV_SHIFT 8 608#define FP_M1_DIV_SHIFT 8
609#define FP_M2_DIV_MASK 0x0000003f 609#define FP_M2_DIV_MASK 0x0000003f
610#define FP_M2_IGD_DIV_MASK 0x000000ff 610#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
611#define FP_M2_DIV_SHIFT 0 611#define FP_M2_DIV_SHIFT 0
612#define DPLL_TEST 0x606c 612#define DPLL_TEST 0x606c
613#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 613#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
@@ -1634,7 +1634,7 @@
1634#define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 1634#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
1635 1635
1636#define DP_SCRAMBLING_DISABLE (1 << 12) 1636#define DP_SCRAMBLING_DISABLE (1 << 12)
1637#define DP_SCRAMBLING_DISABLE_IGDNG (1 << 7) 1637#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
1638 1638
1639/** limit RGB values to avoid confusing TVs */ 1639/** limit RGB values to avoid confusing TVs */
1640#define DP_COLOR_RANGE_16_235 (1 << 8) 1640#define DP_COLOR_RANGE_16_235 (1 << 8)
@@ -1822,7 +1822,7 @@
1822#define DSPFW3 0x7003c 1822#define DSPFW3 0x7003c
1823#define DSPFW_HPLL_SR_EN (1<<31) 1823#define DSPFW_HPLL_SR_EN (1<<31)
1824#define DSPFW_CURSOR_SR_SHIFT 24 1824#define DSPFW_CURSOR_SR_SHIFT 24
1825#define IGD_SELF_REFRESH_EN (1<<30) 1825#define PINEVIEW_SELF_REFRESH_EN (1<<30)
1826 1826
1827/* FIFO watermark sizes etc */ 1827/* FIFO watermark sizes etc */
1828#define G4X_FIFO_LINE_SIZE 64 1828#define G4X_FIFO_LINE_SIZE 64
@@ -1838,16 +1838,16 @@
1838#define G4X_MAX_WM 0x3f 1838#define G4X_MAX_WM 0x3f
1839#define I915_MAX_WM 0x3f 1839#define I915_MAX_WM 0x3f
1840 1840
1841#define IGD_DISPLAY_FIFO 512 /* in 64byte unit */ 1841#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
1842#define IGD_FIFO_LINE_SIZE 64 1842#define PINEVIEW_FIFO_LINE_SIZE 64
1843#define IGD_MAX_WM 0x1ff 1843#define PINEVIEW_MAX_WM 0x1ff
1844#define IGD_DFT_WM 0x3f 1844#define PINEVIEW_DFT_WM 0x3f
1845#define IGD_DFT_HPLLOFF_WM 0 1845#define PINEVIEW_DFT_HPLLOFF_WM 0
1846#define IGD_GUARD_WM 10 1846#define PINEVIEW_GUARD_WM 10
1847#define IGD_CURSOR_FIFO 64 1847#define PINEVIEW_CURSOR_FIFO 64
1848#define IGD_CURSOR_MAX_WM 0x3f 1848#define PINEVIEW_CURSOR_MAX_WM 0x3f
1849#define IGD_CURSOR_DFT_WM 0 1849#define PINEVIEW_CURSOR_DFT_WM 0
1850#define IGD_CURSOR_GUARD_WM 5 1850#define PINEVIEW_CURSOR_GUARD_WM 5
1851 1851
1852/* 1852/*
1853 * The two pipe frame counter registers are not synchronized, so 1853 * The two pipe frame counter registers are not synchronized, so
@@ -1933,7 +1933,7 @@
1933#define DISPPLANE_NO_LINE_DOUBLE 0 1933#define DISPPLANE_NO_LINE_DOUBLE 0
1934#define DISPPLANE_STEREO_POLARITY_FIRST 0 1934#define DISPPLANE_STEREO_POLARITY_FIRST 0
1935#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 1935#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1936#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* IGDNG */ 1936#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
1937#define DISPPLANE_TILED (1<<10) 1937#define DISPPLANE_TILED (1<<10)
1938#define DSPAADDR 0x70184 1938#define DSPAADDR 0x70184
1939#define DSPASTRIDE 0x70188 1939#define DSPASTRIDE 0x70188
@@ -1986,7 +1986,7 @@
1986# define VGA_2X_MODE (1 << 30) 1986# define VGA_2X_MODE (1 << 30)
1987# define VGA_PIPE_B_SELECT (1 << 29) 1987# define VGA_PIPE_B_SELECT (1 << 29)
1988 1988
1989/* IGDNG */ 1989/* Ironlake */
1990 1990
1991#define CPU_VGACNTRL 0x41000 1991#define CPU_VGACNTRL 0x41000
1992 1992
@@ -2315,7 +2315,7 @@
2315#define FDI_DP_PORT_WIDTH_X3 (2<<19) 2315#define FDI_DP_PORT_WIDTH_X3 (2<<19)
2316#define FDI_DP_PORT_WIDTH_X4 (3<<19) 2316#define FDI_DP_PORT_WIDTH_X4 (3<<19)
2317#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 2317#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
2318/* IGDNG: hardwired to 1 */ 2318/* Ironlake: hardwired to 1 */
2319#define FDI_TX_PLL_ENABLE (1<<14) 2319#define FDI_TX_PLL_ENABLE (1<<14)
2320/* both Tx and Rx */ 2320/* both Tx and Rx */
2321#define FDI_SCRAMBLING_ENABLE (0<<7) 2321#define FDI_SCRAMBLING_ENABLE (0<<7)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index c5a6df93e1b6..402a7eb2922c 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -34,7 +34,7 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
34 struct drm_i915_private *dev_priv = dev->dev_private; 34 struct drm_i915_private *dev_priv = dev->dev_private;
35 u32 dpll_reg; 35 u32 dpll_reg;
36 36
37 if (IS_IGDNG(dev)) { 37 if (IS_IRONLAKE(dev)) {
38 dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B; 38 dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B;
39 } else { 39 } else {
40 dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B; 40 dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B;
@@ -53,7 +53,7 @@ static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
53 if (!i915_pipe_enabled(dev, pipe)) 53 if (!i915_pipe_enabled(dev, pipe))
54 return; 54 return;
55 55
56 if (IS_IGDNG(dev)) 56 if (IS_IRONLAKE(dev))
57 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 57 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
58 58
59 if (pipe == PIPE_A) 59 if (pipe == PIPE_A)
@@ -75,7 +75,7 @@ static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
75 if (!i915_pipe_enabled(dev, pipe)) 75 if (!i915_pipe_enabled(dev, pipe))
76 return; 76 return;
77 77
78 if (IS_IGDNG(dev)) 78 if (IS_IRONLAKE(dev))
79 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 79 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
80 80
81 if (pipe == PIPE_A) 81 if (pipe == PIPE_A)
@@ -242,7 +242,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
242 /* Pipe & plane A info */ 242 /* Pipe & plane A info */
243 dev_priv->savePIPEACONF = I915_READ(PIPEACONF); 243 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
244 dev_priv->savePIPEASRC = I915_READ(PIPEASRC); 244 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
245 if (IS_IGDNG(dev)) { 245 if (IS_IRONLAKE(dev)) {
246 dev_priv->saveFPA0 = I915_READ(PCH_FPA0); 246 dev_priv->saveFPA0 = I915_READ(PCH_FPA0);
247 dev_priv->saveFPA1 = I915_READ(PCH_FPA1); 247 dev_priv->saveFPA1 = I915_READ(PCH_FPA1);
248 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A); 248 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A);
@@ -251,7 +251,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
251 dev_priv->saveFPA1 = I915_READ(FPA1); 251 dev_priv->saveFPA1 = I915_READ(FPA1);
252 dev_priv->saveDPLL_A = I915_READ(DPLL_A); 252 dev_priv->saveDPLL_A = I915_READ(DPLL_A);
253 } 253 }
254 if (IS_I965G(dev) && !IS_IGDNG(dev)) 254 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
255 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); 255 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
256 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); 256 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
257 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); 257 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
@@ -259,10 +259,10 @@ static void i915_save_modeset_reg(struct drm_device *dev)
259 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); 259 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
260 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); 260 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
261 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); 261 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
262 if (!IS_IGDNG(dev)) 262 if (!IS_IRONLAKE(dev))
263 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 263 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
264 264
265 if (IS_IGDNG(dev)) { 265 if (IS_IRONLAKE(dev)) {
266 dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL); 266 dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL);
267 dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL); 267 dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL);
268 268
@@ -293,7 +293,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
293 /* Pipe & plane B info */ 293 /* Pipe & plane B info */
294 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); 294 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
295 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); 295 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
296 if (IS_IGDNG(dev)) { 296 if (IS_IRONLAKE(dev)) {
297 dev_priv->saveFPB0 = I915_READ(PCH_FPB0); 297 dev_priv->saveFPB0 = I915_READ(PCH_FPB0);
298 dev_priv->saveFPB1 = I915_READ(PCH_FPB1); 298 dev_priv->saveFPB1 = I915_READ(PCH_FPB1);
299 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B); 299 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B);
@@ -302,7 +302,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
302 dev_priv->saveFPB1 = I915_READ(FPB1); 302 dev_priv->saveFPB1 = I915_READ(FPB1);
303 dev_priv->saveDPLL_B = I915_READ(DPLL_B); 303 dev_priv->saveDPLL_B = I915_READ(DPLL_B);
304 } 304 }
305 if (IS_I965G(dev) && !IS_IGDNG(dev)) 305 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
306 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); 306 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
307 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); 307 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
308 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); 308 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
@@ -310,10 +310,10 @@ static void i915_save_modeset_reg(struct drm_device *dev)
310 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); 310 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
311 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); 311 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
312 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); 312 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
313 if (!IS_IGDNG(dev)) 313 if (!IS_IRONLAKE(dev))
314 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B); 314 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B);
315 315
316 if (IS_IGDNG(dev)) { 316 if (IS_IRONLAKE(dev)) {
317 dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL); 317 dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL);
318 dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL); 318 dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL);
319 319
@@ -352,7 +352,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
352 if (drm_core_check_feature(dev, DRIVER_MODESET)) 352 if (drm_core_check_feature(dev, DRIVER_MODESET))
353 return; 353 return;
354 354
355 if (IS_IGDNG(dev)) { 355 if (IS_IRONLAKE(dev)) {
356 dpll_a_reg = PCH_DPLL_A; 356 dpll_a_reg = PCH_DPLL_A;
357 dpll_b_reg = PCH_DPLL_B; 357 dpll_b_reg = PCH_DPLL_B;
358 fpa0_reg = PCH_FPA0; 358 fpa0_reg = PCH_FPA0;
@@ -380,7 +380,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
380 /* Actually enable it */ 380 /* Actually enable it */
381 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A); 381 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
382 DRM_UDELAY(150); 382 DRM_UDELAY(150);
383 if (IS_I965G(dev) && !IS_IGDNG(dev)) 383 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
384 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); 384 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
385 DRM_UDELAY(150); 385 DRM_UDELAY(150);
386 386
@@ -391,10 +391,10 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
391 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); 391 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
392 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); 392 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
393 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); 393 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
394 if (!IS_IGDNG(dev)) 394 if (!IS_IRONLAKE(dev))
395 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); 395 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
396 396
397 if (IS_IGDNG(dev)) { 397 if (IS_IRONLAKE(dev)) {
398 I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL); 398 I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
399 I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL); 399 I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
400 400
@@ -450,10 +450,10 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
450 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); 450 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
451 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); 451 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
452 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); 452 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
453 if (!IS_IGDNG(dev)) 453 if (!IS_IRONLAKE(dev))
454 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); 454 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
455 455
456 if (IS_IGDNG(dev)) { 456 if (IS_IRONLAKE(dev)) {
457 I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL); 457 I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
458 I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL); 458 I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
459 459
@@ -512,14 +512,14 @@ void i915_save_display(struct drm_device *dev)
512 dev_priv->saveCURSIZE = I915_READ(CURSIZE); 512 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
513 513
514 /* CRT state */ 514 /* CRT state */
515 if (IS_IGDNG(dev)) { 515 if (IS_IRONLAKE(dev)) {
516 dev_priv->saveADPA = I915_READ(PCH_ADPA); 516 dev_priv->saveADPA = I915_READ(PCH_ADPA);
517 } else { 517 } else {
518 dev_priv->saveADPA = I915_READ(ADPA); 518 dev_priv->saveADPA = I915_READ(ADPA);
519 } 519 }
520 520
521 /* LVDS state */ 521 /* LVDS state */
522 if (IS_IGDNG(dev)) { 522 if (IS_IRONLAKE(dev)) {
523 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL); 523 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
524 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1); 524 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
525 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2); 525 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
@@ -537,10 +537,10 @@ void i915_save_display(struct drm_device *dev)
537 dev_priv->saveLVDS = I915_READ(LVDS); 537 dev_priv->saveLVDS = I915_READ(LVDS);
538 } 538 }
539 539
540 if (!IS_I830(dev) && !IS_845G(dev) && !IS_IGDNG(dev)) 540 if (!IS_I830(dev) && !IS_845G(dev) && !IS_IRONLAKE(dev))
541 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); 541 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
542 542
543 if (IS_IGDNG(dev)) { 543 if (IS_IRONLAKE(dev)) {
544 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); 544 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
545 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); 545 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
546 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); 546 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
@@ -580,7 +580,7 @@ void i915_save_display(struct drm_device *dev)
580 dev_priv->saveVGA0 = I915_READ(VGA0); 580 dev_priv->saveVGA0 = I915_READ(VGA0);
581 dev_priv->saveVGA1 = I915_READ(VGA1); 581 dev_priv->saveVGA1 = I915_READ(VGA1);
582 dev_priv->saveVGA_PD = I915_READ(VGA_PD); 582 dev_priv->saveVGA_PD = I915_READ(VGA_PD);
583 if (IS_IGDNG(dev)) 583 if (IS_IRONLAKE(dev))
584 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL); 584 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
585 else 585 else
586 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); 586 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
@@ -622,24 +622,24 @@ void i915_restore_display(struct drm_device *dev)
622 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE); 622 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
623 623
624 /* CRT state */ 624 /* CRT state */
625 if (IS_IGDNG(dev)) 625 if (IS_IRONLAKE(dev))
626 I915_WRITE(PCH_ADPA, dev_priv->saveADPA); 626 I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
627 else 627 else
628 I915_WRITE(ADPA, dev_priv->saveADPA); 628 I915_WRITE(ADPA, dev_priv->saveADPA);
629 629
630 /* LVDS state */ 630 /* LVDS state */
631 if (IS_I965G(dev) && !IS_IGDNG(dev)) 631 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
632 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); 632 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
633 633
634 if (IS_IGDNG(dev)) { 634 if (IS_IRONLAKE(dev)) {
635 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS); 635 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
636 } else if (IS_MOBILE(dev) && !IS_I830(dev)) 636 } else if (IS_MOBILE(dev) && !IS_I830(dev))
637 I915_WRITE(LVDS, dev_priv->saveLVDS); 637 I915_WRITE(LVDS, dev_priv->saveLVDS);
638 638
639 if (!IS_I830(dev) && !IS_845G(dev) && !IS_IGDNG(dev)) 639 if (!IS_I830(dev) && !IS_845G(dev) && !IS_IRONLAKE(dev))
640 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); 640 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
641 641
642 if (IS_IGDNG(dev)) { 642 if (IS_IRONLAKE(dev)) {
643 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL); 643 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
644 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2); 644 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
645 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL); 645 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
@@ -679,7 +679,7 @@ void i915_restore_display(struct drm_device *dev)
679 } 679 }
680 680
681 /* VGA state */ 681 /* VGA state */
682 if (IS_IGDNG(dev)) 682 if (IS_IRONLAKE(dev))
683 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL); 683 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
684 else 684 else
685 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); 685 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
@@ -710,7 +710,7 @@ int i915_save_state(struct drm_device *dev)
710 i915_save_display(dev); 710 i915_save_display(dev);
711 711
712 /* Interrupt state */ 712 /* Interrupt state */
713 if (IS_IGDNG(dev)) { 713 if (IS_IRONLAKE(dev)) {
714 dev_priv->saveDEIER = I915_READ(DEIER); 714 dev_priv->saveDEIER = I915_READ(DEIER);
715 dev_priv->saveDEIMR = I915_READ(DEIMR); 715 dev_priv->saveDEIMR = I915_READ(DEIMR);
716 dev_priv->saveGTIER = I915_READ(GTIER); 716 dev_priv->saveGTIER = I915_READ(GTIER);
@@ -787,7 +787,7 @@ int i915_restore_state(struct drm_device *dev)
787 i915_restore_display(dev); 787 i915_restore_display(dev);
788 788
789 /* Interrupt state */ 789 /* Interrupt state */
790 if (IS_IGDNG(dev)) { 790 if (IS_IRONLAKE(dev)) {
791 I915_WRITE(DEIER, dev_priv->saveDEIER); 791 I915_WRITE(DEIER, dev_priv->saveDEIER);
792 I915_WRITE(DEIMR, dev_priv->saveDEIMR); 792 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
793 I915_WRITE(GTIER, dev_priv->saveGTIER); 793 I915_WRITE(GTIER, dev_priv->saveGTIER);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 73ceb36c790e..f27567747580 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -259,7 +259,7 @@ parse_general_features(struct drm_i915_private *dev_priv,
259 if (IS_I85X(dev_priv->dev)) 259 if (IS_I85X(dev_priv->dev))
260 dev_priv->lvds_ssc_freq = 260 dev_priv->lvds_ssc_freq =
261 general->ssc_freq ? 66 : 48; 261 general->ssc_freq ? 66 : 48;
262 else if (IS_IGDNG(dev_priv->dev)) 262 else if (IS_IRONLAKE(dev_priv->dev))
263 dev_priv->lvds_ssc_freq = 263 dev_priv->lvds_ssc_freq =
264 general->ssc_freq ? 100 : 120; 264 general->ssc_freq ? 100 : 120;
265 else 265 else
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 477a61c5402b..ec5df0f88417 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -39,7 +39,7 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
39 struct drm_i915_private *dev_priv = dev->dev_private; 39 struct drm_i915_private *dev_priv = dev->dev_private;
40 u32 temp, reg; 40 u32 temp, reg;
41 41
42 if (IS_IGDNG(dev)) 42 if (IS_IRONLAKE(dev))
43 reg = PCH_ADPA; 43 reg = PCH_ADPA;
44 else 44 else
45 reg = ADPA; 45 reg = ADPA;
@@ -113,7 +113,7 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
113 else 113 else
114 dpll_md_reg = DPLL_B_MD; 114 dpll_md_reg = DPLL_B_MD;
115 115
116 if (IS_IGDNG(dev)) 116 if (IS_IRONLAKE(dev))
117 adpa_reg = PCH_ADPA; 117 adpa_reg = PCH_ADPA;
118 else 118 else
119 adpa_reg = ADPA; 119 adpa_reg = ADPA;
@@ -122,7 +122,7 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
122 * Disable separate mode multiplier used when cloning SDVO to CRT 122 * Disable separate mode multiplier used when cloning SDVO to CRT
123 * XXX this needs to be adjusted when we really are cloning 123 * XXX this needs to be adjusted when we really are cloning
124 */ 124 */
125 if (IS_I965G(dev) && !IS_IGDNG(dev)) { 125 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
126 dpll_md = I915_READ(dpll_md_reg); 126 dpll_md = I915_READ(dpll_md_reg);
127 I915_WRITE(dpll_md_reg, 127 I915_WRITE(dpll_md_reg,
128 dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); 128 dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
@@ -136,18 +136,18 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
136 136
137 if (intel_crtc->pipe == 0) { 137 if (intel_crtc->pipe == 0) {
138 adpa |= ADPA_PIPE_A_SELECT; 138 adpa |= ADPA_PIPE_A_SELECT;
139 if (!IS_IGDNG(dev)) 139 if (!IS_IRONLAKE(dev))
140 I915_WRITE(BCLRPAT_A, 0); 140 I915_WRITE(BCLRPAT_A, 0);
141 } else { 141 } else {
142 adpa |= ADPA_PIPE_B_SELECT; 142 adpa |= ADPA_PIPE_B_SELECT;
143 if (!IS_IGDNG(dev)) 143 if (!IS_IRONLAKE(dev))
144 I915_WRITE(BCLRPAT_B, 0); 144 I915_WRITE(BCLRPAT_B, 0);
145 } 145 }
146 146
147 I915_WRITE(adpa_reg, adpa); 147 I915_WRITE(adpa_reg, adpa);
148} 148}
149 149
150static bool intel_igdng_crt_detect_hotplug(struct drm_connector *connector) 150static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
151{ 151{
152 struct drm_device *dev = connector->dev; 152 struct drm_device *dev = connector->dev;
153 struct drm_i915_private *dev_priv = dev->dev_private; 153 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -199,8 +199,8 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
199 u32 hotplug_en; 199 u32 hotplug_en;
200 int i, tries = 0; 200 int i, tries = 0;
201 201
202 if (IS_IGDNG(dev)) 202 if (IS_IRONLAKE(dev))
203 return intel_igdng_crt_detect_hotplug(connector); 203 return intel_ironlake_crt_detect_hotplug(connector);
204 204
205 /* 205 /*
206 * On 4 series desktop, CRT detect sequence need to be done twice 206 * On 4 series desktop, CRT detect sequence need to be done twice
@@ -521,7 +521,7 @@ void intel_crt_init(struct drm_device *dev)
521 &intel_output->enc); 521 &intel_output->enc);
522 522
523 /* Set up the DDC bus. */ 523 /* Set up the DDC bus. */
524 if (IS_IGDNG(dev)) 524 if (IS_IRONLAKE(dev))
525 i2c_reg = PCH_GPIOA; 525 i2c_reg = PCH_GPIOA;
526 else { 526 else {
527 i2c_reg = GPIOA; 527 i2c_reg = GPIOA;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6b9dd672dd59..902cc5386f19 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -102,32 +102,32 @@ struct intel_limit {
102#define I9XX_DOT_MAX 400000 102#define I9XX_DOT_MAX 400000
103#define I9XX_VCO_MIN 1400000 103#define I9XX_VCO_MIN 1400000
104#define I9XX_VCO_MAX 2800000 104#define I9XX_VCO_MAX 2800000
105#define IGD_VCO_MIN 1700000 105#define PINEVIEW_VCO_MIN 1700000
106#define IGD_VCO_MAX 3500000 106#define PINEVIEW_VCO_MAX 3500000
107#define I9XX_N_MIN 1 107#define I9XX_N_MIN 1
108#define I9XX_N_MAX 6 108#define I9XX_N_MAX 6
109/* IGD's Ncounter is a ring counter */ 109/* Pineview's Ncounter is a ring counter */
110#define IGD_N_MIN 3 110#define PINEVIEW_N_MIN 3
111#define IGD_N_MAX 6 111#define PINEVIEW_N_MAX 6
112#define I9XX_M_MIN 70 112#define I9XX_M_MIN 70
113#define I9XX_M_MAX 120 113#define I9XX_M_MAX 120
114#define IGD_M_MIN 2 114#define PINEVIEW_M_MIN 2
115#define IGD_M_MAX 256 115#define PINEVIEW_M_MAX 256
116#define I9XX_M1_MIN 10 116#define I9XX_M1_MIN 10
117#define I9XX_M1_MAX 22 117#define I9XX_M1_MAX 22
118#define I9XX_M2_MIN 5 118#define I9XX_M2_MIN 5
119#define I9XX_M2_MAX 9 119#define I9XX_M2_MAX 9
120/* IGD M1 is reserved, and must be 0 */ 120/* Pineview M1 is reserved, and must be 0 */
121#define IGD_M1_MIN 0 121#define PINEVIEW_M1_MIN 0
122#define IGD_M1_MAX 0 122#define PINEVIEW_M1_MAX 0
123#define IGD_M2_MIN 0 123#define PINEVIEW_M2_MIN 0
124#define IGD_M2_MAX 254 124#define PINEVIEW_M2_MAX 254
125#define I9XX_P_SDVO_DAC_MIN 5 125#define I9XX_P_SDVO_DAC_MIN 5
126#define I9XX_P_SDVO_DAC_MAX 80 126#define I9XX_P_SDVO_DAC_MAX 80
127#define I9XX_P_LVDS_MIN 7 127#define I9XX_P_LVDS_MIN 7
128#define I9XX_P_LVDS_MAX 98 128#define I9XX_P_LVDS_MAX 98
129#define IGD_P_LVDS_MIN 7 129#define PINEVIEW_P_LVDS_MIN 7
130#define IGD_P_LVDS_MAX 112 130#define PINEVIEW_P_LVDS_MAX 112
131#define I9XX_P1_MIN 1 131#define I9XX_P1_MIN 1
132#define I9XX_P1_MAX 8 132#define I9XX_P1_MAX 8
133#define I9XX_P2_SDVO_DAC_SLOW 10 133#define I9XX_P2_SDVO_DAC_SLOW 10
@@ -234,33 +234,33 @@ struct intel_limit {
234#define G4X_P2_DISPLAY_PORT_FAST 10 234#define G4X_P2_DISPLAY_PORT_FAST 10
235#define G4X_P2_DISPLAY_PORT_LIMIT 0 235#define G4X_P2_DISPLAY_PORT_LIMIT 0
236 236
237/* IGDNG */ 237/* Ironlake */
238/* as we calculate clock using (register_value + 2) for 238/* as we calculate clock using (register_value + 2) for
239 N/M1/M2, so here the range value for them is (actual_value-2). 239 N/M1/M2, so here the range value for them is (actual_value-2).
240 */ 240 */
241#define IGDNG_DOT_MIN 25000 241#define IRONLAKE_DOT_MIN 25000
242#define IGDNG_DOT_MAX 350000 242#define IRONLAKE_DOT_MAX 350000
243#define IGDNG_VCO_MIN 1760000 243#define IRONLAKE_VCO_MIN 1760000
244#define IGDNG_VCO_MAX 3510000 244#define IRONLAKE_VCO_MAX 3510000
245#define IGDNG_N_MIN 1 245#define IRONLAKE_N_MIN 1
246#define IGDNG_N_MAX 5 246#define IRONLAKE_N_MAX 5
247#define IGDNG_M_MIN 79 247#define IRONLAKE_M_MIN 79
248#define IGDNG_M_MAX 118 248#define IRONLAKE_M_MAX 118
249#define IGDNG_M1_MIN 12 249#define IRONLAKE_M1_MIN 12
250#define IGDNG_M1_MAX 23 250#define IRONLAKE_M1_MAX 23
251#define IGDNG_M2_MIN 5 251#define IRONLAKE_M2_MIN 5
252#define IGDNG_M2_MAX 9 252#define IRONLAKE_M2_MAX 9
253#define IGDNG_P_SDVO_DAC_MIN 5 253#define IRONLAKE_P_SDVO_DAC_MIN 5
254#define IGDNG_P_SDVO_DAC_MAX 80 254#define IRONLAKE_P_SDVO_DAC_MAX 80
255#define IGDNG_P_LVDS_MIN 28 255#define IRONLAKE_P_LVDS_MIN 28
256#define IGDNG_P_LVDS_MAX 112 256#define IRONLAKE_P_LVDS_MAX 112
257#define IGDNG_P1_MIN 1 257#define IRONLAKE_P1_MIN 1
258#define IGDNG_P1_MAX 8 258#define IRONLAKE_P1_MAX 8
259#define IGDNG_P2_SDVO_DAC_SLOW 10 259#define IRONLAKE_P2_SDVO_DAC_SLOW 10
260#define IGDNG_P2_SDVO_DAC_FAST 5 260#define IRONLAKE_P2_SDVO_DAC_FAST 5
261#define IGDNG_P2_LVDS_SLOW 14 /* single channel */ 261#define IRONLAKE_P2_LVDS_SLOW 14 /* single channel */
262#define IGDNG_P2_LVDS_FAST 7 /* double channel */ 262#define IRONLAKE_P2_LVDS_FAST 7 /* double channel */
263#define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */ 263#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
264 264
265static bool 265static bool
266intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 266intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
@@ -272,15 +272,15 @@ static bool
272intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 272intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
273 int target, int refclk, intel_clock_t *best_clock); 273 int target, int refclk, intel_clock_t *best_clock);
274static bool 274static bool
275intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 275intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
276 int target, int refclk, intel_clock_t *best_clock); 276 int target, int refclk, intel_clock_t *best_clock);
277 277
278static bool 278static bool
279intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, 279intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
280 int target, int refclk, intel_clock_t *best_clock); 280 int target, int refclk, intel_clock_t *best_clock);
281static bool 281static bool
282intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc, 282intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
283 int target, int refclk, intel_clock_t *best_clock); 283 int target, int refclk, intel_clock_t *best_clock);
284 284
285static const intel_limit_t intel_limits_i8xx_dvo = { 285static const intel_limit_t intel_limits_i8xx_dvo = {
286 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, 286 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
@@ -453,13 +453,13 @@ static const intel_limit_t intel_limits_g4x_display_port = {
453 .find_pll = intel_find_pll_g4x_dp, 453 .find_pll = intel_find_pll_g4x_dp,
454}; 454};
455 455
456static const intel_limit_t intel_limits_igd_sdvo = { 456static const intel_limit_t intel_limits_pineview_sdvo = {
457 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, 457 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
458 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, 458 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
459 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, 459 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
460 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, 460 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
461 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, 461 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
462 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, 462 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
463 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, 463 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
464 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, 464 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
465 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, 465 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
@@ -468,59 +468,59 @@ static const intel_limit_t intel_limits_igd_sdvo = {
468 .find_reduced_pll = intel_find_best_reduced_PLL, 468 .find_reduced_pll = intel_find_best_reduced_PLL,
469}; 469};
470 470
471static const intel_limit_t intel_limits_igd_lvds = { 471static const intel_limit_t intel_limits_pineview_lvds = {
472 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, 472 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
473 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, 473 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
474 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, 474 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
475 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, 475 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
476 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, 476 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
477 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, 477 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
478 .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX }, 478 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
479 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, 479 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
480 /* IGD only supports single-channel mode. */ 480 /* Pineview only supports single-channel mode. */
481 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, 481 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
482 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, 482 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
483 .find_pll = intel_find_best_PLL, 483 .find_pll = intel_find_best_PLL,
484 .find_reduced_pll = intel_find_best_reduced_PLL, 484 .find_reduced_pll = intel_find_best_reduced_PLL,
485}; 485};
486 486
487static const intel_limit_t intel_limits_igdng_sdvo = { 487static const intel_limit_t intel_limits_ironlake_sdvo = {
488 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX }, 488 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
489 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX }, 489 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
490 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX }, 490 .n = { .min = IRONLAKE_N_MIN, .max = IRONLAKE_N_MAX },
491 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX }, 491 .m = { .min = IRONLAKE_M_MIN, .max = IRONLAKE_M_MAX },
492 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX }, 492 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
493 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX }, 493 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
494 .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX }, 494 .p = { .min = IRONLAKE_P_SDVO_DAC_MIN, .max = IRONLAKE_P_SDVO_DAC_MAX },
495 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX }, 495 .p1 = { .min = IRONLAKE_P1_MIN, .max = IRONLAKE_P1_MAX },
496 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT, 496 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
497 .p2_slow = IGDNG_P2_SDVO_DAC_SLOW, 497 .p2_slow = IRONLAKE_P2_SDVO_DAC_SLOW,
498 .p2_fast = IGDNG_P2_SDVO_DAC_FAST }, 498 .p2_fast = IRONLAKE_P2_SDVO_DAC_FAST },
499 .find_pll = intel_igdng_find_best_PLL, 499 .find_pll = intel_ironlake_find_best_PLL,
500}; 500};
501 501
502static const intel_limit_t intel_limits_igdng_lvds = { 502static const intel_limit_t intel_limits_ironlake_lvds = {
503 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX }, 503 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
504 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX }, 504 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
505 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX }, 505 .n = { .min = IRONLAKE_N_MIN, .max = IRONLAKE_N_MAX },
506 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX }, 506 .m = { .min = IRONLAKE_M_MIN, .max = IRONLAKE_M_MAX },
507 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX }, 507 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
508 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX }, 508 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
509 .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX }, 509 .p = { .min = IRONLAKE_P_LVDS_MIN, .max = IRONLAKE_P_LVDS_MAX },
510 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX }, 510 .p1 = { .min = IRONLAKE_P1_MIN, .max = IRONLAKE_P1_MAX },
511 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT, 511 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
512 .p2_slow = IGDNG_P2_LVDS_SLOW, 512 .p2_slow = IRONLAKE_P2_LVDS_SLOW,
513 .p2_fast = IGDNG_P2_LVDS_FAST }, 513 .p2_fast = IRONLAKE_P2_LVDS_FAST },
514 .find_pll = intel_igdng_find_best_PLL, 514 .find_pll = intel_ironlake_find_best_PLL,
515}; 515};
516 516
517static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc) 517static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
518{ 518{
519 const intel_limit_t *limit; 519 const intel_limit_t *limit;
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
521 limit = &intel_limits_igdng_lvds; 521 limit = &intel_limits_ironlake_lvds;
522 else 522 else
523 limit = &intel_limits_igdng_sdvo; 523 limit = &intel_limits_ironlake_sdvo;
524 524
525 return limit; 525 return limit;
526} 526}
@@ -557,20 +557,20 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
557 struct drm_device *dev = crtc->dev; 557 struct drm_device *dev = crtc->dev;
558 const intel_limit_t *limit; 558 const intel_limit_t *limit;
559 559
560 if (IS_IGDNG(dev)) 560 if (IS_IRONLAKE(dev))
561 limit = intel_igdng_limit(crtc); 561 limit = intel_ironlake_limit(crtc);
562 else if (IS_G4X(dev)) { 562 else if (IS_G4X(dev)) {
563 limit = intel_g4x_limit(crtc); 563 limit = intel_g4x_limit(crtc);
564 } else if (IS_I9XX(dev) && !IS_IGD(dev)) { 564 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
565 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 565 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
566 limit = &intel_limits_i9xx_lvds; 566 limit = &intel_limits_i9xx_lvds;
567 else 567 else
568 limit = &intel_limits_i9xx_sdvo; 568 limit = &intel_limits_i9xx_sdvo;
569 } else if (IS_IGD(dev)) { 569 } else if (IS_PINEVIEW(dev)) {
570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
571 limit = &intel_limits_igd_lvds; 571 limit = &intel_limits_pineview_lvds;
572 else 572 else
573 limit = &intel_limits_igd_sdvo; 573 limit = &intel_limits_pineview_sdvo;
574 } else { 574 } else {
575 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 575 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
576 limit = &intel_limits_i8xx_lvds; 576 limit = &intel_limits_i8xx_lvds;
@@ -580,8 +580,8 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
580 return limit; 580 return limit;
581} 581}
582 582
583/* m1 is reserved as 0 in IGD, n is a ring counter */ 583/* m1 is reserved as 0 in Pineview, n is a ring counter */
584static void igd_clock(int refclk, intel_clock_t *clock) 584static void pineview_clock(int refclk, intel_clock_t *clock)
585{ 585{
586 clock->m = clock->m2 + 2; 586 clock->m = clock->m2 + 2;
587 clock->p = clock->p1 * clock->p2; 587 clock->p = clock->p1 * clock->p2;
@@ -591,8 +591,8 @@ static void igd_clock(int refclk, intel_clock_t *clock)
591 591
592static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) 592static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
593{ 593{
594 if (IS_IGD(dev)) { 594 if (IS_PINEVIEW(dev)) {
595 igd_clock(refclk, clock); 595 pineview_clock(refclk, clock);
596 return; 596 return;
597 } 597 }
598 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 598 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
@@ -657,7 +657,7 @@ static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
657 INTELPllInvalid ("m2 out of range\n"); 657 INTELPllInvalid ("m2 out of range\n");
658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
659 INTELPllInvalid ("m1 out of range\n"); 659 INTELPllInvalid ("m1 out of range\n");
660 if (clock->m1 <= clock->m2 && !IS_IGD(dev)) 660 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
661 INTELPllInvalid ("m1 <= m2\n"); 661 INTELPllInvalid ("m1 <= m2\n");
662 if (clock->m < limit->m.min || limit->m.max < clock->m) 662 if (clock->m < limit->m.min || limit->m.max < clock->m)
663 INTELPllInvalid ("m out of range\n"); 663 INTELPllInvalid ("m out of range\n");
@@ -710,8 +710,8 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
710 clock.m1++) { 710 clock.m1++) {
711 for (clock.m2 = limit->m2.min; 711 for (clock.m2 = limit->m2.min;
712 clock.m2 <= limit->m2.max; clock.m2++) { 712 clock.m2 <= limit->m2.max; clock.m2++) {
713 /* m1 is always 0 in IGD */ 713 /* m1 is always 0 in Pineview */
714 if (clock.m2 >= clock.m1 && !IS_IGD(dev)) 714 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
715 break; 715 break;
716 for (clock.n = limit->n.min; 716 for (clock.n = limit->n.min;
717 clock.n <= limit->n.max; clock.n++) { 717 clock.n <= limit->n.max; clock.n++) {
@@ -752,8 +752,8 @@ intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
752 752
753 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 753 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
754 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) { 754 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
755 /* m1 is always 0 in IGD */ 755 /* m1 is always 0 in Pineview */
756 if (clock.m2 >= clock.m1 && !IS_IGD(dev)) 756 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
757 break; 757 break;
758 for (clock.n = limit->n.min; clock.n <= limit->n.max; 758 for (clock.n = limit->n.min; clock.n <= limit->n.max;
759 clock.n++) { 759 clock.n++) {
@@ -834,8 +834,8 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
834} 834}
835 835
836static bool 836static bool
837intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 837intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
838 int target, int refclk, intel_clock_t *best_clock) 838 int target, int refclk, intel_clock_t *best_clock)
839{ 839{
840 struct drm_device *dev = crtc->dev; 840 struct drm_device *dev = crtc->dev;
841 intel_clock_t clock; 841 intel_clock_t clock;
@@ -858,8 +858,8 @@ intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
858} 858}
859 859
860static bool 860static bool
861intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 861intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
862 int target, int refclk, intel_clock_t *best_clock) 862 int target, int refclk, intel_clock_t *best_clock)
863{ 863{
864 struct drm_device *dev = crtc->dev; 864 struct drm_device *dev = crtc->dev;
865 struct drm_i915_private *dev_priv = dev->dev_private; 865 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -872,7 +872,7 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
872 return true; 872 return true;
873 873
874 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) 874 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
875 return intel_find_pll_igdng_dp(limit, crtc, target, 875 return intel_find_pll_ironlake_dp(limit, crtc, target,
876 refclk, best_clock); 876 refclk, best_clock);
877 877
878 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 878 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
@@ -1322,7 +1322,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1322 dspcntr &= ~DISPPLANE_TILED; 1322 dspcntr &= ~DISPPLANE_TILED;
1323 } 1323 }
1324 1324
1325 if (IS_IGDNG(dev)) 1325 if (IS_IRONLAKE(dev))
1326 /* must disable */ 1326 /* must disable */
1327 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 1327 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1328 1328
@@ -1383,7 +1383,7 @@ static void i915_disable_vga (struct drm_device *dev)
1383 u8 sr1; 1383 u8 sr1;
1384 u32 vga_reg; 1384 u32 vga_reg;
1385 1385
1386 if (IS_IGDNG(dev)) 1386 if (IS_IRONLAKE(dev))
1387 vga_reg = CPU_VGACNTRL; 1387 vga_reg = CPU_VGACNTRL;
1388 else 1388 else
1389 vga_reg = VGACNTRL; 1389 vga_reg = VGACNTRL;
@@ -1399,7 +1399,7 @@ static void i915_disable_vga (struct drm_device *dev)
1399 I915_WRITE(vga_reg, VGA_DISP_DISABLE); 1399 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1400} 1400}
1401 1401
1402static void igdng_disable_pll_edp (struct drm_crtc *crtc) 1402static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1403{ 1403{
1404 struct drm_device *dev = crtc->dev; 1404 struct drm_device *dev = crtc->dev;
1405 struct drm_i915_private *dev_priv = dev->dev_private; 1405 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1411,7 +1411,7 @@ static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1411 I915_WRITE(DP_A, dpa_ctl); 1411 I915_WRITE(DP_A, dpa_ctl);
1412} 1412}
1413 1413
1414static void igdng_enable_pll_edp (struct drm_crtc *crtc) 1414static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1415{ 1415{
1416 struct drm_device *dev = crtc->dev; 1416 struct drm_device *dev = crtc->dev;
1417 struct drm_i915_private *dev_priv = dev->dev_private; 1417 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1424,7 +1424,7 @@ static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1424} 1424}
1425 1425
1426 1426
1427static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock) 1427static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1428{ 1428{
1429 struct drm_device *dev = crtc->dev; 1429 struct drm_device *dev = crtc->dev;
1430 struct drm_i915_private *dev_priv = dev->dev_private; 1430 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1460,7 +1460,7 @@ static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1460 udelay(500); 1460 udelay(500);
1461} 1461}
1462 1462
1463static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode) 1463static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1464{ 1464{
1465 struct drm_device *dev = crtc->dev; 1465 struct drm_device *dev = crtc->dev;
1466 struct drm_i915_private *dev_priv = dev->dev_private; 1466 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1513,7 +1513,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1513 1513
1514 if (HAS_eDP) { 1514 if (HAS_eDP) {
1515 /* enable eDP PLL */ 1515 /* enable eDP PLL */
1516 igdng_enable_pll_edp(crtc); 1516 ironlake_enable_pll_edp(crtc);
1517 } else { 1517 } else {
1518 /* enable PCH DPLL */ 1518 /* enable PCH DPLL */
1519 temp = I915_READ(pch_dpll_reg); 1519 temp = I915_READ(pch_dpll_reg);
@@ -1530,7 +1530,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1530 I915_READ(fdi_rx_reg); 1530 I915_READ(fdi_rx_reg);
1531 udelay(200); 1531 udelay(200);
1532 1532
1533 /* Enable CPU FDI TX PLL, always on for IGDNG */ 1533 /* Enable CPU FDI TX PLL, always on for Ironlake */
1534 temp = I915_READ(fdi_tx_reg); 1534 temp = I915_READ(fdi_tx_reg);
1535 if ((temp & FDI_TX_PLL_ENABLE) == 0) { 1535 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1536 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE); 1536 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
@@ -1800,7 +1800,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1800 } 1800 }
1801 1801
1802 if (HAS_eDP) { 1802 if (HAS_eDP) {
1803 igdng_disable_pll_edp(crtc); 1803 ironlake_disable_pll_edp(crtc);
1804 } 1804 }
1805 1805
1806 temp = I915_READ(fdi_rx_reg); 1806 temp = I915_READ(fdi_rx_reg);
@@ -2042,7 +2042,7 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2042 struct drm_display_mode *adjusted_mode) 2042 struct drm_display_mode *adjusted_mode)
2043{ 2043{
2044 struct drm_device *dev = crtc->dev; 2044 struct drm_device *dev = crtc->dev;
2045 if (IS_IGDNG(dev)) { 2045 if (IS_IRONLAKE(dev)) {
2046 /* FDI link clock is fixed at 2.7G */ 2046 /* FDI link clock is fixed at 2.7G */
2047 if (mode->clock * 3 > 27000 * 4) 2047 if (mode->clock * 3 > 27000 * 4)
2048 return MODE_CLOCK_HIGH; 2048 return MODE_CLOCK_HIGH;
@@ -2162,9 +2162,8 @@ fdi_reduce_ratio(u32 *num, u32 *den)
2162#define LINK_N 0x80000 2162#define LINK_N 0x80000
2163 2163
2164static void 2164static void
2165igdng_compute_m_n(int bits_per_pixel, int nlanes, 2165ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2166 int pixel_clock, int link_clock, 2166 int link_clock, struct fdi_m_n *m_n)
2167 struct fdi_m_n *m_n)
2168{ 2167{
2169 u64 temp; 2168 u64 temp;
2170 2169
@@ -2192,34 +2191,34 @@ struct intel_watermark_params {
2192 unsigned long cacheline_size; 2191 unsigned long cacheline_size;
2193}; 2192};
2194 2193
2195/* IGD has different values for various configs */ 2194/* Pineview has different values for various configs */
2196static struct intel_watermark_params igd_display_wm = { 2195static struct intel_watermark_params pineview_display_wm = {
2197 IGD_DISPLAY_FIFO, 2196 PINEVIEW_DISPLAY_FIFO,
2198 IGD_MAX_WM, 2197 PINEVIEW_MAX_WM,
2199 IGD_DFT_WM, 2198 PINEVIEW_DFT_WM,
2200 IGD_GUARD_WM, 2199 PINEVIEW_GUARD_WM,
2201 IGD_FIFO_LINE_SIZE 2200 PINEVIEW_FIFO_LINE_SIZE
2202}; 2201};
2203static struct intel_watermark_params igd_display_hplloff_wm = { 2202static struct intel_watermark_params pineview_display_hplloff_wm = {
2204 IGD_DISPLAY_FIFO, 2203 PINEVIEW_DISPLAY_FIFO,
2205 IGD_MAX_WM, 2204 PINEVIEW_MAX_WM,
2206 IGD_DFT_HPLLOFF_WM, 2205 PINEVIEW_DFT_HPLLOFF_WM,
2207 IGD_GUARD_WM, 2206 PINEVIEW_GUARD_WM,
2208 IGD_FIFO_LINE_SIZE 2207 PINEVIEW_FIFO_LINE_SIZE
2209}; 2208};
2210static struct intel_watermark_params igd_cursor_wm = { 2209static struct intel_watermark_params pineview_cursor_wm = {
2211 IGD_CURSOR_FIFO, 2210 PINEVIEW_CURSOR_FIFO,
2212 IGD_CURSOR_MAX_WM, 2211 PINEVIEW_CURSOR_MAX_WM,
2213 IGD_CURSOR_DFT_WM, 2212 PINEVIEW_CURSOR_DFT_WM,
2214 IGD_CURSOR_GUARD_WM, 2213 PINEVIEW_CURSOR_GUARD_WM,
2215 IGD_FIFO_LINE_SIZE, 2214 PINEVIEW_FIFO_LINE_SIZE,
2216}; 2215};
2217static struct intel_watermark_params igd_cursor_hplloff_wm = { 2216static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2218 IGD_CURSOR_FIFO, 2217 PINEVIEW_CURSOR_FIFO,
2219 IGD_CURSOR_MAX_WM, 2218 PINEVIEW_CURSOR_MAX_WM,
2220 IGD_CURSOR_DFT_WM, 2219 PINEVIEW_CURSOR_DFT_WM,
2221 IGD_CURSOR_GUARD_WM, 2220 PINEVIEW_CURSOR_GUARD_WM,
2222 IGD_FIFO_LINE_SIZE 2221 PINEVIEW_FIFO_LINE_SIZE
2223}; 2222};
2224static struct intel_watermark_params g4x_wm_info = { 2223static struct intel_watermark_params g4x_wm_info = {
2225 G4X_FIFO_SIZE, 2224 G4X_FIFO_SIZE,
@@ -2363,36 +2362,36 @@ static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2363 return NULL; 2362 return NULL;
2364} 2363}
2365 2364
2366static void igd_disable_cxsr(struct drm_device *dev) 2365static void pineview_disable_cxsr(struct drm_device *dev)
2367{ 2366{
2368 struct drm_i915_private *dev_priv = dev->dev_private; 2367 struct drm_i915_private *dev_priv = dev->dev_private;
2369 u32 reg; 2368 u32 reg;
2370 2369
2371 /* deactivate cxsr */ 2370 /* deactivate cxsr */
2372 reg = I915_READ(DSPFW3); 2371 reg = I915_READ(DSPFW3);
2373 reg &= ~(IGD_SELF_REFRESH_EN); 2372 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2374 I915_WRITE(DSPFW3, reg); 2373 I915_WRITE(DSPFW3, reg);
2375 DRM_INFO("Big FIFO is disabled\n"); 2374 DRM_INFO("Big FIFO is disabled\n");
2376} 2375}
2377 2376
2378static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock, 2377static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2379 int pixel_size) 2378 int pixel_size)
2380{ 2379{
2381 struct drm_i915_private *dev_priv = dev->dev_private; 2380 struct drm_i915_private *dev_priv = dev->dev_private;
2382 u32 reg; 2381 u32 reg;
2383 unsigned long wm; 2382 unsigned long wm;
2384 struct cxsr_latency *latency; 2383 struct cxsr_latency *latency;
2385 2384
2386 latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq, 2385 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2387 dev_priv->mem_freq); 2386 dev_priv->mem_freq);
2388 if (!latency) { 2387 if (!latency) {
2389 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 2388 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2390 igd_disable_cxsr(dev); 2389 pineview_disable_cxsr(dev);
2391 return; 2390 return;
2392 } 2391 }
2393 2392
2394 /* Display SR */ 2393 /* Display SR */
2395 wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size, 2394 wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2396 latency->display_sr); 2395 latency->display_sr);
2397 reg = I915_READ(DSPFW1); 2396 reg = I915_READ(DSPFW1);
2398 reg &= 0x7fffff; 2397 reg &= 0x7fffff;
@@ -2401,7 +2400,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2401 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); 2400 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2402 2401
2403 /* cursor SR */ 2402 /* cursor SR */
2404 wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size, 2403 wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2405 latency->cursor_sr); 2404 latency->cursor_sr);
2406 reg = I915_READ(DSPFW3); 2405 reg = I915_READ(DSPFW3);
2407 reg &= ~(0x3f << 24); 2406 reg &= ~(0x3f << 24);
@@ -2409,7 +2408,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2409 I915_WRITE(DSPFW3, reg); 2408 I915_WRITE(DSPFW3, reg);
2410 2409
2411 /* Display HPLL off SR */ 2410 /* Display HPLL off SR */
2412 wm = intel_calculate_wm(clock, &igd_display_hplloff_wm, 2411 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2413 latency->display_hpll_disable, I915_FIFO_LINE_SIZE); 2412 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2414 reg = I915_READ(DSPFW3); 2413 reg = I915_READ(DSPFW3);
2415 reg &= 0xfffffe00; 2414 reg &= 0xfffffe00;
@@ -2417,7 +2416,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2417 I915_WRITE(DSPFW3, reg); 2416 I915_WRITE(DSPFW3, reg);
2418 2417
2419 /* cursor HPLL off SR */ 2418 /* cursor HPLL off SR */
2420 wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size, 2419 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2421 latency->cursor_hpll_disable); 2420 latency->cursor_hpll_disable);
2422 reg = I915_READ(DSPFW3); 2421 reg = I915_READ(DSPFW3);
2423 reg &= ~(0x3f << 16); 2422 reg &= ~(0x3f << 16);
@@ -2427,7 +2426,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2427 2426
2428 /* activate cxsr */ 2427 /* activate cxsr */
2429 reg = I915_READ(DSPFW3); 2428 reg = I915_READ(DSPFW3);
2430 reg |= IGD_SELF_REFRESH_EN; 2429 reg |= PINEVIEW_SELF_REFRESH_EN;
2431 I915_WRITE(DSPFW3, reg); 2430 I915_WRITE(DSPFW3, reg);
2432 2431
2433 DRM_INFO("Big FIFO is enabled\n"); 2432 DRM_INFO("Big FIFO is enabled\n");
@@ -2786,10 +2785,10 @@ static void intel_update_watermarks(struct drm_device *dev)
2786 return; 2785 return;
2787 2786
2788 /* Single plane configs can enable self refresh */ 2787 /* Single plane configs can enable self refresh */
2789 if (enabled == 1 && IS_IGD(dev)) 2788 if (enabled == 1 && IS_PINEVIEW(dev))
2790 igd_enable_cxsr(dev, sr_clock, pixel_size); 2789 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2791 else if (IS_IGD(dev)) 2790 else if (IS_PINEVIEW(dev))
2792 igd_disable_cxsr(dev); 2791 pineview_disable_cxsr(dev);
2793 2792
2794 dev_priv->display.update_wm(dev, planea_clock, planeb_clock, 2793 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2795 sr_hdisplay, pixel_size); 2794 sr_hdisplay, pixel_size);
@@ -2887,7 +2886,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2887 refclk / 1000); 2886 refclk / 1000);
2888 } else if (IS_I9XX(dev)) { 2887 } else if (IS_I9XX(dev)) {
2889 refclk = 96000; 2888 refclk = 96000;
2890 if (IS_IGDNG(dev)) 2889 if (IS_IRONLAKE(dev))
2891 refclk = 120000; /* 120Mhz refclk */ 2890 refclk = 120000; /* 120Mhz refclk */
2892 } else { 2891 } else {
2893 refclk = 48000; 2892 refclk = 48000;
@@ -2947,7 +2946,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2947 } 2946 }
2948 2947
2949 /* FDI link */ 2948 /* FDI link */
2950 if (IS_IGDNG(dev)) { 2949 if (IS_IRONLAKE(dev)) {
2951 int lane, link_bw, bpp; 2950 int lane, link_bw, bpp;
2952 /* eDP doesn't require FDI link, so just set DP M/N 2951 /* eDP doesn't require FDI link, so just set DP M/N
2953 according to current link config */ 2952 according to current link config */
@@ -2989,8 +2988,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2989 bpp = 24; 2988 bpp = 24;
2990 } 2989 }
2991 2990
2992 igdng_compute_m_n(bpp, lane, target_clock, 2991 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
2993 link_bw, &m_n);
2994 } 2992 }
2995 2993
2996 /* Ironlake: try to setup display ref clock before DPLL 2994 /* Ironlake: try to setup display ref clock before DPLL
@@ -2998,7 +2996,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2998 * PCH B stepping, previous chipset stepping should be 2996 * PCH B stepping, previous chipset stepping should be
2999 * ignoring this setting. 2997 * ignoring this setting.
3000 */ 2998 */
3001 if (IS_IGDNG(dev)) { 2999 if (IS_IRONLAKE(dev)) {
3002 temp = I915_READ(PCH_DREF_CONTROL); 3000 temp = I915_READ(PCH_DREF_CONTROL);
3003 /* Always enable nonspread source */ 3001 /* Always enable nonspread source */
3004 temp &= ~DREF_NONSPREAD_SOURCE_MASK; 3002 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
@@ -3033,7 +3031,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3033 } 3031 }
3034 } 3032 }
3035 3033
3036 if (IS_IGD(dev)) { 3034 if (IS_PINEVIEW(dev)) {
3037 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; 3035 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3038 if (has_reduced_clock) 3036 if (has_reduced_clock)
3039 fp2 = (1 << reduced_clock.n) << 16 | 3037 fp2 = (1 << reduced_clock.n) << 16 |
@@ -3045,7 +3043,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3045 reduced_clock.m2; 3043 reduced_clock.m2;
3046 } 3044 }
3047 3045
3048 if (!IS_IGDNG(dev)) 3046 if (!IS_IRONLAKE(dev))
3049 dpll = DPLL_VGA_MODE_DIS; 3047 dpll = DPLL_VGA_MODE_DIS;
3050 3048
3051 if (IS_I9XX(dev)) { 3049 if (IS_I9XX(dev)) {
@@ -3058,19 +3056,19 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3058 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; 3056 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3059 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 3057 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3060 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 3058 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3061 else if (IS_IGDNG(dev)) 3059 else if (IS_IRONLAKE(dev))
3062 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 3060 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3063 } 3061 }
3064 if (is_dp) 3062 if (is_dp)
3065 dpll |= DPLL_DVO_HIGH_SPEED; 3063 dpll |= DPLL_DVO_HIGH_SPEED;
3066 3064
3067 /* compute bitmask from p1 value */ 3065 /* compute bitmask from p1 value */
3068 if (IS_IGD(dev)) 3066 if (IS_PINEVIEW(dev))
3069 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD; 3067 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3070 else { 3068 else {
3071 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 3069 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3072 /* also FPA1 */ 3070 /* also FPA1 */
3073 if (IS_IGDNG(dev)) 3071 if (IS_IRONLAKE(dev))
3074 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 3072 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3075 if (IS_G4X(dev) && has_reduced_clock) 3073 if (IS_G4X(dev) && has_reduced_clock)
3076 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 3074 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
@@ -3089,7 +3087,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3089 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 3087 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3090 break; 3088 break;
3091 } 3089 }
3092 if (IS_I965G(dev) && !IS_IGDNG(dev)) 3090 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
3093 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 3091 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3094 } else { 3092 } else {
3095 if (is_lvds) { 3093 if (is_lvds) {
@@ -3121,9 +3119,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3121 /* Set up the display plane register */ 3119 /* Set up the display plane register */
3122 dspcntr = DISPPLANE_GAMMA_ENABLE; 3120 dspcntr = DISPPLANE_GAMMA_ENABLE;
3123 3121
3124 /* IGDNG's plane is forced to pipe, bit 24 is to 3122 /* Ironlake's plane is forced to pipe, bit 24 is to
3125 enable color space conversion */ 3123 enable color space conversion */
3126 if (!IS_IGDNG(dev)) { 3124 if (!IS_IRONLAKE(dev)) {
3127 if (pipe == 0) 3125 if (pipe == 0)
3128 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; 3126 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3129 else 3127 else
@@ -3150,20 +3148,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3150 3148
3151 3149
3152 /* Disable the panel fitter if it was on our pipe */ 3150 /* Disable the panel fitter if it was on our pipe */
3153 if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe) 3151 if (!IS_IRONLAKE(dev) && intel_panel_fitter_pipe(dev) == pipe)
3154 I915_WRITE(PFIT_CONTROL, 0); 3152 I915_WRITE(PFIT_CONTROL, 0);
3155 3153
3156 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 3154 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3157 drm_mode_debug_printmodeline(mode); 3155 drm_mode_debug_printmodeline(mode);
3158 3156
3159 /* assign to IGDNG registers */ 3157 /* assign to Ironlake registers */
3160 if (IS_IGDNG(dev)) { 3158 if (IS_IRONLAKE(dev)) {
3161 fp_reg = pch_fp_reg; 3159 fp_reg = pch_fp_reg;
3162 dpll_reg = pch_dpll_reg; 3160 dpll_reg = pch_dpll_reg;
3163 } 3161 }
3164 3162
3165 if (is_edp) { 3163 if (is_edp) {
3166 igdng_disable_pll_edp(crtc); 3164 ironlake_disable_pll_edp(crtc);
3167 } else if ((dpll & DPLL_VCO_ENABLE)) { 3165 } else if ((dpll & DPLL_VCO_ENABLE)) {
3168 I915_WRITE(fp_reg, fp); 3166 I915_WRITE(fp_reg, fp);
3169 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); 3167 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
@@ -3178,7 +3176,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3178 if (is_lvds) { 3176 if (is_lvds) {
3179 u32 lvds; 3177 u32 lvds;
3180 3178
3181 if (IS_IGDNG(dev)) 3179 if (IS_IRONLAKE(dev))
3182 lvds_reg = PCH_LVDS; 3180 lvds_reg = PCH_LVDS;
3183 3181
3184 lvds = I915_READ(lvds_reg); 3182 lvds = I915_READ(lvds_reg);
@@ -3211,7 +3209,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3211 /* Wait for the clocks to stabilize. */ 3209 /* Wait for the clocks to stabilize. */
3212 udelay(150); 3210 udelay(150);
3213 3211
3214 if (IS_I965G(dev) && !IS_IGDNG(dev)) { 3212 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
3215 if (is_sdvo) { 3213 if (is_sdvo) {
3216 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; 3214 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3217 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | 3215 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
@@ -3258,21 +3256,21 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3258 /* pipesrc and dspsize control the size that is scaled from, which should 3256 /* pipesrc and dspsize control the size that is scaled from, which should
3259 * always be the user's requested size. 3257 * always be the user's requested size.
3260 */ 3258 */
3261 if (!IS_IGDNG(dev)) { 3259 if (!IS_IRONLAKE(dev)) {
3262 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | 3260 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3263 (mode->hdisplay - 1)); 3261 (mode->hdisplay - 1));
3264 I915_WRITE(dsppos_reg, 0); 3262 I915_WRITE(dsppos_reg, 0);
3265 } 3263 }
3266 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 3264 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3267 3265
3268 if (IS_IGDNG(dev)) { 3266 if (IS_IRONLAKE(dev)) {
3269 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m); 3267 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3270 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n); 3268 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3271 I915_WRITE(link_m1_reg, m_n.link_m); 3269 I915_WRITE(link_m1_reg, m_n.link_m);
3272 I915_WRITE(link_n1_reg, m_n.link_n); 3270 I915_WRITE(link_n1_reg, m_n.link_n);
3273 3271
3274 if (is_edp) { 3272 if (is_edp) {
3275 igdng_set_pll_edp(crtc, adjusted_mode->clock); 3273 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3276 } else { 3274 } else {
3277 /* enable FDI RX PLL too */ 3275 /* enable FDI RX PLL too */
3278 temp = I915_READ(fdi_rx_reg); 3276 temp = I915_READ(fdi_rx_reg);
@@ -3286,7 +3284,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3286 3284
3287 intel_wait_for_vblank(dev); 3285 intel_wait_for_vblank(dev);
3288 3286
3289 if (IS_IGDNG(dev)) { 3287 if (IS_IRONLAKE(dev)) {
3290 /* enable address swizzle for tiling buffer */ 3288 /* enable address swizzle for tiling buffer */
3291 temp = I915_READ(DISP_ARB_CTL); 3289 temp = I915_READ(DISP_ARB_CTL);
3292 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); 3290 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
@@ -3320,8 +3318,8 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
3320 if (!crtc->enabled) 3318 if (!crtc->enabled)
3321 return; 3319 return;
3322 3320
3323 /* use legacy palette for IGDNG */ 3321 /* use legacy palette for Ironlake */
3324 if (IS_IGDNG(dev)) 3322 if (IS_IRONLAKE(dev))
3325 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : 3323 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3326 LGC_PALETTE_B; 3324 LGC_PALETTE_B;
3327 3325
@@ -3662,18 +3660,18 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3662 fp = I915_READ((pipe == 0) ? FPA1 : FPB1); 3660 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3663 3661
3664 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 3662 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3665 if (IS_IGD(dev)) { 3663 if (IS_PINEVIEW(dev)) {
3666 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 3664 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3667 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT; 3665 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3668 } else { 3666 } else {
3669 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 3667 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3670 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 3668 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3671 } 3669 }
3672 3670
3673 if (IS_I9XX(dev)) { 3671 if (IS_I9XX(dev)) {
3674 if (IS_IGD(dev)) 3672 if (IS_PINEVIEW(dev))
3675 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >> 3673 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3676 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD); 3674 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3677 else 3675 else
3678 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 3676 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3679 DPLL_FPA01_P1_POST_DIV_SHIFT); 3677 DPLL_FPA01_P1_POST_DIV_SHIFT);
@@ -3785,7 +3783,7 @@ void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3785{ 3783{
3786 drm_i915_private_t *dev_priv = dev->dev_private; 3784 drm_i915_private_t *dev_priv = dev->dev_private;
3787 3785
3788 if (IS_IGDNG(dev)) 3786 if (IS_IRONLAKE(dev))
3789 return; 3787 return;
3790 3788
3791 if (!dev_priv->render_reclock_avail) { 3789 if (!dev_priv->render_reclock_avail) {
@@ -3810,7 +3808,7 @@ void intel_decrease_renderclock(struct drm_device *dev)
3810{ 3808{
3811 drm_i915_private_t *dev_priv = dev->dev_private; 3809 drm_i915_private_t *dev_priv = dev->dev_private;
3812 3810
3813 if (IS_IGDNG(dev)) 3811 if (IS_IRONLAKE(dev))
3814 return; 3812 return;
3815 3813
3816 if (!dev_priv->render_reclock_avail) { 3814 if (!dev_priv->render_reclock_avail) {
@@ -3882,7 +3880,7 @@ void intel_decrease_renderclock(struct drm_device *dev)
3882 */ 3880 */
3883void intel_decrease_displayclock(struct drm_device *dev) 3881void intel_decrease_displayclock(struct drm_device *dev)
3884{ 3882{
3885 if (IS_IGDNG(dev)) 3883 if (IS_IRONLAKE(dev))
3886 return; 3884 return;
3887 3885
3888 if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) || 3886 if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
@@ -3924,7 +3922,7 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3924 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 3922 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3925 int dpll = I915_READ(dpll_reg); 3923 int dpll = I915_READ(dpll_reg);
3926 3924
3927 if (IS_IGDNG(dev)) 3925 if (IS_IRONLAKE(dev))
3928 return; 3926 return;
3929 3927
3930 if (!dev_priv->lvds_downclock_avail) 3928 if (!dev_priv->lvds_downclock_avail)
@@ -3963,7 +3961,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
3963 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 3961 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3964 int dpll = I915_READ(dpll_reg); 3962 int dpll = I915_READ(dpll_reg);
3965 3963
3966 if (IS_IGDNG(dev)) 3964 if (IS_IRONLAKE(dev))
3967 return; 3965 return;
3968 3966
3969 if (!dev_priv->lvds_downclock_avail) 3967 if (!dev_priv->lvds_downclock_avail)
@@ -4370,7 +4368,7 @@ static void intel_setup_outputs(struct drm_device *dev)
4370 if (IS_MOBILE(dev) && !IS_I830(dev)) 4368 if (IS_MOBILE(dev) && !IS_I830(dev))
4371 intel_lvds_init(dev); 4369 intel_lvds_init(dev);
4372 4370
4373 if (IS_IGDNG(dev)) { 4371 if (IS_IRONLAKE(dev)) {
4374 int found; 4372 int found;
4375 4373
4376 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED)) 4374 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
@@ -4537,7 +4535,7 @@ void intel_init_clock_gating(struct drm_device *dev)
4537 * Disable clock gating reported to work incorrectly according to the 4535 * Disable clock gating reported to work incorrectly according to the
4538 * specs, but enable as much else as we can. 4536 * specs, but enable as much else as we can.
4539 */ 4537 */
4540 if (IS_IGDNG(dev)) { 4538 if (IS_IRONLAKE(dev)) {
4541 return; 4539 return;
4542 } else if (IS_G4X(dev)) { 4540 } else if (IS_G4X(dev)) {
4543 uint32_t dspclk_gate; 4541 uint32_t dspclk_gate;
@@ -4620,8 +4618,8 @@ static void intel_init_display(struct drm_device *dev)
4620 struct drm_i915_private *dev_priv = dev->dev_private; 4618 struct drm_i915_private *dev_priv = dev->dev_private;
4621 4619
4622 /* We always want a DPMS function */ 4620 /* We always want a DPMS function */
4623 if (IS_IGDNG(dev)) 4621 if (IS_IRONLAKE(dev))
4624 dev_priv->display.dpms = igdng_crtc_dpms; 4622 dev_priv->display.dpms = ironlake_crtc_dpms;
4625 else 4623 else
4626 dev_priv->display.dpms = i9xx_crtc_dpms; 4624 dev_priv->display.dpms = i9xx_crtc_dpms;
4627 4625
@@ -4640,13 +4638,13 @@ static void intel_init_display(struct drm_device *dev)
4640 } 4638 }
4641 4639
4642 /* Returns the core display clock speed */ 4640 /* Returns the core display clock speed */
4643 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_IGDGM(dev))) 4641 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4644 dev_priv->display.get_display_clock_speed = 4642 dev_priv->display.get_display_clock_speed =
4645 i945_get_display_clock_speed; 4643 i945_get_display_clock_speed;
4646 else if (IS_I915G(dev)) 4644 else if (IS_I915G(dev))
4647 dev_priv->display.get_display_clock_speed = 4645 dev_priv->display.get_display_clock_speed =
4648 i915_get_display_clock_speed; 4646 i915_get_display_clock_speed;
4649 else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev)) 4647 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
4650 dev_priv->display.get_display_clock_speed = 4648 dev_priv->display.get_display_clock_speed =
4651 i9xx_misc_get_display_clock_speed; 4649 i9xx_misc_get_display_clock_speed;
4652 else if (IS_I915GM(dev)) 4650 else if (IS_I915GM(dev))
@@ -4663,7 +4661,7 @@ static void intel_init_display(struct drm_device *dev)
4663 i830_get_display_clock_speed; 4661 i830_get_display_clock_speed;
4664 4662
4665 /* For FIFO watermark updates */ 4663 /* For FIFO watermark updates */
4666 if (IS_IGDNG(dev)) 4664 if (IS_IRONLAKE(dev))
4667 dev_priv->display.update_wm = NULL; 4665 dev_priv->display.update_wm = NULL;
4668 else if (IS_G4X(dev)) 4666 else if (IS_G4X(dev))
4669 dev_priv->display.update_wm = g4x_update_wm; 4667 dev_priv->display.update_wm = g4x_update_wm;
@@ -4741,9 +4739,9 @@ void intel_modeset_init(struct drm_device *dev)
4741 4739
4742 intel_setup_overlay(dev); 4740 intel_setup_overlay(dev);
4743 4741
4744 if (IS_IGD(dev) && !intel_get_cxsr_latency(IS_IGDG(dev), 4742 if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4745 dev_priv->fsb_freq, 4743 dev_priv->fsb_freq,
4746 dev_priv->mem_freq)) 4744 dev_priv->mem_freq))
4747 DRM_INFO("failed to find known CxSR latency " 4745 DRM_INFO("failed to find known CxSR latency "
4748 "(found fsb freq %d, mem freq %d), disabling CxSR\n", 4746 "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4749 dev_priv->fsb_freq, dev_priv->mem_freq); 4747 dev_priv->fsb_freq, dev_priv->mem_freq);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 24d3bdeb9842..632f1b44c28a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -224,8 +224,8 @@ intel_dp_aux_ch(struct intel_output *intel_output,
224 */ 224 */
225 if (IS_eDP(intel_output)) 225 if (IS_eDP(intel_output))
226 aux_clock_divider = 225; /* eDP input clock at 450Mhz */ 226 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
227 else if (IS_IGDNG(dev)) 227 else if (IS_IRONLAKE(dev))
228 aux_clock_divider = 62; /* IGDNG: input clock fixed at 125Mhz */ 228 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
229 else 229 else
230 aux_clock_divider = intel_hrawclk(dev) / 2; 230 aux_clock_divider = intel_hrawclk(dev) / 2;
231 231
@@ -516,7 +516,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
516 intel_dp_compute_m_n(3, lane_count, 516 intel_dp_compute_m_n(3, lane_count,
517 mode->clock, adjusted_mode->clock, &m_n); 517 mode->clock, adjusted_mode->clock, &m_n);
518 518
519 if (IS_IGDNG(dev)) { 519 if (IS_IRONLAKE(dev)) {
520 if (intel_crtc->pipe == 0) { 520 if (intel_crtc->pipe == 0) {
521 I915_WRITE(TRANSA_DATA_M1, 521 I915_WRITE(TRANSA_DATA_M1,
522 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 522 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
@@ -608,7 +608,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
608 } 608 }
609} 609}
610 610
611static void igdng_edp_backlight_on (struct drm_device *dev) 611static void ironlake_edp_backlight_on (struct drm_device *dev)
612{ 612{
613 struct drm_i915_private *dev_priv = dev->dev_private; 613 struct drm_i915_private *dev_priv = dev->dev_private;
614 u32 pp; 614 u32 pp;
@@ -619,7 +619,7 @@ static void igdng_edp_backlight_on (struct drm_device *dev)
619 I915_WRITE(PCH_PP_CONTROL, pp); 619 I915_WRITE(PCH_PP_CONTROL, pp);
620} 620}
621 621
622static void igdng_edp_backlight_off (struct drm_device *dev) 622static void ironlake_edp_backlight_off (struct drm_device *dev)
623{ 623{
624 struct drm_i915_private *dev_priv = dev->dev_private; 624 struct drm_i915_private *dev_priv = dev->dev_private;
625 u32 pp; 625 u32 pp;
@@ -643,13 +643,13 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
643 if (dp_reg & DP_PORT_EN) { 643 if (dp_reg & DP_PORT_EN) {
644 intel_dp_link_down(intel_output, dp_priv->DP); 644 intel_dp_link_down(intel_output, dp_priv->DP);
645 if (IS_eDP(intel_output)) 645 if (IS_eDP(intel_output))
646 igdng_edp_backlight_off(dev); 646 ironlake_edp_backlight_off(dev);
647 } 647 }
648 } else { 648 } else {
649 if (!(dp_reg & DP_PORT_EN)) { 649 if (!(dp_reg & DP_PORT_EN)) {
650 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration); 650 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
651 if (IS_eDP(intel_output)) 651 if (IS_eDP(intel_output))
652 igdng_edp_backlight_on(dev); 652 ironlake_edp_backlight_on(dev);
653 } 653 }
654 } 654 }
655 dp_priv->dpms_mode = mode; 655 dp_priv->dpms_mode = mode;
@@ -1073,7 +1073,7 @@ intel_dp_check_link_status(struct intel_output *intel_output)
1073} 1073}
1074 1074
1075static enum drm_connector_status 1075static enum drm_connector_status
1076igdng_dp_detect(struct drm_connector *connector) 1076ironlake_dp_detect(struct drm_connector *connector)
1077{ 1077{
1078 struct intel_output *intel_output = to_intel_output(connector); 1078 struct intel_output *intel_output = to_intel_output(connector);
1079 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 1079 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
@@ -1108,8 +1108,8 @@ intel_dp_detect(struct drm_connector *connector)
1108 1108
1109 dp_priv->has_audio = false; 1109 dp_priv->has_audio = false;
1110 1110
1111 if (IS_IGDNG(dev)) 1111 if (IS_IRONLAKE(dev))
1112 return igdng_dp_detect(connector); 1112 return ironlake_dp_detect(connector);
1113 1113
1114 temp = I915_READ(PORT_HOTPLUG_EN); 1114 temp = I915_READ(PORT_HOTPLUG_EN);
1115 1115
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 7c5c6af23eaf..f04dbbe7d400 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -82,7 +82,7 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
82 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 82 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
83 * we do this anyway which shows more stable in testing. 83 * we do this anyway which shows more stable in testing.
84 */ 84 */
85 if (IS_IGDNG(dev)) { 85 if (IS_IRONLAKE(dev)) {
86 I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE); 86 I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE);
87 POSTING_READ(hdmi_priv->sdvox_reg); 87 POSTING_READ(hdmi_priv->sdvox_reg);
88 } 88 }
@@ -99,7 +99,7 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
99 /* HW workaround, need to write this twice for issue that may result 99 /* HW workaround, need to write this twice for issue that may result
100 * in first write getting masked. 100 * in first write getting masked.
101 */ 101 */
102 if (IS_IGDNG(dev)) { 102 if (IS_IRONLAKE(dev)) {
103 I915_WRITE(hdmi_priv->sdvox_reg, temp); 103 I915_WRITE(hdmi_priv->sdvox_reg, temp);
104 POSTING_READ(hdmi_priv->sdvox_reg); 104 POSTING_READ(hdmi_priv->sdvox_reg);
105 } 105 }
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index b94acc4cc05f..8673c735b8ab 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -39,7 +39,7 @@ void intel_i2c_quirk_set(struct drm_device *dev, bool enable)
39 struct drm_i915_private *dev_priv = dev->dev_private; 39 struct drm_i915_private *dev_priv = dev->dev_private;
40 40
41 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 41 /* When using bit bashing for I2C, this bit needs to be set to 1 */
42 if (!IS_IGD(dev)) 42 if (!IS_PINEVIEW(dev))
43 return; 43 return;
44 if (enable) 44 if (enable)
45 I915_WRITE(DSPCLK_GATE_D, 45 I915_WRITE(DSPCLK_GATE_D,
@@ -128,7 +128,7 @@ intel_i2c_reset_gmbus(struct drm_device *dev)
128{ 128{
129 struct drm_i915_private *dev_priv = dev->dev_private; 129 struct drm_i915_private *dev_priv = dev->dev_private;
130 130
131 if (IS_IGDNG(dev)) { 131 if (IS_IRONLAKE(dev)) {
132 I915_WRITE(PCH_GMBUS0, 0); 132 I915_WRITE(PCH_GMBUS0, 0);
133 } else { 133 } else {
134 I915_WRITE(GMBUS0, 0); 134 I915_WRITE(GMBUS0, 0);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 70763cc353eb..b04d1e63d439 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -56,7 +56,7 @@ static void intel_lvds_set_backlight(struct drm_device *dev, int level)
56 struct drm_i915_private *dev_priv = dev->dev_private; 56 struct drm_i915_private *dev_priv = dev->dev_private;
57 u32 blc_pwm_ctl, reg; 57 u32 blc_pwm_ctl, reg;
58 58
59 if (IS_IGDNG(dev)) 59 if (IS_IRONLAKE(dev))
60 reg = BLC_PWM_CPU_CTL; 60 reg = BLC_PWM_CPU_CTL;
61 else 61 else
62 reg = BLC_PWM_CTL; 62 reg = BLC_PWM_CTL;
@@ -74,7 +74,7 @@ static u32 intel_lvds_get_max_backlight(struct drm_device *dev)
74 struct drm_i915_private *dev_priv = dev->dev_private; 74 struct drm_i915_private *dev_priv = dev->dev_private;
75 u32 reg; 75 u32 reg;
76 76
77 if (IS_IGDNG(dev)) 77 if (IS_IRONLAKE(dev))
78 reg = BLC_PWM_PCH_CTL2; 78 reg = BLC_PWM_PCH_CTL2;
79 else 79 else
80 reg = BLC_PWM_CTL; 80 reg = BLC_PWM_CTL;
@@ -91,7 +91,7 @@ static void intel_lvds_set_power(struct drm_device *dev, bool on)
91 struct drm_i915_private *dev_priv = dev->dev_private; 91 struct drm_i915_private *dev_priv = dev->dev_private;
92 u32 pp_status, ctl_reg, status_reg; 92 u32 pp_status, ctl_reg, status_reg;
93 93
94 if (IS_IGDNG(dev)) { 94 if (IS_IRONLAKE(dev)) {
95 ctl_reg = PCH_PP_CONTROL; 95 ctl_reg = PCH_PP_CONTROL;
96 status_reg = PCH_PP_STATUS; 96 status_reg = PCH_PP_STATUS;
97 } else { 97 } else {
@@ -137,7 +137,7 @@ static void intel_lvds_save(struct drm_connector *connector)
137 u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg; 137 u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg;
138 u32 pwm_ctl_reg; 138 u32 pwm_ctl_reg;
139 139
140 if (IS_IGDNG(dev)) { 140 if (IS_IRONLAKE(dev)) {
141 pp_on_reg = PCH_PP_ON_DELAYS; 141 pp_on_reg = PCH_PP_ON_DELAYS;
142 pp_off_reg = PCH_PP_OFF_DELAYS; 142 pp_off_reg = PCH_PP_OFF_DELAYS;
143 pp_ctl_reg = PCH_PP_CONTROL; 143 pp_ctl_reg = PCH_PP_CONTROL;
@@ -174,7 +174,7 @@ static void intel_lvds_restore(struct drm_connector *connector)
174 u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg; 174 u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg;
175 u32 pwm_ctl_reg; 175 u32 pwm_ctl_reg;
176 176
177 if (IS_IGDNG(dev)) { 177 if (IS_IRONLAKE(dev)) {
178 pp_on_reg = PCH_PP_ON_DELAYS; 178 pp_on_reg = PCH_PP_ON_DELAYS;
179 pp_off_reg = PCH_PP_OFF_DELAYS; 179 pp_off_reg = PCH_PP_OFF_DELAYS;
180 pp_ctl_reg = PCH_PP_CONTROL; 180 pp_ctl_reg = PCH_PP_CONTROL;
@@ -297,7 +297,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
297 } 297 }
298 298
299 /* full screen scale for now */ 299 /* full screen scale for now */
300 if (IS_IGDNG(dev)) 300 if (IS_IRONLAKE(dev))
301 goto out; 301 goto out;
302 302
303 /* 965+ wants fuzzy fitting */ 303 /* 965+ wants fuzzy fitting */
@@ -327,7 +327,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
327 * to register description and PRM. 327 * to register description and PRM.
328 * Change the value here to see the borders for debugging 328 * Change the value here to see the borders for debugging
329 */ 329 */
330 if (!IS_IGDNG(dev)) { 330 if (!IS_IRONLAKE(dev)) {
331 I915_WRITE(BCLRPAT_A, 0); 331 I915_WRITE(BCLRPAT_A, 0);
332 I915_WRITE(BCLRPAT_B, 0); 332 I915_WRITE(BCLRPAT_B, 0);
333 } 333 }
@@ -548,7 +548,7 @@ static void intel_lvds_prepare(struct drm_encoder *encoder)
548 struct drm_i915_private *dev_priv = dev->dev_private; 548 struct drm_i915_private *dev_priv = dev->dev_private;
549 u32 reg; 549 u32 reg;
550 550
551 if (IS_IGDNG(dev)) 551 if (IS_IRONLAKE(dev))
552 reg = BLC_PWM_CPU_CTL; 552 reg = BLC_PWM_CPU_CTL;
553 else 553 else
554 reg = BLC_PWM_CTL; 554 reg = BLC_PWM_CTL;
@@ -587,7 +587,7 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
587 * settings. 587 * settings.
588 */ 588 */
589 589
590 if (IS_IGDNG(dev)) 590 if (IS_IRONLAKE(dev))
591 return; 591 return;
592 592
593 /* 593 /*
@@ -1040,7 +1040,7 @@ void intel_lvds_init(struct drm_device *dev)
1040 return; 1040 return;
1041 } 1041 }
1042 1042
1043 if (IS_IGDNG(dev)) { 1043 if (IS_IRONLAKE(dev)) {
1044 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) 1044 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
1045 return; 1045 return;
1046 if (dev_priv->edp_support) { 1046 if (dev_priv->edp_support) {
@@ -1142,8 +1142,8 @@ void intel_lvds_init(struct drm_device *dev)
1142 * correct mode. 1142 * correct mode.
1143 */ 1143 */
1144 1144
1145 /* IGDNG: FIXME if still fail, not try pipe mode now */ 1145 /* Ironlake: FIXME if still fail, not try pipe mode now */
1146 if (IS_IGDNG(dev)) 1146 if (IS_IRONLAKE(dev))
1147 goto failed; 1147 goto failed;
1148 1148
1149 lvds = I915_READ(LVDS); 1149 lvds = I915_READ(LVDS);
@@ -1164,7 +1164,7 @@ void intel_lvds_init(struct drm_device *dev)
1164 goto failed; 1164 goto failed;
1165 1165
1166out: 1166out:
1167 if (IS_IGDNG(dev)) { 1167 if (IS_IRONLAKE(dev)) {
1168 u32 pwm; 1168 u32 pwm;
1169 /* make sure PWM is enabled */ 1169 /* make sure PWM is enabled */
1170 pwm = I915_READ(BLC_PWM_CPU_CTL2); 1170 pwm = I915_READ(BLC_PWM_CPU_CTL2);
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 49110b3aab6a..2639591c72e9 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -172,7 +172,7 @@ struct overlay_registers {
172#define OFC_UPDATE 0x1 172#define OFC_UPDATE 0x1
173 173
174#define OVERLAY_NONPHYSICAL(dev) (IS_G33(dev) || IS_I965G(dev)) 174#define OVERLAY_NONPHYSICAL(dev) (IS_G33(dev) || IS_I965G(dev))
175#define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IGDNG(dev)) 175#define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IRONLAKE(dev))
176 176
177 177
178static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_overlay *overlay) 178static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 04:10:40 -0500