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authorPaul Mundt <lethal@linux-sh.org>2006-09-27 04:38:11 -0400
committerPaul Mundt <lethal@linux-sh.org>2006-09-27 04:38:11 -0400
commite5723e0eeb2dc16629e86d66785024ead9169000 (patch)
tree7fe39cdaf3106cc726d3b84fdc998b382b6c5e22
parentecd9561687a0952a96a0a705f618e59cb6f3189b (diff)
sh: Add support for SH7706/SH7710/SH7343 CPUs.
This adds support for the aforementioned CPU subtypes, and cleans up some build issues encountered as a result. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat
-rw-r--r--arch/sh/Kconfig12
-rw-r--r--arch/sh/Makefile7
-rw-r--r--arch/sh/boards/hp6xx/setup.c5
-rw-r--r--arch/sh/boards/renesas/hs7751rvoip/io.c2
-rw-r--r--arch/sh/kernel/cpu/irq/ipr.c2
-rw-r--r--arch/sh/kernel/cpu/sh3/Makefile5
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7706.c84
-rw-r--r--arch/sh/kernel/cpu/sh3/ex.S54
-rw-r--r--arch/sh/kernel/cpu/sh3/probe.c6
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c43
-rw-r--r--arch/sh/kernel/cpu/sh4/Makefile1
-rw-r--r--arch/sh/kernel/cpu/sh4/ex.S12
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c17
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7343.c43
-rw-r--r--arch/sh/kernel/process.c2
-rw-r--r--arch/sh/kernel/setup.c31
-rw-r--r--arch/sh/kernel/sh_ksyms.c3
-rw-r--r--arch/sh/mm/Kconfig30
-rw-r--r--include/asm-sh/cpu-sh3/cache.h4
-rw-r--r--include/asm-sh/cpu-sh3/mmu_context.h8
-rw-r--r--include/asm-sh/cpu-sh3/timer.h1
-rw-r--r--include/asm-sh/cpu-sh3/ubc.h15
-rw-r--r--include/asm-sh/irq-sh73180.h2
-rw-r--r--include/asm-sh/irq-sh7343.h317
-rw-r--r--include/asm-sh/irq.h119
-rw-r--r--include/asm-sh/processor.h8
26 files changed, 767 insertions, 66 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 035df7fb2237..557e7232141c 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -324,12 +324,11 @@ config SH_FPU_EMU
324 324
325config SH_DSP 325config SH_DSP
326 bool "DSP support" 326 bool "DSP support"
327 depends on !CPU_SH4 327 default y if SH4AL_DSP || !CPU_SH4
328 default y 328 default n
329 help 329 help
330 Selecting this option will enable support for SH processors that 330 Selecting this option will enable support for SH processors that
331 have DSP units (ie, SH2-DSP and SH3-DSP). It is safe to say Y here 331 have DSP units (ie, SH2-DSP, SH3-DSP, and SH4AL-DSP).
332 by default, as the existance of the DSP will be probed at runtime.
333 332
334 This option must be set in order to enable the DSP. 333 This option must be set in order to enable the DSP.
335 334
@@ -393,8 +392,9 @@ config SH_PCLK_FREQ
393 int "Peripheral clock frequency (in Hz)" 392 int "Peripheral clock frequency (in Hz)"
394 default "50000000" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7780 393 default "50000000" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7780
395 default "60000000" if CPU_SUBTYPE_SH7751 394 default "60000000" if CPU_SUBTYPE_SH7751
396 default "33333333" if CPU_SUBTYPE_SH7300 || CPU_SUBTYPE_SH7770 || CPU_SUBTYPE_SH7760 395 default "33333333" if CPU_SUBTYPE_SH7300 || CPU_SUBTYPE_SH7770 || \
397 default "27000000" if CPU_SUBTYPE_SH73180 396 CPU_SUBTYPE_SH7760
397 default "27000000" if CPU_SUBTYPE_SH73180 || CPU_SUBTYPE_SH7343
398 default "66000000" if CPU_SUBTYPE_SH4_202 398 default "66000000" if CPU_SUBTYPE_SH4_202
399 help 399 help
400 This option is used to specify the peripheral clock frequency. 400 This option is used to specify the peripheral clock frequency.
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index 13b688b13e1c..d118e48ea1ba 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -18,11 +18,13 @@ cflags-y := -mb
18cflags-$(CONFIG_CPU_LITTLE_ENDIAN) := -ml 18cflags-$(CONFIG_CPU_LITTLE_ENDIAN) := -ml
19 19
20isa-y := any 20isa-y := any
21isa-$(CONFIG_SH_DSP) := sh
21isa-$(CONFIG_CPU_SH2) := sh2 22isa-$(CONFIG_CPU_SH2) := sh2
23isa-$(CONFIG_CPU_SH2A) := sh2a
22isa-$(CONFIG_CPU_SH3) := sh3 24isa-$(CONFIG_CPU_SH3) := sh3
23isa-$(CONFIG_CPU_SH4) := sh4 25isa-$(CONFIG_CPU_SH4) := sh4
24isa-$(CONFIG_CPU_SH4A) := sh4a 26isa-$(CONFIG_CPU_SH4A) := sh4a
25isa-$(CONFIG_CPU_SH2A) := sh2a 27isa-$(CONFIG_CPU_SH4AL_DSP) := sh4al
26 28
27isa-$(CONFIG_SH_DSP) := $(isa-y)-dsp 29isa-$(CONFIG_SH_DSP) := $(isa-y)-dsp
28 30
@@ -30,9 +32,11 @@ ifndef CONFIG_MMU
30isa-y := $(isa-y)-nommu 32isa-y := $(isa-y)-nommu
31endif 33endif
32 34
35ifndef CONFIG_SH_DSP
33ifndef CONFIG_SH_FPU 36ifndef CONFIG_SH_FPU
34isa-y := $(isa-y)-nofpu 37isa-y := $(isa-y)-nofpu
35endif 38endif
39endif
36 40
37cflags-y += $(call as-option,-Wa$(comma)-isa=$(isa-y),) 41cflags-y += $(call as-option,-Wa$(comma)-isa=$(isa-y),)
38 42
@@ -188,4 +192,3 @@ CLEAN_FILES += include/asm-sh/machtypes.h
188define archhelp 192define archhelp
189 @echo ' zImage - Compressed kernel image (arch/sh/boot/zImage)' 193 @echo ' zImage - Compressed kernel image (arch/sh/boot/zImage)'
190endef 194endef
191
diff --git a/arch/sh/boards/hp6xx/setup.c b/arch/sh/boards/hp6xx/setup.c
index 5fc00f0727c4..629016bec809 100644
--- a/arch/sh/boards/hp6xx/setup.c
+++ b/arch/sh/boards/hp6xx/setup.c
@@ -8,10 +8,11 @@
8 * 8 *
9 * Setup code for an HP680 (internal peripherials only) 9 * Setup code for an HP680 (internal peripherials only)
10 */ 10 */
11 11#include <linux/types.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/io.h>
14#include <asm/hd64461.h> 13#include <asm/hd64461.h>
14#include <asm/io.h>
15#include <asm/irq.h>
15#include <asm/hp6xx/hp6xx.h> 16#include <asm/hp6xx/hp6xx.h>
16#include <asm/cpu/dac.h> 17#include <asm/cpu/dac.h>
17 18
diff --git a/arch/sh/boards/renesas/hs7751rvoip/io.c b/arch/sh/boards/renesas/hs7751rvoip/io.c
index 8c26550ca2e4..9ea1136b219b 100644
--- a/arch/sh/boards/renesas/hs7751rvoip/io.c
+++ b/arch/sh/boards/renesas/hs7751rvoip/io.c
@@ -10,10 +10,10 @@
10 * placeholder code from io_hs7751rvoip.c left in with the 10 * placeholder code from io_hs7751rvoip.c left in with the
11 * expectation of later SuperIO and PCMCIA access. 11 * expectation of later SuperIO and PCMCIA access.
12 */ 12 */
13
14#include <linux/kernel.h> 13#include <linux/kernel.h>
15#include <linux/types.h> 14#include <linux/types.h>
16#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/pci.h>
17#include <asm/io.h> 17#include <asm/io.h>
18#include <asm/hs7751rvoip/hs7751rvoip.h> 18#include <asm/hs7751rvoip/hs7751rvoip.h>
19#include <asm/addrspace.h> 19#include <asm/addrspace.h>
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 0f545941fb4f..d2b715a04c7e 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -89,6 +89,7 @@ static void mask_and_ack_ipr(unsigned int irq)
89 disable_ipr_irq(irq); 89 disable_ipr_irq(irq);
90 90
91#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 91#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
92 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
92 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 93 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
93 /* This is needed when we use edge triggered setting */ 94 /* This is needed when we use edge triggered setting */
94 /* XXX: Is it really needed? */ 95 /* XXX: Is it really needed? */
@@ -162,6 +163,7 @@ void __init init_IRQ(void)
162#endif 163#endif
163 164
164#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 165#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
166 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
165 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 167 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
166 /* 168 /*
167 * Initialize the Interrupt Controller (INTC) 169 * Initialize the Interrupt Controller (INTC)
diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile
index 1b292ae16f07..58d3815695ff 100644
--- a/arch/sh/kernel/cpu/sh3/Makefile
+++ b/arch/sh/kernel/cpu/sh3/Makefile
@@ -6,16 +6,19 @@ obj-y := ex.o probe.o
6 6
7# CPU subtype setup 7# CPU subtype setup
8obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o 8obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7706) += setup-sh7709.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7707) += setup-sh7709.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7707) += setup-sh7709.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7708) += setup-sh7708.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7708) += setup-sh7708.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh7709.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh7709.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7300) += setup-sh7300.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7300) += setup-sh7300.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o
13 15
14# Primary on-chip clocks (common) 16# Primary on-chip clocks (common)
15clock-$(CONFIG_CPU_SH3) := clock-sh3.o 17clock-$(CONFIG_CPU_SH3) := clock-sh3.o
16clock-$(CONFIG_CPU_SUBTYPE_SH7300) := clock-sh7300.o 18clock-$(CONFIG_CPU_SUBTYPE_SH7300) := clock-sh7300.o
17clock-$(CONFIG_CPU_SUBTYPE_SH7705) := clock-sh7705.o 19clock-$(CONFIG_CPU_SUBTYPE_SH7705) := clock-sh7705.o
20clock-$(CONFIG_CPU_SUBTYPE_SH7706) := clock-sh7706.o
18clock-$(CONFIG_CPU_SUBTYPE_SH7709) := clock-sh7709.o 21clock-$(CONFIG_CPU_SUBTYPE_SH7709) := clock-sh7709.o
22clock-$(CONFIG_CPU_SUBTYPE_SH7710) := clock-sh7300.o
19 23
20obj-y += $(clock-y) 24obj-y += $(clock-y)
21
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7706.c b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
new file mode 100644
index 000000000000..0cf96f9833bc
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
@@ -0,0 +1,84 @@
1/*
2 * arch/sh/kernel/cpu/sh3/clock-sh7706.c
3 *
4 * SH7706 support for the clock framework
5 *
6 * Copyright (C) 2006 Takashi YOSHII
7 *
8 * Based on arch/sh/kernel/cpu/sh3/clock-sh7709.c
9 * Copyright (C) 2005 Andriy Skulysh
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <asm/clock.h>
18#include <asm/freq.h>
19#include <asm/io.h>
20
21static int stc_multipliers[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
22static int ifc_divisors[] = { 1, 2, 4, 1, 3, 1, 1, 1 };
23static int pfc_divisors[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
24
25static void master_clk_init(struct clk *clk)
26{
27 int frqcr = ctrl_inw(FRQCR);
28 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
29
30 clk->rate *= pfc_divisors[idx];
31}
32
33static struct clk_ops sh7706_master_clk_ops = {
34 .init = master_clk_init,
35};
36
37static void module_clk_recalc(struct clk *clk)
38{
39 int frqcr = ctrl_inw(FRQCR);
40 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
41
42 clk->rate = clk->parent->rate / pfc_divisors[idx];
43}
44
45static struct clk_ops sh7706_module_clk_ops = {
46 .recalc = module_clk_recalc,
47};
48
49static void bus_clk_recalc(struct clk *clk)
50{
51 int frqcr = ctrl_inw(FRQCR);
52 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
53
54 clk->rate = clk->parent->rate / stc_multipliers[idx];
55}
56
57static struct clk_ops sh7706_bus_clk_ops = {
58 .recalc = bus_clk_recalc,
59};
60
61static void cpu_clk_recalc(struct clk *clk)
62{
63 int frqcr = ctrl_inw(FRQCR);
64 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
65
66 clk->rate = clk->parent->rate / ifc_divisors[idx];
67}
68
69static struct clk_ops sh7706_cpu_clk_ops = {
70 .recalc = cpu_clk_recalc,
71};
72
73static struct clk_ops *sh7706_clk_ops[] = {
74 &sh7706_master_clk_ops,
75 &sh7706_module_clk_ops,
76 &sh7706_bus_clk_ops,
77 &sh7706_cpu_clk_ops,
78};
79
80void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
81{
82 if (idx < ARRAY_SIZE(sh7706_clk_ops))
83 *ops = sh7706_clk_ops[idx];
84}
diff --git a/arch/sh/kernel/cpu/sh3/ex.S b/arch/sh/kernel/cpu/sh3/ex.S
index cc04e9e239ff..44daf44833f9 100644
--- a/arch/sh/kernel/cpu/sh3/ex.S
+++ b/arch/sh/kernel/cpu/sh3/ex.S
@@ -84,8 +84,12 @@ ENTRY(interrupt_table)
84 .long do_IRQ ! rovi 84 .long do_IRQ ! rovi
85 .long do_IRQ 85 .long do_IRQ
86 .long do_IRQ /* 5E0 */ 86 .long do_IRQ /* 5E0 */
87#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 87#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
88 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 88 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
89 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
90 defined(CONFIG_CPU_SUBTYPE_SH7300) || \
91 defined(CONFIG_CPU_SUBTYPE_SH7705) || \
92 defined(CONFIG_CPU_SUBTYPE_SH7710)
89 .long do_IRQ ! 32 IRQ irq0 /* 600 */ 93 .long do_IRQ ! 32 IRQ irq0 /* 600 */
90 .long do_IRQ ! 33 irq1 94 .long do_IRQ ! 33 irq1
91 .long do_IRQ ! 34 irq2 95 .long do_IRQ ! 34 irq2
@@ -147,6 +151,51 @@ ENTRY(interrupt_table)
147 .long do_IRQ ! 62 PCC pcc0i 151 .long do_IRQ ! 62 PCC pcc0i
148 .long do_IRQ ! 63 pcc1i /* 9E0 */ 152 .long do_IRQ ! 63 pcc1i /* 9E0 */
149#endif 153#endif
154#if defined(CONFIG_CPU_SUBTYPE_SH7710)
155 .long exception_none ! 61 /* 9A0 */
156 .long exception_none ! 62
157 .long exception_none ! 63
158 .long exception_none ! 64 /* A00 */
159 .long exception_none ! 65
160 .long exception_none ! 66
161 .long exception_none ! 67
162 .long exception_none ! 68
163 .long exception_none ! 69
164 .long exception_none ! 70
165 .long exception_none ! 71
166 .long exception_none ! 72 /* B00 */
167 .long exception_none ! 73
168 .long exception_none ! 74
169 .long exception_none ! 75
170 .long do_IRQ ! 76 DMAC2 dei4 /* B80 */
171 .long do_IRQ ! 77 DMAC2 dei5
172 .long exception_none ! 78
173 .long do_IRQ ! 79 IPSEC ipseci /* BE0 */
174 .long do_IRQ ! 80 EDMAC eint0 /* C00 */
175 .long do_IRQ ! 81 EDMAC eint1
176 .long do_IRQ ! 82 EDMAC eint2
177 .long exception_none ! 83 /* C60 */
178 .long exception_none ! 84
179 .long exception_none ! 85
180 .long exception_none ! 86
181 .long exception_none ! 87
182 .long exception_none ! 88 /* D00 */
183 .long exception_none ! 89
184 .long exception_none ! 90
185 .long exception_none ! 91
186 .long exception_none ! 92
187 .long exception_none ! 93
188 .long exception_none ! 94
189 .long exception_none ! 95
190 .long do_IRQ ! 96 SIOF eri0 /* E00 */
191 .long do_IRQ ! 97 txi0
192 .long do_IRQ ! 98 rxi0
193 .long do_IRQ ! 99 cci0
194 .long do_IRQ ! 100 eri1 /* E80 */
195 .long do_IRQ ! 101 txi1
196 .long do_IRQ ! 102 rxi2
197 .long do_IRQ ! 103 cci3
198#endif
150#if defined(CONFIG_CPU_SUBTYPE_SH7300) 199#if defined(CONFIG_CPU_SUBTYPE_SH7300)
151 .long do_IRQ ! 64 200 .long do_IRQ ! 64
152 .long do_IRQ ! 65 201 .long do_IRQ ! 65
@@ -195,4 +244,3 @@ ENTRY(interrupt_table)
195 .long do_IRQ ! 108 244 .long do_IRQ ! 108
196#endif 245#endif
197#endif 246#endif
198
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index 5cdc88638601..e67098836290 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -72,6 +72,12 @@ int __init detect_cpu_and_cache_system(void)
72 cpu_data->dcache.sets = 256; 72 cpu_data->dcache.sets = 256;
73 cpu_data->type = CPU_SH7729; 73 cpu_data->type = CPU_SH7729;
74 74
75#if defined(CONFIG_CPU_SUBTYPE_SH7706)
76 cpu_data->type = CPU_SH7706;
77#endif
78#if defined(CONFIG_CPU_SUBTYPE_SH7710)
79 cpu_data->type = CPU_SH7710;
80#endif
75#if defined(CONFIG_CPU_SUBTYPE_SH7705) 81#if defined(CONFIG_CPU_SUBTYPE_SH7705)
76 cpu_data->type = CPU_SH7705; 82 cpu_data->type = CPU_SH7705;
77 83
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
new file mode 100644
index 000000000000..895f99ee6a95
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -0,0 +1,43 @@
1/*
2 * SH7710 Setup
3 *
4 * Copyright (C) 2006 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/platform_device.h>
11#include <linux/init.h>
12#include <linux/serial.h>
13#include <asm/sci.h>
14
15static struct plat_sci_port sci_platform_data[] = {
16 {
17 .mapbase = 0xa4400000,
18 .flags = UPF_BOOT_AUTOCONF,
19 .type = PORT_SCIF,
20 .irqs = { 52, 53, 55, 54 },
21 }, {
22 .flags = 0,
23 }
24};
25
26static struct platform_device sci_device = {
27 .name = "sh-sci",
28 .id = -1,
29 .dev = {
30 .platform_data = sci_platform_data,
31 },
32};
33
34static struct platform_device *sh7710_devices[] __initdata = {
35 &sci_device,
36};
37
38static int __init sh7710_devices_setup(void)
39{
40 return platform_add_devices(sh7710_devices,
41 ARRAY_SIZE(sh7710_devices));
42}
43__initcall(sh7710_devices_setup);
diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile
index 48946d54a2cd..8dbf3895ece7 100644
--- a/arch/sh/kernel/cpu/sh4/Makefile
+++ b/arch/sh/kernel/cpu/sh4/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7760) += setup-sh7760.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o 14obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
15obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
16obj-$(CONFIG_CPU_SUBTYPE_SH73180) += setup-sh73180.o 16obj-$(CONFIG_CPU_SUBTYPE_SH73180) += setup-sh73180.o
17obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
17obj-$(CONFIG_CPU_SUBTYPE_SH4_202) += setup-sh4-202.o 18obj-$(CONFIG_CPU_SUBTYPE_SH4_202) += setup-sh4-202.o
18 19
19# Primary on-chip clocks (common) 20# Primary on-chip clocks (common)
diff --git a/arch/sh/kernel/cpu/sh4/ex.S b/arch/sh/kernel/cpu/sh4/ex.S
index af5ecbddea55..7146893a6cca 100644
--- a/arch/sh/kernel/cpu/sh4/ex.S
+++ b/arch/sh/kernel/cpu/sh4/ex.S
@@ -123,6 +123,13 @@ ENTRY(interrupt_table)
123 .long do_IRQ ! 45 dmte5 123 .long do_IRQ ! 45 dmte5
124 .long do_IRQ ! 46 dmte6 124 .long do_IRQ ! 46 dmte6
125 .long do_IRQ ! 47 dmte7 /* 7E0 */ 125 .long do_IRQ ! 47 dmte7 /* 7E0 */
126#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
127 .long do_IRQ ! 44 IIC1 ali /* 780 */
128 .long do_IRQ ! 45 tacki
129 .long do_IRQ ! 46 waiti
130 .long do_IRQ ! 47 dtei /* 7E0 */
131 .long do_IRQ ! 48 DMAC dei0 /* 800 */
132 .long do_IRQ ! 49 dei1 /* 820 */
126#else 133#else
127 .long exception_error ! 44 /* 780 */ 134 .long exception_error ! 44 /* 780 */
128 .long exception_error ! 45 135 .long exception_error ! 45
@@ -132,7 +139,8 @@ ENTRY(interrupt_table)
132#if defined(CONFIG_SH_FPU) 139#if defined(CONFIG_SH_FPU)
133 .long do_fpu_state_restore ! 48 /* 800 */ 140 .long do_fpu_state_restore ! 48 /* 800 */
134 .long do_fpu_state_restore ! 49 /* 820 */ 141 .long do_fpu_state_restore ! 49 /* 820 */
135#else 142#elif !defined(CONFIG_CPU_SUBTYPE_SH7343) && \
143 !defined(CONFIG_CPU_SUBTYPE_SH73180)
136 .long exception_error 144 .long exception_error
137 .long exception_error 145 .long exception_error
138#endif 146#endif
@@ -225,7 +233,7 @@ ENTRY(interrupt_table)
225 .long exception_error 233 .long exception_error
226 .long do_IRQ ! ADC adi 234 .long do_IRQ ! ADC adi
227 .long do_IRQ ! CMT cmti /* FA0 */ 235 .long do_IRQ ! CMT cmti /* FA0 */
228#elif defined(CONFIG_CPU_SUBTYPE_SH73180) 236#elif defined(CONFIG_CPU_SUBTYPE_SH73180) || defined(CONFIG_CPU_SUBTYPE_SH7343)
229 .long do_IRQ ! 50 0x840 237 .long do_IRQ ! 50 0x840
230 .long do_IRQ ! 51 0x860 238 .long do_IRQ ! 51 0x860
231 .long do_IRQ ! 52 0x880 239 .long do_IRQ ! 52 0x880
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 2a7707a81d8f..6e8a2b5268e8 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * CPU Subtype Probing for SH-4. 4 * CPU Subtype Probing for SH-4.
5 * 5 *
6 * Copyright (C) 2001 - 2005 Paul Mundt 6 * Copyright (C) 2001 - 2006 Paul Mundt
7 * Copyright (C) 2003 Richard Curnow 7 * Copyright (C) 2003 Richard Curnow
8 * 8 *
9 * This file is subject to the terms and conditions of the GNU General Public 9 * This file is subject to the terms and conditions of the GNU General Public
@@ -76,12 +76,6 @@ int __init detect_cpu_and_cache_system(void)
76 cpu_data->type = CPU_SH73180; 76 cpu_data->type = CPU_SH73180;
77 cpu_data->icache.ways = 4; 77 cpu_data->icache.ways = 4;
78 cpu_data->dcache.ways = 4; 78 cpu_data->dcache.ways = 4;
79
80 /*
81 * XXX: Double check this, none of the SH-4A/SH-4AL processors
82 * should have this, as it's essentially a legacy thing.
83 */
84 cpu_data->flags |= CPU_HAS_PTEA;
85 break; 79 break;
86 case 0x2001: 80 case 0x2001:
87 case 0x2004: 81 case 0x2004:
@@ -89,8 +83,7 @@ int __init detect_cpu_and_cache_system(void)
89 cpu_data->icache.ways = 4; 83 cpu_data->icache.ways = 4;
90 cpu_data->dcache.ways = 4; 84 cpu_data->dcache.ways = 4;
91 85
92 /* Same note as above applies here for PTEA */ 86 cpu_data->flags |= CPU_HAS_FPU;
93 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
94 break; 87 break;
95 case 0x2006: 88 case 0x2006:
96 case 0x200A: 89 case 0x200A:
@@ -104,6 +97,12 @@ int __init detect_cpu_and_cache_system(void)
104 97
105 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER; 98 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER;
106 break; 99 break;
100 case 0x3000:
101 case 0x3003:
102 cpu_data->type = CPU_SH7343;
103 cpu_data->icache.ways = 4;
104 cpu_data->dcache.ways = 4;
105 break;
107 case 0x8000: 106 case 0x8000:
108 cpu_data->type = CPU_ST40RA; 107 cpu_data->type = CPU_ST40RA;
109 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA; 108 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7343.c b/arch/sh/kernel/cpu/sh4/setup-sh7343.c
new file mode 100644
index 000000000000..91d61cf91ba1
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7343.c
@@ -0,0 +1,43 @@
1/*
2 * SH7343 Setup
3 *
4 * Copyright (C) 2006 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/platform_device.h>
11#include <linux/init.h>
12#include <linux/serial.h>
13#include <asm/sci.h>
14
15static struct plat_sci_port sci_platform_data[] = {
16 {
17 .mapbase = 0xffe00000,
18 .flags = UPF_BOOT_AUTOCONF,
19 .type = PORT_SCIF,
20 .irqs = { 80, 81, 83, 82 },
21 }, {
22 .flags = 0,
23 }
24};
25
26static struct platform_device sci_device = {
27 .name = "sh-sci",
28 .id = -1,
29 .dev = {
30 .platform_data = sci_platform_data,
31 },
32};
33
34static struct platform_device *sh7343_devices[] __initdata = {
35 &sci_device,
36};
37
38static int __init sh7343_devices_setup(void)
39{
40 return platform_add_devices(sh7343_devices,
41 ARRAY_SIZE(sh7343_devices));
42}
43__initcall(sh7343_devices_setup);
diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c
index c4aa687ba26a..2167746e88f1 100644
--- a/arch/sh/kernel/process.c
+++ b/arch/sh/kernel/process.c
@@ -310,7 +310,7 @@ ubc_set_tracing(int asid, unsigned long pc)
310 310
311 ctrl_outl(0, UBC_BAMRA); 311 ctrl_outl(0, UBC_BAMRA);
312 312
313 if (cpu_data->type == CPU_SH7729) { 313 if (cpu_data->type == CPU_SH7729 || cpu_data->type == CPU_SH7710) {
314 ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA); 314 ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA);
315 ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR); 315 ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR);
316 } else { 316 } else {
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 4afdec071700..86ef17fe48b5 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -424,25 +424,18 @@ static int __init topology_init(void)
424subsys_initcall(topology_init); 424subsys_initcall(topology_init);
425 425
426static const char *cpu_name[] = { 426static const char *cpu_name[] = {
427 [CPU_SH7604] = "SH7604", 427 [CPU_SH7604] = "SH7604", [CPU_SH7300] = "SH7300",
428 [CPU_SH7705] = "SH7705", 428 [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
429 [CPU_SH7708] = "SH7708", 429 [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
430 [CPU_SH7729] = "SH7729", 430 [CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710",
431 [CPU_SH7300] = "SH7300", 431 [CPU_SH7729] = "SH7729", [CPU_SH7750] = "SH7750",
432 [CPU_SH7750] = "SH7750", 432 [CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R",
433 [CPU_SH7750S] = "SH7750S", 433 [CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R",
434 [CPU_SH7750R] = "SH7750R", 434 [CPU_SH7760] = "SH7760", [CPU_SH73180] = "SH73180",
435 [CPU_SH7751] = "SH7751", 435 [CPU_ST40RA] = "ST40RA", [CPU_ST40GX1] = "ST40GX1",
436 [CPU_SH7751R] = "SH7751R", 436 [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
437 [CPU_SH7760] = "SH7760", 437 [CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780",
438 [CPU_SH73180] = "SH73180", 438 [CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343",
439 [CPU_ST40RA] = "ST40RA",
440 [CPU_ST40GX1] = "ST40GX1",
441 [CPU_SH4_202] = "SH4-202",
442 [CPU_SH4_501] = "SH4-501",
443 [CPU_SH7770] = "SH7770",
444 [CPU_SH7780] = "SH7780",
445 [CPU_SH7781] = "SH7781",
446 [CPU_SH_NONE] = "Unknown" 439 [CPU_SH_NONE] = "Unknown"
447}; 440};
448 441
diff --git a/arch/sh/kernel/sh_ksyms.c b/arch/sh/kernel/sh_ksyms.c
index bf59d73415d7..d3cbfa2ad4a7 100644
--- a/arch/sh/kernel/sh_ksyms.c
+++ b/arch/sh/kernel/sh_ksyms.c
@@ -89,7 +89,8 @@ EXPORT_SYMBOL(flush_dcache_page);
89EXPORT_SYMBOL(__flush_purge_region); 89EXPORT_SYMBOL(__flush_purge_region);
90#endif 90#endif
91 91
92#ifdef CONFIG_MMU 92#if defined(CONFIG_MMU) && (defined(CONFIG_CPU_SH4) || \
93 defined(CONFIG_SH7705_CACHE_32KB))
93EXPORT_SYMBOL(clear_user_page); 94EXPORT_SYMBOL(clear_user_page);
94#endif 95#endif
95 96
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index bed697c0dc19..b445d02075e8 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -21,6 +21,10 @@ config CPU_SH4A
21 bool 21 bool
22 select CPU_SH4 22 select CPU_SH4
23 23
24config CPU_SH4AL_DSP
25 bool
26 select CPU_SH4A
27
24config CPU_SUBTYPE_ST40 28config CPU_SUBTYPE_ST40
25 bool 29 bool
26 select CPU_SH4 30 select CPU_SH4
@@ -47,6 +51,12 @@ config CPU_SUBTYPE_SH7705
47 select CPU_SH3 51 select CPU_SH3
48 select CPU_HAS_PINT_IRQ 52 select CPU_HAS_PINT_IRQ
49 53
54config CPU_SUBTYPE_SH7706
55 bool "Support SH7706 processor"
56 select CPU_SH3
57 help
58 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
59
50config CPU_SUBTYPE_SH7707 60config CPU_SUBTYPE_SH7707
51 bool "Support SH7707 processor" 61 bool "Support SH7707 processor"
52 select CPU_SH3 62 select CPU_SH3
@@ -68,6 +78,12 @@ config CPU_SUBTYPE_SH7709
68 help 78 help
69 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU. 79 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
70 80
81config CPU_SUBTYPE_SH7710
82 bool "Support SH7710 processor"
83 select CPU_SH3
84 help
85 Select SH7710 if you have a SH3-DSP SH7710 CPU.
86
71comment "SH-4 Processor Support" 87comment "SH-4 Processor Support"
72 88
73config CPU_SUBTYPE_SH7750 89config CPU_SUBTYPE_SH7750
@@ -132,10 +148,6 @@ config CPU_SUBTYPE_ST40GX1
132 148
133comment "SH-4A Processor Support" 149comment "SH-4A Processor Support"
134 150
135config CPU_SUBTYPE_SH73180
136 bool "Support SH73180 processor"
137 select CPU_SH4A
138
139config CPU_SUBTYPE_SH7770 151config CPU_SUBTYPE_SH7770
140 bool "Support SH7770 processor" 152 bool "Support SH7770 processor"
141 select CPU_SH4A 153 select CPU_SH4A
@@ -145,6 +157,16 @@ config CPU_SUBTYPE_SH7780
145 select CPU_SH4A 157 select CPU_SH4A
146 select CPU_HAS_INTC2_IRQ 158 select CPU_HAS_INTC2_IRQ
147 159
160comment "SH4AL-DSP Processor Support"
161
162config CPU_SUBTYPE_SH73180
163 bool "Support SH73180 processor"
164 select CPU_SH4AL_DSP
165
166config CPU_SUBTYPE_SH7343
167 bool "Support SH7343 processor"
168 select CPU_SH4AL_DSP
169
148endmenu 170endmenu
149 171
150menu "Memory management options" 172menu "Memory management options"
diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h
index 406aa8d9b947..ffe08d2813f9 100644
--- a/include/asm-sh/cpu-sh3/cache.h
+++ b/include/asm-sh/cpu-sh3/cache.h
@@ -26,12 +26,10 @@
26#define CCR_CACHE_ENABLE CCR_CACHE_CE 26#define CCR_CACHE_ENABLE CCR_CACHE_CE
27#define CCR_CACHE_INVALIDATE CCR_CACHE_CF 27#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
28 28
29#if defined(CONFIG_CPU_SUBTYPE_SH7705) 29#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7710)
30#define CCR3 0xa40000b4 30#define CCR3 0xa40000b4
31#define CCR_CACHE_16KB 0x00010000 31#define CCR_CACHE_16KB 0x00010000
32#define CCR_CACHE_32KB 0x00020000 32#define CCR_CACHE_32KB 0x00020000
33#endif 33#endif
34 34
35
36#endif /* __ASM_CPU_SH3_CACHE_H */ 35#endif /* __ASM_CPU_SH3_CACHE_H */
37
diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h
index a844ea0965b6..bccb7ddb438b 100644
--- a/include/asm-sh/cpu-sh3/mmu_context.h
+++ b/include/asm-sh/cpu-sh3/mmu_context.h
@@ -27,8 +27,12 @@
27#define TRA 0xffffffd0 27#define TRA 0xffffffd0
28#define EXPEVT 0xffffffd4 28#define EXPEVT 0xffffffd4
29 29
30#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 30#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 31 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7300) || \
34 defined(CONFIG_CPU_SUBTYPE_SH7705) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7710)
32#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ 36#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
33#else 37#else
34#define INTEVT 0xffffffd8 38#define INTEVT 0xffffffd8
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h
index 2082ad956f21..b2394cf76f49 100644
--- a/include/asm-sh/cpu-sh3/timer.h
+++ b/include/asm-sh/cpu-sh3/timer.h
@@ -20,6 +20,7 @@
20 * SH7710 20 * SH7710
21 * SH7720 21 * SH7720
22 * SH7300 22 * SH7300
23 * SH7710
23 * --------------------------------------------------------------------------- 24 * ---------------------------------------------------------------------------
24 */ 25 */
25 26
diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h
index 0f809dec4e17..9d308cbe9b29 100644
--- a/include/asm-sh/cpu-sh3/ubc.h
+++ b/include/asm-sh/cpu-sh3/ubc.h
@@ -11,6 +11,19 @@
11#ifndef __ASM_CPU_SH3_UBC_H 11#ifndef __ASM_CPU_SH3_UBC_H
12#define __ASM_CPU_SH3_UBC_H 12#define __ASM_CPU_SH3_UBC_H
13 13
14#if defined(CONFIG_CPU_SUBTYPE_SH7710)
15#define UBC_BARA 0xa4ffffb0
16#define UBC_BAMRA 0xa4ffffb4
17#define UBC_BBRA 0xa4ffffb8
18#define UBC_BASRA 0xffffffe4
19#define UBC_BARB 0xa4ffffa0
20#define UBC_BAMRB 0xa4ffffa4
21#define UBC_BBRB 0xa4ffffa8
22#define UBC_BASRB 0xffffffe8
23#define UBC_BDRB 0xa4ffff90
24#define UBC_BDMRB 0xa4ffff94
25#define UBC_BRCR 0xa4ffff98
26#else
14#define UBC_BARA 0xffffffb0 27#define UBC_BARA 0xffffffb0
15#define UBC_BAMRA 0xffffffb4 28#define UBC_BAMRA 0xffffffb4
16#define UBC_BBRA 0xffffffb8 29#define UBC_BBRA 0xffffffb8
@@ -22,6 +35,6 @@
22#define UBC_BDRB 0xffffff90 35#define UBC_BDRB 0xffffff90
23#define UBC_BDMRB 0xffffff94 36#define UBC_BDMRB 0xffffff94
24#define UBC_BRCR 0xffffff98 37#define UBC_BRCR 0xffffff98
38#endif
25 39
26#endif /* __ASM_CPU_SH3_UBC_H */ 40#endif /* __ASM_CPU_SH3_UBC_H */
27
diff --git a/include/asm-sh/irq-sh73180.h b/include/asm-sh/irq-sh73180.h
index d705252be260..b28af9a69d72 100644
--- a/include/asm-sh/irq-sh73180.h
+++ b/include/asm-sh/irq-sh73180.h
@@ -311,6 +311,4 @@
311#define IRQ6_PRIORITY 1 311#define IRQ6_PRIORITY 1
312#define IRQ7_PRIORITY 1 312#define IRQ7_PRIORITY 1
313 313
314int shmse_irq_demux(int irq);
315
316#endif /* __ASM_SH_IRQ_SH73180_H */ 314#endif /* __ASM_SH_IRQ_SH73180_H */
diff --git a/include/asm-sh/irq-sh7343.h b/include/asm-sh/irq-sh7343.h
new file mode 100644
index 000000000000..5d15419b53b0
--- /dev/null
+++ b/include/asm-sh/irq-sh7343.h
@@ -0,0 +1,317 @@
1#ifndef __ASM_SH_IRQ_SH7343_H
2#define __ASM_SH_IRQ_SH7343_H
3
4/*
5 * linux/include/asm-sh/irq-sh7343.h
6 *
7 * Copyright (C) 2006 Kenati Technologies Inc.
8 * Andre Mccurdy <andre@kenati.com>
9 * Ranjit Deshpande <ranjit@kenati.com>
10 */
11
12#undef INTC_IPRA
13#undef INTC_IPRB
14#undef INTC_IPRC
15#undef INTC_IPRD
16
17#undef DMTE0_IRQ
18#undef DMTE1_IRQ
19#undef DMTE2_IRQ
20#undef DMTE3_IRQ
21#undef DMTE4_IRQ
22#undef DMTE5_IRQ
23#undef DMTE6_IRQ
24#undef DMTE7_IRQ
25#undef DMAE_IRQ
26#undef DMA_IPR_ADDR
27#undef DMA_IPR_POS
28#undef DMA_PRIORITY
29
30#undef INTC_IMCR0
31#undef INTC_IMCR1
32#undef INTC_IMCR2
33#undef INTC_IMCR3
34#undef INTC_IMCR4
35#undef INTC_IMCR5
36#undef INTC_IMCR6
37#undef INTC_IMCR7
38#undef INTC_IMCR8
39#undef INTC_IMCR9
40#undef INTC_IMCR10
41
42
43#define INTC_IPRA 0xA4080000UL
44#define INTC_IPRB 0xA4080004UL
45#define INTC_IPRC 0xA4080008UL
46#define INTC_IPRD 0xA408000CUL
47#define INTC_IPRE 0xA4080010UL
48#define INTC_IPRF 0xA4080014UL
49#define INTC_IPRG 0xA4080018UL
50#define INTC_IPRH 0xA408001CUL
51#define INTC_IPRI 0xA4080020UL
52#define INTC_IPRJ 0xA4080024UL
53#define INTC_IPRK 0xA4080028UL
54#define INTC_IPRL 0xA408002CUL
55
56#define INTC_IMR0 0xA4080080UL
57#define INTC_IMR1 0xA4080084UL
58#define INTC_IMR2 0xA4080088UL
59#define INTC_IMR3 0xA408008CUL
60#define INTC_IMR4 0xA4080090UL
61#define INTC_IMR5 0xA4080094UL
62#define INTC_IMR6 0xA4080098UL
63#define INTC_IMR7 0xA408009CUL
64#define INTC_IMR8 0xA40800A0UL
65#define INTC_IMR9 0xA40800A4UL
66#define INTC_IMR10 0xA40800A8UL
67#define INTC_IMR11 0xA40800ACUL
68
69#define INTC_IMCR0 0xA40800C0UL
70#define INTC_IMCR1 0xA40800C4UL
71#define INTC_IMCR2 0xA40800C8UL
72#define INTC_IMCR3 0xA40800CCUL
73#define INTC_IMCR4 0xA40800D0UL
74#define INTC_IMCR5 0xA40800D4UL
75#define INTC_IMCR6 0xA40800D8UL
76#define INTC_IMCR7 0xA40800DCUL
77#define INTC_IMCR8 0xA40800E0UL
78#define INTC_IMCR9 0xA40800E4UL
79#define INTC_IMCR10 0xA40800E8UL
80#define INTC_IMCR11 0xA40800ECUL
81
82#define INTC_ICR0 0xA4140000UL
83#define INTC_ICR1 0xA414001CUL
84
85#define INTMSK0 0xa4140044
86#define INTMSKCLR0 0xa4140064
87#define INTC_INTPRI0 0xa4140010
88
89/*
90 NOTE:
91
92 *_IRQ = (INTEVT2 - 0x200)/0x20
93*/
94
95/* TMU0 */
96#define TMU0_IRQ 16
97#define TMU0_IPR_ADDR INTC_IPRA
98#define TMU0_IPR_POS 3
99#define TMU0_PRIORITY 2
100
101#define TIMER_IRQ 16
102#define TIMER_IPR_ADDR INTC_IPRA
103#define TIMER_IPR_POS 3
104#define TIMER_PRIORITY 2
105
106/* TMU1 */
107#define TMU1_IRQ 17
108#define TMU1_IPR_ADDR INTC_IPRA
109#define TMU1_IPR_POS 2
110#define TMU1_PRIORITY 2
111
112/* TMU2 */
113#define TMU2_IRQ 18
114#define TMU2_IPR_ADDR INTC_IPRA
115#define TMU2_IPR_POS 1
116#define TMU2_PRIORITY 2
117
118/* LCDC */
119#define LCDC_IRQ 28
120#define LCDC_IPR_ADDR INTC_IPRB
121#define LCDC_IPR_POS 2
122#define LCDC_PRIORITY 2
123
124/* VIO (Video I/O) */
125#define CEU_IRQ 52
126#define BEU_IRQ 53
127#define VEU_IRQ 54
128#define VOU_IRQ 55
129#define VIO_IPR_ADDR INTC_IPRE
130#define VIO_IPR_POS 2
131#define VIO_PRIORITY 2
132
133/* MFI (Multi Functional Interface) */
134#define MFI_IRQ 56
135#define MFI_IPR_ADDR INTC_IPRE
136#define MFI_IPR_POS 1
137#define MFI_PRIORITY 2
138
139/* VPU (Video Processing Unit) */
140#define VPU_IRQ 60
141#define VPU_IPR_ADDR INTC_IPRE
142#define VPU_IPR_POS 0
143#define VPU_PRIORITY 2
144
145/* 3DG */
146#define TDG_IRQ 63
147#define TDG_IPR_ADDR INTC_IPRJ
148#define TDG_IPR_POS 2
149#define TDG_PRIORITY 2
150
151/* DMAC(1) */
152#define DMTE0_IRQ 48
153#define DMTE1_IRQ 49
154#define DMTE2_IRQ 50
155#define DMTE3_IRQ 51
156#define DMA1_IPR_ADDR INTC_IPRE
157#define DMA1_IPR_POS 3
158#define DMA1_PRIORITY 7
159
160/* DMAC(2) */
161#define DMTE4_IRQ 76
162#define DMTE5_IRQ 77
163#define DMA2_IPR_ADDR INTC_IPRF
164#define DMA2_IPR_POS 2
165#define DMA2_PRIORITY 7
166
167/* SCIF0 */
168#define SCIF_ERI_IRQ 80
169#define SCIF_RXI_IRQ 81
170#define SCIF_BRI_IRQ 82
171#define SCIF_TXI_IRQ 83
172#define SCIF_IPR_ADDR INTC_IPRG
173#define SCIF_IPR_POS 3
174#define SCIF_PRIORITY 3
175
176/* SIOF0 */
177#define SIOF0_IRQ 84
178#define SIOF0_IPR_ADDR INTC_IPRH
179#define SIOF0_IPR_POS 3
180#define SIOF0_PRIORITY 3
181
182/* FLCTL (Flash Memory Controller) */
183#define FLSTE_IRQ 92
184#define FLTEND_IRQ 93
185#define FLTRQ0_IRQ 94
186#define FLTRQ1_IRQ 95
187#define FLCTL_IPR_ADDR INTC_IPRH
188#define FLCTL_IPR_POS 1
189#define FLCTL_PRIORITY 3
190
191/* IIC(0) (IIC Bus Interface) */
192#define IIC0_ALI_IRQ 96
193#define IIC0_TACKI_IRQ 97
194#define IIC0_WAITI_IRQ 98
195#define IIC0_DTEI_IRQ 99
196#define IIC0_IPR_ADDR INTC_IPRH
197#define IIC0_IPR_POS 0
198#define IIC0_PRIORITY 3
199
200/* IIC(1) (IIC Bus Interface) */
201#define IIC1_ALI_IRQ 44
202#define IIC1_TACKI_IRQ 45
203#define IIC1_WAITI_IRQ 46
204#define IIC1_DTEI_IRQ 47
205#define IIC1_IPR_ADDR INTC_IPRI
206#define IIC1_IPR_POS 0
207#define IIC1_PRIORITY 3
208
209/* SIO0 */
210#define SIO0_IRQ 88
211#define SIO0_IPR_ADDR INTC_IPRI
212#define SIO0_IPR_POS 3
213#define SIO0_PRIORITY 3
214
215/* SDHI */
216#define SDHI_SDHII0_IRQ 100
217#define SDHI_SDHII1_IRQ 101
218#define SDHI_SDHII2_IRQ 102
219#define SDHI_SDHII3_IRQ 103
220#define SDHI_IPR_ADDR INTC_IPRK
221#define SDHI_IPR_POS 0
222#define SDHI_PRIORITY 3
223
224/* SIU (Sound Interface Unit) */
225#define SIU_IRQ 108
226#define SIU_IPR_ADDR INTC_IPRJ
227#define SIU_IPR_POS 1
228#define SIU_PRIORITY 3
229
230#define PORT_PACR 0xA4050100UL
231#define PORT_PBCR 0xA4050102UL
232#define PORT_PCCR 0xA4050104UL
233#define PORT_PDCR 0xA4050106UL
234#define PORT_PECR 0xA4050108UL
235#define PORT_PFCR 0xA405010AUL
236#define PORT_PGCR 0xA405010CUL
237#define PORT_PHCR 0xA405010EUL
238#define PORT_PJCR 0xA4050110UL
239#define PORT_PKCR 0xA4050112UL
240#define PORT_PLCR 0xA4050114UL
241#define PORT_SCPCR 0xA4050116UL
242#define PORT_PMCR 0xA4050118UL
243#define PORT_PNCR 0xA405011AUL
244#define PORT_PQCR 0xA405011CUL
245#define PORT_PRCR 0xA405011EUL
246#define PORT_PTCR 0xA405014CUL
247#define PORT_PUCR 0xA405014EUL
248#define PORT_PVCR 0xA4050150UL
249
250#define PORT_PSELA 0xA4050140UL
251#define PORT_PSELB 0xA4050142UL
252#define PORT_PSELC 0xA4050144UL
253#define PORT_PSELE 0xA4050158UL
254
255#define PORT_HIZCRA 0xA4050146UL
256#define PORT_HIZCRB 0xA4050148UL
257#define PORT_DRVCR 0xA405014AUL
258
259#define PORT_PADR 0xA4050120UL
260#define PORT_PBDR 0xA4050122UL
261#define PORT_PCDR 0xA4050124UL
262#define PORT_PDDR 0xA4050126UL
263#define PORT_PEDR 0xA4050128UL
264#define PORT_PFDR 0xA405012AUL
265#define PORT_PGDR 0xA405012CUL
266#define PORT_PHDR 0xA405012EUL
267#define PORT_PJDR 0xA4050130UL
268#define PORT_PKDR 0xA4050132UL
269#define PORT_PLDR 0xA4050134UL
270#define PORT_SCPDR 0xA4050136UL
271#define PORT_PMDR 0xA4050138UL
272#define PORT_PNDR 0xA405013AUL
273#define PORT_PQDR 0xA405013CUL
274#define PORT_PRDR 0xA405013EUL
275#define PORT_PTDR 0xA405016CUL
276#define PORT_PUDR 0xA405016EUL
277#define PORT_PVDR 0xA4050170UL
278
279#define IRQ0_IRQ 32
280#define IRQ1_IRQ 33
281#define IRQ2_IRQ 34
282#define IRQ3_IRQ 35
283#define IRQ4_IRQ 36
284#define IRQ5_IRQ 37
285#define IRQ6_IRQ 38
286#define IRQ7_IRQ 39
287
288#define INTPRI00 0xA4140010UL
289
290#define IRQ0_IPR_ADDR INTPRI00
291#define IRQ1_IPR_ADDR INTPRI00
292#define IRQ2_IPR_ADDR INTPRI00
293#define IRQ3_IPR_ADDR INTPRI00
294#define IRQ4_IPR_ADDR INTPRI00
295#define IRQ5_IPR_ADDR INTPRI00
296#define IRQ6_IPR_ADDR INTPRI00
297#define IRQ7_IPR_ADDR INTPRI00
298
299#define IRQ0_IPR_POS 7
300#define IRQ1_IPR_POS 6
301#define IRQ2_IPR_POS 5
302#define IRQ3_IPR_POS 4
303#define IRQ4_IPR_POS 3
304#define IRQ5_IPR_POS 2
305#define IRQ6_IPR_POS 1
306#define IRQ7_IPR_POS 0
307
308#define IRQ0_PRIORITY 1
309#define IRQ1_PRIORITY 1
310#define IRQ2_PRIORITY 1
311#define IRQ3_PRIORITY 1
312#define IRQ4_PRIORITY 1
313#define IRQ5_PRIORITY 1
314#define IRQ6_PRIORITY 1
315#define IRQ7_PRIORITY 1
316
317#endif /* __ASM_SH_IRQ_SH7343_H */
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index 648102e9236f..00886f9adb4d 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -192,7 +192,7 @@
192 192
193#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \ 193#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
194 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \ 194 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
195 defined (CONFIG_CPU_SUBTYPE_SH7751) 195 defined (CONFIG_CPU_SUBTYPE_SH7751) || defined (CONFIG_CPU_SUBTYPE_SH7706)
196#define SCI_ERI_IRQ 23 196#define SCI_ERI_IRQ 23
197#define SCI_RXI_IRQ 24 197#define SCI_RXI_IRQ 24
198#define SCI_TXI_IRQ 25 198#define SCI_TXI_IRQ 25
@@ -207,6 +207,7 @@
207#define SCIF0_IPR_POS 3 207#define SCIF0_IPR_POS 3
208#define SCIF0_PRIORITY 3 208#define SCIF0_PRIORITY 3
209#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 209#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
210 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
210 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 211 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
211 defined(CONFIG_CPU_SUBTYPE_SH7709) 212 defined(CONFIG_CPU_SUBTYPE_SH7709)
212#define SCIF_ERI_IRQ 56 213#define SCIF_ERI_IRQ 56
@@ -261,9 +262,12 @@
261#elif defined(CONFIG_CPU_SUBTYPE_SH7708) 262#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
262# define ONCHIP_NR_IRQS 32 263# define ONCHIP_NR_IRQS 32
263#elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 264#elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
265 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
264 defined(CONFIG_CPU_SUBTYPE_SH7705) 266 defined(CONFIG_CPU_SUBTYPE_SH7705)
265# define ONCHIP_NR_IRQS 64 // Actually 61 267# define ONCHIP_NR_IRQS 64 // Actually 61
266# define PINT_NR_IRQS 16 268# define PINT_NR_IRQS 16
269#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
270# define ONCHIP_NR_IRQS 104
267#elif defined(CONFIG_CPU_SUBTYPE_SH7750) 271#elif defined(CONFIG_CPU_SUBTYPE_SH7750)
268# define ONCHIP_NR_IRQS 48 // Actually 44 272# define ONCHIP_NR_IRQS 48 // Actually 44
269#elif defined(CONFIG_CPU_SUBTYPE_SH7751) 273#elif defined(CONFIG_CPU_SUBTYPE_SH7751)
@@ -275,7 +279,8 @@
275#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) 279#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
276# define ONCHIP_NR_IRQS 144 280# define ONCHIP_NR_IRQS 144
277#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \ 281#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
278 defined(CONFIG_CPU_SUBTYPE_SH73180) 282 defined(CONFIG_CPU_SUBTYPE_SH73180) || \
283 defined(CONFIG_CPU_SUBTYPE_SH7343)
279# define ONCHIP_NR_IRQS 109 284# define ONCHIP_NR_IRQS 109
280#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 285#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
281# define ONCHIP_NR_IRQS 111 286# define ONCHIP_NR_IRQS 111
@@ -476,8 +481,10 @@ extern int ipr_irq_demux(int irq);
476 481
477#define INTC_ICR 0xfffffee0UL 482#define INTC_ICR 0xfffffee0UL
478#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 483#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
484 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
479 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 485 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
480 defined(CONFIG_CPU_SUBTYPE_SH7709) 486 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
487 defined(CONFIG_CPU_SUBTYPE_SH7710)
481#define INTC_IRR0 0xa4000004UL 488#define INTC_IRR0 0xa4000004UL
482#define INTC_IRR1 0xa4000006UL 489#define INTC_IRR1 0xa4000006UL
483#define INTC_IRR2 0xa4000008UL 490#define INTC_IRR2 0xa4000008UL
@@ -496,8 +503,105 @@ extern int ipr_irq_demux(int irq);
496#define INTC_IPRF 0xa4080000UL 503#define INTC_IPRF 0xa4080000UL
497#define INTC_IPRG 0xa4080002UL 504#define INTC_IPRG 0xa4080002UL
498#define INTC_IPRH 0xa4080004UL 505#define INTC_IPRH 0xa4080004UL
499#endif 506#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
507/* Interrupt Controller Registers */
508#undef INTC_IPRA
509#undef INTC_IPRB
510#define INTC_IPRA 0xA414FEE2UL
511#define INTC_IPRB 0xA414FEE4UL
512#define INTC_IPRF 0xA4080000UL
513#define INTC_IPRG 0xA4080002UL
514#define INTC_IPRH 0xA4080004UL
515#define INTC_IPRI 0xA4080006UL
516
517#undef INTC_ICR0
518#undef INTC_ICR1
519#define INTC_ICR0 0xA414FEE0UL
520#define INTC_ICR1 0xA4140010UL
521
522#define INTC_IRR0 0xa4000004UL
523#define INTC_IRR1 0xa4000006UL
524#define INTC_IRR2 0xa4000008UL
525#define INTC_IRR3 0xa400000AUL
526#define INTC_IRR4 0xa400000CUL
527#define INTC_IRR5 0xa4080020UL
528#define INTC_IRR7 0xa4080024UL
529#define INTC_IRR8 0xa4080026UL
530
531/* Interrupt numbers */
532#define TIMER2_IRQ 18
533#define TIMER2_IPR_ADDR INTC_IPRA
534#define TIMER2_IPR_POS 1
535#define TIMER2_PRIORITY 2
500 536
537/* WDT */
538#define WDT_IRQ 27
539#define WDT_IPR_ADDR INTC_IPRB
540#define WDT_IPR_POS 3
541#define WDT_PRIORITY 2
542
543#define SCIF0_ERI_IRQ 52
544#define SCIF0_RXI_IRQ 53
545#define SCIF0_BRI_IRQ 54
546#define SCIF0_TXI_IRQ 55
547#define SCIF0_IPR_ADDR INTC_IPRE
548#define SCIF0_IPR_POS 2
549#define SCIF0_PRIORITY 3
550
551#define DMTE4_IRQ 76
552#define DMTE5_IRQ 77
553#define DMA2_IPR_ADDR INTC_IPRF
554#define DMA2_IPR_POS 2
555#define DMA2_PRIORITY 7
556
557#define IPSEC_IRQ 79
558#define IPSEC_IPR_ADDR INTC_IPRF
559#define IPSEC_IPR_POS 3
560#define IPSEC_PRIORITY 3
561
562/* EDMAC */
563#define EDMAC0_IRQ 80
564#define EDMAC0_IPR_ADDR INTC_IPRG
565#define EDMAC0_IPR_POS 3
566#define EDMAC0_PRIORITY 3
567
568#define EDMAC1_IRQ 81
569#define EDMAC1_IPR_ADDR INTC_IPRG
570#define EDMAC1_IPR_POS 2
571#define EDMAC1_PRIORITY 3
572
573#define EDMAC2_IRQ 82
574#define EDMAC2_IPR_ADDR INTC_IPRG
575#define EDMAC2_IPR_POS 1
576#define EDMAC2_PRIORITY 3
577
578/* SIOF */
579#define SIOF0_ERI_IRQ 96
580#define SIOF0_TXI_IRQ 97
581#define SIOF0_RXI_IRQ 98
582#define SIOF0_CCI_IRQ 99
583#define SIOF0_IPR_ADDR INTC_IPRH
584#define SIOF0_IPR_POS 0
585#define SIOF0_PRIORITY 7
586
587#define SIOF1_ERI_IRQ 100
588#define SIOF1_TXI_IRQ 101
589#define SIOF1_RXI_IRQ 102
590#define SIOF1_CCI_IRQ 103
591#define SIOF1_IPR_ADDR INTC_IPRI
592#define SIOF1_IPR_POS 1
593#define SIOF1_PRIORITY 7
594#endif /* CONFIG_CPU_SUBTYPE_SH7710 */
595
596#if defined(CONFIG_CPU_SUBTYPE_SH7710)
597#define PORT_PACR 0xa4050100UL
598#define PORT_PBCR 0xa4050102UL
599#define PORT_PCCR 0xa4050104UL
600#define PORT_PETCR 0xa4050106UL
601#define PORT_PADR 0xa4050120UL
602#define PORT_PBDR 0xa4050122UL
603#define PORT_PCDR 0xa4050124UL
604#else
501#define PORT_PACR 0xa4000100UL 605#define PORT_PACR 0xa4000100UL
502#define PORT_PBCR 0xa4000102UL 606#define PORT_PBCR 0xa4000102UL
503#define PORT_PCCR 0xa4000104UL 607#define PORT_PCCR 0xa4000104UL
@@ -506,6 +610,7 @@ extern int ipr_irq_demux(int irq);
506#define PORT_PBDR 0xa4000122UL 610#define PORT_PBDR 0xa4000122UL
507#define PORT_PCDR 0xa4000124UL 611#define PORT_PCDR 0xa4000124UL
508#define PORT_PFDR 0xa400012aUL 612#define PORT_PFDR 0xa400012aUL
613#endif
509 614
510#define IRQ0_IRQ 32 615#define IRQ0_IRQ 32
511#define IRQ1_IRQ 33 616#define IRQ1_IRQ 33
@@ -599,6 +704,8 @@ void intc2_add_clear_irq(int irq, int (*fn)(int));
599 704
600#endif 705#endif
601 706
707extern int shmse_irq_demux(int irq);
708
602static inline int generic_irq_demux(int irq) 709static inline int generic_irq_demux(int irq)
603{ 710{
604 return irq; 711 return irq;
@@ -614,4 +721,8 @@ static inline int generic_irq_demux(int irq)
614#include <asm/irq-sh73180.h> 721#include <asm/irq-sh73180.h>
615#endif 722#endif
616 723
724#if defined(CONFIG_CPU_SUBTYPE_SH7343)
725#include <asm/irq-sh7343.h>
726#endif
727
617#endif /* __ASM_SH_IRQ_H */ 728#endif /* __ASM_SH_IRQ_H */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index a22732007dd4..3b3ef4f2bf31 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -38,13 +38,15 @@ enum cpu_type {
38 CPU_SH7604, 38 CPU_SH7604,
39 39
40 /* SH-3 types */ 40 /* SH-3 types */
41 CPU_SH7705, CPU_SH7707, CPU_SH7708, CPU_SH7708S, CPU_SH7708R, 41 CPU_SH7705, CPU_SH7706, CPU_SH7707,
42 CPU_SH7709, CPU_SH7709A, CPU_SH7729, CPU_SH7300, 42 CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
43 CPU_SH7709, CPU_SH7709A, CPU_SH7710,
44 CPU_SH7729, CPU_SH7300,
43 45
44 /* SH-4 types */ 46 /* SH-4 types */
45 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, 47 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
46 CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501, 48 CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
47 CPU_SH73180, CPU_SH7770, CPU_SH7780, CPU_SH7781, 49 CPU_SH73180, CPU_SH7343, CPU_SH7770, CPU_SH7780, CPU_SH7781,
48 50
49 /* Unknown subtype */ 51 /* Unknown subtype */
50 CPU_SH_NONE 52 CPU_SH_NONE
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 14:52:33 -0500