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authorRalf Baechle <ralf@linux-mips.org>2007-10-14 09:27:18 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-16 13:23:46 -0400
commitb37bac94de9ad5eb17bd9327d3ecb6f3b719dc70 (patch)
tree2f1cc110b2a3d83f6f09e2f83eec0c4710af661c
parentdd67b1556ebea118b40986cdb8e70874b5454442 (diff)
[MIPS] MSP71XX: Add workarounds file.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/war.h28
1 files changed, 28 insertions, 0 deletions
diff --git a/include/asm-mips/pmc-sierra/msp71xx/war.h b/include/asm-mips/pmc-sierra/msp71xx/war.h
new file mode 100644
index 000000000000..0bf48fc1892b
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/war.h
@@ -0,0 +1,28 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_PMC_SIERRA_WAR_H
9#define __ASM_MIPS_PMC_SIERRA_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
24 defined(CONFIG_PMC_MSP7120_FPGA)
25#define MIPS34K_MISSED_ITLB_WAR 1
26#endif
27
28#endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */