aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorGuennadi Liakhovetski <g.liakhovetski@gmx.de>2010-02-18 10:24:17 -0500
committerPaul Mundt <lethal@linux-sh.org>2010-03-01 21:10:52 -0500
commitc8e3149ba7de24dfd4c37bb0df23c878cdecd8d4 (patch)
tree29d900f71d3f951cd8061d90a8997317e97c91b7
parentbff932cf6eda730fa42c363f7cfcc98c39240a24 (diff)
sh: merge sh7722 and sh7724 DMA register definitions
DMA CHCR register layout is equal on sh7722 and sh7724, reuse definitions. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-register.h8
1 files changed, 2 insertions, 6 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-register.h b/arch/sh/include/cpu-sh4/cpu/dma-register.h
index 008e7fc8f6c0..55f9fec082d4 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma-register.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma-register.h
@@ -22,7 +22,8 @@
22#define CHCR_TS_LOW_SHIFT 3 22#define CHCR_TS_LOW_SHIFT 3
23#define CHCR_TS_HIGH_MASK 0 23#define CHCR_TS_HIGH_MASK 0
24#define CHCR_TS_HIGH_SHIFT 0 24#define CHCR_TS_HIGH_SHIFT 0
25#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 25#elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \
26 defined(CONFIG_CPU_SUBTYPE_SH7724)
26#define CHCR_TS_LOW_MASK 0x00000018 27#define CHCR_TS_LOW_MASK 0x00000018
27#define CHCR_TS_LOW_SHIFT 3 28#define CHCR_TS_LOW_SHIFT 3
28#define CHCR_TS_HIGH_MASK 0x00300000 29#define CHCR_TS_HIGH_MASK 0x00300000
@@ -38,11 +39,6 @@
38#define CHCR_TS_LOW_SHIFT 3 39#define CHCR_TS_LOW_SHIFT 3
39#define CHCR_TS_HIGH_MASK 0 40#define CHCR_TS_HIGH_MASK 0
40#define CHCR_TS_HIGH_SHIFT 0 41#define CHCR_TS_HIGH_SHIFT 0
41#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
42#define CHCR_TS_LOW_MASK 0x00000018
43#define CHCR_TS_LOW_SHIFT 3
44#define CHCR_TS_HIGH_MASK 0x00600000
45#define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */
46#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 42#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
47#define CHCR_TS_LOW_MASK 0x00000018 43#define CHCR_TS_LOW_MASK 0x00000018
48#define CHCR_TS_LOW_SHIFT 3 44#define CHCR_TS_LOW_SHIFT 3