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authorBen Dooks <ben@simtec.co.uk>2009-07-16 01:24:08 -0400
committerDavid S. Miller <davem@davemloft.net>2009-07-20 11:23:26 -0400
commit3ba81f3ece3cfa4ffb06d21ac93b8cad7fbe6a73 (patch)
tree87b339fec60d3a9f3007acc05c9b2eb6bf6dc459
parente547bc1eccf539b7403138d8ded913ffd2b7fd0d (diff)
net: Micrel KS8851 SPI network driver
Network driver for the SPI version of the Micrel KS8851 network chip. Signed-off-by: Ben Dooks <ben@simtec.co.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/Kconfig6
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/ks8851.c1322
-rw-r--r--drivers/net/ks8851.h296
4 files changed, 1625 insertions, 0 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index c155bd3ec9f1..b5a7513df4eb 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1729,6 +1729,12 @@ config KS8842
1729 help 1729 help
1730 This platform driver is for Micrel KSZ8842 chip. 1730 This platform driver is for Micrel KSZ8842 chip.
1731 1731
1732config KS8851
1733 tristate "Micrel KS8851 SPI"
1734 depends on SPI
1735 help
1736 SPI driver for Micrel KS8851 SPI attached network chip.
1737
1732config VIA_RHINE 1738config VIA_RHINE
1733 tristate "VIA Rhine support" 1739 tristate "VIA Rhine support"
1734 depends on NET_PCI && PCI 1740 depends on NET_PCI && PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 4b58a59f211b..ead8cab3cfe1 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -88,6 +88,7 @@ obj-$(CONFIG_SKGE) += skge.o
88obj-$(CONFIG_SKY2) += sky2.o 88obj-$(CONFIG_SKY2) += sky2.o
89obj-$(CONFIG_SKFP) += skfp/ 89obj-$(CONFIG_SKFP) += skfp/
90obj-$(CONFIG_KS8842) += ks8842.o 90obj-$(CONFIG_KS8842) += ks8842.o
91obj-$(CONFIG_KS8851) += ks8851.o
91obj-$(CONFIG_VIA_RHINE) += via-rhine.o 92obj-$(CONFIG_VIA_RHINE) += via-rhine.o
92obj-$(CONFIG_VIA_VELOCITY) += via-velocity.o 93obj-$(CONFIG_VIA_VELOCITY) += via-velocity.o
93obj-$(CONFIG_ADAPTEC_STARFIRE) += starfire.o 94obj-$(CONFIG_ADAPTEC_STARFIRE) += starfire.o
diff --git a/drivers/net/ks8851.c b/drivers/net/ks8851.c
new file mode 100644
index 000000000000..9a1dea60c1c4
--- /dev/null
+++ b/drivers/net/ks8851.c
@@ -0,0 +1,1322 @@
1/* drivers/net/ks8651.c
2 *
3 * Copyright 2009 Simtec Electronics
4 * http://www.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#define DEBUG
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/netdevice.h>
17#include <linux/etherdevice.h>
18#include <linux/ethtool.h>
19#include <linux/cache.h>
20#include <linux/crc32.h>
21#include <linux/mii.h>
22
23#include <linux/spi/spi.h>
24
25#include "ks8851.h"
26
27/**
28 * struct ks8851_rxctrl - KS8851 driver rx control
29 * @mchash: Multicast hash-table data.
30 * @rxcr1: KS_RXCR1 register setting
31 * @rxcr2: KS_RXCR2 register setting
32 *
33 * Representation of the settings needs to control the receive filtering
34 * such as the multicast hash-filter and the receive register settings. This
35 * is used to make the job of working out if the receive settings change and
36 * then issuing the new settings to the worker that will send the necessary
37 * commands.
38 */
39struct ks8851_rxctrl {
40 u16 mchash[4];
41 u16 rxcr1;
42 u16 rxcr2;
43};
44
45/**
46 * union ks8851_tx_hdr - tx header data
47 * @txb: The header as bytes
48 * @txw: The header as 16bit, little-endian words
49 *
50 * A dual representation of the tx header data to allow
51 * access to individual bytes, and to allow 16bit accesses
52 * with 16bit alignment.
53 */
54union ks8851_tx_hdr {
55 u8 txb[6];
56 __le16 txw[3];
57};
58
59/**
60 * struct ks8851_net - KS8851 driver private data
61 * @netdev: The network device we're bound to
62 * @spidev: The spi device we're bound to.
63 * @lock: Lock to ensure that the device is not accessed when busy.
64 * @statelock: Lock on this structure for tx list.
65 * @mii: The MII state information for the mii calls.
66 * @rxctrl: RX settings for @rxctrl_work.
67 * @tx_work: Work queue for tx packets
68 * @irq_work: Work queue for servicing interrupts
69 * @rxctrl_work: Work queue for updating RX mode and multicast lists
70 * @txq: Queue of packets for transmission.
71 * @spi_msg1: pre-setup SPI transfer with one message, @spi_xfer1.
72 * @spi_msg2: pre-setup SPI transfer with two messages, @spi_xfer2.
73 * @txh: Space for generating packet TX header in DMA-able data
74 * @rxd: Space for receiving SPI data, in DMA-able space.
75 * @txd: Space for transmitting SPI data, in DMA-able space.
76 * @msg_enable: The message flags controlling driver output (see ethtool).
77 * @fid: Incrementing frame id tag.
78 * @rc_ier: Cached copy of KS_IER.
79 * @rc_rxqcr: Cached copy of KS_RXQCR.
80 *
81 * The @lock ensures that the chip is protected when certain operations are
82 * in progress. When the read or write packet transfer is in progress, most
83 * of the chip registers are not ccessible until the transfer is finished and
84 * the DMA has been de-asserted.
85 *
86 * The @statelock is used to protect information in the structure which may
87 * need to be accessed via several sources, such as the network driver layer
88 * or one of the work queues.
89 *
90 * We align the buffers we may use for rx/tx to ensure that if the SPI driver
91 * wants to DMA map them, it will not have any problems with data the driver
92 * modifies.
93 */
94struct ks8851_net {
95 struct net_device *netdev;
96 struct spi_device *spidev;
97 struct mutex lock;
98 spinlock_t statelock;
99
100 union ks8851_tx_hdr txh ____cacheline_aligned;
101 u8 rxd[8];
102 u8 txd[8];
103
104 u32 msg_enable ____cacheline_aligned;
105 u16 tx_space;
106 u8 fid;
107
108 u16 rc_ier;
109 u16 rc_rxqcr;
110
111 struct mii_if_info mii;
112 struct ks8851_rxctrl rxctrl;
113
114 struct work_struct tx_work;
115 struct work_struct irq_work;
116 struct work_struct rxctrl_work;
117
118 struct sk_buff_head txq;
119
120 struct spi_message spi_msg1;
121 struct spi_message spi_msg2;
122 struct spi_transfer spi_xfer1;
123 struct spi_transfer spi_xfer2[2];
124};
125
126static int msg_enable;
127
128#define ks_info(_ks, _msg...) dev_info(&(_ks)->spidev->dev, _msg)
129#define ks_warn(_ks, _msg...) dev_warn(&(_ks)->spidev->dev, _msg)
130#define ks_dbg(_ks, _msg...) dev_dbg(&(_ks)->spidev->dev, _msg)
131#define ks_err(_ks, _msg...) dev_err(&(_ks)->spidev->dev, _msg)
132
133/* shift for byte-enable data */
134#define BYTE_EN(_x) ((_x) << 2)
135
136/* turn register number and byte-enable mask into data for start of packet */
137#define MK_OP(_byteen, _reg) (BYTE_EN(_byteen) | (_reg) << (8+2) | (_reg) >> 6)
138
139/* SPI register read/write calls.
140 *
141 * All these calls issue SPI transactions to access the chip's registers. They
142 * all require that the necessary lock is held to prevent accesses when the
143 * chip is busy transfering packet data (RX/TX FIFO accesses).
144 */
145
146/**
147 * ks8851_wrreg16 - write 16bit register value to chip
148 * @ks: The chip state
149 * @reg: The register address
150 * @val: The value to write
151 *
152 * Issue a write to put the value @val into the register specified in @reg.
153 */
154static void ks8851_wrreg16(struct ks8851_net *ks, unsigned reg, unsigned val)
155{
156 struct spi_transfer *xfer = &ks->spi_xfer1;
157 struct spi_message *msg = &ks->spi_msg1;
158 __le16 txb[2];
159 int ret;
160
161 txb[0] = cpu_to_le16(MK_OP(reg & 2 ? 0xC : 0x03, reg) | KS_SPIOP_WR);
162 txb[1] = cpu_to_le16(val);
163
164 xfer->tx_buf = txb;
165 xfer->rx_buf = NULL;
166 xfer->len = 4;
167
168 ret = spi_sync(ks->spidev, msg);
169 if (ret < 0)
170 ks_err(ks, "spi_sync() failed\n");
171}
172
173/**
174 * ks8851_rx_1msg - select whether to use one or two messages for spi read
175 * @ks: The device structure
176 *
177 * Return whether to generate a single message with a tx and rx buffer
178 * supplied to spi_sync(), or alternatively send the tx and rx buffers
179 * as separate messages.
180 *
181 * Depending on the hardware in use, a single message may be more efficient
182 * on interrupts or work done by the driver.
183 *
184 * This currently always returns true until we add some per-device data passed
185 * from the platform code to specify which mode is better.
186 */
187static inline bool ks8851_rx_1msg(struct ks8851_net *ks)
188{
189 return true;
190}
191
192/**
193 * ks8851_rdreg - issue read register command and return the data
194 * @ks: The device state
195 * @op: The register address and byte enables in message format.
196 * @rxb: The RX buffer to return the result into
197 * @rxl: The length of data expected.
198 *
199 * This is the low level read call that issues the necessary spi message(s)
200 * to read data from the register specified in @op.
201 */
202static void ks8851_rdreg(struct ks8851_net *ks, unsigned op,
203 u8 *rxb, unsigned rxl)
204{
205 struct spi_transfer *xfer;
206 struct spi_message *msg;
207 __le16 *txb = (__le16 *)ks->txd;
208 u8 *trx = ks->rxd;
209 int ret;
210
211 txb[0] = cpu_to_le16(op | KS_SPIOP_RD);
212
213 if (ks8851_rx_1msg(ks)) {
214 msg = &ks->spi_msg1;
215 xfer = &ks->spi_xfer1;
216
217 xfer->tx_buf = txb;
218 xfer->rx_buf = trx;
219 xfer->len = rxl + 2;
220 } else {
221 msg = &ks->spi_msg2;
222 xfer = ks->spi_xfer2;
223
224 xfer->tx_buf = txb;
225 xfer->rx_buf = NULL;
226 xfer->len = 2;
227
228 xfer++;
229 xfer->tx_buf = NULL;
230 xfer->rx_buf = trx;
231 xfer->len = rxl;
232 }
233
234 ret = spi_sync(ks->spidev, msg);
235 if (ret < 0)
236 ks_err(ks, "read: spi_sync() failed\n");
237 else if (ks8851_rx_1msg(ks))
238 memcpy(rxb, trx + 2, rxl);
239 else
240 memcpy(rxb, trx, rxl);
241}
242
243/**
244 * ks8851_rdreg8 - read 8 bit register from device
245 * @ks: The chip information
246 * @reg: The register address
247 *
248 * Read a 8bit register from the chip, returning the result
249*/
250static unsigned ks8851_rdreg8(struct ks8851_net *ks, unsigned reg)
251{
252 u8 rxb[1];
253
254 ks8851_rdreg(ks, MK_OP(1 << (reg & 3), reg), rxb, 1);
255 return rxb[0];
256}
257
258/**
259 * ks8851_rdreg16 - read 16 bit register from device
260 * @ks: The chip information
261 * @reg: The register address
262 *
263 * Read a 16bit register from the chip, returning the result
264*/
265static unsigned ks8851_rdreg16(struct ks8851_net *ks, unsigned reg)
266{
267 __le16 rx = 0;
268
269 ks8851_rdreg(ks, MK_OP(reg & 2 ? 0xC : 0x3, reg), (u8 *)&rx, 2);
270 return le16_to_cpu(rx);
271}
272
273/**
274 * ks8851_rdreg32 - read 32 bit register from device
275 * @ks: The chip information
276 * @reg: The register address
277 *
278 * Read a 32bit register from the chip.
279 *
280 * Note, this read requires the address be aligned to 4 bytes.
281*/
282static unsigned ks8851_rdreg32(struct ks8851_net *ks, unsigned reg)
283{
284 __le32 rx = 0;
285
286 WARN_ON(reg & 3);
287
288 ks8851_rdreg(ks, MK_OP(0xf, reg), (u8 *)&rx, 4);
289 return le32_to_cpu(rx);
290}
291
292/**
293 * ks8851_soft_reset - issue one of the soft reset to the device
294 * @ks: The device state.
295 * @op: The bit(s) to set in the GRR
296 *
297 * Issue the relevant soft-reset command to the device's GRR register
298 * specified by @op.
299 *
300 * Note, the delays are in there as a caution to ensure that the reset
301 * has time to take effect and then complete. Since the datasheet does
302 * not currently specify the exact sequence, we have chosen something
303 * that seems to work with our device.
304 */
305static void ks8851_soft_reset(struct ks8851_net *ks, unsigned op)
306{
307 ks8851_wrreg16(ks, KS_GRR, op);
308 mdelay(1); /* wait a short time to effect reset */
309 ks8851_wrreg16(ks, KS_GRR, 0);
310 mdelay(1); /* wait for condition to clear */
311}
312
313/**
314 * ks8851_write_mac_addr - write mac address to device registers
315 * @dev: The network device
316 *
317 * Update the KS8851 MAC address registers from the address in @dev.
318 *
319 * This call assumes that the chip is not running, so there is no need to
320 * shutdown the RXQ process whilst setting this.
321*/
322static int ks8851_write_mac_addr(struct net_device *dev)
323{
324 struct ks8851_net *ks = netdev_priv(dev);
325 u16 *mcp = (u16 *)dev->dev_addr;
326
327 mutex_lock(&ks->lock);
328
329 ks8851_wrreg16(ks, KS_MARL, mcp[0]);
330 ks8851_wrreg16(ks, KS_MARM, mcp[1]);
331 ks8851_wrreg16(ks, KS_MARH, mcp[2]);
332
333 mutex_unlock(&ks->lock);
334
335 return 0;
336}
337
338/**
339 * ks8851_init_mac - initialise the mac address
340 * @ks: The device structure
341 *
342 * Get or create the initial mac address for the device and then set that
343 * into the station address register. Currently we assume that the device
344 * does not have a valid mac address in it, and so we use random_ether_addr()
345 * to create a new one.
346 *
347 * In future, the driver should check to see if the device has an EEPROM
348 * attached and whether that has a valid ethernet address in it.
349 */
350static void ks8851_init_mac(struct ks8851_net *ks)
351{
352 struct net_device *dev = ks->netdev;
353
354 random_ether_addr(dev->dev_addr);
355 ks8851_write_mac_addr(dev);
356}
357
358/**
359 * ks8851_irq - device interrupt handler
360 * @irq: Interrupt number passed from the IRQ hnalder.
361 * @pw: The private word passed to register_irq(), our struct ks8851_net.
362 *
363 * Disable the interrupt from happening again until we've processed the
364 * current status by scheduling ks8851_irq_work().
365 */
366static irqreturn_t ks8851_irq(int irq, void *pw)
367{
368 struct ks8851_net *ks = pw;
369
370 disable_irq_nosync(irq);
371 schedule_work(&ks->irq_work);
372 return IRQ_HANDLED;
373}
374
375/**
376 * ks8851_rdfifo - read data from the receive fifo
377 * @ks: The device state.
378 * @buff: The buffer address
379 * @len: The length of the data to read
380 *
381 * Issue an RXQ FIFO read command and read the @len ammount of data from
382 * the FIFO into the buffer specified by @buff.
383 */
384static void ks8851_rdfifo(struct ks8851_net *ks, u8 *buff, unsigned len)
385{
386 struct spi_transfer *xfer = ks->spi_xfer2;
387 struct spi_message *msg = &ks->spi_msg2;
388 u8 txb[1];
389 int ret;
390
391 if (netif_msg_rx_status(ks))
392 ks_dbg(ks, "%s: %d@%p\n", __func__, len, buff);
393
394 /* set the operation we're issuing */
395 txb[0] = KS_SPIOP_RXFIFO;
396
397 xfer->tx_buf = txb;
398 xfer->rx_buf = NULL;
399 xfer->len = 1;
400
401 xfer++;
402 xfer->rx_buf = buff;
403 xfer->tx_buf = NULL;
404 xfer->len = len;
405
406 ret = spi_sync(ks->spidev, msg);
407 if (ret < 0)
408 ks_err(ks, "%s: spi_sync() failed\n", __func__);
409}
410
411/**
412 * ks8851_dbg_dumpkkt - dump initial packet contents to debug
413 * @ks: The device state
414 * @rxpkt: The data for the received packet
415 *
416 * Dump the initial data from the packet to dev_dbg().
417*/
418static void ks8851_dbg_dumpkkt(struct ks8851_net *ks, u8 *rxpkt)
419{
420 ks_dbg(ks, "pkt %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x\n",
421 rxpkt[4], rxpkt[5], rxpkt[6], rxpkt[7],
422 rxpkt[8], rxpkt[9], rxpkt[10], rxpkt[11],
423 rxpkt[12], rxpkt[13], rxpkt[14], rxpkt[15]);
424}
425
426/**
427 * ks8851_rx_pkts - receive packets from the host
428 * @ks: The device information.
429 *
430 * This is called from the IRQ work queue when the system detects that there
431 * are packets in the receive queue. Find out how many packets there are and
432 * read them from the FIFO.
433 */
434static void ks8851_rx_pkts(struct ks8851_net *ks)
435{
436 struct sk_buff *skb;
437 unsigned rxfc;
438 unsigned rxlen;
439 unsigned rxstat;
440 u32 rxh;
441 u8 *rxpkt;
442
443 rxfc = ks8851_rdreg8(ks, KS_RXFC);
444
445 if (netif_msg_rx_status(ks))
446 ks_dbg(ks, "%s: %d packets\n", __func__, rxfc);
447
448 /* Currently we're issuing a read per packet, but we could possibly
449 * improve the code by issuing a single read, getting the receive
450 * header, allocating the packet and then reading the packet data
451 * out in one go.
452 *
453 * This form of operation would require us to hold the SPI bus'
454 * chipselect low during the entie transaction to avoid any
455 * reset to the data stream comming from the chip.
456 */
457
458 for (; rxfc != 0; rxfc--) {
459 rxh = ks8851_rdreg32(ks, KS_RXFHSR);
460 rxstat = rxh & 0xffff;
461 rxlen = rxh >> 16;
462
463 if (netif_msg_rx_status(ks))
464 ks_dbg(ks, "rx: stat 0x%04x, len 0x%04x\n",
465 rxstat, rxlen);
466
467 /* the length of the packet includes the 32bit CRC */
468
469 /* set dma read address */
470 ks8851_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI | 0x00);
471
472 /* start the packet dma process, and set auto-dequeue rx */
473 ks8851_wrreg16(ks, KS_RXQCR,
474 ks->rc_rxqcr | RXQCR_SDA | RXQCR_ADRFE);
475
476 if (rxlen > 0) {
477 skb = netdev_alloc_skb(ks->netdev, rxlen + 2 + 8);
478 if (!skb) {
479 /* todo - dump frame and move on */
480 }
481
482 /* two bytes to ensure ip is aligned, and four bytes
483 * for the status header and 4 bytes of garbage */
484 skb_reserve(skb, 2 + 4 + 4);
485
486 rxpkt = skb_put(skb, rxlen - 4) - 8;
487
488 /* align the packet length to 4 bytes, and add 4 bytes
489 * as we're getting the rx status header as well */
490 ks8851_rdfifo(ks, rxpkt, ALIGN(rxlen, 4) + 8);
491
492 if (netif_msg_pktdata(ks))
493 ks8851_dbg_dumpkkt(ks, rxpkt);
494
495 skb->protocol = eth_type_trans(skb, ks->netdev);
496 netif_rx(skb);
497
498 ks->netdev->stats.rx_packets++;
499 ks->netdev->stats.rx_bytes += rxlen - 4;
500 }
501
502 ks8851_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr);
503 }
504}
505
506/**
507 * ks8851_irq_work - work queue handler for dealing with interrupt requests
508 * @work: The work structure that was scheduled by schedule_work()
509 *
510 * This is the handler invoked when the ks8851_irq() is called to find out
511 * what happened, as we cannot allow ourselves to sleep whilst waiting for
512 * anything other process has the chip's lock.
513 *
514 * Read the interrupt status, work out what needs to be done and then clear
515 * any of the interrupts that are not needed.
516 */
517static void ks8851_irq_work(struct work_struct *work)
518{
519 struct ks8851_net *ks = container_of(work, struct ks8851_net, irq_work);
520 unsigned status;
521 unsigned handled = 0;
522
523 mutex_lock(&ks->lock);
524
525 status = ks8851_rdreg16(ks, KS_ISR);
526
527 if (netif_msg_intr(ks))
528 dev_dbg(&ks->spidev->dev, "%s: status 0x%04x\n",
529 __func__, status);
530
531 if (status & IRQ_LCI) {
532 /* should do something about checking link status */
533 handled |= IRQ_LCI;
534 }
535
536 if (status & IRQ_LDI) {
537 u16 pmecr = ks8851_rdreg16(ks, KS_PMECR);
538 pmecr &= ~PMECR_WKEVT_MASK;
539 ks8851_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
540
541 handled |= IRQ_LDI;
542 }
543
544 if (status & IRQ_RXPSI)
545 handled |= IRQ_RXPSI;
546
547 if (status & IRQ_TXI) {
548 handled |= IRQ_TXI;
549
550 /* no lock here, tx queue should have been stopped */
551
552 /* update our idea of how much tx space is available to the
553 * system */
554 ks->tx_space = ks8851_rdreg16(ks, KS_TXMIR);
555
556 if (netif_msg_intr(ks))
557 ks_dbg(ks, "%s: txspace %d\n", __func__, ks->tx_space);
558 }
559
560 if (status & IRQ_RXI)
561 handled |= IRQ_RXI;
562
563 if (status & IRQ_SPIBEI) {
564 dev_err(&ks->spidev->dev, "%s: spi bus error\n", __func__);
565 handled |= IRQ_SPIBEI;
566 }
567
568 ks8851_wrreg16(ks, KS_ISR, handled);
569
570 if (status & IRQ_RXI) {
571 /* the datasheet says to disable the rx interrupt during
572 * packet read-out, however we're masking the interrupt
573 * from the device so do not bother masking just the RX
574 * from the device. */
575
576 ks8851_rx_pkts(ks);
577 }
578
579 /* if something stopped the rx process, probably due to wanting
580 * to change the rx settings, then do something about restarting
581 * it. */
582 if (status & IRQ_RXPSI) {
583 struct ks8851_rxctrl *rxc = &ks->rxctrl;
584
585 /* update the multicast hash table */
586 ks8851_wrreg16(ks, KS_MAHTR0, rxc->mchash[0]);
587 ks8851_wrreg16(ks, KS_MAHTR1, rxc->mchash[1]);
588 ks8851_wrreg16(ks, KS_MAHTR2, rxc->mchash[2]);
589 ks8851_wrreg16(ks, KS_MAHTR3, rxc->mchash[3]);
590
591 ks8851_wrreg16(ks, KS_RXCR2, rxc->rxcr2);
592 ks8851_wrreg16(ks, KS_RXCR1, rxc->rxcr1);
593 }
594
595 mutex_unlock(&ks->lock);
596
597 if (status & IRQ_TXI)
598 netif_wake_queue(ks->netdev);
599
600 enable_irq(ks->netdev->irq);
601}
602
603/**
604 * calc_txlen - calculate size of message to send packet
605 * @len: Lenght of data
606 *
607 * Returns the size of the TXFIFO message needed to send
608 * this packet.
609 */
610static inline unsigned calc_txlen(unsigned len)
611{
612 return ALIGN(len + 4, 4);
613}
614
615/**
616 * ks8851_wrpkt - write packet to TX FIFO
617 * @ks: The device state.
618 * @txp: The sk_buff to transmit.
619 * @irq: IRQ on completion of the packet.
620 *
621 * Send the @txp to the chip. This means creating the relevant packet header
622 * specifying the length of the packet and the other information the chip
623 * needs, such as IRQ on completion. Send the header and the packet data to
624 * the device.
625 */
626static void ks8851_wrpkt(struct ks8851_net *ks, struct sk_buff *txp, bool irq)
627{
628 struct spi_transfer *xfer = ks->spi_xfer2;
629 struct spi_message *msg = &ks->spi_msg2;
630 unsigned fid = 0;
631 int ret;
632
633 if (netif_msg_tx_queued(ks))
634 dev_dbg(&ks->spidev->dev, "%s: skb %p, %d@%p, irq %d\n",
635 __func__, txp, txp->len, txp->data, irq);
636
637 fid = ks->fid++;
638 fid &= TXFR_TXFID_MASK;
639
640 if (irq)
641 fid |= TXFR_TXIC; /* irq on completion */
642
643 /* start header at txb[1] to align txw entries */
644 ks->txh.txb[1] = KS_SPIOP_TXFIFO;
645 ks->txh.txw[1] = cpu_to_le16(fid);
646 ks->txh.txw[2] = cpu_to_le16(txp->len);
647
648 xfer->tx_buf = &ks->txh.txb[1];
649 xfer->rx_buf = NULL;
650 xfer->len = 5;
651
652 xfer++;
653 xfer->tx_buf = txp->data;
654 xfer->rx_buf = NULL;
655 xfer->len = ALIGN(txp->len, 4);
656
657 ret = spi_sync(ks->spidev, msg);
658 if (ret < 0)
659 ks_err(ks, "%s: spi_sync() failed\n", __func__);
660}
661
662/**
663 * ks8851_done_tx - update and then free skbuff after transmitting
664 * @ks: The device state
665 * @txb: The buffer transmitted
666 */
667static void ks8851_done_tx(struct ks8851_net *ks, struct sk_buff *txb)
668{
669 struct net_device *dev = ks->netdev;
670
671 dev->stats.tx_bytes += txb->len;
672 dev->stats.tx_packets++;
673
674 dev_kfree_skb(txb);
675}
676
677/**
678 * ks8851_tx_work - process tx packet(s)
679 * @work: The work strucutre what was scheduled.
680 *
681 * This is called when a number of packets have been scheduled for
682 * transmission and need to be sent to the device.
683 */
684static void ks8851_tx_work(struct work_struct *work)
685{
686 struct ks8851_net *ks = container_of(work, struct ks8851_net, tx_work);
687 struct sk_buff *txb;
688 bool last = false;
689
690 mutex_lock(&ks->lock);
691
692 while (!last) {
693 txb = skb_dequeue(&ks->txq);
694 last = skb_queue_empty(&ks->txq);
695
696 ks8851_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr | RXQCR_SDA);
697 ks8851_wrpkt(ks, txb, last);
698 ks8851_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr);
699 ks8851_wrreg16(ks, KS_TXQCR, TXQCR_METFE);
700
701 ks8851_done_tx(ks, txb);
702 }
703
704 mutex_unlock(&ks->lock);
705}
706
707/**
708 * ks8851_set_powermode - set power mode of the device
709 * @ks: The device state
710 * @pwrmode: The power mode value to write to KS_PMECR.
711 *
712 * Change the power mode of the chip.
713 */
714static void ks8851_set_powermode(struct ks8851_net *ks, unsigned pwrmode)
715{
716 unsigned pmecr;
717
718 if (netif_msg_hw(ks))
719 ks_dbg(ks, "setting power mode %d\n", pwrmode);
720
721 pmecr = ks8851_rdreg16(ks, KS_PMECR);
722 pmecr &= ~PMECR_PM_MASK;
723 pmecr |= pwrmode;
724
725 ks8851_wrreg16(ks, KS_PMECR, pmecr);
726}
727
728/**
729 * ks8851_net_open - open network device
730 * @dev: The network device being opened.
731 *
732 * Called when the network device is marked active, such as a user executing
733 * 'ifconfig up' on the device.
734 */
735static int ks8851_net_open(struct net_device *dev)
736{
737 struct ks8851_net *ks = netdev_priv(dev);
738
739 /* lock the card, even if we may not actually be doing anything
740 * else at the moment */
741 mutex_lock(&ks->lock);
742
743 if (netif_msg_ifup(ks))
744 ks_dbg(ks, "opening %s\n", dev->name);
745
746 /* bring chip out of any power saving mode it was in */
747 ks8851_set_powermode(ks, PMECR_PM_NORMAL);
748
749 /* issue a soft reset to the RX/TX QMU to put it into a known
750 * state. */
751 ks8851_soft_reset(ks, GRR_QMU);
752
753 /* setup transmission parameters */
754
755 ks8851_wrreg16(ks, KS_TXCR, (TXCR_TXE | /* enable transmit process */
756 TXCR_TXPE | /* pad to min length */
757 TXCR_TXCRC | /* add CRC */
758 TXCR_TXFCE)); /* enable flow control */
759
760 /* auto-increment tx data, reset tx pointer */
761 ks8851_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
762
763 /* setup receiver control */
764
765 ks8851_wrreg16(ks, KS_RXCR1, (RXCR1_RXPAFMA | /* from mac filter */
766 RXCR1_RXFCE | /* enable flow control */
767 RXCR1_RXBE | /* broadcast enable */
768 RXCR1_RXUE | /* unicast enable */
769 RXCR1_RXE)); /* enable rx block */
770
771 /* transfer entire frames out in one go */
772 ks8851_wrreg16(ks, KS_RXCR2, RXCR2_SRDBL_FRAME);
773
774 /* set receive counter timeouts */
775 ks8851_wrreg16(ks, KS_RXDTTR, 1000); /* 1ms after first frame to IRQ */
776 ks8851_wrreg16(ks, KS_RXDBCTR, 4096); /* >4Kbytes in buffer to IRQ */
777 ks8851_wrreg16(ks, KS_RXFCTR, 10); /* 10 frames to IRQ */
778
779 ks->rc_rxqcr = (RXQCR_RXFCTE | /* IRQ on frame count exceeded */
780 RXQCR_RXDBCTE | /* IRQ on byte count exceeded */
781 RXQCR_RXDTTE); /* IRQ on time exceeded */
782
783 ks8851_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr);
784
785 /* clear then enable interrupts */
786
787#define STD_IRQ (IRQ_LCI | /* Link Change */ \
788 IRQ_TXI | /* TX done */ \
789 IRQ_RXI | /* RX done */ \
790 IRQ_SPIBEI | /* SPI bus error */ \
791 IRQ_TXPSI | /* TX process stop */ \
792 IRQ_RXPSI) /* RX process stop */
793
794 ks->rc_ier = STD_IRQ;
795 ks8851_wrreg16(ks, KS_ISR, STD_IRQ);
796 ks8851_wrreg16(ks, KS_IER, STD_IRQ);
797
798 netif_start_queue(ks->netdev);
799
800 if (netif_msg_ifup(ks))
801 ks_dbg(ks, "network device %s up\n", dev->name);
802
803 mutex_unlock(&ks->lock);
804 return 0;
805}
806
807/**
808 * ks8851_net_stop - close network device
809 * @dev: The device being closed.
810 *
811 * Called to close down a network device which has been active. Cancell any
812 * work, shutdown the RX and TX process and then place the chip into a low
813 * power state whilst it is not being used.
814 */
815static int ks8851_net_stop(struct net_device *dev)
816{
817 struct ks8851_net *ks = netdev_priv(dev);
818
819 if (netif_msg_ifdown(ks))
820 ks_info(ks, "%s: shutting down\n", dev->name);
821
822 netif_stop_queue(dev);
823
824 mutex_lock(&ks->lock);
825
826 /* stop any outstanding work */
827 flush_work(&ks->irq_work);
828 flush_work(&ks->tx_work);
829 flush_work(&ks->rxctrl_work);
830
831 /* turn off the IRQs and ack any outstanding */
832 ks8851_wrreg16(ks, KS_IER, 0x0000);
833 ks8851_wrreg16(ks, KS_ISR, 0xffff);
834
835 /* shutdown RX process */
836 ks8851_wrreg16(ks, KS_RXCR1, 0x0000);
837
838 /* shutdown TX process */
839 ks8851_wrreg16(ks, KS_TXCR, 0x0000);
840
841 /* set powermode to soft power down to save power */
842 ks8851_set_powermode(ks, PMECR_PM_SOFTDOWN);
843
844 /* ensure any queued tx buffers are dumped */
845 while (!skb_queue_empty(&ks->txq)) {
846 struct sk_buff *txb = skb_dequeue(&ks->txq);
847
848 if (netif_msg_ifdown(ks))
849 ks_dbg(ks, "%s: freeing txb %p\n", __func__, txb);
850
851 dev_kfree_skb(txb);
852 }
853
854 mutex_unlock(&ks->lock);
855 return 0;
856}
857
858/**
859 * ks8851_start_xmit - transmit packet
860 * @skb: The buffer to transmit
861 * @dev: The device used to transmit the packet.
862 *
863 * Called by the network layer to transmit the @skb. Queue the packet for
864 * the device and schedule the necessary work to transmit the packet when
865 * it is free.
866 *
867 * We do this to firstly avoid sleeping with the network device locked,
868 * and secondly so we can round up more than one packet to transmit which
869 * means we can try and avoid generating too many transmit done interrupts.
870 */
871static int ks8851_start_xmit(struct sk_buff *skb, struct net_device *dev)
872{
873 struct ks8851_net *ks = netdev_priv(dev);
874 unsigned needed = calc_txlen(skb->len);
875 int ret = NETDEV_TX_OK;
876
877 if (netif_msg_tx_queued(ks))
878 ks_dbg(ks, "%s: skb %p, %d@%p\n", __func__,
879 skb, skb->len, skb->data);
880
881 spin_lock(&ks->statelock);
882
883 if (needed > ks->tx_space) {
884 netif_stop_queue(dev);
885 ret = NETDEV_TX_BUSY;
886 } else {
887 ks->tx_space -= needed;
888 skb_queue_tail(&ks->txq, skb);
889 }
890
891 spin_unlock(&ks->statelock);
892 schedule_work(&ks->tx_work);
893
894 return ret;
895}
896
897/**
898 * ks8851_rxctrl_work - work handler to change rx mode
899 * @work: The work structure this belongs to.
900 *
901 * Lock the device and issue the necessary changes to the receive mode from
902 * the network device layer. This is done so that we can do this without
903 * having to sleep whilst holding the network device lock.
904 *
905 * Since the recommendation from Micrel is that the RXQ is shutdown whilst the
906 * receive parameters are programmed, we issue a write to disable the RXQ and
907 * then wait for the interrupt handler to be triggered once the RXQ shutdown is
908 * complete. The interrupt handler then writes the new values into the chip.
909 */
910static void ks8851_rxctrl_work(struct work_struct *work)
911{
912 struct ks8851_net *ks = container_of(work, struct ks8851_net, rxctrl_work);
913
914 mutex_lock(&ks->lock);
915
916 /* need to shutdown RXQ before modifying filter parameters */
917 ks8851_wrreg16(ks, KS_RXCR1, 0x00);
918
919 mutex_unlock(&ks->lock);
920}
921
922static void ks8851_set_rx_mode(struct net_device *dev)
923{
924 struct ks8851_net *ks = netdev_priv(dev);
925 struct ks8851_rxctrl rxctrl;
926
927 memset(&rxctrl, 0, sizeof(rxctrl));
928
929 if (dev->flags & IFF_PROMISC) {
930 /* interface to receive everything */
931
932 rxctrl.rxcr1 = RXCR1_RXAE | RXCR1_RXINVF;
933 } else if (dev->flags & IFF_ALLMULTI) {
934 /* accept all multicast packets */
935
936 rxctrl.rxcr1 = (RXCR1_RXME | RXCR1_RXAE |
937 RXCR1_RXPAFMA | RXCR1_RXMAFMA);
938 } else if (dev->flags & IFF_MULTICAST && dev->mc_count > 0) {
939 struct dev_mc_list *mcptr = dev->mc_list;
940 u32 crc;
941 int i;
942
943 /* accept some multicast */
944
945 for (i = dev->mc_count; i > 0; i--) {
946 crc = ether_crc(ETH_ALEN, mcptr->dmi_addr);
947 crc >>= (32 - 6); /* get top six bits */
948
949 rxctrl.mchash[crc >> 4] |= (1 << (crc & 0xf));
950 mcptr = mcptr->next;
951 }
952
953 rxctrl.rxcr1 = RXCR1_RXME | RXCR1_RXAE | RXCR1_RXPAFMA;
954 } else {
955 /* just accept broadcast / unicast */
956 rxctrl.rxcr1 = RXCR1_RXPAFMA;
957 }
958
959 rxctrl.rxcr1 |= (RXCR1_RXUE | /* unicast enable */
960 RXCR1_RXBE | /* broadcast enable */
961 RXCR1_RXE | /* RX process enable */
962 RXCR1_RXFCE); /* enable flow control */
963
964 rxctrl.rxcr2 |= RXCR2_SRDBL_FRAME;
965
966 /* schedule work to do the actual set of the data if needed */
967
968 spin_lock(&ks->statelock);
969
970 if (memcmp(&rxctrl, &ks->rxctrl, sizeof(rxctrl)) != 0) {
971 memcpy(&ks->rxctrl, &rxctrl, sizeof(ks->rxctrl));
972 schedule_work(&ks->rxctrl_work);
973 }
974
975 spin_unlock(&ks->statelock);
976}
977
978static int ks8851_set_mac_address(struct net_device *dev, void *addr)
979{
980 struct sockaddr *sa = addr;
981
982 if (netif_running(dev))
983 return -EBUSY;
984
985 if (!is_valid_ether_addr(sa->sa_data))
986 return -EADDRNOTAVAIL;
987
988 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
989 return ks8851_write_mac_addr(dev);
990}
991
992static int ks8851_net_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
993{
994 struct ks8851_net *ks = netdev_priv(dev);
995
996 if (!netif_running(dev))
997 return -EINVAL;
998
999 return generic_mii_ioctl(&ks->mii, if_mii(req), cmd, NULL);
1000}
1001
1002static const struct net_device_ops ks8851_netdev_ops = {
1003 .ndo_open = ks8851_net_open,
1004 .ndo_stop = ks8851_net_stop,
1005 .ndo_do_ioctl = ks8851_net_ioctl,
1006 .ndo_start_xmit = ks8851_start_xmit,
1007 .ndo_set_mac_address = ks8851_set_mac_address,
1008 .ndo_set_rx_mode = ks8851_set_rx_mode,
1009 .ndo_change_mtu = eth_change_mtu,
1010 .ndo_validate_addr = eth_validate_addr,
1011};
1012
1013/* ethtool support */
1014
1015static void ks8851_get_drvinfo(struct net_device *dev,
1016 struct ethtool_drvinfo *di)
1017{
1018 strlcpy(di->driver, "KS8851", sizeof(di->driver));
1019 strlcpy(di->version, "1.00", sizeof(di->version));
1020 strlcpy(di->bus_info, dev_name(dev->dev.parent), sizeof(di->bus_info));
1021}
1022
1023static u32 ks8851_get_msglevel(struct net_device *dev)
1024{
1025 struct ks8851_net *ks = netdev_priv(dev);
1026 return ks->msg_enable;
1027}
1028
1029static void ks8851_set_msglevel(struct net_device *dev, u32 to)
1030{
1031 struct ks8851_net *ks = netdev_priv(dev);
1032 ks->msg_enable = to;
1033}
1034
1035static int ks8851_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1036{
1037 struct ks8851_net *ks = netdev_priv(dev);
1038 return mii_ethtool_gset(&ks->mii, cmd);
1039}
1040
1041static int ks8851_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1042{
1043 struct ks8851_net *ks = netdev_priv(dev);
1044 return mii_ethtool_sset(&ks->mii, cmd);
1045}
1046
1047static u32 ks8851_get_link(struct net_device *dev)
1048{
1049 struct ks8851_net *ks = netdev_priv(dev);
1050 return mii_link_ok(&ks->mii);
1051}
1052
1053static int ks8851_nway_reset(struct net_device *dev)
1054{
1055 struct ks8851_net *ks = netdev_priv(dev);
1056 return mii_nway_restart(&ks->mii);
1057}
1058
1059static const struct ethtool_ops ks8851_ethtool_ops = {
1060 .get_drvinfo = ks8851_get_drvinfo,
1061 .get_msglevel = ks8851_get_msglevel,
1062 .set_msglevel = ks8851_set_msglevel,
1063 .get_settings = ks8851_get_settings,
1064 .set_settings = ks8851_set_settings,
1065 .get_link = ks8851_get_link,
1066 .nway_reset = ks8851_nway_reset,
1067};
1068
1069/* MII interface controls */
1070
1071/**
1072 * ks8851_phy_reg - convert MII register into a KS8851 register
1073 * @reg: MII register number.
1074 *
1075 * Return the KS8851 register number for the corresponding MII PHY register
1076 * if possible. Return zero if the MII register has no direct mapping to the
1077 * KS8851 register set.
1078 */
1079static int ks8851_phy_reg(int reg)
1080{
1081 switch (reg) {
1082 case MII_BMCR:
1083 return KS_P1MBCR;
1084 case MII_BMSR:
1085 return KS_P1MBSR;
1086 case MII_PHYSID1:
1087 return KS_PHY1ILR;
1088 case MII_PHYSID2:
1089 return KS_PHY1IHR;
1090 case MII_ADVERTISE:
1091 return KS_P1ANAR;
1092 case MII_LPA:
1093 return KS_P1ANLPR;
1094 }
1095
1096 return 0x0;
1097}
1098
1099/**
1100 * ks8851_phy_read - MII interface PHY register read.
1101 * @dev: The network device the PHY is on.
1102 * @phy_addr: Address of PHY (ignored as we only have one)
1103 * @reg: The register to read.
1104 *
1105 * This call reads data from the PHY register specified in @reg. Since the
1106 * device does not support all the MII registers, the non-existant values
1107 * are always returned as zero.
1108 *
1109 * We return zero for unsupported registers as the MII code does not check
1110 * the value returned for any error status, and simply returns it to the
1111 * caller. The mii-tool that the driver was tested with takes any -ve error
1112 * as real PHY capabilities, thus displaying incorrect data to the user.
1113 */
1114static int ks8851_phy_read(struct net_device *dev, int phy_addr, int reg)
1115{
1116 struct ks8851_net *ks = netdev_priv(dev);
1117 int ksreg;
1118 int result;
1119
1120 ksreg = ks8851_phy_reg(reg);
1121 if (!ksreg)
1122 return 0x0; /* no error return allowed, so use zero */
1123
1124 mutex_lock(&ks->lock);
1125 result = ks8851_rdreg16(ks, ksreg);
1126 mutex_unlock(&ks->lock);
1127
1128 return result;
1129}
1130
1131static void ks8851_phy_write(struct net_device *dev,
1132 int phy, int reg, int value)
1133{
1134 struct ks8851_net *ks = netdev_priv(dev);
1135 int ksreg;
1136
1137 ksreg = ks8851_phy_reg(reg);
1138 if (ksreg) {
1139 mutex_lock(&ks->lock);
1140 ks8851_wrreg16(ks, ksreg, value);
1141 mutex_unlock(&ks->lock);
1142 }
1143}
1144
1145/**
1146 * ks8851_read_selftest - read the selftest memory info.
1147 * @ks: The device state
1148 *
1149 * Read and check the TX/RX memory selftest information.
1150 */
1151static int ks8851_read_selftest(struct ks8851_net *ks)
1152{
1153 unsigned both_done = MBIR_TXMBF | MBIR_RXMBF;
1154 int ret = 0;
1155 unsigned rd;
1156
1157 rd = ks8851_rdreg16(ks, KS_MBIR);
1158
1159 if ((rd & both_done) != both_done) {
1160 ks_warn(ks, "Memory selftest not finished\n");
1161 return 0;
1162 }
1163
1164 if (rd & MBIR_TXMBFA) {
1165 ks_err(ks, "TX memory selftest fail\n");
1166 ret |= 1;
1167 }
1168
1169 if (rd & MBIR_RXMBFA) {
1170 ks_err(ks, "RX memory selftest fail\n");
1171 ret |= 2;
1172 }
1173
1174 return 0;
1175}
1176
1177/* driver bus management functions */
1178
1179static int __devinit ks8851_probe(struct spi_device *spi)
1180{
1181 struct net_device *ndev;
1182 struct ks8851_net *ks;
1183 int ret;
1184
1185 ndev = alloc_etherdev(sizeof(struct ks8851_net));
1186 if (!ndev) {
1187 dev_err(&spi->dev, "failed to alloc ethernet device\n");
1188 return -ENOMEM;
1189 }
1190
1191 spi->bits_per_word = 8;
1192
1193 ks = netdev_priv(ndev);
1194
1195 ks->netdev = ndev;
1196 ks->spidev = spi;
1197 ks->tx_space = 6144;
1198
1199 mutex_init(&ks->lock);
1200 spin_lock_init(&ks->statelock);
1201
1202 INIT_WORK(&ks->tx_work, ks8851_tx_work);
1203 INIT_WORK(&ks->irq_work, ks8851_irq_work);
1204 INIT_WORK(&ks->rxctrl_work, ks8851_rxctrl_work);
1205
1206 /* initialise pre-made spi transfer messages */
1207
1208 spi_message_init(&ks->spi_msg1);
1209 spi_message_add_tail(&ks->spi_xfer1, &ks->spi_msg1);
1210
1211 spi_message_init(&ks->spi_msg2);
1212 spi_message_add_tail(&ks->spi_xfer2[0], &ks->spi_msg2);
1213 spi_message_add_tail(&ks->spi_xfer2[1], &ks->spi_msg2);
1214
1215 /* setup mii state */
1216 ks->mii.dev = ndev;
1217 ks->mii.phy_id = 1,
1218 ks->mii.phy_id_mask = 1;
1219 ks->mii.reg_num_mask = 0xf;
1220 ks->mii.mdio_read = ks8851_phy_read;
1221 ks->mii.mdio_write = ks8851_phy_write;
1222
1223 dev_info(&spi->dev, "message enable is %d\n", msg_enable);
1224
1225 /* set the default message enable */
1226 ks->msg_enable = netif_msg_init(msg_enable, (NETIF_MSG_DRV |
1227 NETIF_MSG_PROBE |
1228 NETIF_MSG_LINK));
1229
1230 skb_queue_head_init(&ks->txq);
1231
1232 SET_ETHTOOL_OPS(ndev, &ks8851_ethtool_ops);
1233 SET_NETDEV_DEV(ndev, &spi->dev);
1234
1235 dev_set_drvdata(&spi->dev, ks);
1236
1237 ndev->if_port = IF_PORT_100BASET;
1238 ndev->netdev_ops = &ks8851_netdev_ops;
1239 ndev->irq = spi->irq;
1240
1241 /* simple check for a valid chip being connected to the bus */
1242
1243 if ((ks8851_rdreg16(ks, KS_CIDER) & ~CIDER_REV_MASK) != CIDER_ID) {
1244 dev_err(&spi->dev, "failed to read device ID\n");
1245 ret = -ENODEV;
1246 goto err_id;
1247 }
1248
1249 ks8851_read_selftest(ks);
1250 ks8851_init_mac(ks);
1251
1252 ret = request_irq(spi->irq, ks8851_irq, IRQF_TRIGGER_LOW,
1253 ndev->name, ks);
1254 if (ret < 0) {
1255 dev_err(&spi->dev, "failed to get irq\n");
1256 goto err_irq;
1257 }
1258
1259 ret = register_netdev(ndev);
1260 if (ret) {
1261 dev_err(&spi->dev, "failed to register network device\n");
1262 goto err_netdev;
1263 }
1264
1265 dev_info(&spi->dev, "revision %d, MAC %pM, IRQ %d\n",
1266 CIDER_REV_GET(ks8851_rdreg16(ks, KS_CIDER)),
1267 ndev->dev_addr, ndev->irq);
1268
1269 return 0;
1270
1271
1272err_netdev:
1273 free_irq(ndev->irq, ndev);
1274
1275err_id:
1276err_irq:
1277 free_netdev(ndev);
1278 return ret;
1279}
1280
1281static int __devexit ks8851_remove(struct spi_device *spi)
1282{
1283 struct ks8851_net *priv = dev_get_drvdata(&spi->dev);
1284
1285 if (netif_msg_drv(priv))
1286 dev_info(&spi->dev, "remove");
1287
1288 unregister_netdev(priv->netdev);
1289 free_irq(spi->irq, priv);
1290 free_netdev(priv->netdev);
1291
1292 return 0;
1293}
1294
1295static struct spi_driver ks8851_driver = {
1296 .driver = {
1297 .name = "ks8851",
1298 .owner = THIS_MODULE,
1299 },
1300 .probe = ks8851_probe,
1301 .remove = __devexit_p(ks8851_remove),
1302};
1303
1304static int __init ks8851_init(void)
1305{
1306 return spi_register_driver(&ks8851_driver);
1307}
1308
1309static void __exit ks8851_exit(void)
1310{
1311 spi_unregister_driver(&ks8851_driver);
1312}
1313
1314module_init(ks8851_init);
1315module_exit(ks8851_exit);
1316
1317MODULE_DESCRIPTION("KS8851 Network driver");
1318MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1319MODULE_LICENSE("GPL");
1320
1321module_param_named(message, msg_enable, int, 0);
1322MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
diff --git a/drivers/net/ks8851.h b/drivers/net/ks8851.h
new file mode 100644
index 000000000000..85abe147afbf
--- /dev/null
+++ b/drivers/net/ks8851.h
@@ -0,0 +1,296 @@
1/* drivers/net/ks8851.h
2 *
3 * Copyright 2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * KS8851 register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#define KS_CCR 0x08
14#define CCR_EEPROM (1 << 9)
15#define CCR_SPI (1 << 8)
16#define CCR_32PIN (1 << 0)
17
18/* MAC address registers */
19#define KS_MARL 0x10
20#define KS_MARM 0x12
21#define KS_MARH 0x14
22
23#define KS_OBCR 0x20
24#define OBCR_ODS_16mA (1 << 6)
25
26#define KS_EEPCR 0x22
27#define EEPCR_EESA (1 << 4)
28#define EEPCR_EESB (1 << 3)
29#define EEPCR_EEDO (1 << 2)
30#define EEPCR_EESCK (1 << 1)
31#define EEPCR_EECS (1 << 0)
32
33#define KS_MBIR 0x24
34#define MBIR_TXMBF (1 << 12)
35#define MBIR_TXMBFA (1 << 11)
36#define MBIR_RXMBF (1 << 4)
37#define MBIR_RXMBFA (1 << 3)
38
39#define KS_GRR 0x26
40#define GRR_QMU (1 << 1)
41#define GRR_GSR (1 << 0)
42
43#define KS_WFCR 0x2A
44#define WFCR_MPRXE (1 << 7)
45#define WFCR_WF3E (1 << 3)
46#define WFCR_WF2E (1 << 2)
47#define WFCR_WF1E (1 << 1)
48#define WFCR_WF0E (1 << 0)
49
50#define KS_WF0CRC0 0x30
51#define KS_WF0CRC1 0x32
52#define KS_WF0BM0 0x34
53#define KS_WF0BM1 0x36
54#define KS_WF0BM2 0x38
55#define KS_WF0BM3 0x3A
56
57#define KS_WF1CRC0 0x40
58#define KS_WF1CRC1 0x42
59#define KS_WF1BM0 0x44
60#define KS_WF1BM1 0x46
61#define KS_WF1BM2 0x48
62#define KS_WF1BM3 0x4A
63
64#define KS_WF2CRC0 0x50
65#define KS_WF2CRC1 0x52
66#define KS_WF2BM0 0x54
67#define KS_WF2BM1 0x56
68#define KS_WF2BM2 0x58
69#define KS_WF2BM3 0x5A
70
71#define KS_WF3CRC0 0x60
72#define KS_WF3CRC1 0x62
73#define KS_WF3BM0 0x64
74#define KS_WF3BM1 0x66
75#define KS_WF3BM2 0x68
76#define KS_WF3BM3 0x6A
77
78#define KS_TXCR 0x70
79#define TXCR_TCGICMP (1 << 8)
80#define TXCR_TCGUDP (1 << 7)
81#define TXCR_TCGTCP (1 << 6)
82#define TXCR_TCGIP (1 << 5)
83#define TXCR_FTXQ (1 << 4)
84#define TXCR_TXFCE (1 << 3)
85#define TXCR_TXPE (1 << 2)
86#define TXCR_TXCRC (1 << 1)
87#define TXCR_TXE (1 << 0)
88
89#define KS_TXSR 0x72
90#define TXSR_TXLC (1 << 13)
91#define TXSR_TXMC (1 << 12)
92#define TXSR_TXFID_MASK (0x3f << 0)
93#define TXSR_TXFID_SHIFT (0)
94#define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
95
96#define KS_RXCR1 0x74
97#define RXCR1_FRXQ (1 << 15)
98#define RXCR1_RXUDPFCC (1 << 14)
99#define RXCR1_RXTCPFCC (1 << 13)
100#define RXCR1_RXIPFCC (1 << 12)
101#define RXCR1_RXPAFMA (1 << 11)
102#define RXCR1_RXFCE (1 << 10)
103#define RXCR1_RXEFE (1 << 9)
104#define RXCR1_RXMAFMA (1 << 8)
105#define RXCR1_RXBE (1 << 7)
106#define RXCR1_RXME (1 << 6)
107#define RXCR1_RXUE (1 << 5)
108#define RXCR1_RXAE (1 << 4)
109#define RXCR1_RXINVF (1 << 1)
110#define RXCR1_RXE (1 << 0)
111
112#define KS_RXCR2 0x76
113#define RXCR2_SRDBL_MASK (0x7 << 5)
114#define RXCR2_SRDBL_SHIFT (5)
115#define RXCR2_SRDBL_4B (0x0 << 5)
116#define RXCR2_SRDBL_8B (0x1 << 5)
117#define RXCR2_SRDBL_16B (0x2 << 5)
118#define RXCR2_SRDBL_32B (0x3 << 5)
119#define RXCR2_SRDBL_FRAME (0x4 << 5)
120#define RXCR2_IUFFP (1 << 4)
121#define RXCR2_RXIUFCEZ (1 << 3)
122#define RXCR2_UDPLFE (1 << 2)
123#define RXCR2_RXICMPFCC (1 << 1)
124#define RXCR2_RXSAF (1 << 0)
125
126#define KS_TXMIR 0x78
127
128#define KS_RXFHSR 0x7C
129#define RXFSHR_RXFV (1 << 15)
130#define RXFSHR_RXICMPFCS (1 << 13)
131#define RXFSHR_RXIPFCS (1 << 12)
132#define RXFSHR_RXTCPFCS (1 << 11)
133#define RXFSHR_RXUDPFCS (1 << 10)
134#define RXFSHR_RXBF (1 << 7)
135#define RXFSHR_RXMF (1 << 6)
136#define RXFSHR_RXUF (1 << 5)
137#define RXFSHR_RXMR (1 << 4)
138#define RXFSHR_RXFT (1 << 3)
139#define RXFSHR_RXFTL (1 << 2)
140#define RXFSHR_RXRF (1 << 1)
141#define RXFSHR_RXCE (1 << 0)
142
143#define KS_RXFHBCR 0x7E
144#define KS_TXQCR 0x80
145#define TXQCR_AETFE (1 << 2)
146#define TXQCR_TXQMAM (1 << 1)
147#define TXQCR_METFE (1 << 0)
148
149#define KS_RXQCR 0x82
150#define RXQCR_RXDTTS (1 << 12)
151#define RXQCR_RXDBCTS (1 << 11)
152#define RXQCR_RXFCTS (1 << 10)
153#define RXQCR_RXIPHTOE (1 << 9)
154#define RXQCR_RXDTTE (1 << 7)
155#define RXQCR_RXDBCTE (1 << 6)
156#define RXQCR_RXFCTE (1 << 5)
157#define RXQCR_ADRFE (1 << 4)
158#define RXQCR_SDA (1 << 3)
159#define RXQCR_RRXEF (1 << 0)
160
161#define KS_TXFDPR 0x84
162#define TXFDPR_TXFPAI (1 << 14)
163#define TXFDPR_TXFP_MASK (0x7ff << 0)
164#define TXFDPR_TXFP_SHIFT (0)
165
166#define KS_RXFDPR 0x86
167#define RXFDPR_RXFPAI (1 << 14)
168
169#define KS_RXDTTR 0x8C
170#define KS_RXDBCTR 0x8E
171
172#define KS_IER 0x90
173#define KS_ISR 0x92
174#define IRQ_LCI (1 << 15)
175#define IRQ_TXI (1 << 14)
176#define IRQ_RXI (1 << 13)
177#define IRQ_RXOI (1 << 11)
178#define IRQ_TXPSI (1 << 9)
179#define IRQ_RXPSI (1 << 8)
180#define IRQ_TXSAI (1 << 6)
181#define IRQ_RXWFDI (1 << 5)
182#define IRQ_RXMPDI (1 << 4)
183#define IRQ_LDI (1 << 3)
184#define IRQ_EDI (1 << 2)
185#define IRQ_SPIBEI (1 << 1)
186#define IRQ_DEDI (1 << 0)
187
188#define KS_RXFCTR 0x9C
189#define KS_RXFC 0x9D
190#define RXFCTR_RXFC_MASK (0xff << 8)
191#define RXFCTR_RXFC_SHIFT (8)
192#define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
193#define RXFCTR_RXFCT_MASK (0xff << 0)
194#define RXFCTR_RXFCT_SHIFT (0)
195
196#define KS_TXNTFSR 0x9E
197
198#define KS_MAHTR0 0xA0
199#define KS_MAHTR1 0xA2
200#define KS_MAHTR2 0xA4
201#define KS_MAHTR3 0xA6
202
203#define KS_FCLWR 0xB0
204#define KS_FCHWR 0xB2
205#define KS_FCOWR 0xB4
206
207#define KS_CIDER 0xC0
208#define CIDER_ID 0x8870
209#define CIDER_REV_MASK (0x7 << 1)
210#define CIDER_REV_SHIFT (1)
211#define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
212
213#define KS_CGCR 0xC6
214
215#define KS_IACR 0xC8
216#define IACR_RDEN (1 << 12)
217#define IACR_TSEL_MASK (0x3 << 10)
218#define IACR_TSEL_SHIFT (10)
219#define IACR_TSEL_MIB (0x3 << 10)
220#define IACR_ADDR_MASK (0x1f << 0)
221#define IACR_ADDR_SHIFT (0)
222
223#define KS_IADLR 0xD0
224#define KS_IAHDR 0xD2
225
226#define KS_PMECR 0xD4
227#define PMECR_PME_DELAY (1 << 14)
228#define PMECR_PME_POL (1 << 12)
229#define PMECR_WOL_WAKEUP (1 << 11)
230#define PMECR_WOL_MAGICPKT (1 << 10)
231#define PMECR_WOL_LINKUP (1 << 9)
232#define PMECR_WOL_ENERGY (1 << 8)
233#define PMECR_AUTO_WAKE_EN (1 << 7)
234#define PMECR_WAKEUP_NORMAL (1 << 6)
235#define PMECR_WKEVT_MASK (0xf << 2)
236#define PMECR_WKEVT_SHIFT (2)
237#define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
238#define PMECR_WKEVT_ENERGY (0x1 << 2)
239#define PMECR_WKEVT_LINK (0x2 << 2)
240#define PMECR_WKEVT_MAGICPKT (0x4 << 2)
241#define PMECR_WKEVT_FRAME (0x8 << 2)
242#define PMECR_PM_MASK (0x3 << 0)
243#define PMECR_PM_SHIFT (0)
244#define PMECR_PM_NORMAL (0x0 << 0)
245#define PMECR_PM_ENERGY (0x1 << 0)
246#define PMECR_PM_SOFTDOWN (0x2 << 0)
247#define PMECR_PM_POWERSAVE (0x3 << 0)
248
249/* Standard MII PHY data */
250#define KS_P1MBCR 0xE4
251#define KS_P1MBSR 0xE6
252#define KS_PHY1ILR 0xE8
253#define KS_PHY1IHR 0xEA
254#define KS_P1ANAR 0xEC
255#define KS_P1ANLPR 0xEE
256
257#define KS_P1SCLMD 0xF4
258#define P1SCLMD_LEDOFF (1 << 15)
259#define P1SCLMD_TXIDS (1 << 14)
260#define P1SCLMD_RESTARTAN (1 << 13)
261#define P1SCLMD_DISAUTOMDIX (1 << 10)
262#define P1SCLMD_FORCEMDIX (1 << 9)
263#define P1SCLMD_AUTONEGEN (1 << 7)
264#define P1SCLMD_FORCE100 (1 << 6)
265#define P1SCLMD_FORCEFDX (1 << 5)
266#define P1SCLMD_ADV_FLOW (1 << 4)
267#define P1SCLMD_ADV_100BT_FDX (1 << 3)
268#define P1SCLMD_ADV_100BT_HDX (1 << 2)
269#define P1SCLMD_ADV_10BT_FDX (1 << 1)
270#define P1SCLMD_ADV_10BT_HDX (1 << 0)
271
272#define KS_P1CR 0xF6
273#define P1CR_HP_MDIX (1 << 15)
274#define P1CR_REV_POL (1 << 13)
275#define P1CR_OP_100M (1 << 10)
276#define P1CR_OP_FDX (1 << 9)
277#define P1CR_OP_MDI (1 << 7)
278#define P1CR_AN_DONE (1 << 6)
279#define P1CR_LINK_GOOD (1 << 5)
280#define P1CR_PNTR_FLOW (1 << 4)
281#define P1CR_PNTR_100BT_FDX (1 << 3)
282#define P1CR_PNTR_100BT_HDX (1 << 2)
283#define P1CR_PNTR_10BT_FDX (1 << 1)
284#define P1CR_PNTR_10BT_HDX (1 << 0)
285
286/* TX Frame control */
287
288#define TXFR_TXIC (1 << 15)
289#define TXFR_TXFID_MASK (0x3f << 0)
290#define TXFR_TXFID_SHIFT (0)
291
292/* SPI frame opcodes */
293#define KS_SPIOP_RD (0x00)
294#define KS_SPIOP_WR (0x40)
295#define KS_SPIOP_RXFIFO (0x80)
296#define KS_SPIOP_TXFIFO (0xC0)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 23:42:43 -0500