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authorSujith <Sujith.Manoharan@atheros.com>2009-02-09 02:57:12 -0500
committerJohn W. Linville <linville@tuxdriver.com>2009-02-13 13:45:05 -0500
commitcbe61d8a41210600bc76b212edcd4dc0f55c014f (patch)
treed8bd8e43d3556c58d410f1bef0d2ca3bf7d75c92
parentba52da58be0acf3b7775972b2b5234ce64388c79 (diff)
ath9k: Merge ath_hal and ath_hal_5416 structures
Finally, merge these structures and have a single HW specific data structure. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat
-rw-r--r--drivers/net/wireless/ath9k/ahb.c4
-rw-r--r--drivers/net/wireless/ath9k/ani.c232
-rw-r--r--drivers/net/wireless/ath9k/ani.h22
-rw-r--r--drivers/net/wireless/ath9k/ath9k.h6
-rw-r--r--drivers/net/wireless/ath9k/beacon.c12
-rw-r--r--drivers/net/wireless/ath9k/calib.c175
-rw-r--r--drivers/net/wireless/ath9k/calib.h20
-rw-r--r--drivers/net/wireless/ath9k/debug.c2
-rw-r--r--drivers/net/wireless/ath9k/eeprom.c251
-rw-r--r--drivers/net/wireless/ath9k/eeprom.h36
-rw-r--r--drivers/net/wireless/ath9k/hw.c675
-rw-r--r--drivers/net/wireless/ath9k/hw.h134
-rw-r--r--drivers/net/wireless/ath9k/mac.c144
-rw-r--r--drivers/net/wireless/ath9k/mac.h64
-rw-r--r--drivers/net/wireless/ath9k/main.c22
-rw-r--r--drivers/net/wireless/ath9k/pci.c4
-rw-r--r--drivers/net/wireless/ath9k/phy.c194
-rw-r--r--drivers/net/wireless/ath9k/phy.h14
-rw-r--r--drivers/net/wireless/ath9k/recv.c10
-rw-r--r--drivers/net/wireless/ath9k/regd.c18
-rw-r--r--drivers/net/wireless/ath9k/regd.h14
-rw-r--r--drivers/net/wireless/ath9k/xmit.c12
22 files changed, 956 insertions, 1109 deletions
diff --git a/drivers/net/wireless/ath9k/ahb.c b/drivers/net/wireless/ath9k/ahb.c
index d254b357804d..391c9fd3b646 100644
--- a/drivers/net/wireless/ath9k/ahb.c
+++ b/drivers/net/wireless/ath9k/ahb.c
@@ -32,7 +32,7 @@ static void ath_ahb_cleanup(struct ath_softc *sc)
32 iounmap(sc->mem); 32 iounmap(sc->mem);
33} 33}
34 34
35static bool ath_ahb_eeprom_read(struct ath_hal *ah, u32 off, u16 *data) 35static bool ath_ahb_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
36{ 36{
37 struct ath_softc *sc = ah->ah_sc; 37 struct ath_softc *sc = ah->ah_sc;
38 struct platform_device *pdev = to_platform_device(sc->dev); 38 struct platform_device *pdev = to_platform_device(sc->dev);
@@ -65,7 +65,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
65 struct resource *res; 65 struct resource *res;
66 int irq; 66 int irq;
67 int ret = 0; 67 int ret = 0;
68 struct ath_hal *ah; 68 struct ath_hw *ah;
69 69
70 if (!pdev->dev.platform_data) { 70 if (!pdev->dev.platform_data) {
71 dev_err(&pdev->dev, "no platform data specified\n"); 71 dev_err(&pdev->dev, "no platform data specified\n");
diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c
index 9cebf0e78a76..6bd2d5766019 100644
--- a/drivers/net/wireless/ath9k/ani.c
+++ b/drivers/net/wireless/ath9k/ani.c
@@ -16,18 +16,17 @@
16 16
17#include "ath9k.h" 17#include "ath9k.h"
18 18
19static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah, 19static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
20 struct ath9k_channel *chan) 20 struct ath9k_channel *chan)
21{ 21{
22 struct ath_hal_5416 *ahp = AH5416(ah);
23 int i; 22 int i;
24 23
25 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { 24 for (i = 0; i < ARRAY_SIZE(ah->ah_ani); i++) {
26 if (ahp->ah_ani[i].c && 25 if (ah->ah_ani[i].c &&
27 ahp->ah_ani[i].c->channel == chan->channel) 26 ah->ah_ani[i].c->channel == chan->channel)
28 return i; 27 return i;
29 if (ahp->ah_ani[i].c == NULL) { 28 if (ah->ah_ani[i].c == NULL) {
30 ahp->ah_ani[i].c = chan; 29 ah->ah_ani[i].c = chan;
31 return i; 30 return i;
32 } 31 }
33 } 32 }
@@ -38,41 +37,40 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
38 return 0; 37 return 0;
39} 38}
40 39
41static bool ath9k_hw_ani_control(struct ath_hal *ah, 40static bool ath9k_hw_ani_control(struct ath_hw *ah,
42 enum ath9k_ani_cmd cmd, int param) 41 enum ath9k_ani_cmd cmd, int param)
43{ 42{
44 struct ath_hal_5416 *ahp = AH5416(ah); 43 struct ar5416AniState *aniState = ah->ah_curani;
45 struct ar5416AniState *aniState = ahp->ah_curani;
46 44
47 switch (cmd & ahp->ah_ani_function) { 45 switch (cmd & ah->ah_ani_function) {
48 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ 46 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
49 u32 level = param; 47 u32 level = param;
50 48
51 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) { 49 if (level >= ARRAY_SIZE(ah->ah_totalSizeDesired)) {
52 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 50 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
53 "level out of range (%u > %u)\n", 51 "level out of range (%u > %u)\n",
54 level, 52 level,
55 (unsigned)ARRAY_SIZE(ahp->ah_totalSizeDesired)); 53 (unsigned)ARRAY_SIZE(ah->ah_totalSizeDesired));
56 return false; 54 return false;
57 } 55 }
58 56
59 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 57 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
60 AR_PHY_DESIRED_SZ_TOT_DES, 58 AR_PHY_DESIRED_SZ_TOT_DES,
61 ahp->ah_totalSizeDesired[level]); 59 ah->ah_totalSizeDesired[level]);
62 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, 60 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
63 AR_PHY_AGC_CTL1_COARSE_LOW, 61 AR_PHY_AGC_CTL1_COARSE_LOW,
64 ahp->ah_coarseLow[level]); 62 ah->ah_coarseLow[level]);
65 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, 63 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
66 AR_PHY_AGC_CTL1_COARSE_HIGH, 64 AR_PHY_AGC_CTL1_COARSE_HIGH,
67 ahp->ah_coarseHigh[level]); 65 ah->ah_coarseHigh[level]);
68 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 66 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
69 AR_PHY_FIND_SIG_FIRPWR, 67 AR_PHY_FIND_SIG_FIRPWR,
70 ahp->ah_firpwr[level]); 68 ah->ah_firpwr[level]);
71 69
72 if (level > aniState->noiseImmunityLevel) 70 if (level > aniState->noiseImmunityLevel)
73 ahp->ah_stats.ast_ani_niup++; 71 ah->ah_stats.ast_ani_niup++;
74 else if (level < aniState->noiseImmunityLevel) 72 else if (level < aniState->noiseImmunityLevel)
75 ahp->ah_stats.ast_ani_nidown++; 73 ah->ah_stats.ast_ani_nidown++;
76 aniState->noiseImmunityLevel = level; 74 aniState->noiseImmunityLevel = level;
77 break; 75 break;
78 } 76 }
@@ -126,9 +124,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
126 124
127 if (!on != aniState->ofdmWeakSigDetectOff) { 125 if (!on != aniState->ofdmWeakSigDetectOff) {
128 if (on) 126 if (on)
129 ahp->ah_stats.ast_ani_ofdmon++; 127 ah->ah_stats.ast_ani_ofdmon++;
130 else 128 else
131 ahp->ah_stats.ast_ani_ofdmoff++; 129 ah->ah_stats.ast_ani_ofdmoff++;
132 aniState->ofdmWeakSigDetectOff = !on; 130 aniState->ofdmWeakSigDetectOff = !on;
133 } 131 }
134 break; 132 break;
@@ -142,9 +140,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
142 weakSigThrCck[high]); 140 weakSigThrCck[high]);
143 if (high != aniState->cckWeakSigThreshold) { 141 if (high != aniState->cckWeakSigThreshold) {
144 if (high) 142 if (high)
145 ahp->ah_stats.ast_ani_cckhigh++; 143 ah->ah_stats.ast_ani_cckhigh++;
146 else 144 else
147 ahp->ah_stats.ast_ani_ccklow++; 145 ah->ah_stats.ast_ani_ccklow++;
148 aniState->cckWeakSigThreshold = high; 146 aniState->cckWeakSigThreshold = high;
149 } 147 }
150 break; 148 break;
@@ -164,9 +162,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
164 AR_PHY_FIND_SIG_FIRSTEP, 162 AR_PHY_FIND_SIG_FIRSTEP,
165 firstep[level]); 163 firstep[level]);
166 if (level > aniState->firstepLevel) 164 if (level > aniState->firstepLevel)
167 ahp->ah_stats.ast_ani_stepup++; 165 ah->ah_stats.ast_ani_stepup++;
168 else if (level < aniState->firstepLevel) 166 else if (level < aniState->firstepLevel)
169 ahp->ah_stats.ast_ani_stepdown++; 167 ah->ah_stats.ast_ani_stepdown++;
170 aniState->firstepLevel = level; 168 aniState->firstepLevel = level;
171 break; 169 break;
172 } 170 }
@@ -187,9 +185,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
187 AR_PHY_TIMING5_CYCPWR_THR1, 185 AR_PHY_TIMING5_CYCPWR_THR1,
188 cycpwrThr1[level]); 186 cycpwrThr1[level]);
189 if (level > aniState->spurImmunityLevel) 187 if (level > aniState->spurImmunityLevel)
190 ahp->ah_stats.ast_ani_spurup++; 188 ah->ah_stats.ast_ani_spurup++;
191 else if (level < aniState->spurImmunityLevel) 189 else if (level < aniState->spurImmunityLevel)
192 ahp->ah_stats.ast_ani_spurdown++; 190 ah->ah_stats.ast_ani_spurdown++;
193 aniState->spurImmunityLevel = level; 191 aniState->spurImmunityLevel = level;
194 break; 192 break;
195 } 193 }
@@ -220,7 +218,7 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
220 return true; 218 return true;
221} 219}
222 220
223static void ath9k_hw_update_mibstats(struct ath_hal *ah, 221static void ath9k_hw_update_mibstats(struct ath_hw *ah,
224 struct ath9k_mib_stats *stats) 222 struct ath9k_mib_stats *stats)
225{ 223{
226 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL); 224 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
@@ -230,18 +228,17 @@ static void ath9k_hw_update_mibstats(struct ath_hal *ah,
230 stats->beacons += REG_READ(ah, AR_BEACON_CNT); 228 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
231} 229}
232 230
233static void ath9k_ani_restart(struct ath_hal *ah) 231static void ath9k_ani_restart(struct ath_hw *ah)
234{ 232{
235 struct ath_hal_5416 *ahp = AH5416(ah);
236 struct ar5416AniState *aniState; 233 struct ar5416AniState *aniState;
237 234
238 if (!DO_ANI(ah)) 235 if (!DO_ANI(ah))
239 return; 236 return;
240 237
241 aniState = ahp->ah_curani; 238 aniState = ah->ah_curani;
242 239
243 aniState->listenTime = 0; 240 aniState->listenTime = 0;
244 if (ahp->ah_hasHwPhyCounters) { 241 if (ah->ah_hasHwPhyCounters) {
245 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { 242 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
246 aniState->ofdmPhyErrBase = 0; 243 aniState->ofdmPhyErrBase = 0;
247 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 244 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
@@ -267,15 +264,14 @@ static void ath9k_ani_restart(struct ath_hal *ah)
267 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 264 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
268 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 265 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
269 266
270 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); 267 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
271 } 268 }
272 aniState->ofdmPhyErrCount = 0; 269 aniState->ofdmPhyErrCount = 0;
273 aniState->cckPhyErrCount = 0; 270 aniState->cckPhyErrCount = 0;
274} 271}
275 272
276static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) 273static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
277{ 274{
278 struct ath_hal_5416 *ahp = AH5416(ah);
279 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 275 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
280 struct ar5416AniState *aniState; 276 struct ar5416AniState *aniState;
281 int32_t rssi; 277 int32_t rssi;
@@ -283,7 +279,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
283 if (!DO_ANI(ah)) 279 if (!DO_ANI(ah))
284 return; 280 return;
285 281
286 aniState = ahp->ah_curani; 282 aniState = ah->ah_curani;
287 283
288 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { 284 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
289 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 285 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
@@ -306,7 +302,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
306 } 302 }
307 return; 303 return;
308 } 304 }
309 rssi = BEACON_RSSI(ahp); 305 rssi = BEACON_RSSI(ah);
310 if (rssi > aniState->rssiThrHigh) { 306 if (rssi > aniState->rssiThrHigh) {
311 if (!aniState->ofdmWeakSigDetectOff) { 307 if (!aniState->ofdmWeakSigDetectOff) {
312 if (ath9k_hw_ani_control(ah, 308 if (ath9k_hw_ani_control(ah,
@@ -345,9 +341,8 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
345 } 341 }
346} 342}
347 343
348static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) 344static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
349{ 345{
350 struct ath_hal_5416 *ahp = AH5416(ah);
351 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 346 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
352 struct ar5416AniState *aniState; 347 struct ar5416AniState *aniState;
353 int32_t rssi; 348 int32_t rssi;
@@ -355,7 +350,7 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
355 if (!DO_ANI(ah)) 350 if (!DO_ANI(ah))
356 return; 351 return;
357 352
358 aniState = ahp->ah_curani; 353 aniState = ah->ah_curani;
359 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { 354 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
360 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 355 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
361 aniState->noiseImmunityLevel + 1)) { 356 aniState->noiseImmunityLevel + 1)) {
@@ -369,7 +364,7 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
369 } 364 }
370 return; 365 return;
371 } 366 }
372 rssi = BEACON_RSSI(ahp); 367 rssi = BEACON_RSSI(ah);
373 if (rssi > aniState->rssiThrLow) { 368 if (rssi > aniState->rssiThrLow) {
374 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) 369 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
375 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 370 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
@@ -383,13 +378,12 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
383 } 378 }
384} 379}
385 380
386static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah) 381static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
387{ 382{
388 struct ath_hal_5416 *ahp = AH5416(ah);
389 struct ar5416AniState *aniState; 383 struct ar5416AniState *aniState;
390 int32_t rssi; 384 int32_t rssi;
391 385
392 aniState = ahp->ah_curani; 386 aniState = ah->ah_curani;
393 387
394 if (ah->ah_opmode == NL80211_IFTYPE_AP) { 388 if (ah->ah_opmode == NL80211_IFTYPE_AP) {
395 if (aniState->firstepLevel > 0) { 389 if (aniState->firstepLevel > 0) {
@@ -398,7 +392,7 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
398 return; 392 return;
399 } 393 }
400 } else { 394 } else {
401 rssi = BEACON_RSSI(ahp); 395 rssi = BEACON_RSSI(ah);
402 if (rssi > aniState->rssiThrHigh) { 396 if (rssi > aniState->rssiThrHigh) {
403 /* XXX: Handle me */ 397 /* XXX: Handle me */
404 } else if (rssi > aniState->rssiThrLow) { 398 } else if (rssi > aniState->rssiThrLow) {
@@ -437,9 +431,8 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
437 } 431 }
438} 432}
439 433
440static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah) 434static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
441{ 435{
442 struct ath_hal_5416 *ahp = AH5416(ah);
443 struct ar5416AniState *aniState; 436 struct ar5416AniState *aniState;
444 u32 txFrameCount, rxFrameCount, cycleCount; 437 u32 txFrameCount, rxFrameCount, cycleCount;
445 int32_t listenTime; 438 int32_t listenTime;
@@ -448,11 +441,11 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
448 rxFrameCount = REG_READ(ah, AR_RFCNT); 441 rxFrameCount = REG_READ(ah, AR_RFCNT);
449 cycleCount = REG_READ(ah, AR_CCCNT); 442 cycleCount = REG_READ(ah, AR_CCCNT);
450 443
451 aniState = ahp->ah_curani; 444 aniState = ah->ah_curani;
452 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) { 445 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
453 446
454 listenTime = 0; 447 listenTime = 0;
455 ahp->ah_stats.ast_ani_lzero++; 448 ah->ah_stats.ast_ani_lzero++;
456 } else { 449 } else {
457 int32_t ccdelta = cycleCount - aniState->cycleCount; 450 int32_t ccdelta = cycleCount - aniState->cycleCount;
458 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount; 451 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
@@ -466,9 +459,8 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
466 return listenTime; 459 return listenTime;
467} 460}
468 461
469void ath9k_ani_reset(struct ath_hal *ah) 462void ath9k_ani_reset(struct ath_hw *ah)
470{ 463{
471 struct ath_hal_5416 *ahp = AH5416(ah);
472 struct ar5416AniState *aniState; 464 struct ar5416AniState *aniState;
473 struct ath9k_channel *chan = ah->ah_curchan; 465 struct ath9k_channel *chan = ah->ah_curchan;
474 int index; 466 int index;
@@ -477,14 +469,14 @@ void ath9k_ani_reset(struct ath_hal *ah)
477 return; 469 return;
478 470
479 index = ath9k_hw_get_ani_channel_idx(ah, chan); 471 index = ath9k_hw_get_ani_channel_idx(ah, chan);
480 aniState = &ahp->ah_ani[index]; 472 aniState = &ah->ah_ani[index];
481 ahp->ah_curani = aniState; 473 ah->ah_curani = aniState;
482 474
483 if (DO_ANI(ah) && ah->ah_opmode != NL80211_IFTYPE_STATION 475 if (DO_ANI(ah) && ah->ah_opmode != NL80211_IFTYPE_STATION
484 && ah->ah_opmode != NL80211_IFTYPE_ADHOC) { 476 && ah->ah_opmode != NL80211_IFTYPE_ADHOC) {
485 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 477 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
486 "Reset ANI state opmode %u\n", ah->ah_opmode); 478 "Reset ANI state opmode %u\n", ah->ah_opmode);
487 ahp->ah_stats.ast_ani_reset++; 479 ah->ah_stats.ast_ani_reset++;
488 480
489 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); 481 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
490 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); 482 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
@@ -498,13 +490,13 @@ void ath9k_ani_reset(struct ath_hal *ah)
498 ATH9K_RX_FILTER_PHYERR); 490 ATH9K_RX_FILTER_PHYERR);
499 491
500 if (ah->ah_opmode == NL80211_IFTYPE_AP) { 492 if (ah->ah_opmode == NL80211_IFTYPE_AP) {
501 ahp->ah_curani->ofdmTrigHigh = 493 ah->ah_curani->ofdmTrigHigh =
502 ah->ah_config.ofdm_trig_high; 494 ah->ah_config.ofdm_trig_high;
503 ahp->ah_curani->ofdmTrigLow = 495 ah->ah_curani->ofdmTrigLow =
504 ah->ah_config.ofdm_trig_low; 496 ah->ah_config.ofdm_trig_low;
505 ahp->ah_curani->cckTrigHigh = 497 ah->ah_curani->cckTrigHigh =
506 ah->ah_config.cck_trig_high; 498 ah->ah_config.cck_trig_high;
507 ahp->ah_curani->cckTrigLow = 499 ah->ah_curani->cckTrigLow =
508 ah->ah_config.cck_trig_low; 500 ah->ah_config.cck_trig_low;
509 } 501 }
510 ath9k_ani_restart(ah); 502 ath9k_ani_restart(ah);
@@ -526,7 +518,7 @@ void ath9k_ani_reset(struct ath_hal *ah)
526 if (aniState->firstepLevel != 0) 518 if (aniState->firstepLevel != 0)
527 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 519 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
528 aniState->firstepLevel); 520 aniState->firstepLevel);
529 if (ahp->ah_hasHwPhyCounters) { 521 if (ah->ah_hasHwPhyCounters) {
530 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) & 522 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
531 ~ATH9K_RX_FILTER_PHYERR); 523 ~ATH9K_RX_FILTER_PHYERR);
532 ath9k_ani_restart(ah); 524 ath9k_ani_restart(ah);
@@ -540,34 +532,33 @@ void ath9k_ani_reset(struct ath_hal *ah)
540 } 532 }
541} 533}
542 534
543void ath9k_hw_ani_monitor(struct ath_hal *ah, 535void ath9k_hw_ani_monitor(struct ath_hw *ah,
544 const struct ath9k_node_stats *stats, 536 const struct ath9k_node_stats *stats,
545 struct ath9k_channel *chan) 537 struct ath9k_channel *chan)
546{ 538{
547 struct ath_hal_5416 *ahp = AH5416(ah);
548 struct ar5416AniState *aniState; 539 struct ar5416AniState *aniState;
549 int32_t listenTime; 540 int32_t listenTime;
550 541
551 if (!DO_ANI(ah)) 542 if (!DO_ANI(ah))
552 return; 543 return;
553 544
554 aniState = ahp->ah_curani; 545 aniState = ah->ah_curani;
555 ahp->ah_stats.ast_nodestats = *stats; 546 ah->ah_stats.ast_nodestats = *stats;
556 547
557 listenTime = ath9k_hw_ani_get_listen_time(ah); 548 listenTime = ath9k_hw_ani_get_listen_time(ah);
558 if (listenTime < 0) { 549 if (listenTime < 0) {
559 ahp->ah_stats.ast_ani_lneg++; 550 ah->ah_stats.ast_ani_lneg++;
560 ath9k_ani_restart(ah); 551 ath9k_ani_restart(ah);
561 return; 552 return;
562 } 553 }
563 554
564 aniState->listenTime += listenTime; 555 aniState->listenTime += listenTime;
565 556
566 if (ahp->ah_hasHwPhyCounters) { 557 if (ah->ah_hasHwPhyCounters) {
567 u32 phyCnt1, phyCnt2; 558 u32 phyCnt1, phyCnt2;
568 u32 ofdmPhyErrCnt, cckPhyErrCnt; 559 u32 ofdmPhyErrCnt, cckPhyErrCnt;
569 560
570 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); 561 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
571 562
572 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); 563 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
573 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); 564 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
@@ -600,24 +591,24 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah,
600 } 591 }
601 592
602 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; 593 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
603 ahp->ah_stats.ast_ani_ofdmerrs += 594 ah->ah_stats.ast_ani_ofdmerrs +=
604 ofdmPhyErrCnt - aniState->ofdmPhyErrCount; 595 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
605 aniState->ofdmPhyErrCount = ofdmPhyErrCnt; 596 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
606 597
607 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; 598 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
608 ahp->ah_stats.ast_ani_cckerrs += 599 ah->ah_stats.ast_ani_cckerrs +=
609 cckPhyErrCnt - aniState->cckPhyErrCount; 600 cckPhyErrCnt - aniState->cckPhyErrCount;
610 aniState->cckPhyErrCount = cckPhyErrCnt; 601 aniState->cckPhyErrCount = cckPhyErrCnt;
611 } 602 }
612 603
613 if (aniState->listenTime > 5 * ahp->ah_aniPeriod) { 604 if (aniState->listenTime > 5 * ah->ah_aniPeriod) {
614 if (aniState->ofdmPhyErrCount <= aniState->listenTime * 605 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
615 aniState->ofdmTrigLow / 1000 && 606 aniState->ofdmTrigLow / 1000 &&
616 aniState->cckPhyErrCount <= aniState->listenTime * 607 aniState->cckPhyErrCount <= aniState->listenTime *
617 aniState->cckTrigLow / 1000) 608 aniState->cckTrigLow / 1000)
618 ath9k_hw_ani_lower_immunity(ah); 609 ath9k_hw_ani_lower_immunity(ah);
619 ath9k_ani_restart(ah); 610 ath9k_ani_restart(ah);
620 } else if (aniState->listenTime > ahp->ah_aniPeriod) { 611 } else if (aniState->listenTime > ah->ah_aniPeriod) {
621 if (aniState->ofdmPhyErrCount > aniState->listenTime * 612 if (aniState->ofdmPhyErrCount > aniState->listenTime *
622 aniState->ofdmTrigHigh / 1000) { 613 aniState->ofdmTrigHigh / 1000) {
623 ath9k_hw_ani_ofdm_err_trigger(ah); 614 ath9k_hw_ani_ofdm_err_trigger(ah);
@@ -631,20 +622,16 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah,
631 } 622 }
632} 623}
633 624
634bool ath9k_hw_phycounters(struct ath_hal *ah) 625bool ath9k_hw_phycounters(struct ath_hw *ah)
635{ 626{
636 struct ath_hal_5416 *ahp = AH5416(ah); 627 return ah->ah_hasHwPhyCounters ? true : false;
637
638 return ahp->ah_hasHwPhyCounters ? true : false;
639} 628}
640 629
641void ath9k_enable_mib_counters(struct ath_hal *ah) 630void ath9k_enable_mib_counters(struct ath_hw *ah)
642{ 631{
643 struct ath_hal_5416 *ahp = AH5416(ah);
644
645 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n"); 632 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n");
646 633
647 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); 634 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
648 635
649 REG_WRITE(ah, AR_FILT_OFDM, 0); 636 REG_WRITE(ah, AR_FILT_OFDM, 0);
650 REG_WRITE(ah, AR_FILT_CCK, 0); 637 REG_WRITE(ah, AR_FILT_CCK, 0);
@@ -655,21 +642,19 @@ void ath9k_enable_mib_counters(struct ath_hal *ah)
655 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 642 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
656} 643}
657 644
658void ath9k_hw_disable_mib_counters(struct ath_hal *ah) 645void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
659{ 646{
660 struct ath_hal_5416 *ahp = AH5416(ah);
661
662 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n"); 647 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n");
663 648
664 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC); 649 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
665 650
666 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); 651 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
667 652
668 REG_WRITE(ah, AR_FILT_OFDM, 0); 653 REG_WRITE(ah, AR_FILT_OFDM, 0);
669 REG_WRITE(ah, AR_FILT_CCK, 0); 654 REG_WRITE(ah, AR_FILT_CCK, 0);
670} 655}
671 656
672u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, 657u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
673 u32 *rxc_pcnt, 658 u32 *rxc_pcnt,
674 u32 *rxf_pcnt, 659 u32 *rxf_pcnt,
675 u32 *txf_pcnt) 660 u32 *txf_pcnt)
@@ -714,10 +699,9 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
714 * any of the MIB counters overflow/trigger so don't assume we're 699 * any of the MIB counters overflow/trigger so don't assume we're
715 * here because a PHY error counter triggered. 700 * here because a PHY error counter triggered.
716 */ 701 */
717void ath9k_hw_procmibevent(struct ath_hal *ah, 702void ath9k_hw_procmibevent(struct ath_hw *ah,
718 const struct ath9k_node_stats *stats) 703 const struct ath9k_node_stats *stats)
719{ 704{
720 struct ath_hal_5416 *ahp = AH5416(ah);
721 u32 phyCnt1, phyCnt2; 705 u32 phyCnt1, phyCnt2;
722 706
723 /* Reset these counters regardless */ 707 /* Reset these counters regardless */
@@ -727,8 +711,8 @@ void ath9k_hw_procmibevent(struct ath_hal *ah,
727 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR); 711 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
728 712
729 /* Clear the mib counters and save them in the stats */ 713 /* Clear the mib counters and save them in the stats */
730 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); 714 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
731 ahp->ah_stats.ast_nodestats = *stats; 715 ah->ah_stats.ast_nodestats = *stats;
732 716
733 if (!DO_ANI(ah)) 717 if (!DO_ANI(ah))
734 return; 718 return;
@@ -738,17 +722,17 @@ void ath9k_hw_procmibevent(struct ath_hal *ah,
738 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); 722 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
739 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || 723 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
740 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { 724 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
741 struct ar5416AniState *aniState = ahp->ah_curani; 725 struct ar5416AniState *aniState = ah->ah_curani;
742 u32 ofdmPhyErrCnt, cckPhyErrCnt; 726 u32 ofdmPhyErrCnt, cckPhyErrCnt;
743 727
744 /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */ 728 /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */
745 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; 729 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
746 ahp->ah_stats.ast_ani_ofdmerrs += 730 ah->ah_stats.ast_ani_ofdmerrs +=
747 ofdmPhyErrCnt - aniState->ofdmPhyErrCount; 731 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
748 aniState->ofdmPhyErrCount = ofdmPhyErrCnt; 732 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
749 733
750 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; 734 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
751 ahp->ah_stats.ast_ani_cckerrs += 735 ah->ah_stats.ast_ani_cckerrs +=
752 cckPhyErrCnt - aniState->cckPhyErrCount; 736 cckPhyErrCnt - aniState->cckPhyErrCount;
753 aniState->cckPhyErrCount = cckPhyErrCnt; 737 aniState->cckPhyErrCount = cckPhyErrCnt;
754 738
@@ -767,9 +751,8 @@ void ath9k_hw_procmibevent(struct ath_hal *ah,
767 } 751 }
768} 752}
769 753
770void ath9k_hw_ani_setup(struct ath_hal *ah) 754void ath9k_hw_ani_setup(struct ath_hw *ah)
771{ 755{
772 struct ath_hal_5416 *ahp = AH5416(ah);
773 int i; 756 int i;
774 757
775 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 }; 758 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
@@ -778,66 +761,63 @@ void ath9k_hw_ani_setup(struct ath_hal *ah)
778 const int firpwr[] = { -78, -78, -78, -78, -80 }; 761 const int firpwr[] = { -78, -78, -78, -78, -80 };
779 762
780 for (i = 0; i < 5; i++) { 763 for (i = 0; i < 5; i++) {
781 ahp->ah_totalSizeDesired[i] = totalSizeDesired[i]; 764 ah->ah_totalSizeDesired[i] = totalSizeDesired[i];
782 ahp->ah_coarseHigh[i] = coarseHigh[i]; 765 ah->ah_coarseHigh[i] = coarseHigh[i];
783 ahp->ah_coarseLow[i] = coarseLow[i]; 766 ah->ah_coarseLow[i] = coarseLow[i];
784 ahp->ah_firpwr[i] = firpwr[i]; 767 ah->ah_firpwr[i] = firpwr[i];
785 } 768 }
786} 769}
787 770
788void ath9k_hw_ani_attach(struct ath_hal *ah) 771void ath9k_hw_ani_attach(struct ath_hw *ah)
789{ 772{
790 struct ath_hal_5416 *ahp = AH5416(ah);
791 int i; 773 int i;
792 774
793 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n"); 775 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n");
794 776
795 ahp->ah_hasHwPhyCounters = 1; 777 ah->ah_hasHwPhyCounters = 1;
796 778
797 memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani)); 779 memset(ah->ah_ani, 0, sizeof(ah->ah_ani));
798 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { 780 for (i = 0; i < ARRAY_SIZE(ah->ah_ani); i++) {
799 ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; 781 ah->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
800 ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; 782 ah->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
801 ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; 783 ah->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
802 ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; 784 ah->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
803 ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; 785 ah->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
804 ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; 786 ah->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
805 ahp->ah_ani[i].ofdmWeakSigDetectOff = 787 ah->ah_ani[i].ofdmWeakSigDetectOff =
806 !ATH9K_ANI_USE_OFDM_WEAK_SIG; 788 !ATH9K_ANI_USE_OFDM_WEAK_SIG;
807 ahp->ah_ani[i].cckWeakSigThreshold = 789 ah->ah_ani[i].cckWeakSigThreshold =
808 ATH9K_ANI_CCK_WEAK_SIG_THR; 790 ATH9K_ANI_CCK_WEAK_SIG_THR;
809 ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 791 ah->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
810 ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 792 ah->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
811 if (ahp->ah_hasHwPhyCounters) { 793 if (ah->ah_hasHwPhyCounters) {
812 ahp->ah_ani[i].ofdmPhyErrBase = 794 ah->ah_ani[i].ofdmPhyErrBase =
813 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH; 795 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
814 ahp->ah_ani[i].cckPhyErrBase = 796 ah->ah_ani[i].cckPhyErrBase =
815 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; 797 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
816 } 798 }
817 } 799 }
818 if (ahp->ah_hasHwPhyCounters) { 800 if (ah->ah_hasHwPhyCounters) {
819 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 801 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
820 "Setting OfdmErrBase = 0x%08x\n", 802 "Setting OfdmErrBase = 0x%08x\n",
821 ahp->ah_ani[0].ofdmPhyErrBase); 803 ah->ah_ani[0].ofdmPhyErrBase);
822 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", 804 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
823 ahp->ah_ani[0].cckPhyErrBase); 805 ah->ah_ani[0].cckPhyErrBase);
824 806
825 REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase); 807 REG_WRITE(ah, AR_PHY_ERR_1, ah->ah_ani[0].ofdmPhyErrBase);
826 REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase); 808 REG_WRITE(ah, AR_PHY_ERR_2, ah->ah_ani[0].cckPhyErrBase);
827 ath9k_enable_mib_counters(ah); 809 ath9k_enable_mib_counters(ah);
828 } 810 }
829 ahp->ah_aniPeriod = ATH9K_ANI_PERIOD; 811 ah->ah_aniPeriod = ATH9K_ANI_PERIOD;
830 if (ah->ah_config.enable_ani) 812 if (ah->ah_config.enable_ani)
831 ahp->ah_procPhyErr |= HAL_PROCESS_ANI; 813 ah->ah_procPhyErr |= HAL_PROCESS_ANI;
832} 814}
833 815
834void ath9k_hw_ani_detach(struct ath_hal *ah) 816void ath9k_hw_ani_detach(struct ath_hw *ah)
835{ 817{
836 struct ath_hal_5416 *ahp = AH5416(ah);
837
838 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n"); 818 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n");
839 819
840 if (ahp->ah_hasHwPhyCounters) { 820 if (ah->ah_hasHwPhyCounters) {
841 ath9k_hw_disable_mib_counters(ah); 821 ath9k_hw_disable_mib_counters(ah);
842 REG_WRITE(ah, AR_PHY_ERR_1, 0); 822 REG_WRITE(ah, AR_PHY_ERR_1, 0);
843 REG_WRITE(ah, AR_PHY_ERR_2, 0); 823 REG_WRITE(ah, AR_PHY_ERR_2, 0);
diff --git a/drivers/net/wireless/ath9k/ani.h b/drivers/net/wireless/ath9k/ani.h
index 78880e591052..7e9ca9519799 100644
--- a/drivers/net/wireless/ath9k/ani.h
+++ b/drivers/net/wireless/ath9k/ani.h
@@ -20,7 +20,7 @@
20#define HAL_PROCESS_ANI 0x00000001 20#define HAL_PROCESS_ANI 0x00000001
21#define ATH9K_RSSI_EP_MULTIPLIER (1<<7) 21#define ATH9K_RSSI_EP_MULTIPLIER (1<<7)
22 22
23#define DO_ANI(ah) ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI)) 23#define DO_ANI(ah) (((ah)->ah_procPhyErr & HAL_PROCESS_ANI))
24 24
25#define HAL_EP_RND(x, mul) \ 25#define HAL_EP_RND(x, mul) \
26 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 26 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
@@ -120,19 +120,19 @@ struct ar5416Stats {
120}; 120};
121#define ah_mibStats ah_stats.ast_mibstats 121#define ah_mibStats ah_stats.ast_mibstats
122 122
123void ath9k_ani_reset(struct ath_hal *ah); 123void ath9k_ani_reset(struct ath_hw *ah);
124void ath9k_hw_ani_monitor(struct ath_hal *ah, 124void ath9k_hw_ani_monitor(struct ath_hw *ah,
125 const struct ath9k_node_stats *stats, 125 const struct ath9k_node_stats *stats,
126 struct ath9k_channel *chan); 126 struct ath9k_channel *chan);
127bool ath9k_hw_phycounters(struct ath_hal *ah); 127bool ath9k_hw_phycounters(struct ath_hw *ah);
128void ath9k_enable_mib_counters(struct ath_hal *ah); 128void ath9k_enable_mib_counters(struct ath_hw *ah);
129void ath9k_hw_disable_mib_counters(struct ath_hal *ah); 129void ath9k_hw_disable_mib_counters(struct ath_hw *ah);
130u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, u32 *rxc_pcnt, 130u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt,
131 u32 *rxf_pcnt, u32 *txf_pcnt); 131 u32 *rxf_pcnt, u32 *txf_pcnt);
132void ath9k_hw_procmibevent(struct ath_hal *ah, 132void ath9k_hw_procmibevent(struct ath_hw *ah,
133 const struct ath9k_node_stats *stats); 133 const struct ath9k_node_stats *stats);
134void ath9k_hw_ani_setup(struct ath_hal *ah); 134void ath9k_hw_ani_setup(struct ath_hw *ah);
135void ath9k_hw_ani_attach(struct ath_hal *ah); 135void ath9k_hw_ani_attach(struct ath_hw *ah);
136void ath9k_hw_ani_detach(struct ath_hal *ah); 136void ath9k_hw_ani_detach(struct ath_hw *ah);
137 137
138#endif /* ANI_H */ 138#endif /* ANI_H */
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h
index 03e4d0bf1590..91140b7214b1 100644
--- a/drivers/net/wireless/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath9k/ath9k.h
@@ -455,7 +455,7 @@ struct ath_beacon {
455 455
456void ath9k_beacon_tasklet(unsigned long data); 456void ath9k_beacon_tasklet(unsigned long data);
457void ath_beacon_config(struct ath_softc *sc, int if_id); 457void ath_beacon_config(struct ath_softc *sc, int if_id);
458int ath_beaconq_setup(struct ath_hal *ah); 458int ath_beaconq_setup(struct ath_hw *ah);
459int ath_beacon_alloc(struct ath_softc *sc, int if_id); 459int ath_beacon_alloc(struct ath_softc *sc, int if_id);
460void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); 460void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
461void ath_beacon_sync(struct ath_softc *sc, int if_id); 461void ath_beacon_sync(struct ath_softc *sc, int if_id);
@@ -565,7 +565,7 @@ struct ath_rfkill {
565struct ath_bus_ops { 565struct ath_bus_ops {
566 void (*read_cachesize)(struct ath_softc *sc, int *csz); 566 void (*read_cachesize)(struct ath_softc *sc, int *csz);
567 void (*cleanup)(struct ath_softc *sc); 567 void (*cleanup)(struct ath_softc *sc);
568 bool (*eeprom_read)(struct ath_hal *ah, u32 off, u16 *data); 568 bool (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data);
569}; 569};
570 570
571struct ath_softc { 571struct ath_softc {
@@ -573,7 +573,7 @@ struct ath_softc {
573 struct device *dev; 573 struct device *dev;
574 struct tasklet_struct intr_tq; 574 struct tasklet_struct intr_tq;
575 struct tasklet_struct bcon_tasklet; 575 struct tasklet_struct bcon_tasklet;
576 struct ath_hal *sc_ah; 576 struct ath_hw *sc_ah;
577 void __iomem *mem; 577 void __iomem *mem;
578 int irq; 578 int irq;
579 spinlock_t sc_resetlock; 579 spinlock_t sc_resetlock;
diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c
index 139bba738c5f..19ec4e8791b4 100644
--- a/drivers/net/wireless/ath9k/beacon.c
+++ b/drivers/net/wireless/ath9k/beacon.c
@@ -23,7 +23,7 @@
23*/ 23*/
24static int ath_beaconq_config(struct ath_softc *sc) 24static int ath_beaconq_config(struct ath_softc *sc)
25{ 25{
26 struct ath_hal *ah = sc->sc_ah; 26 struct ath_hw *ah = sc->sc_ah;
27 struct ath9k_tx_queue_info qi; 27 struct ath9k_tx_queue_info qi;
28 28
29 ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi); 29 ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
@@ -66,7 +66,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
66 struct ath_vif *avp, struct ath_buf *bf) 66 struct ath_vif *avp, struct ath_buf *bf)
67{ 67{
68 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; 68 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
69 struct ath_hal *ah = sc->sc_ah; 69 struct ath_hw *ah = sc->sc_ah;
70 struct ath_desc *ds; 70 struct ath_desc *ds;
71 struct ath9k_11n_rate_series series[4]; 71 struct ath9k_11n_rate_series series[4];
72 struct ath_rate_table *rt; 72 struct ath_rate_table *rt;
@@ -248,7 +248,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
248static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id) 248static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
249{ 249{
250 struct ieee80211_vif *vif; 250 struct ieee80211_vif *vif;
251 struct ath_hal *ah = sc->sc_ah; 251 struct ath_hw *ah = sc->sc_ah;
252 struct ath_buf *bf; 252 struct ath_buf *bf;
253 struct ath_vif *avp; 253 struct ath_vif *avp;
254 struct sk_buff *skb; 254 struct sk_buff *skb;
@@ -276,7 +276,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
276 sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc); 276 sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc);
277} 277}
278 278
279int ath_beaconq_setup(struct ath_hal *ah) 279int ath_beaconq_setup(struct ath_hw *ah)
280{ 280{
281 struct ath9k_tx_queue_info qi; 281 struct ath9k_tx_queue_info qi;
282 282
@@ -444,7 +444,7 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp)
444void ath9k_beacon_tasklet(unsigned long data) 444void ath9k_beacon_tasklet(unsigned long data)
445{ 445{
446 struct ath_softc *sc = (struct ath_softc *)data; 446 struct ath_softc *sc = (struct ath_softc *)data;
447 struct ath_hal *ah = sc->sc_ah; 447 struct ath_hw *ah = sc->sc_ah;
448 struct ath_buf *bf = NULL; 448 struct ath_buf *bf = NULL;
449 int slot, if_id; 449 int slot, if_id;
450 u32 bfaddr; 450 u32 bfaddr;
@@ -619,7 +619,7 @@ void ath9k_beacon_tasklet(unsigned long data)
619void ath_beacon_config(struct ath_softc *sc, int if_id) 619void ath_beacon_config(struct ath_softc *sc, int if_id)
620{ 620{
621 struct ieee80211_vif *vif; 621 struct ieee80211_vif *vif;
622 struct ath_hal *ah = sc->sc_ah; 622 struct ath_hw *ah = sc->sc_ah;
623 struct ath_beacon_config conf; 623 struct ath_beacon_config conf;
624 struct ath_vif *avp; 624 struct ath_vif *avp;
625 enum nl80211_iftype opmode; 625 enum nl80211_iftype opmode;
diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c
index 016302c53cc5..8c44d5a439e7 100644
--- a/drivers/net/wireless/ath9k/calib.c
+++ b/drivers/net/wireless/ath9k/calib.c
@@ -23,7 +23,7 @@
23 * is incorrect and we should use the static NF value. Later we can try to 23 * is incorrect and we should use the static NF value. Later we can try to
24 * find out why they are reporting these values */ 24 * find out why they are reporting these values */
25 25
26static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf) 26static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
27{ 27{
28 if (nf > ATH9K_NF_TOO_LOW) { 28 if (nf > ATH9K_NF_TOO_LOW) {
29 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 29 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
@@ -86,7 +86,7 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
86 return; 86 return;
87} 87}
88 88
89static void ath9k_hw_do_getnf(struct ath_hal *ah, 89static void ath9k_hw_do_getnf(struct ath_hw *ah,
90 int16_t nfarray[NUM_NF_READINGS]) 90 int16_t nfarray[NUM_NF_READINGS])
91{ 91{
92 int16_t nf; 92 int16_t nf;
@@ -166,7 +166,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah,
166 } 166 }
167} 167}
168 168
169static bool getNoiseFloorThresh(struct ath_hal *ah, 169static bool getNoiseFloorThresh(struct ath_hw *ah,
170 enum ieee80211_band band, 170 enum ieee80211_band band,
171 int16_t *nft) 171 int16_t *nft)
172{ 172{
@@ -185,7 +185,7 @@ static bool getNoiseFloorThresh(struct ath_hal *ah,
185 return true; 185 return true;
186} 186}
187 187
188static void ath9k_hw_setup_calibration(struct ath_hal *ah, 188static void ath9k_hw_setup_calibration(struct ath_hw *ah,
189 struct hal_cal_list *currCal) 189 struct hal_cal_list *currCal)
190{ 190{
191 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), 191 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
@@ -219,10 +219,9 @@ static void ath9k_hw_setup_calibration(struct ath_hal *ah,
219 AR_PHY_TIMING_CTRL4_DO_CAL); 219 AR_PHY_TIMING_CTRL4_DO_CAL);
220} 220}
221 221
222static void ath9k_hw_reset_calibration(struct ath_hal *ah, 222static void ath9k_hw_reset_calibration(struct ath_hw *ah,
223 struct hal_cal_list *currCal) 223 struct hal_cal_list *currCal)
224{ 224{
225 struct ath_hal_5416 *ahp = AH5416(ah);
226 int i; 225 int i;
227 226
228 ath9k_hw_setup_calibration(ah, currCal); 227 ath9k_hw_setup_calibration(ah, currCal);
@@ -230,23 +229,21 @@ static void ath9k_hw_reset_calibration(struct ath_hal *ah,
230 currCal->calState = CAL_RUNNING; 229 currCal->calState = CAL_RUNNING;
231 230
232 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 231 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
233 ahp->ah_Meas0.sign[i] = 0; 232 ah->ah_Meas0.sign[i] = 0;
234 ahp->ah_Meas1.sign[i] = 0; 233 ah->ah_Meas1.sign[i] = 0;
235 ahp->ah_Meas2.sign[i] = 0; 234 ah->ah_Meas2.sign[i] = 0;
236 ahp->ah_Meas3.sign[i] = 0; 235 ah->ah_Meas3.sign[i] = 0;
237 } 236 }
238 237
239 ahp->ah_CalSamples = 0; 238 ah->ah_CalSamples = 0;
240} 239}
241 240
242static void ath9k_hw_per_calibration(struct ath_hal *ah, 241static void ath9k_hw_per_calibration(struct ath_hw *ah,
243 struct ath9k_channel *ichan, 242 struct ath9k_channel *ichan,
244 u8 rxchainmask, 243 u8 rxchainmask,
245 struct hal_cal_list *currCal, 244 struct hal_cal_list *currCal,
246 bool *isCalDone) 245 bool *isCalDone)
247{ 246{
248 struct ath_hal_5416 *ahp = AH5416(ah);
249
250 *isCalDone = false; 247 *isCalDone = false;
251 248
252 if (currCal->calState == CAL_RUNNING) { 249 if (currCal->calState == CAL_RUNNING) {
@@ -254,9 +251,9 @@ static void ath9k_hw_per_calibration(struct ath_hal *ah,
254 AR_PHY_TIMING_CTRL4_DO_CAL)) { 251 AR_PHY_TIMING_CTRL4_DO_CAL)) {
255 252
256 currCal->calData->calCollect(ah); 253 currCal->calData->calCollect(ah);
257 ahp->ah_CalSamples++; 254 ah->ah_CalSamples++;
258 255
259 if (ahp->ah_CalSamples >= currCal->calData->calNumSamples) { 256 if (ah->ah_CalSamples >= currCal->calData->calNumSamples) {
260 int i, numChains = 0; 257 int i, numChains = 0;
261 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 258 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
262 if (rxchainmask & (1 << i)) 259 if (rxchainmask & (1 << i))
@@ -277,13 +274,12 @@ static void ath9k_hw_per_calibration(struct ath_hal *ah,
277} 274}
278 275
279/* Assumes you are talking about the currently configured channel */ 276/* Assumes you are talking about the currently configured channel */
280static bool ath9k_hw_iscal_supported(struct ath_hal *ah, 277static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
281 enum hal_cal_types calType) 278 enum hal_cal_types calType)
282{ 279{
283 struct ath_hal_5416 *ahp = AH5416(ah);
284 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 280 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
285 281
286 switch (calType & ahp->ah_suppCals) { 282 switch (calType & ah->ah_suppCals) {
287 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */ 283 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
288 return true; 284 return true;
289 case ADC_GAIN_CAL: 285 case ADC_GAIN_CAL:
@@ -296,90 +292,86 @@ static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
296 return false; 292 return false;
297} 293}
298 294
299static void ath9k_hw_iqcal_collect(struct ath_hal *ah) 295static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
300{ 296{
301 struct ath_hal_5416 *ahp = AH5416(ah);
302 int i; 297 int i;
303 298
304 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 299 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
305 ahp->ah_totalPowerMeasI[i] += 300 ah->ah_totalPowerMeasI[i] +=
306 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 301 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
307 ahp->ah_totalPowerMeasQ[i] += 302 ah->ah_totalPowerMeasQ[i] +=
308 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 303 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
309 ahp->ah_totalIqCorrMeas[i] += 304 ah->ah_totalIqCorrMeas[i] +=
310 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 305 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
311 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 306 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
312 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", 307 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
313 ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i], 308 ah->ah_CalSamples, i, ah->ah_totalPowerMeasI[i],
314 ahp->ah_totalPowerMeasQ[i], 309 ah->ah_totalPowerMeasQ[i],
315 ahp->ah_totalIqCorrMeas[i]); 310 ah->ah_totalIqCorrMeas[i]);
316 } 311 }
317} 312}
318 313
319static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah) 314static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
320{ 315{
321 struct ath_hal_5416 *ahp = AH5416(ah);
322 int i; 316 int i;
323 317
324 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 318 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
325 ahp->ah_totalAdcIOddPhase[i] += 319 ah->ah_totalAdcIOddPhase[i] +=
326 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 320 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
327 ahp->ah_totalAdcIEvenPhase[i] += 321 ah->ah_totalAdcIEvenPhase[i] +=
328 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 322 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
329 ahp->ah_totalAdcQOddPhase[i] += 323 ah->ah_totalAdcQOddPhase[i] +=
330 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 324 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
331 ahp->ah_totalAdcQEvenPhase[i] += 325 ah->ah_totalAdcQEvenPhase[i] +=
332 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 326 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
333 327
334 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 328 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
335 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 329 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
336 "oddq=0x%08x; evenq=0x%08x;\n", 330 "oddq=0x%08x; evenq=0x%08x;\n",
337 ahp->ah_CalSamples, i, 331 ah->ah_CalSamples, i,
338 ahp->ah_totalAdcIOddPhase[i], 332 ah->ah_totalAdcIOddPhase[i],
339 ahp->ah_totalAdcIEvenPhase[i], 333 ah->ah_totalAdcIEvenPhase[i],
340 ahp->ah_totalAdcQOddPhase[i], 334 ah->ah_totalAdcQOddPhase[i],
341 ahp->ah_totalAdcQEvenPhase[i]); 335 ah->ah_totalAdcQEvenPhase[i]);
342 } 336 }
343} 337}
344 338
345static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah) 339static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
346{ 340{
347 struct ath_hal_5416 *ahp = AH5416(ah);
348 int i; 341 int i;
349 342
350 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 343 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
351 ahp->ah_totalAdcDcOffsetIOddPhase[i] += 344 ah->ah_totalAdcDcOffsetIOddPhase[i] +=
352 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 345 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
353 ahp->ah_totalAdcDcOffsetIEvenPhase[i] += 346 ah->ah_totalAdcDcOffsetIEvenPhase[i] +=
354 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 347 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
355 ahp->ah_totalAdcDcOffsetQOddPhase[i] += 348 ah->ah_totalAdcDcOffsetQOddPhase[i] +=
356 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 349 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
357 ahp->ah_totalAdcDcOffsetQEvenPhase[i] += 350 ah->ah_totalAdcDcOffsetQEvenPhase[i] +=
358 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 351 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
359 352
360 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 353 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
361 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 354 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
362 "oddq=0x%08x; evenq=0x%08x;\n", 355 "oddq=0x%08x; evenq=0x%08x;\n",
363 ahp->ah_CalSamples, i, 356 ah->ah_CalSamples, i,
364 ahp->ah_totalAdcDcOffsetIOddPhase[i], 357 ah->ah_totalAdcDcOffsetIOddPhase[i],
365 ahp->ah_totalAdcDcOffsetIEvenPhase[i], 358 ah->ah_totalAdcDcOffsetIEvenPhase[i],
366 ahp->ah_totalAdcDcOffsetQOddPhase[i], 359 ah->ah_totalAdcDcOffsetQOddPhase[i],
367 ahp->ah_totalAdcDcOffsetQEvenPhase[i]); 360 ah->ah_totalAdcDcOffsetQEvenPhase[i]);
368 } 361 }
369} 362}
370 363
371static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains) 364static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
372{ 365{
373 struct ath_hal_5416 *ahp = AH5416(ah);
374 u32 powerMeasQ, powerMeasI, iqCorrMeas; 366 u32 powerMeasQ, powerMeasI, iqCorrMeas;
375 u32 qCoffDenom, iCoffDenom; 367 u32 qCoffDenom, iCoffDenom;
376 int32_t qCoff, iCoff; 368 int32_t qCoff, iCoff;
377 int iqCorrNeg, i; 369 int iqCorrNeg, i;
378 370
379 for (i = 0; i < numChains; i++) { 371 for (i = 0; i < numChains; i++) {
380 powerMeasI = ahp->ah_totalPowerMeasI[i]; 372 powerMeasI = ah->ah_totalPowerMeasI[i];
381 powerMeasQ = ahp->ah_totalPowerMeasQ[i]; 373 powerMeasQ = ah->ah_totalPowerMeasQ[i];
382 iqCorrMeas = ahp->ah_totalIqCorrMeas[i]; 374 iqCorrMeas = ah->ah_totalIqCorrMeas[i];
383 375
384 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 376 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
385 "Starting IQ Cal and Correction for Chain %d\n", 377 "Starting IQ Cal and Correction for Chain %d\n",
@@ -387,7 +379,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
387 379
388 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 380 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
389 "Orignal: Chn %diq_corr_meas = 0x%08x\n", 381 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
390 i, ahp->ah_totalIqCorrMeas[i]); 382 i, ah->ah_totalIqCorrMeas[i]);
391 383
392 iqCorrNeg = 0; 384 iqCorrNeg = 0;
393 385
@@ -445,17 +437,16 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
445 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 437 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
446} 438}
447 439
448static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains) 440static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
449{ 441{
450 struct ath_hal_5416 *ahp = AH5416(ah);
451 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset; 442 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
452 u32 qGainMismatch, iGainMismatch, val, i; 443 u32 qGainMismatch, iGainMismatch, val, i;
453 444
454 for (i = 0; i < numChains; i++) { 445 for (i = 0; i < numChains; i++) {
455 iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i]; 446 iOddMeasOffset = ah->ah_totalAdcIOddPhase[i];
456 iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i]; 447 iEvenMeasOffset = ah->ah_totalAdcIEvenPhase[i];
457 qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i]; 448 qOddMeasOffset = ah->ah_totalAdcQOddPhase[i];
458 qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i]; 449 qEvenMeasOffset = ah->ah_totalAdcQEvenPhase[i];
459 450
460 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 451 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
461 "Starting ADC Gain Cal for Chain %d\n", i); 452 "Starting ADC Gain Cal for Chain %d\n", i);
@@ -503,21 +494,20 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains)
503 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE); 494 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
504} 495}
505 496
506static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains) 497static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
507{ 498{
508 struct ath_hal_5416 *ahp = AH5416(ah);
509 u32 iOddMeasOffset, iEvenMeasOffset, val, i; 499 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
510 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; 500 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
511 const struct hal_percal_data *calData = 501 const struct hal_percal_data *calData =
512 ahp->ah_cal_list_curr->calData; 502 ah->ah_cal_list_curr->calData;
513 u32 numSamples = 503 u32 numSamples =
514 (1 << (calData->calCountMax + 5)) * calData->calNumSamples; 504 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
515 505
516 for (i = 0; i < numChains; i++) { 506 for (i = 0; i < numChains; i++) {
517 iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i]; 507 iOddMeasOffset = ah->ah_totalAdcDcOffsetIOddPhase[i];
518 iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i]; 508 iEvenMeasOffset = ah->ah_totalAdcDcOffsetIEvenPhase[i];
519 qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i]; 509 qOddMeasOffset = ah->ah_totalAdcDcOffsetQOddPhase[i];
520 qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i]; 510 qEvenMeasOffset = ah->ah_totalAdcDcOffsetQEvenPhase[i];
521 511
522 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 512 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
523 "Starting ADC DC Offset Cal for Chain %d\n", i); 513 "Starting ADC DC Offset Cal for Chain %d\n", i);
@@ -562,11 +552,10 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains)
562} 552}
563 553
564/* This is done for the currently configured channel */ 554/* This is done for the currently configured channel */
565bool ath9k_hw_reset_calvalid(struct ath_hal *ah) 555bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
566{ 556{
567 struct ath_hal_5416 *ahp = AH5416(ah);
568 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 557 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
569 struct hal_cal_list *currCal = ahp->ah_cal_list_curr; 558 struct hal_cal_list *currCal = ah->ah_cal_list_curr;
570 559
571 if (!ah->ah_curchan) 560 if (!ah->ah_curchan)
572 return true; 561 return true;
@@ -597,7 +586,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hal *ah)
597 return false; 586 return false;
598} 587}
599 588
600void ath9k_hw_start_nfcal(struct ath_hal *ah) 589void ath9k_hw_start_nfcal(struct ath_hw *ah)
601{ 590{
602 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, 591 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
603 AR_PHY_AGC_CONTROL_ENABLE_NF); 592 AR_PHY_AGC_CONTROL_ENABLE_NF);
@@ -606,7 +595,7 @@ void ath9k_hw_start_nfcal(struct ath_hal *ah)
606 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 595 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
607} 596}
608 597
609void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan) 598void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
610{ 599{
611 struct ath9k_nfcal_hist *h; 600 struct ath9k_nfcal_hist *h;
612 int i, j; 601 int i, j;
@@ -662,7 +651,7 @@ void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
662 } 651 }
663} 652}
664 653
665int16_t ath9k_hw_getnf(struct ath_hal *ah, 654int16_t ath9k_hw_getnf(struct ath_hw *ah,
666 struct ath9k_channel *chan) 655 struct ath9k_channel *chan)
667{ 656{
668 int16_t nf, nfThresh; 657 int16_t nf, nfThresh;
@@ -698,7 +687,7 @@ int16_t ath9k_hw_getnf(struct ath_hal *ah,
698 return chan->rawNoiseFloor; 687 return chan->rawNoiseFloor;
699} 688}
700 689
701void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah) 690void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah)
702{ 691{
703 int i, j; 692 int i, j;
704 693
@@ -712,10 +701,9 @@ void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
712 AR_PHY_CCA_MAX_GOOD_VALUE; 701 AR_PHY_CCA_MAX_GOOD_VALUE;
713 } 702 }
714 } 703 }
715 return;
716} 704}
717 705
718s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan) 706s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
719{ 707{
720 s16 nf; 708 s16 nf;
721 709
@@ -730,12 +718,11 @@ s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
730 return nf; 718 return nf;
731} 719}
732 720
733bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, 721bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
734 u8 rxchainmask, bool longcal, 722 u8 rxchainmask, bool longcal,
735 bool *isCalDone) 723 bool *isCalDone)
736{ 724{
737 struct ath_hal_5416 *ahp = AH5416(ah); 725 struct hal_cal_list *currCal = ah->ah_cal_list_curr;
738 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
739 726
740 *isCalDone = true; 727 *isCalDone = true;
741 728
@@ -745,7 +732,7 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
745 ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal, 732 ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal,
746 isCalDone); 733 isCalDone);
747 if (*isCalDone) { 734 if (*isCalDone) {
748 ahp->ah_cal_list_curr = currCal = currCal->calNext; 735 ah->ah_cal_list_curr = currCal = currCal->calNext;
749 736
750 if (currCal->calState == CAL_WAITING) { 737 if (currCal->calState == CAL_WAITING) {
751 *isCalDone = false; 738 *isCalDone = false;
@@ -766,7 +753,7 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
766 return true; 753 return true;
767} 754}
768 755
769static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah) 756static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah)
770{ 757{
771 758
772 u32 regVal; 759 u32 regVal;
@@ -861,11 +848,9 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah)
861 848
862} 849}
863 850
864bool ath9k_hw_init_cal(struct ath_hal *ah, 851bool ath9k_hw_init_cal(struct ath_hw *ah,
865 struct ath9k_channel *chan) 852 struct ath9k_channel *chan)
866{ 853{
867 struct ath_hal_5416 *ahp = AH5416(ah);
868
869 REG_WRITE(ah, AR_PHY_AGC_CONTROL, 854 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
870 REG_READ(ah, AR_PHY_AGC_CONTROL) | 855 REG_READ(ah, AR_PHY_AGC_CONTROL) |
871 AR_PHY_AGC_CONTROL_CAL); 856 AR_PHY_AGC_CONTROL_CAL);
@@ -884,32 +869,32 @@ bool ath9k_hw_init_cal(struct ath_hal *ah,
884 REG_READ(ah, AR_PHY_AGC_CONTROL) | 869 REG_READ(ah, AR_PHY_AGC_CONTROL) |
885 AR_PHY_AGC_CONTROL_NF); 870 AR_PHY_AGC_CONTROL_NF);
886 871
887 ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL; 872 ah->ah_cal_list = ah->ah_cal_list_last = ah->ah_cal_list_curr = NULL;
888 873
889 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { 874 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
890 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { 875 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
891 INIT_CAL(&ahp->ah_adcGainCalData); 876 INIT_CAL(&ah->ah_adcGainCalData);
892 INSERT_CAL(ahp, &ahp->ah_adcGainCalData); 877 INSERT_CAL(ah, &ah->ah_adcGainCalData);
893 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 878 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
894 "enabling ADC Gain Calibration.\n"); 879 "enabling ADC Gain Calibration.\n");
895 } 880 }
896 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { 881 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
897 INIT_CAL(&ahp->ah_adcDcCalData); 882 INIT_CAL(&ah->ah_adcDcCalData);
898 INSERT_CAL(ahp, &ahp->ah_adcDcCalData); 883 INSERT_CAL(ah, &ah->ah_adcDcCalData);
899 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 884 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
900 "enabling ADC DC Calibration.\n"); 885 "enabling ADC DC Calibration.\n");
901 } 886 }
902 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { 887 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
903 INIT_CAL(&ahp->ah_iqCalData); 888 INIT_CAL(&ah->ah_iqCalData);
904 INSERT_CAL(ahp, &ahp->ah_iqCalData); 889 INSERT_CAL(ah, &ah->ah_iqCalData);
905 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 890 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
906 "enabling IQ Calibration.\n"); 891 "enabling IQ Calibration.\n");
907 } 892 }
908 893
909 ahp->ah_cal_list_curr = ahp->ah_cal_list; 894 ah->ah_cal_list_curr = ah->ah_cal_list;
910 895
911 if (ahp->ah_cal_list_curr) 896 if (ah->ah_cal_list_curr)
912 ath9k_hw_reset_calibration(ah, ahp->ah_cal_list_curr); 897 ath9k_hw_reset_calibration(ah, ah->ah_cal_list_curr);
913 } 898 }
914 899
915 chan->CalValid = 0; 900 chan->CalValid = 0;
diff --git a/drivers/net/wireless/ath9k/calib.h b/drivers/net/wireless/ath9k/calib.h
index ac7d88fa8268..e2c614098545 100644
--- a/drivers/net/wireless/ath9k/calib.h
+++ b/drivers/net/wireless/ath9k/calib.h
@@ -91,8 +91,8 @@ struct hal_percal_data {
91 enum hal_cal_types calType; 91 enum hal_cal_types calType;
92 u32 calNumSamples; 92 u32 calNumSamples;
93 u32 calCountMax; 93 u32 calCountMax;
94 void (*calCollect) (struct ath_hal *); 94 void (*calCollect) (struct ath_hw *);
95 void (*calPostProc) (struct ath_hal *, u8); 95 void (*calPostProc) (struct ath_hw *, u8);
96}; 96};
97 97
98struct hal_cal_list { 98struct hal_cal_list {
@@ -108,17 +108,17 @@ struct ath9k_nfcal_hist {
108 u8 invalidNFcount; 108 u8 invalidNFcount;
109}; 109};
110 110
111bool ath9k_hw_reset_calvalid(struct ath_hal *ah); 111bool ath9k_hw_reset_calvalid(struct ath_hw *ah);
112void ath9k_hw_start_nfcal(struct ath_hal *ah); 112void ath9k_hw_start_nfcal(struct ath_hw *ah);
113void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan); 113void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan);
114int16_t ath9k_hw_getnf(struct ath_hal *ah, 114int16_t ath9k_hw_getnf(struct ath_hw *ah,
115 struct ath9k_channel *chan); 115 struct ath9k_channel *chan);
116void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah); 116void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah);
117s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan); 117s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan);
118bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, 118bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
119 u8 rxchainmask, bool longcal, 119 u8 rxchainmask, bool longcal,
120 bool *isCalDone); 120 bool *isCalDone);
121bool ath9k_hw_init_cal(struct ath_hal *ah, 121bool ath9k_hw_init_cal(struct ath_hw *ah,
122 struct ath9k_channel *chan); 122 struct ath9k_channel *chan);
123 123
124#endif /* CALIB_H */ 124#endif /* CALIB_H */
diff --git a/drivers/net/wireless/ath9k/debug.c b/drivers/net/wireless/ath9k/debug.c
index daca5ce91452..800ad5926b6f 100644
--- a/drivers/net/wireless/ath9k/debug.c
+++ b/drivers/net/wireless/ath9k/debug.c
@@ -44,7 +44,7 @@ static ssize_t read_file_dma(struct file *file, char __user *user_buf,
44 size_t count, loff_t *ppos) 44 size_t count, loff_t *ppos)
45{ 45{
46 struct ath_softc *sc = file->private_data; 46 struct ath_softc *sc = file->private_data;
47 struct ath_hal *ah = sc->sc_ah; 47 struct ath_hw *ah = sc->sc_ah;
48 char buf[1024]; 48 char buf[1024];
49 unsigned int len = 0; 49 unsigned int len = 0;
50 u32 val[ATH9K_NUM_DMA_DEBUG_REGS]; 50 u32 val[ATH9K_NUM_DMA_DEBUG_REGS];
diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c
index d58d8a330b64..94e79938b93a 100644
--- a/drivers/net/wireless/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath9k/eeprom.c
@@ -16,7 +16,7 @@
16 16
17#include "ath9k.h" 17#include "ath9k.h"
18 18
19static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah, 19static void ath9k_hw_analog_shift_rmw(struct ath_hw *ah,
20 u32 reg, u32 mask, 20 u32 reg, u32 mask,
21 u32 shift, u32 val) 21 u32 shift, u32 val)
22{ 22{
@@ -88,18 +88,17 @@ static inline bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList,
88 return false; 88 return false;
89} 89}
90 90
91static inline bool ath9k_hw_nvram_read(struct ath_hal *ah, u32 off, u16 *data) 91static inline bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data)
92{ 92{
93 struct ath_softc *sc = ah->ah_sc; 93 struct ath_softc *sc = ah->ah_sc;
94 94
95 return sc->bus_ops->eeprom_read(ah, off, data); 95 return sc->bus_ops->eeprom_read(ah, off, data);
96} 96}
97 97
98static bool ath9k_hw_fill_4k_eeprom(struct ath_hal *ah) 98static bool ath9k_hw_fill_4k_eeprom(struct ath_hw *ah)
99{ 99{
100#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 100#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
101 struct ath_hal_5416 *ahp = AH5416(ah); 101 struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k;
102 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
103 u16 *eep_data; 102 u16 *eep_data;
104 int addr, eep_start_loc = 0; 103 int addr, eep_start_loc = 0;
105 104
@@ -124,11 +123,10 @@ static bool ath9k_hw_fill_4k_eeprom(struct ath_hal *ah)
124#undef SIZE_EEPROM_4K 123#undef SIZE_EEPROM_4K
125} 124}
126 125
127static bool ath9k_hw_fill_def_eeprom(struct ath_hal *ah) 126static bool ath9k_hw_fill_def_eeprom(struct ath_hw *ah)
128{ 127{
129#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) 128#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
130 struct ath_hal_5416 *ahp = AH5416(ah); 129 struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def;
131 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
132 u16 *eep_data; 130 u16 *eep_data;
133 int addr, ar5416_eep_start_loc = 0x100; 131 int addr, ar5416_eep_start_loc = 0x100;
134 132
@@ -147,23 +145,20 @@ static bool ath9k_hw_fill_def_eeprom(struct ath_hal *ah)
147#undef SIZE_EEPROM_DEF 145#undef SIZE_EEPROM_DEF
148} 146}
149 147
150static bool (*ath9k_fill_eeprom[]) (struct ath_hal *) = { 148static bool (*ath9k_fill_eeprom[]) (struct ath_hw *) = {
151 ath9k_hw_fill_def_eeprom, 149 ath9k_hw_fill_def_eeprom,
152 ath9k_hw_fill_4k_eeprom 150 ath9k_hw_fill_4k_eeprom
153}; 151};
154 152
155static inline bool ath9k_hw_fill_eeprom(struct ath_hal *ah) 153static inline bool ath9k_hw_fill_eeprom(struct ath_hw *ah)
156{ 154{
157 struct ath_hal_5416 *ahp = AH5416(ah); 155 return ath9k_fill_eeprom[ah->ah_eep_map](ah);
158
159 return ath9k_fill_eeprom[ahp->ah_eep_map](ah);
160} 156}
161 157
162static int ath9k_hw_check_def_eeprom(struct ath_hal *ah) 158static int ath9k_hw_check_def_eeprom(struct ath_hw *ah)
163{ 159{
164 struct ath_hal_5416 *ahp = AH5416(ah);
165 struct ar5416_eeprom_def *eep = 160 struct ar5416_eeprom_def *eep =
166 (struct ar5416_eeprom_def *) &ahp->ah_eeprom.def; 161 (struct ar5416_eeprom_def *) &ah->ah_eeprom.def;
167 u16 *eepdata, temp, magic, magic2; 162 u16 *eepdata, temp, magic, magic2;
168 u32 sum = 0, el; 163 u32 sum = 0, el;
169 bool need_swap = false; 164 bool need_swap = false;
@@ -187,7 +182,7 @@ static int ath9k_hw_check_def_eeprom(struct ath_hal *ah)
187 if (magic2 == AR5416_EEPROM_MAGIC) { 182 if (magic2 == AR5416_EEPROM_MAGIC) {
188 size = sizeof(struct ar5416_eeprom_def); 183 size = sizeof(struct ar5416_eeprom_def);
189 need_swap = true; 184 need_swap = true;
190 eepdata = (u16 *) (&ahp->ah_eeprom); 185 eepdata = (u16 *) (&ah->ah_eeprom);
191 186
192 for (addr = 0; addr < size / sizeof(u16); addr++) { 187 for (addr = 0; addr < size / sizeof(u16); addr++) {
193 temp = swab16(*eepdata); 188 temp = swab16(*eepdata);
@@ -214,16 +209,16 @@ static int ath9k_hw_check_def_eeprom(struct ath_hal *ah)
214 need_swap ? "True" : "False"); 209 need_swap ? "True" : "False");
215 210
216 if (need_swap) 211 if (need_swap)
217 el = swab16(ahp->ah_eeprom.def.baseEepHeader.length); 212 el = swab16(ah->ah_eeprom.def.baseEepHeader.length);
218 else 213 else
219 el = ahp->ah_eeprom.def.baseEepHeader.length; 214 el = ah->ah_eeprom.def.baseEepHeader.length;
220 215
221 if (el > sizeof(struct ar5416_eeprom_def)) 216 if (el > sizeof(struct ar5416_eeprom_def))
222 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16); 217 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
223 else 218 else
224 el = el / sizeof(u16); 219 el = el / sizeof(u16);
225 220
226 eepdata = (u16 *)(&ahp->ah_eeprom); 221 eepdata = (u16 *)(&ah->ah_eeprom);
227 222
228 for (i = 0; i < el; i++) 223 for (i = 0; i < el; i++)
229 sum ^= *eepdata++; 224 sum ^= *eepdata++;
@@ -277,23 +272,22 @@ static int ath9k_hw_check_def_eeprom(struct ath_hal *ah)
277 } 272 }
278 } 273 }
279 274
280 if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER || 275 if (sum != 0xffff || ar5416_get_eep_ver(ah) != AR5416_EEP_VER ||
281 ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) { 276 ar5416_get_eep_rev(ah) < AR5416_EEP_NO_BACK_VER) {
282 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 277 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
283 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 278 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
284 sum, ar5416_get_eep_ver(ahp)); 279 sum, ar5416_get_eep_ver(ah));
285 return -EINVAL; 280 return -EINVAL;
286 } 281 }
287 282
288 return 0; 283 return 0;
289} 284}
290 285
291static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah) 286static int ath9k_hw_check_4k_eeprom(struct ath_hw *ah)
292{ 287{
293#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 288#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
294 struct ath_hal_5416 *ahp = AH5416(ah);
295 struct ar5416_eeprom_4k *eep = 289 struct ar5416_eeprom_4k *eep =
296 (struct ar5416_eeprom_4k *) &ahp->ah_eeprom.map4k; 290 (struct ar5416_eeprom_4k *) &ah->ah_eeprom.map4k;
297 u16 *eepdata, temp, magic, magic2; 291 u16 *eepdata, temp, magic, magic2;
298 u32 sum = 0, el; 292 u32 sum = 0, el;
299 bool need_swap = false; 293 bool need_swap = false;
@@ -317,7 +311,7 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah)
317 311
318 if (magic2 == AR5416_EEPROM_MAGIC) { 312 if (magic2 == AR5416_EEPROM_MAGIC) {
319 need_swap = true; 313 need_swap = true;
320 eepdata = (u16 *) (&ahp->ah_eeprom); 314 eepdata = (u16 *) (&ah->ah_eeprom);
321 315
322 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) { 316 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
323 temp = swab16(*eepdata); 317 temp = swab16(*eepdata);
@@ -344,16 +338,16 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah)
344 need_swap ? "True" : "False"); 338 need_swap ? "True" : "False");
345 339
346 if (need_swap) 340 if (need_swap)
347 el = swab16(ahp->ah_eeprom.map4k.baseEepHeader.length); 341 el = swab16(ah->ah_eeprom.map4k.baseEepHeader.length);
348 else 342 else
349 el = ahp->ah_eeprom.map4k.baseEepHeader.length; 343 el = ah->ah_eeprom.map4k.baseEepHeader.length;
350 344
351 if (el > sizeof(struct ar5416_eeprom_def)) 345 if (el > sizeof(struct ar5416_eeprom_def))
352 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); 346 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
353 else 347 else
354 el = el / sizeof(u16); 348 el = el / sizeof(u16);
355 349
356 eepdata = (u16 *)(&ahp->ah_eeprom); 350 eepdata = (u16 *)(&ah->ah_eeprom);
357 351
358 for (i = 0; i < el; i++) 352 for (i = 0; i < el; i++)
359 sum ^= *eepdata++; 353 sum ^= *eepdata++;
@@ -403,11 +397,11 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah)
403 } 397 }
404 } 398 }
405 399
406 if (sum != 0xffff || ar5416_get_eep4k_ver(ahp) != AR5416_EEP_VER || 400 if (sum != 0xffff || ar5416_get_eep4k_ver(ah) != AR5416_EEP_VER ||
407 ar5416_get_eep4k_rev(ahp) < AR5416_EEP_NO_BACK_VER) { 401 ar5416_get_eep4k_rev(ah) < AR5416_EEP_NO_BACK_VER) {
408 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 402 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
409 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 403 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
410 sum, ar5416_get_eep4k_ver(ahp)); 404 sum, ar5416_get_eep4k_ver(ah));
411 return -EINVAL; 405 return -EINVAL;
412 } 406 }
413 407
@@ -415,16 +409,14 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah)
415#undef EEPROM_4K_SIZE 409#undef EEPROM_4K_SIZE
416} 410}
417 411
418static int (*ath9k_check_eeprom[]) (struct ath_hal *) = { 412static int (*ath9k_check_eeprom[]) (struct ath_hw *) = {
419 ath9k_hw_check_def_eeprom, 413 ath9k_hw_check_def_eeprom,
420 ath9k_hw_check_4k_eeprom 414 ath9k_hw_check_4k_eeprom
421}; 415};
422 416
423static inline int ath9k_hw_check_eeprom(struct ath_hal *ah) 417static inline int ath9k_hw_check_eeprom(struct ath_hw *ah)
424{ 418{
425 struct ath_hal_5416 *ahp = AH5416(ah); 419 return ath9k_check_eeprom[ah->ah_eep_map](ah);
426
427 return ath9k_check_eeprom[ahp->ah_eep_map](ah);
428} 420}
429 421
430static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, 422static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
@@ -456,7 +448,7 @@ static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
456 return true; 448 return true;
457} 449}
458 450
459static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hal *ah, 451static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
460 struct ath9k_channel *chan, 452 struct ath9k_channel *chan,
461 struct cal_data_per_freq_4k *pRawDataSet, 453 struct cal_data_per_freq_4k *pRawDataSet,
462 u8 *bChans, u16 availPiers, 454 u8 *bChans, u16 availPiers,
@@ -624,7 +616,7 @@ static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hal *ah,
624#undef TMP_VAL_VPD_TABLE 616#undef TMP_VAL_VPD_TABLE
625} 617}
626 618
627static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hal *ah, 619static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
628 struct ath9k_channel *chan, 620 struct ath9k_channel *chan,
629 struct cal_data_per_freq *pRawDataSet, 621 struct cal_data_per_freq *pRawDataSet,
630 u8 *bChans, u16 availPiers, 622 u8 *bChans, u16 availPiers,
@@ -789,7 +781,7 @@ static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hal *ah,
789 return; 781 return;
790} 782}
791 783
792static void ath9k_hw_get_legacy_target_powers(struct ath_hal *ah, 784static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
793 struct ath9k_channel *chan, 785 struct ath9k_channel *chan,
794 struct cal_target_power_leg *powInfo, 786 struct cal_target_power_leg *powInfo,
795 u16 numChannels, 787 u16 numChannels,
@@ -844,7 +836,7 @@ static void ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
844 } 836 }
845} 837}
846 838
847static void ath9k_hw_get_target_powers(struct ath_hal *ah, 839static void ath9k_hw_get_target_powers(struct ath_hw *ah,
848 struct ath9k_channel *chan, 840 struct ath9k_channel *chan,
849 struct cal_target_power_ht *powInfo, 841 struct cal_target_power_ht *powInfo,
850 u16 numChannels, 842 u16 numChannels,
@@ -927,12 +919,11 @@ static u16 ath9k_hw_get_max_edge_power(u16 freq,
927 return twiceMaxEdgePower; 919 return twiceMaxEdgePower;
928} 920}
929 921
930static bool ath9k_hw_set_def_power_cal_table(struct ath_hal *ah, 922static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
931 struct ath9k_channel *chan, 923 struct ath9k_channel *chan,
932 int16_t *pTxPowerIndexOffset) 924 int16_t *pTxPowerIndexOffset)
933{ 925{
934 struct ath_hal_5416 *ahp = AH5416(ah); 926 struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def;
935 struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def;
936 struct cal_data_per_freq *pRawDataset; 927 struct cal_data_per_freq *pRawDataset;
937 u8 *pCalBChans = NULL; 928 u8 *pCalBChans = NULL;
938 u16 pdGainOverlap_t2; 929 u16 pdGainOverlap_t2;
@@ -988,7 +979,7 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hal *ah,
988 979
989 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 980 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
990 if (AR_SREV_5416_V20_OR_LATER(ah) && 981 if (AR_SREV_5416_V20_OR_LATER(ah) &&
991 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) && 982 (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) &&
992 (i != 0)) { 983 (i != 0)) {
993 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 984 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
994 } else 985 } else
@@ -1054,12 +1045,11 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hal *ah,
1054 return true; 1045 return true;
1055} 1046}
1056 1047
1057static bool ath9k_hw_set_4k_power_cal_table(struct ath_hal *ah, 1048static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
1058 struct ath9k_channel *chan, 1049 struct ath9k_channel *chan,
1059 int16_t *pTxPowerIndexOffset) 1050 int16_t *pTxPowerIndexOffset)
1060{ 1051{
1061 struct ath_hal_5416 *ahp = AH5416(ah); 1052 struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k;
1062 struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k;
1063 struct cal_data_per_freq_4k *pRawDataset; 1053 struct cal_data_per_freq_4k *pRawDataset;
1064 u8 *pCalBChans = NULL; 1054 u8 *pCalBChans = NULL;
1065 u16 pdGainOverlap_t2; 1055 u16 pdGainOverlap_t2;
@@ -1108,7 +1098,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hal *ah,
1108 1098
1109 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 1099 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1110 if (AR_SREV_5416_V20_OR_LATER(ah) && 1100 if (AR_SREV_5416_V20_OR_LATER(ah) &&
1111 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) && 1101 (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) &&
1112 (i != 0)) { 1102 (i != 0)) {
1113 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 1103 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1114 } else 1104 } else
@@ -1171,7 +1161,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hal *ah,
1171 return true; 1161 return true;
1172} 1162}
1173 1163
1174static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah, 1164static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
1175 struct ath9k_channel *chan, 1165 struct ath9k_channel *chan,
1176 int16_t *ratesArray, 1166 int16_t *ratesArray,
1177 u16 cfgCtl, 1167 u16 cfgCtl,
@@ -1182,8 +1172,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah,
1182#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ 1172#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
1183#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ 1173#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
1184 1174
1185 struct ath_hal_5416 *ahp = AH5416(ah); 1175 struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def;
1186 struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def;
1187 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1176 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1188 static const u16 tpScaleReductionTable[5] = 1177 static const u16 tpScaleReductionTable[5] =
1189 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; 1178 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
@@ -1213,7 +1202,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah,
1213 int tx_chainmask; 1202 int tx_chainmask;
1214 u16 twiceMinEdgePower; 1203 u16 twiceMinEdgePower;
1215 1204
1216 tx_chainmask = ahp->ah_txchainmask; 1205 tx_chainmask = ah->ah_txchainmask;
1217 1206
1218 ath9k_hw_get_channel_centers(ah, chan, &centers); 1207 ath9k_hw_get_channel_centers(ah, chan, &centers);
1219 1208
@@ -1322,7 +1311,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah,
1322 else 1311 else
1323 freq = centers.ctl_center; 1312 freq = centers.ctl_center;
1324 1313
1325 if (ar5416_get_eep_ver(ahp) == 14 && ar5416_get_eep_rev(ahp) <= 2) 1314 if (ar5416_get_eep_ver(ah) == 14 && ar5416_get_eep_rev(ah) <= 2)
1326 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1315 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1327 1316
1328 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 1317 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
@@ -1462,7 +1451,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah,
1462 return true; 1451 return true;
1463} 1452}
1464 1453
1465static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah, 1454static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
1466 struct ath9k_channel *chan, 1455 struct ath9k_channel *chan,
1467 int16_t *ratesArray, 1456 int16_t *ratesArray,
1468 u16 cfgCtl, 1457 u16 cfgCtl,
@@ -1470,8 +1459,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah,
1470 u16 twiceMaxRegulatoryPower, 1459 u16 twiceMaxRegulatoryPower,
1471 u16 powerLimit) 1460 u16 powerLimit)
1472{ 1461{
1473 struct ath_hal_5416 *ahp = AH5416(ah); 1462 struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k;
1474 struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k;
1475 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1463 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1476 static const u16 tpScaleReductionTable[5] = 1464 static const u16 tpScaleReductionTable[5] =
1477 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; 1465 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
@@ -1499,7 +1487,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah,
1499 int tx_chainmask; 1487 int tx_chainmask;
1500 u16 twiceMinEdgePower; 1488 u16 twiceMinEdgePower;
1501 1489
1502 tx_chainmask = ahp->ah_txchainmask; 1490 tx_chainmask = ah->ah_txchainmask;
1503 1491
1504 ath9k_hw_get_channel_centers(ah, chan, &centers); 1492 ath9k_hw_get_channel_centers(ah, chan, &centers);
1505 1493
@@ -1560,8 +1548,8 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah,
1560 else 1548 else
1561 freq = centers.ctl_center; 1549 freq = centers.ctl_center;
1562 1550
1563 if (ar5416_get_eep_ver(ahp) == 14 && 1551 if (ar5416_get_eep_ver(ah) == 14 &&
1564 ar5416_get_eep_rev(ahp) <= 2) 1552 ar5416_get_eep_rev(ah) <= 2)
1565 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1553 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1566 1554
1567 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 1555 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
@@ -1698,15 +1686,14 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah,
1698 return true; 1686 return true;
1699} 1687}
1700 1688
1701static int ath9k_hw_def_set_txpower(struct ath_hal *ah, 1689static int ath9k_hw_def_set_txpower(struct ath_hw *ah,
1702 struct ath9k_channel *chan, 1690 struct ath9k_channel *chan,
1703 u16 cfgCtl, 1691 u16 cfgCtl,
1704 u8 twiceAntennaReduction, 1692 u8 twiceAntennaReduction,
1705 u8 twiceMaxRegulatoryPower, 1693 u8 twiceMaxRegulatoryPower,
1706 u8 powerLimit) 1694 u8 powerLimit)
1707{ 1695{
1708 struct ath_hal_5416 *ahp = AH5416(ah); 1696 struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def;
1709 struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def;
1710 struct modal_eep_header *pModal = 1697 struct modal_eep_header *pModal =
1711 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); 1698 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1712 int16_t ratesArray[Ar5416RateSize]; 1699 int16_t ratesArray[Ar5416RateSize];
@@ -1831,15 +1818,14 @@ static int ath9k_hw_def_set_txpower(struct ath_hal *ah,
1831 return 0; 1818 return 0;
1832} 1819}
1833 1820
1834static int ath9k_hw_4k_set_txpower(struct ath_hal *ah, 1821static int ath9k_hw_4k_set_txpower(struct ath_hw *ah,
1835 struct ath9k_channel *chan, 1822 struct ath9k_channel *chan,
1836 u16 cfgCtl, 1823 u16 cfgCtl,
1837 u8 twiceAntennaReduction, 1824 u8 twiceAntennaReduction,
1838 u8 twiceMaxRegulatoryPower, 1825 u8 twiceMaxRegulatoryPower,
1839 u8 powerLimit) 1826 u8 powerLimit)
1840{ 1827{
1841 struct ath_hal_5416 *ahp = AH5416(ah); 1828 struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k;
1842 struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k;
1843 struct modal_eep_4k_header *pModal = &pEepData->modalHeader; 1829 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
1844 int16_t ratesArray[Ar5416RateSize]; 1830 int16_t ratesArray[Ar5416RateSize];
1845 int16_t txPowerIndexOffset = 0; 1831 int16_t txPowerIndexOffset = 0;
@@ -1959,40 +1945,37 @@ static int ath9k_hw_4k_set_txpower(struct ath_hal *ah,
1959 return 0; 1945 return 0;
1960} 1946}
1961 1947
1962static int (*ath9k_set_txpower[]) (struct ath_hal *, 1948static int (*ath9k_set_txpower[]) (struct ath_hw *,
1963 struct ath9k_channel *, 1949 struct ath9k_channel *,
1964 u16, u8, u8, u8) = { 1950 u16, u8, u8, u8) = {
1965 ath9k_hw_def_set_txpower, 1951 ath9k_hw_def_set_txpower,
1966 ath9k_hw_4k_set_txpower 1952 ath9k_hw_4k_set_txpower
1967}; 1953};
1968 1954
1969int ath9k_hw_set_txpower(struct ath_hal *ah, 1955int ath9k_hw_set_txpower(struct ath_hw *ah,
1970 struct ath9k_channel *chan, 1956 struct ath9k_channel *chan,
1971 u16 cfgCtl, 1957 u16 cfgCtl,
1972 u8 twiceAntennaReduction, 1958 u8 twiceAntennaReduction,
1973 u8 twiceMaxRegulatoryPower, 1959 u8 twiceMaxRegulatoryPower,
1974 u8 powerLimit) 1960 u8 powerLimit)
1975{ 1961{
1976 struct ath_hal_5416 *ahp = AH5416(ah); 1962 return ath9k_set_txpower[ah->ah_eep_map](ah, chan, cfgCtl,
1977 1963 twiceAntennaReduction, twiceMaxRegulatoryPower,
1978 return ath9k_set_txpower[ahp->ah_eep_map](ah, chan, cfgCtl, 1964 powerLimit);
1979 twiceAntennaReduction, twiceMaxRegulatoryPower,
1980 powerLimit);
1981} 1965}
1982 1966
1983static void ath9k_hw_set_def_addac(struct ath_hal *ah, 1967static void ath9k_hw_set_def_addac(struct ath_hw *ah,
1984 struct ath9k_channel *chan) 1968 struct ath9k_channel *chan)
1985{ 1969{
1986#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) 1970#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
1987 struct modal_eep_header *pModal; 1971 struct modal_eep_header *pModal;
1988 struct ath_hal_5416 *ahp = AH5416(ah); 1972 struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def;
1989 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
1990 u8 biaslevel; 1973 u8 biaslevel;
1991 1974
1992 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) 1975 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
1993 return; 1976 return;
1994 1977
1995 if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7) 1978 if (ar5416_get_eep_rev(ah) < AR5416_EEP_MINOR_VER_7)
1996 return; 1979 return;
1997 1980
1998 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); 1981 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
@@ -2026,60 +2009,54 @@ static void ath9k_hw_set_def_addac(struct ath_hal *ah,
2026 } 2009 }
2027 2010
2028 if (IS_CHAN_2GHZ(chan)) { 2011 if (IS_CHAN_2GHZ(chan)) {
2029 INI_RA(&ahp->ah_iniAddac, 7, 1) = (INI_RA(&ahp->ah_iniAddac, 2012 INI_RA(&ah->ah_iniAddac, 7, 1) = (INI_RA(&ah->ah_iniAddac,
2030 7, 1) & (~0x18)) | biaslevel << 3; 2013 7, 1) & (~0x18)) | biaslevel << 3;
2031 } else { 2014 } else {
2032 INI_RA(&ahp->ah_iniAddac, 6, 1) = (INI_RA(&ahp->ah_iniAddac, 2015 INI_RA(&ah->ah_iniAddac, 6, 1) = (INI_RA(&ah->ah_iniAddac,
2033 6, 1) & (~0xc0)) | biaslevel << 6; 2016 6, 1) & (~0xc0)) | biaslevel << 6;
2034 } 2017 }
2035#undef XPA_LVL_FREQ 2018#undef XPA_LVL_FREQ
2036} 2019}
2037 2020
2038static void ath9k_hw_set_4k_addac(struct ath_hal *ah, 2021static void ath9k_hw_set_4k_addac(struct ath_hw *ah,
2039 struct ath9k_channel *chan) 2022 struct ath9k_channel *chan)
2040{ 2023{
2041 struct modal_eep_4k_header *pModal; 2024 struct modal_eep_4k_header *pModal;
2042 struct ath_hal_5416 *ahp = AH5416(ah); 2025 struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k;
2043 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
2044 u8 biaslevel; 2026 u8 biaslevel;
2045 2027
2046 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) 2028 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
2047 return; 2029 return;
2048 2030
2049 if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7) 2031 if (ar5416_get_eep_rev(ah) < AR5416_EEP_MINOR_VER_7)
2050 return; 2032 return;
2051 2033
2052 pModal = &eep->modalHeader; 2034 pModal = &eep->modalHeader;
2053 2035
2054 if (pModal->xpaBiasLvl != 0xff) { 2036 if (pModal->xpaBiasLvl != 0xff) {
2055 biaslevel = pModal->xpaBiasLvl; 2037 biaslevel = pModal->xpaBiasLvl;
2056 INI_RA(&ahp->ah_iniAddac, 7, 1) = 2038 INI_RA(&ah->ah_iniAddac, 7, 1) =
2057 (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; 2039 (INI_RA(&ah->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
2058 } 2040 }
2059} 2041}
2060 2042
2061static void (*ath9k_set_addac[]) (struct ath_hal *, struct ath9k_channel *) = { 2043static void (*ath9k_set_addac[]) (struct ath_hw *, struct ath9k_channel *) = {
2062 ath9k_hw_set_def_addac, 2044 ath9k_hw_set_def_addac,
2063 ath9k_hw_set_4k_addac 2045 ath9k_hw_set_4k_addac
2064}; 2046};
2065 2047
2066void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan) 2048void ath9k_hw_set_addac(struct ath_hw *ah, struct ath9k_channel *chan)
2067{ 2049{
2068 struct ath_hal_5416 *ahp = AH5416(ah); 2050 ath9k_set_addac[ah->ah_eep_map](ah, chan);
2069
2070 ath9k_set_addac[ahp->ah_eep_map](ah, chan);
2071} 2051}
2072 2052
2073
2074
2075/* XXX: Clean me up, make me more legible */ 2053/* XXX: Clean me up, make me more legible */
2076static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah, 2054static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hw *ah,
2077 struct ath9k_channel *chan) 2055 struct ath9k_channel *chan)
2078{ 2056{
2079#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) 2057#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
2080 struct modal_eep_header *pModal; 2058 struct modal_eep_header *pModal;
2081 struct ath_hal_5416 *ahp = AH5416(ah); 2059 struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def;
2082 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
2083 int i, regChainOffset; 2060 int i, regChainOffset;
2084 u8 txRxAttenLocal; 2061 u8 txRxAttenLocal;
2085 2062
@@ -2097,7 +2074,7 @@ static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah,
2097 } 2074 }
2098 2075
2099 if (AR_SREV_5416_V20_OR_LATER(ah) && 2076 if (AR_SREV_5416_V20_OR_LATER(ah) &&
2100 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) 2077 (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5)
2101 && (i != 0)) 2078 && (i != 0))
2102 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 2079 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
2103 else 2080 else
@@ -2318,12 +2295,11 @@ static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah,
2318#undef AR5416_VER_MASK 2295#undef AR5416_VER_MASK
2319} 2296}
2320 2297
2321static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hal *ah, 2298static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hw *ah,
2322 struct ath9k_channel *chan) 2299 struct ath9k_channel *chan)
2323{ 2300{
2324 struct modal_eep_4k_header *pModal; 2301 struct modal_eep_4k_header *pModal;
2325 struct ath_hal_5416 *ahp = AH5416(ah); 2302 struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k;
2326 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
2327 int regChainOffset; 2303 int regChainOffset;
2328 u8 txRxAttenLocal; 2304 u8 txRxAttenLocal;
2329 u8 ob[5], db1[5], db2[5]; 2305 u8 ob[5], db1[5], db2[5];
@@ -2505,66 +2481,59 @@ static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hal *ah,
2505 return true; 2481 return true;
2506} 2482}
2507 2483
2508static bool (*ath9k_eeprom_set_board_values[])(struct ath_hal *, 2484static bool (*ath9k_eeprom_set_board_values[])(struct ath_hw *,
2509 struct ath9k_channel *) = { 2485 struct ath9k_channel *) = {
2510 ath9k_hw_eeprom_set_def_board_values, 2486 ath9k_hw_eeprom_set_def_board_values,
2511 ath9k_hw_eeprom_set_4k_board_values 2487 ath9k_hw_eeprom_set_4k_board_values
2512}; 2488};
2513 2489
2514bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, 2490bool ath9k_hw_eeprom_set_board_values(struct ath_hw *ah,
2515 struct ath9k_channel *chan) 2491 struct ath9k_channel *chan)
2516{ 2492{
2517 struct ath_hal_5416 *ahp = AH5416(ah); 2493 return ath9k_eeprom_set_board_values[ah->ah_eep_map](ah, chan);
2518
2519 return ath9k_eeprom_set_board_values[ahp->ah_eep_map](ah, chan);
2520} 2494}
2521 2495
2522static u16 ath9k_hw_get_def_eeprom_antenna_cfg(struct ath_hal *ah, 2496static u16 ath9k_hw_get_def_eeprom_antenna_cfg(struct ath_hw *ah,
2523 struct ath9k_channel *chan) 2497 struct ath9k_channel *chan)
2524{ 2498{
2525 struct ath_hal_5416 *ahp = AH5416(ah); 2499 struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def;
2526 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
2527 struct modal_eep_header *pModal = 2500 struct modal_eep_header *pModal =
2528 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); 2501 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
2529 2502
2530 return pModal->antCtrlCommon & 0xFFFF; 2503 return pModal->antCtrlCommon & 0xFFFF;
2531} 2504}
2532 2505
2533static u16 ath9k_hw_get_4k_eeprom_antenna_cfg(struct ath_hal *ah, 2506static u16 ath9k_hw_get_4k_eeprom_antenna_cfg(struct ath_hw *ah,
2534 struct ath9k_channel *chan) 2507 struct ath9k_channel *chan)
2535{ 2508{
2536 struct ath_hal_5416 *ahp = AH5416(ah); 2509 struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k;
2537 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
2538 struct modal_eep_4k_header *pModal = &eep->modalHeader; 2510 struct modal_eep_4k_header *pModal = &eep->modalHeader;
2539 2511
2540 return pModal->antCtrlCommon & 0xFFFF; 2512 return pModal->antCtrlCommon & 0xFFFF;
2541} 2513}
2542 2514
2543static u16 (*ath9k_get_eeprom_antenna_cfg[])(struct ath_hal *, 2515static u16 (*ath9k_get_eeprom_antenna_cfg[])(struct ath_hw *,
2544 struct ath9k_channel *) = { 2516 struct ath9k_channel *) = {
2545 ath9k_hw_get_def_eeprom_antenna_cfg, 2517 ath9k_hw_get_def_eeprom_antenna_cfg,
2546 ath9k_hw_get_4k_eeprom_antenna_cfg 2518 ath9k_hw_get_4k_eeprom_antenna_cfg
2547}; 2519};
2548 2520
2549u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah, 2521u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hw *ah,
2550 struct ath9k_channel *chan) 2522 struct ath9k_channel *chan)
2551{ 2523{
2552 struct ath_hal_5416 *ahp = AH5416(ah); 2524 return ath9k_get_eeprom_antenna_cfg[ah->ah_eep_map](ah, chan);
2553
2554 return ath9k_get_eeprom_antenna_cfg[ahp->ah_eep_map](ah, chan);
2555} 2525}
2556 2526
2557static u8 ath9k_hw_get_4k_num_ant_config(struct ath_hal *ah, 2527static u8 ath9k_hw_get_4k_num_ant_config(struct ath_hw *ah,
2558 enum ieee80211_band freq_band) 2528 enum ieee80211_band freq_band)
2559{ 2529{
2560 return 1; 2530 return 1;
2561} 2531}
2562 2532
2563static u8 ath9k_hw_get_def_num_ant_config(struct ath_hal *ah, 2533static u8 ath9k_hw_get_def_num_ant_config(struct ath_hw *ah,
2564 enum ieee80211_band freq_band) 2534 enum ieee80211_band freq_band)
2565{ 2535{
2566 struct ath_hal_5416 *ahp = AH5416(ah); 2536 struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def;
2567 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
2568 struct modal_eep_header *pModal = 2537 struct modal_eep_header *pModal =
2569 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]); 2538 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
2570 struct base_eep_header *pBase = &eep->baseEepHeader; 2539 struct base_eep_header *pBase = &eep->baseEepHeader;
@@ -2579,27 +2548,24 @@ static u8 ath9k_hw_get_def_num_ant_config(struct ath_hal *ah,
2579 return num_ant_config; 2548 return num_ant_config;
2580} 2549}
2581 2550
2582static u8 (*ath9k_get_num_ant_config[])(struct ath_hal *, 2551static u8 (*ath9k_get_num_ant_config[])(struct ath_hw *,
2583 enum ieee80211_band) = { 2552 enum ieee80211_band) = {
2584 ath9k_hw_get_def_num_ant_config, 2553 ath9k_hw_get_def_num_ant_config,
2585 ath9k_hw_get_4k_num_ant_config 2554 ath9k_hw_get_4k_num_ant_config
2586}; 2555};
2587 2556
2588u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah, 2557u8 ath9k_hw_get_num_ant_config(struct ath_hw *ah,
2589 enum ieee80211_band freq_band) 2558 enum ieee80211_band freq_band)
2590{ 2559{
2591 struct ath_hal_5416 *ahp = AH5416(ah); 2560 return ath9k_get_num_ant_config[ah->ah_eep_map](ah, freq_band);
2592
2593 return ath9k_get_num_ant_config[ahp->ah_eep_map](ah, freq_band);
2594} 2561}
2595 2562
2596u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz) 2563u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hw *ah, u16 i, bool is2GHz)
2597{ 2564{
2598#define EEP_MAP4K_SPURCHAN \ 2565#define EEP_MAP4K_SPURCHAN \
2599 (ahp->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan) 2566 (ah->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan)
2600#define EEP_DEF_SPURCHAN \ 2567#define EEP_DEF_SPURCHAN \
2601 (ahp->ah_eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) 2568 (ah->ah_eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
2602 struct ath_hal_5416 *ahp = AH5416(ah);
2603 u16 spur_val = AR_NO_SPUR; 2569 u16 spur_val = AR_NO_SPUR;
2604 2570
2605 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 2571 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
@@ -2615,7 +2581,7 @@ u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz)
2615 "Getting spur val from new loc. %d\n", spur_val); 2581 "Getting spur val from new loc. %d\n", spur_val);
2616 break; 2582 break;
2617 case SPUR_ENABLE_EEPROM: 2583 case SPUR_ENABLE_EEPROM:
2618 if (ahp->ah_eep_map == EEP_MAP_4KBITS) 2584 if (ah->ah_eep_map == EEP_MAP_4KBITS)
2619 spur_val = EEP_MAP4K_SPURCHAN; 2585 spur_val = EEP_MAP4K_SPURCHAN;
2620 else 2586 else
2621 spur_val = EEP_DEF_SPURCHAN; 2587 spur_val = EEP_DEF_SPURCHAN;
@@ -2628,11 +2594,10 @@ u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz)
2628#undef EEP_MAP4K_SPURCHAN 2594#undef EEP_MAP4K_SPURCHAN
2629} 2595}
2630 2596
2631static u32 ath9k_hw_get_eeprom_4k(struct ath_hal *ah, 2597static u32 ath9k_hw_get_eeprom_4k(struct ath_hw *ah,
2632 enum eeprom_param param) 2598 enum eeprom_param param)
2633{ 2599{
2634 struct ath_hal_5416 *ahp = AH5416(ah); 2600 struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k;
2635 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
2636 struct modal_eep_4k_header *pModal = &eep->modalHeader; 2601 struct modal_eep_4k_header *pModal = &eep->modalHeader;
2637 struct base_eep_header_4k *pBase = &eep->baseEepHeader; 2602 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
2638 2603
@@ -2670,12 +2635,11 @@ static u32 ath9k_hw_get_eeprom_4k(struct ath_hal *ah,
2670 } 2635 }
2671} 2636}
2672 2637
2673static u32 ath9k_hw_get_eeprom_def(struct ath_hal *ah, 2638static u32 ath9k_hw_get_eeprom_def(struct ath_hw *ah,
2674 enum eeprom_param param) 2639 enum eeprom_param param)
2675{ 2640{
2676#define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK) 2641#define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK)
2677 struct ath_hal_5416 *ahp = AH5416(ah); 2642 struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def;
2678 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
2679 struct modal_eep_header *pModal = eep->modalHeader; 2643 struct modal_eep_header *pModal = eep->modalHeader;
2680 struct base_eep_header *pBase = &eep->baseEepHeader; 2644 struct base_eep_header *pBase = &eep->baseEepHeader;
2681 2645
@@ -2729,28 +2693,25 @@ static u32 ath9k_hw_get_eeprom_def(struct ath_hal *ah,
2729#undef AR5416_VER_MASK 2693#undef AR5416_VER_MASK
2730} 2694}
2731 2695
2732static u32 (*ath9k_get_eeprom[])(struct ath_hal *, enum eeprom_param) = { 2696static u32 (*ath9k_get_eeprom[])(struct ath_hw *, enum eeprom_param) = {
2733 ath9k_hw_get_eeprom_def, 2697 ath9k_hw_get_eeprom_def,
2734 ath9k_hw_get_eeprom_4k 2698 ath9k_hw_get_eeprom_4k
2735}; 2699};
2736 2700
2737u32 ath9k_hw_get_eeprom(struct ath_hal *ah, 2701u32 ath9k_hw_get_eeprom(struct ath_hw *ah,
2738 enum eeprom_param param) 2702 enum eeprom_param param)
2739{ 2703{
2740 struct ath_hal_5416 *ahp = AH5416(ah); 2704 return ath9k_get_eeprom[ah->ah_eep_map](ah, param);
2741
2742 return ath9k_get_eeprom[ahp->ah_eep_map](ah, param);
2743} 2705}
2744 2706
2745int ath9k_hw_eeprom_attach(struct ath_hal *ah) 2707int ath9k_hw_eeprom_attach(struct ath_hw *ah)
2746{ 2708{
2747 int status; 2709 int status;
2748 struct ath_hal_5416 *ahp = AH5416(ah);
2749 2710
2750 if (AR_SREV_9285(ah)) 2711 if (AR_SREV_9285(ah))
2751 ahp->ah_eep_map = EEP_MAP_4KBITS; 2712 ah->ah_eep_map = EEP_MAP_4KBITS;
2752 else 2713 else
2753 ahp->ah_eep_map = EEP_MAP_DEFAULT; 2714 ah->ah_eep_map = EEP_MAP_DEFAULT;
2754 2715
2755 if (!ath9k_hw_fill_eeprom(ah)) 2716 if (!ath9k_hw_fill_eeprom(ah))
2756 return -EIO; 2717 return -EIO;
diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h
index 9eb777465144..81a7a708bc85 100644
--- a/drivers/net/wireless/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath9k/eeprom.h
@@ -447,38 +447,38 @@ enum hal_eep_map {
447 EEP_MAP_MAX 447 EEP_MAP_MAX
448}; 448};
449 449
450#define ar5416_get_eep_ver(_ahp) \ 450#define ar5416_get_eep_ver(_ah) \
451 (((_ahp)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF) 451 (((_ah)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF)
452#define ar5416_get_eep_rev(_ahp) \ 452#define ar5416_get_eep_rev(_ah) \
453 (((_ahp)->ah_eeprom.def.baseEepHeader.version) & 0xFFF) 453 (((_ah)->ah_eeprom.def.baseEepHeader.version) & 0xFFF)
454#define ar5416_get_ntxchains(_txchainmask) \ 454#define ar5416_get_ntxchains(_txchainmask) \
455 (((_txchainmask >> 2) & 1) + \ 455 (((_txchainmask >> 2) & 1) + \
456 ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 456 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
457 457
458#define ar5416_get_eep4k_ver(_ahp) \ 458#define ar5416_get_eep4k_ver(_ah) \
459 (((_ahp)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF) 459 (((_ah)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF)
460#define ar5416_get_eep4k_rev(_ahp) \ 460#define ar5416_get_eep4k_rev(_ah) \
461 (((_ahp)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF) 461 (((_ah)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF)
462 462
463int ath9k_hw_set_txpower(struct ath_hal *ah, struct ath9k_channel *chan, 463int ath9k_hw_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
464 u16 cfgCtl, u8 twiceAntennaReduction, 464 u16 cfgCtl, u8 twiceAntennaReduction,
465 u8 twiceMaxRegulatoryPower, u8 powerLimit); 465 u8 twiceMaxRegulatoryPower, u8 powerLimit);
466void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan); 466void ath9k_hw_set_addac(struct ath_hw *ah, struct ath9k_channel *chan);
467bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah, 467bool ath9k_hw_set_power_per_rate_table(struct ath_hw *ah,
468 struct ath9k_channel *chan, int16_t *ratesArray, 468 struct ath9k_channel *chan, int16_t *ratesArray,
469 u16 cfgCtl, u8 AntennaReduction, 469 u16 cfgCtl, u8 AntennaReduction,
470 u8 twiceMaxRegulatoryPower, u8 powerLimit); 470 u8 twiceMaxRegulatoryPower, u8 powerLimit);
471bool ath9k_hw_set_power_cal_table(struct ath_hal *ah, 471bool ath9k_hw_set_power_cal_table(struct ath_hw *ah,
472 struct ath9k_channel *chan, 472 struct ath9k_channel *chan,
473 int16_t *pTxPowerIndexOffset); 473 int16_t *pTxPowerIndexOffset);
474bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, 474bool ath9k_hw_eeprom_set_board_values(struct ath_hw *ah,
475 struct ath9k_channel *chan); 475 struct ath9k_channel *chan);
476u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah, 476u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hw *ah,
477 struct ath9k_channel *chan); 477 struct ath9k_channel *chan);
478u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah, 478u8 ath9k_hw_get_num_ant_config(struct ath_hw *ah,
479 enum ieee80211_band freq_band); 479 enum ieee80211_band freq_band);
480u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz); 480u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hw *ah, u16 i, bool is2GHz);
481u32 ath9k_hw_get_eeprom(struct ath_hal *ah, enum eeprom_param param); 481u32 ath9k_hw_get_eeprom(struct ath_hw *ah, enum eeprom_param param);
482int ath9k_hw_eeprom_attach(struct ath_hal *ah); 482int ath9k_hw_eeprom_attach(struct ath_hw *ah);
483 483
484#endif /* EEPROM_H */ 484#endif /* EEPROM_H */
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index 5d7287549c0b..ba908e9f1a8e 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -28,41 +28,45 @@ MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
28#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 28#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 29#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
30 30
31static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type); 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, 32static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode); 33 enum ath9k_ht_macmode macmode);
34static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, 34static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35 struct ar5416_eeprom_def *pEepData, 35 struct ar5416_eeprom_def *pEepData,
36 u32 reg, u32 value); 36 u32 reg, u32 value);
37static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan); 37static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan); 38static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
39 39
40/********************/ 40/********************/
41/* Helper Functions */ 41/* Helper Functions */
42/********************/ 42/********************/
43 43
44static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks) 44static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
45{ 45{
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47
47 if (!ah->ah_curchan) /* should really check for CCK instead */ 48 if (!ah->ah_curchan) /* should really check for CCK instead */
48 return clks / ATH9K_CLOCK_RATE_CCK; 49 return clks / ATH9K_CLOCK_RATE_CCK;
49 if (conf->channel->band == IEEE80211_BAND_2GHZ) 50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
50 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM; 51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
52
51 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM; 53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
52} 54}
53 55
54static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks) 56static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
55{ 57{
56 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
59
57 if (conf_is_ht40(conf)) 60 if (conf_is_ht40(conf))
58 return ath9k_hw_mac_usec(ah, clks) / 2; 61 return ath9k_hw_mac_usec(ah, clks) / 2;
59 else 62 else
60 return ath9k_hw_mac_usec(ah, clks); 63 return ath9k_hw_mac_usec(ah, clks);
61} 64}
62 65
63static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs) 66static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
64{ 67{
65 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69
66 if (!ah->ah_curchan) /* should really check for CCK instead */ 70 if (!ah->ah_curchan) /* should really check for CCK instead */
67 return usecs *ATH9K_CLOCK_RATE_CCK; 71 return usecs *ATH9K_CLOCK_RATE_CCK;
68 if (conf->channel->band == IEEE80211_BAND_2GHZ) 72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
@@ -70,16 +74,17 @@ static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
70 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM; 74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
71} 75}
72 76
73static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs) 77static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
74{ 78{
75 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
80
76 if (conf_is_ht40(conf)) 81 if (conf_is_ht40(conf))
77 return ath9k_hw_mac_clks(ah, usecs) * 2; 82 return ath9k_hw_mac_clks(ah, usecs) * 2;
78 else 83 else
79 return ath9k_hw_mac_clks(ah, usecs); 84 return ath9k_hw_mac_clks(ah, usecs);
80} 85}
81 86
82bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val) 87bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val)
83{ 88{
84 int i; 89 int i;
85 90
@@ -109,7 +114,7 @@ u32 ath9k_hw_reverse_bits(u32 val, u32 n)
109 return retval; 114 return retval;
110} 115}
111 116
112bool ath9k_get_channel_edges(struct ath_hal *ah, 117bool ath9k_get_channel_edges(struct ath_hw *ah,
113 u16 flags, u16 *low, 118 u16 flags, u16 *low,
114 u16 *high) 119 u16 *high)
115{ 120{
@@ -128,7 +133,7 @@ bool ath9k_get_channel_edges(struct ath_hal *ah,
128 return false; 133 return false;
129} 134}
130 135
131u16 ath9k_hw_computetxtime(struct ath_hal *ah, 136u16 ath9k_hw_computetxtime(struct ath_hw *ah,
132 struct ath_rate_table *rates, 137 struct ath_rate_table *rates,
133 u32 frameLen, u16 rateix, 138 u32 frameLen, u16 rateix,
134 bool shortPreamble) 139 bool shortPreamble)
@@ -184,12 +189,11 @@ u16 ath9k_hw_computetxtime(struct ath_hal *ah,
184 return txTime; 189 return txTime;
185} 190}
186 191
187void ath9k_hw_get_channel_centers(struct ath_hal *ah, 192void ath9k_hw_get_channel_centers(struct ath_hw *ah,
188 struct ath9k_channel *chan, 193 struct ath9k_channel *chan,
189 struct chan_centers *centers) 194 struct chan_centers *centers)
190{ 195{
191 int8_t extoff; 196 int8_t extoff;
192 struct ath_hal_5416 *ahp = AH5416(ah);
193 197
194 if (!IS_CHAN_HT40(chan)) { 198 if (!IS_CHAN_HT40(chan)) {
195 centers->ctl_center = centers->ext_center = 199 centers->ctl_center = centers->ext_center =
@@ -212,16 +216,15 @@ void ath9k_hw_get_channel_centers(struct ath_hal *ah,
212 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 216 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
213 centers->ext_center = 217 centers->ext_center =
214 centers->synth_center + (extoff * 218 centers->synth_center + (extoff *
215 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? 219 ((ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
216 HT40_CHANNEL_CENTER_SHIFT : 15)); 220 HT40_CHANNEL_CENTER_SHIFT : 15));
217
218} 221}
219 222
220/******************/ 223/******************/
221/* Chip Revisions */ 224/* Chip Revisions */
222/******************/ 225/******************/
223 226
224static void ath9k_hw_read_revisions(struct ath_hal *ah) 227static void ath9k_hw_read_revisions(struct ath_hw *ah)
225{ 228{
226 u32 val; 229 u32 val;
227 230
@@ -244,7 +247,7 @@ static void ath9k_hw_read_revisions(struct ath_hal *ah)
244 } 247 }
245} 248}
246 249
247static int ath9k_hw_get_radiorev(struct ath_hal *ah) 250static int ath9k_hw_get_radiorev(struct ath_hw *ah)
248{ 251{
249 u32 val; 252 u32 val;
250 int i; 253 int i;
@@ -263,7 +266,7 @@ static int ath9k_hw_get_radiorev(struct ath_hal *ah)
263/* HW Attach, Detach, Init Routines */ 266/* HW Attach, Detach, Init Routines */
264/************************************/ 267/************************************/
265 268
266static void ath9k_hw_disablepcie(struct ath_hal *ah) 269static void ath9k_hw_disablepcie(struct ath_hw *ah)
267{ 270{
268 if (AR_SREV_9100(ah)) 271 if (AR_SREV_9100(ah))
269 return; 272 return;
@@ -281,7 +284,7 @@ static void ath9k_hw_disablepcie(struct ath_hal *ah)
281 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 284 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
282} 285}
283 286
284static bool ath9k_hw_chip_test(struct ath_hal *ah) 287static bool ath9k_hw_chip_test(struct ath_hw *ah)
285{ 288{
286 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; 289 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
287 u32 regHold[2]; 290 u32 regHold[2];
@@ -323,6 +326,7 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
323 REG_WRITE(ah, regAddr[i], regHold[i]); 326 REG_WRITE(ah, regAddr[i], regHold[i]);
324 } 327 }
325 udelay(100); 328 udelay(100);
329
326 return true; 330 return true;
327} 331}
328 332
@@ -347,7 +351,7 @@ static const char *ath9k_hw_devname(u16 devid)
347 return NULL; 351 return NULL;
348} 352}
349 353
350static void ath9k_hw_set_defaults(struct ath_hal *ah) 354static void ath9k_hw_set_defaults(struct ath_hw *ah)
351{ 355{
352 int i; 356 int i;
353 357
@@ -387,25 +391,20 @@ static void ath9k_hw_set_defaults(struct ath_hal *ah)
387 ah->ah_config.intr_mitigation = 1; 391 ah->ah_config.intr_mitigation = 1;
388} 392}
389 393
390static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, 394static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
391 struct ath_softc *sc, 395 int *status)
392 void __iomem *mem,
393 int *status)
394{ 396{
395 struct ath_hal_5416 *ahp; 397 struct ath_hw *ah;
396 struct ath_hal *ah;
397 398
398 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL); 399 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
399 if (ahp == NULL) { 400 if (ah == NULL) {
400 DPRINTF(sc, ATH_DBG_FATAL, 401 DPRINTF(sc, ATH_DBG_FATAL,
401 "Cannot allocate memory for state block\n"); 402 "Cannot allocate memory for state block\n");
402 *status = -ENOMEM; 403 *status = -ENOMEM;
403 return NULL; 404 return NULL;
404 } 405 }
405 406
406 ah = &ahp->ah;
407 ah->ah_sc = sc; 407 ah->ah_sc = sc;
408 ah->ah_sh = mem;
409 ah->hw_version.magic = AR5416_MAGIC; 408 ah->hw_version.magic = AR5416_MAGIC;
410 ah->regulatory.country_code = CTRY_DEFAULT; 409 ah->regulatory.country_code = CTRY_DEFAULT;
411 ah->hw_version.devid = devid; 410 ah->hw_version.devid = devid;
@@ -419,24 +418,24 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
419 418
420 ah->regulatory.power_limit = MAX_RATE_POWER; 419 ah->regulatory.power_limit = MAX_RATE_POWER;
421 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX; 420 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
422 ahp->ah_atimWindow = 0; 421 ah->ah_atimWindow = 0;
423 ahp->ah_diversityControl = ah->ah_config.diversity_control; 422 ah->ah_diversityControl = ah->ah_config.diversity_control;
424 ahp->ah_antennaSwitchSwap = 423 ah->ah_antennaSwitchSwap =
425 ah->ah_config.antenna_switch_swap; 424 ah->ah_config.antenna_switch_swap;
426 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 425 ah->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
427 ahp->ah_beaconInterval = 100; 426 ah->ah_beaconInterval = 100;
428 ahp->ah_enable32kHzClock = DONT_USE_32KHZ; 427 ah->ah_enable32kHzClock = DONT_USE_32KHZ;
429 ahp->ah_slottime = (u32) -1; 428 ah->ah_slottime = (u32) -1;
430 ahp->ah_acktimeout = (u32) -1; 429 ah->ah_acktimeout = (u32) -1;
431 ahp->ah_ctstimeout = (u32) -1; 430 ah->ah_ctstimeout = (u32) -1;
432 ahp->ah_globaltxtimeout = (u32) -1; 431 ah->ah_globaltxtimeout = (u32) -1;
433 432
434 ahp->ah_gBeaconRate = 0; 433 ah->ah_gBeaconRate = 0;
435 434
436 return ahp; 435 return ah;
437} 436}
438 437
439static int ath9k_hw_rfattach(struct ath_hal *ah) 438static int ath9k_hw_rfattach(struct ath_hw *ah)
440{ 439{
441 bool rfStatus = false; 440 bool rfStatus = false;
442 int ecode = 0; 441 int ecode = 0;
@@ -451,7 +450,7 @@ static int ath9k_hw_rfattach(struct ath_hal *ah)
451 return 0; 450 return 0;
452} 451}
453 452
454static int ath9k_hw_rf_claim(struct ath_hal *ah) 453static int ath9k_hw_rf_claim(struct ath_hw *ah)
455{ 454{
456 u32 val; 455 u32 val;
457 456
@@ -480,7 +479,7 @@ static int ath9k_hw_rf_claim(struct ath_hal *ah)
480 return 0; 479 return 0;
481} 480}
482 481
483static int ath9k_hw_init_macaddr(struct ath_hal *ah) 482static int ath9k_hw_init_macaddr(struct ath_hw *ah)
484{ 483{
485 u32 sum; 484 u32 sum;
486 int i; 485 int i;
@@ -503,55 +502,55 @@ static int ath9k_hw_init_macaddr(struct ath_hal *ah)
503 return 0; 502 return 0;
504} 503}
505 504
506static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah) 505static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
507{ 506{
508 u32 rxgain_type; 507 u32 rxgain_type;
509 struct ath_hal_5416 *ahp = AH5416(ah);
510 508
511 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { 509 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
512 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE); 510 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
513 511
514 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) 512 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
515 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 513 INIT_INI_ARRAY(&ah->ah_iniModesRxGain,
516 ar9280Modes_backoff_13db_rxgain_9280_2, 514 ar9280Modes_backoff_13db_rxgain_9280_2,
517 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); 515 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
518 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) 516 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
519 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 517 INIT_INI_ARRAY(&ah->ah_iniModesRxGain,
520 ar9280Modes_backoff_23db_rxgain_9280_2, 518 ar9280Modes_backoff_23db_rxgain_9280_2,
521 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); 519 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
522 else 520 else
523 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 521 INIT_INI_ARRAY(&ah->ah_iniModesRxGain,
524 ar9280Modes_original_rxgain_9280_2, 522 ar9280Modes_original_rxgain_9280_2,
525 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 523 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
526 } else 524 } else {
527 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 525 INIT_INI_ARRAY(&ah->ah_iniModesRxGain,
528 ar9280Modes_original_rxgain_9280_2, 526 ar9280Modes_original_rxgain_9280_2,
529 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 527 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
528 }
530} 529}
531 530
532static void ath9k_hw_init_txgain_ini(struct ath_hal *ah) 531static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
533{ 532{
534 u32 txgain_type; 533 u32 txgain_type;
535 struct ath_hal_5416 *ahp = AH5416(ah);
536 534
537 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { 535 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
538 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE); 536 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
539 537
540 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) 538 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
541 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, 539 INIT_INI_ARRAY(&ah->ah_iniModesTxGain,
542 ar9280Modes_high_power_tx_gain_9280_2, 540 ar9280Modes_high_power_tx_gain_9280_2,
543 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); 541 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
544 else 542 else
545 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, 543 INIT_INI_ARRAY(&ah->ah_iniModesTxGain,
546 ar9280Modes_original_tx_gain_9280_2, 544 ar9280Modes_original_tx_gain_9280_2,
547 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 545 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
548 } else 546 } else {
549 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, 547 INIT_INI_ARRAY(&ah->ah_iniModesTxGain,
550 ar9280Modes_original_tx_gain_9280_2, 548 ar9280Modes_original_tx_gain_9280_2,
551 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 549 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
550 }
552} 551}
553 552
554static int ath9k_hw_post_attach(struct ath_hal *ah) 553static int ath9k_hw_post_attach(struct ath_hw *ah)
555{ 554{
556 int ecode; 555 int ecode;
557 556
@@ -580,33 +579,30 @@ static int ath9k_hw_post_attach(struct ath_hal *ah)
580 return 0; 579 return 0;
581} 580}
582 581
583static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, 582static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
584 void __iomem *mem, int *status) 583 int *status)
585{ 584{
586 struct ath_hal_5416 *ahp; 585 struct ath_hw *ah;
587 struct ath_hal *ah;
588 int ecode; 586 int ecode;
589 u32 i, j; 587 u32 i, j;
590 588
591 ahp = ath9k_hw_newstate(devid, sc, mem, status); 589 ah = ath9k_hw_newstate(devid, sc, status);
592 if (ahp == NULL) 590 if (ah == NULL)
593 return NULL; 591 return NULL;
594 592
595 ah = &ahp->ah;
596
597 ath9k_hw_set_defaults(ah); 593 ath9k_hw_set_defaults(ah);
598 594
599 if (ah->ah_config.intr_mitigation != 0) 595 if (ah->ah_config.intr_mitigation != 0)
600 ahp->ah_intrMitigation = true; 596 ah->ah_intrMitigation = true;
601 597
602 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 598 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
603 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n"); 599 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
604 ecode = -EIO; 600 ecode = -EIO;
605 goto bad; 601 goto bad;
606 } 602 }
607 603
608 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 604 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
609 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n"); 605 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
610 ecode = -EIO; 606 ecode = -EIO;
611 goto bad; 607 goto bad;
612 } 608 }
@@ -621,15 +617,14 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
621 } 617 }
622 } 618 }
623 619
624 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 620 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
625 "serialize_regmode is %d\n",
626 ah->ah_config.serialize_regmode); 621 ah->ah_config.serialize_regmode);
627 622
628 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) && 623 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
629 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) && 624 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
630 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) && 625 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
631 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) { 626 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
632 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 627 DPRINTF(sc, ATH_DBG_RESET,
633 "Mac Chip Rev 0x%02x.%x is not supported by " 628 "Mac Chip Rev 0x%02x.%x is not supported by "
634 "this driver\n", ah->hw_version.macVersion, 629 "this driver\n", ah->hw_version.macVersion,
635 ah->hw_version.macRev); 630 ah->hw_version.macRev);
@@ -638,176 +633,176 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
638 } 633 }
639 634
640 if (AR_SREV_9100(ah)) { 635 if (AR_SREV_9100(ah)) {
641 ahp->ah_iqCalData.calData = &iq_cal_multi_sample; 636 ah->ah_iqCalData.calData = &iq_cal_multi_sample;
642 ahp->ah_suppCals = IQ_MISMATCH_CAL; 637 ah->ah_suppCals = IQ_MISMATCH_CAL;
643 ah->ah_isPciExpress = false; 638 ah->ah_isPciExpress = false;
644 } 639 }
645 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 640 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
646 641
647 if (AR_SREV_9160_10_OR_LATER(ah)) { 642 if (AR_SREV_9160_10_OR_LATER(ah)) {
648 if (AR_SREV_9280_10_OR_LATER(ah)) { 643 if (AR_SREV_9280_10_OR_LATER(ah)) {
649 ahp->ah_iqCalData.calData = &iq_cal_single_sample; 644 ah->ah_iqCalData.calData = &iq_cal_single_sample;
650 ahp->ah_adcGainCalData.calData = 645 ah->ah_adcGainCalData.calData =
651 &adc_gain_cal_single_sample; 646 &adc_gain_cal_single_sample;
652 ahp->ah_adcDcCalData.calData = 647 ah->ah_adcDcCalData.calData =
653 &adc_dc_cal_single_sample; 648 &adc_dc_cal_single_sample;
654 ahp->ah_adcDcCalInitData.calData = 649 ah->ah_adcDcCalInitData.calData =
655 &adc_init_dc_cal; 650 &adc_init_dc_cal;
656 } else { 651 } else {
657 ahp->ah_iqCalData.calData = &iq_cal_multi_sample; 652 ah->ah_iqCalData.calData = &iq_cal_multi_sample;
658 ahp->ah_adcGainCalData.calData = 653 ah->ah_adcGainCalData.calData =
659 &adc_gain_cal_multi_sample; 654 &adc_gain_cal_multi_sample;
660 ahp->ah_adcDcCalData.calData = 655 ah->ah_adcDcCalData.calData =
661 &adc_dc_cal_multi_sample; 656 &adc_dc_cal_multi_sample;
662 ahp->ah_adcDcCalInitData.calData = 657 ah->ah_adcDcCalInitData.calData =
663 &adc_init_dc_cal; 658 &adc_init_dc_cal;
664 } 659 }
665 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 660 ah->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
666 } 661 }
667 662
668 if (AR_SREV_9160(ah)) { 663 if (AR_SREV_9160(ah)) {
669 ah->ah_config.enable_ani = 1; 664 ah->ah_config.enable_ani = 1;
670 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | 665 ah->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
671 ATH9K_ANI_FIRSTEP_LEVEL); 666 ATH9K_ANI_FIRSTEP_LEVEL);
672 } else { 667 } else {
673 ahp->ah_ani_function = ATH9K_ANI_ALL; 668 ah->ah_ani_function = ATH9K_ANI_ALL;
674 if (AR_SREV_9280_10_OR_LATER(ah)) { 669 if (AR_SREV_9280_10_OR_LATER(ah)) {
675 ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 670 ah->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
676 } 671 }
677 } 672 }
678 673
679 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 674 DPRINTF(sc, ATH_DBG_RESET,
680 "This Mac Chip Rev 0x%02x.%x is \n", 675 "This Mac Chip Rev 0x%02x.%x is \n",
681 ah->hw_version.macVersion, ah->hw_version.macRev); 676 ah->hw_version.macVersion, ah->hw_version.macRev);
682 677
683 if (AR_SREV_9285_12_OR_LATER(ah)) { 678 if (AR_SREV_9285_12_OR_LATER(ah)) {
684 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2, 679 INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285_1_2,
685 ARRAY_SIZE(ar9285Modes_9285_1_2), 6); 680 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
686 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2, 681 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285_1_2,
687 ARRAY_SIZE(ar9285Common_9285_1_2), 2); 682 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
688 683
689 if (ah->ah_config.pcie_clock_req) { 684 if (ah->ah_config.pcie_clock_req) {
690 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 685 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
691 ar9285PciePhy_clkreq_off_L1_9285_1_2, 686 ar9285PciePhy_clkreq_off_L1_9285_1_2,
692 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); 687 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
693 } else { 688 } else {
694 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 689 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
695 ar9285PciePhy_clkreq_always_on_L1_9285_1_2, 690 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
696 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), 691 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
697 2); 692 2);
698 } 693 }
699 } else if (AR_SREV_9285_10_OR_LATER(ah)) { 694 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
700 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285, 695 INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285,
701 ARRAY_SIZE(ar9285Modes_9285), 6); 696 ARRAY_SIZE(ar9285Modes_9285), 6);
702 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285, 697 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285,
703 ARRAY_SIZE(ar9285Common_9285), 2); 698 ARRAY_SIZE(ar9285Common_9285), 2);
704 699
705 if (ah->ah_config.pcie_clock_req) { 700 if (ah->ah_config.pcie_clock_req) {
706 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 701 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
707 ar9285PciePhy_clkreq_off_L1_9285, 702 ar9285PciePhy_clkreq_off_L1_9285,
708 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); 703 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
709 } else { 704 } else {
710 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 705 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
711 ar9285PciePhy_clkreq_always_on_L1_9285, 706 ar9285PciePhy_clkreq_always_on_L1_9285,
712 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); 707 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
713 } 708 }
714 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 709 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
715 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2, 710 INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280_2,
716 ARRAY_SIZE(ar9280Modes_9280_2), 6); 711 ARRAY_SIZE(ar9280Modes_9280_2), 6);
717 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2, 712 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280_2,
718 ARRAY_SIZE(ar9280Common_9280_2), 2); 713 ARRAY_SIZE(ar9280Common_9280_2), 2);
719 714
720 if (ah->ah_config.pcie_clock_req) { 715 if (ah->ah_config.pcie_clock_req) {
721 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 716 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
722 ar9280PciePhy_clkreq_off_L1_9280, 717 ar9280PciePhy_clkreq_off_L1_9280,
723 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); 718 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
724 } else { 719 } else {
725 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 720 INIT_INI_ARRAY(&ah->ah_iniPcieSerdes,
726 ar9280PciePhy_clkreq_always_on_L1_9280, 721 ar9280PciePhy_clkreq_always_on_L1_9280,
727 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); 722 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
728 } 723 }
729 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional, 724 INIT_INI_ARRAY(&ah->ah_iniModesAdditional,
730 ar9280Modes_fast_clock_9280_2, 725 ar9280Modes_fast_clock_9280_2,
731 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); 726 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
732 } else if (AR_SREV_9280_10_OR_LATER(ah)) { 727 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
733 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280, 728 INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280,
734 ARRAY_SIZE(ar9280Modes_9280), 6); 729 ARRAY_SIZE(ar9280Modes_9280), 6);
735 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280, 730 INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280,
736 ARRAY_SIZE(ar9280Common_9280), 2); 731 ARRAY_SIZE(ar9280Common_9280), 2);
737 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 732 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
738 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160, 733 INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9160,
739 ARRAY_SIZE(ar5416Modes_9160), 6); 734 ARRAY_SIZE(ar5416Modes_9160), 6);
740 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160, 735 INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9160,
741 ARRAY_SIZE(ar5416Common_9160), 2); 736 ARRAY_SIZE(ar5416Common_9160), 2);
742 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160, 737 INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9160,
743 ARRAY_SIZE(ar5416Bank0_9160), 2); 738 ARRAY_SIZE(ar5416Bank0_9160), 2);
744 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160, 739 INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
745 ARRAY_SIZE(ar5416BB_RfGain_9160), 3); 740 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
746 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160, 741 INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9160,
747 ARRAY_SIZE(ar5416Bank1_9160), 2); 742 ARRAY_SIZE(ar5416Bank1_9160), 2);
748 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160, 743 INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9160,
749 ARRAY_SIZE(ar5416Bank2_9160), 2); 744 ARRAY_SIZE(ar5416Bank2_9160), 2);
750 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160, 745 INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9160,
751 ARRAY_SIZE(ar5416Bank3_9160), 3); 746 ARRAY_SIZE(ar5416Bank3_9160), 3);
752 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160, 747 INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9160,
753 ARRAY_SIZE(ar5416Bank6_9160), 3); 748 ARRAY_SIZE(ar5416Bank6_9160), 3);
754 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160, 749 INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9160,
755 ARRAY_SIZE(ar5416Bank6TPC_9160), 3); 750 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
756 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160, 751 INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9160,
757 ARRAY_SIZE(ar5416Bank7_9160), 2); 752 ARRAY_SIZE(ar5416Bank7_9160), 2);
758 if (AR_SREV_9160_11(ah)) { 753 if (AR_SREV_9160_11(ah)) {
759 INIT_INI_ARRAY(&ahp->ah_iniAddac, 754 INIT_INI_ARRAY(&ah->ah_iniAddac,
760 ar5416Addac_91601_1, 755 ar5416Addac_91601_1,
761 ARRAY_SIZE(ar5416Addac_91601_1), 2); 756 ARRAY_SIZE(ar5416Addac_91601_1), 2);
762 } else { 757 } else {
763 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160, 758 INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9160,
764 ARRAY_SIZE(ar5416Addac_9160), 2); 759 ARRAY_SIZE(ar5416Addac_9160), 2);
765 } 760 }
766 } else if (AR_SREV_9100_OR_LATER(ah)) { 761 } else if (AR_SREV_9100_OR_LATER(ah)) {
767 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100, 762 INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9100,
768 ARRAY_SIZE(ar5416Modes_9100), 6); 763 ARRAY_SIZE(ar5416Modes_9100), 6);
769 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100, 764 INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9100,
770 ARRAY_SIZE(ar5416Common_9100), 2); 765 ARRAY_SIZE(ar5416Common_9100), 2);
771 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100, 766 INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9100,
772 ARRAY_SIZE(ar5416Bank0_9100), 2); 767 ARRAY_SIZE(ar5416Bank0_9100), 2);
773 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100, 768 INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
774 ARRAY_SIZE(ar5416BB_RfGain_9100), 3); 769 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
775 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100, 770 INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9100,
776 ARRAY_SIZE(ar5416Bank1_9100), 2); 771 ARRAY_SIZE(ar5416Bank1_9100), 2);
777 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100, 772 INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9100,
778 ARRAY_SIZE(ar5416Bank2_9100), 2); 773 ARRAY_SIZE(ar5416Bank2_9100), 2);
779 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100, 774 INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9100,
780 ARRAY_SIZE(ar5416Bank3_9100), 3); 775 ARRAY_SIZE(ar5416Bank3_9100), 3);
781 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100, 776 INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9100,
782 ARRAY_SIZE(ar5416Bank6_9100), 3); 777 ARRAY_SIZE(ar5416Bank6_9100), 3);
783 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100, 778 INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9100,
784 ARRAY_SIZE(ar5416Bank6TPC_9100), 3); 779 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
785 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100, 780 INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9100,
786 ARRAY_SIZE(ar5416Bank7_9100), 2); 781 ARRAY_SIZE(ar5416Bank7_9100), 2);
787 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100, 782 INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9100,
788 ARRAY_SIZE(ar5416Addac_9100), 2); 783 ARRAY_SIZE(ar5416Addac_9100), 2);
789 } else { 784 } else {
790 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes, 785 INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes,
791 ARRAY_SIZE(ar5416Modes), 6); 786 ARRAY_SIZE(ar5416Modes), 6);
792 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common, 787 INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common,
793 ARRAY_SIZE(ar5416Common), 2); 788 ARRAY_SIZE(ar5416Common), 2);
794 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0, 789 INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0,
795 ARRAY_SIZE(ar5416Bank0), 2); 790 ARRAY_SIZE(ar5416Bank0), 2);
796 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain, 791 INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain,
797 ARRAY_SIZE(ar5416BB_RfGain), 3); 792 ARRAY_SIZE(ar5416BB_RfGain), 3);
798 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1, 793 INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1,
799 ARRAY_SIZE(ar5416Bank1), 2); 794 ARRAY_SIZE(ar5416Bank1), 2);
800 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2, 795 INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2,
801 ARRAY_SIZE(ar5416Bank2), 2); 796 ARRAY_SIZE(ar5416Bank2), 2);
802 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3, 797 INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3,
803 ARRAY_SIZE(ar5416Bank3), 3); 798 ARRAY_SIZE(ar5416Bank3), 3);
804 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6, 799 INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6,
805 ARRAY_SIZE(ar5416Bank6), 3); 800 ARRAY_SIZE(ar5416Bank6), 3);
806 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC, 801 INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC,
807 ARRAY_SIZE(ar5416Bank6TPC), 3); 802 ARRAY_SIZE(ar5416Bank6TPC), 3);
808 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7, 803 INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7,
809 ARRAY_SIZE(ar5416Bank7), 2); 804 ARRAY_SIZE(ar5416Bank7), 2);
810 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac, 805 INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac,
811 ARRAY_SIZE(ar5416Addac), 2); 806 ARRAY_SIZE(ar5416Addac), 2);
812 } 807 }
813 808
@@ -829,22 +824,22 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
829 ath9k_hw_init_txgain_ini(ah); 824 ath9k_hw_init_txgain_ini(ah);
830 825
831 if (ah->hw_version.devid == AR9280_DEVID_PCI) { 826 if (ah->hw_version.devid == AR9280_DEVID_PCI) {
832 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { 827 for (i = 0; i < ah->ah_iniModes.ia_rows; i++) {
833 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); 828 u32 reg = INI_RA(&ah->ah_iniModes, i, 0);
834 829
835 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) { 830 for (j = 1; j < ah->ah_iniModes.ia_columns; j++) {
836 u32 val = INI_RA(&ahp->ah_iniModes, i, j); 831 u32 val = INI_RA(&ah->ah_iniModes, i, j);
837 832
838 INI_RA(&ahp->ah_iniModes, i, j) = 833 INI_RA(&ah->ah_iniModes, i, j) =
839 ath9k_hw_ini_fixup(ah, 834 ath9k_hw_ini_fixup(ah,
840 &ahp->ah_eeprom.def, 835 &ah->ah_eeprom.def,
841 reg, val); 836 reg, val);
842 } 837 }
843 } 838 }
844 } 839 }
845 840
846 if (!ath9k_hw_fill_cap_info(ah)) { 841 if (!ath9k_hw_fill_cap_info(ah)) {
847 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 842 DPRINTF(sc, ATH_DBG_RESET,
848 "failed ath9k_hw_fill_cap_info\n"); 843 "failed ath9k_hw_fill_cap_info\n");
849 ecode = -EINVAL; 844 ecode = -EINVAL;
850 goto bad; 845 goto bad;
@@ -852,7 +847,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
852 847
853 ecode = ath9k_hw_init_macaddr(ah); 848 ecode = ath9k_hw_init_macaddr(ah);
854 if (ecode != 0) { 849 if (ecode != 0) {
855 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 850 DPRINTF(sc, ATH_DBG_RESET,
856 "failed initializing mac address\n"); 851 "failed initializing mac address\n");
857 goto bad; 852 goto bad;
858 } 853 }
@@ -866,15 +861,15 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
866 861
867 return ah; 862 return ah;
868bad: 863bad:
869 if (ahp) 864 if (ah)
870 ath9k_hw_detach((struct ath_hal *) ahp); 865 ath9k_hw_detach(ah);
871 if (status) 866 if (status)
872 *status = ecode; 867 *status = ecode;
873 868
874 return NULL; 869 return NULL;
875} 870}
876 871
877static void ath9k_hw_init_bb(struct ath_hal *ah, 872static void ath9k_hw_init_bb(struct ath_hw *ah,
878 struct ath9k_channel *chan) 873 struct ath9k_channel *chan)
879{ 874{
880 u32 synthDelay; 875 u32 synthDelay;
@@ -890,7 +885,7 @@ static void ath9k_hw_init_bb(struct ath_hal *ah,
890 udelay(synthDelay + BASE_ACTIVATE_DELAY); 885 udelay(synthDelay + BASE_ACTIVATE_DELAY);
891} 886}
892 887
893static void ath9k_hw_init_qos(struct ath_hal *ah) 888static void ath9k_hw_init_qos(struct ath_hw *ah)
894{ 889{
895 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 890 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
896 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 891 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
@@ -907,7 +902,7 @@ static void ath9k_hw_init_qos(struct ath_hal *ah)
907 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 902 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
908} 903}
909 904
910static void ath9k_hw_init_pll(struct ath_hal *ah, 905static void ath9k_hw_init_pll(struct ath_hw *ah,
911 struct ath9k_channel *chan) 906 struct ath9k_channel *chan)
912{ 907{
913 u32 pll; 908 u32 pll;
@@ -975,13 +970,12 @@ static void ath9k_hw_init_pll(struct ath_hal *ah,
975 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 970 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
976} 971}
977 972
978static void ath9k_hw_init_chain_masks(struct ath_hal *ah) 973static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
979{ 974{
980 struct ath_hal_5416 *ahp = AH5416(ah);
981 int rx_chainmask, tx_chainmask; 975 int rx_chainmask, tx_chainmask;
982 976
983 rx_chainmask = ahp->ah_rxchainmask; 977 rx_chainmask = ah->ah_rxchainmask;
984 tx_chainmask = ahp->ah_txchainmask; 978 tx_chainmask = ah->ah_txchainmask;
985 979
986 switch (rx_chainmask) { 980 switch (rx_chainmask) {
987 case 0x5: 981 case 0x5:
@@ -1013,28 +1007,26 @@ static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1013 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 1007 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1014} 1008}
1015 1009
1016static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, 1010static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1017 enum nl80211_iftype opmode) 1011 enum nl80211_iftype opmode)
1018{ 1012{
1019 struct ath_hal_5416 *ahp = AH5416(ah); 1013 ah->ah_maskReg = AR_IMR_TXERR |
1020
1021 ahp->ah_maskReg = AR_IMR_TXERR |
1022 AR_IMR_TXURN | 1014 AR_IMR_TXURN |
1023 AR_IMR_RXERR | 1015 AR_IMR_RXERR |
1024 AR_IMR_RXORN | 1016 AR_IMR_RXORN |
1025 AR_IMR_BCNMISC; 1017 AR_IMR_BCNMISC;
1026 1018
1027 if (ahp->ah_intrMitigation) 1019 if (ah->ah_intrMitigation)
1028 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 1020 ah->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1029 else 1021 else
1030 ahp->ah_maskReg |= AR_IMR_RXOK; 1022 ah->ah_maskReg |= AR_IMR_RXOK;
1031 1023
1032 ahp->ah_maskReg |= AR_IMR_TXOK; 1024 ah->ah_maskReg |= AR_IMR_TXOK;
1033 1025
1034 if (opmode == NL80211_IFTYPE_AP) 1026 if (opmode == NL80211_IFTYPE_AP)
1035 ahp->ah_maskReg |= AR_IMR_MIB; 1027 ah->ah_maskReg |= AR_IMR_MIB;
1036 1028
1037 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); 1029 REG_WRITE(ah, AR_IMR, ah->ah_maskReg);
1038 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); 1030 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1039 1031
1040 if (!AR_SREV_9100(ah)) { 1032 if (!AR_SREV_9100(ah)) {
@@ -1044,72 +1036,64 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1044 } 1036 }
1045} 1037}
1046 1038
1047static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us) 1039static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1048{ 1040{
1049 struct ath_hal_5416 *ahp = AH5416(ah);
1050
1051 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 1041 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1052 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us); 1042 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1053 ahp->ah_acktimeout = (u32) -1; 1043 ah->ah_acktimeout = (u32) -1;
1054 return false; 1044 return false;
1055 } else { 1045 } else {
1056 REG_RMW_FIELD(ah, AR_TIME_OUT, 1046 REG_RMW_FIELD(ah, AR_TIME_OUT,
1057 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us)); 1047 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1058 ahp->ah_acktimeout = us; 1048 ah->ah_acktimeout = us;
1059 return true; 1049 return true;
1060 } 1050 }
1061} 1051}
1062 1052
1063static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us) 1053static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1064{ 1054{
1065 struct ath_hal_5416 *ahp = AH5416(ah);
1066
1067 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { 1055 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1068 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us); 1056 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1069 ahp->ah_ctstimeout = (u32) -1; 1057 ah->ah_ctstimeout = (u32) -1;
1070 return false; 1058 return false;
1071 } else { 1059 } else {
1072 REG_RMW_FIELD(ah, AR_TIME_OUT, 1060 REG_RMW_FIELD(ah, AR_TIME_OUT,
1073 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); 1061 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1074 ahp->ah_ctstimeout = us; 1062 ah->ah_ctstimeout = us;
1075 return true; 1063 return true;
1076 } 1064 }
1077} 1065}
1078 1066
1079static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu) 1067static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1080{ 1068{
1081 struct ath_hal_5416 *ahp = AH5416(ah);
1082
1083 if (tu > 0xFFFF) { 1069 if (tu > 0xFFFF) {
1084 DPRINTF(ah->ah_sc, ATH_DBG_XMIT, 1070 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1085 "bad global tx timeout %u\n", tu); 1071 "bad global tx timeout %u\n", tu);
1086 ahp->ah_globaltxtimeout = (u32) -1; 1072 ah->ah_globaltxtimeout = (u32) -1;
1087 return false; 1073 return false;
1088 } else { 1074 } else {
1089 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1075 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1090 ahp->ah_globaltxtimeout = tu; 1076 ah->ah_globaltxtimeout = tu;
1091 return true; 1077 return true;
1092 } 1078 }
1093} 1079}
1094 1080
1095static void ath9k_hw_init_user_settings(struct ath_hal *ah) 1081static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1096{ 1082{
1097 struct ath_hal_5416 *ahp = AH5416(ah); 1083 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->ah_miscMode 0x%x\n",
1084 ah->ah_miscMode);
1098 1085
1099 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n", 1086 if (ah->ah_miscMode != 0)
1100 ahp->ah_miscMode);
1101
1102 if (ahp->ah_miscMode != 0)
1103 REG_WRITE(ah, AR_PCU_MISC, 1087 REG_WRITE(ah, AR_PCU_MISC,
1104 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode); 1088 REG_READ(ah, AR_PCU_MISC) | ah->ah_miscMode);
1105 if (ahp->ah_slottime != (u32) -1) 1089 if (ah->ah_slottime != (u32) -1)
1106 ath9k_hw_setslottime(ah, ahp->ah_slottime); 1090 ath9k_hw_setslottime(ah, ah->ah_slottime);
1107 if (ahp->ah_acktimeout != (u32) -1) 1091 if (ah->ah_acktimeout != (u32) -1)
1108 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout); 1092 ath9k_hw_set_ack_timeout(ah, ah->ah_acktimeout);
1109 if (ahp->ah_ctstimeout != (u32) -1) 1093 if (ah->ah_ctstimeout != (u32) -1)
1110 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout); 1094 ath9k_hw_set_cts_timeout(ah, ah->ah_ctstimeout);
1111 if (ahp->ah_globaltxtimeout != (u32) -1) 1095 if (ah->ah_globaltxtimeout != (u32) -1)
1112 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout); 1096 ath9k_hw_set_global_txtimeout(ah, ah->ah_globaltxtimeout);
1113} 1097}
1114 1098
1115const char *ath9k_hw_probe(u16 vendorid, u16 devid) 1099const char *ath9k_hw_probe(u16 vendorid, u16 devid)
@@ -1118,7 +1102,7 @@ const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1118 ath9k_hw_devname(devid) : NULL; 1102 ath9k_hw_devname(devid) : NULL;
1119} 1103}
1120 1104
1121void ath9k_hw_detach(struct ath_hal *ah) 1105void ath9k_hw_detach(struct ath_hw *ah)
1122{ 1106{
1123 if (!AR_SREV_9100(ah)) 1107 if (!AR_SREV_9100(ah))
1124 ath9k_hw_ani_detach(ah); 1108 ath9k_hw_ani_detach(ah);
@@ -1128,10 +1112,9 @@ void ath9k_hw_detach(struct ath_hal *ah)
1128 kfree(ah); 1112 kfree(ah);
1129} 1113}
1130 1114
1131struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, 1115struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1132 void __iomem *mem, int *error)
1133{ 1116{
1134 struct ath_hal *ah = NULL; 1117 struct ath_hw *ah = NULL;
1135 1118
1136 switch (devid) { 1119 switch (devid) {
1137 case AR5416_DEVID_PCI: 1120 case AR5416_DEVID_PCI:
@@ -1141,7 +1124,7 @@ struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1141 case AR9280_DEVID_PCI: 1124 case AR9280_DEVID_PCI:
1142 case AR9280_DEVID_PCIE: 1125 case AR9280_DEVID_PCIE:
1143 case AR9285_DEVID_PCIE: 1126 case AR9285_DEVID_PCIE:
1144 ah = ath9k_hw_do_attach(devid, sc, mem, error); 1127 ah = ath9k_hw_do_attach(devid, sc, error);
1145 break; 1128 break;
1146 default: 1129 default:
1147 *error = -ENXIO; 1130 *error = -ENXIO;
@@ -1155,7 +1138,7 @@ struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1155/* INI */ 1138/* INI */
1156/*******/ 1139/*******/
1157 1140
1158static void ath9k_hw_override_ini(struct ath_hal *ah, 1141static void ath9k_hw_override_ini(struct ath_hw *ah,
1159 struct ath9k_channel *chan) 1142 struct ath9k_channel *chan)
1160{ 1143{
1161 /* 1144 /*
@@ -1173,7 +1156,7 @@ static void ath9k_hw_override_ini(struct ath_hal *ah,
1173 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 1156 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1174} 1157}
1175 1158
1176static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah, 1159static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1177 struct ar5416_eeprom_def *pEepData, 1160 struct ar5416_eeprom_def *pEepData,
1178 u32 reg, u32 value) 1161 u32 reg, u32 value)
1179{ 1162{
@@ -1207,24 +1190,21 @@ static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1207 return value; 1190 return value;
1208} 1191}
1209 1192
1210static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, 1193static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1211 struct ar5416_eeprom_def *pEepData, 1194 struct ar5416_eeprom_def *pEepData,
1212 u32 reg, u32 value) 1195 u32 reg, u32 value)
1213{ 1196{
1214 struct ath_hal_5416 *ahp = AH5416(ah); 1197 if (ah->ah_eep_map == EEP_MAP_4KBITS)
1215
1216 if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1217 return value; 1198 return value;
1218 else 1199 else
1219 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value); 1200 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1220} 1201}
1221 1202
1222static int ath9k_hw_process_ini(struct ath_hal *ah, 1203static int ath9k_hw_process_ini(struct ath_hw *ah,
1223 struct ath9k_channel *chan, 1204 struct ath9k_channel *chan,
1224 enum ath9k_ht_macmode macmode) 1205 enum ath9k_ht_macmode macmode)
1225{ 1206{
1226 int i, regWrites = 0; 1207 int i, regWrites = 0;
1227 struct ath_hal_5416 *ahp = AH5416(ah);
1228 struct ieee80211_channel *channel = chan->chan; 1208 struct ieee80211_channel *channel = chan->chan;
1229 u32 modesIndex, freqIndex; 1209 u32 modesIndex, freqIndex;
1230 int status; 1210 int status;
@@ -1257,35 +1237,33 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1257 } 1237 }
1258 1238
1259 REG_WRITE(ah, AR_PHY(0), 0x00000007); 1239 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1260
1261 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 1240 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1262
1263 ath9k_hw_set_addac(ah, chan); 1241 ath9k_hw_set_addac(ah, chan);
1264 1242
1265 if (AR_SREV_5416_V22_OR_LATER(ah)) { 1243 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1266 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites); 1244 REG_WRITE_ARRAY(&ah->ah_iniAddac, 1, regWrites);
1267 } else { 1245 } else {
1268 struct ar5416IniArray temp; 1246 struct ar5416IniArray temp;
1269 u32 addacSize = 1247 u32 addacSize =
1270 sizeof(u32) * ahp->ah_iniAddac.ia_rows * 1248 sizeof(u32) * ah->ah_iniAddac.ia_rows *
1271 ahp->ah_iniAddac.ia_columns; 1249 ah->ah_iniAddac.ia_columns;
1272 1250
1273 memcpy(ahp->ah_addac5416_21, 1251 memcpy(ah->ah_addac5416_21,
1274 ahp->ah_iniAddac.ia_array, addacSize); 1252 ah->ah_iniAddac.ia_array, addacSize);
1275 1253
1276 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0; 1254 (ah->ah_addac5416_21)[31 * ah->ah_iniAddac.ia_columns + 1] = 0;
1277 1255
1278 temp.ia_array = ahp->ah_addac5416_21; 1256 temp.ia_array = ah->ah_addac5416_21;
1279 temp.ia_columns = ahp->ah_iniAddac.ia_columns; 1257 temp.ia_columns = ah->ah_iniAddac.ia_columns;
1280 temp.ia_rows = ahp->ah_iniAddac.ia_rows; 1258 temp.ia_rows = ah->ah_iniAddac.ia_rows;
1281 REG_WRITE_ARRAY(&temp, 1, regWrites); 1259 REG_WRITE_ARRAY(&temp, 1, regWrites);
1282 } 1260 }
1283 1261
1284 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 1262 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1285 1263
1286 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { 1264 for (i = 0; i < ah->ah_iniModes.ia_rows; i++) {
1287 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); 1265 u32 reg = INI_RA(&ah->ah_iniModes, i, 0);
1288 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex); 1266 u32 val = INI_RA(&ah->ah_iniModes, i, modesIndex);
1289 1267
1290 REG_WRITE(ah, reg, val); 1268 REG_WRITE(ah, reg, val);
1291 1269
@@ -1298,14 +1276,14 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1298 } 1276 }
1299 1277
1300 if (AR_SREV_9280(ah)) 1278 if (AR_SREV_9280(ah))
1301 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites); 1279 REG_WRITE_ARRAY(&ah->ah_iniModesRxGain, modesIndex, regWrites);
1302 1280
1303 if (AR_SREV_9280(ah)) 1281 if (AR_SREV_9280(ah))
1304 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites); 1282 REG_WRITE_ARRAY(&ah->ah_iniModesTxGain, modesIndex, regWrites);
1305 1283
1306 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) { 1284 for (i = 0; i < ah->ah_iniCommon.ia_rows; i++) {
1307 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0); 1285 u32 reg = INI_RA(&ah->ah_iniCommon, i, 0);
1308 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1); 1286 u32 val = INI_RA(&ah->ah_iniCommon, i, 1);
1309 1287
1310 REG_WRITE(ah, reg, val); 1288 REG_WRITE(ah, reg, val);
1311 1289
@@ -1320,7 +1298,7 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1320 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); 1298 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1321 1299
1322 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { 1300 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1323 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex, 1301 REG_WRITE_ARRAY(&ah->ah_iniModesAdditional, modesIndex,
1324 regWrites); 1302 regWrites);
1325 } 1303 }
1326 1304
@@ -1353,7 +1331,7 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1353/* Reset and Channel Switching Routines */ 1331/* Reset and Channel Switching Routines */
1354/****************************************/ 1332/****************************************/
1355 1333
1356static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan) 1334static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1357{ 1335{
1358 u32 rfMode = 0; 1336 u32 rfMode = 0;
1359 1337
@@ -1373,12 +1351,12 @@ static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1373 REG_WRITE(ah, AR_PHY_MODE, rfMode); 1351 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1374} 1352}
1375 1353
1376static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah) 1354static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1377{ 1355{
1378 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 1356 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1379} 1357}
1380 1358
1381static inline void ath9k_hw_set_dma(struct ath_hal *ah) 1359static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1382{ 1360{
1383 u32 regval; 1361 u32 regval;
1384 1362
@@ -1404,7 +1382,7 @@ static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1404 } 1382 }
1405} 1383}
1406 1384
1407static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode) 1385static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1408{ 1386{
1409 u32 val; 1387 u32 val;
1410 1388
@@ -1428,7 +1406,7 @@ static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1428 } 1406 }
1429} 1407}
1430 1408
1431static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah, 1409static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1432 u32 coef_scaled, 1410 u32 coef_scaled,
1433 u32 *coef_mantissa, 1411 u32 *coef_mantissa,
1434 u32 *coef_exponent) 1412 u32 *coef_exponent)
@@ -1447,7 +1425,7 @@ static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1447 *coef_exponent = coef_exp - 16; 1425 *coef_exponent = coef_exp - 16;
1448} 1426}
1449 1427
1450static void ath9k_hw_set_delta_slope(struct ath_hal *ah, 1428static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1451 struct ath9k_channel *chan) 1429 struct ath9k_channel *chan)
1452{ 1430{
1453 u32 coef_scaled, ds_coef_exp, ds_coef_man; 1431 u32 coef_scaled, ds_coef_exp, ds_coef_man;
@@ -1481,7 +1459,7 @@ static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1481 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 1459 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1482} 1460}
1483 1461
1484static bool ath9k_hw_set_reset(struct ath_hal *ah, int type) 1462static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1485{ 1463{
1486 u32 rst_flags; 1464 u32 rst_flags;
1487 u32 tmpReg; 1465 u32 tmpReg;
@@ -1529,7 +1507,7 @@ static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1529 return true; 1507 return true;
1530} 1508}
1531 1509
1532static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah) 1510static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1533{ 1511{
1534 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1512 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1535 AR_RTC_FORCE_WAKE_ON_INT); 1513 AR_RTC_FORCE_WAKE_ON_INT);
@@ -1550,7 +1528,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1550 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1528 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1551} 1529}
1552 1530
1553static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type) 1531static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1554{ 1532{
1555 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1533 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1556 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1534 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
@@ -1568,12 +1546,11 @@ static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1568 } 1546 }
1569} 1547}
1570 1548
1571static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, 1549static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1572 enum ath9k_ht_macmode macmode) 1550 enum ath9k_ht_macmode macmode)
1573{ 1551{
1574 u32 phymode; 1552 u32 phymode;
1575 u32 enableDacFifo = 0; 1553 u32 enableDacFifo = 0;
1576 struct ath_hal_5416 *ahp = AH5416(ah);
1577 1554
1578 if (AR_SREV_9285_10_OR_LATER(ah)) 1555 if (AR_SREV_9285_10_OR_LATER(ah))
1579 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 1556 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
@@ -1589,7 +1566,7 @@ static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1589 (chan->chanmode == CHANNEL_G_HT40PLUS)) 1566 (chan->chanmode == CHANNEL_G_HT40PLUS))
1590 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 1567 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1591 1568
1592 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25) 1569 if (ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1593 phymode |= AR_PHY_FC_DYN2040_EXT_CH; 1570 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1594 } 1571 }
1595 REG_WRITE(ah, AR_PHY_TURBO, phymode); 1572 REG_WRITE(ah, AR_PHY_TURBO, phymode);
@@ -1600,27 +1577,23 @@ static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1600 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 1577 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1601} 1578}
1602 1579
1603static bool ath9k_hw_chip_reset(struct ath_hal *ah, 1580static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1604 struct ath9k_channel *chan) 1581 struct ath9k_channel *chan)
1605{ 1582{
1606 struct ath_hal_5416 *ahp = AH5416(ah);
1607
1608 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1583 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1609 return false; 1584 return false;
1610 1585
1611 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1586 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1612 return false; 1587 return false;
1613 1588
1614 ahp->ah_chipFullSleep = false; 1589 ah->ah_chipFullSleep = false;
1615
1616 ath9k_hw_init_pll(ah, chan); 1590 ath9k_hw_init_pll(ah, chan);
1617
1618 ath9k_hw_set_rfmode(ah, chan); 1591 ath9k_hw_set_rfmode(ah, chan);
1619 1592
1620 return true; 1593 return true;
1621} 1594}
1622 1595
1623static bool ath9k_hw_channel_change(struct ath_hal *ah, 1596static bool ath9k_hw_channel_change(struct ath_hw *ah,
1624 struct ath9k_channel *chan, 1597 struct ath9k_channel *chan,
1625 enum ath9k_ht_macmode macmode) 1598 enum ath9k_ht_macmode macmode)
1626{ 1599{
@@ -1694,7 +1667,7 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah,
1694 return true; 1667 return true;
1695} 1668}
1696 1669
1697static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) 1670static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1698{ 1671{
1699 int bb_spur = AR_NO_SPUR; 1672 int bb_spur = AR_NO_SPUR;
1700 int freq; 1673 int freq;
@@ -1944,7 +1917,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel
1944 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 1917 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1945} 1918}
1946 1919
1947static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) 1920static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1948{ 1921{
1949 int bb_spur = AR_NO_SPUR; 1922 int bb_spur = AR_NO_SPUR;
1950 int bin, cur_bin; 1923 int bin, cur_bin;
@@ -2145,27 +2118,26 @@ static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *cha
2145 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 2118 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2146} 2119}
2147 2120
2148int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, 2121int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2149 bool bChannelChange) 2122 bool bChannelChange)
2150{ 2123{
2151 u32 saveLedState; 2124 u32 saveLedState;
2152 struct ath_softc *sc = ah->ah_sc; 2125 struct ath_softc *sc = ah->ah_sc;
2153 struct ath_hal_5416 *ahp = AH5416(ah);
2154 struct ath9k_channel *curchan = ah->ah_curchan; 2126 struct ath9k_channel *curchan = ah->ah_curchan;
2155 u32 saveDefAntenna; 2127 u32 saveDefAntenna;
2156 u32 macStaId1; 2128 u32 macStaId1;
2157 int i, rx_chainmask, r; 2129 int i, rx_chainmask, r;
2158 2130
2159 ahp->ah_extprotspacing = sc->ht_extprotspacing; 2131 ah->ah_extprotspacing = sc->ht_extprotspacing;
2160 ahp->ah_txchainmask = sc->tx_chainmask; 2132 ah->ah_txchainmask = sc->tx_chainmask;
2161 ahp->ah_rxchainmask = sc->rx_chainmask; 2133 ah->ah_rxchainmask = sc->rx_chainmask;
2162 2134
2163 if (AR_SREV_9285(ah)) { 2135 if (AR_SREV_9285(ah)) {
2164 ahp->ah_txchainmask &= 0x1; 2136 ah->ah_txchainmask &= 0x1;
2165 ahp->ah_rxchainmask &= 0x1; 2137 ah->ah_rxchainmask &= 0x1;
2166 } else if (AR_SREV_9280(ah)) { 2138 } else if (AR_SREV_9280(ah)) {
2167 ahp->ah_txchainmask &= 0x3; 2139 ah->ah_txchainmask &= 0x3;
2168 ahp->ah_rxchainmask &= 0x3; 2140 ah->ah_rxchainmask &= 0x3;
2169 } 2141 }
2170 2142
2171 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2143 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
@@ -2175,7 +2147,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2175 ath9k_hw_getnf(ah, curchan); 2147 ath9k_hw_getnf(ah, curchan);
2176 2148
2177 if (bChannelChange && 2149 if (bChannelChange &&
2178 (ahp->ah_chipFullSleep != true) && 2150 (ah->ah_chipFullSleep != true) &&
2179 (ah->ah_curchan != NULL) && 2151 (ah->ah_curchan != NULL) &&
2180 (chan->channel != ah->ah_curchan->channel) && 2152 (chan->channel != ah->ah_curchan->channel) &&
2181 ((chan->channelFlags & CHANNEL_ALL) == 2153 ((chan->channelFlags & CHANNEL_ALL) ==
@@ -2253,7 +2225,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2253 | AR_STA_ID1_RTS_USE_DEF 2225 | AR_STA_ID1_RTS_USE_DEF
2254 | (ah->ah_config. 2226 | (ah->ah_config.
2255 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 2227 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2256 | ahp->ah_staId1Defaults); 2228 | ah->ah_staId1Defaults);
2257 ath9k_hw_set_operating_mode(ah, ah->ah_opmode); 2229 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2258 2230
2259 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); 2231 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
@@ -2280,7 +2252,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2280 for (i = 0; i < AR_NUM_DCU; i++) 2252 for (i = 0; i < AR_NUM_DCU; i++)
2281 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 2253 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2282 2254
2283 ahp->ah_intrTxqs = 0; 2255 ah->ah_intrTxqs = 0;
2284 for (i = 0; i < ah->ah_caps.total_queues; i++) 2256 for (i = 0; i < ah->ah_caps.total_queues; i++)
2285 ath9k_hw_resettxqueue(ah, i); 2257 ath9k_hw_resettxqueue(ah, i);
2286 2258
@@ -2300,7 +2272,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2300 2272
2301 REG_WRITE(ah, AR_OBS, 8); 2273 REG_WRITE(ah, AR_OBS, 8);
2302 2274
2303 if (ahp->ah_intrMitigation) { 2275 if (ah->ah_intrMitigation) {
2304 2276
2305 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 2277 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2306 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 2278 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
@@ -2311,7 +2283,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2311 if (!ath9k_hw_init_cal(ah, chan)) 2283 if (!ath9k_hw_init_cal(ah, chan))
2312 return -EIO;; 2284 return -EIO;;
2313 2285
2314 rx_chainmask = ahp->ah_rxchainmask; 2286 rx_chainmask = ah->ah_rxchainmask;
2315 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 2287 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2316 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 2288 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2317 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 2289 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
@@ -2345,7 +2317,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2345/* Key Cache Management */ 2317/* Key Cache Management */
2346/************************/ 2318/************************/
2347 2319
2348bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry) 2320bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2349{ 2321{
2350 u32 keyType; 2322 u32 keyType;
2351 2323
@@ -2382,7 +2354,7 @@ bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2382 return true; 2354 return true;
2383} 2355}
2384 2356
2385bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac) 2357bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2386{ 2358{
2387 u32 macHi, macLo; 2359 u32 macHi, macLo;
2388 2360
@@ -2410,7 +2382,7 @@ bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2410 return true; 2382 return true;
2411} 2383}
2412 2384
2413bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, 2385bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2414 const struct ath9k_keyval *k, 2386 const struct ath9k_keyval *k,
2415 const u8 *mac, int xorKey) 2387 const u8 *mac, int xorKey)
2416{ 2388{
@@ -2420,7 +2392,6 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2420 u32 xorMask = xorKey ? 2392 u32 xorMask = xorKey ?
2421 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8 2393 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2422 | ATH9K_KEY_XOR) : 0; 2394 | ATH9K_KEY_XOR) : 0;
2423 struct ath_hal_5416 *ahp = AH5416(ah);
2424 2395
2425 if (entry >= pCap->keycache_size) { 2396 if (entry >= pCap->keycache_size) {
2426 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2397 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
@@ -2491,7 +2462,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2491 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 2462 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2492 (void) ath9k_hw_keysetmac(ah, entry, mac); 2463 (void) ath9k_hw_keysetmac(ah, entry, mac);
2493 2464
2494 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) { 2465 if (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2495 u32 mic0, mic1, mic2, mic3, mic4; 2466 u32 mic0, mic1, mic2, mic3, mic4;
2496 2467
2497 mic0 = get_unaligned_le32(k->kv_mic + 0); 2468 mic0 = get_unaligned_le32(k->kv_mic + 0);
@@ -2541,7 +2512,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2541 return true; 2512 return true;
2542} 2513}
2543 2514
2544bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry) 2515bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2545{ 2516{
2546 if (entry < ah->ah_caps.keycache_size) { 2517 if (entry < ah->ah_caps.keycache_size) {
2547 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 2518 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
@@ -2555,7 +2526,7 @@ bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2555/* Power Management (Chipset) */ 2526/* Power Management (Chipset) */
2556/******************************/ 2527/******************************/
2557 2528
2558static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip) 2529static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2559{ 2530{
2560 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2531 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2561 if (setChip) { 2532 if (setChip) {
@@ -2569,7 +2540,7 @@ static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2569 } 2540 }
2570} 2541}
2571 2542
2572static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip) 2543static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2573{ 2544{
2574 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2545 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2575 if (setChip) { 2546 if (setChip) {
@@ -2585,8 +2556,7 @@ static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2585 } 2556 }
2586} 2557}
2587 2558
2588static bool ath9k_hw_set_power_awake(struct ath_hal *ah, 2559static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2589 int setChip)
2590{ 2560{
2591 u32 val; 2561 u32 val;
2592 int i; 2562 int i;
@@ -2627,17 +2597,15 @@ static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2627 return true; 2597 return true;
2628} 2598}
2629 2599
2630bool ath9k_hw_setpower(struct ath_hal *ah, 2600bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2631 enum ath9k_power_mode mode)
2632{ 2601{
2633 struct ath_hal_5416 *ahp = AH5416(ah); 2602 int status = true, setChip = true;
2634 static const char *modes[] = { 2603 static const char *modes[] = {
2635 "AWAKE", 2604 "AWAKE",
2636 "FULL-SLEEP", 2605 "FULL-SLEEP",
2637 "NETWORK SLEEP", 2606 "NETWORK SLEEP",
2638 "UNDEFINED" 2607 "UNDEFINED"
2639 }; 2608 };
2640 int status = true, setChip = true;
2641 2609
2642 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n", 2610 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2643 modes[ah->ah_power_mode], modes[mode], 2611 modes[ah->ah_power_mode], modes[mode],
@@ -2649,7 +2617,7 @@ bool ath9k_hw_setpower(struct ath_hal *ah,
2649 break; 2617 break;
2650 case ATH9K_PM_FULL_SLEEP: 2618 case ATH9K_PM_FULL_SLEEP:
2651 ath9k_set_power_sleep(ah, setChip); 2619 ath9k_set_power_sleep(ah, setChip);
2652 ahp->ah_chipFullSleep = true; 2620 ah->ah_chipFullSleep = true;
2653 break; 2621 break;
2654 case ATH9K_PM_NETWORK_SLEEP: 2622 case ATH9K_PM_NETWORK_SLEEP:
2655 ath9k_set_power_network_sleep(ah, setChip); 2623 ath9k_set_power_network_sleep(ah, setChip);
@@ -2664,9 +2632,8 @@ bool ath9k_hw_setpower(struct ath_hal *ah,
2664 return status; 2632 return status;
2665} 2633}
2666 2634
2667void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) 2635void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2668{ 2636{
2669 struct ath_hal_5416 *ahp = AH5416(ah);
2670 u8 i; 2637 u8 i;
2671 2638
2672 if (ah->ah_isPciExpress != true) 2639 if (ah->ah_isPciExpress != true)
@@ -2679,9 +2646,9 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2679 return; 2646 return;
2680 2647
2681 if (AR_SREV_9280_20_OR_LATER(ah)) { 2648 if (AR_SREV_9280_20_OR_LATER(ah)) {
2682 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) { 2649 for (i = 0; i < ah->ah_iniPcieSerdes.ia_rows; i++) {
2683 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0), 2650 REG_WRITE(ah, INI_RA(&ah->ah_iniPcieSerdes, i, 0),
2684 INI_RA(&ahp->ah_iniPcieSerdes, i, 1)); 2651 INI_RA(&ah->ah_iniPcieSerdes, i, 1));
2685 } 2652 }
2686 udelay(1000); 2653 udelay(1000);
2687 } else if (AR_SREV_9280(ah) && 2654 } else if (AR_SREV_9280(ah) &&
@@ -2730,14 +2697,13 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2730 else 2697 else
2731 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 2698 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2732 } 2699 }
2733
2734} 2700}
2735 2701
2736/**********************/ 2702/**********************/
2737/* Interrupt Handling */ 2703/* Interrupt Handling */
2738/**********************/ 2704/**********************/
2739 2705
2740bool ath9k_hw_intrpend(struct ath_hal *ah) 2706bool ath9k_hw_intrpend(struct ath_hw *ah)
2741{ 2707{
2742 u32 host_isr; 2708 u32 host_isr;
2743 2709
@@ -2756,14 +2722,13 @@ bool ath9k_hw_intrpend(struct ath_hal *ah)
2756 return false; 2722 return false;
2757} 2723}
2758 2724
2759bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) 2725bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2760{ 2726{
2761 u32 isr = 0; 2727 u32 isr = 0;
2762 u32 mask2 = 0; 2728 u32 mask2 = 0;
2763 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2729 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2764 u32 sync_cause = 0; 2730 u32 sync_cause = 0;
2765 bool fatal_int = false; 2731 bool fatal_int = false;
2766 struct ath_hal_5416 *ahp = AH5416(ah);
2767 2732
2768 if (!AR_SREV_9100(ah)) { 2733 if (!AR_SREV_9100(ah)) {
2769 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 2734 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
@@ -2811,7 +2776,7 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2811 2776
2812 *masked = isr & ATH9K_INT_COMMON; 2777 *masked = isr & ATH9K_INT_COMMON;
2813 2778
2814 if (ahp->ah_intrMitigation) { 2779 if (ah->ah_intrMitigation) {
2815 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 2780 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2816 *masked |= ATH9K_INT_RX; 2781 *masked |= ATH9K_INT_RX;
2817 } 2782 }
@@ -2826,12 +2791,12 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2826 *masked |= ATH9K_INT_TX; 2791 *masked |= ATH9K_INT_TX;
2827 2792
2828 s0_s = REG_READ(ah, AR_ISR_S0_S); 2793 s0_s = REG_READ(ah, AR_ISR_S0_S);
2829 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); 2794 ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2830 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); 2795 ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2831 2796
2832 s1_s = REG_READ(ah, AR_ISR_S1_S); 2797 s1_s = REG_READ(ah, AR_ISR_S1_S);
2833 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); 2798 ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2834 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); 2799 ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2835 } 2800 }
2836 2801
2837 if (isr & AR_ISR_RXORN) { 2802 if (isr & AR_ISR_RXORN) {
@@ -2888,15 +2853,14 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2888 return true; 2853 return true;
2889} 2854}
2890 2855
2891enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah) 2856enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
2892{ 2857{
2893 return AH5416(ah)->ah_maskReg; 2858 return ah->ah_maskReg;
2894} 2859}
2895 2860
2896enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) 2861enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2897{ 2862{
2898 struct ath_hal_5416 *ahp = AH5416(ah); 2863 u32 omask = ah->ah_maskReg;
2899 u32 omask = ahp->ah_maskReg;
2900 u32 mask, mask2; 2864 u32 mask, mask2;
2901 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2865 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2902 2866
@@ -2919,18 +2883,18 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2919 mask2 = 0; 2883 mask2 = 0;
2920 2884
2921 if (ints & ATH9K_INT_TX) { 2885 if (ints & ATH9K_INT_TX) {
2922 if (ahp->ah_txOkInterruptMask) 2886 if (ah->ah_txOkInterruptMask)
2923 mask |= AR_IMR_TXOK; 2887 mask |= AR_IMR_TXOK;
2924 if (ahp->ah_txDescInterruptMask) 2888 if (ah->ah_txDescInterruptMask)
2925 mask |= AR_IMR_TXDESC; 2889 mask |= AR_IMR_TXDESC;
2926 if (ahp->ah_txErrInterruptMask) 2890 if (ah->ah_txErrInterruptMask)
2927 mask |= AR_IMR_TXERR; 2891 mask |= AR_IMR_TXERR;
2928 if (ahp->ah_txEolInterruptMask) 2892 if (ah->ah_txEolInterruptMask)
2929 mask |= AR_IMR_TXEOL; 2893 mask |= AR_IMR_TXEOL;
2930 } 2894 }
2931 if (ints & ATH9K_INT_RX) { 2895 if (ints & ATH9K_INT_RX) {
2932 mask |= AR_IMR_RXERR; 2896 mask |= AR_IMR_RXERR;
2933 if (ahp->ah_intrMitigation) 2897 if (ah->ah_intrMitigation)
2934 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; 2898 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2935 else 2899 else
2936 mask |= AR_IMR_RXOK | AR_IMR_RXDESC; 2900 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
@@ -2968,7 +2932,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2968 AR_IMR_S2_TSFOOR | 2932 AR_IMR_S2_TSFOOR |
2969 AR_IMR_S2_GTT | AR_IMR_S2_CST); 2933 AR_IMR_S2_GTT | AR_IMR_S2_CST);
2970 REG_WRITE(ah, AR_IMR_S2, mask | mask2); 2934 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2971 ahp->ah_maskReg = ints; 2935 ah->ah_maskReg = ints;
2972 2936
2973 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2937 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2974 if (ints & ATH9K_INT_TIM_TIMER) 2938 if (ints & ATH9K_INT_TIM_TIMER)
@@ -3002,12 +2966,11 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
3002/* Beacon Handling */ 2966/* Beacon Handling */
3003/*******************/ 2967/*******************/
3004 2968
3005void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period) 2969void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3006{ 2970{
3007 struct ath_hal_5416 *ahp = AH5416(ah);
3008 int flags = 0; 2971 int flags = 0;
3009 2972
3010 ahp->ah_beaconInterval = beacon_period; 2973 ah->ah_beaconInterval = beacon_period;
3011 2974
3012 switch (ah->ah_opmode) { 2975 switch (ah->ah_opmode) {
3013 case NL80211_IFTYPE_STATION: 2976 case NL80211_IFTYPE_STATION:
@@ -3022,7 +2985,7 @@ void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3022 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2985 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3023 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 2986 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3024 TU_TO_USEC(next_beacon + 2987 TU_TO_USEC(next_beacon +
3025 (ahp->ah_atimWindow ? ahp-> 2988 (ah->ah_atimWindow ? ah->
3026 ah_atimWindow : 1))); 2989 ah_atimWindow : 1)));
3027 flags |= AR_NDP_TIMER_EN; 2990 flags |= AR_NDP_TIMER_EN;
3028 case NL80211_IFTYPE_AP: 2991 case NL80211_IFTYPE_AP:
@@ -3060,7 +3023,7 @@ void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3060 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 3023 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3061} 3024}
3062 3025
3063void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, 3026void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3064 const struct ath9k_beacon_state *bs) 3027 const struct ath9k_beacon_state *bs)
3065{ 3028{
3066 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 3029 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
@@ -3124,9 +3087,8 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3124/* HW Capabilities */ 3087/* HW Capabilities */
3125/*******************/ 3088/*******************/
3126 3089
3127bool ath9k_hw_fill_cap_info(struct ath_hal *ah) 3090bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3128{ 3091{
3129 struct ath_hal_5416 *ahp = AH5416(ah);
3130 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3092 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3131 u16 capField = 0, eeval; 3093 u16 capField = 0, eeval;
3132 3094
@@ -3195,7 +3157,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3195 } 3157 }
3196 3158
3197 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) 3159 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3198 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA; 3160 ah->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3199 3161
3200 pCap->low_2ghz_chan = 2312; 3162 pCap->low_2ghz_chan = 2312;
3201 pCap->high_2ghz_chan = 2732; 3163 pCap->high_2ghz_chan = 2732;
@@ -3317,10 +3279,9 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3317 return true; 3279 return true;
3318} 3280}
3319 3281
3320bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, 3282bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3321 u32 capability, u32 *result) 3283 u32 capability, u32 *result)
3322{ 3284{
3323 struct ath_hal_5416 *ahp = AH5416(ah);
3324 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3285 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3325 3286
3326 switch (type) { 3287 switch (type) {
@@ -3341,17 +3302,17 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3341 case 0: 3302 case 0:
3342 return true; 3303 return true;
3343 case 1: 3304 case 1:
3344 return (ahp->ah_staId1Defaults & 3305 return (ah->ah_staId1Defaults &
3345 AR_STA_ID1_CRPT_MIC_ENABLE) ? true : 3306 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3346 false; 3307 false;
3347 } 3308 }
3348 case ATH9K_CAP_TKIP_SPLIT: 3309 case ATH9K_CAP_TKIP_SPLIT:
3349 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ? 3310 return (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3350 false : true; 3311 false : true;
3351 case ATH9K_CAP_WME_TKIPMIC: 3312 case ATH9K_CAP_WME_TKIPMIC:
3352 return 0; 3313 return 0;
3353 case ATH9K_CAP_PHYCOUNTERS: 3314 case ATH9K_CAP_PHYCOUNTERS:
3354 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO; 3315 return ah->ah_hasHwPhyCounters ? 0 : -ENXIO;
3355 case ATH9K_CAP_DIVERSITY: 3316 case ATH9K_CAP_DIVERSITY:
3356 return (REG_READ(ah, AR_PHY_CCK_DETECT) & 3317 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3357 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 3318 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
@@ -3366,14 +3327,14 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3366 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 3327 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3367 return false; 3328 return false;
3368 } else { 3329 } else {
3369 return (ahp->ah_staId1Defaults & 3330 return (ah->ah_staId1Defaults &
3370 AR_STA_ID1_MCAST_KSRCH) ? true : 3331 AR_STA_ID1_MCAST_KSRCH) ? true :
3371 false; 3332 false;
3372 } 3333 }
3373 } 3334 }
3374 return false; 3335 return false;
3375 case ATH9K_CAP_TSF_ADJUST: 3336 case ATH9K_CAP_TSF_ADJUST:
3376 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ? 3337 return (ah->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3377 true : false; 3338 true : false;
3378 case ATH9K_CAP_RFSILENT: 3339 case ATH9K_CAP_RFSILENT:
3379 if (capability == 3) 3340 if (capability == 3)
@@ -3404,19 +3365,18 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3404 } 3365 }
3405} 3366}
3406 3367
3407bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, 3368bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3408 u32 capability, u32 setting, int *status) 3369 u32 capability, u32 setting, int *status)
3409{ 3370{
3410 struct ath_hal_5416 *ahp = AH5416(ah);
3411 u32 v; 3371 u32 v;
3412 3372
3413 switch (type) { 3373 switch (type) {
3414 case ATH9K_CAP_TKIP_MIC: 3374 case ATH9K_CAP_TKIP_MIC:
3415 if (setting) 3375 if (setting)
3416 ahp->ah_staId1Defaults |= 3376 ah->ah_staId1Defaults |=
3417 AR_STA_ID1_CRPT_MIC_ENABLE; 3377 AR_STA_ID1_CRPT_MIC_ENABLE;
3418 else 3378 else
3419 ahp->ah_staId1Defaults &= 3379 ah->ah_staId1Defaults &=
3420 ~AR_STA_ID1_CRPT_MIC_ENABLE; 3380 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3421 return true; 3381 return true;
3422 case ATH9K_CAP_DIVERSITY: 3382 case ATH9K_CAP_DIVERSITY:
@@ -3429,15 +3389,15 @@ bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3429 return true; 3389 return true;
3430 case ATH9K_CAP_MCAST_KEYSRCH: 3390 case ATH9K_CAP_MCAST_KEYSRCH:
3431 if (setting) 3391 if (setting)
3432 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH; 3392 ah->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3433 else 3393 else
3434 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH; 3394 ah->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3435 return true; 3395 return true;
3436 case ATH9K_CAP_TSF_ADJUST: 3396 case ATH9K_CAP_TSF_ADJUST:
3437 if (setting) 3397 if (setting)
3438 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; 3398 ah->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3439 else 3399 else
3440 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; 3400 ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3441 return true; 3401 return true;
3442 default: 3402 default:
3443 return false; 3403 return false;
@@ -3448,7 +3408,7 @@ bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3448/* GPIO / RFKILL / Antennae */ 3408/* GPIO / RFKILL / Antennae */
3449/****************************/ 3409/****************************/
3450 3410
3451static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah, 3411static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3452 u32 gpio, u32 type) 3412 u32 gpio, u32 type)
3453{ 3413{
3454 int addr; 3414 int addr;
@@ -3476,7 +3436,7 @@ static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3476 } 3436 }
3477} 3437}
3478 3438
3479void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio) 3439void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3480{ 3440{
3481 u32 gpio_shift; 3441 u32 gpio_shift;
3482 3442
@@ -3490,7 +3450,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3490 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3450 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3491} 3451}
3492 3452
3493u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio) 3453u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3494{ 3454{
3495#define MS_REG_READ(x, y) \ 3455#define MS_REG_READ(x, y) \
3496 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 3456 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
@@ -3506,7 +3466,7 @@ u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3506 return MS_REG_READ(AR, gpio) != 0; 3466 return MS_REG_READ(AR, gpio) != 0;
3507} 3467}
3508 3468
3509void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, 3469void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3510 u32 ah_signal_type) 3470 u32 ah_signal_type)
3511{ 3471{
3512 u32 gpio_shift; 3472 u32 gpio_shift;
@@ -3521,14 +3481,14 @@ void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3521 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3481 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3522} 3482}
3523 3483
3524void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val) 3484void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3525{ 3485{
3526 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 3486 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3527 AR_GPIO_BIT(gpio)); 3487 AR_GPIO_BIT(gpio));
3528} 3488}
3529 3489
3530#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 3490#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3531void ath9k_enable_rfkill(struct ath_hal *ah) 3491void ath9k_enable_rfkill(struct ath_hw *ah)
3532{ 3492{
3533 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 3493 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3534 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 3494 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
@@ -3541,24 +3501,23 @@ void ath9k_enable_rfkill(struct ath_hal *ah)
3541} 3501}
3542#endif 3502#endif
3543 3503
3544u32 ath9k_hw_getdefantenna(struct ath_hal *ah) 3504u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3545{ 3505{
3546 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 3506 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3547} 3507}
3548 3508
3549void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna) 3509void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3550{ 3510{
3551 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 3511 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3552} 3512}
3553 3513
3554bool ath9k_hw_setantennaswitch(struct ath_hal *ah, 3514bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3555 enum ath9k_ant_setting settings, 3515 enum ath9k_ant_setting settings,
3556 struct ath9k_channel *chan, 3516 struct ath9k_channel *chan,
3557 u8 *tx_chainmask, 3517 u8 *tx_chainmask,
3558 u8 *rx_chainmask, 3518 u8 *rx_chainmask,
3559 u8 *antenna_cfgd) 3519 u8 *antenna_cfgd)
3560{ 3520{
3561 struct ath_hal_5416 *ahp = AH5416(ah);
3562 static u8 tx_chainmask_cfg, rx_chainmask_cfg; 3521 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3563 3522
3564 if (AR_SREV_9280(ah)) { 3523 if (AR_SREV_9280(ah)) {
@@ -3591,7 +3550,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3591 break; 3550 break;
3592 } 3551 }
3593 } else { 3552 } else {
3594 ahp->ah_diversityControl = settings; 3553 ah->ah_diversityControl = settings;
3595 } 3554 }
3596 3555
3597 return true; 3556 return true;
@@ -3601,7 +3560,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3601/* General Operation */ 3560/* General Operation */
3602/*********************/ 3561/*********************/
3603 3562
3604u32 ath9k_hw_getrxfilter(struct ath_hal *ah) 3563u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3605{ 3564{
3606 u32 bits = REG_READ(ah, AR_RX_FILTER); 3565 u32 bits = REG_READ(ah, AR_RX_FILTER);
3607 u32 phybits = REG_READ(ah, AR_PHY_ERR); 3566 u32 phybits = REG_READ(ah, AR_PHY_ERR);
@@ -3614,7 +3573,7 @@ u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3614 return bits; 3573 return bits;
3615} 3574}
3616 3575
3617void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits) 3576void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3618{ 3577{
3619 u32 phybits; 3578 u32 phybits;
3620 3579
@@ -3634,12 +3593,12 @@ void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3634 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 3593 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3635} 3594}
3636 3595
3637bool ath9k_hw_phy_disable(struct ath_hal *ah) 3596bool ath9k_hw_phy_disable(struct ath_hw *ah)
3638{ 3597{
3639 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM); 3598 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3640} 3599}
3641 3600
3642bool ath9k_hw_disable(struct ath_hal *ah) 3601bool ath9k_hw_disable(struct ath_hw *ah)
3643{ 3602{
3644 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 3603 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3645 return false; 3604 return false;
@@ -3647,7 +3606,7 @@ bool ath9k_hw_disable(struct ath_hal *ah)
3647 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD); 3606 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3648} 3607}
3649 3608
3650bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit) 3609bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3651{ 3610{
3652 struct ath9k_channel *chan = ah->ah_curchan; 3611 struct ath9k_channel *chan = ah->ah_curchan;
3653 struct ieee80211_channel *channel = chan->chan; 3612 struct ieee80211_channel *channel = chan->chan;
@@ -3665,17 +3624,17 @@ bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3665 return true; 3624 return true;
3666} 3625}
3667 3626
3668void ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac) 3627void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3669{ 3628{
3670 memcpy(ah->macaddr, mac, ETH_ALEN); 3629 memcpy(ah->macaddr, mac, ETH_ALEN);
3671} 3630}
3672 3631
3673void ath9k_hw_setopmode(struct ath_hal *ah) 3632void ath9k_hw_setopmode(struct ath_hw *ah)
3674{ 3633{
3675 ath9k_hw_set_operating_mode(ah, ah->ah_opmode); 3634 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3676} 3635}
3677 3636
3678void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1) 3637void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3679{ 3638{
3680 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 3639 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3681 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 3640 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
@@ -3694,7 +3653,7 @@ void ath9k_hw_write_associd(struct ath_softc *sc)
3694 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 3653 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3695} 3654}
3696 3655
3697u64 ath9k_hw_gettsf64(struct ath_hal *ah) 3656u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3698{ 3657{
3699 u64 tsf; 3658 u64 tsf;
3700 3659
@@ -3704,14 +3663,14 @@ u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3704 return tsf; 3663 return tsf;
3705} 3664}
3706 3665
3707void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64) 3666void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3708{ 3667{
3709 REG_WRITE(ah, AR_TSF_L32, 0x00000000); 3668 REG_WRITE(ah, AR_TSF_L32, 0x00000000);
3710 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 3669 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3711 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 3670 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3712} 3671}
3713 3672
3714void ath9k_hw_reset_tsf(struct ath_hal *ah) 3673void ath9k_hw_reset_tsf(struct ath_hw *ah)
3715{ 3674{
3716 int count; 3675 int count;
3717 3676
@@ -3728,34 +3687,30 @@ void ath9k_hw_reset_tsf(struct ath_hal *ah)
3728 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 3687 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3729} 3688}
3730 3689
3731bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting) 3690bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3732{ 3691{
3733 struct ath_hal_5416 *ahp = AH5416(ah);
3734
3735 if (setting) 3692 if (setting)
3736 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; 3693 ah->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3737 else 3694 else
3738 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; 3695 ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3739 3696
3740 return true; 3697 return true;
3741} 3698}
3742 3699
3743bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us) 3700bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3744{ 3701{
3745 struct ath_hal_5416 *ahp = AH5416(ah);
3746
3747 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { 3702 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3748 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us); 3703 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3749 ahp->ah_slottime = (u32) -1; 3704 ah->ah_slottime = (u32) -1;
3750 return false; 3705 return false;
3751 } else { 3706 } else {
3752 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); 3707 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3753 ahp->ah_slottime = us; 3708 ah->ah_slottime = us;
3754 return true; 3709 return true;
3755 } 3710 }
3756} 3711}
3757 3712
3758void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode) 3713void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3759{ 3714{
3760 u32 macmode; 3715 u32 macmode;
3761 3716
@@ -3772,7 +3727,7 @@ void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3772/* Bluetooth Coexistence */ 3727/* Bluetooth Coexistence */
3773/***************************/ 3728/***************************/
3774 3729
3775void ath9k_hw_btcoex_enable(struct ath_hal *ah) 3730void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3776{ 3731{
3777 /* connect bt_active to baseband */ 3732 /* connect bt_active to baseband */
3778 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL, 3733 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h
index f4bf70215744..84914e205892 100644
--- a/drivers/net/wireless/ath9k/hw.h
+++ b/drivers/net/wireless/ath9k/hw.h
@@ -42,8 +42,8 @@
42#define AR5416_MAGIC 0x19641014 42#define AR5416_MAGIC 0x19641014
43 43
44/* Register read/write primitives */ 44/* Register read/write primitives */
45#define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg) 45#define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sc->mem + _reg)
46#define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg) 46#define REG_READ(_ah, _reg) ioread32(_ah->ah_sc->mem + _reg)
47 47
48#define SM(_v, _f) (((_v) << _f##_S) & _f) 48#define SM(_v, _f) (((_v) << _f##_S) & _f)
49#define MS(_v, _f) (((_v) & _f) >> _f##_S) 49#define MS(_v, _f) (((_v) & _f) >> _f##_S)
@@ -417,46 +417,38 @@ struct ath9k_hw_version {
417 u16 analog2GhzRev; 417 u16 analog2GhzRev;
418}; 418};
419 419
420struct ath_hal { 420struct ath_hw {
421 struct ath9k_hw_version hw_version;
422 void __iomem *ah_sh;
423 struct ath_softc *ah_sc; 421 struct ath_softc *ah_sc;
424 422 struct ath9k_hw_version hw_version;
425 enum nl80211_iftype ah_opmode;
426 struct ath9k_ops_config ah_config; 423 struct ath9k_ops_config ah_config;
427 struct ath9k_hw_capabilities ah_caps; 424 struct ath9k_hw_capabilities ah_caps;
428 struct ath9k_regulatory regulatory; 425 struct ath9k_regulatory regulatory;
429 u32 ah_flags;
430 u8 macaddr[ETH_ALEN];
431
432 enum ath9k_power_mode ah_power_mode;
433 enum ath9k_power_mode ah_restore_mode;
434
435 struct ath9k_channel ah_channels[38]; 426 struct ath9k_channel ah_channels[38];
436 struct ath9k_channel *ah_curchan; 427 struct ath9k_channel *ah_curchan;
437 428
429 union {
430 struct ar5416_eeprom_def def;
431 struct ar5416_eeprom_4k map4k;
432 } ah_eeprom;
433
434 bool sw_mgmt_crypto;
438 bool ah_isPciExpress; 435 bool ah_isPciExpress;
436 u8 macaddr[ETH_ALEN];
439 u16 ah_txTrigLevel; 437 u16 ah_txTrigLevel;
440 u16 ah_rfsilent; 438 u16 ah_rfsilent;
441 u32 ah_rfkill_gpio; 439 u32 ah_rfkill_gpio;
442 u32 ah_rfkill_polarity; 440 u32 ah_rfkill_polarity;
443 u32 ah_btactive_gpio; 441 u32 ah_btactive_gpio;
444 u32 ah_wlanactive_gpio; 442 u32 ah_wlanactive_gpio;
443 u32 ah_flags;
444 enum nl80211_iftype ah_opmode;
445 445
446 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 446 enum ath9k_power_mode ah_power_mode;
447 447 enum ath9k_power_mode ah_restore_mode;
448 bool sw_mgmt_crypto;
449};
450 448
451struct ath_hal_5416 { 449 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
452 struct ath_hal ah;
453 union {
454 struct ar5416_eeprom_def def;
455 struct ar5416_eeprom_4k map4k;
456 } ah_eeprom;
457 struct ar5416Stats ah_stats; 450 struct ar5416Stats ah_stats;
458 struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES]; 451 struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES];
459 void __iomem *ah_cal_mem;
460 452
461 int16_t ah_curchanRadIndex; 453 int16_t ah_curchanRadIndex;
462 u32 ah_maskReg; 454 u32 ah_maskReg;
@@ -574,85 +566,83 @@ struct ath_hal_5416 {
574 /* To indicate EEPROM mapping used */ 566 /* To indicate EEPROM mapping used */
575 enum hal_eep_map ah_eep_map; 567 enum hal_eep_map ah_eep_map;
576}; 568};
577#define AH5416(_ah) ((struct ath_hal_5416 *)(_ah))
578 569
579/* Attach, Detach, Reset */ 570/* Attach, Detach, Reset */
580const char *ath9k_hw_probe(u16 vendorid, u16 devid); 571const char *ath9k_hw_probe(u16 vendorid, u16 devid);
581void ath9k_hw_detach(struct ath_hal *ah); 572void ath9k_hw_detach(struct ath_hw *ah);
582struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, 573struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error);
583 void __iomem *mem, int *error); 574void ath9k_hw_rfdetach(struct ath_hw *ah);
584void ath9k_hw_rfdetach(struct ath_hal *ah); 575int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
585int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
586 bool bChannelChange); 576 bool bChannelChange);
587bool ath9k_hw_fill_cap_info(struct ath_hal *ah); 577bool ath9k_hw_fill_cap_info(struct ath_hw *ah);
588bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, 578bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
589 u32 capability, u32 *result); 579 u32 capability, u32 *result);
590bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, 580bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
591 u32 capability, u32 setting, int *status); 581 u32 capability, u32 setting, int *status);
592 582
593/* Key Cache Management */ 583/* Key Cache Management */
594bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry); 584bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
595bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac); 585bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
596bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, 586bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
597 const struct ath9k_keyval *k, 587 const struct ath9k_keyval *k,
598 const u8 *mac, int xorKey); 588 const u8 *mac, int xorKey);
599bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry); 589bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
600 590
601/* GPIO / RFKILL / Antennae */ 591/* GPIO / RFKILL / Antennae */
602void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio); 592void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
603u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio); 593u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
604void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, 594void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
605 u32 ah_signal_type); 595 u32 ah_signal_type);
606void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val); 596void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
607#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 597#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
608void ath9k_enable_rfkill(struct ath_hal *ah); 598void ath9k_enable_rfkill(struct ath_hw *ah);
609#endif 599#endif
610u32 ath9k_hw_getdefantenna(struct ath_hal *ah); 600u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
611void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna); 601void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
612bool ath9k_hw_setantennaswitch(struct ath_hal *ah, 602bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
613 enum ath9k_ant_setting settings, 603 enum ath9k_ant_setting settings,
614 struct ath9k_channel *chan, 604 struct ath9k_channel *chan,
615 u8 *tx_chainmask, u8 *rx_chainmask, 605 u8 *tx_chainmask, u8 *rx_chainmask,
616 u8 *antenna_cfgd); 606 u8 *antenna_cfgd);
617 607
618/* General Operation */ 608/* General Operation */
619bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val); 609bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val);
620u32 ath9k_hw_reverse_bits(u32 val, u32 n); 610u32 ath9k_hw_reverse_bits(u32 val, u32 n);
621bool ath9k_get_channel_edges(struct ath_hal *ah, u16 flags, u16 *low, u16 *high); 611bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
622u16 ath9k_hw_computetxtime(struct ath_hal *ah, struct ath_rate_table *rates, 612u16 ath9k_hw_computetxtime(struct ath_hw *ah, struct ath_rate_table *rates,
623 u32 frameLen, u16 rateix, bool shortPreamble); 613 u32 frameLen, u16 rateix, bool shortPreamble);
624void ath9k_hw_get_channel_centers(struct ath_hal *ah, 614void ath9k_hw_get_channel_centers(struct ath_hw *ah,
625 struct ath9k_channel *chan, 615 struct ath9k_channel *chan,
626 struct chan_centers *centers); 616 struct chan_centers *centers);
627u32 ath9k_hw_getrxfilter(struct ath_hal *ah); 617u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
628void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits); 618void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
629bool ath9k_hw_phy_disable(struct ath_hal *ah); 619bool ath9k_hw_phy_disable(struct ath_hw *ah);
630bool ath9k_hw_disable(struct ath_hal *ah); 620bool ath9k_hw_disable(struct ath_hw *ah);
631bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit); 621bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
632void ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac); 622void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
633void ath9k_hw_setopmode(struct ath_hal *ah); 623void ath9k_hw_setopmode(struct ath_hw *ah);
634void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1); 624void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
635void ath9k_hw_setbssidmask(struct ath_softc *sc); 625void ath9k_hw_setbssidmask(struct ath_softc *sc);
636void ath9k_hw_write_associd(struct ath_softc *sc); 626void ath9k_hw_write_associd(struct ath_softc *sc);
637u64 ath9k_hw_gettsf64(struct ath_hal *ah); 627u64 ath9k_hw_gettsf64(struct ath_hw *ah);
638void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64); 628void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
639void ath9k_hw_reset_tsf(struct ath_hal *ah); 629void ath9k_hw_reset_tsf(struct ath_hw *ah);
640bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting); 630bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
641bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us); 631bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
642void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode); 632void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode);
643void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period); 633void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
644void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, 634void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
645 const struct ath9k_beacon_state *bs); 635 const struct ath9k_beacon_state *bs);
646bool ath9k_hw_setpower(struct ath_hal *ah, 636bool ath9k_hw_setpower(struct ath_hw *ah,
647 enum ath9k_power_mode mode); 637 enum ath9k_power_mode mode);
648void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore); 638void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore);
649 639
650/* Interrupt Handling */ 640/* Interrupt Handling */
651bool ath9k_hw_intrpend(struct ath_hal *ah); 641bool ath9k_hw_intrpend(struct ath_hw *ah);
652bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked); 642bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
653enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah); 643enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah);
654enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints); 644enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
655 645
656void ath9k_hw_btcoex_enable(struct ath_hal *ah); 646void ath9k_hw_btcoex_enable(struct ath_hw *ah);
657 647
658#endif 648#endif
diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c
index b375a2964d2a..ac2071444017 100644
--- a/drivers/net/wireless/ath9k/mac.c
+++ b/drivers/net/wireless/ath9k/mac.c
@@ -16,40 +16,38 @@
16 16
17#include "ath9k.h" 17#include "ath9k.h"
18 18
19static void ath9k_hw_set_txq_interrupts(struct ath_hal *ah, 19static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
20 struct ath9k_tx_queue_info *qi) 20 struct ath9k_tx_queue_info *qi)
21{ 21{
22 struct ath_hal_5416 *ahp = AH5416(ah);
23
24 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 22 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
25 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", 23 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
26 ahp->ah_txOkInterruptMask, ahp->ah_txErrInterruptMask, 24 ah->ah_txOkInterruptMask, ah->ah_txErrInterruptMask,
27 ahp->ah_txDescInterruptMask, ahp->ah_txEolInterruptMask, 25 ah->ah_txDescInterruptMask, ah->ah_txEolInterruptMask,
28 ahp->ah_txUrnInterruptMask); 26 ah->ah_txUrnInterruptMask);
29 27
30 REG_WRITE(ah, AR_IMR_S0, 28 REG_WRITE(ah, AR_IMR_S0,
31 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) 29 SM(ah->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
32 | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)); 30 | SM(ah->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC));
33 REG_WRITE(ah, AR_IMR_S1, 31 REG_WRITE(ah, AR_IMR_S1,
34 SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR) 32 SM(ah->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
35 | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)); 33 | SM(ah->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL));
36 REG_RMW_FIELD(ah, AR_IMR_S2, 34 REG_RMW_FIELD(ah, AR_IMR_S2,
37 AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask); 35 AR_IMR_S2_QCU_TXURN, ah->ah_txUrnInterruptMask);
38} 36}
39 37
40u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q) 38u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
41{ 39{
42 return REG_READ(ah, AR_QTXDP(q)); 40 return REG_READ(ah, AR_QTXDP(q));
43} 41}
44 42
45bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp) 43bool ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
46{ 44{
47 REG_WRITE(ah, AR_QTXDP(q), txdp); 45 REG_WRITE(ah, AR_QTXDP(q), txdp);
48 46
49 return true; 47 return true;
50} 48}
51 49
52bool ath9k_hw_txstart(struct ath_hal *ah, u32 q) 50bool ath9k_hw_txstart(struct ath_hw *ah, u32 q)
53{ 51{
54 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); 52 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q);
55 53
@@ -58,7 +56,7 @@ bool ath9k_hw_txstart(struct ath_hal *ah, u32 q)
58 return true; 56 return true;
59} 57}
60 58
61u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q) 59u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
62{ 60{
63 u32 npend; 61 u32 npend;
64 62
@@ -72,16 +70,15 @@ u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q)
72 return npend; 70 return npend;
73} 71}
74 72
75bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel) 73bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
76{ 74{
77 struct ath_hal_5416 *ahp = AH5416(ah);
78 u32 txcfg, curLevel, newLevel; 75 u32 txcfg, curLevel, newLevel;
79 enum ath9k_int omask; 76 enum ath9k_int omask;
80 77
81 if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD) 78 if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD)
82 return false; 79 return false;
83 80
84 omask = ath9k_hw_set_interrupts(ah, ahp->ah_maskReg & ~ATH9K_INT_GLOBAL); 81 omask = ath9k_hw_set_interrupts(ah, ah->ah_maskReg & ~ATH9K_INT_GLOBAL);
85 82
86 txcfg = REG_READ(ah, AR_TXCFG); 83 txcfg = REG_READ(ah, AR_TXCFG);
87 curLevel = MS(txcfg, AR_FTRIG); 84 curLevel = MS(txcfg, AR_FTRIG);
@@ -102,12 +99,11 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel)
102 return newLevel != curLevel; 99 return newLevel != curLevel;
103} 100}
104 101
105bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q) 102bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
106{ 103{
107#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */ 104#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
108#define ATH9K_TIME_QUANTUM 100 /* usec */ 105#define ATH9K_TIME_QUANTUM 100 /* usec */
109 106
110 struct ath_hal_5416 *ahp = AH5416(ah);
111 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 107 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
112 struct ath9k_tx_queue_info *qi; 108 struct ath9k_tx_queue_info *qi;
113 u32 tsfLow, j, wait; 109 u32 tsfLow, j, wait;
@@ -118,7 +114,7 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
118 return false; 114 return false;
119 } 115 }
120 116
121 qi = &ahp->ah_txq[q]; 117 qi = &ah->ah_txq[q];
122 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 118 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
123 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); 119 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
124 return false; 120 return false;
@@ -180,7 +176,7 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
180#undef ATH9K_TIME_QUANTUM 176#undef ATH9K_TIME_QUANTUM
181} 177}
182 178
183bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, 179bool ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
184 u32 segLen, bool firstSeg, 180 u32 segLen, bool firstSeg,
185 bool lastSeg, const struct ath_desc *ds0) 181 bool lastSeg, const struct ath_desc *ds0)
186{ 182{
@@ -208,7 +204,7 @@ bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
208 return true; 204 return true;
209} 205}
210 206
211void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds) 207void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
212{ 208{
213 struct ar5416_desc *ads = AR5416DESC(ds); 209 struct ar5416_desc *ads = AR5416DESC(ds);
214 210
@@ -219,7 +215,7 @@ void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds)
219 ads->ds_txstatus8 = ads->ds_txstatus9 = 0; 215 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
220} 216}
221 217
222int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds) 218int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds)
223{ 219{
224 struct ar5416_desc *ads = AR5416DESC(ds); 220 struct ar5416_desc *ads = AR5416DESC(ds);
225 221
@@ -294,14 +290,13 @@ int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
294 return 0; 290 return 0;
295} 291}
296 292
297void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, 293void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
298 u32 pktLen, enum ath9k_pkt_type type, u32 txPower, 294 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
299 u32 keyIx, enum ath9k_key_type keyType, u32 flags) 295 u32 keyIx, enum ath9k_key_type keyType, u32 flags)
300{ 296{
301 struct ar5416_desc *ads = AR5416DESC(ds); 297 struct ar5416_desc *ads = AR5416DESC(ds);
302 struct ath_hal_5416 *ahp = AH5416(ah);
303 298
304 txPower += ahp->ah_txPowerIndexOffset; 299 txPower += ah->ah_txPowerIndexOffset;
305 if (txPower > 63) 300 if (txPower > 63)
306 txPower = 63; 301 txPower = 63;
307 302
@@ -330,7 +325,7 @@ void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
330 } 325 }
331} 326}
332 327
333void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, 328void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
334 struct ath_desc *lastds, 329 struct ath_desc *lastds,
335 u32 durUpdateEn, u32 rtsctsRate, 330 u32 durUpdateEn, u32 rtsctsRate,
336 u32 rtsctsDuration, 331 u32 rtsctsDuration,
@@ -385,7 +380,7 @@ void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
385 last_ads->ds_ctl3 = ads->ds_ctl3; 380 last_ads->ds_ctl3 = ads->ds_ctl3;
386} 381}
387 382
388void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, 383void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
389 u32 aggrLen) 384 u32 aggrLen)
390{ 385{
391 struct ar5416_desc *ads = AR5416DESC(ds); 386 struct ar5416_desc *ads = AR5416DESC(ds);
@@ -395,7 +390,7 @@ void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
395 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen); 390 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
396} 391}
397 392
398void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, 393void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
399 u32 numDelims) 394 u32 numDelims)
400{ 395{
401 struct ar5416_desc *ads = AR5416DESC(ds); 396 struct ar5416_desc *ads = AR5416DESC(ds);
@@ -409,7 +404,7 @@ void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
409 ads->ds_ctl6 = ctl6; 404 ads->ds_ctl6 = ctl6;
410} 405}
411 406
412void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds) 407void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds)
413{ 408{
414 struct ar5416_desc *ads = AR5416DESC(ds); 409 struct ar5416_desc *ads = AR5416DESC(ds);
415 410
@@ -418,14 +413,14 @@ void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds)
418 ads->ds_ctl6 &= ~AR_PadDelim; 413 ads->ds_ctl6 &= ~AR_PadDelim;
419} 414}
420 415
421void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds) 416void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds)
422{ 417{
423 struct ar5416_desc *ads = AR5416DESC(ds); 418 struct ar5416_desc *ads = AR5416DESC(ds);
424 419
425 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); 420 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
426} 421}
427 422
428void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds, 423void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
429 u32 burstDuration) 424 u32 burstDuration)
430{ 425{
431 struct ar5416_desc *ads = AR5416DESC(ds); 426 struct ar5416_desc *ads = AR5416DESC(ds);
@@ -434,7 +429,7 @@ void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
434 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur); 429 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
435} 430}
436 431
437void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, 432void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
438 u32 vmf) 433 u32 vmf)
439{ 434{
440 struct ar5416_desc *ads = AR5416DESC(ds); 435 struct ar5416_desc *ads = AR5416DESC(ds);
@@ -445,19 +440,16 @@ void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
445 ads->ds_ctl0 &= ~AR_VirtMoreFrag; 440 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
446} 441}
447 442
448void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs) 443void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
449{ 444{
450 struct ath_hal_5416 *ahp = AH5416(ah); 445 *txqs &= ah->ah_intrTxqs;
451 446 ah->ah_intrTxqs &= ~(*txqs);
452 *txqs &= ahp->ah_intrTxqs;
453 ahp->ah_intrTxqs &= ~(*txqs);
454} 447}
455 448
456bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, 449bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
457 const struct ath9k_tx_queue_info *qinfo) 450 const struct ath9k_tx_queue_info *qinfo)
458{ 451{
459 u32 cw; 452 u32 cw;
460 struct ath_hal_5416 *ahp = AH5416(ah);
461 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 453 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
462 struct ath9k_tx_queue_info *qi; 454 struct ath9k_tx_queue_info *qi;
463 455
@@ -466,7 +458,7 @@ bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
466 return false; 458 return false;
467 } 459 }
468 460
469 qi = &ahp->ah_txq[q]; 461 qi = &ah->ah_txq[q];
470 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 462 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
471 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); 463 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
472 return false; 464 return false;
@@ -522,10 +514,9 @@ bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
522 return true; 514 return true;
523} 515}
524 516
525bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, 517bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
526 struct ath9k_tx_queue_info *qinfo) 518 struct ath9k_tx_queue_info *qinfo)
527{ 519{
528 struct ath_hal_5416 *ahp = AH5416(ah);
529 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 520 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
530 struct ath9k_tx_queue_info *qi; 521 struct ath9k_tx_queue_info *qi;
531 522
@@ -534,7 +525,7 @@ bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
534 return false; 525 return false;
535 } 526 }
536 527
537 qi = &ahp->ah_txq[q]; 528 qi = &ah->ah_txq[q];
538 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 529 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
539 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); 530 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
540 return false; 531 return false;
@@ -558,10 +549,9 @@ bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
558 return true; 549 return true;
559} 550}
560 551
561int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, 552int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
562 const struct ath9k_tx_queue_info *qinfo) 553 const struct ath9k_tx_queue_info *qinfo)
563{ 554{
564 struct ath_hal_5416 *ahp = AH5416(ah);
565 struct ath9k_tx_queue_info *qi; 555 struct ath9k_tx_queue_info *qi;
566 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 556 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
567 int q; 557 int q;
@@ -581,7 +571,7 @@ int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
581 break; 571 break;
582 case ATH9K_TX_QUEUE_DATA: 572 case ATH9K_TX_QUEUE_DATA:
583 for (q = 0; q < pCap->total_queues; q++) 573 for (q = 0; q < pCap->total_queues; q++)
584 if (ahp->ah_txq[q].tqi_type == 574 if (ah->ah_txq[q].tqi_type ==
585 ATH9K_TX_QUEUE_INACTIVE) 575 ATH9K_TX_QUEUE_INACTIVE)
586 break; 576 break;
587 if (q == pCap->total_queues) { 577 if (q == pCap->total_queues) {
@@ -597,7 +587,7 @@ int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
597 587
598 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); 588 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q);
599 589
600 qi = &ahp->ah_txq[q]; 590 qi = &ah->ah_txq[q];
601 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { 591 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
602 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 592 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
603 "tx queue %u already active\n", q); 593 "tx queue %u already active\n", q);
@@ -624,9 +614,8 @@ int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
624 return q; 614 return q;
625} 615}
626 616
627bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q) 617bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
628{ 618{
629 struct ath_hal_5416 *ahp = AH5416(ah);
630 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 619 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
631 struct ath9k_tx_queue_info *qi; 620 struct ath9k_tx_queue_info *qi;
632 621
@@ -634,7 +623,7 @@ bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q)
634 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); 623 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
635 return false; 624 return false;
636 } 625 }
637 qi = &ahp->ah_txq[q]; 626 qi = &ah->ah_txq[q];
638 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 627 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
639 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); 628 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q);
640 return false; 629 return false;
@@ -643,19 +632,18 @@ bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q)
643 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q); 632 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q);
644 633
645 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; 634 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
646 ahp->ah_txOkInterruptMask &= ~(1 << q); 635 ah->ah_txOkInterruptMask &= ~(1 << q);
647 ahp->ah_txErrInterruptMask &= ~(1 << q); 636 ah->ah_txErrInterruptMask &= ~(1 << q);
648 ahp->ah_txDescInterruptMask &= ~(1 << q); 637 ah->ah_txDescInterruptMask &= ~(1 << q);
649 ahp->ah_txEolInterruptMask &= ~(1 << q); 638 ah->ah_txEolInterruptMask &= ~(1 << q);
650 ahp->ah_txUrnInterruptMask &= ~(1 << q); 639 ah->ah_txUrnInterruptMask &= ~(1 << q);
651 ath9k_hw_set_txq_interrupts(ah, qi); 640 ath9k_hw_set_txq_interrupts(ah, qi);
652 641
653 return true; 642 return true;
654} 643}
655 644
656bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q) 645bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
657{ 646{
658 struct ath_hal_5416 *ahp = AH5416(ah);
659 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 647 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
660 struct ath9k_channel *chan = ah->ah_curchan; 648 struct ath9k_channel *chan = ah->ah_curchan;
661 struct ath9k_tx_queue_info *qi; 649 struct ath9k_tx_queue_info *qi;
@@ -666,7 +654,7 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q)
666 return false; 654 return false;
667 } 655 }
668 656
669 qi = &ahp->ah_txq[q]; 657 qi = &ah->ah_txq[q];
670 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 658 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
671 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); 659 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q);
672 return true; 660 return true;
@@ -784,31 +772,31 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q)
784 } 772 }
785 773
786 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE) 774 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
787 ahp->ah_txOkInterruptMask |= 1 << q; 775 ah->ah_txOkInterruptMask |= 1 << q;
788 else 776 else
789 ahp->ah_txOkInterruptMask &= ~(1 << q); 777 ah->ah_txOkInterruptMask &= ~(1 << q);
790 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE) 778 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
791 ahp->ah_txErrInterruptMask |= 1 << q; 779 ah->ah_txErrInterruptMask |= 1 << q;
792 else 780 else
793 ahp->ah_txErrInterruptMask &= ~(1 << q); 781 ah->ah_txErrInterruptMask &= ~(1 << q);
794 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE) 782 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
795 ahp->ah_txDescInterruptMask |= 1 << q; 783 ah->ah_txDescInterruptMask |= 1 << q;
796 else 784 else
797 ahp->ah_txDescInterruptMask &= ~(1 << q); 785 ah->ah_txDescInterruptMask &= ~(1 << q);
798 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) 786 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
799 ahp->ah_txEolInterruptMask |= 1 << q; 787 ah->ah_txEolInterruptMask |= 1 << q;
800 else 788 else
801 ahp->ah_txEolInterruptMask &= ~(1 << q); 789 ah->ah_txEolInterruptMask &= ~(1 << q);
802 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) 790 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
803 ahp->ah_txUrnInterruptMask |= 1 << q; 791 ah->ah_txUrnInterruptMask |= 1 << q;
804 else 792 else
805 ahp->ah_txUrnInterruptMask &= ~(1 << q); 793 ah->ah_txUrnInterruptMask &= ~(1 << q);
806 ath9k_hw_set_txq_interrupts(ah, qi); 794 ath9k_hw_set_txq_interrupts(ah, qi);
807 795
808 return true; 796 return true;
809} 797}
810 798
811int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds, 799int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
812 u32 pa, struct ath_desc *nds, u64 tsf) 800 u32 pa, struct ath_desc *nds, u64 tsf)
813{ 801{
814 struct ar5416_desc ads; 802 struct ar5416_desc ads;
@@ -873,7 +861,7 @@ int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
873 return 0; 861 return 0;
874} 862}
875 863
876bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, 864bool ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
877 u32 size, u32 flags) 865 u32 size, u32 flags)
878{ 866{
879 struct ar5416_desc *ads = AR5416DESC(ds); 867 struct ar5416_desc *ads = AR5416DESC(ds);
@@ -890,7 +878,7 @@ bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
890 return true; 878 return true;
891} 879}
892 880
893bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set) 881bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
894{ 882{
895 u32 reg; 883 u32 reg;
896 884
@@ -917,17 +905,17 @@ bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set)
917 return true; 905 return true;
918} 906}
919 907
920void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp) 908void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
921{ 909{
922 REG_WRITE(ah, AR_RXDP, rxdp); 910 REG_WRITE(ah, AR_RXDP, rxdp);
923} 911}
924 912
925void ath9k_hw_rxena(struct ath_hal *ah) 913void ath9k_hw_rxena(struct ath_hw *ah)
926{ 914{
927 REG_WRITE(ah, AR_CR, AR_CR_RXE); 915 REG_WRITE(ah, AR_CR, AR_CR_RXE);
928} 916}
929 917
930void ath9k_hw_startpcureceive(struct ath_hal *ah) 918void ath9k_hw_startpcureceive(struct ath_hw *ah)
931{ 919{
932 ath9k_enable_mib_counters(ah); 920 ath9k_enable_mib_counters(ah);
933 921
@@ -936,14 +924,14 @@ void ath9k_hw_startpcureceive(struct ath_hal *ah)
936 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 924 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
937} 925}
938 926
939void ath9k_hw_stoppcurecv(struct ath_hal *ah) 927void ath9k_hw_stoppcurecv(struct ath_hw *ah)
940{ 928{
941 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); 929 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
942 930
943 ath9k_hw_disable_mib_counters(ah); 931 ath9k_hw_disable_mib_counters(ah);
944} 932}
945 933
946bool ath9k_hw_stopdmarecv(struct ath_hal *ah) 934bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
947{ 935{
948 REG_WRITE(ah, AR_CR, AR_CR_RXD); 936 REG_WRITE(ah, AR_CR, AR_CR_RXD);
949 937
diff --git a/drivers/net/wireless/ath9k/mac.h b/drivers/net/wireless/ath9k/mac.h
index 9012af247797..74b660ae8add 100644
--- a/drivers/net/wireless/ath9k/mac.h
+++ b/drivers/net/wireless/ath9k/mac.h
@@ -619,58 +619,58 @@ enum ath9k_ht_extprotspacing {
619 ATH9K_HT_EXTPROTSPACING_25 = 1, 619 ATH9K_HT_EXTPROTSPACING_25 = 1,
620}; 620};
621 621
622struct ath_hal; 622struct ath_hw;
623struct ath9k_channel; 623struct ath9k_channel;
624struct ath_rate_table; 624struct ath_rate_table;
625 625
626u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q); 626u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
627bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp); 627bool ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
628bool ath9k_hw_txstart(struct ath_hal *ah, u32 q); 628bool ath9k_hw_txstart(struct ath_hw *ah, u32 q);
629u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q); 629u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
630bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel); 630bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
631bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q); 631bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q);
632bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, 632bool ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
633 u32 segLen, bool firstSeg, 633 u32 segLen, bool firstSeg,
634 bool lastSeg, const struct ath_desc *ds0); 634 bool lastSeg, const struct ath_desc *ds0);
635void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds); 635void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds);
636int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds); 636int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds);
637void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, 637void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
638 u32 pktLen, enum ath9k_pkt_type type, u32 txPower, 638 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
639 u32 keyIx, enum ath9k_key_type keyType, u32 flags); 639 u32 keyIx, enum ath9k_key_type keyType, u32 flags);
640void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, 640void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
641 struct ath_desc *lastds, 641 struct ath_desc *lastds,
642 u32 durUpdateEn, u32 rtsctsRate, 642 u32 durUpdateEn, u32 rtsctsRate,
643 u32 rtsctsDuration, 643 u32 rtsctsDuration,
644 struct ath9k_11n_rate_series series[], 644 struct ath9k_11n_rate_series series[],
645 u32 nseries, u32 flags); 645 u32 nseries, u32 flags);
646void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, 646void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
647 u32 aggrLen); 647 u32 aggrLen);
648void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, 648void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
649 u32 numDelims); 649 u32 numDelims);
650void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds); 650void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds);
651void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds); 651void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds);
652void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds, 652void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
653 u32 burstDuration); 653 u32 burstDuration);
654void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, 654void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
655 u32 vmf); 655 u32 vmf);
656void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs); 656void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
657bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, 657bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
658 const struct ath9k_tx_queue_info *qinfo); 658 const struct ath9k_tx_queue_info *qinfo);
659bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, 659bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
660 struct ath9k_tx_queue_info *qinfo); 660 struct ath9k_tx_queue_info *qinfo);
661int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, 661int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
662 const struct ath9k_tx_queue_info *qinfo); 662 const struct ath9k_tx_queue_info *qinfo);
663bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q); 663bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q);
664bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q); 664bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q);
665int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds, 665int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
666 u32 pa, struct ath_desc *nds, u64 tsf); 666 u32 pa, struct ath_desc *nds, u64 tsf);
667bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, 667bool ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
668 u32 size, u32 flags); 668 u32 size, u32 flags);
669bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set); 669bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
670void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp); 670void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
671void ath9k_hw_rxena(struct ath_hal *ah); 671void ath9k_hw_rxena(struct ath_hw *ah);
672void ath9k_hw_startpcureceive(struct ath_hal *ah); 672void ath9k_hw_startpcureceive(struct ath_hw *ah);
673void ath9k_hw_stoppcurecv(struct ath_hal *ah); 673void ath9k_hw_stoppcurecv(struct ath_hw *ah);
674bool ath9k_hw_stopdmarecv(struct ath_hal *ah); 674bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
675 675
676#endif /* MAC_H */ 676#endif /* MAC_H */
diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c
index bafefbed8382..a50f989abd6c 100644
--- a/drivers/net/wireless/ath9k/main.c
+++ b/drivers/net/wireless/ath9k/main.c
@@ -137,7 +137,7 @@ static void ath_cache_conf_rate(struct ath_softc *sc,
137 137
138static void ath_update_txpow(struct ath_softc *sc) 138static void ath_update_txpow(struct ath_softc *sc)
139{ 139{
140 struct ath_hal *ah = sc->sc_ah; 140 struct ath_hw *ah = sc->sc_ah;
141 u32 txpow; 141 u32 txpow;
142 142
143 if (sc->curtxpow != sc->config.txpowlimit) { 143 if (sc->curtxpow != sc->config.txpowlimit) {
@@ -234,7 +234,7 @@ static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
234*/ 234*/
235static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan) 235static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
236{ 236{
237 struct ath_hal *ah = sc->sc_ah; 237 struct ath_hw *ah = sc->sc_ah;
238 bool fastcc = true, stopped; 238 bool fastcc = true, stopped;
239 struct ieee80211_hw *hw = sc->hw; 239 struct ieee80211_hw *hw = sc->hw;
240 struct ieee80211_channel *channel = hw->conf.channel; 240 struct ieee80211_channel *channel = hw->conf.channel;
@@ -309,7 +309,7 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
309static void ath_ani_calibrate(unsigned long data) 309static void ath_ani_calibrate(unsigned long data)
310{ 310{
311 struct ath_softc *sc; 311 struct ath_softc *sc;
312 struct ath_hal *ah; 312 struct ath_hw *ah;
313 bool longcal = false; 313 bool longcal = false;
314 bool shortcal = false; 314 bool shortcal = false;
315 bool aniflag = false; 315 bool aniflag = false;
@@ -479,7 +479,7 @@ static void ath9k_tasklet(unsigned long data)
479irqreturn_t ath_isr(int irq, void *dev) 479irqreturn_t ath_isr(int irq, void *dev)
480{ 480{
481 struct ath_softc *sc = dev; 481 struct ath_softc *sc = dev;
482 struct ath_hal *ah = sc->sc_ah; 482 struct ath_hw *ah = sc->sc_ah;
483 enum ath9k_int status; 483 enum ath9k_int status;
484 bool sched = false; 484 bool sched = false;
485 485
@@ -1091,7 +1091,7 @@ fail:
1091 1091
1092static void ath_radio_enable(struct ath_softc *sc) 1092static void ath_radio_enable(struct ath_softc *sc)
1093{ 1093{
1094 struct ath_hal *ah = sc->sc_ah; 1094 struct ath_hw *ah = sc->sc_ah;
1095 struct ieee80211_channel *channel = sc->hw->conf.channel; 1095 struct ieee80211_channel *channel = sc->hw->conf.channel;
1096 int r; 1096 int r;
1097 1097
@@ -1132,7 +1132,7 @@ static void ath_radio_enable(struct ath_softc *sc)
1132 1132
1133static void ath_radio_disable(struct ath_softc *sc) 1133static void ath_radio_disable(struct ath_softc *sc)
1134{ 1134{
1135 struct ath_hal *ah = sc->sc_ah; 1135 struct ath_hw *ah = sc->sc_ah;
1136 struct ieee80211_channel *channel = sc->hw->conf.channel; 1136 struct ieee80211_channel *channel = sc->hw->conf.channel;
1137 int r; 1137 int r;
1138 1138
@@ -1167,7 +1167,7 @@ static void ath_radio_disable(struct ath_softc *sc)
1167 1167
1168static bool ath_is_rfkill_set(struct ath_softc *sc) 1168static bool ath_is_rfkill_set(struct ath_softc *sc)
1169{ 1169{
1170 struct ath_hal *ah = sc->sc_ah; 1170 struct ath_hw *ah = sc->sc_ah;
1171 1171
1172 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) == 1172 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1173 ah->ah_rfkill_polarity; 1173 ah->ah_rfkill_polarity;
@@ -1345,7 +1345,7 @@ void ath_detach(struct ath_softc *sc)
1345 1345
1346static int ath_init(u16 devid, struct ath_softc *sc) 1346static int ath_init(u16 devid, struct ath_softc *sc)
1347{ 1347{
1348 struct ath_hal *ah = NULL; 1348 struct ath_hw *ah = NULL;
1349 int status; 1349 int status;
1350 int error = 0, i; 1350 int error = 0, i;
1351 int csz = 0; 1351 int csz = 0;
@@ -1370,7 +1370,7 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1370 /* XXX assert csz is non-zero */ 1370 /* XXX assert csz is non-zero */
1371 sc->cachelsz = csz << 2; /* convert to bytes */ 1371 sc->cachelsz = csz << 2; /* convert to bytes */
1372 1372
1373 ah = ath9k_hw_attach(devid, sc, sc->mem, &status); 1373 ah = ath9k_hw_attach(devid, sc, &status);
1374 if (ah == NULL) { 1374 if (ah == NULL) {
1375 DPRINTF(sc, ATH_DBG_FATAL, 1375 DPRINTF(sc, ATH_DBG_FATAL,
1376 "Unable to attach hardware; HAL status %d\n", status); 1376 "Unable to attach hardware; HAL status %d\n", status);
@@ -1671,7 +1671,7 @@ detach:
1671 1671
1672int ath_reset(struct ath_softc *sc, bool retry_tx) 1672int ath_reset(struct ath_softc *sc, bool retry_tx)
1673{ 1673{
1674 struct ath_hal *ah = sc->sc_ah; 1674 struct ath_hw *ah = sc->sc_ah;
1675 struct ieee80211_hw *hw = sc->hw; 1675 struct ieee80211_hw *hw = sc->hw;
1676 int r; 1676 int r;
1677 1677
@@ -2272,7 +2272,7 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
2272 struct ieee80211_if_conf *conf) 2272 struct ieee80211_if_conf *conf)
2273{ 2273{
2274 struct ath_softc *sc = hw->priv; 2274 struct ath_softc *sc = hw->priv;
2275 struct ath_hal *ah = sc->sc_ah; 2275 struct ath_hw *ah = sc->sc_ah;
2276 struct ath_vif *avp = (void *)vif->drv_priv; 2276 struct ath_vif *avp = (void *)vif->drv_priv;
2277 u32 rfilt = 0; 2277 u32 rfilt = 0;
2278 int error, i; 2278 int error, i;
diff --git a/drivers/net/wireless/ath9k/pci.c b/drivers/net/wireless/ath9k/pci.c
index 192c8c4e59fc..eac8db742602 100644
--- a/drivers/net/wireless/ath9k/pci.c
+++ b/drivers/net/wireless/ath9k/pci.c
@@ -56,7 +56,7 @@ static void ath_pci_cleanup(struct ath_softc *sc)
56 pci_disable_device(pdev); 56 pci_disable_device(pdev);
57} 57}
58 58
59static bool ath_pci_eeprom_read(struct ath_hal *ah, u32 off, u16 *data) 59static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
60{ 60{
61 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); 61 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
62 62
@@ -87,7 +87,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
87 u8 csz; 87 u8 csz;
88 u32 val; 88 u32 val;
89 int ret = 0; 89 int ret = 0;
90 struct ath_hal *ah; 90 struct ath_hw *ah;
91 91
92 if (pci_enable_device(pdev)) 92 if (pci_enable_device(pdev))
93 return -EIO; 93 return -EIO;
diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c
index ea29941412d4..da4165b8d6be 100644
--- a/drivers/net/wireless/ath9k/phy.c
+++ b/drivers/net/wireless/ath9k/phy.c
@@ -17,16 +17,14 @@
17#include "ath9k.h" 17#include "ath9k.h"
18 18
19void 19void
20ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, u32 freqIndex, 20ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex,
21 int regWrites) 21 int regWrites)
22{ 22{
23 struct ath_hal_5416 *ahp = AH5416(ah); 23 REG_WRITE_ARRAY(&ah->ah_iniBB_RfGain, freqIndex, regWrites);
24
25 REG_WRITE_ARRAY(&ahp->ah_iniBB_RfGain, freqIndex, regWrites);
26} 24}
27 25
28bool 26bool
29ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan) 27ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
30{ 28{
31 u32 channelSel = 0; 29 u32 channelSel = 0;
32 u32 bModeSynth = 0; 30 u32 bModeSynth = 0;
@@ -93,14 +91,13 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan)
93 REG_WRITE(ah, AR_PHY(0x37), reg32); 91 REG_WRITE(ah, AR_PHY(0x37), reg32);
94 92
95 ah->ah_curchan = chan; 93 ah->ah_curchan = chan;
96 94 ah->ah_curchanRadIndex = -1;
97 AH5416(ah)->ah_curchanRadIndex = -1;
98 95
99 return true; 96 return true;
100} 97}
101 98
102bool 99bool
103ath9k_hw_ar9280_set_channel(struct ath_hal *ah, 100ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
104 struct ath9k_channel *chan) 101 struct ath9k_channel *chan)
105{ 102{
106 u16 bMode, fracMode, aModeRefSel = 0; 103 u16 bMode, fracMode, aModeRefSel = 0;
@@ -164,8 +161,7 @@ ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
164 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); 161 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
165 162
166 ah->ah_curchan = chan; 163 ah->ah_curchan = chan;
167 164 ah->ah_curchanRadIndex = -1;
168 AH5416(ah)->ah_curchanRadIndex = -1;
169 165
170 return true; 166 return true;
171} 167}
@@ -198,11 +194,9 @@ ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
198} 194}
199 195
200bool 196bool
201ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan, 197ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
202 u16 modesIndex) 198 u16 modesIndex)
203{ 199{
204 struct ath_hal_5416 *ahp = AH5416(ah);
205
206 u32 eepMinorRev; 200 u32 eepMinorRev;
207 u32 ob5GHz = 0, db5GHz = 0; 201 u32 ob5GHz = 0, db5GHz = 0;
208 u32 ob2GHz = 0, db2GHz = 0; 202 u32 ob2GHz = 0, db2GHz = 0;
@@ -213,19 +207,19 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan,
213 207
214 eepMinorRev = ath9k_hw_get_eeprom(ah, EEP_MINOR_REV); 208 eepMinorRev = ath9k_hw_get_eeprom(ah, EEP_MINOR_REV);
215 209
216 RF_BANK_SETUP(ahp->ah_analogBank0Data, &ahp->ah_iniBank0, 1); 210 RF_BANK_SETUP(ah->ah_analogBank0Data, &ah->ah_iniBank0, 1);
217 211
218 RF_BANK_SETUP(ahp->ah_analogBank1Data, &ahp->ah_iniBank1, 1); 212 RF_BANK_SETUP(ah->ah_analogBank1Data, &ah->ah_iniBank1, 1);
219 213
220 RF_BANK_SETUP(ahp->ah_analogBank2Data, &ahp->ah_iniBank2, 1); 214 RF_BANK_SETUP(ah->ah_analogBank2Data, &ah->ah_iniBank2, 1);
221 215
222 RF_BANK_SETUP(ahp->ah_analogBank3Data, &ahp->ah_iniBank3, 216 RF_BANK_SETUP(ah->ah_analogBank3Data, &ah->ah_iniBank3,
223 modesIndex); 217 modesIndex);
224 { 218 {
225 int i; 219 int i;
226 for (i = 0; i < ahp->ah_iniBank6TPC.ia_rows; i++) { 220 for (i = 0; i < ah->ah_iniBank6TPC.ia_rows; i++) {
227 ahp->ah_analogBank6Data[i] = 221 ah->ah_analogBank6Data[i] =
228 INI_RA(&ahp->ah_iniBank6TPC, i, modesIndex); 222 INI_RA(&ah->ah_iniBank6TPC, i, modesIndex);
229 } 223 }
230 } 224 }
231 225
@@ -233,137 +227,132 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan,
233 if (IS_CHAN_2GHZ(chan)) { 227 if (IS_CHAN_2GHZ(chan)) {
234 ob2GHz = ath9k_hw_get_eeprom(ah, EEP_OB_2); 228 ob2GHz = ath9k_hw_get_eeprom(ah, EEP_OB_2);
235 db2GHz = ath9k_hw_get_eeprom(ah, EEP_DB_2); 229 db2GHz = ath9k_hw_get_eeprom(ah, EEP_DB_2);
236 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, 230 ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data,
237 ob2GHz, 3, 197, 0); 231 ob2GHz, 3, 197, 0);
238 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, 232 ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data,
239 db2GHz, 3, 194, 0); 233 db2GHz, 3, 194, 0);
240 } else { 234 } else {
241 ob5GHz = ath9k_hw_get_eeprom(ah, EEP_OB_5); 235 ob5GHz = ath9k_hw_get_eeprom(ah, EEP_OB_5);
242 db5GHz = ath9k_hw_get_eeprom(ah, EEP_DB_5); 236 db5GHz = ath9k_hw_get_eeprom(ah, EEP_DB_5);
243 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, 237 ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data,
244 ob5GHz, 3, 203, 0); 238 ob5GHz, 3, 203, 0);
245 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, 239 ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data,
246 db5GHz, 3, 200, 0); 240 db5GHz, 3, 200, 0);
247 } 241 }
248 } 242 }
249 243
250 RF_BANK_SETUP(ahp->ah_analogBank7Data, &ahp->ah_iniBank7, 1); 244 RF_BANK_SETUP(ah->ah_analogBank7Data, &ah->ah_iniBank7, 1);
251 245
252 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank0, ahp->ah_analogBank0Data, 246 REG_WRITE_RF_ARRAY(&ah->ah_iniBank0, ah->ah_analogBank0Data,
253 regWrites); 247 regWrites);
254 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank1, ahp->ah_analogBank1Data, 248 REG_WRITE_RF_ARRAY(&ah->ah_iniBank1, ah->ah_analogBank1Data,
255 regWrites); 249 regWrites);
256 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank2, ahp->ah_analogBank2Data, 250 REG_WRITE_RF_ARRAY(&ah->ah_iniBank2, ah->ah_analogBank2Data,
257 regWrites); 251 regWrites);
258 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank3, ahp->ah_analogBank3Data, 252 REG_WRITE_RF_ARRAY(&ah->ah_iniBank3, ah->ah_analogBank3Data,
259 regWrites); 253 regWrites);
260 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6TPC, ahp->ah_analogBank6Data, 254 REG_WRITE_RF_ARRAY(&ah->ah_iniBank6TPC, ah->ah_analogBank6Data,
261 regWrites); 255 regWrites);
262 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank7, ahp->ah_analogBank7Data, 256 REG_WRITE_RF_ARRAY(&ah->ah_iniBank7, ah->ah_analogBank7Data,
263 regWrites); 257 regWrites);
264 258
265 return true; 259 return true;
266} 260}
267 261
268void 262void
269ath9k_hw_rfdetach(struct ath_hal *ah) 263ath9k_hw_rfdetach(struct ath_hw *ah)
270{ 264{
271 struct ath_hal_5416 *ahp = AH5416(ah); 265 if (ah->ah_analogBank0Data != NULL) {
272 266 kfree(ah->ah_analogBank0Data);
273 if (ahp->ah_analogBank0Data != NULL) { 267 ah->ah_analogBank0Data = NULL;
274 kfree(ahp->ah_analogBank0Data);
275 ahp->ah_analogBank0Data = NULL;
276 } 268 }
277 if (ahp->ah_analogBank1Data != NULL) { 269 if (ah->ah_analogBank1Data != NULL) {
278 kfree(ahp->ah_analogBank1Data); 270 kfree(ah->ah_analogBank1Data);
279 ahp->ah_analogBank1Data = NULL; 271 ah->ah_analogBank1Data = NULL;
280 } 272 }
281 if (ahp->ah_analogBank2Data != NULL) { 273 if (ah->ah_analogBank2Data != NULL) {
282 kfree(ahp->ah_analogBank2Data); 274 kfree(ah->ah_analogBank2Data);
283 ahp->ah_analogBank2Data = NULL; 275 ah->ah_analogBank2Data = NULL;
284 } 276 }
285 if (ahp->ah_analogBank3Data != NULL) { 277 if (ah->ah_analogBank3Data != NULL) {
286 kfree(ahp->ah_analogBank3Data); 278 kfree(ah->ah_analogBank3Data);
287 ahp->ah_analogBank3Data = NULL; 279 ah->ah_analogBank3Data = NULL;
288 } 280 }
289 if (ahp->ah_analogBank6Data != NULL) { 281 if (ah->ah_analogBank6Data != NULL) {
290 kfree(ahp->ah_analogBank6Data); 282 kfree(ah->ah_analogBank6Data);
291 ahp->ah_analogBank6Data = NULL; 283 ah->ah_analogBank6Data = NULL;
292 } 284 }
293 if (ahp->ah_analogBank6TPCData != NULL) { 285 if (ah->ah_analogBank6TPCData != NULL) {
294 kfree(ahp->ah_analogBank6TPCData); 286 kfree(ah->ah_analogBank6TPCData);
295 ahp->ah_analogBank6TPCData = NULL; 287 ah->ah_analogBank6TPCData = NULL;
296 } 288 }
297 if (ahp->ah_analogBank7Data != NULL) { 289 if (ah->ah_analogBank7Data != NULL) {
298 kfree(ahp->ah_analogBank7Data); 290 kfree(ah->ah_analogBank7Data);
299 ahp->ah_analogBank7Data = NULL; 291 ah->ah_analogBank7Data = NULL;
300 } 292 }
301 if (ahp->ah_addac5416_21 != NULL) { 293 if (ah->ah_addac5416_21 != NULL) {
302 kfree(ahp->ah_addac5416_21); 294 kfree(ah->ah_addac5416_21);
303 ahp->ah_addac5416_21 = NULL; 295 ah->ah_addac5416_21 = NULL;
304 } 296 }
305 if (ahp->ah_bank6Temp != NULL) { 297 if (ah->ah_bank6Temp != NULL) {
306 kfree(ahp->ah_bank6Temp); 298 kfree(ah->ah_bank6Temp);
307 ahp->ah_bank6Temp = NULL; 299 ah->ah_bank6Temp = NULL;
308 } 300 }
309} 301}
310 302
311bool ath9k_hw_init_rf(struct ath_hal *ah, int *status) 303bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
312{ 304{
313 struct ath_hal_5416 *ahp = AH5416(ah);
314
315 if (!AR_SREV_9280_10_OR_LATER(ah)) { 305 if (!AR_SREV_9280_10_OR_LATER(ah)) {
316 306 ah->ah_analogBank0Data =
317 ahp->ah_analogBank0Data =
318 kzalloc((sizeof(u32) * 307 kzalloc((sizeof(u32) *
319 ahp->ah_iniBank0.ia_rows), GFP_KERNEL); 308 ah->ah_iniBank0.ia_rows), GFP_KERNEL);
320 ahp->ah_analogBank1Data = 309 ah->ah_analogBank1Data =
321 kzalloc((sizeof(u32) * 310 kzalloc((sizeof(u32) *
322 ahp->ah_iniBank1.ia_rows), GFP_KERNEL); 311 ah->ah_iniBank1.ia_rows), GFP_KERNEL);
323 ahp->ah_analogBank2Data = 312 ah->ah_analogBank2Data =
324 kzalloc((sizeof(u32) * 313 kzalloc((sizeof(u32) *
325 ahp->ah_iniBank2.ia_rows), GFP_KERNEL); 314 ah->ah_iniBank2.ia_rows), GFP_KERNEL);
326 ahp->ah_analogBank3Data = 315 ah->ah_analogBank3Data =
327 kzalloc((sizeof(u32) * 316 kzalloc((sizeof(u32) *
328 ahp->ah_iniBank3.ia_rows), GFP_KERNEL); 317 ah->ah_iniBank3.ia_rows), GFP_KERNEL);
329 ahp->ah_analogBank6Data = 318 ah->ah_analogBank6Data =
330 kzalloc((sizeof(u32) * 319 kzalloc((sizeof(u32) *
331 ahp->ah_iniBank6.ia_rows), GFP_KERNEL); 320 ah->ah_iniBank6.ia_rows), GFP_KERNEL);
332 ahp->ah_analogBank6TPCData = 321 ah->ah_analogBank6TPCData =
333 kzalloc((sizeof(u32) * 322 kzalloc((sizeof(u32) *
334 ahp->ah_iniBank6TPC.ia_rows), GFP_KERNEL); 323 ah->ah_iniBank6TPC.ia_rows), GFP_KERNEL);
335 ahp->ah_analogBank7Data = 324 ah->ah_analogBank7Data =
336 kzalloc((sizeof(u32) * 325 kzalloc((sizeof(u32) *
337 ahp->ah_iniBank7.ia_rows), GFP_KERNEL); 326 ah->ah_iniBank7.ia_rows), GFP_KERNEL);
338 327
339 if (ahp->ah_analogBank0Data == NULL 328 if (ah->ah_analogBank0Data == NULL
340 || ahp->ah_analogBank1Data == NULL 329 || ah->ah_analogBank1Data == NULL
341 || ahp->ah_analogBank2Data == NULL 330 || ah->ah_analogBank2Data == NULL
342 || ahp->ah_analogBank3Data == NULL 331 || ah->ah_analogBank3Data == NULL
343 || ahp->ah_analogBank6Data == NULL 332 || ah->ah_analogBank6Data == NULL
344 || ahp->ah_analogBank6TPCData == NULL 333 || ah->ah_analogBank6TPCData == NULL
345 || ahp->ah_analogBank7Data == NULL) { 334 || ah->ah_analogBank7Data == NULL) {
346 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 335 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
347 "Cannot allocate RF banks\n"); 336 "Cannot allocate RF banks\n");
348 *status = -ENOMEM; 337 *status = -ENOMEM;
349 return false; 338 return false;
350 } 339 }
351 340
352 ahp->ah_addac5416_21 = 341 ah->ah_addac5416_21 =
353 kzalloc((sizeof(u32) * 342 kzalloc((sizeof(u32) *
354 ahp->ah_iniAddac.ia_rows * 343 ah->ah_iniAddac.ia_rows *
355 ahp->ah_iniAddac.ia_columns), GFP_KERNEL); 344 ah->ah_iniAddac.ia_columns), GFP_KERNEL);
356 if (ahp->ah_addac5416_21 == NULL) { 345 if (ah->ah_addac5416_21 == NULL) {
357 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 346 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
358 "Cannot allocate ah_addac5416_21\n"); 347 "Cannot allocate ah_addac5416_21\n");
359 *status = -ENOMEM; 348 *status = -ENOMEM;
360 return false; 349 return false;
361 } 350 }
362 351
363 ahp->ah_bank6Temp = 352 ah->ah_bank6Temp =
364 kzalloc((sizeof(u32) * 353 kzalloc((sizeof(u32) *
365 ahp->ah_iniBank6.ia_rows), GFP_KERNEL); 354 ah->ah_iniBank6.ia_rows), GFP_KERNEL);
366 if (ahp->ah_bank6Temp == NULL) { 355 if (ah->ah_bank6Temp == NULL) {
367 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 356 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
368 "Cannot allocate ah_bank6Temp\n"); 357 "Cannot allocate ah_bank6Temp\n");
369 *status = -ENOMEM; 358 *status = -ENOMEM;
@@ -375,23 +364,22 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, int *status)
375} 364}
376 365
377void 366void
378ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan) 367ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
379{ 368{
380 int i, regWrites = 0; 369 int i, regWrites = 0;
381 struct ath_hal_5416 *ahp = AH5416(ah);
382 u32 bank6SelMask; 370 u32 bank6SelMask;
383 u32 *bank6Temp = ahp->ah_bank6Temp; 371 u32 *bank6Temp = ah->ah_bank6Temp;
384 372
385 switch (ahp->ah_diversityControl) { 373 switch (ah->ah_diversityControl) {
386 case ATH9K_ANT_FIXED_A: 374 case ATH9K_ANT_FIXED_A:
387 bank6SelMask = 375 bank6SelMask =
388 (ahp-> 376 (ah->
389 ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 : 377 ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 :
390 REDUCE_CHAIN_1; 378 REDUCE_CHAIN_1;
391 break; 379 break;
392 case ATH9K_ANT_FIXED_B: 380 case ATH9K_ANT_FIXED_B:
393 bank6SelMask = 381 bank6SelMask =
394 (ahp-> 382 (ah->
395 ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 : 383 ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 :
396 REDUCE_CHAIN_0; 384 REDUCE_CHAIN_0;
397 break; 385 break;
@@ -403,8 +391,8 @@ ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan)
403 break; 391 break;
404 } 392 }
405 393
406 for (i = 0; i < ahp->ah_iniBank6.ia_rows; i++) 394 for (i = 0; i < ah->ah_iniBank6.ia_rows; i++)
407 bank6Temp[i] = ahp->ah_analogBank6Data[i]; 395 bank6Temp[i] = ah->ah_analogBank6Data[i];
408 396
409 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask); 397 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
410 398
@@ -418,7 +406,7 @@ ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan)
418 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0); 406 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
419 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0); 407 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
420 408
421 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6, bank6Temp, regWrites); 409 REG_WRITE_RF_ARRAY(&ah->ah_iniBank6, bank6Temp, regWrites);
422 410
423 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053); 411 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
424#ifdef ALTER_SWITCH 412#ifdef ALTER_SWITCH
diff --git a/drivers/net/wireless/ath9k/phy.h b/drivers/net/wireless/ath9k/phy.h
index 3a406a5c0593..71a7f5af7004 100644
--- a/drivers/net/wireless/ath9k/phy.h
+++ b/drivers/net/wireless/ath9k/phy.h
@@ -17,19 +17,19 @@
17#ifndef PHY_H 17#ifndef PHY_H
18#define PHY_H 18#define PHY_H
19 19
20bool ath9k_hw_ar9280_set_channel(struct ath_hal *ah, 20bool ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
21 struct ath9k_channel 21 struct ath9k_channel
22 *chan); 22 *chan);
23bool ath9k_hw_set_channel(struct ath_hal *ah, 23bool ath9k_hw_set_channel(struct ath_hw *ah,
24 struct ath9k_channel *chan); 24 struct ath9k_channel *chan);
25void ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, 25void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex,
26 u32 freqIndex, int regWrites); 26 u32 freqIndex, int regWrites);
27bool ath9k_hw_set_rf_regs(struct ath_hal *ah, 27bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
28 struct ath9k_channel *chan, 28 struct ath9k_channel *chan,
29 u16 modesIndex); 29 u16 modesIndex);
30void ath9k_hw_decrease_chain_power(struct ath_hal *ah, 30void ath9k_hw_decrease_chain_power(struct ath_hw *ah,
31 struct ath9k_channel *chan); 31 struct ath9k_channel *chan);
32bool ath9k_hw_init_rf(struct ath_hal *ah, 32bool ath9k_hw_init_rf(struct ath_hw *ah,
33 int *status); 33 int *status);
34 34
35#define AR_PHY_BASE 0x9800 35#define AR_PHY_BASE 0x9800
@@ -533,7 +533,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah,
533#define ATH9K_KEY_XOR 0xaa 533#define ATH9K_KEY_XOR 0xaa
534 534
535#define ATH9K_IS_MIC_ENABLED(ah) \ 535#define ATH9K_IS_MIC_ENABLED(ah) \
536 (AH5416(ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE) 536 ((ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE)
537 537
538#define ANTSWAP_AB 0x0001 538#define ANTSWAP_AB 0x0001
539#define REDUCE_CHAIN_0 0x00000050 539#define REDUCE_CHAIN_0 0x00000050
diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c
index c51c085f55d6..7c011b1ba333 100644
--- a/drivers/net/wireless/ath9k/recv.c
+++ b/drivers/net/wireless/ath9k/recv.c
@@ -26,7 +26,7 @@
26 */ 26 */
27static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) 27static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
28{ 28{
29 struct ath_hal *ah = sc->sc_ah; 29 struct ath_hw *ah = sc->sc_ah;
30 struct ath_desc *ds; 30 struct ath_desc *ds;
31 struct sk_buff *skb; 31 struct sk_buff *skb;
32 32
@@ -233,7 +233,7 @@ rx_next:
233 233
234static void ath_opmode_init(struct ath_softc *sc) 234static void ath_opmode_init(struct ath_softc *sc)
235{ 235{
236 struct ath_hal *ah = sc->sc_ah; 236 struct ath_hw *ah = sc->sc_ah;
237 u32 rfilt, mfilt[2]; 237 u32 rfilt, mfilt[2];
238 238
239 /* configure rx filter */ 239 /* configure rx filter */
@@ -391,7 +391,7 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
391 391
392int ath_startrecv(struct ath_softc *sc) 392int ath_startrecv(struct ath_softc *sc)
393{ 393{
394 struct ath_hal *ah = sc->sc_ah; 394 struct ath_hw *ah = sc->sc_ah;
395 struct ath_buf *bf, *tbf; 395 struct ath_buf *bf, *tbf;
396 396
397 spin_lock_bh(&sc->rx.rxbuflock); 397 spin_lock_bh(&sc->rx.rxbuflock);
@@ -421,7 +421,7 @@ start_recv:
421 421
422bool ath_stoprecv(struct ath_softc *sc) 422bool ath_stoprecv(struct ath_softc *sc)
423{ 423{
424 struct ath_hal *ah = sc->sc_ah; 424 struct ath_hw *ah = sc->sc_ah;
425 bool stopped; 425 bool stopped;
426 426
427 ath9k_hw_stoppcurecv(ah); 427 ath9k_hw_stoppcurecv(ah);
@@ -452,7 +452,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
452 struct ath_desc *ds; 452 struct ath_desc *ds;
453 struct sk_buff *skb = NULL, *requeue_skb; 453 struct sk_buff *skb = NULL, *requeue_skb;
454 struct ieee80211_rx_status rx_status; 454 struct ieee80211_rx_status rx_status;
455 struct ath_hal *ah = sc->sc_ah; 455 struct ath_hw *ah = sc->sc_ah;
456 struct ieee80211_hdr *hdr; 456 struct ieee80211_hdr *hdr;
457 int hdrlen, padsize, retval; 457 int hdrlen, padsize, retval;
458 bool decrypt_error = false; 458 bool decrypt_error = false;
diff --git a/drivers/net/wireless/ath9k/regd.c b/drivers/net/wireless/ath9k/regd.c
index 32dd0cb34490..8c2b56ac55ff 100644
--- a/drivers/net/wireless/ath9k/regd.c
+++ b/drivers/net/wireless/ath9k/regd.c
@@ -106,17 +106,17 @@ static const struct ieee80211_regdomain ath9k_world_regdom_67_68_6A = {
106 } 106 }
107}; 107};
108 108
109static u16 ath9k_regd_get_eepromRD(struct ath_hal *ah) 109static u16 ath9k_regd_get_eepromRD(struct ath_hw *ah)
110{ 110{
111 return ah->regulatory.current_rd & ~WORLDWIDE_ROAMING_FLAG; 111 return ah->regulatory.current_rd & ~WORLDWIDE_ROAMING_FLAG;
112} 112}
113 113
114u16 ath9k_regd_get_rd(struct ath_hal *ah) 114u16 ath9k_regd_get_rd(struct ath_hw *ah)
115{ 115{
116 return ath9k_regd_get_eepromRD(ah); 116 return ath9k_regd_get_eepromRD(ah);
117} 117}
118 118
119bool ath9k_is_world_regd(struct ath_hal *ah) 119bool ath9k_is_world_regd(struct ath_hw *ah)
120{ 120{
121 return isWwrSKU(ah); 121 return isWwrSKU(ah);
122} 122}
@@ -127,7 +127,7 @@ const struct ieee80211_regdomain *ath9k_default_world_regdomain(void)
127 return &ath9k_world_regdom_64; 127 return &ath9k_world_regdom_64;
128} 128}
129 129
130const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hal *ah) 130const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hw *ah)
131{ 131{
132 switch (ah->regulatory.regpair->regDmnEnum) { 132 switch (ah->regulatory.regpair->regDmnEnum) {
133 case 0x60: 133 case 0x60:
@@ -282,7 +282,7 @@ void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby)
282{ 282{
283 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 283 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
284 struct ath_softc *sc = hw->priv; 284 struct ath_softc *sc = hw->priv;
285 struct ath_hal *ah = sc->sc_ah; 285 struct ath_hw *ah = sc->sc_ah;
286 286
287 switch (ah->regulatory.regpair->regDmnEnum) { 287 switch (ah->regulatory.regpair->regDmnEnum) {
288 case 0x60: 288 case 0x60:
@@ -322,7 +322,7 @@ int ath9k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
322 return 0; 322 return 0;
323} 323}
324 324
325bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah) 325bool ath9k_regd_is_eeprom_valid(struct ath_hw *ah)
326{ 326{
327 u16 rd = ath9k_regd_get_eepromRD(ah); 327 u16 rd = ath9k_regd_get_eepromRD(ah);
328 int i; 328 int i;
@@ -371,7 +371,7 @@ ath9k_regd_find_country_by_rd(int regdmn)
371} 371}
372 372
373/* Returns the map of the EEPROM set RD to a country code */ 373/* Returns the map of the EEPROM set RD to a country code */
374static u16 ath9k_regd_get_default_country(struct ath_hal *ah) 374static u16 ath9k_regd_get_default_country(struct ath_hw *ah)
375{ 375{
376 u16 rd; 376 u16 rd;
377 377
@@ -402,7 +402,7 @@ ath9k_get_regpair(int regdmn)
402 return NULL; 402 return NULL;
403} 403}
404 404
405int ath9k_regd_init(struct ath_hal *ah) 405int ath9k_regd_init(struct ath_hw *ah)
406{ 406{
407 struct country_code_to_enum_rd *country = NULL; 407 struct country_code_to_enum_rd *country = NULL;
408 int regdmn; 408 int regdmn;
@@ -462,7 +462,7 @@ int ath9k_regd_init(struct ath_hal *ah)
462 return 0; 462 return 0;
463} 463}
464 464
465u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan) 465u32 ath9k_regd_get_ctl(struct ath_hw *ah, struct ath9k_channel *chan)
466{ 466{
467 u32 ctl = NO_CTL; 467 u32 ctl = NO_CTL;
468 468
diff --git a/drivers/net/wireless/ath9k/regd.h b/drivers/net/wireless/ath9k/regd.h
index 65abdf46115d..39420de818f8 100644
--- a/drivers/net/wireless/ath9k/regd.h
+++ b/drivers/net/wireless/ath9k/regd.h
@@ -239,17 +239,17 @@ enum CountryCode {
239 CTRY_BELGIUM2 = 5002 239 CTRY_BELGIUM2 = 5002
240}; 240};
241 241
242u16 ath9k_regd_get_rd(struct ath_hal *ah); 242u16 ath9k_regd_get_rd(struct ath_hw *ah);
243bool ath9k_is_world_regd(struct ath_hal *ah); 243bool ath9k_is_world_regd(struct ath_hw *ah);
244const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hal *ah); 244const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hw *ah);
245const struct ieee80211_regdomain *ath9k_default_world_regdomain(void); 245const struct ieee80211_regdomain *ath9k_default_world_regdomain(void);
246void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby); 246void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby);
247void ath9k_reg_apply_radar_flags(struct wiphy *wiphy); 247void ath9k_reg_apply_radar_flags(struct wiphy *wiphy);
248int ath9k_regd_init(struct ath_hal *ah); 248int ath9k_regd_init(struct ath_hw *ah);
249bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah); 249bool ath9k_regd_is_eeprom_valid(struct ath_hw *ah);
250u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan); 250u32 ath9k_regd_get_ctl(struct ath_hw *ah, struct ath9k_channel *chan);
251int ath9k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request); 251int ath9k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request);
252void ath9k_regd_get_current_country(struct ath_hal *ah, 252void ath9k_regd_get_current_country(struct ath_hw *ah,
253 struct ath9k_country_entry *ctry); 253 struct ath9k_country_entry *ctry);
254 254
255#endif 255#endif
diff --git a/drivers/net/wireless/ath9k/xmit.c b/drivers/net/wireless/ath9k/xmit.c
index 777376094a4a..3fff3344b2ee 100644
--- a/drivers/net/wireless/ath9k/xmit.c
+++ b/drivers/net/wireless/ath9k/xmit.c
@@ -809,7 +809,7 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
809 809
810struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 810struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
811{ 811{
812 struct ath_hal *ah = sc->sc_ah; 812 struct ath_hw *ah = sc->sc_ah;
813 struct ath9k_tx_queue_info qi; 813 struct ath9k_tx_queue_info qi;
814 int qnum; 814 int qnum;
815 815
@@ -926,7 +926,7 @@ struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
926int ath_txq_update(struct ath_softc *sc, int qnum, 926int ath_txq_update(struct ath_softc *sc, int qnum,
927 struct ath9k_tx_queue_info *qinfo) 927 struct ath9k_tx_queue_info *qinfo)
928{ 928{
929 struct ath_hal *ah = sc->sc_ah; 929 struct ath_hw *ah = sc->sc_ah;
930 int error = 0; 930 int error = 0;
931 struct ath9k_tx_queue_info qi; 931 struct ath9k_tx_queue_info qi;
932 932
@@ -1047,7 +1047,7 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1047 1047
1048void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) 1048void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1049{ 1049{
1050 struct ath_hal *ah = sc->sc_ah; 1050 struct ath_hw *ah = sc->sc_ah;
1051 struct ath_txq *txq; 1051 struct ath_txq *txq;
1052 int i, npend = 0; 1052 int i, npend = 0;
1053 1053
@@ -1165,7 +1165,7 @@ int ath_tx_setup(struct ath_softc *sc, int haltype)
1165static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 1165static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1166 struct list_head *head) 1166 struct list_head *head)
1167{ 1167{
1168 struct ath_hal *ah = sc->sc_ah; 1168 struct ath_hw *ah = sc->sc_ah;
1169 struct ath_buf *bf; 1169 struct ath_buf *bf;
1170 1170
1171 /* 1171 /*
@@ -1580,7 +1580,7 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1580 struct list_head bf_head; 1580 struct list_head bf_head;
1581 struct ath_desc *ds; 1581 struct ath_desc *ds;
1582 struct ath_atx_tid *tid; 1582 struct ath_atx_tid *tid;
1583 struct ath_hal *ah = sc->sc_ah; 1583 struct ath_hw *ah = sc->sc_ah;
1584 int frm_type; 1584 int frm_type;
1585 1585
1586 frm_type = get_hw_packet_type(skb); 1586 frm_type = get_hw_packet_type(skb);
@@ -1879,7 +1879,7 @@ static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1879 1879
1880static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 1880static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1881{ 1881{
1882 struct ath_hal *ah = sc->sc_ah; 1882 struct ath_hw *ah = sc->sc_ah;
1883 struct ath_buf *bf, *lastbf, *bf_held = NULL; 1883 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1884 struct list_head bf_head; 1884 struct list_head bf_head;
1885 struct ath_desc *ds; 1885 struct ath_desc *ds;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 21:58:32 -0500