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authorBen Dooks <ben-linux@fluff.org>2005-10-20 18:21:18 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-10-20 18:21:18 -0400
commita7ce8edc8232da51dc3a804ec9c734019d115b40 (patch)
tree05d79d60b96b59d62709b11c2b1c1b497cb70902
parentb2640b420a806c91f6b8799314ca96bb88a246d2 (diff)
[ARM] 3026/1: S3C2410 - avoid possible overflow in pll calculations
Patch from Ben Dooks Avoid the possiblity that if the board is using a 16.9334 or higher crystal with a high PLL multiplier, then the pll value could overflow the capability of an int. Also fix the value types of the intermediate variables to unsigned int. Rewrite of patch from Guillaume Gourat Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h15
1 files changed, 11 insertions, 4 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index 16f4c3cc1388..66794b13e185 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -18,7 +18,8 @@
18 * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat) 18 * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat)
19 * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA 19 * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA
20 * 27-Aug-2005 Ben Dooks Add clock-slow info 20 * 27-Aug-2005 Ben Dooks Add clock-slow info
21 */ 21 * 20-Oct-2005 Ben Dooks Fixed overflow in PLL (Guillaume Gourat)
22*/
22 23
23#ifndef __ASM_ARM_REGS_CLOCK 24#ifndef __ASM_ARM_REGS_CLOCK
24#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $" 25#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
@@ -83,10 +84,13 @@
83 84
84#ifndef __ASSEMBLY__ 85#ifndef __ASSEMBLY__
85 86
87#include <asm/div64.h>
88
86static inline unsigned int 89static inline unsigned int
87s3c2410_get_pll(int pllval, int baseclk) 90s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
88{ 91{
89 int mdiv, pdiv, sdiv; 92 unsigned int mdiv, pdiv, sdiv;
93 uint64_t fvco;
90 94
91 mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT; 95 mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
92 pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT; 96 pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
@@ -96,7 +100,10 @@ s3c2410_get_pll(int pllval, int baseclk)
96 pdiv &= S3C2410_PLLCON_PDIVMASK; 100 pdiv &= S3C2410_PLLCON_PDIVMASK;
97 sdiv &= S3C2410_PLLCON_SDIVMASK; 101 sdiv &= S3C2410_PLLCON_SDIVMASK;
98 102
99 return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv); 103 fvco = (uint64_t)baseclk * (mdiv + 8);
104 do_div(fvco, (pdiv + 2) << sdiv);
105
106 return (unsigned int)fvco;
100} 107}
101 108
102#endif /* __ASSEMBLY__ */ 109#endif /* __ASSEMBLY__ */