diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-08-08 13:01:46 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-08-08 13:01:46 -0400 |
| commit | d71048e22f47725a5808ea2e4e1e72fa36c1a788 (patch) | |
| tree | 65debebb2964cb4cbde4d29e15730527d686a540 | |
| parent | 44d51a029f95d49c5c7ccd7808f81904c20c3abd (diff) | |
| parent | d21872b3683ff37f73c68993749a6e6aeeaed265 (diff) | |
Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (143 commits)
omap: mailbox: reorganize headers
omap: mailbox: standarize on 'omap-mailbox'
omap: mailbox: only compile for configured archs
omap: mailbox: simplify omap_mbox_register()
omap: mailbox: reorganize registering
omap: mailbox: add IRQ names
omap: mailbox: remove unecessary fields
omap: mailbox: don't export unecessary symbols
omap: mailbox: update omap1 probing
omap: mailbox: use correct config for omap1
omap: mailbox: 2420 should be detected at run-time
omap: mailbox: reorganize structures
omap: mailbox: trivial cleanups
omap mailbox: Set a device in logical mbox instance for traceability
omap: mailbox: convert block api to kfifo
omap: mailbox: remove (un)likely macros from cold paths
omap: mailbox cleanup: split MODULE_AUTHOR line
omap: mailbox: convert rwlocks to spinlock
Mailbox: disable mailbox interrupt when request queue
Mailbox: new mutext lock for h/w mailbox configuration
...
154 files changed, 6420 insertions, 6534 deletions
diff --git a/arch/arm/configs/am3517_evm_defconfig b/arch/arm/configs/am3517_evm_defconfig deleted file mode 100644 index ad2bc503f2b8..000000000000 --- a/arch/arm/configs/am3517_evm_defconfig +++ /dev/null | |||
| @@ -1,127 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 5 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 6 | CONFIG_BLK_DEV_INITRD=y | ||
| 7 | CONFIG_EMBEDDED=y | ||
| 8 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 9 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 10 | CONFIG_SLAB=y | ||
| 11 | CONFIG_MODULES=y | ||
| 12 | CONFIG_MODULE_UNLOAD=y | ||
| 13 | CONFIG_MODVERSIONS=y | ||
| 14 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 15 | # CONFIG_BLK_DEV_BSG is not set | ||
| 16 | CONFIG_ARCH_OMAP=y | ||
| 17 | CONFIG_ARCH_OMAP3=y | ||
| 18 | CONFIG_OMAP_RESET_CLOCKS=y | ||
| 19 | # CONFIG_OMAP_MCBSP is not set | ||
| 20 | CONFIG_OMAP_32K_TIMER=y | ||
| 21 | CONFIG_OMAP_DM_TIMER=y | ||
| 22 | CONFIG_ARCH_OMAP3430=y | ||
| 23 | CONFIG_MACH_OMAP3517EVM=y | ||
| 24 | CONFIG_NO_HZ=y | ||
| 25 | CONFIG_HIGH_RES_TIMERS=y | ||
| 26 | CONFIG_AEABI=y | ||
| 27 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 28 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 29 | CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" | ||
| 30 | CONFIG_FPE_NWFPE=y | ||
| 31 | CONFIG_VFP=y | ||
| 32 | CONFIG_NEON=y | ||
| 33 | CONFIG_BINFMT_MISC=y | ||
| 34 | CONFIG_NET=y | ||
| 35 | CONFIG_PACKET=y | ||
| 36 | CONFIG_UNIX=y | ||
| 37 | CONFIG_NET_KEY=y | ||
| 38 | CONFIG_INET=y | ||
| 39 | CONFIG_IP_PNP=y | ||
| 40 | CONFIG_IP_PNP_DHCP=y | ||
| 41 | CONFIG_IP_PNP_BOOTP=y | ||
| 42 | CONFIG_IP_PNP_RARP=y | ||
| 43 | # CONFIG_INET_LRO is not set | ||
| 44 | # CONFIG_IPV6 is not set | ||
| 45 | CONFIG_CAN=y | ||
| 46 | CONFIG_CAN_RAW=y | ||
| 47 | CONFIG_CAN_BCM=y | ||
| 48 | CONFIG_CAN_VCAN=y | ||
| 49 | CONFIG_CAN_DEV=y | ||
| 50 | CONFIG_CAN_CALC_BITTIMING=y | ||
| 51 | CONFIG_CAN_TI_HECC=y | ||
| 52 | CONFIG_CAN_DEBUG_DEVICES=y | ||
| 53 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 54 | # CONFIG_FW_LOADER is not set | ||
| 55 | CONFIG_BLK_DEV_LOOP=y | ||
| 56 | CONFIG_BLK_DEV_RAM=y | ||
| 57 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 58 | # CONFIG_MISC_DEVICES is not set | ||
| 59 | CONFIG_SCSI=y | ||
| 60 | CONFIG_BLK_DEV_SD=y | ||
| 61 | CONFIG_NETDEVICES=y | ||
| 62 | CONFIG_NET_ETHERNET=y | ||
| 63 | CONFIG_TI_DAVINCI_EMAC=y | ||
| 64 | # CONFIG_NETDEV_1000 is not set | ||
| 65 | # CONFIG_NETDEV_10000 is not set | ||
| 66 | # CONFIG_WLAN is not set | ||
| 67 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 68 | CONFIG_INPUT_EVDEV=y | ||
| 69 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 70 | # CONFIG_INPUT_MOUSE is not set | ||
| 71 | # CONFIG_SERIO is not set | ||
| 72 | CONFIG_SERIAL_8250=y | ||
| 73 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 74 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 75 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 76 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 77 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 78 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 79 | CONFIG_SERIAL_8250_RSA=y | ||
| 80 | # CONFIG_LEGACY_PTYS is not set | ||
| 81 | CONFIG_HW_RANDOM=y | ||
| 82 | CONFIG_I2C=y | ||
| 83 | CONFIG_I2C_CHARDEV=y | ||
| 84 | CONFIG_I2C_OMAP=y | ||
| 85 | # CONFIG_HWMON is not set | ||
| 86 | CONFIG_FB=y | ||
| 87 | CONFIG_OMAP2_DSS=y | ||
| 88 | CONFIG_OMAP2_VRAM_SIZE=4 | ||
| 89 | CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 | ||
| 90 | CONFIG_FB_OMAP2=y | ||
| 91 | CONFIG_PANEL_GENERIC=y | ||
| 92 | CONFIG_PANEL_SHARP_LQ043T1DG01=y | ||
| 93 | # CONFIG_VGA_CONSOLE is not set | ||
| 94 | CONFIG_USB=y | ||
| 95 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 96 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 97 | CONFIG_USB_EHCI_HCD=y | ||
| 98 | CONFIG_USB_STORAGE=y | ||
| 99 | CONFIG_EXT2_FS=y | ||
| 100 | CONFIG_EXT3_FS=y | ||
| 101 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 102 | CONFIG_INOTIFY=y | ||
| 103 | CONFIG_QUOTA=y | ||
| 104 | CONFIG_QFMT_V2=y | ||
| 105 | CONFIG_MSDOS_FS=y | ||
| 106 | CONFIG_VFAT_FS=y | ||
| 107 | CONFIG_TMPFS=y | ||
| 108 | CONFIG_NFS_FS=y | ||
| 109 | CONFIG_NFS_V3=y | ||
| 110 | CONFIG_NFS_V4=y | ||
| 111 | CONFIG_ROOT_NFS=y | ||
| 112 | CONFIG_PARTITION_ADVANCED=y | ||
| 113 | CONFIG_NLS_CODEPAGE_437=y | ||
| 114 | CONFIG_NLS_ISO8859_1=y | ||
| 115 | CONFIG_MAGIC_SYSRQ=y | ||
| 116 | CONFIG_DEBUG_KERNEL=y | ||
| 117 | # CONFIG_SCHED_DEBUG is not set | ||
| 118 | CONFIG_DEBUG_MUTEXES=y | ||
| 119 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 120 | CONFIG_DEBUG_INFO=y | ||
| 121 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 122 | CONFIG_DEBUG_LL=y | ||
| 123 | CONFIG_CRYPTO_ECB=m | ||
| 124 | CONFIG_CRYPTO_PCBC=m | ||
| 125 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 126 | CONFIG_CRC_CCITT=y | ||
| 127 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/cm_t35_defconfig b/arch/arm/configs/cm_t35_defconfig deleted file mode 100644 index 8bb06334ce9c..000000000000 --- a/arch/arm/configs/cm_t35_defconfig +++ /dev/null | |||
| @@ -1,157 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_IKCONFIG=y | ||
| 5 | CONFIG_IKCONFIG_PROC=y | ||
| 6 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 7 | CONFIG_BLK_DEV_INITRD=y | ||
| 8 | CONFIG_EMBEDDED=y | ||
| 9 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 10 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 11 | CONFIG_SLAB=y | ||
| 12 | CONFIG_MODULES=y | ||
| 13 | CONFIG_MODULE_UNLOAD=y | ||
| 14 | CONFIG_MODVERSIONS=y | ||
| 15 | # CONFIG_BLK_DEV_BSG is not set | ||
| 16 | CONFIG_ARCH_OMAP=y | ||
| 17 | CONFIG_ARCH_OMAP3=y | ||
| 18 | CONFIG_OMAP_RESET_CLOCKS=y | ||
| 19 | CONFIG_OMAP_32K_TIMER=y | ||
| 20 | CONFIG_OMAP_DM_TIMER=y | ||
| 21 | CONFIG_ARCH_OMAP3430=y | ||
| 22 | CONFIG_MACH_CM_T35=y | ||
| 23 | CONFIG_NO_HZ=y | ||
| 24 | CONFIG_HIGH_RES_TIMERS=y | ||
| 25 | CONFIG_AEABI=y | ||
| 26 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 27 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 28 | CONFIG_FPE_NWFPE=y | ||
| 29 | CONFIG_VFP=y | ||
| 30 | CONFIG_NEON=y | ||
| 31 | CONFIG_BINFMT_MISC=y | ||
| 32 | CONFIG_PM=y | ||
| 33 | CONFIG_PM_RUNTIME=y | ||
| 34 | CONFIG_NET=y | ||
| 35 | CONFIG_PACKET=y | ||
| 36 | CONFIG_UNIX=y | ||
| 37 | CONFIG_NET_KEY=y | ||
| 38 | CONFIG_INET=y | ||
| 39 | CONFIG_IP_PNP=y | ||
| 40 | CONFIG_IP_PNP_DHCP=y | ||
| 41 | CONFIG_IP_PNP_BOOTP=y | ||
| 42 | CONFIG_IP_PNP_RARP=y | ||
| 43 | # CONFIG_INET_LRO is not set | ||
| 44 | # CONFIG_IPV6 is not set | ||
| 45 | CONFIG_LIB80211=m | ||
| 46 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 47 | CONFIG_FW_LOADER=m | ||
| 48 | CONFIG_MTD=y | ||
| 49 | CONFIG_MTD_CONCAT=y | ||
| 50 | CONFIG_MTD_PARTITIONS=y | ||
| 51 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 52 | CONFIG_MTD_CHAR=y | ||
| 53 | CONFIG_MTD_BLOCK=y | ||
| 54 | CONFIG_MTD_CFI=y | ||
| 55 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 56 | CONFIG_MTD_NAND=y | ||
| 57 | CONFIG_MTD_NAND_OMAP2=y | ||
| 58 | CONFIG_BLK_DEV_LOOP=y | ||
| 59 | CONFIG_BLK_DEV_RAM=y | ||
| 60 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 61 | CONFIG_SCSI=y | ||
| 62 | CONFIG_BLK_DEV_SD=y | ||
| 63 | CONFIG_NETDEVICES=y | ||
| 64 | CONFIG_NET_ETHERNET=y | ||
| 65 | CONFIG_SMSC911X=y | ||
| 66 | # CONFIG_NETDEV_1000 is not set | ||
| 67 | # CONFIG_NETDEV_10000 is not set | ||
| 68 | CONFIG_INPUT_EVDEV=y | ||
| 69 | CONFIG_KEYBOARD_TWL4030=m | ||
| 70 | # CONFIG_INPUT_MOUSE is not set | ||
| 71 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 72 | CONFIG_TOUCHSCREEN_ADS7846=m | ||
| 73 | CONFIG_SERIAL_8250=y | ||
| 74 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 75 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 76 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 77 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 78 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 79 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 80 | CONFIG_SERIAL_8250_RSA=y | ||
| 81 | # CONFIG_LEGACY_PTYS is not set | ||
| 82 | CONFIG_HW_RANDOM=y | ||
| 83 | CONFIG_I2C=y | ||
| 84 | CONFIG_I2C_CHARDEV=y | ||
| 85 | CONFIG_I2C_OMAP=y | ||
| 86 | CONFIG_SPI=y | ||
| 87 | CONFIG_SPI_OMAP24XX=y | ||
| 88 | CONFIG_GPIO_SYSFS=y | ||
| 89 | CONFIG_GPIO_TWL4030=y | ||
| 90 | # CONFIG_HWMON is not set | ||
| 91 | CONFIG_WATCHDOG=y | ||
| 92 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 93 | CONFIG_OMAP_WATCHDOG=y | ||
| 94 | CONFIG_TWL4030_CORE=y | ||
| 95 | CONFIG_REGULATOR=y | ||
| 96 | CONFIG_REGULATOR_TWL4030=y | ||
| 97 | # CONFIG_VGA_CONSOLE is not set | ||
| 98 | CONFIG_USB=y | ||
| 99 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 100 | CONFIG_USB_DEVICEFS=y | ||
| 101 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 102 | CONFIG_USB_SUSPEND=y | ||
| 103 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 104 | CONFIG_USB_MON=y | ||
| 105 | CONFIG_USB_EHCI_HCD=y | ||
| 106 | CONFIG_USB_MUSB_HDRC=y | ||
| 107 | CONFIG_USB_MUSB_OTG=y | ||
| 108 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 109 | CONFIG_USB_STORAGE=y | ||
| 110 | CONFIG_USB_TEST=y | ||
| 111 | CONFIG_USB_GADGET=y | ||
| 112 | CONFIG_USB_ETH=m | ||
| 113 | CONFIG_TWL4030_USB=y | ||
| 114 | CONFIG_MMC=y | ||
| 115 | CONFIG_MMC_OMAP_HS=y | ||
| 116 | CONFIG_NEW_LEDS=y | ||
| 117 | CONFIG_LEDS_CLASS=y | ||
| 118 | CONFIG_LEDS_GPIO=y | ||
| 119 | CONFIG_LEDS_TRIGGERS=y | ||
| 120 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 121 | CONFIG_RTC_CLASS=y | ||
| 122 | CONFIG_RTC_DRV_TWL4030=y | ||
| 123 | CONFIG_EXT2_FS=y | ||
| 124 | CONFIG_EXT3_FS=y | ||
| 125 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 126 | CONFIG_INOTIFY=y | ||
| 127 | CONFIG_QUOTA=y | ||
| 128 | CONFIG_QFMT_V2=y | ||
| 129 | CONFIG_MSDOS_FS=y | ||
| 130 | CONFIG_VFAT_FS=y | ||
| 131 | CONFIG_NTFS_FS=m | ||
| 132 | CONFIG_TMPFS=y | ||
| 133 | CONFIG_JFFS2_FS=y | ||
| 134 | CONFIG_JFFS2_SUMMARY=y | ||
| 135 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 136 | CONFIG_NFS_FS=y | ||
| 137 | CONFIG_NFS_V3=y | ||
| 138 | CONFIG_NFS_V4=y | ||
| 139 | CONFIG_ROOT_NFS=y | ||
| 140 | CONFIG_PARTITION_ADVANCED=y | ||
| 141 | CONFIG_NLS_CODEPAGE_437=y | ||
| 142 | CONFIG_NLS_ISO8859_1=y | ||
| 143 | CONFIG_NLS_UTF8=m | ||
| 144 | CONFIG_MAGIC_SYSRQ=y | ||
| 145 | CONFIG_DEBUG_FS=y | ||
| 146 | CONFIG_DEBUG_KERNEL=y | ||
| 147 | # CONFIG_SCHED_DEBUG is not set | ||
| 148 | CONFIG_DEBUG_MUTEXES=y | ||
| 149 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 150 | CONFIG_DEBUG_INFO=y | ||
| 151 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 152 | CONFIG_DEBUG_LL=y | ||
| 153 | CONFIG_CRYPTO_ECB=m | ||
| 154 | CONFIG_CRYPTO_PCBC=m | ||
| 155 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 156 | CONFIG_CRC_CCITT=y | ||
| 157 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/devkit8000_defconfig b/arch/arm/configs/devkit8000_defconfig deleted file mode 100644 index 786cbe49528e..000000000000 --- a/arch/arm/configs/devkit8000_defconfig +++ /dev/null | |||
| @@ -1,184 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_IKCONFIG=y | ||
| 5 | CONFIG_IKCONFIG_PROC=y | ||
| 6 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 7 | CONFIG_BLK_DEV_INITRD=y | ||
| 8 | CONFIG_RD_BZIP2=y | ||
| 9 | CONFIG_RD_LZMA=y | ||
| 10 | CONFIG_EMBEDDED=y | ||
| 11 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 12 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 13 | CONFIG_SLAB=y | ||
| 14 | CONFIG_MODULES=y | ||
| 15 | CONFIG_MODULE_FORCE_LOAD=y | ||
| 16 | CONFIG_MODULE_UNLOAD=y | ||
| 17 | CONFIG_MODVERSIONS=y | ||
| 18 | # CONFIG_BLK_DEV_BSG is not set | ||
| 19 | CONFIG_ARCH_OMAP=y | ||
| 20 | CONFIG_ARCH_OMAP3=y | ||
| 21 | CONFIG_OMAP_32K_TIMER=y | ||
| 22 | CONFIG_OMAP_DM_TIMER=y | ||
| 23 | CONFIG_ARCH_OMAP3430=y | ||
| 24 | CONFIG_MACH_DEVKIT8000=y | ||
| 25 | CONFIG_NO_HZ=y | ||
| 26 | CONFIG_HIGH_RES_TIMERS=y | ||
| 27 | CONFIG_AEABI=y | ||
| 28 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 29 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 30 | CONFIG_CMDLINE="console=ttyS2,115200n8 root=/dev/nfs nfsroot=192.168.1.1:home/nfsroot/current,home/nfsroot/current ip=dhcp rw noinitrd root delay=3" | ||
| 31 | CONFIG_FPE_NWFPE=y | ||
| 32 | CONFIG_VFP=y | ||
| 33 | CONFIG_NEON=y | ||
| 34 | CONFIG_PM=y | ||
| 35 | CONFIG_NET=y | ||
| 36 | CONFIG_PACKET=y | ||
| 37 | CONFIG_UNIX=y | ||
| 38 | CONFIG_NET_KEY=y | ||
| 39 | CONFIG_INET=y | ||
| 40 | CONFIG_IP_MULTICAST=y | ||
| 41 | CONFIG_IP_PNP=y | ||
| 42 | CONFIG_IP_PNP_DHCP=y | ||
| 43 | CONFIG_IP_PNP_BOOTP=y | ||
| 44 | CONFIG_IP_PNP_RARP=y | ||
| 45 | # CONFIG_INET_LRO is not set | ||
| 46 | # CONFIG_IPV6 is not set | ||
| 47 | CONFIG_IRDA=y | ||
| 48 | CONFIG_BT=y | ||
| 49 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 50 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
| 51 | # CONFIG_FW_LOADER is not set | ||
| 52 | CONFIG_MTD=y | ||
| 53 | CONFIG_MTD_PARTITIONS=y | ||
| 54 | CONFIG_MTD_CHAR=y | ||
| 55 | CONFIG_MTD_BLOCK=y | ||
| 56 | CONFIG_MTD_RAM=y | ||
| 57 | CONFIG_MTD_ROM=y | ||
| 58 | CONFIG_MTD_NAND=y | ||
| 59 | CONFIG_MTD_NAND_OMAP2=y | ||
| 60 | CONFIG_MTD_UBI=y | ||
| 61 | CONFIG_BLK_DEV_LOOP=y | ||
| 62 | CONFIG_BLK_DEV_RAM=y | ||
| 63 | CONFIG_BLK_DEV_RAM_SIZE=40960 | ||
| 64 | # CONFIG_MISC_DEVICES is not set | ||
| 65 | CONFIG_SCSI=y | ||
| 66 | CONFIG_BLK_DEV_SD=y | ||
| 67 | CONFIG_NETDEVICES=y | ||
| 68 | CONFIG_NET_ETHERNET=y | ||
| 69 | CONFIG_DM9000=y | ||
| 70 | CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y | ||
| 71 | # CONFIG_NETDEV_1000 is not set | ||
| 72 | # CONFIG_NETDEV_10000 is not set | ||
| 73 | # CONFIG_WLAN is not set | ||
| 74 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 75 | CONFIG_INPUT_EVDEV=y | ||
| 76 | CONFIG_KEYBOARD_MATRIX=y | ||
| 77 | CONFIG_KEYBOARD_TWL4030=y | ||
| 78 | # CONFIG_INPUT_MOUSE is not set | ||
| 79 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 80 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 81 | CONFIG_SERIO_RAW=y | ||
| 82 | CONFIG_SERIAL_8250=y | ||
| 83 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 84 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 85 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 86 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 87 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 88 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 89 | CONFIG_SERIAL_8250_RSA=y | ||
| 90 | # CONFIG_LEGACY_PTYS is not set | ||
| 91 | CONFIG_HW_RANDOM=y | ||
| 92 | CONFIG_RAW_DRIVER=y | ||
| 93 | CONFIG_I2C=y | ||
| 94 | CONFIG_I2C_CHARDEV=y | ||
| 95 | CONFIG_I2C_OMAP=y | ||
| 96 | CONFIG_SPI=y | ||
| 97 | CONFIG_SPI_OMAP24XX=y | ||
| 98 | CONFIG_GPIO_TWL4030=y | ||
| 99 | # CONFIG_HWMON is not set | ||
| 100 | CONFIG_TWL4030_CORE=y | ||
| 101 | CONFIG_TWL4030_POWER=y | ||
| 102 | CONFIG_REGULATOR=y | ||
| 103 | CONFIG_REGULATOR_TWL4030=y | ||
| 104 | CONFIG_FB=y | ||
| 105 | CONFIG_FB_FOREIGN_ENDIAN=y | ||
| 106 | CONFIG_FB_OMAP_BOOTLOADER_INIT=y | ||
| 107 | CONFIG_OMAP2_DSS=y | ||
| 108 | CONFIG_FB_OMAP2=y | ||
| 109 | CONFIG_PANEL_GENERIC=y | ||
| 110 | CONFIG_DISPLAY_SUPPORT=y | ||
| 111 | # CONFIG_VGA_CONSOLE is not set | ||
| 112 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 113 | CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y | ||
| 114 | CONFIG_LOGO=y | ||
| 115 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 116 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 117 | CONFIG_SOUND=y | ||
| 118 | CONFIG_SND=y | ||
| 119 | CONFIG_SND_SOC=y | ||
| 120 | CONFIG_SND_OMAP_SOC=y | ||
| 121 | CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE=y | ||
| 122 | CONFIG_USB=y | ||
| 123 | CONFIG_USB_DEBUG=y | ||
| 124 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 125 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 126 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 127 | CONFIG_USB_MON=y | ||
| 128 | CONFIG_USB_EHCI_HCD=y | ||
| 129 | CONFIG_USB_EHCI_ROOT_HUB_TT=y | ||
| 130 | CONFIG_USB_MUSB_HDRC=y | ||
| 131 | CONFIG_USB_MUSB_OTG=y | ||
| 132 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 133 | CONFIG_USB_MUSB_DEBUG=y | ||
| 134 | CONFIG_USB_STORAGE=m | ||
| 135 | CONFIG_USB_GADGET=y | ||
| 136 | CONFIG_USB_GADGET_DEBUG=y | ||
| 137 | CONFIG_USB_ETH=m | ||
| 138 | # CONFIG_USB_ETH_RNDIS is not set | ||
| 139 | CONFIG_TWL4030_USB=y | ||
| 140 | CONFIG_MMC=y | ||
| 141 | CONFIG_MMC_SDHCI=y | ||
| 142 | CONFIG_MMC_SDHCI_PLTFM=m | ||
| 143 | CONFIG_MMC_OMAP_HS=y | ||
| 144 | CONFIG_MMC_SPI=m | ||
| 145 | CONFIG_NEW_LEDS=y | ||
| 146 | CONFIG_LEDS_CLASS=y | ||
| 147 | CONFIG_LEDS_GPIO=y | ||
| 148 | CONFIG_LEDS_TRIGGERS=y | ||
| 149 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 150 | CONFIG_RTC_CLASS=y | ||
| 151 | CONFIG_RTC_DRV_TWL4030=y | ||
| 152 | CONFIG_EXT2_FS=y | ||
| 153 | CONFIG_EXT3_FS=y | ||
| 154 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 155 | CONFIG_INOTIFY=y | ||
| 156 | CONFIG_QUOTA=y | ||
| 157 | CONFIG_QFMT_V2=y | ||
| 158 | CONFIG_MSDOS_FS=y | ||
| 159 | CONFIG_VFAT_FS=y | ||
| 160 | CONFIG_TMPFS=y | ||
| 161 | CONFIG_JFFS2_FS=y | ||
| 162 | CONFIG_UBIFS_FS=y | ||
| 163 | CONFIG_CRAMFS=y | ||
| 164 | CONFIG_NFS_FS=y | ||
| 165 | CONFIG_NFS_V3=y | ||
| 166 | CONFIG_NFS_V4=y | ||
| 167 | CONFIG_ROOT_NFS=y | ||
| 168 | CONFIG_PARTITION_ADVANCED=y | ||
| 169 | CONFIG_NLS_CODEPAGE_437=y | ||
| 170 | CONFIG_NLS_ISO8859_1=y | ||
| 171 | CONFIG_PRINTK_TIME=y | ||
| 172 | CONFIG_MAGIC_SYSRQ=y | ||
| 173 | CONFIG_DEBUG_KERNEL=y | ||
| 174 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y | ||
| 175 | CONFIG_DEBUG_MUTEXES=y | ||
| 176 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 177 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 178 | CONFIG_DEBUG_USER=y | ||
| 179 | CONFIG_DEBUG_ERRORS=y | ||
| 180 | CONFIG_CRYPTO_ECB=m | ||
| 181 | CONFIG_CRYPTO_PCBC=m | ||
| 182 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 183 | CONFIG_CRC_T10DIF=m | ||
| 184 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/igep0020_defconfig b/arch/arm/configs/igep0020_defconfig deleted file mode 100644 index fcda057d5844..000000000000 --- a/arch/arm/configs/igep0020_defconfig +++ /dev/null | |||
| @@ -1,179 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 3 | CONFIG_SYSVIPC=y | ||
| 4 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 5 | CONFIG_BLK_DEV_INITRD=y | ||
| 6 | CONFIG_EMBEDDED=y | ||
| 7 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 8 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 9 | CONFIG_SLAB=y | ||
| 10 | CONFIG_MODULES=y | ||
| 11 | CONFIG_MODULE_UNLOAD=y | ||
| 12 | # CONFIG_BLK_DEV_BSG is not set | ||
| 13 | CONFIG_ARCH_OMAP=y | ||
| 14 | CONFIG_ARCH_OMAP3=y | ||
| 15 | CONFIG_OMAP_RESET_CLOCKS=y | ||
| 16 | # CONFIG_OMAP_MUX is not set | ||
| 17 | CONFIG_OMAP_32K_TIMER=y | ||
| 18 | CONFIG_OMAP_DM_TIMER=y | ||
| 19 | CONFIG_ARCH_OMAP3430=y | ||
| 20 | CONFIG_MACH_IGEP0020=y | ||
| 21 | CONFIG_ARM_THUMBEE=y | ||
| 22 | CONFIG_NO_HZ=y | ||
| 23 | CONFIG_HIGH_RES_TIMERS=y | ||
| 24 | CONFIG_AEABI=y | ||
| 25 | # CONFIG_OABI_COMPAT is not set | ||
| 26 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 27 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 28 | CONFIG_VFP=y | ||
| 29 | CONFIG_NEON=y | ||
| 30 | CONFIG_BINFMT_MISC=y | ||
| 31 | CONFIG_NET=y | ||
| 32 | CONFIG_PACKET=y | ||
| 33 | CONFIG_UNIX=y | ||
| 34 | CONFIG_XFRM_USER=y | ||
| 35 | CONFIG_NET_KEY=y | ||
| 36 | CONFIG_NET_KEY_MIGRATE=y | ||
| 37 | CONFIG_INET=y | ||
| 38 | CONFIG_IP_MULTICAST=y | ||
| 39 | CONFIG_IP_PNP=y | ||
| 40 | CONFIG_IP_PNP_DHCP=y | ||
| 41 | CONFIG_IP_PNP_BOOTP=y | ||
| 42 | CONFIG_IP_PNP_RARP=y | ||
| 43 | # CONFIG_INET_LRO is not set | ||
| 44 | # CONFIG_IPV6 is not set | ||
| 45 | CONFIG_BT=m | ||
| 46 | CONFIG_BT_L2CAP=m | ||
| 47 | CONFIG_BT_SCO=m | ||
| 48 | CONFIG_BT_RFCOMM=m | ||
| 49 | CONFIG_BT_RFCOMM_TTY=y | ||
| 50 | CONFIG_BT_BNEP=m | ||
| 51 | CONFIG_BT_BNEP_MC_FILTER=y | ||
| 52 | CONFIG_BT_BNEP_PROTO_FILTER=y | ||
| 53 | CONFIG_BT_HIDP=m | ||
| 54 | CONFIG_BT_HCIUART=m | ||
| 55 | CONFIG_BT_HCIUART_H4=y | ||
| 56 | CONFIG_BT_HCIUART_BCSP=y | ||
| 57 | CONFIG_BT_HCIUART_LL=y | ||
| 58 | CONFIG_BT_HCIVHCI=m | ||
| 59 | CONFIG_BT_MRVL=m | ||
| 60 | CONFIG_BT_MRVL_SDIO=m | ||
| 61 | CONFIG_CFG80211=y | ||
| 62 | CONFIG_MAC80211=y | ||
| 63 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 64 | # CONFIG_STANDALONE is not set | ||
| 65 | CONFIG_CONNECTOR=y | ||
| 66 | CONFIG_MTD=y | ||
| 67 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 68 | CONFIG_MTD_CHAR=y | ||
| 69 | CONFIG_MTD_BLOCK=y | ||
| 70 | CONFIG_MTD_ONENAND=y | ||
| 71 | CONFIG_MTD_ONENAND_OMAP2=y | ||
| 72 | CONFIG_MTD_ONENAND_2X_PROGRAM=y | ||
| 73 | CONFIG_BLK_DEV_LOOP=y | ||
| 74 | CONFIG_BLK_DEV_RAM=y | ||
| 75 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 76 | # CONFIG_MISC_DEVICES is not set | ||
| 77 | CONFIG_SCSI=y | ||
| 78 | CONFIG_BLK_DEV_SD=y | ||
| 79 | CONFIG_NETDEVICES=y | ||
| 80 | CONFIG_NET_ETHERNET=y | ||
| 81 | CONFIG_SMSC911X=y | ||
| 82 | # CONFIG_NETDEV_1000 is not set | ||
| 83 | # CONFIG_NETDEV_10000 is not set | ||
| 84 | CONFIG_LIBERTAS=y | ||
| 85 | CONFIG_LIBERTAS_SDIO=y | ||
| 86 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 87 | CONFIG_INPUT_EVDEV=y | ||
| 88 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 89 | # CONFIG_INPUT_MOUSE is not set | ||
| 90 | # CONFIG_SERIO is not set | ||
| 91 | CONFIG_SERIAL_8250=y | ||
| 92 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 93 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 94 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 95 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 96 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 97 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 98 | CONFIG_SERIAL_8250_RSA=y | ||
| 99 | # CONFIG_LEGACY_PTYS is not set | ||
| 100 | CONFIG_HW_RANDOM=y | ||
| 101 | CONFIG_I2C=y | ||
| 102 | CONFIG_I2C_CHARDEV=y | ||
| 103 | CONFIG_I2C_OMAP=y | ||
| 104 | CONFIG_SPI=y | ||
| 105 | CONFIG_SPI_OMAP24XX=y | ||
| 106 | CONFIG_GPIO_SYSFS=y | ||
| 107 | CONFIG_GPIO_TWL4030=y | ||
| 108 | CONFIG_POWER_SUPPLY=y | ||
| 109 | # CONFIG_HWMON is not set | ||
| 110 | CONFIG_SSB=m | ||
| 111 | CONFIG_TWL4030_CORE=y | ||
| 112 | CONFIG_REGULATOR=y | ||
| 113 | CONFIG_REGULATOR_TWL4030=y | ||
| 114 | CONFIG_FB=y | ||
| 115 | CONFIG_FB_MODE_HELPERS=y | ||
| 116 | CONFIG_OMAP2_DSS=y | ||
| 117 | CONFIG_OMAP2_VRAM_SIZE=14 | ||
| 118 | # CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set | ||
| 119 | # CONFIG_OMAP2_DSS_VENC is not set | ||
| 120 | CONFIG_OMAP2_DSS_DSI=y | ||
| 121 | CONFIG_OMAP2_DSS_USE_DSI_PLL=y | ||
| 122 | CONFIG_FB_OMAP2=y | ||
| 123 | # CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set | ||
| 124 | CONFIG_PANEL_GENERIC=y | ||
| 125 | CONFIG_DISPLAY_SUPPORT=y | ||
| 126 | # CONFIG_VGA_CONSOLE is not set | ||
| 127 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 128 | CONFIG_LOGO=y | ||
| 129 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 130 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 131 | CONFIG_SOUND=y | ||
| 132 | CONFIG_SND=y | ||
| 133 | # CONFIG_SND_SUPPORT_OLD_API is not set | ||
| 134 | # CONFIG_SND_VERBOSE_PROCFS is not set | ||
| 135 | CONFIG_SND_SOC=y | ||
| 136 | CONFIG_SND_OMAP_SOC=y | ||
| 137 | CONFIG_SND_OMAP_SOC_IGEP0020=y | ||
| 138 | # CONFIG_HID_SUPPORT is not set | ||
| 139 | CONFIG_USB=y | ||
| 140 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 141 | CONFIG_USB_EHCI_HCD=y | ||
| 142 | CONFIG_USB_EHCI_ROOT_HUB_TT=y | ||
| 143 | CONFIG_USB_OHCI_HCD=y | ||
| 144 | CONFIG_MMC=y | ||
| 145 | CONFIG_MMC_DEBUG=y | ||
| 146 | CONFIG_MMC_SDHCI=y | ||
| 147 | CONFIG_MMC_OMAP_HS=y | ||
| 148 | CONFIG_EXT2_FS=y | ||
| 149 | CONFIG_EXT3_FS=y | ||
| 150 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 151 | CONFIG_INOTIFY=y | ||
| 152 | CONFIG_QUOTA=y | ||
| 153 | CONFIG_QFMT_V2=y | ||
| 154 | CONFIG_MSDOS_FS=y | ||
| 155 | CONFIG_VFAT_FS=y | ||
| 156 | CONFIG_TMPFS=y | ||
| 157 | CONFIG_NFS_FS=y | ||
| 158 | CONFIG_NFS_V3=y | ||
| 159 | CONFIG_NFS_V3_ACL=y | ||
| 160 | CONFIG_NFS_V4=y | ||
| 161 | CONFIG_ROOT_NFS=y | ||
| 162 | CONFIG_PARTITION_ADVANCED=y | ||
| 163 | CONFIG_NLS_CODEPAGE_437=y | ||
| 164 | CONFIG_NLS_ISO8859_1=y | ||
| 165 | CONFIG_PRINTK_TIME=y | ||
| 166 | CONFIG_MAGIC_SYSRQ=y | ||
| 167 | CONFIG_DEBUG_KERNEL=y | ||
| 168 | CONFIG_DEBUG_MUTEXES=y | ||
| 169 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 170 | CONFIG_DEBUG_INFO=y | ||
| 171 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 172 | CONFIG_DEBUG_LL=y | ||
| 173 | CONFIG_CRYPTO_PCBC=m | ||
| 174 | CONFIG_CRYPTO_MICHAEL_MIC=m | ||
| 175 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 176 | CONFIG_CRC_CCITT=y | ||
| 177 | CONFIG_CRC_T10DIF=y | ||
| 178 | CONFIG_CRC_ITU_T=m | ||
| 179 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/omap3_beagle_defconfig b/arch/arm/configs/omap3_beagle_defconfig deleted file mode 100644 index aa24172a3e2c..000000000000 --- a/arch/arm/configs/omap3_beagle_defconfig +++ /dev/null | |||
| @@ -1,134 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 5 | CONFIG_BLK_DEV_INITRD=y | ||
| 6 | CONFIG_EMBEDDED=y | ||
| 7 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 8 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 9 | CONFIG_SLAB=y | ||
| 10 | CONFIG_MODULES=y | ||
| 11 | CONFIG_MODULE_UNLOAD=y | ||
| 12 | CONFIG_MODVERSIONS=y | ||
| 13 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 14 | # CONFIG_BLK_DEV_BSG is not set | ||
| 15 | CONFIG_ARCH_OMAP=y | ||
| 16 | CONFIG_ARCH_OMAP3=y | ||
| 17 | # CONFIG_OMAP_MUX is not set | ||
| 18 | # CONFIG_OMAP_MCBSP is not set | ||
| 19 | CONFIG_OMAP_32K_TIMER=y | ||
| 20 | CONFIG_OMAP_DM_TIMER=y | ||
| 21 | CONFIG_ARCH_OMAP3430=y | ||
| 22 | CONFIG_MACH_OMAP3_BEAGLE=y | ||
| 23 | CONFIG_NO_HZ=y | ||
| 24 | CONFIG_HIGH_RES_TIMERS=y | ||
| 25 | CONFIG_AEABI=y | ||
| 26 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 27 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 28 | CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" | ||
| 29 | CONFIG_FPE_NWFPE=y | ||
| 30 | CONFIG_VFP=y | ||
| 31 | CONFIG_BINFMT_MISC=y | ||
| 32 | CONFIG_PM=y | ||
| 33 | CONFIG_PM_RUNTIME=y | ||
| 34 | CONFIG_NET=y | ||
| 35 | CONFIG_PACKET=y | ||
| 36 | CONFIG_UNIX=y | ||
| 37 | CONFIG_NET_KEY=y | ||
| 38 | CONFIG_INET=y | ||
| 39 | CONFIG_IP_PNP=y | ||
| 40 | CONFIG_IP_PNP_DHCP=y | ||
| 41 | CONFIG_IP_PNP_BOOTP=y | ||
| 42 | CONFIG_IP_PNP_RARP=y | ||
| 43 | # CONFIG_INET_LRO is not set | ||
| 44 | # CONFIG_IPV6 is not set | ||
| 45 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 46 | # CONFIG_FW_LOADER is not set | ||
| 47 | CONFIG_MTD=y | ||
| 48 | CONFIG_MTD_PARTITIONS=y | ||
| 49 | CONFIG_MTD_CHAR=y | ||
| 50 | CONFIG_MTD_BLOCK=y | ||
| 51 | CONFIG_MTD_NAND=y | ||
| 52 | CONFIG_BLK_DEV_LOOP=y | ||
| 53 | CONFIG_BLK_DEV_RAM=y | ||
| 54 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 55 | # CONFIG_MISC_DEVICES is not set | ||
| 56 | CONFIG_SCSI=y | ||
| 57 | CONFIG_BLK_DEV_SD=y | ||
| 58 | CONFIG_NETDEVICES=y | ||
| 59 | # CONFIG_NETDEV_1000 is not set | ||
| 60 | # CONFIG_NETDEV_10000 is not set | ||
| 61 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 62 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 63 | # CONFIG_INPUT_MOUSE is not set | ||
| 64 | # CONFIG_SERIO is not set | ||
| 65 | CONFIG_SERIAL_8250=y | ||
| 66 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 67 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 68 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 69 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 70 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 71 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 72 | CONFIG_SERIAL_8250_RSA=y | ||
| 73 | # CONFIG_LEGACY_PTYS is not set | ||
| 74 | CONFIG_HW_RANDOM=y | ||
| 75 | CONFIG_I2C=y | ||
| 76 | CONFIG_I2C_CHARDEV=y | ||
| 77 | CONFIG_I2C_OMAP=y | ||
| 78 | CONFIG_GPIO_TWL4030=y | ||
| 79 | # CONFIG_HWMON is not set | ||
| 80 | CONFIG_TWL4030_CORE=y | ||
| 81 | CONFIG_REGULATOR=y | ||
| 82 | CONFIG_REGULATOR_TWL4030=y | ||
| 83 | CONFIG_FB=y | ||
| 84 | CONFIG_FB_OMAP=y | ||
| 85 | # CONFIG_VGA_CONSOLE is not set | ||
| 86 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 87 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y | ||
| 88 | CONFIG_FONTS=y | ||
| 89 | CONFIG_FONT_8x8=y | ||
| 90 | CONFIG_FONT_8x16=y | ||
| 91 | # CONFIG_HID_SUPPORT is not set | ||
| 92 | CONFIG_USB=y | ||
| 93 | CONFIG_USB_DEVICEFS=y | ||
| 94 | CONFIG_USB_SUSPEND=y | ||
| 95 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 96 | CONFIG_USB_MON=y | ||
| 97 | CONFIG_USB_EHCI_HCD=y | ||
| 98 | CONFIG_USB_EHCI_ROOT_HUB_TT=y | ||
| 99 | CONFIG_USB_MUSB_HDRC=y | ||
| 100 | CONFIG_USB_MUSB_OTG=y | ||
| 101 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 102 | CONFIG_USB_GADGET=y | ||
| 103 | CONFIG_USB_ETH=m | ||
| 104 | CONFIG_TWL4030_USB=y | ||
| 105 | CONFIG_MMC=y | ||
| 106 | CONFIG_MMC_OMAP_HS=y | ||
| 107 | CONFIG_RTC_CLASS=y | ||
| 108 | CONFIG_EXT2_FS=y | ||
| 109 | CONFIG_EXT3_FS=y | ||
| 110 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 111 | CONFIG_INOTIFY=y | ||
| 112 | CONFIG_QUOTA=y | ||
| 113 | CONFIG_QFMT_V2=y | ||
| 114 | CONFIG_MSDOS_FS=y | ||
| 115 | CONFIG_VFAT_FS=y | ||
| 116 | CONFIG_TMPFS=y | ||
| 117 | CONFIG_JFFS2_FS=y | ||
| 118 | CONFIG_NFS_FS=y | ||
| 119 | CONFIG_NFS_V3=y | ||
| 120 | CONFIG_NFS_V4=y | ||
| 121 | CONFIG_ROOT_NFS=y | ||
| 122 | CONFIG_PARTITION_ADVANCED=y | ||
| 123 | CONFIG_NLS_CODEPAGE_437=y | ||
| 124 | CONFIG_NLS_ISO8859_1=y | ||
| 125 | CONFIG_MAGIC_SYSRQ=y | ||
| 126 | CONFIG_DEBUG_KERNEL=y | ||
| 127 | CONFIG_DEBUG_MUTEXES=y | ||
| 128 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 129 | CONFIG_DEBUG_INFO=y | ||
| 130 | # CONFIG_FTRACE is not set | ||
| 131 | CONFIG_CRYPTO_ECB=m | ||
| 132 | CONFIG_CRYPTO_PCBC=m | ||
| 133 | CONFIG_CRC_CCITT=y | ||
| 134 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/omap3_evm_defconfig b/arch/arm/configs/omap3_evm_defconfig deleted file mode 100644 index 3b072e8e71fb..000000000000 --- a/arch/arm/configs/omap3_evm_defconfig +++ /dev/null | |||
| @@ -1,160 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 5 | CONFIG_BLK_DEV_INITRD=y | ||
| 6 | CONFIG_EMBEDDED=y | ||
| 7 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 8 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 9 | CONFIG_SLAB=y | ||
| 10 | CONFIG_MODULES=y | ||
| 11 | CONFIG_MODULE_UNLOAD=y | ||
| 12 | CONFIG_MODVERSIONS=y | ||
| 13 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 14 | # CONFIG_BLK_DEV_BSG is not set | ||
| 15 | CONFIG_ARCH_OMAP=y | ||
| 16 | CONFIG_ARCH_OMAP3=y | ||
| 17 | CONFIG_OMAP_RESET_CLOCKS=y | ||
| 18 | # CONFIG_OMAP_MCBSP is not set | ||
| 19 | CONFIG_OMAP_32K_TIMER=y | ||
| 20 | CONFIG_OMAP_DM_TIMER=y | ||
| 21 | CONFIG_ARCH_OMAP3430=y | ||
| 22 | CONFIG_MACH_OMAP3EVM=y | ||
| 23 | CONFIG_NO_HZ=y | ||
| 24 | CONFIG_HIGH_RES_TIMERS=y | ||
| 25 | CONFIG_AEABI=y | ||
| 26 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 27 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 28 | CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" | ||
| 29 | CONFIG_FPE_NWFPE=y | ||
| 30 | CONFIG_VFP=y | ||
| 31 | CONFIG_NEON=y | ||
| 32 | CONFIG_BINFMT_MISC=y | ||
| 33 | CONFIG_PM=y | ||
| 34 | CONFIG_PM_DEBUG=y | ||
| 35 | CONFIG_PM_RUNTIME=y | ||
| 36 | CONFIG_NET=y | ||
| 37 | CONFIG_PACKET=y | ||
| 38 | CONFIG_UNIX=y | ||
| 39 | CONFIG_NET_KEY=y | ||
| 40 | CONFIG_INET=y | ||
| 41 | CONFIG_IP_PNP=y | ||
| 42 | CONFIG_IP_PNP_DHCP=y | ||
| 43 | CONFIG_IP_PNP_BOOTP=y | ||
| 44 | CONFIG_IP_PNP_RARP=y | ||
| 45 | # CONFIG_INET_LRO is not set | ||
| 46 | # CONFIG_IPV6 is not set | ||
| 47 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 48 | # CONFIG_FW_LOADER is not set | ||
| 49 | CONFIG_MTD=y | ||
| 50 | CONFIG_MTD_CONCAT=y | ||
| 51 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 52 | CONFIG_MTD_CHAR=y | ||
| 53 | CONFIG_MTD_BLOCK=y | ||
| 54 | CONFIG_MTD_CFI=y | ||
| 55 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 56 | CONFIG_MTD_NAND=y | ||
| 57 | CONFIG_MTD_ONENAND=y | ||
| 58 | CONFIG_MTD_ONENAND_VERIFY_WRITE=y | ||
| 59 | CONFIG_MTD_ONENAND_OMAP2=y | ||
| 60 | CONFIG_BLK_DEV_LOOP=y | ||
| 61 | CONFIG_BLK_DEV_RAM=y | ||
| 62 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 63 | # CONFIG_MISC_DEVICES is not set | ||
| 64 | CONFIG_SCSI=y | ||
| 65 | CONFIG_BLK_DEV_SD=y | ||
| 66 | CONFIG_NETDEVICES=y | ||
| 67 | CONFIG_NET_ETHERNET=y | ||
| 68 | CONFIG_SMSC911X=y | ||
| 69 | # CONFIG_NETDEV_1000 is not set | ||
| 70 | # CONFIG_NETDEV_10000 is not set | ||
| 71 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 72 | CONFIG_INPUT_EVDEV=y | ||
| 73 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 74 | CONFIG_KEYBOARD_TWL4030=y | ||
| 75 | # CONFIG_INPUT_MOUSE is not set | ||
| 76 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 77 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 78 | # CONFIG_SERIO is not set | ||
| 79 | CONFIG_SERIAL_8250=y | ||
| 80 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 81 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 82 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 83 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 84 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 85 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 86 | CONFIG_SERIAL_8250_RSA=y | ||
| 87 | # CONFIG_LEGACY_PTYS is not set | ||
| 88 | CONFIG_HW_RANDOM=y | ||
| 89 | CONFIG_I2C=y | ||
| 90 | CONFIG_I2C_CHARDEV=y | ||
| 91 | CONFIG_I2C_OMAP=y | ||
| 92 | CONFIG_SPI=y | ||
| 93 | CONFIG_SPI_OMAP24XX=y | ||
| 94 | CONFIG_GPIO_TWL4030=y | ||
| 95 | # CONFIG_HWMON is not set | ||
| 96 | CONFIG_WATCHDOG=y | ||
| 97 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 98 | CONFIG_OMAP_WATCHDOG=y | ||
| 99 | CONFIG_TWL4030_CORE=y | ||
| 100 | CONFIG_REGULATOR=y | ||
| 101 | CONFIG_REGULATOR_TWL4030=y | ||
| 102 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 103 | CONFIG_FB=y | ||
| 104 | CONFIG_OMAP2_DSS=y | ||
| 105 | CONFIG_OMAP2_VRAM_SIZE=4 | ||
| 106 | # CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set | ||
| 107 | CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 | ||
| 108 | CONFIG_FB_OMAP2=y | ||
| 109 | # CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set | ||
| 110 | CONFIG_PANEL_GENERIC=y | ||
| 111 | CONFIG_PANEL_SHARP_LS037V7DW01=y | ||
| 112 | # CONFIG_VGA_CONSOLE is not set | ||
| 113 | CONFIG_USB=y | ||
| 114 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 115 | CONFIG_USB_DEVICEFS=y | ||
| 116 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 117 | CONFIG_USB_SUSPEND=y | ||
| 118 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 119 | CONFIG_USB_MON=y | ||
| 120 | CONFIG_USB_MUSB_HDRC=y | ||
| 121 | CONFIG_USB_MUSB_OTG=y | ||
| 122 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 123 | CONFIG_USB_STORAGE=y | ||
| 124 | CONFIG_USB_TEST=y | ||
| 125 | CONFIG_USB_GADGET=y | ||
| 126 | CONFIG_USB_ZERO=m | ||
| 127 | CONFIG_MMC=y | ||
| 128 | CONFIG_MMC_OMAP_HS=y | ||
| 129 | CONFIG_EXT2_FS=y | ||
| 130 | CONFIG_EXT3_FS=y | ||
| 131 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 132 | CONFIG_INOTIFY=y | ||
| 133 | CONFIG_QUOTA=y | ||
| 134 | CONFIG_QFMT_V2=y | ||
| 135 | CONFIG_MSDOS_FS=y | ||
| 136 | CONFIG_VFAT_FS=y | ||
| 137 | CONFIG_TMPFS=y | ||
| 138 | CONFIG_JFFS2_FS=y | ||
| 139 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 140 | CONFIG_NFS_FS=y | ||
| 141 | CONFIG_NFS_V3=y | ||
| 142 | CONFIG_NFS_V4=y | ||
| 143 | CONFIG_ROOT_NFS=y | ||
| 144 | CONFIG_PARTITION_ADVANCED=y | ||
| 145 | CONFIG_NLS_CODEPAGE_437=y | ||
| 146 | CONFIG_NLS_ISO8859_1=y | ||
| 147 | CONFIG_MAGIC_SYSRQ=y | ||
| 148 | CONFIG_DEBUG_FS=y | ||
| 149 | CONFIG_DEBUG_KERNEL=y | ||
| 150 | # CONFIG_SCHED_DEBUG is not set | ||
| 151 | CONFIG_DEBUG_MUTEXES=y | ||
| 152 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 153 | CONFIG_DEBUG_INFO=y | ||
| 154 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 155 | CONFIG_DEBUG_LL=y | ||
| 156 | CONFIG_CRYPTO_ECB=m | ||
| 157 | CONFIG_CRYPTO_PCBC=m | ||
| 158 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 159 | CONFIG_CRC_CCITT=y | ||
| 160 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/omap3_pandora_defconfig b/arch/arm/configs/omap3_pandora_defconfig deleted file mode 100644 index d5a622689370..000000000000 --- a/arch/arm/configs/omap3_pandora_defconfig +++ /dev/null | |||
| @@ -1,158 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_IKCONFIG=y | ||
| 5 | CONFIG_IKCONFIG_PROC=y | ||
| 6 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 7 | CONFIG_BLK_DEV_INITRD=y | ||
| 8 | CONFIG_EMBEDDED=y | ||
| 9 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 10 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 11 | CONFIG_SLAB=y | ||
| 12 | CONFIG_MODULES=y | ||
| 13 | CONFIG_MODULE_UNLOAD=y | ||
| 14 | CONFIG_MODVERSIONS=y | ||
| 15 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 16 | # CONFIG_BLK_DEV_BSG is not set | ||
| 17 | CONFIG_ARCH_OMAP=y | ||
| 18 | CONFIG_ARCH_OMAP3=y | ||
| 19 | # CONFIG_OMAP_MUX is not set | ||
| 20 | CONFIG_OMAP_32K_TIMER=y | ||
| 21 | CONFIG_OMAP_DM_TIMER=y | ||
| 22 | CONFIG_ARCH_OMAP3430=y | ||
| 23 | CONFIG_MACH_OMAP3_PANDORA=y | ||
| 24 | CONFIG_ARM_THUMBEE=y | ||
| 25 | CONFIG_NO_HZ=y | ||
| 26 | CONFIG_HIGH_RES_TIMERS=y | ||
| 27 | CONFIG_PREEMPT_VOLUNTARY=y | ||
| 28 | CONFIG_AEABI=y | ||
| 29 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 30 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 31 | CONFIG_CMDLINE=" debug " | ||
| 32 | CONFIG_FPE_NWFPE=y | ||
| 33 | CONFIG_VFP=y | ||
| 34 | CONFIG_NEON=y | ||
| 35 | CONFIG_BINFMT_MISC=y | ||
| 36 | CONFIG_NET=y | ||
| 37 | CONFIG_PACKET=y | ||
| 38 | CONFIG_UNIX=y | ||
| 39 | CONFIG_NET_KEY=y | ||
| 40 | CONFIG_INET=y | ||
| 41 | CONFIG_IP_PNP=y | ||
| 42 | CONFIG_IP_PNP_DHCP=y | ||
| 43 | CONFIG_IP_PNP_BOOTP=y | ||
| 44 | CONFIG_IP_PNP_RARP=y | ||
| 45 | # CONFIG_INET_LRO is not set | ||
| 46 | # CONFIG_IPV6 is not set | ||
| 47 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 48 | CONFIG_DEVTMPFS=y | ||
| 49 | CONFIG_DEVTMPFS_MOUNT=y | ||
| 50 | # CONFIG_FW_LOADER is not set | ||
| 51 | CONFIG_MTD=y | ||
| 52 | CONFIG_MTD_PARTITIONS=y | ||
| 53 | CONFIG_MTD_CHAR=y | ||
| 54 | CONFIG_MTD_BLOCK=y | ||
| 55 | CONFIG_MTD_NAND=y | ||
| 56 | CONFIG_MTD_NAND_OMAP2=y | ||
| 57 | CONFIG_BLK_DEV_LOOP=y | ||
| 58 | CONFIG_BLK_DEV_RAM=y | ||
| 59 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 60 | CONFIG_SCSI=y | ||
| 61 | CONFIG_BLK_DEV_SD=y | ||
| 62 | CONFIG_NETDEVICES=y | ||
| 63 | # CONFIG_NETDEV_1000 is not set | ||
| 64 | # CONFIG_NETDEV_10000 is not set | ||
| 65 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=800 | ||
| 66 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 | ||
| 67 | CONFIG_INPUT_JOYDEV=y | ||
| 68 | CONFIG_INPUT_EVDEV=y | ||
| 69 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 70 | CONFIG_KEYBOARD_GPIO=y | ||
| 71 | CONFIG_KEYBOARD_TWL4030=y | ||
| 72 | # CONFIG_MOUSE_PS2 is not set | ||
| 73 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 74 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 75 | CONFIG_INPUT_MISC=y | ||
| 76 | CONFIG_INPUT_TWL4030_PWRBUTTON=y | ||
| 77 | # CONFIG_SERIO is not set | ||
| 78 | CONFIG_SERIAL_8250=y | ||
| 79 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 80 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 81 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 82 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 83 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 84 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 85 | CONFIG_SERIAL_8250_RSA=y | ||
| 86 | # CONFIG_LEGACY_PTYS is not set | ||
| 87 | CONFIG_HW_RANDOM=y | ||
| 88 | CONFIG_I2C=y | ||
| 89 | CONFIG_I2C_CHARDEV=y | ||
| 90 | CONFIG_I2C_OMAP=y | ||
| 91 | CONFIG_SPI=y | ||
| 92 | CONFIG_SPI_OMAP24XX=y | ||
| 93 | CONFIG_GPIO_TWL4030=y | ||
| 94 | # CONFIG_HWMON is not set | ||
| 95 | CONFIG_TWL4030_CORE=y | ||
| 96 | CONFIG_TWL4030_POWER=y | ||
| 97 | CONFIG_REGULATOR=y | ||
| 98 | CONFIG_REGULATOR_DEBUG=y | ||
| 99 | CONFIG_REGULATOR_TWL4030=y | ||
| 100 | CONFIG_VIDEO_OUTPUT_CONTROL=y | ||
| 101 | CONFIG_FB=y | ||
| 102 | CONFIG_OMAP2_DSS=y | ||
| 103 | CONFIG_FB_OMAP2=y | ||
| 104 | CONFIG_PANEL_TPO_TD043MTEA1=y | ||
| 105 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 106 | # CONFIG_LCD_CLASS_DEVICE is not set | ||
| 107 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
| 108 | # CONFIG_VGA_CONSOLE is not set | ||
| 109 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 110 | CONFIG_LOGO=y | ||
| 111 | CONFIG_SOUND=y | ||
| 112 | CONFIG_SND=y | ||
| 113 | CONFIG_SND_MIXER_OSS=y | ||
| 114 | CONFIG_SND_PCM_OSS=y | ||
| 115 | CONFIG_SND_VERBOSE_PRINTK=y | ||
| 116 | CONFIG_SND_SOC=y | ||
| 117 | CONFIG_SND_OMAP_SOC=y | ||
| 118 | CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y | ||
| 119 | CONFIG_USB=y | ||
| 120 | CONFIG_USB_DEVICEFS=y | ||
| 121 | CONFIG_USB_EHCI_HCD=y | ||
| 122 | CONFIG_USB_MUSB_HDRC=y | ||
| 123 | CONFIG_USB_MUSB_PERIPHERAL=y | ||
| 124 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 125 | CONFIG_USB_GADGET=y | ||
| 126 | CONFIG_USB_ETH=m | ||
| 127 | CONFIG_TWL4030_USB=y | ||
| 128 | CONFIG_MMC=y | ||
| 129 | CONFIG_MMC_OMAP_HS=y | ||
| 130 | CONFIG_NEW_LEDS=y | ||
| 131 | CONFIG_LEDS_CLASS=y | ||
| 132 | CONFIG_LEDS_GPIO=y | ||
| 133 | CONFIG_LEDS_TRIGGERS=y | ||
| 134 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | ||
| 135 | CONFIG_RTC_CLASS=y | ||
| 136 | CONFIG_RTC_DRV_TWL4030=y | ||
| 137 | CONFIG_EXT2_FS=y | ||
| 138 | CONFIG_EXT3_FS=y | ||
| 139 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 140 | CONFIG_QUOTA=y | ||
| 141 | CONFIG_QFMT_V2=y | ||
| 142 | CONFIG_MSDOS_FS=y | ||
| 143 | CONFIG_VFAT_FS=y | ||
| 144 | CONFIG_TMPFS=y | ||
| 145 | CONFIG_CIFS=y | ||
| 146 | CONFIG_PARTITION_ADVANCED=y | ||
| 147 | CONFIG_NLS_CODEPAGE_437=y | ||
| 148 | CONFIG_NLS_ISO8859_1=y | ||
| 149 | CONFIG_MAGIC_SYSRQ=y | ||
| 150 | CONFIG_DEBUG_KERNEL=y | ||
| 151 | CONFIG_DEBUG_MUTEXES=y | ||
| 152 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 153 | CONFIG_DEBUG_INFO=y | ||
| 154 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 155 | CONFIG_CRYPTO_CRC32C=y | ||
| 156 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 157 | # CONFIG_CRYPTO_HW is not set | ||
| 158 | CONFIG_CRC_CCITT=y | ||
diff --git a/arch/arm/configs/omap3_stalker_lks_defconfig b/arch/arm/configs/omap3_stalker_lks_defconfig deleted file mode 100644 index 1d1ab0b0b71c..000000000000 --- a/arch/arm/configs/omap3_stalker_lks_defconfig +++ /dev/null | |||
| @@ -1,150 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 5 | CONFIG_BLK_DEV_INITRD=y | ||
| 6 | CONFIG_EMBEDDED=y | ||
| 7 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 8 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 9 | CONFIG_SLAB=y | ||
| 10 | CONFIG_MODULES=y | ||
| 11 | CONFIG_MODULE_UNLOAD=y | ||
| 12 | CONFIG_MODVERSIONS=y | ||
| 13 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 14 | # CONFIG_BLK_DEV_BSG is not set | ||
| 15 | CONFIG_ARCH_OMAP=y | ||
| 16 | CONFIG_ARCH_OMAP3=y | ||
| 17 | CONFIG_OMAP_RESET_CLOCKS=y | ||
| 18 | # CONFIG_OMAP_MCBSP is not set | ||
| 19 | CONFIG_OMAP_32K_TIMER=y | ||
| 20 | CONFIG_OMAP_DM_TIMER=y | ||
| 21 | CONFIG_ARCH_OMAP3430=y | ||
| 22 | CONFIG_MACH_SBC3530=y | ||
| 23 | CONFIG_NO_HZ=y | ||
| 24 | CONFIG_HIGH_RES_TIMERS=y | ||
| 25 | CONFIG_AEABI=y | ||
| 26 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 27 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 28 | CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" | ||
| 29 | CONFIG_FPE_NWFPE=y | ||
| 30 | CONFIG_VFP=y | ||
| 31 | CONFIG_NEON=y | ||
| 32 | CONFIG_BINFMT_MISC=y | ||
| 33 | CONFIG_PM=y | ||
| 34 | CONFIG_PM_DEBUG=y | ||
| 35 | CONFIG_NET=y | ||
| 36 | CONFIG_PACKET=y | ||
| 37 | CONFIG_UNIX=y | ||
| 38 | CONFIG_NET_KEY=y | ||
| 39 | CONFIG_INET=y | ||
| 40 | CONFIG_IP_PNP=y | ||
| 41 | CONFIG_IP_PNP_DHCP=y | ||
| 42 | CONFIG_IP_PNP_BOOTP=y | ||
| 43 | CONFIG_IP_PNP_RARP=y | ||
| 44 | # CONFIG_INET_LRO is not set | ||
| 45 | # CONFIG_IPV6 is not set | ||
| 46 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 47 | # CONFIG_FW_LOADER is not set | ||
| 48 | CONFIG_MTD=y | ||
| 49 | CONFIG_MTD_CONCAT=y | ||
| 50 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 51 | CONFIG_MTD_CHAR=y | ||
| 52 | CONFIG_MTD_BLOCK=y | ||
| 53 | CONFIG_MTD_CFI=y | ||
| 54 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 55 | CONFIG_MTD_NAND=y | ||
| 56 | CONFIG_MTD_ONENAND=y | ||
| 57 | CONFIG_MTD_ONENAND_VERIFY_WRITE=y | ||
| 58 | CONFIG_MTD_ONENAND_OMAP2=y | ||
| 59 | CONFIG_BLK_DEV_LOOP=y | ||
| 60 | CONFIG_BLK_DEV_RAM=y | ||
| 61 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 62 | # CONFIG_MISC_DEVICES is not set | ||
| 63 | CONFIG_SCSI=y | ||
| 64 | CONFIG_BLK_DEV_SD=y | ||
| 65 | CONFIG_NETDEVICES=y | ||
| 66 | CONFIG_NET_ETHERNET=y | ||
| 67 | CONFIG_SMSC911X=y | ||
| 68 | # CONFIG_NETDEV_1000 is not set | ||
| 69 | # CONFIG_NETDEV_10000 is not set | ||
| 70 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 71 | CONFIG_INPUT_EVDEV=y | ||
| 72 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 73 | CONFIG_KEYBOARD_TWL4030=y | ||
| 74 | # CONFIG_INPUT_MOUSE is not set | ||
| 75 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 76 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 77 | # CONFIG_SERIO is not set | ||
| 78 | CONFIG_SERIAL_8250=y | ||
| 79 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 80 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 81 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 82 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 83 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 84 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 85 | CONFIG_SERIAL_8250_RSA=y | ||
| 86 | # CONFIG_LEGACY_PTYS is not set | ||
| 87 | CONFIG_HW_RANDOM=y | ||
| 88 | CONFIG_I2C=y | ||
| 89 | CONFIG_I2C_CHARDEV=y | ||
| 90 | CONFIG_I2C_OMAP=y | ||
| 91 | CONFIG_SPI=y | ||
| 92 | CONFIG_SPI_OMAP24XX=y | ||
| 93 | CONFIG_GPIO_TWL4030=y | ||
| 94 | # CONFIG_HWMON is not set | ||
| 95 | CONFIG_WATCHDOG=y | ||
| 96 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 97 | CONFIG_OMAP_WATCHDOG=y | ||
| 98 | CONFIG_TWL4030_CORE=y | ||
| 99 | CONFIG_REGULATOR=y | ||
| 100 | CONFIG_REGULATOR_TWL4030=y | ||
| 101 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 102 | # CONFIG_VGA_CONSOLE is not set | ||
| 103 | CONFIG_USB=y | ||
| 104 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 105 | CONFIG_USB_DEVICEFS=y | ||
| 106 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 107 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 108 | CONFIG_USB_MON=y | ||
| 109 | CONFIG_USB_MUSB_HDRC=y | ||
| 110 | CONFIG_USB_MUSB_OTG=y | ||
| 111 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 112 | CONFIG_USB_STORAGE=y | ||
| 113 | CONFIG_USB_TEST=y | ||
| 114 | CONFIG_USB_GADGET=y | ||
| 115 | CONFIG_USB_ZERO=m | ||
| 116 | CONFIG_TWL4030_USB=y | ||
| 117 | CONFIG_MMC=y | ||
| 118 | CONFIG_MMC_OMAP_HS=y | ||
| 119 | CONFIG_EXT2_FS=y | ||
| 120 | CONFIG_EXT3_FS=y | ||
| 121 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 122 | CONFIG_INOTIFY=y | ||
| 123 | CONFIG_QUOTA=y | ||
| 124 | CONFIG_QFMT_V2=y | ||
| 125 | CONFIG_MSDOS_FS=y | ||
| 126 | CONFIG_VFAT_FS=y | ||
| 127 | CONFIG_TMPFS=y | ||
| 128 | CONFIG_JFFS2_FS=y | ||
| 129 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 130 | CONFIG_NFS_FS=y | ||
| 131 | CONFIG_NFS_V3=y | ||
| 132 | CONFIG_NFS_V4=y | ||
| 133 | CONFIG_ROOT_NFS=y | ||
| 134 | CONFIG_PARTITION_ADVANCED=y | ||
| 135 | CONFIG_NLS_CODEPAGE_437=y | ||
| 136 | CONFIG_NLS_ISO8859_1=y | ||
| 137 | CONFIG_MAGIC_SYSRQ=y | ||
| 138 | CONFIG_DEBUG_FS=y | ||
| 139 | CONFIG_DEBUG_KERNEL=y | ||
| 140 | # CONFIG_SCHED_DEBUG is not set | ||
| 141 | CONFIG_DEBUG_MUTEXES=y | ||
| 142 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 143 | CONFIG_DEBUG_INFO=y | ||
| 144 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 145 | CONFIG_DEBUG_LL=y | ||
| 146 | CONFIG_CRYPTO_ECB=m | ||
| 147 | CONFIG_CRYPTO_PCBC=m | ||
| 148 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 149 | CONFIG_CRC_CCITT=y | ||
| 150 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/omap3_touchbook_defconfig b/arch/arm/configs/omap3_touchbook_defconfig deleted file mode 100644 index e988eccc93a8..000000000000 --- a/arch/arm/configs/omap3_touchbook_defconfig +++ /dev/null | |||
| @@ -1,621 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 3 | CONFIG_SYSVIPC=y | ||
| 4 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 5 | CONFIG_TASKSTATS=y | ||
| 6 | CONFIG_TASK_DELAY_ACCT=y | ||
| 7 | CONFIG_TASK_XACCT=y | ||
| 8 | CONFIG_TASK_IO_ACCOUNTING=y | ||
| 9 | CONFIG_IKCONFIG=y | ||
| 10 | CONFIG_IKCONFIG_PROC=y | ||
| 11 | CONFIG_LOG_BUF_SHIFT=15 | ||
| 12 | CONFIG_BLK_DEV_INITRD=y | ||
| 13 | CONFIG_EMBEDDED=y | ||
| 14 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 15 | # CONFIG_ELF_CORE is not set | ||
| 16 | # CONFIG_COMPAT_BRK is not set | ||
| 17 | CONFIG_SLAB=y | ||
| 18 | CONFIG_PROFILING=y | ||
| 19 | CONFIG_OPROFILE=y | ||
| 20 | CONFIG_MODULES=y | ||
| 21 | CONFIG_MODULE_FORCE_LOAD=y | ||
| 22 | CONFIG_MODULE_UNLOAD=y | ||
| 23 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 24 | CONFIG_MODVERSIONS=y | ||
| 25 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 26 | # CONFIG_BLK_DEV_BSG is not set | ||
| 27 | CONFIG_ARCH_OMAP=y | ||
| 28 | CONFIG_ARCH_OMAP3=y | ||
| 29 | CONFIG_OMAP_RESET_CLOCKS=y | ||
| 30 | # CONFIG_OMAP_MUX is not set | ||
| 31 | CONFIG_OMAP_32K_TIMER=y | ||
| 32 | CONFIG_OMAP_DM_TIMER=y | ||
| 33 | CONFIG_ARCH_OMAP3430=y | ||
| 34 | CONFIG_MACH_OMAP3_TOUCHBOOK=y | ||
| 35 | CONFIG_ARM_THUMBEE=y | ||
| 36 | CONFIG_NO_HZ=y | ||
| 37 | CONFIG_HIGH_RES_TIMERS=y | ||
| 38 | CONFIG_PREEMPT=y | ||
| 39 | CONFIG_AEABI=y | ||
| 40 | # CONFIG_OABI_COMPAT is not set | ||
| 41 | CONFIG_LEDS=y | ||
| 42 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 43 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 44 | CONFIG_CMDLINE=" debug " | ||
| 45 | CONFIG_KEXEC=y | ||
| 46 | CONFIG_VFP=y | ||
| 47 | CONFIG_NEON=y | ||
| 48 | CONFIG_BINFMT_AOUT=m | ||
| 49 | CONFIG_BINFMT_MISC=y | ||
| 50 | CONFIG_PM=y | ||
| 51 | CONFIG_PM_DEBUG=y | ||
| 52 | CONFIG_PM_RUNTIME=y | ||
| 53 | CONFIG_NET=y | ||
| 54 | CONFIG_PACKET=y | ||
| 55 | CONFIG_UNIX=y | ||
| 56 | CONFIG_NET_KEY=y | ||
| 57 | CONFIG_INET=y | ||
| 58 | CONFIG_IP_PNP=y | ||
| 59 | CONFIG_IP_PNP_DHCP=y | ||
| 60 | CONFIG_IP_PNP_BOOTP=y | ||
| 61 | CONFIG_IP_PNP_RARP=y | ||
| 62 | CONFIG_NET_IPIP=m | ||
| 63 | CONFIG_NET_IPGRE=m | ||
| 64 | CONFIG_INET_AH=m | ||
| 65 | CONFIG_INET_ESP=m | ||
| 66 | CONFIG_INET_IPCOMP=m | ||
| 67 | CONFIG_INET_DIAG=m | ||
| 68 | CONFIG_TCP_CONG_ADVANCED=y | ||
| 69 | CONFIG_TCP_CONG_HSTCP=m | ||
| 70 | CONFIG_TCP_CONG_HYBLA=m | ||
| 71 | CONFIG_TCP_CONG_SCALABLE=m | ||
| 72 | CONFIG_TCP_CONG_LP=m | ||
| 73 | CONFIG_TCP_CONG_VENO=m | ||
| 74 | CONFIG_TCP_CONG_YEAH=m | ||
| 75 | CONFIG_TCP_CONG_ILLINOIS=m | ||
| 76 | CONFIG_INET6_AH=m | ||
| 77 | CONFIG_INET6_ESP=m | ||
| 78 | CONFIG_INET6_IPCOMP=m | ||
| 79 | CONFIG_IPV6_MIP6=m | ||
| 80 | CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m | ||
| 81 | CONFIG_IPV6_TUNNEL=m | ||
| 82 | CONFIG_IPV6_MULTIPLE_TABLES=y | ||
| 83 | CONFIG_IPV6_SUBTREES=y | ||
| 84 | CONFIG_IPV6_MROUTE=y | ||
| 85 | CONFIG_NETFILTER=y | ||
| 86 | CONFIG_NETFILTER_NETLINK_QUEUE=m | ||
| 87 | CONFIG_NF_CONNTRACK=m | ||
| 88 | CONFIG_NF_CONNTRACK_EVENTS=y | ||
| 89 | CONFIG_NF_CT_PROTO_UDPLITE=m | ||
| 90 | CONFIG_NF_CONNTRACK_AMANDA=m | ||
| 91 | CONFIG_NF_CONNTRACK_FTP=m | ||
| 92 | CONFIG_NF_CONNTRACK_H323=m | ||
| 93 | CONFIG_NF_CONNTRACK_IRC=m | ||
| 94 | CONFIG_NF_CONNTRACK_NETBIOS_NS=m | ||
| 95 | CONFIG_NF_CONNTRACK_PPTP=m | ||
| 96 | CONFIG_NF_CONNTRACK_SANE=m | ||
| 97 | CONFIG_NF_CONNTRACK_SIP=m | ||
| 98 | CONFIG_NF_CONNTRACK_TFTP=m | ||
| 99 | CONFIG_NF_CT_NETLINK=m | ||
| 100 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m | ||
| 101 | CONFIG_NETFILTER_XT_TARGET_CONNMARK=m | ||
| 102 | CONFIG_NETFILTER_XT_TARGET_MARK=m | ||
| 103 | CONFIG_NETFILTER_XT_TARGET_NFLOG=m | ||
| 104 | CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m | ||
| 105 | CONFIG_NETFILTER_XT_TARGET_TCPMSS=m | ||
| 106 | CONFIG_NETFILTER_XT_MATCH_COMMENT=m | ||
| 107 | CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m | ||
| 108 | CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m | ||
| 109 | CONFIG_NETFILTER_XT_MATCH_CONNMARK=m | ||
| 110 | CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m | ||
| 111 | CONFIG_NETFILTER_XT_MATCH_DSCP=m | ||
| 112 | CONFIG_NETFILTER_XT_MATCH_ESP=m | ||
| 113 | CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m | ||
| 114 | CONFIG_NETFILTER_XT_MATCH_HELPER=m | ||
| 115 | CONFIG_NETFILTER_XT_MATCH_IPRANGE=m | ||
| 116 | CONFIG_NETFILTER_XT_MATCH_LENGTH=m | ||
| 117 | CONFIG_NETFILTER_XT_MATCH_LIMIT=m | ||
| 118 | CONFIG_NETFILTER_XT_MATCH_MAC=m | ||
| 119 | CONFIG_NETFILTER_XT_MATCH_MARK=m | ||
| 120 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m | ||
| 121 | CONFIG_NETFILTER_XT_MATCH_OWNER=m | ||
| 122 | CONFIG_NETFILTER_XT_MATCH_POLICY=m | ||
| 123 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m | ||
| 124 | CONFIG_NETFILTER_XT_MATCH_QUOTA=m | ||
| 125 | CONFIG_NETFILTER_XT_MATCH_RATEEST=m | ||
| 126 | CONFIG_NETFILTER_XT_MATCH_REALM=m | ||
| 127 | CONFIG_NETFILTER_XT_MATCH_RECENT=m | ||
| 128 | CONFIG_NETFILTER_XT_MATCH_STATE=m | ||
| 129 | CONFIG_NETFILTER_XT_MATCH_STATISTIC=m | ||
| 130 | CONFIG_NETFILTER_XT_MATCH_STRING=m | ||
| 131 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m | ||
| 132 | CONFIG_NETFILTER_XT_MATCH_TIME=m | ||
| 133 | CONFIG_NETFILTER_XT_MATCH_U32=m | ||
| 134 | CONFIG_IP_VS=m | ||
| 135 | CONFIG_IP_VS_IPV6=y | ||
| 136 | CONFIG_IP_VS_DEBUG=y | ||
| 137 | CONFIG_IP_VS_PROTO_TCP=y | ||
| 138 | CONFIG_IP_VS_PROTO_UDP=y | ||
| 139 | CONFIG_IP_VS_PROTO_ESP=y | ||
| 140 | CONFIG_IP_VS_PROTO_AH=y | ||
| 141 | CONFIG_IP_VS_RR=m | ||
| 142 | CONFIG_IP_VS_WRR=m | ||
| 143 | CONFIG_IP_VS_LC=m | ||
| 144 | CONFIG_IP_VS_WLC=m | ||
| 145 | CONFIG_IP_VS_LBLC=m | ||
| 146 | CONFIG_IP_VS_LBLCR=m | ||
| 147 | CONFIG_IP_VS_DH=m | ||
| 148 | CONFIG_IP_VS_SH=m | ||
| 149 | CONFIG_IP_VS_SED=m | ||
| 150 | CONFIG_IP_VS_NQ=m | ||
| 151 | CONFIG_IP_VS_FTP=m | ||
| 152 | CONFIG_NF_CONNTRACK_IPV4=m | ||
| 153 | CONFIG_IP_NF_QUEUE=m | ||
| 154 | CONFIG_IP_NF_IPTABLES=m | ||
| 155 | CONFIG_IP_NF_MATCH_ADDRTYPE=m | ||
| 156 | CONFIG_IP_NF_MATCH_AH=m | ||
| 157 | CONFIG_IP_NF_MATCH_ECN=m | ||
| 158 | CONFIG_IP_NF_MATCH_TTL=m | ||
| 159 | CONFIG_IP_NF_FILTER=m | ||
| 160 | CONFIG_IP_NF_TARGET_REJECT=m | ||
| 161 | CONFIG_IP_NF_TARGET_LOG=m | ||
| 162 | CONFIG_IP_NF_TARGET_ULOG=m | ||
| 163 | CONFIG_NF_NAT=m | ||
| 164 | CONFIG_IP_NF_TARGET_MASQUERADE=m | ||
| 165 | CONFIG_IP_NF_TARGET_NETMAP=m | ||
| 166 | CONFIG_IP_NF_TARGET_REDIRECT=m | ||
| 167 | CONFIG_NF_NAT_SNMP_BASIC=m | ||
| 168 | CONFIG_IP_NF_MANGLE=m | ||
| 169 | CONFIG_IP_NF_TARGET_CLUSTERIP=m | ||
| 170 | CONFIG_IP_NF_TARGET_ECN=m | ||
| 171 | CONFIG_IP_NF_TARGET_TTL=m | ||
| 172 | CONFIG_IP_NF_RAW=m | ||
| 173 | CONFIG_IP_NF_ARPTABLES=m | ||
| 174 | CONFIG_IP_NF_ARPFILTER=m | ||
| 175 | CONFIG_IP_NF_ARP_MANGLE=m | ||
| 176 | CONFIG_NF_CONNTRACK_IPV6=m | ||
| 177 | CONFIG_IP6_NF_QUEUE=m | ||
| 178 | CONFIG_IP6_NF_IPTABLES=m | ||
| 179 | CONFIG_IP6_NF_MATCH_AH=m | ||
| 180 | CONFIG_IP6_NF_MATCH_EUI64=m | ||
| 181 | CONFIG_IP6_NF_MATCH_FRAG=m | ||
| 182 | CONFIG_IP6_NF_MATCH_OPTS=m | ||
| 183 | CONFIG_IP6_NF_MATCH_HL=m | ||
| 184 | CONFIG_IP6_NF_MATCH_IPV6HEADER=m | ||
| 185 | CONFIG_IP6_NF_MATCH_MH=m | ||
| 186 | CONFIG_IP6_NF_MATCH_RT=m | ||
| 187 | CONFIG_IP6_NF_TARGET_HL=m | ||
| 188 | CONFIG_IP6_NF_TARGET_LOG=m | ||
| 189 | CONFIG_IP6_NF_FILTER=m | ||
| 190 | CONFIG_IP6_NF_TARGET_REJECT=m | ||
| 191 | CONFIG_IP6_NF_MANGLE=m | ||
| 192 | CONFIG_IP6_NF_RAW=m | ||
| 193 | CONFIG_IP_DCCP=m | ||
| 194 | CONFIG_IP_SCTP=m | ||
| 195 | CONFIG_TIPC=m | ||
| 196 | CONFIG_ATM=m | ||
| 197 | CONFIG_ATM_CLIP=m | ||
| 198 | CONFIG_ATM_LANE=m | ||
| 199 | CONFIG_ATM_MPOA=m | ||
| 200 | CONFIG_ATM_BR2684=m | ||
| 201 | CONFIG_BRIDGE=m | ||
| 202 | CONFIG_VLAN_8021Q=m | ||
| 203 | CONFIG_VLAN_8021Q_GVRP=y | ||
| 204 | CONFIG_WAN_ROUTER=m | ||
| 205 | CONFIG_NET_SCHED=y | ||
| 206 | CONFIG_NET_SCH_CBQ=m | ||
| 207 | CONFIG_NET_SCH_HTB=m | ||
| 208 | CONFIG_NET_SCH_HFSC=m | ||
| 209 | CONFIG_NET_SCH_ATM=m | ||
| 210 | CONFIG_NET_SCH_PRIO=m | ||
| 211 | CONFIG_NET_SCH_MULTIQ=m | ||
| 212 | CONFIG_NET_SCH_RED=m | ||
| 213 | CONFIG_NET_SCH_SFQ=m | ||
| 214 | CONFIG_NET_SCH_TEQL=m | ||
| 215 | CONFIG_NET_SCH_TBF=m | ||
| 216 | CONFIG_NET_SCH_GRED=m | ||
| 217 | CONFIG_NET_SCH_DSMARK=m | ||
| 218 | CONFIG_NET_SCH_NETEM=m | ||
| 219 | CONFIG_NET_SCH_DRR=m | ||
| 220 | CONFIG_NET_CLS_BASIC=m | ||
| 221 | CONFIG_NET_CLS_TCINDEX=m | ||
| 222 | CONFIG_NET_CLS_ROUTE4=m | ||
| 223 | CONFIG_NET_CLS_FW=m | ||
| 224 | CONFIG_NET_CLS_U32=m | ||
| 225 | CONFIG_CLS_U32_PERF=y | ||
| 226 | CONFIG_CLS_U32_MARK=y | ||
| 227 | CONFIG_NET_CLS_RSVP=m | ||
| 228 | CONFIG_NET_CLS_RSVP6=m | ||
| 229 | CONFIG_NET_CLS_FLOW=m | ||
| 230 | CONFIG_NET_CLS_IND=y | ||
| 231 | CONFIG_BT=y | ||
| 232 | CONFIG_BT_L2CAP=y | ||
| 233 | CONFIG_BT_SCO=y | ||
| 234 | CONFIG_BT_RFCOMM=y | ||
| 235 | CONFIG_BT_RFCOMM_TTY=y | ||
| 236 | CONFIG_BT_BNEP=y | ||
| 237 | CONFIG_BT_BNEP_MC_FILTER=y | ||
| 238 | CONFIG_BT_BNEP_PROTO_FILTER=y | ||
| 239 | CONFIG_BT_HIDP=y | ||
| 240 | CONFIG_BT_HCIBTUSB=y | ||
| 241 | CONFIG_BT_HCIBTSDIO=y | ||
| 242 | CONFIG_BT_HCIUART=y | ||
| 243 | CONFIG_BT_HCIUART_H4=y | ||
| 244 | CONFIG_BT_HCIUART_BCSP=y | ||
| 245 | CONFIG_BT_HCIUART_LL=y | ||
| 246 | CONFIG_BT_HCIBCM203X=y | ||
| 247 | CONFIG_BT_HCIBPA10X=y | ||
| 248 | CONFIG_BT_HCIBFUSB=y | ||
| 249 | CONFIG_AF_RXRPC=m | ||
| 250 | CONFIG_CFG80211=m | ||
| 251 | CONFIG_LIB80211=y | ||
| 252 | CONFIG_MAC80211=m | ||
| 253 | CONFIG_MAC80211_RC_PID=y | ||
| 254 | # CONFIG_MAC80211_RC_MINSTREL is not set | ||
| 255 | CONFIG_WIMAX=m | ||
| 256 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 257 | CONFIG_MTD=y | ||
| 258 | CONFIG_MTD_CONCAT=y | ||
| 259 | CONFIG_MTD_PARTITIONS=y | ||
| 260 | CONFIG_MTD_CHAR=y | ||
| 261 | CONFIG_MTD_BLOCK=y | ||
| 262 | CONFIG_MTD_NAND=y | ||
| 263 | CONFIG_MTD_NAND_OMAP2=y | ||
| 264 | CONFIG_MTD_NAND_PLATFORM=y | ||
| 265 | CONFIG_MTD_UBI=y | ||
| 266 | CONFIG_BLK_DEV_LOOP=y | ||
| 267 | CONFIG_BLK_DEV_CRYPTOLOOP=m | ||
| 268 | CONFIG_BLK_DEV_RAM=y | ||
| 269 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 270 | CONFIG_CDROM_PKTCDVD=m | ||
| 271 | CONFIG_EEPROM_93CX6=y | ||
| 272 | CONFIG_RAID_ATTRS=m | ||
| 273 | CONFIG_SCSI=y | ||
| 274 | CONFIG_BLK_DEV_SD=y | ||
| 275 | CONFIG_BLK_DEV_SR=y | ||
| 276 | CONFIG_BLK_DEV_SR_VENDOR=y | ||
| 277 | CONFIG_CHR_DEV_SG=y | ||
| 278 | CONFIG_CHR_DEV_SCH=m | ||
| 279 | CONFIG_SCSI_MULTI_LUN=y | ||
| 280 | CONFIG_ISCSI_TCP=m | ||
| 281 | CONFIG_MD=y | ||
| 282 | CONFIG_BLK_DEV_MD=m | ||
| 283 | CONFIG_MD_LINEAR=m | ||
| 284 | CONFIG_MD_RAID0=m | ||
| 285 | CONFIG_MD_RAID1=m | ||
| 286 | CONFIG_MD_RAID10=m | ||
| 287 | CONFIG_MD_RAID456=m | ||
| 288 | CONFIG_MD_MULTIPATH=m | ||
| 289 | CONFIG_MD_FAULTY=m | ||
| 290 | CONFIG_BLK_DEV_DM=m | ||
| 291 | CONFIG_DM_CRYPT=m | ||
| 292 | CONFIG_DM_SNAPSHOT=m | ||
| 293 | CONFIG_DM_MIRROR=m | ||
| 294 | CONFIG_DM_ZERO=m | ||
| 295 | CONFIG_DM_MULTIPATH=m | ||
| 296 | CONFIG_DM_DELAY=m | ||
| 297 | CONFIG_NETDEVICES=y | ||
| 298 | CONFIG_DUMMY=m | ||
| 299 | CONFIG_BONDING=m | ||
| 300 | CONFIG_MACVLAN=m | ||
| 301 | CONFIG_EQUALIZER=m | ||
| 302 | CONFIG_TUN=m | ||
| 303 | CONFIG_VETH=m | ||
| 304 | # CONFIG_NETDEV_1000 is not set | ||
| 305 | # CONFIG_NETDEV_10000 is not set | ||
| 306 | # CONFIG_ATM_DRIVERS is not set | ||
| 307 | CONFIG_PPP=m | ||
| 308 | CONFIG_PPP_MULTILINK=y | ||
| 309 | CONFIG_PPP_FILTER=y | ||
| 310 | CONFIG_PPP_ASYNC=m | ||
| 311 | CONFIG_PPP_SYNC_TTY=m | ||
| 312 | CONFIG_PPP_DEFLATE=m | ||
| 313 | CONFIG_PPP_BSDCOMP=m | ||
| 314 | CONFIG_PPP_MPPE=m | ||
| 315 | CONFIG_PPPOE=m | ||
| 316 | CONFIG_NETCONSOLE=m | ||
| 317 | CONFIG_NETCONSOLE_DYNAMIC=y | ||
| 318 | CONFIG_NETPOLL_TRAP=y | ||
| 319 | CONFIG_INPUT_FF_MEMLESS=y | ||
| 320 | CONFIG_INPUT_EVDEV=y | ||
| 321 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 322 | CONFIG_KEYBOARD_GPIO=y | ||
| 323 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 324 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 325 | CONFIG_INPUT_MISC=y | ||
| 326 | CONFIG_INPUT_TWL4030_PWRBUTTON=y | ||
| 327 | CONFIG_INPUT_UINPUT=y | ||
| 328 | CONFIG_VT_HW_CONSOLE_BINDING=y | ||
| 329 | CONFIG_SERIAL_8250=y | ||
| 330 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 331 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 332 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 333 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 334 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 335 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 336 | CONFIG_SERIAL_8250_RSA=y | ||
| 337 | # CONFIG_LEGACY_PTYS is not set | ||
| 338 | CONFIG_HW_RANDOM=y | ||
| 339 | CONFIG_I2C=y | ||
| 340 | CONFIG_I2C_CHARDEV=y | ||
| 341 | CONFIG_I2C_OMAP=y | ||
| 342 | CONFIG_SPI=y | ||
| 343 | CONFIG_SPI_OMAP24XX=y | ||
| 344 | CONFIG_SPI_SPIDEV=y | ||
| 345 | CONFIG_GPIO_SYSFS=y | ||
| 346 | CONFIG_GPIO_TWL4030=y | ||
| 347 | CONFIG_POWER_SUPPLY=y | ||
| 348 | CONFIG_BATTERY_BQ27x00=y | ||
| 349 | CONFIG_THERMAL=y | ||
| 350 | CONFIG_THERMAL_HWMON=y | ||
| 351 | CONFIG_WATCHDOG=y | ||
| 352 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 353 | CONFIG_OMAP_WATCHDOG=y | ||
| 354 | CONFIG_TWL4030_CORE=y | ||
| 355 | CONFIG_REGULATOR=y | ||
| 356 | CONFIG_REGULATOR_TWL4030=y | ||
| 357 | CONFIG_FB=y | ||
| 358 | CONFIG_DISPLAY_SUPPORT=y | ||
| 359 | # CONFIG_VGA_CONSOLE is not set | ||
| 360 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 361 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y | ||
| 362 | CONFIG_LOGO=y | ||
| 363 | CONFIG_SOUND=y | ||
| 364 | CONFIG_SND=y | ||
| 365 | CONFIG_SND_SEQUENCER=m | ||
| 366 | CONFIG_SND_MIXER_OSS=y | ||
| 367 | CONFIG_SND_PCM_OSS=y | ||
| 368 | CONFIG_SND_SEQUENCER_OSS=y | ||
| 369 | CONFIG_SND_HRTIMER=m | ||
| 370 | # CONFIG_SND_ARM is not set | ||
| 371 | CONFIG_SND_USB_AUDIO=y | ||
| 372 | CONFIG_SND_USB_CAIAQ=m | ||
| 373 | CONFIG_SND_USB_CAIAQ_INPUT=y | ||
| 374 | CONFIG_SND_SOC=y | ||
| 375 | CONFIG_SND_OMAP_SOC=y | ||
| 376 | CONFIG_USB=y | ||
| 377 | CONFIG_USB_DEVICEFS=y | ||
| 378 | CONFIG_USB_SUSPEND=y | ||
| 379 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 380 | CONFIG_USB_MON=y | ||
| 381 | CONFIG_USB_OXU210HP_HCD=y | ||
| 382 | CONFIG_USB_MUSB_HDRC=y | ||
| 383 | CONFIG_USB_MUSB_OTG=y | ||
| 384 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 385 | CONFIG_USB_ACM=m | ||
| 386 | CONFIG_USB_PRINTER=m | ||
| 387 | CONFIG_USB_WDM=m | ||
| 388 | CONFIG_USB_TMC=m | ||
| 389 | CONFIG_USB_STORAGE=y | ||
| 390 | CONFIG_USB_SERIAL=m | ||
| 391 | CONFIG_USB_SERIAL_GENERIC=y | ||
| 392 | CONFIG_USB_SERIAL_AIRCABLE=m | ||
| 393 | CONFIG_USB_SERIAL_ARK3116=m | ||
| 394 | CONFIG_USB_SERIAL_BELKIN=m | ||
| 395 | CONFIG_USB_SERIAL_CH341=m | ||
| 396 | CONFIG_USB_SERIAL_WHITEHEAT=m | ||
| 397 | CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m | ||
| 398 | CONFIG_USB_SERIAL_CYPRESS_M8=m | ||
| 399 | CONFIG_USB_SERIAL_EMPEG=m | ||
| 400 | CONFIG_USB_SERIAL_FTDI_SIO=m | ||
| 401 | CONFIG_USB_SERIAL_FUNSOFT=m | ||
| 402 | CONFIG_USB_SERIAL_VISOR=m | ||
| 403 | CONFIG_USB_SERIAL_IPAQ=m | ||
| 404 | CONFIG_USB_SERIAL_IR=m | ||
| 405 | CONFIG_USB_SERIAL_EDGEPORT=m | ||
| 406 | CONFIG_USB_SERIAL_EDGEPORT_TI=m | ||
| 407 | CONFIG_USB_SERIAL_GARMIN=m | ||
| 408 | CONFIG_USB_SERIAL_IPW=m | ||
| 409 | CONFIG_USB_SERIAL_IUU=m | ||
| 410 | CONFIG_USB_SERIAL_KEYSPAN_PDA=m | ||
| 411 | CONFIG_USB_SERIAL_KEYSPAN=m | ||
| 412 | CONFIG_USB_SERIAL_KEYSPAN_MPR=y | ||
| 413 | CONFIG_USB_SERIAL_KEYSPAN_USA28=y | ||
| 414 | CONFIG_USB_SERIAL_KEYSPAN_USA28X=y | ||
| 415 | CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y | ||
| 416 | CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y | ||
| 417 | CONFIG_USB_SERIAL_KEYSPAN_USA19=y | ||
| 418 | CONFIG_USB_SERIAL_KEYSPAN_USA18X=y | ||
| 419 | CONFIG_USB_SERIAL_KEYSPAN_USA19W=y | ||
| 420 | CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y | ||
| 421 | CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y | ||
| 422 | CONFIG_USB_SERIAL_KEYSPAN_USA49W=y | ||
| 423 | CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y | ||
| 424 | CONFIG_USB_SERIAL_KLSI=m | ||
| 425 | CONFIG_USB_SERIAL_KOBIL_SCT=m | ||
| 426 | CONFIG_USB_SERIAL_MCT_U232=m | ||
| 427 | CONFIG_USB_SERIAL_MOS7720=m | ||
| 428 | CONFIG_USB_SERIAL_MOS7840=m | ||
| 429 | CONFIG_USB_SERIAL_MOTOROLA=m | ||
| 430 | CONFIG_USB_SERIAL_NAVMAN=m | ||
| 431 | CONFIG_USB_SERIAL_PL2303=m | ||
| 432 | CONFIG_USB_SERIAL_OTI6858=m | ||
| 433 | CONFIG_USB_SERIAL_SPCP8X5=m | ||
| 434 | CONFIG_USB_SERIAL_HP4X=m | ||
| 435 | CONFIG_USB_SERIAL_SAFE=m | ||
| 436 | CONFIG_USB_SERIAL_SIEMENS_MPI=m | ||
| 437 | CONFIG_USB_SERIAL_SIERRAWIRELESS=m | ||
| 438 | CONFIG_USB_SERIAL_TI=m | ||
| 439 | CONFIG_USB_SERIAL_CYBERJACK=m | ||
| 440 | CONFIG_USB_SERIAL_XIRCOM=m | ||
| 441 | CONFIG_USB_SERIAL_OPTION=m | ||
| 442 | CONFIG_USB_SERIAL_OMNINET=m | ||
| 443 | CONFIG_USB_SERIAL_OPTICON=m | ||
| 444 | CONFIG_USB_SERIAL_DEBUG=m | ||
| 445 | CONFIG_USB_EMI62=m | ||
| 446 | CONFIG_USB_EMI26=m | ||
| 447 | CONFIG_USB_SISUSBVGA=m | ||
| 448 | CONFIG_USB_SISUSBVGA_CON=y | ||
| 449 | CONFIG_USB_TEST=m | ||
| 450 | CONFIG_USB_GADGET=m | ||
| 451 | CONFIG_USB_GADGET_DEBUG_FS=y | ||
| 452 | CONFIG_USB_ZERO=m | ||
| 453 | CONFIG_USB_ZERO_HNPTEST=y | ||
| 454 | CONFIG_USB_ETH=m | ||
| 455 | CONFIG_USB_GADGETFS=m | ||
| 456 | CONFIG_USB_FILE_STORAGE=m | ||
| 457 | CONFIG_USB_G_SERIAL=m | ||
| 458 | CONFIG_USB_MIDI_GADGET=m | ||
| 459 | CONFIG_USB_G_PRINTER=m | ||
| 460 | CONFIG_USB_CDC_COMPOSITE=m | ||
| 461 | CONFIG_USB_GPIO_VBUS=y | ||
| 462 | CONFIG_TWL4030_USB=y | ||
| 463 | CONFIG_MMC=y | ||
| 464 | CONFIG_MMC_UNSAFE_RESUME=y | ||
| 465 | CONFIG_SDIO_UART=y | ||
| 466 | CONFIG_MMC_OMAP_HS=y | ||
| 467 | CONFIG_MMC_SPI=m | ||
| 468 | CONFIG_NEW_LEDS=y | ||
| 469 | CONFIG_LEDS_CLASS=y | ||
| 470 | CONFIG_LEDS_GPIO=y | ||
| 471 | CONFIG_LEDS_TRIGGERS=y | ||
| 472 | CONFIG_LEDS_TRIGGER_TIMER=m | ||
| 473 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 474 | CONFIG_LEDS_TRIGGER_BACKLIGHT=m | ||
| 475 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=m | ||
| 476 | CONFIG_RTC_CLASS=y | ||
| 477 | CONFIG_RTC_DRV_TWL4030=y | ||
| 478 | CONFIG_UIO=m | ||
| 479 | CONFIG_UIO_PDRV=m | ||
| 480 | CONFIG_UIO_PDRV_GENIRQ=m | ||
| 481 | CONFIG_STAGING=y | ||
| 482 | # CONFIG_STAGING_EXCLUDE_BUILD is not set | ||
| 483 | CONFIG_EXT2_FS=y | ||
| 484 | CONFIG_EXT3_FS=y | ||
| 485 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 486 | CONFIG_EXT4_FS=m | ||
| 487 | CONFIG_REISERFS_FS=m | ||
| 488 | CONFIG_REISERFS_PROC_INFO=y | ||
| 489 | CONFIG_REISERFS_FS_XATTR=y | ||
| 490 | CONFIG_JFS_FS=m | ||
| 491 | CONFIG_XFS_FS=m | ||
| 492 | CONFIG_INOTIFY=y | ||
| 493 | CONFIG_QUOTA=y | ||
| 494 | CONFIG_QFMT_V2=y | ||
| 495 | CONFIG_AUTOFS4_FS=m | ||
| 496 | CONFIG_FUSE_FS=y | ||
| 497 | CONFIG_ISO9660_FS=m | ||
| 498 | CONFIG_JOLIET=y | ||
| 499 | CONFIG_ZISOFS=y | ||
| 500 | CONFIG_UDF_FS=m | ||
| 501 | CONFIG_MSDOS_FS=y | ||
| 502 | CONFIG_VFAT_FS=y | ||
| 503 | CONFIG_NTFS_FS=m | ||
| 504 | CONFIG_NTFS_RW=y | ||
| 505 | CONFIG_TMPFS=y | ||
| 506 | CONFIG_JFFS2_FS=y | ||
| 507 | CONFIG_JFFS2_SUMMARY=y | ||
| 508 | CONFIG_JFFS2_FS_XATTR=y | ||
| 509 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 510 | CONFIG_JFFS2_LZO=y | ||
| 511 | CONFIG_JFFS2_RUBIN=y | ||
| 512 | CONFIG_JFFS2_CMODE_FAVOURLZO=y | ||
| 513 | CONFIG_UBIFS_FS=y | ||
| 514 | CONFIG_UBIFS_FS_XATTR=y | ||
| 515 | CONFIG_UBIFS_FS_ADVANCED_COMPR=y | ||
| 516 | CONFIG_SQUASHFS=y | ||
| 517 | CONFIG_NFS_FS=y | ||
| 518 | CONFIG_NFS_V3=y | ||
| 519 | CONFIG_NFS_V4=y | ||
| 520 | CONFIG_ROOT_NFS=y | ||
| 521 | CONFIG_NFSD=m | ||
| 522 | CONFIG_NFSD_V3_ACL=y | ||
| 523 | CONFIG_NFSD_V4=y | ||
| 524 | CONFIG_CIFS=m | ||
| 525 | CONFIG_CIFS_STATS=y | ||
| 526 | CONFIG_CIFS_STATS2=y | ||
| 527 | CONFIG_CIFS_EXPERIMENTAL=y | ||
| 528 | CONFIG_PARTITION_ADVANCED=y | ||
| 529 | CONFIG_BSD_DISKLABEL=y | ||
| 530 | CONFIG_MINIX_SUBPARTITION=y | ||
| 531 | CONFIG_SOLARIS_X86_PARTITION=y | ||
| 532 | CONFIG_UNIXWARE_DISKLABEL=y | ||
| 533 | CONFIG_EFI_PARTITION=y | ||
| 534 | CONFIG_NLS_CODEPAGE_437=y | ||
| 535 | CONFIG_NLS_CODEPAGE_737=m | ||
| 536 | CONFIG_NLS_CODEPAGE_775=m | ||
| 537 | CONFIG_NLS_CODEPAGE_850=m | ||
| 538 | CONFIG_NLS_CODEPAGE_852=m | ||
| 539 | CONFIG_NLS_CODEPAGE_855=m | ||
| 540 | CONFIG_NLS_CODEPAGE_857=m | ||
| 541 | CONFIG_NLS_CODEPAGE_860=m | ||
| 542 | CONFIG_NLS_CODEPAGE_861=m | ||
| 543 | CONFIG_NLS_CODEPAGE_862=m | ||
| 544 | CONFIG_NLS_CODEPAGE_863=m | ||
| 545 | CONFIG_NLS_CODEPAGE_864=m | ||
| 546 | CONFIG_NLS_CODEPAGE_865=m | ||
| 547 | CONFIG_NLS_CODEPAGE_866=m | ||
| 548 | CONFIG_NLS_CODEPAGE_869=m | ||
| 549 | CONFIG_NLS_CODEPAGE_936=m | ||
| 550 | CONFIG_NLS_CODEPAGE_950=m | ||
| 551 | CONFIG_NLS_CODEPAGE_932=m | ||
| 552 | CONFIG_NLS_CODEPAGE_949=m | ||
| 553 | CONFIG_NLS_CODEPAGE_874=m | ||
| 554 | CONFIG_NLS_ISO8859_8=m | ||
| 555 | CONFIG_NLS_CODEPAGE_1250=m | ||
| 556 | CONFIG_NLS_CODEPAGE_1251=m | ||
| 557 | CONFIG_NLS_ASCII=m | ||
| 558 | CONFIG_NLS_ISO8859_1=m | ||
| 559 | CONFIG_NLS_ISO8859_2=m | ||
| 560 | CONFIG_NLS_ISO8859_3=m | ||
| 561 | CONFIG_NLS_ISO8859_4=m | ||
| 562 | CONFIG_NLS_ISO8859_5=m | ||
| 563 | CONFIG_NLS_ISO8859_6=m | ||
| 564 | CONFIG_NLS_ISO8859_7=m | ||
| 565 | CONFIG_NLS_ISO8859_9=m | ||
| 566 | CONFIG_NLS_ISO8859_13=m | ||
| 567 | CONFIG_NLS_ISO8859_14=m | ||
| 568 | CONFIG_NLS_ISO8859_15=m | ||
| 569 | CONFIG_NLS_KOI8_R=m | ||
| 570 | CONFIG_NLS_KOI8_U=m | ||
| 571 | CONFIG_NLS_UTF8=y | ||
| 572 | CONFIG_PRINTK_TIME=y | ||
| 573 | CONFIG_MAGIC_SYSRQ=y | ||
| 574 | CONFIG_DEBUG_FS=y | ||
| 575 | CONFIG_DEBUG_KERNEL=y | ||
| 576 | CONFIG_SCHEDSTATS=y | ||
| 577 | CONFIG_TIMER_STATS=y | ||
| 578 | CONFIG_DEBUG_MUTEXES=y | ||
| 579 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 580 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 581 | CONFIG_CRYPTO_FIPS=y | ||
| 582 | CONFIG_CRYPTO_NULL=m | ||
| 583 | CONFIG_CRYPTO_CRYPTD=m | ||
| 584 | CONFIG_CRYPTO_TEST=m | ||
| 585 | CONFIG_CRYPTO_CCM=m | ||
| 586 | CONFIG_CRYPTO_GCM=m | ||
| 587 | CONFIG_CRYPTO_CTS=m | ||
| 588 | CONFIG_CRYPTO_ECB=y | ||
| 589 | CONFIG_CRYPTO_LRW=m | ||
| 590 | CONFIG_CRYPTO_PCBC=m | ||
| 591 | CONFIG_CRYPTO_XTS=m | ||
| 592 | CONFIG_CRYPTO_XCBC=m | ||
| 593 | CONFIG_CRYPTO_MD4=m | ||
| 594 | CONFIG_CRYPTO_MICHAEL_MIC=y | ||
| 595 | CONFIG_CRYPTO_RMD128=m | ||
| 596 | CONFIG_CRYPTO_RMD160=m | ||
| 597 | CONFIG_CRYPTO_RMD256=m | ||
| 598 | CONFIG_CRYPTO_RMD320=m | ||
| 599 | CONFIG_CRYPTO_SHA256=m | ||
| 600 | CONFIG_CRYPTO_SHA512=m | ||
| 601 | CONFIG_CRYPTO_TGR192=m | ||
| 602 | CONFIG_CRYPTO_WP512=m | ||
| 603 | CONFIG_CRYPTO_AES=y | ||
| 604 | CONFIG_CRYPTO_ANUBIS=m | ||
| 605 | CONFIG_CRYPTO_ARC4=y | ||
| 606 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 607 | CONFIG_CRYPTO_CAMELLIA=m | ||
| 608 | CONFIG_CRYPTO_CAST5=m | ||
| 609 | CONFIG_CRYPTO_CAST6=m | ||
| 610 | CONFIG_CRYPTO_FCRYPT=m | ||
| 611 | CONFIG_CRYPTO_KHAZAD=m | ||
| 612 | CONFIG_CRYPTO_SALSA20=m | ||
| 613 | CONFIG_CRYPTO_SEED=m | ||
| 614 | CONFIG_CRYPTO_SERPENT=m | ||
| 615 | CONFIG_CRYPTO_TEA=m | ||
| 616 | CONFIG_CRYPTO_TWOFISH=m | ||
| 617 | CONFIG_CRC_CCITT=y | ||
| 618 | CONFIG_CRC_T10DIF=y | ||
| 619 | CONFIG_CRC_ITU_T=y | ||
| 620 | CONFIG_CRC7=y | ||
| 621 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/omap_2430sdp_defconfig b/arch/arm/configs/omap_2430sdp_defconfig deleted file mode 100644 index 0cf4147a9366..000000000000 --- a/arch/arm/configs/omap_2430sdp_defconfig +++ /dev/null | |||
| @@ -1,136 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 5 | CONFIG_BLK_DEV_INITRD=y | ||
| 6 | CONFIG_EMBEDDED=y | ||
| 7 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 8 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 9 | CONFIG_SLAB=y | ||
| 10 | CONFIG_MODULES=y | ||
| 11 | CONFIG_MODULE_UNLOAD=y | ||
| 12 | CONFIG_MODVERSIONS=y | ||
| 13 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 14 | # CONFIG_BLK_DEV_BSG is not set | ||
| 15 | CONFIG_ARCH_OMAP=y | ||
| 16 | CONFIG_ARCH_OMAP2=y | ||
| 17 | # CONFIG_OMAP_MUX_WARNINGS is not set | ||
| 18 | CONFIG_OMAP_DM_TIMER=y | ||
| 19 | CONFIG_ARCH_OMAP2430=y | ||
| 20 | CONFIG_MACH_OMAP_2430SDP=y | ||
| 21 | CONFIG_PREEMPT=y | ||
| 22 | CONFIG_AEABI=y | ||
| 23 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 24 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 25 | CONFIG_CMDLINE="root=/dev/ram0 rw console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192" | ||
| 26 | CONFIG_FPE_NWFPE=y | ||
| 27 | CONFIG_BINFMT_MISC=y | ||
| 28 | CONFIG_PM=y | ||
| 29 | CONFIG_NET=y | ||
| 30 | CONFIG_PACKET=y | ||
| 31 | CONFIG_UNIX=y | ||
| 32 | CONFIG_NET_KEY=y | ||
| 33 | CONFIG_INET=y | ||
| 34 | CONFIG_IP_PNP=y | ||
| 35 | CONFIG_IP_PNP_DHCP=y | ||
| 36 | # CONFIG_IPV6 is not set | ||
| 37 | # CONFIG_FW_LOADER is not set | ||
| 38 | CONFIG_MTD=y | ||
| 39 | CONFIG_MTD_CONCAT=y | ||
| 40 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 41 | CONFIG_MTD_CHAR=y | ||
| 42 | CONFIG_MTD_BLOCK=y | ||
| 43 | CONFIG_MTD_CFI=y | ||
| 44 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 45 | CONFIG_MTD_ONENAND=y | ||
| 46 | CONFIG_MTD_ONENAND_VERIFY_WRITE=y | ||
| 47 | CONFIG_MTD_ONENAND_OMAP2=y | ||
| 48 | CONFIG_BLK_DEV_LOOP=y | ||
| 49 | CONFIG_BLK_DEV_RAM=y | ||
| 50 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 51 | CONFIG_SCSI=m | ||
| 52 | CONFIG_BLK_DEV_SD=m | ||
| 53 | CONFIG_CHR_DEV_SG=m | ||
| 54 | CONFIG_NETDEVICES=y | ||
| 55 | CONFIG_NET_ETHERNET=y | ||
| 56 | CONFIG_SMC91X=y | ||
| 57 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 58 | CONFIG_INPUT_EVDEV=y | ||
| 59 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 60 | CONFIG_KEYBOARD_TWL4030=y | ||
| 61 | # CONFIG_INPUT_MOUSE is not set | ||
| 62 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 63 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 64 | # CONFIG_SERIO is not set | ||
| 65 | CONFIG_SERIAL_8250=y | ||
| 66 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 67 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 68 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 69 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 70 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 71 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 72 | CONFIG_SERIAL_8250_RSA=y | ||
| 73 | # CONFIG_LEGACY_PTYS is not set | ||
| 74 | CONFIG_HW_RANDOM=y | ||
| 75 | CONFIG_I2C=y | ||
| 76 | CONFIG_I2C_CHARDEV=y | ||
| 77 | CONFIG_I2C_OMAP=y | ||
| 78 | CONFIG_SPI=y | ||
| 79 | # CONFIG_HWMON is not set | ||
| 80 | CONFIG_WATCHDOG=y | ||
| 81 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 82 | CONFIG_OMAP_WATCHDOG=y | ||
| 83 | CONFIG_TWL4030_CORE=y | ||
| 84 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 85 | CONFIG_FB=y | ||
| 86 | CONFIG_FIRMWARE_EDID=y | ||
| 87 | CONFIG_FB_OMAP=y | ||
| 88 | # CONFIG_VGA_CONSOLE is not set | ||
| 89 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 90 | CONFIG_LOGO=y | ||
| 91 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 92 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 93 | CONFIG_USB=m | ||
| 94 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 95 | CONFIG_USB_MON=m | ||
| 96 | CONFIG_USB_MUSB_HDRC=m | ||
| 97 | CONFIG_USB_MUSB_OTG=y | ||
| 98 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 99 | CONFIG_USB_STORAGE=m | ||
| 100 | CONFIG_USB_GADGET=m | ||
| 101 | CONFIG_USB_GADGET_DEBUG_FILES=y | ||
| 102 | CONFIG_USB_ZERO=m | ||
| 103 | CONFIG_USB_ETH=m | ||
| 104 | CONFIG_USB_GADGETFS=m | ||
| 105 | CONFIG_USB_FILE_STORAGE=m | ||
| 106 | CONFIG_USB_G_SERIAL=m | ||
| 107 | CONFIG_MMC=y | ||
| 108 | CONFIG_MMC_OMAP_HS=y | ||
| 109 | CONFIG_EXT2_FS=y | ||
| 110 | CONFIG_EXT3_FS=y | ||
| 111 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 112 | CONFIG_INOTIFY=y | ||
| 113 | CONFIG_QUOTA=y | ||
| 114 | CONFIG_QFMT_V2=y | ||
| 115 | CONFIG_MSDOS_FS=y | ||
| 116 | CONFIG_VFAT_FS=y | ||
| 117 | CONFIG_TMPFS=y | ||
| 118 | CONFIG_JFFS2_FS=y | ||
| 119 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 120 | CONFIG_NFS_FS=y | ||
| 121 | CONFIG_NFS_V3=y | ||
| 122 | CONFIG_ROOT_NFS=y | ||
| 123 | CONFIG_PARTITION_ADVANCED=y | ||
| 124 | CONFIG_NLS_CODEPAGE_437=y | ||
| 125 | CONFIG_MAGIC_SYSRQ=y | ||
| 126 | CONFIG_DEBUG_KERNEL=y | ||
| 127 | CONFIG_TIMER_STATS=y | ||
| 128 | CONFIG_DEBUG_MUTEXES=y | ||
| 129 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 130 | CONFIG_CRYPTO_CBC=y | ||
| 131 | CONFIG_CRYPTO_ECB=m | ||
| 132 | CONFIG_CRYPTO_PCBC=m | ||
| 133 | CONFIG_CRYPTO_MD5=y | ||
| 134 | CONFIG_CRYPTO_DES=y | ||
| 135 | CONFIG_CRC_CCITT=y | ||
| 136 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/omap_3430sdp_defconfig b/arch/arm/configs/omap_3430sdp_defconfig deleted file mode 100644 index 5dbe595999be..000000000000 --- a/arch/arm/configs/omap_3430sdp_defconfig +++ /dev/null | |||
| @@ -1,178 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_IKCONFIG=y | ||
| 5 | CONFIG_IKCONFIG_PROC=y | ||
| 6 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 7 | CONFIG_BLK_DEV_INITRD=y | ||
| 8 | CONFIG_EMBEDDED=y | ||
| 9 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 10 | CONFIG_SLAB=y | ||
| 11 | CONFIG_MODULES=y | ||
| 12 | CONFIG_MODULE_UNLOAD=y | ||
| 13 | CONFIG_MODVERSIONS=y | ||
| 14 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 15 | # CONFIG_BLK_DEV_BSG is not set | ||
| 16 | CONFIG_ARCH_OMAP=y | ||
| 17 | CONFIG_ARCH_OMAP3=y | ||
| 18 | CONFIG_OMAP_RESET_CLOCKS=y | ||
| 19 | CONFIG_OMAP_MUX_DEBUG=y | ||
| 20 | CONFIG_OMAP_32K_TIMER=y | ||
| 21 | CONFIG_OMAP_DM_TIMER=y | ||
| 22 | CONFIG_ARCH_OMAP3430=y | ||
| 23 | CONFIG_MACH_OMAP_3430SDP=y | ||
| 24 | CONFIG_NO_HZ=y | ||
| 25 | CONFIG_HIGH_RES_TIMERS=y | ||
| 26 | CONFIG_AEABI=y | ||
| 27 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 28 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 29 | CONFIG_CMDLINE="console=ttyS2,115200 root=/dev/mmcblk0p3 rootwait debug" | ||
| 30 | CONFIG_CPU_FREQ=y | ||
| 31 | CONFIG_CPU_FREQ_STAT_DETAILS=y | ||
| 32 | CONFIG_CPU_FREQ_GOV_USERSPACE=y | ||
| 33 | CONFIG_CPU_FREQ_GOV_ONDEMAND=y | ||
| 34 | CONFIG_FPE_NWFPE=y | ||
| 35 | CONFIG_VFP=y | ||
| 36 | CONFIG_NEON=y | ||
| 37 | CONFIG_BINFMT_MISC=y | ||
| 38 | CONFIG_PM=y | ||
| 39 | CONFIG_PM_RUNTIME=y | ||
| 40 | CONFIG_NET=y | ||
| 41 | CONFIG_PACKET=y | ||
| 42 | CONFIG_UNIX=y | ||
| 43 | CONFIG_NET_KEY=y | ||
| 44 | CONFIG_INET=y | ||
| 45 | CONFIG_IP_PNP=y | ||
| 46 | CONFIG_IP_PNP_DHCP=y | ||
| 47 | CONFIG_IP_PNP_BOOTP=y | ||
| 48 | CONFIG_IP_PNP_RARP=y | ||
| 49 | # CONFIG_INET_LRO is not set | ||
| 50 | # CONFIG_IPV6 is not set | ||
| 51 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 52 | # CONFIG_FW_LOADER is not set | ||
| 53 | CONFIG_MTD=y | ||
| 54 | CONFIG_MTD_CONCAT=y | ||
| 55 | CONFIG_MTD_PARTITIONS=y | ||
| 56 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 57 | CONFIG_MTD_CHAR=y | ||
| 58 | CONFIG_MTD_BLOCK=y | ||
| 59 | CONFIG_MTD_CFI=y | ||
| 60 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 61 | CONFIG_MTD_NAND=y | ||
| 62 | CONFIG_BLK_DEV_LOOP=y | ||
| 63 | CONFIG_BLK_DEV_RAM=y | ||
| 64 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 65 | CONFIG_SCSI=y | ||
| 66 | CONFIG_BLK_DEV_SD=y | ||
| 67 | CONFIG_SCSI_MULTI_LUN=y | ||
| 68 | CONFIG_NETDEVICES=y | ||
| 69 | CONFIG_PHYLIB=y | ||
| 70 | CONFIG_NET_ETHERNET=y | ||
| 71 | CONFIG_SMC91X=y | ||
| 72 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 73 | CONFIG_INPUT_EVDEV=y | ||
| 74 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 75 | # CONFIG_INPUT_MOUSE is not set | ||
| 76 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 77 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 78 | # CONFIG_SERIO is not set | ||
| 79 | # CONFIG_CONSOLE_TRANSLATIONS is not set | ||
| 80 | CONFIG_SERIAL_8250=y | ||
| 81 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 82 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 83 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 84 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 85 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 86 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 87 | CONFIG_SERIAL_8250_RSA=y | ||
| 88 | # CONFIG_LEGACY_PTYS is not set | ||
| 89 | CONFIG_HW_RANDOM=y | ||
| 90 | CONFIG_I2C=y | ||
| 91 | CONFIG_I2C_CHARDEV=y | ||
| 92 | CONFIG_I2C_OMAP=y | ||
| 93 | CONFIG_SPI=y | ||
| 94 | CONFIG_SPI_OMAP24XX=y | ||
| 95 | CONFIG_GPIO_SYSFS=y | ||
| 96 | CONFIG_GPIO_TWL4030=y | ||
| 97 | # CONFIG_HWMON is not set | ||
| 98 | CONFIG_WATCHDOG=y | ||
| 99 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 100 | CONFIG_OMAP_WATCHDOG=y | ||
| 101 | CONFIG_TWL4030_WATCHDOG=y | ||
| 102 | CONFIG_TWL4030_CORE=y | ||
| 103 | CONFIG_REGULATOR=y | ||
| 104 | CONFIG_REGULATOR_TWL4030=y | ||
| 105 | CONFIG_FB=y | ||
| 106 | CONFIG_OMAP2_DSS=y | ||
| 107 | CONFIG_OMAP2_VRAM_SIZE=4 | ||
| 108 | CONFIG_FB_OMAP2=y | ||
| 109 | CONFIG_PANEL_GENERIC=y | ||
| 110 | CONFIG_PANEL_SHARP_LS037V7DW01=y | ||
| 111 | CONFIG_DISPLAY_SUPPORT=y | ||
| 112 | # CONFIG_VGA_CONSOLE is not set | ||
| 113 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 114 | CONFIG_LOGO=y | ||
| 115 | CONFIG_USB=y | ||
| 116 | CONFIG_USB_DEBUG=y | ||
| 117 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 118 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 119 | CONFIG_USB_SUSPEND=y | ||
| 120 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 121 | CONFIG_USB_MON=y | ||
| 122 | CONFIG_USB_EHCI_HCD=m | ||
| 123 | CONFIG_USB_MUSB_HDRC=y | ||
| 124 | CONFIG_USB_MUSB_OTG=y | ||
| 125 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 126 | CONFIG_USB_STORAGE=y | ||
| 127 | CONFIG_USB_TEST=y | ||
| 128 | CONFIG_USB_GADGET=y | ||
| 129 | CONFIG_USB_ETH=m | ||
| 130 | CONFIG_USB_GADGETFS=m | ||
| 131 | CONFIG_USB_FILE_STORAGE=m | ||
| 132 | CONFIG_USB_G_SERIAL=m | ||
| 133 | CONFIG_USB_CDC_COMPOSITE=m | ||
| 134 | CONFIG_MMC=y | ||
| 135 | CONFIG_MMC_UNSAFE_RESUME=y | ||
| 136 | CONFIG_SDIO_UART=y | ||
| 137 | CONFIG_MMC_OMAP_HS=y | ||
| 138 | CONFIG_NEW_LEDS=y | ||
| 139 | CONFIG_LEDS_CLASS=y | ||
| 140 | CONFIG_LEDS_GPIO=y | ||
| 141 | CONFIG_LEDS_TRIGGERS=y | ||
| 142 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 143 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 144 | CONFIG_RTC_CLASS=y | ||
| 145 | CONFIG_RTC_DRV_TWL4030=y | ||
| 146 | CONFIG_EXT2_FS=y | ||
| 147 | CONFIG_EXT3_FS=y | ||
| 148 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 149 | CONFIG_INOTIFY=y | ||
| 150 | CONFIG_QUOTA=y | ||
| 151 | CONFIG_QFMT_V2=y | ||
| 152 | CONFIG_MSDOS_FS=y | ||
| 153 | CONFIG_VFAT_FS=y | ||
| 154 | CONFIG_TMPFS=y | ||
| 155 | CONFIG_JFFS2_FS=y | ||
| 156 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 157 | CONFIG_NFS_FS=y | ||
| 158 | CONFIG_NFS_V3=y | ||
| 159 | CONFIG_NFS_V4=y | ||
| 160 | CONFIG_ROOT_NFS=y | ||
| 161 | CONFIG_PARTITION_ADVANCED=y | ||
| 162 | CONFIG_NLS_CODEPAGE_437=y | ||
| 163 | CONFIG_NLS_ISO8859_1=y | ||
| 164 | CONFIG_MAGIC_SYSRQ=y | ||
| 165 | CONFIG_DEBUG_FS=y | ||
| 166 | CONFIG_DEBUG_KERNEL=y | ||
| 167 | CONFIG_DEBUG_MUTEXES=y | ||
| 168 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 169 | CONFIG_DEBUG_INFO=y | ||
| 170 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 171 | # CONFIG_FTRACE is not set | ||
| 172 | # CONFIG_ARM_UNWIND is not set | ||
| 173 | CONFIG_DEBUG_LL=y | ||
| 174 | CONFIG_CRYPTO_ECB=m | ||
| 175 | CONFIG_CRYPTO_PCBC=m | ||
| 176 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 177 | CONFIG_CRC_CCITT=y | ||
| 178 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/omap_3630sdp_defconfig b/arch/arm/configs/omap_3630sdp_defconfig deleted file mode 100644 index 8e8f4e94609c..000000000000 --- a/arch/arm/configs/omap_3630sdp_defconfig +++ /dev/null | |||
| @@ -1,154 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 5 | CONFIG_BLK_DEV_INITRD=y | ||
| 6 | CONFIG_EMBEDDED=y | ||
| 7 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 8 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 9 | CONFIG_SLAB=y | ||
| 10 | CONFIG_MODULES=y | ||
| 11 | CONFIG_MODULE_UNLOAD=y | ||
| 12 | CONFIG_MODVERSIONS=y | ||
| 13 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 14 | # CONFIG_BLK_DEV_BSG is not set | ||
| 15 | CONFIG_ARCH_OMAP=y | ||
| 16 | CONFIG_ARCH_OMAP3=y | ||
| 17 | CONFIG_OMAP_MUX_DEBUG=y | ||
| 18 | CONFIG_OMAP_32K_TIMER=y | ||
| 19 | CONFIG_OMAP_DM_TIMER=y | ||
| 20 | CONFIG_ARCH_OMAP3430=y | ||
| 21 | CONFIG_MACH_OMAP_3630SDP=y | ||
| 22 | CONFIG_NO_HZ=y | ||
| 23 | CONFIG_HIGH_RES_TIMERS=y | ||
| 24 | CONFIG_AEABI=y | ||
| 25 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 26 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 27 | CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" | ||
| 28 | CONFIG_FPE_NWFPE=y | ||
| 29 | CONFIG_VFP=y | ||
| 30 | CONFIG_BINFMT_MISC=y | ||
| 31 | CONFIG_PM=y | ||
| 32 | CONFIG_PM_DEBUG=y | ||
| 33 | CONFIG_PM_VERBOSE=y | ||
| 34 | CONFIG_PM_RUNTIME=y | ||
| 35 | CONFIG_NET=y | ||
| 36 | CONFIG_PACKET=y | ||
| 37 | CONFIG_UNIX=y | ||
| 38 | CONFIG_XFRM_USER=y | ||
| 39 | CONFIG_NET_KEY=y | ||
| 40 | CONFIG_NET_KEY_MIGRATE=y | ||
| 41 | CONFIG_INET=y | ||
| 42 | CONFIG_IP_MULTICAST=y | ||
| 43 | CONFIG_IP_PNP=y | ||
| 44 | CONFIG_IP_PNP_DHCP=y | ||
| 45 | CONFIG_IP_PNP_BOOTP=y | ||
| 46 | CONFIG_IP_PNP_RARP=y | ||
| 47 | # CONFIG_INET_LRO is not set | ||
| 48 | # CONFIG_IPV6 is not set | ||
| 49 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 50 | # CONFIG_FW_LOADER is not set | ||
| 51 | CONFIG_CONNECTOR=y | ||
| 52 | CONFIG_BLK_DEV_LOOP=y | ||
| 53 | CONFIG_BLK_DEV_RAM=y | ||
| 54 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 55 | CONFIG_SCSI=y | ||
| 56 | CONFIG_BLK_DEV_SD=y | ||
| 57 | CONFIG_NETDEVICES=y | ||
| 58 | CONFIG_PHYLIB=y | ||
| 59 | CONFIG_SMSC_PHY=y | ||
| 60 | CONFIG_NET_ETHERNET=y | ||
| 61 | CONFIG_SMC91X=y | ||
| 62 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 63 | CONFIG_INPUT_EVDEV=y | ||
| 64 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 65 | # CONFIG_INPUT_MOUSE is not set | ||
| 66 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 67 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 68 | # CONFIG_SERIO is not set | ||
| 69 | CONFIG_SERIAL_8250=y | ||
| 70 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 71 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 72 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 73 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 74 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 75 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 76 | CONFIG_SERIAL_8250_RSA=y | ||
| 77 | # CONFIG_LEGACY_PTYS is not set | ||
| 78 | CONFIG_HW_RANDOM=y | ||
| 79 | CONFIG_I2C=y | ||
| 80 | CONFIG_I2C_CHARDEV=y | ||
| 81 | CONFIG_I2C_OMAP=y | ||
| 82 | CONFIG_SPI=y | ||
| 83 | CONFIG_SPI_OMAP24XX=y | ||
| 84 | CONFIG_GPIO_TWL4030=y | ||
| 85 | CONFIG_W1=y | ||
| 86 | CONFIG_POWER_SUPPLY=y | ||
| 87 | # CONFIG_HWMON is not set | ||
| 88 | CONFIG_WATCHDOG=y | ||
| 89 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 90 | CONFIG_TWL4030_CORE=y | ||
| 91 | CONFIG_REGULATOR=y | ||
| 92 | CONFIG_REGULATOR_TWL4030=y | ||
| 93 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 94 | # CONFIG_VGA_CONSOLE is not set | ||
| 95 | CONFIG_SOUND=y | ||
| 96 | CONFIG_SND=y | ||
| 97 | CONFIG_USB=y | ||
| 98 | CONFIG_USB_DEBUG=y | ||
| 99 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 100 | CONFIG_USB_DEVICEFS=y | ||
| 101 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 102 | CONFIG_USB_SUSPEND=y | ||
| 103 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 104 | CONFIG_USB_MON=y | ||
| 105 | CONFIG_USB_MUSB_HDRC=y | ||
| 106 | CONFIG_USB_MUSB_OTG=y | ||
| 107 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 108 | CONFIG_USB_MUSB_DEBUG=y | ||
| 109 | CONFIG_USB_STORAGE=y | ||
| 110 | CONFIG_USB_TEST=m | ||
| 111 | CONFIG_USB_GADGET=m | ||
| 112 | CONFIG_USB_GADGET_DEBUG=y | ||
| 113 | CONFIG_USB_GADGET_DEBUG_FILES=y | ||
| 114 | CONFIG_USB_ZERO=m | ||
| 115 | CONFIG_USB_AUDIO=m | ||
| 116 | CONFIG_USB_ETH=m | ||
| 117 | CONFIG_USB_GADGETFS=m | ||
| 118 | CONFIG_USB_FILE_STORAGE=m | ||
| 119 | CONFIG_USB_G_SERIAL=m | ||
| 120 | CONFIG_USB_CDC_COMPOSITE=m | ||
| 121 | CONFIG_TWL4030_USB=y | ||
| 122 | CONFIG_MMC=y | ||
| 123 | CONFIG_MMC_OMAP_HS=y | ||
| 124 | CONFIG_RTC_CLASS=y | ||
| 125 | CONFIG_EXT2_FS=y | ||
| 126 | CONFIG_EXT3_FS=y | ||
| 127 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 128 | CONFIG_INOTIFY=y | ||
| 129 | CONFIG_QUOTA=y | ||
| 130 | CONFIG_QFMT_V2=y | ||
| 131 | CONFIG_MSDOS_FS=y | ||
| 132 | CONFIG_VFAT_FS=y | ||
| 133 | CONFIG_TMPFS=y | ||
| 134 | CONFIG_NFS_FS=y | ||
| 135 | CONFIG_NFS_V3=y | ||
| 136 | CONFIG_NFS_V3_ACL=y | ||
| 137 | CONFIG_NFS_V4=y | ||
| 138 | CONFIG_ROOT_NFS=y | ||
| 139 | CONFIG_PARTITION_ADVANCED=y | ||
| 140 | CONFIG_NLS_CODEPAGE_437=y | ||
| 141 | CONFIG_NLS_ISO8859_1=y | ||
| 142 | CONFIG_MAGIC_SYSRQ=y | ||
| 143 | CONFIG_DEBUG_KERNEL=y | ||
| 144 | CONFIG_DEBUG_MUTEXES=y | ||
| 145 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 146 | CONFIG_DEBUG_INFO=y | ||
| 147 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 148 | CONFIG_DEBUG_LL=y | ||
| 149 | CONFIG_CRYPTO_ECB=m | ||
| 150 | CONFIG_CRYPTO_PCBC=m | ||
| 151 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 152 | CONFIG_CRC_CCITT=y | ||
| 153 | CONFIG_CRC_T10DIF=y | ||
| 154 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/omap_apollon_2420_defconfig b/arch/arm/configs/omap_apollon_2420_defconfig deleted file mode 100644 index 0b24858f5d46..000000000000 --- a/arch/arm/configs/omap_apollon_2420_defconfig +++ /dev/null | |||
| @@ -1,92 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 3 | CONFIG_SYSVIPC=y | ||
| 4 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 5 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 6 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 7 | CONFIG_SLAB=y | ||
| 8 | CONFIG_MODULES=y | ||
| 9 | CONFIG_MODULE_UNLOAD=y | ||
| 10 | # CONFIG_BLK_DEV_BSG is not set | ||
| 11 | CONFIG_ARCH_OMAP=y | ||
| 12 | CONFIG_ARCH_OMAP2=y | ||
| 13 | # CONFIG_OMAP_MCBSP is not set | ||
| 14 | CONFIG_OMAP_32K_TIMER=y | ||
| 15 | CONFIG_ARCH_OMAP2420=y | ||
| 16 | CONFIG_MACH_OMAP_APOLLON=y | ||
| 17 | # CONFIG_ARM_THUMB is not set | ||
| 18 | CONFIG_PREEMPT=y | ||
| 19 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 20 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 21 | CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192" | ||
| 22 | CONFIG_VFP=y | ||
| 23 | CONFIG_NET=y | ||
| 24 | CONFIG_PACKET=y | ||
| 25 | CONFIG_UNIX=y | ||
| 26 | CONFIG_INET=y | ||
| 27 | CONFIG_IP_PNP=y | ||
| 28 | CONFIG_IP_PNP_DHCP=y | ||
| 29 | CONFIG_IP_PNP_BOOTP=y | ||
| 30 | # CONFIG_IPV6 is not set | ||
| 31 | CONFIG_MTD=y | ||
| 32 | CONFIG_MTD_CONCAT=y | ||
| 33 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 34 | CONFIG_MTD_CHAR=y | ||
| 35 | CONFIG_MTD_BLOCK=y | ||
| 36 | CONFIG_MTD_ONENAND=y | ||
| 37 | CONFIG_MTD_ONENAND_GENERIC=y | ||
| 38 | CONFIG_BLK_DEV_LOOP=y | ||
| 39 | CONFIG_NETDEVICES=y | ||
| 40 | CONFIG_NET_ETHERNET=y | ||
| 41 | CONFIG_SMC91X=y | ||
| 42 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 43 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 44 | # CONFIG_INPUT_MOUSE is not set | ||
| 45 | # CONFIG_SERIO is not set | ||
| 46 | CONFIG_SERIAL_8250=y | ||
| 47 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 48 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 49 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 50 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 51 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 52 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 53 | CONFIG_SERIAL_8250_RSA=y | ||
| 54 | # CONFIG_LEGACY_PTYS is not set | ||
| 55 | CONFIG_HW_RANDOM=y | ||
| 56 | CONFIG_SPI=y | ||
| 57 | CONFIG_SPI_OMAP24XX=y | ||
| 58 | # CONFIG_HWMON is not set | ||
| 59 | CONFIG_WATCHDOG=y | ||
| 60 | CONFIG_OMAP_WATCHDOG=y | ||
| 61 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 62 | CONFIG_FB=y | ||
| 63 | CONFIG_FIRMWARE_EDID=y | ||
| 64 | CONFIG_FB_OMAP=y | ||
| 65 | # CONFIG_VGA_CONSOLE is not set | ||
| 66 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 67 | CONFIG_FONTS=y | ||
| 68 | CONFIG_FONT_8x8=y | ||
| 69 | CONFIG_FONT_8x16=y | ||
| 70 | CONFIG_LOGO=y | ||
| 71 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 72 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 73 | # CONFIG_HID is not set | ||
| 74 | CONFIG_USB_GADGET=y | ||
| 75 | CONFIG_USB_ETH=m | ||
| 76 | CONFIG_USB_FILE_STORAGE=m | ||
| 77 | CONFIG_MMC=y | ||
| 78 | CONFIG_MMC_OMAP=y | ||
| 79 | CONFIG_EXT2_FS=y | ||
| 80 | CONFIG_AUTOFS4_FS=y | ||
| 81 | CONFIG_TMPFS=y | ||
| 82 | CONFIG_JFFS2_FS=y | ||
| 83 | CONFIG_CRAMFS=y | ||
| 84 | CONFIG_NFS_FS=y | ||
| 85 | CONFIG_NFS_V3=y | ||
| 86 | CONFIG_ROOT_NFS=y | ||
| 87 | CONFIG_DEBUG_KERNEL=y | ||
| 88 | CONFIG_DEBUG_SPINLOCK=y | ||
| 89 | CONFIG_DEBUG_MUTEXES=y | ||
| 90 | CONFIG_DEBUG_SPINLOCK_SLEEP=y | ||
| 91 | CONFIG_CRC_CCITT=y | ||
| 92 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/omap_h4_2420_defconfig b/arch/arm/configs/omap_h4_2420_defconfig deleted file mode 100644 index 858f93aac2b2..000000000000 --- a/arch/arm/configs/omap_h4_2420_defconfig +++ /dev/null | |||
| @@ -1,107 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 5 | CONFIG_BLK_DEV_INITRD=y | ||
| 6 | CONFIG_EMBEDDED=y | ||
| 7 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 8 | CONFIG_SLAB=y | ||
| 9 | CONFIG_MODULES=y | ||
| 10 | CONFIG_MODULE_UNLOAD=y | ||
| 11 | CONFIG_MODVERSIONS=y | ||
| 12 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 13 | # CONFIG_BLK_DEV_BSG is not set | ||
| 14 | CONFIG_ARCH_OMAP=y | ||
| 15 | CONFIG_ARCH_OMAP2=y | ||
| 16 | CONFIG_OMAP_MUX_DEBUG=y | ||
| 17 | CONFIG_ARCH_OMAP2420=y | ||
| 18 | CONFIG_MACH_OMAP_H4=y | ||
| 19 | CONFIG_AEABI=y | ||
| 20 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 21 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 22 | CONFIG_CMDLINE="root=/dev/ram0 rw console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192" | ||
| 23 | CONFIG_FPE_NWFPE=y | ||
| 24 | CONFIG_BINFMT_MISC=y | ||
| 25 | CONFIG_NET=y | ||
| 26 | CONFIG_PACKET=y | ||
| 27 | CONFIG_UNIX=y | ||
| 28 | CONFIG_NET_KEY=y | ||
| 29 | CONFIG_INET=y | ||
| 30 | CONFIG_IP_PNP=y | ||
| 31 | CONFIG_IP_PNP_DHCP=y | ||
| 32 | # CONFIG_IPV6 is not set | ||
| 33 | CONFIG_IRDA=y | ||
| 34 | CONFIG_IRLAN=y | ||
| 35 | CONFIG_IRCOMM=y | ||
| 36 | # CONFIG_FW_LOADER is not set | ||
| 37 | CONFIG_MTD=y | ||
| 38 | CONFIG_MTD_CONCAT=y | ||
| 39 | CONFIG_MTD_PARTITIONS=y | ||
| 40 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 41 | CONFIG_MTD_CHAR=y | ||
| 42 | CONFIG_MTD_BLOCK=y | ||
| 43 | CONFIG_MTD_CFI=y | ||
| 44 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 45 | CONFIG_BLK_DEV_LOOP=y | ||
| 46 | CONFIG_BLK_DEV_RAM=y | ||
| 47 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 48 | CONFIG_NETDEVICES=y | ||
| 49 | CONFIG_NET_ETHERNET=y | ||
| 50 | CONFIG_SMC91X=y | ||
| 51 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 52 | CONFIG_INPUT_EVDEV=y | ||
| 53 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 54 | CONFIG_KEYBOARD_OMAP=y | ||
| 55 | # CONFIG_INPUT_MOUSE is not set | ||
| 56 | # CONFIG_SERIO is not set | ||
| 57 | CONFIG_SERIAL_8250=y | ||
| 58 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 59 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 60 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 61 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 62 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 63 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 64 | CONFIG_SERIAL_8250_RSA=y | ||
| 65 | # CONFIG_LEGACY_PTYS is not set | ||
| 66 | CONFIG_I2C=y | ||
| 67 | CONFIG_I2C_OMAP=y | ||
| 68 | # CONFIG_HWMON is not set | ||
| 69 | CONFIG_WATCHDOG=y | ||
| 70 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 71 | CONFIG_OMAP_WATCHDOG=y | ||
| 72 | CONFIG_MENELAUS=y | ||
| 73 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 74 | CONFIG_FB=y | ||
| 75 | CONFIG_FIRMWARE_EDID=y | ||
| 76 | CONFIG_FB_OMAP=y | ||
| 77 | # CONFIG_VGA_CONSOLE is not set | ||
| 78 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 79 | CONFIG_LOGO=y | ||
| 80 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 81 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 82 | CONFIG_MMC=y | ||
| 83 | CONFIG_MMC_OMAP=y | ||
| 84 | CONFIG_EXT2_FS=y | ||
| 85 | CONFIG_EXT3_FS=y | ||
| 86 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 87 | CONFIG_INOTIFY=y | ||
| 88 | CONFIG_QUOTA=y | ||
| 89 | CONFIG_QFMT_V2=y | ||
| 90 | CONFIG_MSDOS_FS=y | ||
| 91 | CONFIG_VFAT_FS=y | ||
| 92 | CONFIG_TMPFS=y | ||
| 93 | CONFIG_JFFS2_FS=y | ||
| 94 | CONFIG_NFS_FS=y | ||
| 95 | CONFIG_NFS_V3=y | ||
| 96 | CONFIG_NFS_V4=y | ||
| 97 | CONFIG_ROOT_NFS=y | ||
| 98 | CONFIG_PARTITION_ADVANCED=y | ||
| 99 | CONFIG_NLS_CODEPAGE_437=y | ||
| 100 | CONFIG_MAGIC_SYSRQ=y | ||
| 101 | CONFIG_DEBUG_KERNEL=y | ||
| 102 | CONFIG_DEBUG_MUTEXES=y | ||
| 103 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 104 | CONFIG_DEBUG_LL=y | ||
| 105 | CONFIG_CRYPTO_ECB=m | ||
| 106 | CONFIG_CRYPTO_PCBC=m | ||
| 107 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/omap_ldp_defconfig b/arch/arm/configs/omap_ldp_defconfig deleted file mode 100644 index c7bb558316d5..000000000000 --- a/arch/arm/configs/omap_ldp_defconfig +++ /dev/null | |||
| @@ -1,135 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 5 | CONFIG_BLK_DEV_INITRD=y | ||
| 6 | CONFIG_EMBEDDED=y | ||
| 7 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 8 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 9 | CONFIG_SLAB=y | ||
| 10 | CONFIG_MODULES=y | ||
| 11 | CONFIG_MODULE_UNLOAD=y | ||
| 12 | CONFIG_MODVERSIONS=y | ||
| 13 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 14 | # CONFIG_BLK_DEV_BSG is not set | ||
| 15 | CONFIG_ARCH_OMAP=y | ||
| 16 | CONFIG_ARCH_OMAP3=y | ||
| 17 | CONFIG_OMAP_MUX_DEBUG=y | ||
| 18 | CONFIG_OMAP_32K_TIMER=y | ||
| 19 | CONFIG_OMAP_DM_TIMER=y | ||
| 20 | CONFIG_ARCH_OMAP3430=y | ||
| 21 | CONFIG_MACH_OMAP_LDP=y | ||
| 22 | CONFIG_NO_HZ=y | ||
| 23 | CONFIG_HIGH_RES_TIMERS=y | ||
| 24 | CONFIG_AEABI=y | ||
| 25 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 26 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 27 | CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" | ||
| 28 | CONFIG_FPE_NWFPE=y | ||
| 29 | CONFIG_VFP=y | ||
| 30 | CONFIG_BINFMT_MISC=y | ||
| 31 | CONFIG_NET=y | ||
| 32 | CONFIG_PACKET=y | ||
| 33 | CONFIG_UNIX=y | ||
| 34 | CONFIG_XFRM_USER=y | ||
| 35 | CONFIG_NET_KEY=y | ||
| 36 | CONFIG_NET_KEY_MIGRATE=y | ||
| 37 | CONFIG_INET=y | ||
| 38 | CONFIG_IP_MULTICAST=y | ||
| 39 | CONFIG_IP_PNP=y | ||
| 40 | CONFIG_IP_PNP_DHCP=y | ||
| 41 | CONFIG_IP_PNP_BOOTP=y | ||
| 42 | CONFIG_IP_PNP_RARP=y | ||
| 43 | # CONFIG_INET_LRO is not set | ||
| 44 | # CONFIG_IPV6 is not set | ||
| 45 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 46 | # CONFIG_FW_LOADER is not set | ||
| 47 | CONFIG_CONNECTOR=y | ||
| 48 | CONFIG_BLK_DEV_LOOP=y | ||
| 49 | CONFIG_BLK_DEV_RAM=y | ||
| 50 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 51 | CONFIG_SCSI=y | ||
| 52 | CONFIG_BLK_DEV_SD=y | ||
| 53 | CONFIG_NETDEVICES=y | ||
| 54 | CONFIG_SMSC_PHY=y | ||
| 55 | CONFIG_NET_ETHERNET=y | ||
| 56 | CONFIG_SMSC911X=y | ||
| 57 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 58 | CONFIG_INPUT_EVDEV=y | ||
| 59 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 60 | # CONFIG_INPUT_MOUSE is not set | ||
| 61 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 62 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 63 | # CONFIG_SERIO is not set | ||
| 64 | CONFIG_SERIAL_8250=y | ||
| 65 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 66 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 67 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 68 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 69 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 70 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 71 | CONFIG_SERIAL_8250_RSA=y | ||
| 72 | # CONFIG_LEGACY_PTYS is not set | ||
| 73 | CONFIG_HW_RANDOM=y | ||
| 74 | CONFIG_I2C=y | ||
| 75 | CONFIG_I2C_CHARDEV=y | ||
| 76 | CONFIG_I2C_OMAP=y | ||
| 77 | CONFIG_SPI=y | ||
| 78 | CONFIG_SPI_OMAP24XX=y | ||
| 79 | CONFIG_GPIO_TWL4030=y | ||
| 80 | CONFIG_W1=y | ||
| 81 | CONFIG_POWER_SUPPLY=y | ||
| 82 | # CONFIG_HWMON is not set | ||
| 83 | CONFIG_WATCHDOG=y | ||
| 84 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 85 | CONFIG_TWL4030_CORE=y | ||
| 86 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 87 | CONFIG_FB=y | ||
| 88 | CONFIG_FIRMWARE_EDID=y | ||
| 89 | CONFIG_FB_MODE_HELPERS=y | ||
| 90 | CONFIG_FB_TILEBLITTING=y | ||
| 91 | CONFIG_FB_OMAP=y | ||
| 92 | CONFIG_FB_OMAP_LCD_VGA=y | ||
| 93 | CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=4 | ||
| 94 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 95 | CONFIG_LCD_CLASS_DEVICE=y | ||
| 96 | CONFIG_LCD_PLATFORM=y | ||
| 97 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
| 98 | # CONFIG_BACKLIGHT_GENERIC is not set | ||
| 99 | # CONFIG_VGA_CONSOLE is not set | ||
| 100 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 101 | CONFIG_LOGO=y | ||
| 102 | CONFIG_SOUND=y | ||
| 103 | CONFIG_SND=y | ||
| 104 | # CONFIG_USB_SUPPORT is not set | ||
| 105 | CONFIG_MMC=y | ||
| 106 | CONFIG_RTC_CLASS=y | ||
| 107 | CONFIG_EXT2_FS=y | ||
| 108 | CONFIG_EXT3_FS=y | ||
| 109 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 110 | CONFIG_INOTIFY=y | ||
| 111 | CONFIG_QUOTA=y | ||
| 112 | CONFIG_QFMT_V2=y | ||
| 113 | CONFIG_MSDOS_FS=y | ||
| 114 | CONFIG_VFAT_FS=y | ||
| 115 | CONFIG_TMPFS=y | ||
| 116 | CONFIG_NFS_FS=y | ||
| 117 | CONFIG_NFS_V3=y | ||
| 118 | CONFIG_NFS_V3_ACL=y | ||
| 119 | CONFIG_NFS_V4=y | ||
| 120 | CONFIG_ROOT_NFS=y | ||
| 121 | CONFIG_PARTITION_ADVANCED=y | ||
| 122 | CONFIG_NLS_CODEPAGE_437=y | ||
| 123 | CONFIG_NLS_ISO8859_1=y | ||
| 124 | CONFIG_MAGIC_SYSRQ=y | ||
| 125 | CONFIG_DEBUG_KERNEL=y | ||
| 126 | CONFIG_DEBUG_MUTEXES=y | ||
| 127 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 128 | CONFIG_DEBUG_INFO=y | ||
| 129 | # CONFIG_FTRACE is not set | ||
| 130 | CONFIG_DEBUG_LL=y | ||
| 131 | CONFIG_CRYPTO_ECB=m | ||
| 132 | CONFIG_CRYPTO_PCBC=m | ||
| 133 | CONFIG_CRC_CCITT=y | ||
| 134 | CONFIG_CRC_T10DIF=y | ||
| 135 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/omap_zoom2_defconfig b/arch/arm/configs/omap_zoom2_defconfig deleted file mode 100644 index 0a7ed449cded..000000000000 --- a/arch/arm/configs/omap_zoom2_defconfig +++ /dev/null | |||
| @@ -1,143 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 5 | CONFIG_BLK_DEV_INITRD=y | ||
| 6 | CONFIG_EMBEDDED=y | ||
| 7 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 8 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 9 | CONFIG_SLAB=y | ||
| 10 | CONFIG_MODULES=y | ||
| 11 | CONFIG_MODULE_UNLOAD=y | ||
| 12 | CONFIG_MODVERSIONS=y | ||
| 13 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 14 | # CONFIG_BLK_DEV_BSG is not set | ||
| 15 | CONFIG_ARCH_OMAP=y | ||
| 16 | CONFIG_ARCH_OMAP3=y | ||
| 17 | CONFIG_OMAP_MUX_DEBUG=y | ||
| 18 | CONFIG_OMAP_32K_TIMER=y | ||
| 19 | CONFIG_OMAP_DM_TIMER=y | ||
| 20 | CONFIG_ARCH_OMAP3430=y | ||
| 21 | CONFIG_MACH_OMAP_ZOOM2=y | ||
| 22 | CONFIG_NO_HZ=y | ||
| 23 | CONFIG_HIGH_RES_TIMERS=y | ||
| 24 | CONFIG_AEABI=y | ||
| 25 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 26 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 27 | CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" | ||
| 28 | CONFIG_FPE_NWFPE=y | ||
| 29 | CONFIG_VFP=y | ||
| 30 | CONFIG_BINFMT_MISC=y | ||
| 31 | CONFIG_PM=y | ||
| 32 | CONFIG_PM_DEBUG=y | ||
| 33 | CONFIG_PM_VERBOSE=y | ||
| 34 | CONFIG_PM_RUNTIME=y | ||
| 35 | CONFIG_NET=y | ||
| 36 | CONFIG_PACKET=y | ||
| 37 | CONFIG_UNIX=y | ||
| 38 | CONFIG_XFRM_USER=y | ||
| 39 | CONFIG_NET_KEY=y | ||
| 40 | CONFIG_NET_KEY_MIGRATE=y | ||
| 41 | CONFIG_INET=y | ||
| 42 | CONFIG_IP_MULTICAST=y | ||
| 43 | CONFIG_IP_PNP=y | ||
| 44 | CONFIG_IP_PNP_DHCP=y | ||
| 45 | CONFIG_IP_PNP_BOOTP=y | ||
| 46 | CONFIG_IP_PNP_RARP=y | ||
| 47 | # CONFIG_INET_LRO is not set | ||
| 48 | # CONFIG_IPV6 is not set | ||
| 49 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 50 | # CONFIG_FW_LOADER is not set | ||
| 51 | CONFIG_CONNECTOR=y | ||
| 52 | CONFIG_BLK_DEV_LOOP=y | ||
| 53 | CONFIG_BLK_DEV_RAM=y | ||
| 54 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 55 | CONFIG_SCSI=y | ||
| 56 | CONFIG_BLK_DEV_SD=y | ||
| 57 | CONFIG_NETDEVICES=y | ||
| 58 | CONFIG_SMSC_PHY=y | ||
| 59 | CONFIG_NET_ETHERNET=y | ||
| 60 | CONFIG_SMSC911X=y | ||
| 61 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 62 | CONFIG_INPUT_EVDEV=y | ||
| 63 | CONFIG_KEYBOARD_TWL4030=y | ||
| 64 | # CONFIG_INPUT_MOUSE is not set | ||
| 65 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 66 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 67 | CONFIG_SERIAL_8250=y | ||
| 68 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 69 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 70 | CONFIG_SERIAL_8250_RUNTIME_UARTS=1 | ||
| 71 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 72 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 73 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 74 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 75 | CONFIG_SERIAL_8250_RSA=y | ||
| 76 | # CONFIG_LEGACY_PTYS is not set | ||
| 77 | CONFIG_HW_RANDOM=y | ||
| 78 | CONFIG_I2C=y | ||
| 79 | CONFIG_I2C_CHARDEV=y | ||
| 80 | CONFIG_I2C_OMAP=y | ||
| 81 | CONFIG_SPI=y | ||
| 82 | CONFIG_SPI_OMAP24XX=y | ||
| 83 | CONFIG_GPIO_TWL4030=y | ||
| 84 | CONFIG_W1=y | ||
| 85 | CONFIG_POWER_SUPPLY=y | ||
| 86 | # CONFIG_HWMON is not set | ||
| 87 | CONFIG_WATCHDOG=y | ||
| 88 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 89 | CONFIG_TWL4030_CORE=y | ||
| 90 | CONFIG_REGULATOR=y | ||
| 91 | CONFIG_REGULATOR_TWL4030=y | ||
| 92 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 93 | # CONFIG_VGA_CONSOLE is not set | ||
| 94 | CONFIG_SOUND=y | ||
| 95 | CONFIG_SND=y | ||
| 96 | CONFIG_USB=y | ||
| 97 | CONFIG_USB_DEBUG=y | ||
| 98 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 99 | CONFIG_USB_SUSPEND=y | ||
| 100 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 101 | CONFIG_USB_MON=y | ||
| 102 | CONFIG_USB_MUSB_HDRC=y | ||
| 103 | CONFIG_USB_MUSB_OTG=y | ||
| 104 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 105 | CONFIG_USB_MUSB_DEBUG=y | ||
| 106 | CONFIG_USB_GADGET=y | ||
| 107 | CONFIG_USB_GADGET_DEBUG=y | ||
| 108 | CONFIG_USB_GADGET_DEBUG_FILES=y | ||
| 109 | CONFIG_USB_ZERO=m | ||
| 110 | CONFIG_TWL4030_USB=y | ||
| 111 | CONFIG_MMC=y | ||
| 112 | CONFIG_MMC_OMAP_HS=y | ||
| 113 | CONFIG_RTC_CLASS=y | ||
| 114 | CONFIG_EXT2_FS=y | ||
| 115 | CONFIG_EXT3_FS=y | ||
| 116 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 117 | CONFIG_INOTIFY=y | ||
| 118 | CONFIG_QUOTA=y | ||
| 119 | CONFIG_QFMT_V2=y | ||
| 120 | CONFIG_MSDOS_FS=y | ||
| 121 | CONFIG_VFAT_FS=y | ||
| 122 | CONFIG_TMPFS=y | ||
| 123 | CONFIG_NFS_FS=y | ||
| 124 | CONFIG_NFS_V3=y | ||
| 125 | CONFIG_NFS_V3_ACL=y | ||
| 126 | CONFIG_NFS_V4=y | ||
| 127 | CONFIG_ROOT_NFS=y | ||
| 128 | CONFIG_PARTITION_ADVANCED=y | ||
| 129 | CONFIG_NLS_CODEPAGE_437=y | ||
| 130 | CONFIG_NLS_ISO8859_1=y | ||
| 131 | CONFIG_MAGIC_SYSRQ=y | ||
| 132 | CONFIG_DEBUG_KERNEL=y | ||
| 133 | CONFIG_DEBUG_MUTEXES=y | ||
| 134 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 135 | CONFIG_DEBUG_INFO=y | ||
| 136 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 137 | CONFIG_DEBUG_LL=y | ||
| 138 | CONFIG_CRYPTO_ECB=m | ||
| 139 | CONFIG_CRYPTO_PCBC=m | ||
| 140 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 141 | CONFIG_CRC_CCITT=y | ||
| 142 | CONFIG_CRC_T10DIF=y | ||
| 143 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/omap_zoom3_defconfig b/arch/arm/configs/omap_zoom3_defconfig deleted file mode 100644 index f8085b0b9ecb..000000000000 --- a/arch/arm/configs/omap_zoom3_defconfig +++ /dev/null | |||
| @@ -1,155 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 5 | CONFIG_BLK_DEV_INITRD=y | ||
| 6 | CONFIG_EMBEDDED=y | ||
| 7 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 8 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 9 | CONFIG_SLAB=y | ||
| 10 | CONFIG_MODULES=y | ||
| 11 | CONFIG_MODULE_UNLOAD=y | ||
| 12 | CONFIG_MODVERSIONS=y | ||
| 13 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 14 | # CONFIG_BLK_DEV_BSG is not set | ||
| 15 | CONFIG_ARCH_OMAP=y | ||
| 16 | CONFIG_ARCH_OMAP3=y | ||
| 17 | CONFIG_OMAP_MUX_DEBUG=y | ||
| 18 | CONFIG_OMAP_32K_TIMER=y | ||
| 19 | CONFIG_OMAP_DM_TIMER=y | ||
| 20 | CONFIG_ARCH_OMAP3430=y | ||
| 21 | CONFIG_MACH_OMAP_ZOOM3=y | ||
| 22 | CONFIG_NO_HZ=y | ||
| 23 | CONFIG_HIGH_RES_TIMERS=y | ||
| 24 | CONFIG_AEABI=y | ||
| 25 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 26 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 27 | CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" | ||
| 28 | CONFIG_FPE_NWFPE=y | ||
| 29 | CONFIG_VFP=y | ||
| 30 | CONFIG_BINFMT_MISC=y | ||
| 31 | CONFIG_PM=y | ||
| 32 | CONFIG_PM_DEBUG=y | ||
| 33 | CONFIG_PM_VERBOSE=y | ||
| 34 | CONFIG_PM_RUNTIME=y | ||
| 35 | CONFIG_NET=y | ||
| 36 | CONFIG_PACKET=y | ||
| 37 | CONFIG_UNIX=y | ||
| 38 | CONFIG_XFRM_USER=y | ||
| 39 | CONFIG_NET_KEY=y | ||
| 40 | CONFIG_NET_KEY_MIGRATE=y | ||
| 41 | CONFIG_INET=y | ||
| 42 | CONFIG_IP_MULTICAST=y | ||
| 43 | CONFIG_IP_PNP=y | ||
| 44 | CONFIG_IP_PNP_DHCP=y | ||
| 45 | CONFIG_IP_PNP_BOOTP=y | ||
| 46 | CONFIG_IP_PNP_RARP=y | ||
| 47 | # CONFIG_INET_LRO is not set | ||
| 48 | # CONFIG_IPV6 is not set | ||
| 49 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 50 | # CONFIG_FW_LOADER is not set | ||
| 51 | CONFIG_CONNECTOR=y | ||
| 52 | CONFIG_BLK_DEV_LOOP=y | ||
| 53 | CONFIG_BLK_DEV_RAM=y | ||
| 54 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 55 | CONFIG_SCSI=y | ||
| 56 | CONFIG_BLK_DEV_SD=y | ||
| 57 | CONFIG_NETDEVICES=y | ||
| 58 | CONFIG_SMSC_PHY=y | ||
| 59 | CONFIG_NET_ETHERNET=y | ||
| 60 | CONFIG_SMSC911X=y | ||
| 61 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 62 | CONFIG_INPUT_EVDEV=y | ||
| 63 | CONFIG_KEYBOARD_TWL4030=y | ||
| 64 | # CONFIG_INPUT_MOUSE is not set | ||
| 65 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 66 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 67 | CONFIG_SERIAL_8250=y | ||
| 68 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 69 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 70 | CONFIG_SERIAL_8250_RUNTIME_UARTS=1 | ||
| 71 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 72 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 73 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 74 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 75 | CONFIG_SERIAL_8250_RSA=y | ||
| 76 | # CONFIG_LEGACY_PTYS is not set | ||
| 77 | CONFIG_HW_RANDOM=y | ||
| 78 | CONFIG_I2C=y | ||
| 79 | CONFIG_I2C_CHARDEV=y | ||
| 80 | CONFIG_I2C_OMAP=y | ||
| 81 | CONFIG_SPI=y | ||
| 82 | CONFIG_SPI_OMAP24XX=y | ||
| 83 | CONFIG_GPIO_TWL4030=y | ||
| 84 | CONFIG_W1=y | ||
| 85 | CONFIG_POWER_SUPPLY=y | ||
| 86 | # CONFIG_HWMON is not set | ||
| 87 | CONFIG_WATCHDOG=y | ||
| 88 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 89 | CONFIG_TWL4030_CORE=y | ||
| 90 | CONFIG_REGULATOR=y | ||
| 91 | CONFIG_REGULATOR_TWL4030=y | ||
| 92 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 93 | # CONFIG_VGA_CONSOLE is not set | ||
| 94 | CONFIG_SOUND=y | ||
| 95 | CONFIG_SND=y | ||
| 96 | CONFIG_USB=y | ||
| 97 | CONFIG_USB_DEBUG=y | ||
| 98 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 99 | CONFIG_USB_DEVICEFS=y | ||
| 100 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 101 | CONFIG_USB_SUSPEND=y | ||
| 102 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 103 | CONFIG_USB_MON=y | ||
| 104 | CONFIG_USB_MUSB_HDRC=y | ||
| 105 | CONFIG_USB_MUSB_OTG=y | ||
| 106 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 107 | CONFIG_USB_MUSB_DEBUG=y | ||
| 108 | CONFIG_USB_STORAGE=y | ||
| 109 | CONFIG_USB_TEST=m | ||
| 110 | CONFIG_USB_GADGET=m | ||
| 111 | CONFIG_USB_GADGET_DEBUG=y | ||
| 112 | CONFIG_USB_GADGET_DEBUG_FILES=y | ||
| 113 | CONFIG_USB_ZERO=m | ||
| 114 | CONFIG_USB_AUDIO=m | ||
| 115 | CONFIG_USB_ETH=m | ||
| 116 | CONFIG_USB_GADGETFS=m | ||
| 117 | CONFIG_USB_FILE_STORAGE=m | ||
| 118 | CONFIG_USB_G_SERIAL=m | ||
| 119 | CONFIG_USB_CDC_COMPOSITE=m | ||
| 120 | CONFIG_TWL4030_USB=y | ||
| 121 | CONFIG_MMC=y | ||
| 122 | CONFIG_MMC_UNSAFE_RESUME=y | ||
| 123 | CONFIG_MMC_OMAP_HS=y | ||
| 124 | CONFIG_RTC_CLASS=y | ||
| 125 | CONFIG_RTC_DRV_TWL4030=y | ||
| 126 | CONFIG_EXT2_FS=y | ||
| 127 | CONFIG_EXT3_FS=y | ||
| 128 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 129 | CONFIG_INOTIFY=y | ||
| 130 | CONFIG_QUOTA=y | ||
| 131 | CONFIG_QFMT_V2=y | ||
| 132 | CONFIG_MSDOS_FS=y | ||
| 133 | CONFIG_VFAT_FS=y | ||
| 134 | CONFIG_TMPFS=y | ||
| 135 | CONFIG_NFS_FS=y | ||
| 136 | CONFIG_NFS_V3=y | ||
| 137 | CONFIG_NFS_V3_ACL=y | ||
| 138 | CONFIG_NFS_V4=y | ||
| 139 | CONFIG_ROOT_NFS=y | ||
| 140 | CONFIG_PARTITION_ADVANCED=y | ||
| 141 | CONFIG_NLS_CODEPAGE_437=y | ||
| 142 | CONFIG_NLS_ISO8859_1=y | ||
| 143 | CONFIG_MAGIC_SYSRQ=y | ||
| 144 | CONFIG_DEBUG_FS=y | ||
| 145 | CONFIG_DEBUG_KERNEL=y | ||
| 146 | CONFIG_DEBUG_MUTEXES=y | ||
| 147 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 148 | CONFIG_DEBUG_INFO=y | ||
| 149 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 150 | CONFIG_CRYPTO_ECB=m | ||
| 151 | CONFIG_CRYPTO_PCBC=m | ||
| 152 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 153 | CONFIG_CRC_CCITT=y | ||
| 154 | CONFIG_CRC_T10DIF=y | ||
| 155 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/overo_defconfig b/arch/arm/configs/overo_defconfig deleted file mode 100644 index 6fa1b14a7a9c..000000000000 --- a/arch/arm/configs/overo_defconfig +++ /dev/null | |||
| @@ -1,275 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_IKCONFIG=y | ||
| 5 | CONFIG_IKCONFIG_PROC=y | ||
| 6 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 7 | CONFIG_BLK_DEV_INITRD=y | ||
| 8 | CONFIG_EMBEDDED=y | ||
| 9 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 10 | # CONFIG_ELF_CORE is not set | ||
| 11 | # CONFIG_COMPAT_BRK is not set | ||
| 12 | CONFIG_PROFILING=y | ||
| 13 | CONFIG_OPROFILE=y | ||
| 14 | CONFIG_MODULES=y | ||
| 15 | CONFIG_MODULE_UNLOAD=y | ||
| 16 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 17 | CONFIG_MODVERSIONS=y | ||
| 18 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 19 | # CONFIG_BLK_DEV_BSG is not set | ||
| 20 | CONFIG_ARCH_OMAP=y | ||
| 21 | CONFIG_ARCH_OMAP3=y | ||
| 22 | # CONFIG_OMAP_MUX is not set | ||
| 23 | CONFIG_OMAP_32K_TIMER=y | ||
| 24 | CONFIG_OMAP_DM_TIMER=y | ||
| 25 | CONFIG_ARCH_OMAP3430=y | ||
| 26 | CONFIG_MACH_OVERO=y | ||
| 27 | CONFIG_ARM_THUMBEE=y | ||
| 28 | CONFIG_NO_HZ=y | ||
| 29 | CONFIG_HIGH_RES_TIMERS=y | ||
| 30 | CONFIG_AEABI=y | ||
| 31 | # CONFIG_OABI_COMPAT is not set | ||
| 32 | CONFIG_LEDS=y | ||
| 33 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 34 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 35 | CONFIG_CMDLINE=" debug " | ||
| 36 | CONFIG_KEXEC=y | ||
| 37 | CONFIG_CPU_FREQ=y | ||
| 38 | CONFIG_CPU_FREQ_STAT_DETAILS=y | ||
| 39 | CONFIG_CPU_FREQ_GOV_USERSPACE=y | ||
| 40 | CONFIG_CPU_FREQ_GOV_ONDEMAND=y | ||
| 41 | CONFIG_VFP=y | ||
| 42 | CONFIG_NEON=y | ||
| 43 | CONFIG_BINFMT_AOUT=m | ||
| 44 | CONFIG_BINFMT_MISC=y | ||
| 45 | CONFIG_NET=y | ||
| 46 | CONFIG_PACKET=y | ||
| 47 | CONFIG_UNIX=y | ||
| 48 | CONFIG_NET_KEY=y | ||
| 49 | CONFIG_INET=y | ||
| 50 | CONFIG_IP_PNP=y | ||
| 51 | CONFIG_IP_PNP_DHCP=y | ||
| 52 | CONFIG_IP_PNP_BOOTP=y | ||
| 53 | CONFIG_IP_PNP_RARP=y | ||
| 54 | # CONFIG_INET_LRO is not set | ||
| 55 | CONFIG_BT=y | ||
| 56 | CONFIG_BT_L2CAP=y | ||
| 57 | CONFIG_BT_SCO=y | ||
| 58 | CONFIG_BT_RFCOMM=y | ||
| 59 | CONFIG_BT_RFCOMM_TTY=y | ||
| 60 | CONFIG_BT_BNEP=y | ||
| 61 | CONFIG_BT_BNEP_MC_FILTER=y | ||
| 62 | CONFIG_BT_BNEP_PROTO_FILTER=y | ||
| 63 | CONFIG_BT_HIDP=y | ||
| 64 | CONFIG_BT_HCIUART=y | ||
| 65 | CONFIG_BT_HCIUART_H4=y | ||
| 66 | CONFIG_BT_HCIUART_BCSP=y | ||
| 67 | CONFIG_BT_HCIBCM203X=y | ||
| 68 | CONFIG_BT_HCIBPA10X=y | ||
| 69 | CONFIG_CFG80211=y | ||
| 70 | CONFIG_MAC80211=y | ||
| 71 | CONFIG_MAC80211_RC_PID=y | ||
| 72 | CONFIG_MAC80211_RC_DEFAULT_PID=y | ||
| 73 | CONFIG_MAC80211_LEDS=y | ||
| 74 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 75 | CONFIG_MTD=y | ||
| 76 | CONFIG_MTD_CONCAT=y | ||
| 77 | CONFIG_MTD_PARTITIONS=y | ||
| 78 | CONFIG_MTD_CHAR=y | ||
| 79 | CONFIG_MTD_BLOCK=y | ||
| 80 | CONFIG_MTD_NAND=y | ||
| 81 | CONFIG_BLK_DEV_LOOP=y | ||
| 82 | CONFIG_BLK_DEV_CRYPTOLOOP=m | ||
| 83 | CONFIG_BLK_DEV_RAM=y | ||
| 84 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 85 | CONFIG_CDROM_PKTCDVD=m | ||
| 86 | CONFIG_EEPROM_LEGACY=y | ||
| 87 | CONFIG_RAID_ATTRS=m | ||
| 88 | CONFIG_SCSI=y | ||
| 89 | CONFIG_BLK_DEV_SD=y | ||
| 90 | CONFIG_CHR_DEV_SG=m | ||
| 91 | CONFIG_SCSI_MULTI_LUN=y | ||
| 92 | CONFIG_MD=y | ||
| 93 | CONFIG_BLK_DEV_MD=m | ||
| 94 | CONFIG_MD_LINEAR=m | ||
| 95 | CONFIG_MD_RAID0=m | ||
| 96 | CONFIG_MD_RAID1=m | ||
| 97 | CONFIG_MD_RAID10=m | ||
| 98 | CONFIG_MD_RAID456=m | ||
| 99 | CONFIG_MD_MULTIPATH=m | ||
| 100 | CONFIG_MD_FAULTY=m | ||
| 101 | CONFIG_BLK_DEV_DM=m | ||
| 102 | CONFIG_DM_CRYPT=m | ||
| 103 | CONFIG_DM_SNAPSHOT=m | ||
| 104 | CONFIG_DM_MIRROR=m | ||
| 105 | CONFIG_DM_ZERO=m | ||
| 106 | CONFIG_DM_MULTIPATH=m | ||
| 107 | CONFIG_DM_DELAY=m | ||
| 108 | CONFIG_NETDEVICES=y | ||
| 109 | CONFIG_DUMMY=m | ||
| 110 | CONFIG_TUN=m | ||
| 111 | # CONFIG_NETDEV_1000 is not set | ||
| 112 | # CONFIG_NETDEV_10000 is not set | ||
| 113 | CONFIG_USB_ZD1201=m | ||
| 114 | CONFIG_RTL8187=m | ||
| 115 | CONFIG_HOSTAP=m | ||
| 116 | CONFIG_HOSTAP_FIRMWARE=y | ||
| 117 | CONFIG_HOSTAP_FIRMWARE_NVRAM=y | ||
| 118 | CONFIG_LIBERTAS=y | ||
| 119 | CONFIG_LIBERTAS_USB=y | ||
| 120 | CONFIG_LIBERTAS_SDIO=y | ||
| 121 | CONFIG_LIBERTAS_DEBUG=y | ||
| 122 | CONFIG_P54_COMMON=m | ||
| 123 | CONFIG_P54_USB=m | ||
| 124 | CONFIG_USB_CATC=m | ||
| 125 | CONFIG_USB_KAWETH=m | ||
| 126 | CONFIG_USB_PEGASUS=m | ||
| 127 | CONFIG_USB_RTL8150=m | ||
| 128 | CONFIG_USB_USBNET=y | ||
| 129 | CONFIG_USB_NET_DM9601=m | ||
| 130 | CONFIG_USB_NET_GL620A=m | ||
| 131 | CONFIG_USB_NET_NET1080=m | ||
| 132 | CONFIG_USB_NET_PLUSB=m | ||
| 133 | CONFIG_USB_NET_MCS7830=m | ||
| 134 | CONFIG_USB_NET_RNDIS_HOST=m | ||
| 135 | CONFIG_USB_NET_CDC_SUBSET=m | ||
| 136 | CONFIG_USB_ALI_M5632=y | ||
| 137 | CONFIG_USB_AN2720=y | ||
| 138 | CONFIG_USB_EPSON2888=y | ||
| 139 | CONFIG_USB_KC2190=y | ||
| 140 | CONFIG_USB_NET_ZAURUS=m | ||
| 141 | CONFIG_PPP=m | ||
| 142 | CONFIG_PPP_ASYNC=m | ||
| 143 | CONFIG_PPP_SYNC_TTY=m | ||
| 144 | CONFIG_PPP_DEFLATE=m | ||
| 145 | CONFIG_PPP_BSDCOMP=m | ||
| 146 | CONFIG_PPP_MPPE=m | ||
| 147 | CONFIG_PPPOE=m | ||
| 148 | CONFIG_INPUT_EVDEV=y | ||
| 149 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 150 | CONFIG_VT_HW_CONSOLE_BINDING=y | ||
| 151 | CONFIG_SERIAL_8250=y | ||
| 152 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 153 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 154 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 155 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 156 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 157 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 158 | CONFIG_SERIAL_8250_RSA=y | ||
| 159 | # CONFIG_LEGACY_PTYS is not set | ||
| 160 | CONFIG_HW_RANDOM=y | ||
| 161 | CONFIG_I2C=y | ||
| 162 | CONFIG_I2C_CHARDEV=y | ||
| 163 | CONFIG_I2C_OMAP=y | ||
| 164 | CONFIG_SPI=y | ||
| 165 | CONFIG_SPI_OMAP24XX=y | ||
| 166 | CONFIG_DEBUG_GPIO=y | ||
| 167 | CONFIG_GPIO_SYSFS=y | ||
| 168 | CONFIG_POWER_SUPPLY=m | ||
| 169 | CONFIG_WATCHDOG=y | ||
| 170 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 171 | CONFIG_DISPLAY_SUPPORT=y | ||
| 172 | # CONFIG_VGA_CONSOLE is not set | ||
| 173 | CONFIG_SOUND=y | ||
| 174 | CONFIG_SND=y | ||
| 175 | CONFIG_SND_SEQUENCER=m | ||
| 176 | CONFIG_SND_MIXER_OSS=y | ||
| 177 | CONFIG_SND_PCM_OSS=y | ||
| 178 | CONFIG_SND_SEQUENCER_OSS=y | ||
| 179 | CONFIG_SND_VERBOSE_PRINTK=y | ||
| 180 | CONFIG_SND_DEBUG=y | ||
| 181 | CONFIG_SND_USB_AUDIO=y | ||
| 182 | CONFIG_SND_USB_CAIAQ=m | ||
| 183 | CONFIG_SND_USB_CAIAQ_INPUT=y | ||
| 184 | CONFIG_SND_SOC=y | ||
| 185 | CONFIG_SND_OMAP_SOC=y | ||
| 186 | CONFIG_USB=y | ||
| 187 | CONFIG_USB_DEBUG=y | ||
| 188 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 189 | CONFIG_USB_DEVICEFS=y | ||
| 190 | CONFIG_USB_MON=y | ||
| 191 | CONFIG_USB_MUSB_HDRC=y | ||
| 192 | CONFIG_MUSB_PIO_ONLY=y | ||
| 193 | CONFIG_USB_ACM=m | ||
| 194 | CONFIG_USB_PRINTER=m | ||
| 195 | CONFIG_USB_WDM=y | ||
| 196 | CONFIG_USB_STORAGE=y | ||
| 197 | CONFIG_USB_SERIAL=m | ||
| 198 | CONFIG_USB_EMI62=m | ||
| 199 | CONFIG_USB_EMI26=m | ||
| 200 | CONFIG_USB_LEGOTOWER=m | ||
| 201 | CONFIG_USB_LCD=m | ||
| 202 | CONFIG_USB_LED=m | ||
| 203 | CONFIG_MMC=y | ||
| 204 | CONFIG_MMC_UNSAFE_RESUME=y | ||
| 205 | CONFIG_SDIO_UART=y | ||
| 206 | CONFIG_LEDS_CLASS=y | ||
| 207 | CONFIG_LEDS_GPIO=y | ||
| 208 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 209 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 210 | CONFIG_RTC_CLASS=y | ||
| 211 | CONFIG_EXT2_FS=y | ||
| 212 | CONFIG_EXT3_FS=y | ||
| 213 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 214 | CONFIG_XFS_FS=m | ||
| 215 | CONFIG_INOTIFY=y | ||
| 216 | CONFIG_QUOTA=y | ||
| 217 | CONFIG_QFMT_V2=y | ||
| 218 | CONFIG_FUSE_FS=m | ||
| 219 | CONFIG_ISO9660_FS=m | ||
| 220 | CONFIG_JOLIET=y | ||
| 221 | CONFIG_ZISOFS=y | ||
| 222 | CONFIG_UDF_FS=m | ||
| 223 | CONFIG_MSDOS_FS=y | ||
| 224 | CONFIG_VFAT_FS=y | ||
| 225 | CONFIG_TMPFS=y | ||
| 226 | CONFIG_JFFS2_FS=y | ||
| 227 | CONFIG_JFFS2_SUMMARY=y | ||
| 228 | CONFIG_JFFS2_FS_XATTR=y | ||
| 229 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 230 | CONFIG_JFFS2_LZO=y | ||
| 231 | CONFIG_JFFS2_RUBIN=y | ||
| 232 | CONFIG_NFS_FS=y | ||
| 233 | CONFIG_NFS_V3=y | ||
| 234 | CONFIG_NFS_V4=y | ||
| 235 | CONFIG_ROOT_NFS=y | ||
| 236 | CONFIG_PARTITION_ADVANCED=y | ||
| 237 | CONFIG_NLS_CODEPAGE_437=y | ||
| 238 | CONFIG_NLS_ISO8859_1=y | ||
| 239 | CONFIG_MAGIC_SYSRQ=y | ||
| 240 | CONFIG_DEBUG_FS=y | ||
| 241 | CONFIG_DEBUG_KERNEL=y | ||
| 242 | CONFIG_SCHEDSTATS=y | ||
| 243 | CONFIG_TIMER_STATS=y | ||
| 244 | CONFIG_DEBUG_MUTEXES=y | ||
| 245 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 246 | # CONFIG_FTRACE is not set | ||
| 247 | CONFIG_CRYPTO_NULL=m | ||
| 248 | CONFIG_CRYPTO_CRYPTD=m | ||
| 249 | CONFIG_CRYPTO_TEST=m | ||
| 250 | CONFIG_CRYPTO_LRW=m | ||
| 251 | CONFIG_CRYPTO_PCBC=m | ||
| 252 | CONFIG_CRYPTO_HMAC=m | ||
| 253 | CONFIG_CRYPTO_XCBC=m | ||
| 254 | CONFIG_CRYPTO_MD4=m | ||
| 255 | CONFIG_CRYPTO_MICHAEL_MIC=y | ||
| 256 | CONFIG_CRYPTO_SHA256=m | ||
| 257 | CONFIG_CRYPTO_SHA512=m | ||
| 258 | CONFIG_CRYPTO_TGR192=m | ||
| 259 | CONFIG_CRYPTO_WP512=m | ||
| 260 | CONFIG_CRYPTO_ANUBIS=m | ||
| 261 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 262 | CONFIG_CRYPTO_CAMELLIA=m | ||
| 263 | CONFIG_CRYPTO_CAST5=m | ||
| 264 | CONFIG_CRYPTO_CAST6=m | ||
| 265 | CONFIG_CRYPTO_FCRYPT=m | ||
| 266 | CONFIG_CRYPTO_KHAZAD=m | ||
| 267 | CONFIG_CRYPTO_SERPENT=m | ||
| 268 | CONFIG_CRYPTO_TEA=m | ||
| 269 | CONFIG_CRYPTO_TWOFISH=m | ||
| 270 | CONFIG_CRYPTO_DEFLATE=m | ||
| 271 | CONFIG_CRC_CCITT=y | ||
| 272 | CONFIG_CRC_T10DIF=y | ||
| 273 | CONFIG_CRC_ITU_T=y | ||
| 274 | CONFIG_CRC7=y | ||
| 275 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig deleted file mode 100644 index ffaef43ec0bb..000000000000 --- a/arch/arm/configs/rx51_defconfig +++ /dev/null | |||
| @@ -1,222 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_POSIX_MQUEUE=y | ||
| 4 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 5 | CONFIG_BLK_DEV_INITRD=y | ||
| 6 | CONFIG_EMBEDDED=y | ||
| 7 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 8 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 9 | CONFIG_SLAB=y | ||
| 10 | CONFIG_KPROBES=y | ||
| 11 | CONFIG_MODULES=y | ||
| 12 | CONFIG_MODULE_FORCE_LOAD=y | ||
| 13 | CONFIG_MODULE_UNLOAD=y | ||
| 14 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 15 | CONFIG_MODVERSIONS=y | ||
| 16 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 17 | # CONFIG_BLK_DEV_BSG is not set | ||
| 18 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 19 | CONFIG_ARCH_OMAP=y | ||
| 20 | CONFIG_ARCH_OMAP3=y | ||
| 21 | CONFIG_OMAP_RESET_CLOCKS=y | ||
| 22 | CONFIG_OMAP_MUX_DEBUG=y | ||
| 23 | CONFIG_OMAP_32K_TIMER=y | ||
| 24 | CONFIG_OMAP_DM_TIMER=y | ||
| 25 | CONFIG_ARCH_OMAP3430=y | ||
| 26 | CONFIG_MACH_NOKIA_RX51=y | ||
| 27 | CONFIG_NO_HZ=y | ||
| 28 | CONFIG_HIGH_RES_TIMERS=y | ||
| 29 | CONFIG_AEABI=y | ||
| 30 | # CONFIG_OABI_COMPAT is not set | ||
| 31 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 32 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 33 | CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0 console=ttyS2,115200n8" | ||
| 34 | CONFIG_VFP=y | ||
| 35 | CONFIG_NEON=y | ||
| 36 | CONFIG_BINFMT_MISC=y | ||
| 37 | CONFIG_PM=y | ||
| 38 | CONFIG_PM_DEBUG=y | ||
| 39 | CONFIG_PM_RUNTIME=y | ||
| 40 | CONFIG_NET=y | ||
| 41 | CONFIG_PACKET=y | ||
| 42 | CONFIG_UNIX=y | ||
| 43 | CONFIG_NET_KEY=y | ||
| 44 | CONFIG_INET=y | ||
| 45 | CONFIG_IP_PNP=y | ||
| 46 | CONFIG_IP_PNP_DHCP=y | ||
| 47 | CONFIG_IP_PNP_BOOTP=y | ||
| 48 | CONFIG_IP_PNP_RARP=y | ||
| 49 | # CONFIG_INET_LRO is not set | ||
| 50 | # CONFIG_IPV6 is not set | ||
| 51 | CONFIG_NETFILTER=y | ||
| 52 | CONFIG_IP_NF_IPTABLES=m | ||
| 53 | CONFIG_IP_NF_FILTER=m | ||
| 54 | CONFIG_PHONET=y | ||
| 55 | CONFIG_BT=m | ||
| 56 | CONFIG_BT_L2CAP=m | ||
| 57 | CONFIG_BT_SCO=m | ||
| 58 | CONFIG_BT_RFCOMM=m | ||
| 59 | CONFIG_BT_RFCOMM_TTY=y | ||
| 60 | CONFIG_BT_BNEP=m | ||
| 61 | CONFIG_BT_BNEP_MC_FILTER=y | ||
| 62 | CONFIG_BT_BNEP_PROTO_FILTER=y | ||
| 63 | CONFIG_BT_HIDP=m | ||
| 64 | CONFIG_CFG80211=y | ||
| 65 | CONFIG_MAC80211=m | ||
| 66 | CONFIG_MAC80211_RC_PID=y | ||
| 67 | # CONFIG_MAC80211_RC_MINSTREL is not set | ||
| 68 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 69 | CONFIG_MTD=y | ||
| 70 | CONFIG_MTD_CONCAT=y | ||
| 71 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 72 | CONFIG_MTD_CHAR=y | ||
| 73 | CONFIG_MTD_BLOCK=y | ||
| 74 | CONFIG_MTD_OOPS=y | ||
| 75 | CONFIG_MTD_CFI=y | ||
| 76 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 77 | CONFIG_MTD_ONENAND=y | ||
| 78 | CONFIG_MTD_ONENAND_OMAP2=y | ||
| 79 | CONFIG_MTD_UBI=y | ||
| 80 | CONFIG_BLK_DEV_LOOP=y | ||
| 81 | CONFIG_BLK_DEV_RAM=y | ||
| 82 | CONFIG_SCSI=m | ||
| 83 | CONFIG_BLK_DEV_SD=m | ||
| 84 | CONFIG_SCSI_MULTI_LUN=y | ||
| 85 | CONFIG_SCSI_SCAN_ASYNC=y | ||
| 86 | CONFIG_NETDEVICES=y | ||
| 87 | CONFIG_TUN=m | ||
| 88 | CONFIG_NET_ETHERNET=y | ||
| 89 | CONFIG_SMC91X=m | ||
| 90 | # CONFIG_NETDEV_1000 is not set | ||
| 91 | # CONFIG_NETDEV_10000 is not set | ||
| 92 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 93 | CONFIG_INPUT_EVDEV=y | ||
| 94 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 95 | CONFIG_KEYBOARD_GPIO=m | ||
| 96 | CONFIG_KEYBOARD_TWL4030=y | ||
| 97 | # CONFIG_INPUT_MOUSE is not set | ||
| 98 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 99 | CONFIG_INPUT_MISC=y | ||
| 100 | CONFIG_INPUT_TWL4030_PWRBUTTON=y | ||
| 101 | CONFIG_INPUT_UINPUT=m | ||
| 102 | # CONFIG_SERIO is not set | ||
| 103 | CONFIG_SERIAL_8250=y | ||
| 104 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 105 | # CONFIG_LEGACY_PTYS is not set | ||
| 106 | CONFIG_I2C=y | ||
| 107 | CONFIG_I2C_CHARDEV=y | ||
| 108 | CONFIG_I2C_OMAP=y | ||
| 109 | CONFIG_SPI=y | ||
| 110 | CONFIG_SPI_OMAP24XX=y | ||
| 111 | CONFIG_GPIO_SYSFS=y | ||
| 112 | CONFIG_GPIO_TWL4030=y | ||
| 113 | CONFIG_WATCHDOG=y | ||
| 114 | CONFIG_OMAP_WATCHDOG=m | ||
| 115 | CONFIG_TWL4030_WATCHDOG=m | ||
| 116 | CONFIG_TWL4030_CORE=y | ||
| 117 | CONFIG_REGULATOR=y | ||
| 118 | CONFIG_REGULATOR_TWL4030=y | ||
| 119 | CONFIG_FB=y | ||
| 120 | CONFIG_OMAP2_DSS=y | ||
| 121 | # CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set | ||
| 122 | # CONFIG_OMAP2_DSS_DPI is not set | ||
| 123 | # CONFIG_OMAP2_DSS_VENC is not set | ||
| 124 | CONFIG_OMAP2_DSS_SDI=y | ||
| 125 | CONFIG_FB_OMAP2=y | ||
| 126 | CONFIG_PANEL_ACX565AKM=y | ||
| 127 | CONFIG_DISPLAY_SUPPORT=y | ||
| 128 | # CONFIG_VGA_CONSOLE is not set | ||
| 129 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 130 | CONFIG_LOGO=y | ||
| 131 | CONFIG_SOUND=y | ||
| 132 | CONFIG_SND=y | ||
| 133 | # CONFIG_SND_USB is not set | ||
| 134 | CONFIG_SND_SOC=y | ||
| 135 | CONFIG_SND_OMAP_SOC=y | ||
| 136 | CONFIG_HID=m | ||
| 137 | CONFIG_USB_HID=m | ||
| 138 | CONFIG_HID_A4TECH=m | ||
| 139 | CONFIG_HID_APPLE=m | ||
| 140 | CONFIG_HID_BELKIN=m | ||
| 141 | CONFIG_HID_CHERRY=m | ||
| 142 | CONFIG_HID_CHICONY=m | ||
| 143 | CONFIG_HID_CYPRESS=m | ||
| 144 | CONFIG_HID_EZKEY=m | ||
| 145 | CONFIG_HID_GYRATION=m | ||
| 146 | CONFIG_HID_LOGITECH=m | ||
| 147 | CONFIG_HID_MICROSOFT=m | ||
| 148 | CONFIG_HID_MONTEREY=m | ||
| 149 | CONFIG_HID_PANTHERLORD=m | ||
| 150 | CONFIG_HID_PETALYNX=m | ||
| 151 | CONFIG_HID_SAMSUNG=m | ||
| 152 | CONFIG_HID_SONY=m | ||
| 153 | CONFIG_HID_SUNPLUS=m | ||
| 154 | CONFIG_USB=y | ||
| 155 | CONFIG_USB_DEBUG=y | ||
| 156 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 157 | CONFIG_USB_DEVICEFS=y | ||
| 158 | CONFIG_USB_SUSPEND=y | ||
| 159 | CONFIG_USB_OTG_BLACKLIST_HUB=y | ||
| 160 | CONFIG_USB_MON=y | ||
| 161 | CONFIG_USB_MUSB_HDRC=y | ||
| 162 | CONFIG_USB_MUSB_OTG=y | ||
| 163 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 164 | CONFIG_USB_STORAGE=m | ||
| 165 | CONFIG_USB_LIBUSUAL=y | ||
| 166 | CONFIG_USB_TEST=m | ||
| 167 | CONFIG_USB_GADGET=m | ||
| 168 | CONFIG_USB_GADGET_DEBUG=y | ||
| 169 | CONFIG_USB_GADGET_DEBUG_FILES=y | ||
| 170 | CONFIG_USB_GADGET_DEBUG_FS=y | ||
| 171 | CONFIG_USB_ZERO=m | ||
| 172 | CONFIG_USB_FILE_STORAGE=m | ||
| 173 | CONFIG_USB_G_NOKIA=m | ||
| 174 | CONFIG_TWL4030_USB=y | ||
| 175 | CONFIG_MMC=m | ||
| 176 | # CONFIG_MMC_BLOCK_BOUNCE is not set | ||
| 177 | CONFIG_MMC_OMAP_HS=m | ||
| 178 | CONFIG_NEW_LEDS=y | ||
| 179 | CONFIG_LEDS_CLASS=m | ||
| 180 | CONFIG_RTC_CLASS=m | ||
| 181 | CONFIG_RTC_DRV_TWL4030=m | ||
| 182 | CONFIG_EXT2_FS=m | ||
| 183 | CONFIG_EXT3_FS=m | ||
| 184 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 185 | CONFIG_INOTIFY=y | ||
| 186 | CONFIG_QUOTA=y | ||
| 187 | CONFIG_QFMT_V2=y | ||
| 188 | CONFIG_FUSE_FS=m | ||
| 189 | CONFIG_MSDOS_FS=m | ||
| 190 | CONFIG_VFAT_FS=m | ||
| 191 | CONFIG_TMPFS=y | ||
| 192 | CONFIG_UBIFS_FS=y | ||
| 193 | CONFIG_CRAMFS=y | ||
| 194 | CONFIG_NFS_FS=m | ||
| 195 | CONFIG_NFS_V3=y | ||
| 196 | CONFIG_NFS_V4=y | ||
| 197 | CONFIG_PARTITION_ADVANCED=y | ||
| 198 | CONFIG_NLS_CODEPAGE_437=y | ||
| 199 | CONFIG_NLS_ISO8859_1=y | ||
| 200 | CONFIG_PRINTK_TIME=y | ||
| 201 | CONFIG_MAGIC_SYSRQ=y | ||
| 202 | CONFIG_DEBUG_FS=y | ||
| 203 | CONFIG_DEBUG_KERNEL=y | ||
| 204 | CONFIG_TIMER_STATS=y | ||
| 205 | CONFIG_PROVE_LOCKING=y | ||
| 206 | CONFIG_LOCK_STAT=y | ||
| 207 | CONFIG_DEBUG_SPINLOCK_SLEEP=y | ||
| 208 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 209 | CONFIG_DEBUG_INFO=y | ||
| 210 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 211 | CONFIG_SECURITY=y | ||
| 212 | CONFIG_CRYPTO_CBC=y | ||
| 213 | CONFIG_CRYPTO_ECB=y | ||
| 214 | CONFIG_CRYPTO_PCBC=m | ||
| 215 | CONFIG_CRYPTO_MD5=y | ||
| 216 | CONFIG_CRYPTO_AES=y | ||
| 217 | CONFIG_CRYPTO_ARC4=y | ||
| 218 | CONFIG_CRYPTO_DES=y | ||
| 219 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 220 | CONFIG_CRC_CCITT=y | ||
| 221 | CONFIG_CRC7=m | ||
| 222 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index b18d7c28ab7a..3b02d3b944af 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig | |||
| @@ -1,3 +1,7 @@ | |||
| 1 | if ARCH_OMAP1 | ||
| 2 | |||
| 3 | menu "TI OMAP1 specific features" | ||
| 4 | |||
| 1 | comment "OMAP Core Type" | 5 | comment "OMAP Core Type" |
| 2 | depends on ARCH_OMAP1 | 6 | depends on ARCH_OMAP1 |
| 3 | 7 | ||
| @@ -224,6 +228,12 @@ config OMAP_ARM_120MHZ | |||
| 224 | help | 228 | help |
| 225 | Enable 120MHz clock for OMAP CPU. If unsure, say N. | 229 | Enable 120MHz clock for OMAP CPU. If unsure, say N. |
| 226 | 230 | ||
| 231 | config OMAP_ARM_96MHZ | ||
| 232 | bool "OMAP ARM 96 MHz CPU" | ||
| 233 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) | ||
| 234 | help | ||
| 235 | Enable 96MHz clock for OMAP CPU. If unsure, say N. | ||
| 236 | |||
| 227 | config OMAP_ARM_60MHZ | 237 | config OMAP_ARM_60MHZ |
| 228 | bool "OMAP ARM 60 MHz CPU" | 238 | bool "OMAP ARM 60 MHz CPU" |
| 229 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) | 239 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) |
| @@ -237,3 +247,6 @@ config OMAP_ARM_30MHZ | |||
| 237 | help | 247 | help |
| 238 | Enable 30MHz clock for OMAP CPU. If unsure, say N. | 248 | Enable 30MHz clock for OMAP CPU. If unsure, say N. |
| 239 | 249 | ||
| 250 | endmenu | ||
| 251 | |||
| 252 | endif | ||
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index ea231c7a550a..facfaeb1ae5c 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile | |||
| @@ -23,6 +23,9 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y) | |||
| 23 | 23 | ||
| 24 | led-y := leds.o | 24 | led-y := leds.o |
| 25 | 25 | ||
| 26 | usb-fs-$(CONFIG_USB) := usb.o | ||
| 27 | obj-y += $(usb-fs-m) $(usb-fs-y) | ||
| 28 | |||
| 26 | # Specific board support | 29 | # Specific board support |
| 27 | obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o | 30 | obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o |
| 28 | obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o | 31 | obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o |
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 0a9d61d2d229..41992ab71961 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c | |||
| @@ -235,7 +235,7 @@ static void __init ams_delta_init(void) | |||
| 235 | /* Clear latch2 (NAND, LCD, modem enable) */ | 235 | /* Clear latch2 (NAND, LCD, modem enable) */ |
| 236 | ams_delta_latch2_write(~0, 0); | 236 | ams_delta_latch2_write(~0, 0); |
| 237 | 237 | ||
| 238 | omap_usb_init(&ams_delta_usb_config); | 238 | omap1_usb_init(&ams_delta_usb_config); |
| 239 | platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); | 239 | platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); |
| 240 | 240 | ||
| 241 | #ifdef CONFIG_AMS_DELTA_FIQ | 241 | #ifdef CONFIG_AMS_DELTA_FIQ |
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 059bac60b35a..180ce79e5eac 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c | |||
| @@ -292,6 +292,18 @@ static void __init omap_fsample_init(void) | |||
| 292 | omap_cfg_reg(L3_1610_FLASH_CS2B_OE); | 292 | omap_cfg_reg(L3_1610_FLASH_CS2B_OE); |
| 293 | omap_cfg_reg(M8_1610_FLASH_CS2B_WE); | 293 | omap_cfg_reg(M8_1610_FLASH_CS2B_WE); |
| 294 | 294 | ||
| 295 | /* Mux pins for keypad */ | ||
| 296 | omap_cfg_reg(E2_7XX_KBR0); | ||
| 297 | omap_cfg_reg(J7_7XX_KBR1); | ||
| 298 | omap_cfg_reg(E1_7XX_KBR2); | ||
| 299 | omap_cfg_reg(F3_7XX_KBR3); | ||
| 300 | omap_cfg_reg(D2_7XX_KBR4); | ||
| 301 | omap_cfg_reg(C2_7XX_KBC0); | ||
| 302 | omap_cfg_reg(D3_7XX_KBC1); | ||
| 303 | omap_cfg_reg(E4_7XX_KBC2); | ||
| 304 | omap_cfg_reg(F4_7XX_KBC3); | ||
| 305 | omap_cfg_reg(E3_7XX_KBC4); | ||
| 306 | |||
| 295 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 307 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 296 | 308 | ||
| 297 | omap_board_config = fsample_config; | 309 | omap_board_config = fsample_config; |
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index 7a65684d2a15..93b9ab8fc3be 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c | |||
| @@ -72,12 +72,12 @@ static void __init omap_generic_init(void) | |||
| 72 | omap_cfg_reg(UART3_TX); | 72 | omap_cfg_reg(UART3_TX); |
| 73 | omap_cfg_reg(UART3_RX); | 73 | omap_cfg_reg(UART3_RX); |
| 74 | 74 | ||
| 75 | omap_usb_init(&generic1510_usb_config); | 75 | omap1_usb_init(&generic1510_usb_config); |
| 76 | } | 76 | } |
| 77 | #endif | 77 | #endif |
| 78 | #if defined(CONFIG_ARCH_OMAP16XX) | 78 | #if defined(CONFIG_ARCH_OMAP16XX) |
| 79 | if (!cpu_is_omap1510()) { | 79 | if (!cpu_is_omap1510()) { |
| 80 | omap_usb_init(&generic1610_usb_config); | 80 | omap1_usb_init(&generic1610_usb_config); |
| 81 | } | 81 | } |
| 82 | #endif | 82 | #endif |
| 83 | 83 | ||
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 68b2beda8b99..d2cda58bcc48 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c | |||
| @@ -292,15 +292,6 @@ static struct platform_device h2_kp_device = { | |||
| 292 | 292 | ||
| 293 | #define H2_IRDA_FIRSEL_GPIO_PIN 17 | 293 | #define H2_IRDA_FIRSEL_GPIO_PIN 17 |
| 294 | 294 | ||
| 295 | #if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE) | ||
| 296 | static int h2_transceiver_mode(struct device *dev, int state) | ||
| 297 | { | ||
| 298 | /* SIR when low, else MIR/FIR when HIGH */ | ||
| 299 | gpio_set_value(H2_IRDA_FIRSEL_GPIO_PIN, !(state & IR_SIRMODE)); | ||
| 300 | return 0; | ||
| 301 | } | ||
| 302 | #endif | ||
| 303 | |||
| 304 | static struct omap_irda_config h2_irda_data = { | 295 | static struct omap_irda_config h2_irda_data = { |
| 305 | .transceiver_cap = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE, | 296 | .transceiver_cap = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE, |
| 306 | .rx_channel = OMAP_DMA_UART3_RX, | 297 | .rx_channel = OMAP_DMA_UART3_RX, |
| @@ -437,14 +428,18 @@ static void __init h2_init(void) | |||
| 437 | /* omap_cfg_reg(U19_ARMIO1); */ /* CD */ | 428 | /* omap_cfg_reg(U19_ARMIO1); */ /* CD */ |
| 438 | omap_cfg_reg(BALLOUT_V8_ARMIO3); /* WP */ | 429 | omap_cfg_reg(BALLOUT_V8_ARMIO3); /* WP */ |
| 439 | 430 | ||
| 440 | /* Irda */ | 431 | /* Mux pins for keypad */ |
| 441 | #if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE) | 432 | omap_cfg_reg(F18_1610_KBC0); |
| 442 | omap_writel(omap_readl(FUNC_MUX_CTRL_A) | 7, FUNC_MUX_CTRL_A); | 433 | omap_cfg_reg(D20_1610_KBC1); |
| 443 | if (gpio_request(H2_IRDA_FIRSEL_GPIO_PIN, "IRDA mode") < 0) | 434 | omap_cfg_reg(D19_1610_KBC2); |
| 444 | BUG(); | 435 | omap_cfg_reg(E18_1610_KBC3); |
| 445 | gpio_direction_output(H2_IRDA_FIRSEL_GPIO_PIN, 0); | 436 | omap_cfg_reg(C21_1610_KBC4); |
| 446 | h2_irda_data.transceiver_mode = h2_transceiver_mode; | 437 | omap_cfg_reg(G18_1610_KBR0); |
| 447 | #endif | 438 | omap_cfg_reg(F19_1610_KBR1); |
| 439 | omap_cfg_reg(H14_1610_KBR2); | ||
| 440 | omap_cfg_reg(E20_1610_KBR3); | ||
| 441 | omap_cfg_reg(E19_1610_KBR4); | ||
| 442 | omap_cfg_reg(N19_1610_KBR5); | ||
| 448 | 443 | ||
| 449 | platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices)); | 444 | platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices)); |
| 450 | omap_board_config = h2_config; | 445 | omap_board_config = h2_config; |
| @@ -452,7 +447,7 @@ static void __init h2_init(void) | |||
| 452 | omap_serial_init(); | 447 | omap_serial_init(); |
| 453 | omap_register_i2c_bus(1, 100, h2_i2c_board_info, | 448 | omap_register_i2c_bus(1, 100, h2_i2c_board_info, |
| 454 | ARRAY_SIZE(h2_i2c_board_info)); | 449 | ARRAY_SIZE(h2_i2c_board_info)); |
| 455 | omap_usb_init(&h2_usb_config); | 450 | omap1_usb_init(&h2_usb_config); |
| 456 | h2_mmc_init(); | 451 | h2_mmc_init(); |
| 457 | } | 452 | } |
| 458 | 453 | ||
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 0b0825fe6751..c2ef4ff846c7 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c | |||
| @@ -397,6 +397,19 @@ static void __init h3_init(void) | |||
| 397 | /* GPIO10 pullup/down register, Enable pullup on GPIO10 */ | 397 | /* GPIO10 pullup/down register, Enable pullup on GPIO10 */ |
| 398 | omap_cfg_reg(V2_1710_GPIO10); | 398 | omap_cfg_reg(V2_1710_GPIO10); |
| 399 | 399 | ||
| 400 | /* Mux pins for keypad */ | ||
| 401 | omap_cfg_reg(F18_1610_KBC0); | ||
| 402 | omap_cfg_reg(D20_1610_KBC1); | ||
| 403 | omap_cfg_reg(D19_1610_KBC2); | ||
| 404 | omap_cfg_reg(E18_1610_KBC3); | ||
| 405 | omap_cfg_reg(C21_1610_KBC4); | ||
| 406 | omap_cfg_reg(G18_1610_KBR0); | ||
| 407 | omap_cfg_reg(F19_1610_KBR1); | ||
| 408 | omap_cfg_reg(H14_1610_KBR2); | ||
| 409 | omap_cfg_reg(E20_1610_KBR3); | ||
| 410 | omap_cfg_reg(E19_1610_KBR4); | ||
| 411 | omap_cfg_reg(N19_1610_KBR5); | ||
| 412 | |||
| 400 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 413 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 401 | spi_register_board_info(h3_spi_board_info, | 414 | spi_register_board_info(h3_spi_board_info, |
| 402 | ARRAY_SIZE(h3_spi_board_info)); | 415 | ARRAY_SIZE(h3_spi_board_info)); |
| @@ -405,7 +418,7 @@ static void __init h3_init(void) | |||
| 405 | omap_serial_init(); | 418 | omap_serial_init(); |
| 406 | omap_register_i2c_bus(1, 100, h3_i2c_board_info, | 419 | omap_register_i2c_bus(1, 100, h3_i2c_board_info, |
| 407 | ARRAY_SIZE(h3_i2c_board_info)); | 420 | ARRAY_SIZE(h3_i2c_board_info)); |
| 408 | omap_usb_init(&h3_usb_config); | 421 | omap1_usb_init(&h3_usb_config); |
| 409 | h3_mmc_init(); | 422 | h3_mmc_init(); |
| 410 | } | 423 | } |
| 411 | 424 | ||
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index d70a4f0923f5..311899ff5ffc 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c | |||
| @@ -287,7 +287,7 @@ static void __init htcherald_init(void) | |||
| 287 | htcherald_disable_watchdog(); | 287 | htcherald_disable_watchdog(); |
| 288 | 288 | ||
| 289 | htcherald_usb_enable(); | 289 | htcherald_usb_enable(); |
| 290 | omap_usb_init(&htcherald_usb_config); | 290 | omap1_usb_init(&htcherald_usb_config); |
| 291 | } | 291 | } |
| 292 | 292 | ||
| 293 | static void __init htcherald_init_irq(void) | 293 | static void __init htcherald_init_irq(void) |
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 91064b37859a..3daf87ad2576 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c | |||
| @@ -422,13 +422,13 @@ static void __init innovator_init(void) | |||
| 422 | 422 | ||
| 423 | #ifdef CONFIG_ARCH_OMAP15XX | 423 | #ifdef CONFIG_ARCH_OMAP15XX |
| 424 | if (cpu_is_omap1510()) { | 424 | if (cpu_is_omap1510()) { |
| 425 | omap_usb_init(&innovator1510_usb_config); | 425 | omap1_usb_init(&innovator1510_usb_config); |
| 426 | innovator_config[1].data = &innovator1510_lcd_config; | 426 | innovator_config[1].data = &innovator1510_lcd_config; |
| 427 | } | 427 | } |
| 428 | #endif | 428 | #endif |
| 429 | #ifdef CONFIG_ARCH_OMAP16XX | 429 | #ifdef CONFIG_ARCH_OMAP16XX |
| 430 | if (cpu_is_omap1610()) { | 430 | if (cpu_is_omap1610()) { |
| 431 | omap_usb_init(&h2_usb_config); | 431 | omap1_usb_init(&h2_usb_config); |
| 432 | innovator_config[1].data = &innovator1610_lcd_config; | 432 | innovator_config[1].data = &innovator1610_lcd_config; |
| 433 | } | 433 | } |
| 434 | #endif | 434 | #endif |
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 8c28b10f3dae..51a4539aecf5 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c | |||
| @@ -32,7 +32,6 @@ | |||
| 32 | #include <plat/board.h> | 32 | #include <plat/board.h> |
| 33 | #include <plat/keypad.h> | 33 | #include <plat/keypad.h> |
| 34 | #include <plat/common.h> | 34 | #include <plat/common.h> |
| 35 | #include <plat/dsp_common.h> | ||
| 36 | #include <plat/hwa742.h> | 35 | #include <plat/hwa742.h> |
| 37 | #include <plat/lcd_mipid.h> | 36 | #include <plat/lcd_mipid.h> |
| 38 | #include <plat/mmc.h> | 37 | #include <plat/mmc.h> |
| @@ -242,138 +241,6 @@ static inline void nokia770_mmc_init(void) | |||
| 242 | } | 241 | } |
| 243 | #endif | 242 | #endif |
| 244 | 243 | ||
| 245 | #if defined(CONFIG_OMAP_DSP) | ||
| 246 | /* | ||
| 247 | * audio power control | ||
| 248 | */ | ||
| 249 | #define HEADPHONE_GPIO 14 | ||
| 250 | #define AMPLIFIER_CTRL_GPIO 58 | ||
| 251 | |||
| 252 | static struct clk *dspxor_ck; | ||
| 253 | static DEFINE_MUTEX(audio_pwr_lock); | ||
| 254 | /* | ||
| 255 | * audio_pwr_state | ||
| 256 | * +--+-------------------------+---------------------------------------+ | ||
| 257 | * |-1|down |power-up request -> 0 | | ||
| 258 | * +--+-------------------------+---------------------------------------+ | ||
| 259 | * | 0|up |power-down(1) request -> 1 | | ||
| 260 | * | | |power-down(2) request -> (ignore) | | ||
| 261 | * +--+-------------------------+---------------------------------------+ | ||
| 262 | * | 1|up, |power-up request -> 0 | | ||
| 263 | * | |received down(1) request |power-down(2) request -> -1 | | ||
| 264 | * +--+-------------------------+---------------------------------------+ | ||
| 265 | */ | ||
| 266 | static int audio_pwr_state = -1; | ||
| 267 | |||
| 268 | static inline void aic23_power_up(void) | ||
| 269 | { | ||
| 270 | } | ||
| 271 | static inline void aic23_power_down(void) | ||
| 272 | { | ||
| 273 | } | ||
| 274 | |||
| 275 | /* | ||
| 276 | * audio_pwr_up / down should be called under audio_pwr_lock | ||
| 277 | */ | ||
| 278 | static void nokia770_audio_pwr_up(void) | ||
| 279 | { | ||
| 280 | clk_enable(dspxor_ck); | ||
| 281 | |||
| 282 | /* Turn on codec */ | ||
| 283 | aic23_power_up(); | ||
| 284 | |||
| 285 | if (gpio_get_value(HEADPHONE_GPIO)) | ||
| 286 | /* HP not connected, turn on amplifier */ | ||
| 287 | gpio_set_value(AMPLIFIER_CTRL_GPIO, 1); | ||
| 288 | else | ||
| 289 | /* HP connected, do not turn on amplifier */ | ||
| 290 | printk("HP connected\n"); | ||
| 291 | } | ||
| 292 | |||
| 293 | static void codec_delayed_power_down(struct work_struct *work) | ||
| 294 | { | ||
| 295 | mutex_lock(&audio_pwr_lock); | ||
| 296 | if (audio_pwr_state == -1) | ||
| 297 | aic23_power_down(); | ||
| 298 | clk_disable(dspxor_ck); | ||
| 299 | mutex_unlock(&audio_pwr_lock); | ||
| 300 | } | ||
| 301 | |||
| 302 | static DECLARE_DELAYED_WORK(codec_power_down_work, codec_delayed_power_down); | ||
| 303 | |||
| 304 | static void nokia770_audio_pwr_down(void) | ||
| 305 | { | ||
| 306 | /* Turn off amplifier */ | ||
| 307 | gpio_set_value(AMPLIFIER_CTRL_GPIO, 0); | ||
| 308 | |||
| 309 | /* Turn off codec: schedule delayed work */ | ||
| 310 | schedule_delayed_work(&codec_power_down_work, HZ / 20); /* 50ms */ | ||
| 311 | } | ||
| 312 | |||
| 313 | static int | ||
| 314 | nokia770_audio_pwr_up_request(struct dsp_kfunc_device *kdev, int stage) | ||
| 315 | { | ||
| 316 | mutex_lock(&audio_pwr_lock); | ||
| 317 | if (audio_pwr_state == -1) | ||
| 318 | nokia770_audio_pwr_up(); | ||
| 319 | /* force audio_pwr_state = 0, even if it was 1. */ | ||
| 320 | audio_pwr_state = 0; | ||
| 321 | mutex_unlock(&audio_pwr_lock); | ||
| 322 | return 0; | ||
| 323 | } | ||
| 324 | |||
| 325 | static int | ||
| 326 | nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage) | ||
| 327 | { | ||
| 328 | mutex_lock(&audio_pwr_lock); | ||
| 329 | switch (stage) { | ||
| 330 | case 1: | ||
| 331 | if (audio_pwr_state == 0) | ||
| 332 | audio_pwr_state = 1; | ||
| 333 | break; | ||
| 334 | case 2: | ||
| 335 | if (audio_pwr_state == 1) { | ||
| 336 | nokia770_audio_pwr_down(); | ||
| 337 | audio_pwr_state = -1; | ||
| 338 | } | ||
| 339 | break; | ||
| 340 | } | ||
| 341 | mutex_unlock(&audio_pwr_lock); | ||
| 342 | return 0; | ||
| 343 | } | ||
| 344 | |||
| 345 | static struct dsp_kfunc_device nokia770_audio_device = { | ||
| 346 | .name = "audio", | ||
| 347 | .type = DSP_KFUNC_DEV_TYPE_AUDIO, | ||
| 348 | .enable = nokia770_audio_pwr_up_request, | ||
| 349 | .disable = nokia770_audio_pwr_down_request, | ||
| 350 | }; | ||
| 351 | |||
| 352 | static __init int omap_dsp_init(void) | ||
| 353 | { | ||
| 354 | int ret; | ||
| 355 | |||
| 356 | dspxor_ck = clk_get(0, "dspxor_ck"); | ||
| 357 | if (IS_ERR(dspxor_ck)) { | ||
| 358 | printk(KERN_ERR "couldn't acquire dspxor_ck\n"); | ||
| 359 | return PTR_ERR(dspxor_ck); | ||
| 360 | } | ||
| 361 | |||
| 362 | ret = dsp_kfunc_device_register(&nokia770_audio_device); | ||
| 363 | if (ret) { | ||
| 364 | printk(KERN_ERR | ||
| 365 | "KFUNC device registration faild: %s\n", | ||
| 366 | nokia770_audio_device.name); | ||
| 367 | goto out; | ||
| 368 | } | ||
| 369 | return 0; | ||
| 370 | out: | ||
| 371 | return ret; | ||
| 372 | } | ||
| 373 | #else | ||
| 374 | #define omap_dsp_init() do {} while (0) | ||
| 375 | #endif /* CONFIG_OMAP_DSP */ | ||
| 376 | |||
| 377 | static void __init omap_nokia770_init(void) | 244 | static void __init omap_nokia770_init(void) |
| 378 | { | 245 | { |
| 379 | platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices)); | 246 | platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices)); |
| @@ -382,11 +249,10 @@ static void __init omap_nokia770_init(void) | |||
| 382 | omap_gpio_init(); | 249 | omap_gpio_init(); |
| 383 | omap_serial_init(); | 250 | omap_serial_init(); |
| 384 | omap_register_i2c_bus(1, 100, NULL, 0); | 251 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 385 | omap_dsp_init(); | ||
| 386 | hwa742_dev_init(); | 252 | hwa742_dev_init(); |
| 387 | ads7846_dev_init(); | 253 | ads7846_dev_init(); |
| 388 | mipid_dev_init(); | 254 | mipid_dev_init(); |
| 389 | omap_usb_init(&nokia770_usb_config); | 255 | omap1_usb_init(&nokia770_usb_config); |
| 390 | nokia770_mmc_init(); | 256 | nokia770_mmc_init(); |
| 391 | } | 257 | } |
| 392 | 258 | ||
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index e2a72af30890..679740cc1e90 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c | |||
| @@ -560,7 +560,7 @@ static void __init osk_init(void) | |||
| 560 | l |= (3 << 1); | 560 | l |= (3 << 1); |
| 561 | omap_writel(l, USB_TRANSCEIVER_CTRL); | 561 | omap_writel(l, USB_TRANSCEIVER_CTRL); |
| 562 | 562 | ||
| 563 | omap_usb_init(&osk_usb_config); | 563 | omap1_usb_init(&osk_usb_config); |
| 564 | 564 | ||
| 565 | /* irq for tps65010 chip */ | 565 | /* irq for tps65010 chip */ |
| 566 | /* bootloader effectively does: omap_cfg_reg(U19_1610_MPUIO1); */ | 566 | /* bootloader effectively does: omap_cfg_reg(U19_1610_MPUIO1); */ |
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 61a2321b9732..782bb257a85d 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c | |||
| @@ -213,90 +213,6 @@ static struct omap_lcd_config palmte_lcd_config __initdata = { | |||
| 213 | .ctrl_name = "internal", | 213 | .ctrl_name = "internal", |
| 214 | }; | 214 | }; |
| 215 | 215 | ||
| 216 | #ifdef CONFIG_APM | ||
| 217 | /* | ||
| 218 | * Values measured in 10 minute intervals averaged over 10 samples. | ||
| 219 | * May differ slightly from device to device but should be accurate | ||
| 220 | * enough to give basic idea of battery life left and trigger | ||
| 221 | * potential alerts. | ||
| 222 | */ | ||
| 223 | static const int palmte_battery_sample[] = { | ||
| 224 | 2194, 2157, 2138, 2120, | ||
| 225 | 2104, 2089, 2075, 2061, | ||
| 226 | 2048, 2038, 2026, 2016, | ||
| 227 | 2008, 1998, 1989, 1980, | ||
| 228 | 1970, 1958, 1945, 1928, | ||
| 229 | 1910, 1888, 1860, 1827, | ||
| 230 | 1791, 1751, 1709, 1656, | ||
| 231 | }; | ||
| 232 | |||
| 233 | #define INTERVAL 10 | ||
| 234 | #define BATTERY_HIGH_TRESHOLD 66 | ||
| 235 | #define BATTERY_LOW_TRESHOLD 33 | ||
| 236 | |||
| 237 | static void palmte_get_power_status(struct apm_power_info *info, int *battery) | ||
| 238 | { | ||
| 239 | int charging, batt, hi, lo, mid; | ||
| 240 | |||
| 241 | charging = !gpio_get_value(PALMTE_DC_GPIO); | ||
| 242 | batt = battery[0]; | ||
| 243 | if (charging) | ||
| 244 | batt -= 60; | ||
| 245 | |||
| 246 | hi = ARRAY_SIZE(palmte_battery_sample); | ||
| 247 | lo = 0; | ||
| 248 | |||
| 249 | info->battery_flag = 0; | ||
| 250 | info->units = APM_UNITS_MINS; | ||
| 251 | |||
| 252 | if (batt > palmte_battery_sample[lo]) { | ||
| 253 | info->battery_life = 100; | ||
| 254 | info->time = INTERVAL * ARRAY_SIZE(palmte_battery_sample); | ||
| 255 | } else if (batt <= palmte_battery_sample[hi - 1]) { | ||
| 256 | info->battery_life = 0; | ||
| 257 | info->time = 0; | ||
| 258 | } else { | ||
| 259 | while (hi > lo + 1) { | ||
| 260 | mid = (hi + lo) >> 1; | ||
| 261 | if (batt <= palmte_battery_sample[mid]) | ||
| 262 | lo = mid; | ||
| 263 | else | ||
| 264 | hi = mid; | ||
| 265 | } | ||
| 266 | |||
| 267 | mid = palmte_battery_sample[lo] - palmte_battery_sample[hi]; | ||
| 268 | hi = palmte_battery_sample[lo] - batt; | ||
| 269 | info->battery_life = 100 - (100 * lo + 100 * hi / mid) / | ||
| 270 | ARRAY_SIZE(palmte_battery_sample); | ||
| 271 | info->time = INTERVAL * (ARRAY_SIZE(palmte_battery_sample) - | ||
| 272 | lo) - INTERVAL * hi / mid; | ||
| 273 | } | ||
| 274 | |||
| 275 | if (charging) { | ||
| 276 | info->ac_line_status = APM_AC_ONLINE; | ||
| 277 | info->battery_status = APM_BATTERY_STATUS_CHARGING; | ||
| 278 | info->battery_flag |= APM_BATTERY_FLAG_CHARGING; | ||
| 279 | } else { | ||
| 280 | info->ac_line_status = APM_AC_OFFLINE; | ||
| 281 | if (info->battery_life > BATTERY_HIGH_TRESHOLD) | ||
| 282 | info->battery_status = APM_BATTERY_STATUS_HIGH; | ||
| 283 | else if (info->battery_life > BATTERY_LOW_TRESHOLD) | ||
| 284 | info->battery_status = APM_BATTERY_STATUS_LOW; | ||
| 285 | else | ||
| 286 | info->battery_status = APM_BATTERY_STATUS_CRITICAL; | ||
| 287 | } | ||
| 288 | |||
| 289 | if (info->battery_life > BATTERY_HIGH_TRESHOLD) | ||
| 290 | info->battery_flag |= APM_BATTERY_FLAG_HIGH; | ||
| 291 | else if (info->battery_life > BATTERY_LOW_TRESHOLD) | ||
| 292 | info->battery_flag |= APM_BATTERY_FLAG_LOW; | ||
| 293 | else | ||
| 294 | info->battery_flag |= APM_BATTERY_FLAG_CRITICAL; | ||
| 295 | } | ||
| 296 | #else | ||
| 297 | #define palmte_get_power_status NULL | ||
| 298 | #endif | ||
| 299 | |||
| 300 | static struct omap_board_config_kernel palmte_config[] __initdata = { | 216 | static struct omap_board_config_kernel palmte_config[] __initdata = { |
| 301 | { OMAP_TAG_LCD, &palmte_lcd_config }, | 217 | { OMAP_TAG_LCD, &palmte_lcd_config }, |
| 302 | }; | 218 | }; |
| @@ -359,7 +275,7 @@ static void __init omap_palmte_init(void) | |||
| 359 | spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); | 275 | spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); |
| 360 | palmte_misc_gpio_setup(); | 276 | palmte_misc_gpio_setup(); |
| 361 | omap_serial_init(); | 277 | omap_serial_init(); |
| 362 | omap_usb_init(&palmte_usb_config); | 278 | omap1_usb_init(&palmte_usb_config); |
| 363 | omap_register_i2c_bus(1, 100, NULL, 0); | 279 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 364 | } | 280 | } |
| 365 | 281 | ||
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 21c01c6afcc1..0b35ef54a64f 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c | |||
| @@ -307,7 +307,7 @@ static void __init omap_palmtt_init(void) | |||
| 307 | 307 | ||
| 308 | spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo)); | 308 | spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo)); |
| 309 | omap_serial_init(); | 309 | omap_serial_init(); |
| 310 | omap_usb_init(&palmtt_usb_config); | 310 | omap1_usb_init(&palmtt_usb_config); |
| 311 | omap_register_i2c_bus(1, 100, NULL, 0); | 311 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 312 | } | 312 | } |
| 313 | 313 | ||
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index f32492451533..66362903b6e2 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c | |||
| @@ -325,7 +325,7 @@ omap_palmz71_init(void) | |||
| 325 | 325 | ||
| 326 | spi_register_board_info(palmz71_boardinfo, | 326 | spi_register_board_info(palmz71_boardinfo, |
| 327 | ARRAY_SIZE(palmz71_boardinfo)); | 327 | ARRAY_SIZE(palmz71_boardinfo)); |
| 328 | omap_usb_init(&palmz71_usb_config); | 328 | omap1_usb_init(&palmz71_usb_config); |
| 329 | omap_serial_init(); | 329 | omap_serial_init(); |
| 330 | omap_register_i2c_bus(1, 100, NULL, 0); | 330 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 331 | palmz71_gpio_setup(0); | 331 | palmz71_gpio_setup(0); |
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 8b5ab1fcc405..34ab354758b0 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c | |||
| @@ -260,6 +260,18 @@ static void __init omap_perseus2_init(void) | |||
| 260 | omap_cfg_reg(L3_1610_FLASH_CS2B_OE); | 260 | omap_cfg_reg(L3_1610_FLASH_CS2B_OE); |
| 261 | omap_cfg_reg(M8_1610_FLASH_CS2B_WE); | 261 | omap_cfg_reg(M8_1610_FLASH_CS2B_WE); |
| 262 | 262 | ||
| 263 | /* Mux pins for keypad */ | ||
| 264 | omap_cfg_reg(E2_7XX_KBR0); | ||
| 265 | omap_cfg_reg(J7_7XX_KBR1); | ||
| 266 | omap_cfg_reg(E1_7XX_KBR2); | ||
| 267 | omap_cfg_reg(F3_7XX_KBR3); | ||
| 268 | omap_cfg_reg(D2_7XX_KBR4); | ||
| 269 | omap_cfg_reg(C2_7XX_KBC0); | ||
| 270 | omap_cfg_reg(D3_7XX_KBC1); | ||
| 271 | omap_cfg_reg(E4_7XX_KBC2); | ||
| 272 | omap_cfg_reg(F4_7XX_KBC3); | ||
| 273 | omap_cfg_reg(E3_7XX_KBC4); | ||
| 274 | |||
| 263 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 275 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 264 | 276 | ||
| 265 | omap_board_config = perseus2_config; | 277 | omap_board_config = perseus2_config; |
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 995566b862bb..2eb148b8de93 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c | |||
| @@ -392,7 +392,7 @@ static void __init omap_sx1_init(void) | |||
| 392 | omap_board_config_size = ARRAY_SIZE(sx1_config); | 392 | omap_board_config_size = ARRAY_SIZE(sx1_config); |
| 393 | omap_serial_init(); | 393 | omap_serial_init(); |
| 394 | omap_register_i2c_bus(1, 100, NULL, 0); | 394 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 395 | omap_usb_init(&sx1_usb_config); | 395 | omap1_usb_init(&sx1_usb_config); |
| 396 | sx1_mmc_init(); | 396 | sx1_mmc_init(); |
| 397 | 397 | ||
| 398 | /* turn on USB power */ | 398 | /* turn on USB power */ |
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 4c483dc1de5c..6b3cf14bc757 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c | |||
| @@ -198,7 +198,7 @@ static void __init voiceblue_init(void) | |||
| 198 | omap_board_config = voiceblue_config; | 198 | omap_board_config = voiceblue_config; |
| 199 | omap_board_config_size = ARRAY_SIZE(voiceblue_config); | 199 | omap_board_config_size = ARRAY_SIZE(voiceblue_config); |
| 200 | omap_serial_init(); | 200 | omap_serial_init(); |
| 201 | omap_usb_init(&voiceblue_usb_config); | 201 | omap1_usb_init(&voiceblue_usb_config); |
| 202 | omap_register_i2c_bus(1, 100, NULL, 0); | 202 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 203 | 203 | ||
| 204 | /* There is a good chance board is going up, so enable power LED | 204 | /* There is a good chance board is going up, so enable power LED |
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 6bbb1b8b8294..b8c7fb9d7921 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c | |||
| @@ -11,7 +11,6 @@ | |||
| 11 | * it under the terms of the GNU General Public License version 2 as | 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. | 12 | * published by the Free Software Foundation. |
| 13 | */ | 13 | */ |
| 14 | #include <linux/module.h> | ||
| 15 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
| 16 | #include <linux/list.h> | 15 | #include <linux/list.h> |
| 17 | #include <linux/errno.h> | 16 | #include <linux/errno.h> |
| @@ -34,9 +33,9 @@ | |||
| 34 | __u32 arm_idlect1_mask; | 33 | __u32 arm_idlect1_mask; |
| 35 | struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; | 34 | struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; |
| 36 | 35 | ||
| 37 | /*------------------------------------------------------------------------- | 36 | /* |
| 38 | * Omap1 specific clock functions | 37 | * Omap1 specific clock functions |
| 39 | *-------------------------------------------------------------------------*/ | 38 | */ |
| 40 | 39 | ||
| 41 | unsigned long omap1_uart_recalc(struct clk *clk) | 40 | unsigned long omap1_uart_recalc(struct clk *clk) |
| 42 | { | 41 | { |
| @@ -523,7 +522,8 @@ const struct clkops clkops_dspck = { | |||
| 523 | .disable = omap1_clk_disable_dsp_domain, | 522 | .disable = omap1_clk_disable_dsp_domain, |
| 524 | }; | 523 | }; |
| 525 | 524 | ||
| 526 | static int omap1_clk_enable_uart_functional(struct clk *clk) | 525 | /* XXX SYSC register handling does not belong in the clock framework */ |
| 526 | static int omap1_clk_enable_uart_functional_16xx(struct clk *clk) | ||
| 527 | { | 527 | { |
| 528 | int ret; | 528 | int ret; |
| 529 | struct uart_clk *uclk; | 529 | struct uart_clk *uclk; |
| @@ -539,7 +539,8 @@ static int omap1_clk_enable_uart_functional(struct clk *clk) | |||
| 539 | return ret; | 539 | return ret; |
| 540 | } | 540 | } |
| 541 | 541 | ||
| 542 | static void omap1_clk_disable_uart_functional(struct clk *clk) | 542 | /* XXX SYSC register handling does not belong in the clock framework */ |
| 543 | static void omap1_clk_disable_uart_functional_16xx(struct clk *clk) | ||
| 543 | { | 544 | { |
| 544 | struct uart_clk *uclk; | 545 | struct uart_clk *uclk; |
| 545 | 546 | ||
| @@ -550,9 +551,10 @@ static void omap1_clk_disable_uart_functional(struct clk *clk) | |||
| 550 | omap1_clk_disable_generic(clk); | 551 | omap1_clk_disable_generic(clk); |
| 551 | } | 552 | } |
| 552 | 553 | ||
| 553 | const struct clkops clkops_uart = { | 554 | /* XXX SYSC register handling does not belong in the clock framework */ |
| 554 | .enable = omap1_clk_enable_uart_functional, | 555 | const struct clkops clkops_uart_16xx = { |
| 555 | .disable = omap1_clk_disable_uart_functional, | 556 | .enable = omap1_clk_enable_uart_functional_16xx, |
| 557 | .disable = omap1_clk_disable_uart_functional_16xx, | ||
| 556 | }; | 558 | }; |
| 557 | 559 | ||
| 558 | long omap1_clk_round_rate(struct clk *clk, unsigned long rate) | 560 | long omap1_clk_round_rate(struct clk *clk, unsigned long rate) |
| @@ -572,9 +574,9 @@ int omap1_clk_set_rate(struct clk *clk, unsigned long rate) | |||
| 572 | return ret; | 574 | return ret; |
| 573 | } | 575 | } |
| 574 | 576 | ||
| 575 | /*------------------------------------------------------------------------- | 577 | /* |
| 576 | * Omap1 clock reset and init functions | 578 | * Omap1 clock reset and init functions |
| 577 | *-------------------------------------------------------------------------*/ | 579 | */ |
| 578 | 580 | ||
| 579 | #ifdef CONFIG_OMAP_RESET_CLOCKS | 581 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
| 580 | 582 | ||
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index 75d0d7d90bff..eaf09efb91ca 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h | |||
| @@ -107,7 +107,7 @@ extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; | |||
| 107 | 107 | ||
| 108 | extern const struct clkops clkops_dspck; | 108 | extern const struct clkops clkops_dspck; |
| 109 | extern const struct clkops clkops_dummy; | 109 | extern const struct clkops clkops_dummy; |
| 110 | extern const struct clkops clkops_uart; | 110 | extern const struct clkops clkops_uart_16xx; |
| 111 | extern const struct clkops clkops_generic; | 111 | extern const struct clkops clkops_generic; |
| 112 | 112 | ||
| 113 | #endif | 113 | #endif |
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index aa8558adbf1c..af54114b8f08 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c | |||
| @@ -8,6 +8,10 @@ | |||
| 8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as | 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. | 10 | * published by the Free Software Foundation. |
| 11 | * | ||
| 12 | * To do: | ||
| 13 | * - Clocks that are only available on some chips should be marked with the | ||
| 14 | * chips that they are present on. | ||
| 11 | */ | 15 | */ |
| 12 | 16 | ||
| 13 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
| @@ -23,9 +27,49 @@ | |||
| 23 | 27 | ||
| 24 | #include "clock.h" | 28 | #include "clock.h" |
| 25 | 29 | ||
| 26 | /*------------------------------------------------------------------------ | 30 | /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */ |
| 31 | #define IDL_CLKOUT_ARM_SHIFT 12 | ||
| 32 | #define IDLTIM_ARM_SHIFT 9 | ||
| 33 | #define IDLAPI_ARM_SHIFT 8 | ||
| 34 | #define IDLIF_ARM_SHIFT 6 | ||
| 35 | #define IDLLB_ARM_SHIFT 4 /* undocumented? */ | ||
| 36 | #define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */ | ||
| 37 | #define IDLPER_ARM_SHIFT 2 | ||
| 38 | #define IDLXORP_ARM_SHIFT 1 | ||
| 39 | #define IDLWDT_ARM_SHIFT 0 | ||
| 40 | |||
| 41 | /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */ | ||
| 42 | #define CONF_MOD_UART3_CLK_MODE_R 31 | ||
| 43 | #define CONF_MOD_UART2_CLK_MODE_R 30 | ||
| 44 | #define CONF_MOD_UART1_CLK_MODE_R 29 | ||
| 45 | #define CONF_MOD_MMC_SD_CLK_REQ_R 23 | ||
| 46 | #define CONF_MOD_MCBSP3_AUXON 20 | ||
| 47 | |||
| 48 | /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */ | ||
| 49 | #define CONF_MOD_SOSSI_CLK_EN_R 16 | ||
| 50 | |||
| 51 | /* Some OTG_SYSCON_2-specific bit fields */ | ||
| 52 | #define OTG_SYSCON_2_UHOST_EN_SHIFT 8 | ||
| 53 | |||
| 54 | /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */ | ||
| 55 | #define SOFT_MMC2_DPLL_REQ_SHIFT 13 | ||
| 56 | #define SOFT_MMC_DPLL_REQ_SHIFT 12 | ||
| 57 | #define SOFT_UART3_DPLL_REQ_SHIFT 11 | ||
| 58 | #define SOFT_UART2_DPLL_REQ_SHIFT 10 | ||
| 59 | #define SOFT_UART1_DPLL_REQ_SHIFT 9 | ||
| 60 | #define SOFT_USB_OTG_DPLL_REQ_SHIFT 8 | ||
| 61 | #define SOFT_CAM_DPLL_REQ_SHIFT 7 | ||
| 62 | #define SOFT_COM_MCKO_REQ_SHIFT 6 | ||
| 63 | #define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */ | ||
| 64 | #define USB_REQ_EN_SHIFT 4 | ||
| 65 | #define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */ | ||
| 66 | #define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */ | ||
| 67 | #define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */ | ||
| 68 | #define SOFT_DPLL_REQ_SHIFT 0 | ||
| 69 | |||
| 70 | /* | ||
| 27 | * Omap1 clocks | 71 | * Omap1 clocks |
| 28 | *-------------------------------------------------------------------------*/ | 72 | */ |
| 29 | 73 | ||
| 30 | static struct clk ck_ref = { | 74 | static struct clk ck_ref = { |
| 31 | .name = "ck_ref", | 75 | .name = "ck_ref", |
| @@ -54,7 +98,7 @@ static struct arm_idlect1_clk ck_dpll1out = { | |||
| 54 | .enable_bit = EN_CKOUT_ARM, | 98 | .enable_bit = EN_CKOUT_ARM, |
| 55 | .recalc = &followparent_recalc, | 99 | .recalc = &followparent_recalc, |
| 56 | }, | 100 | }, |
| 57 | .idlect_shift = 12, | 101 | .idlect_shift = IDL_CLKOUT_ARM_SHIFT, |
| 58 | }; | 102 | }; |
| 59 | 103 | ||
| 60 | static struct clk sossi_ck = { | 104 | static struct clk sossi_ck = { |
| @@ -63,7 +107,7 @@ static struct clk sossi_ck = { | |||
| 63 | .parent = &ck_dpll1out.clk, | 107 | .parent = &ck_dpll1out.clk, |
| 64 | .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, | 108 | .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, |
| 65 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), | 109 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), |
| 66 | .enable_bit = 16, | 110 | .enable_bit = CONF_MOD_SOSSI_CLK_EN_R, |
| 67 | .recalc = &omap1_sossi_recalc, | 111 | .recalc = &omap1_sossi_recalc, |
| 68 | .set_rate = &omap1_set_sossi_rate, | 112 | .set_rate = &omap1_set_sossi_rate, |
| 69 | }; | 113 | }; |
| @@ -91,7 +135,7 @@ static struct arm_idlect1_clk armper_ck = { | |||
| 91 | .round_rate = omap1_clk_round_rate_ckctl_arm, | 135 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 92 | .set_rate = omap1_clk_set_rate_ckctl_arm, | 136 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 93 | }, | 137 | }, |
| 94 | .idlect_shift = 2, | 138 | .idlect_shift = IDLPER_ARM_SHIFT, |
| 95 | }; | 139 | }; |
| 96 | 140 | ||
| 97 | /* | 141 | /* |
| @@ -118,7 +162,7 @@ static struct arm_idlect1_clk armxor_ck = { | |||
| 118 | .enable_bit = EN_XORPCK, | 162 | .enable_bit = EN_XORPCK, |
| 119 | .recalc = &followparent_recalc, | 163 | .recalc = &followparent_recalc, |
| 120 | }, | 164 | }, |
| 121 | .idlect_shift = 1, | 165 | .idlect_shift = IDLXORP_ARM_SHIFT, |
| 122 | }; | 166 | }; |
| 123 | 167 | ||
| 124 | static struct arm_idlect1_clk armtim_ck = { | 168 | static struct arm_idlect1_clk armtim_ck = { |
| @@ -131,7 +175,7 @@ static struct arm_idlect1_clk armtim_ck = { | |||
| 131 | .enable_bit = EN_TIMCK, | 175 | .enable_bit = EN_TIMCK, |
| 132 | .recalc = &followparent_recalc, | 176 | .recalc = &followparent_recalc, |
| 133 | }, | 177 | }, |
| 134 | .idlect_shift = 9, | 178 | .idlect_shift = IDLTIM_ARM_SHIFT, |
| 135 | }; | 179 | }; |
| 136 | 180 | ||
| 137 | static struct arm_idlect1_clk armwdt_ck = { | 181 | static struct arm_idlect1_clk armwdt_ck = { |
| @@ -145,7 +189,7 @@ static struct arm_idlect1_clk armwdt_ck = { | |||
| 145 | .fixed_div = 14, | 189 | .fixed_div = 14, |
| 146 | .recalc = &omap_fixed_divisor_recalc, | 190 | .recalc = &omap_fixed_divisor_recalc, |
| 147 | }, | 191 | }, |
| 148 | .idlect_shift = 0, | 192 | .idlect_shift = IDLWDT_ARM_SHIFT, |
| 149 | }; | 193 | }; |
| 150 | 194 | ||
| 151 | static struct clk arminth_ck16xx = { | 195 | static struct clk arminth_ck16xx = { |
| @@ -212,7 +256,6 @@ static struct clk dsptim_ck = { | |||
| 212 | .recalc = &followparent_recalc, | 256 | .recalc = &followparent_recalc, |
| 213 | }; | 257 | }; |
| 214 | 258 | ||
| 215 | /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ | ||
| 216 | static struct arm_idlect1_clk tc_ck = { | 259 | static struct arm_idlect1_clk tc_ck = { |
| 217 | .clk = { | 260 | .clk = { |
| 218 | .name = "tc_ck", | 261 | .name = "tc_ck", |
| @@ -224,7 +267,7 @@ static struct arm_idlect1_clk tc_ck = { | |||
| 224 | .round_rate = omap1_clk_round_rate_ckctl_arm, | 267 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 225 | .set_rate = omap1_clk_set_rate_ckctl_arm, | 268 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 226 | }, | 269 | }, |
| 227 | .idlect_shift = 6, | 270 | .idlect_shift = IDLIF_ARM_SHIFT, |
| 228 | }; | 271 | }; |
| 229 | 272 | ||
| 230 | static struct clk arminth_ck1510 = { | 273 | static struct clk arminth_ck1510 = { |
| @@ -304,7 +347,7 @@ static struct arm_idlect1_clk api_ck = { | |||
| 304 | .enable_bit = EN_APICK, | 347 | .enable_bit = EN_APICK, |
| 305 | .recalc = &followparent_recalc, | 348 | .recalc = &followparent_recalc, |
| 306 | }, | 349 | }, |
| 307 | .idlect_shift = 8, | 350 | .idlect_shift = IDLAPI_ARM_SHIFT, |
| 308 | }; | 351 | }; |
| 309 | 352 | ||
| 310 | static struct arm_idlect1_clk lb_ck = { | 353 | static struct arm_idlect1_clk lb_ck = { |
| @@ -317,7 +360,7 @@ static struct arm_idlect1_clk lb_ck = { | |||
| 317 | .enable_bit = EN_LBCK, | 360 | .enable_bit = EN_LBCK, |
| 318 | .recalc = &followparent_recalc, | 361 | .recalc = &followparent_recalc, |
| 319 | }, | 362 | }, |
| 320 | .idlect_shift = 4, | 363 | .idlect_shift = IDLLB_ARM_SHIFT, |
| 321 | }; | 364 | }; |
| 322 | 365 | ||
| 323 | static struct clk rhea1_ck = { | 366 | static struct clk rhea1_ck = { |
| @@ -359,9 +402,15 @@ static struct arm_idlect1_clk lcd_ck_1510 = { | |||
| 359 | .round_rate = omap1_clk_round_rate_ckctl_arm, | 402 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 360 | .set_rate = omap1_clk_set_rate_ckctl_arm, | 403 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 361 | }, | 404 | }, |
| 362 | .idlect_shift = 3, | 405 | .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT, |
| 363 | }; | 406 | }; |
| 364 | 407 | ||
| 408 | /* | ||
| 409 | * XXX The enable_bit here is misused - it simply switches between 12MHz | ||
| 410 | * and 48MHz. Reimplement with clksel. | ||
| 411 | * | ||
| 412 | * XXX does this need SYSC register handling? | ||
| 413 | */ | ||
| 365 | static struct clk uart1_1510 = { | 414 | static struct clk uart1_1510 = { |
| 366 | .name = "uart1_ck", | 415 | .name = "uart1_ck", |
| 367 | .ops = &clkops_null, | 416 | .ops = &clkops_null, |
| @@ -370,25 +419,37 @@ static struct clk uart1_1510 = { | |||
| 370 | .rate = 12000000, | 419 | .rate = 12000000, |
| 371 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 420 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 372 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 421 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 373 | .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ | 422 | .enable_bit = CONF_MOD_UART1_CLK_MODE_R, |
| 374 | .set_rate = &omap1_set_uart_rate, | 423 | .set_rate = &omap1_set_uart_rate, |
| 375 | .recalc = &omap1_uart_recalc, | 424 | .recalc = &omap1_uart_recalc, |
| 376 | }; | 425 | }; |
| 377 | 426 | ||
| 427 | /* | ||
| 428 | * XXX The enable_bit here is misused - it simply switches between 12MHz | ||
| 429 | * and 48MHz. Reimplement with clksel. | ||
| 430 | * | ||
| 431 | * XXX SYSC register handling does not belong in the clock framework | ||
| 432 | */ | ||
| 378 | static struct uart_clk uart1_16xx = { | 433 | static struct uart_clk uart1_16xx = { |
| 379 | .clk = { | 434 | .clk = { |
| 380 | .name = "uart1_ck", | 435 | .name = "uart1_ck", |
| 381 | .ops = &clkops_uart, | 436 | .ops = &clkops_uart_16xx, |
| 382 | /* Direct from ULPD, no real parent */ | 437 | /* Direct from ULPD, no real parent */ |
| 383 | .parent = &armper_ck.clk, | 438 | .parent = &armper_ck.clk, |
| 384 | .rate = 48000000, | 439 | .rate = 48000000, |
| 385 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 440 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 386 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 441 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 387 | .enable_bit = 29, | 442 | .enable_bit = CONF_MOD_UART1_CLK_MODE_R, |
| 388 | }, | 443 | }, |
| 389 | .sysc_addr = 0xfffb0054, | 444 | .sysc_addr = 0xfffb0054, |
| 390 | }; | 445 | }; |
| 391 | 446 | ||
| 447 | /* | ||
| 448 | * XXX The enable_bit here is misused - it simply switches between 12MHz | ||
| 449 | * and 48MHz. Reimplement with clksel. | ||
| 450 | * | ||
| 451 | * XXX does this need SYSC register handling? | ||
| 452 | */ | ||
| 392 | static struct clk uart2_ck = { | 453 | static struct clk uart2_ck = { |
| 393 | .name = "uart2_ck", | 454 | .name = "uart2_ck", |
| 394 | .ops = &clkops_null, | 455 | .ops = &clkops_null, |
| @@ -397,11 +458,17 @@ static struct clk uart2_ck = { | |||
| 397 | .rate = 12000000, | 458 | .rate = 12000000, |
| 398 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 459 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 399 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 460 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 400 | .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ | 461 | .enable_bit = CONF_MOD_UART2_CLK_MODE_R, |
| 401 | .set_rate = &omap1_set_uart_rate, | 462 | .set_rate = &omap1_set_uart_rate, |
| 402 | .recalc = &omap1_uart_recalc, | 463 | .recalc = &omap1_uart_recalc, |
| 403 | }; | 464 | }; |
| 404 | 465 | ||
| 466 | /* | ||
| 467 | * XXX The enable_bit here is misused - it simply switches between 12MHz | ||
| 468 | * and 48MHz. Reimplement with clksel. | ||
| 469 | * | ||
| 470 | * XXX does this need SYSC register handling? | ||
| 471 | */ | ||
| 405 | static struct clk uart3_1510 = { | 472 | static struct clk uart3_1510 = { |
| 406 | .name = "uart3_ck", | 473 | .name = "uart3_ck", |
| 407 | .ops = &clkops_null, | 474 | .ops = &clkops_null, |
| @@ -410,21 +477,27 @@ static struct clk uart3_1510 = { | |||
| 410 | .rate = 12000000, | 477 | .rate = 12000000, |
| 411 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 478 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 412 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 479 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 413 | .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ | 480 | .enable_bit = CONF_MOD_UART3_CLK_MODE_R, |
| 414 | .set_rate = &omap1_set_uart_rate, | 481 | .set_rate = &omap1_set_uart_rate, |
| 415 | .recalc = &omap1_uart_recalc, | 482 | .recalc = &omap1_uart_recalc, |
| 416 | }; | 483 | }; |
| 417 | 484 | ||
| 485 | /* | ||
| 486 | * XXX The enable_bit here is misused - it simply switches between 12MHz | ||
| 487 | * and 48MHz. Reimplement with clksel. | ||
| 488 | * | ||
| 489 | * XXX SYSC register handling does not belong in the clock framework | ||
| 490 | */ | ||
| 418 | static struct uart_clk uart3_16xx = { | 491 | static struct uart_clk uart3_16xx = { |
| 419 | .clk = { | 492 | .clk = { |
| 420 | .name = "uart3_ck", | 493 | .name = "uart3_ck", |
| 421 | .ops = &clkops_uart, | 494 | .ops = &clkops_uart_16xx, |
| 422 | /* Direct from ULPD, no real parent */ | 495 | /* Direct from ULPD, no real parent */ |
| 423 | .parent = &armper_ck.clk, | 496 | .parent = &armper_ck.clk, |
| 424 | .rate = 48000000, | 497 | .rate = 48000000, |
| 425 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 498 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 426 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 499 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 427 | .enable_bit = 31, | 500 | .enable_bit = CONF_MOD_UART3_CLK_MODE_R, |
| 428 | }, | 501 | }, |
| 429 | .sysc_addr = 0xfffb9854, | 502 | .sysc_addr = 0xfffb9854, |
| 430 | }; | 503 | }; |
| @@ -457,7 +530,7 @@ static struct clk usb_hhc_ck16xx = { | |||
| 457 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ | 530 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ |
| 458 | .flags = ENABLE_REG_32BIT, | 531 | .flags = ENABLE_REG_32BIT, |
| 459 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ | 532 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ |
| 460 | .enable_bit = 8 /* UHOST_EN */, | 533 | .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT |
| 461 | }; | 534 | }; |
| 462 | 535 | ||
| 463 | static struct clk usb_dc_ck = { | 536 | static struct clk usb_dc_ck = { |
| @@ -466,7 +539,7 @@ static struct clk usb_dc_ck = { | |||
| 466 | /* Direct from ULPD, no parent */ | 539 | /* Direct from ULPD, no parent */ |
| 467 | .rate = 48000000, | 540 | .rate = 48000000, |
| 468 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 541 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
| 469 | .enable_bit = 4, | 542 | .enable_bit = USB_REQ_EN_SHIFT, |
| 470 | }; | 543 | }; |
| 471 | 544 | ||
| 472 | static struct clk usb_dc_ck7xx = { | 545 | static struct clk usb_dc_ck7xx = { |
| @@ -475,7 +548,25 @@ static struct clk usb_dc_ck7xx = { | |||
| 475 | /* Direct from ULPD, no parent */ | 548 | /* Direct from ULPD, no parent */ |
| 476 | .rate = 48000000, | 549 | .rate = 48000000, |
| 477 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 550 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
| 478 | .enable_bit = 8, | 551 | .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT, |
| 552 | }; | ||
| 553 | |||
| 554 | static struct clk uart1_7xx = { | ||
| 555 | .name = "uart1_ck", | ||
| 556 | .ops = &clkops_generic, | ||
| 557 | /* Direct from ULPD, no parent */ | ||
| 558 | .rate = 12000000, | ||
| 559 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
| 560 | .enable_bit = 9, | ||
| 561 | }; | ||
| 562 | |||
| 563 | static struct clk uart2_7xx = { | ||
| 564 | .name = "uart2_ck", | ||
| 565 | .ops = &clkops_generic, | ||
| 566 | /* Direct from ULPD, no parent */ | ||
| 567 | .rate = 12000000, | ||
| 568 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
| 569 | .enable_bit = 11, | ||
| 479 | }; | 570 | }; |
| 480 | 571 | ||
| 481 | static struct clk mclk_1510 = { | 572 | static struct clk mclk_1510 = { |
| @@ -484,7 +575,7 @@ static struct clk mclk_1510 = { | |||
| 484 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | 575 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 485 | .rate = 12000000, | 576 | .rate = 12000000, |
| 486 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 577 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
| 487 | .enable_bit = 6, | 578 | .enable_bit = SOFT_COM_MCKO_REQ_SHIFT, |
| 488 | }; | 579 | }; |
| 489 | 580 | ||
| 490 | static struct clk mclk_16xx = { | 581 | static struct clk mclk_16xx = { |
| @@ -524,9 +615,13 @@ static struct clk mmc1_ck = { | |||
| 524 | .rate = 48000000, | 615 | .rate = 48000000, |
| 525 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 616 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 526 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 617 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 527 | .enable_bit = 23, | 618 | .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R, |
| 528 | }; | 619 | }; |
| 529 | 620 | ||
| 621 | /* | ||
| 622 | * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as | ||
| 623 | * CONF_MOD_MCBSP3_AUXON ?? | ||
| 624 | */ | ||
| 530 | static struct clk mmc2_ck = { | 625 | static struct clk mmc2_ck = { |
| 531 | .name = "mmc2_ck", | 626 | .name = "mmc2_ck", |
| 532 | .ops = &clkops_generic, | 627 | .ops = &clkops_generic, |
| @@ -546,7 +641,7 @@ static struct clk mmc3_ck = { | |||
| 546 | .rate = 48000000, | 641 | .rate = 48000000, |
| 547 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 642 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 548 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 643 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
| 549 | .enable_bit = 12, | 644 | .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT, |
| 550 | }; | 645 | }; |
| 551 | 646 | ||
| 552 | static struct clk virtual_ck_mpu = { | 647 | static struct clk virtual_ck_mpu = { |
| @@ -620,7 +715,9 @@ static struct omap_clk omap_clks[] = { | |||
| 620 | /* ULPD clocks */ | 715 | /* ULPD clocks */ |
| 621 | CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), | 716 | CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), |
| 622 | CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), | 717 | CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), |
| 718 | CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX), | ||
| 623 | CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), | 719 | CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), |
| 720 | CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX), | ||
| 624 | CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), | 721 | CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), |
| 625 | CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), | 722 | CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), |
| 626 | CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), | 723 | CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), |
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index 379100c17639..aa0725608fb1 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c | |||
| @@ -63,44 +63,7 @@ static void omap_init_rtc(void) | |||
| 63 | static inline void omap_init_rtc(void) {} | 63 | static inline void omap_init_rtc(void) {} |
| 64 | #endif | 64 | #endif |
| 65 | 65 | ||
| 66 | #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) | ||
| 67 | |||
| 68 | #if defined(CONFIG_ARCH_OMAP15XX) | ||
| 69 | # define OMAP1_MBOX_SIZE 0x23 | ||
| 70 | # define INT_DSP_MAILBOX1 INT_1510_DSP_MAILBOX1 | ||
| 71 | #elif defined(CONFIG_ARCH_OMAP16XX) | ||
| 72 | # define OMAP1_MBOX_SIZE 0x2f | ||
| 73 | # define INT_DSP_MAILBOX1 INT_1610_DSP_MAILBOX1 | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #define OMAP1_MBOX_BASE OMAP16XX_MAILBOX_BASE | ||
| 77 | |||
| 78 | static struct resource mbox_resources[] = { | ||
| 79 | { | ||
| 80 | .start = OMAP1_MBOX_BASE, | ||
| 81 | .end = OMAP1_MBOX_BASE + OMAP1_MBOX_SIZE, | ||
| 82 | .flags = IORESOURCE_MEM, | ||
| 83 | }, | ||
| 84 | { | ||
| 85 | .start = INT_DSP_MAILBOX1, | ||
| 86 | .flags = IORESOURCE_IRQ, | ||
| 87 | }, | ||
| 88 | }; | ||
| 89 | |||
| 90 | static struct platform_device mbox_device = { | ||
| 91 | .name = "omap1-mailbox", | ||
| 92 | .id = -1, | ||
| 93 | .num_resources = ARRAY_SIZE(mbox_resources), | ||
| 94 | .resource = mbox_resources, | ||
| 95 | }; | ||
| 96 | |||
| 97 | static inline void omap_init_mbox(void) | ||
| 98 | { | ||
| 99 | platform_device_register(&mbox_device); | ||
| 100 | } | ||
| 101 | #else | ||
| 102 | static inline void omap_init_mbox(void) { } | 66 | static inline void omap_init_mbox(void) { } |
| 103 | #endif | ||
| 104 | 67 | ||
| 105 | /*-------------------------------------------------------------------------*/ | 68 | /*-------------------------------------------------------------------------*/ |
| 106 | 69 | ||
| @@ -230,42 +193,7 @@ static inline void omap_init_spi100k(void) | |||
| 230 | 193 | ||
| 231 | /*-------------------------------------------------------------------------*/ | 194 | /*-------------------------------------------------------------------------*/ |
| 232 | 195 | ||
| 233 | #if defined(CONFIG_OMAP_STI) | ||
| 234 | |||
| 235 | #define OMAP1_STI_BASE 0xfffea000 | ||
| 236 | #define OMAP1_STI_CHANNEL_BASE (OMAP1_STI_BASE + 0x400) | ||
| 237 | |||
| 238 | static struct resource sti_resources[] = { | ||
| 239 | { | ||
| 240 | .start = OMAP1_STI_BASE, | ||
| 241 | .end = OMAP1_STI_BASE + SZ_1K - 1, | ||
| 242 | .flags = IORESOURCE_MEM, | ||
| 243 | }, | ||
| 244 | { | ||
| 245 | .start = OMAP1_STI_CHANNEL_BASE, | ||
| 246 | .end = OMAP1_STI_CHANNEL_BASE + SZ_1K - 1, | ||
| 247 | .flags = IORESOURCE_MEM, | ||
| 248 | }, | ||
| 249 | { | ||
| 250 | .start = INT_1610_STI, | ||
| 251 | .flags = IORESOURCE_IRQ, | ||
| 252 | } | ||
| 253 | }; | ||
| 254 | |||
| 255 | static struct platform_device sti_device = { | ||
| 256 | .name = "sti", | ||
| 257 | .id = -1, | ||
| 258 | .num_resources = ARRAY_SIZE(sti_resources), | ||
| 259 | .resource = sti_resources, | ||
| 260 | }; | ||
| 261 | |||
| 262 | static inline void omap_init_sti(void) | ||
| 263 | { | ||
| 264 | platform_device_register(&sti_device); | ||
| 265 | } | ||
| 266 | #else | ||
| 267 | static inline void omap_init_sti(void) {} | 196 | static inline void omap_init_sti(void) {} |
| 268 | #endif | ||
| 269 | 197 | ||
| 270 | /*-------------------------------------------------------------------------*/ | 198 | /*-------------------------------------------------------------------------*/ |
| 271 | 199 | ||
diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S index e8a8cf36b7f0..671408eb4ab4 100644 --- a/arch/arm/mach-omap1/include/mach/debug-macro.S +++ b/arch/arm/mach-omap1/include/mach/debug-macro.S | |||
| @@ -33,7 +33,7 @@ omap_uart_virt: .word 0x0 | |||
| 33 | /* Use omap_uart_phys/virt if already configured */ | 33 | /* Use omap_uart_phys/virt if already configured */ |
| 34 | 9: mrc p15, 0, \rx, c1, c0 | 34 | 9: mrc p15, 0, \rx, c1, c0 |
| 35 | tst \rx, #1 @ MMU enabled? | 35 | tst \rx, #1 @ MMU enabled? |
| 36 | ldreq \rx, =omap_uart_phys @ physical base address | 36 | ldreq \rx, =__virt_to_phys(omap_uart_phys) @ physical base address |
| 37 | ldrne \rx, =omap_uart_virt @ virtual base | 37 | ldrne \rx, =omap_uart_virt @ virtual base |
| 38 | ldr \rx, [\rx, #0] | 38 | ldr \rx, [\rx, #0] |
| 39 | cmp \rx, #0 @ is port configured? | 39 | cmp \rx, #0 @ is port configured? |
| @@ -68,11 +68,15 @@ omap_uart_virt: .word 0x0 | |||
| 68 | 68 | ||
| 69 | /* Store both phys and virt address for the uart */ | 69 | /* Store both phys and virt address for the uart */ |
| 70 | 98: add \rx, \rx, #0xff000000 @ phys base | 70 | 98: add \rx, \rx, #0xff000000 @ phys base |
| 71 | ldr \tmp, =omap_uart_phys | 71 | mrc p15, 0, \tmp, c1, c0 |
| 72 | tst \tmp, #1 @ MMU enabled? | ||
| 73 | ldreq \tmp, =__virt_to_phys(omap_uart_phys) | ||
| 74 | ldrne \tmp, =omap_uart_phys | ||
| 72 | str \rx, [\tmp, #0] | 75 | str \rx, [\tmp, #0] |
| 73 | sub \rx, \rx, #0xff000000 @ phys base | 76 | sub \rx, \rx, #0xff000000 @ phys base |
| 74 | add \rx, \rx, #0xfe000000 @ virt base | 77 | add \rx, \rx, #0xfe000000 @ virt base |
| 75 | ldr \tmp, =omap_uart_virt | 78 | ldreq \tmp, =__virt_to_phys(omap_uart_virt) |
| 79 | ldrne \tmp, =omap_uart_virt | ||
| 76 | str \rx, [\tmp, #0] | 80 | str \rx, [\tmp, #0] |
| 77 | b 9b | 81 | b 9b |
| 78 | 99: | 82 | 99: |
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c index 4f5b3da3d559..1a85a421007f 100644 --- a/arch/arm/mach-omap1/mailbox.c +++ b/arch/arm/mach-omap1/mailbox.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Mailbox reservation modules for DSP | 2 | * Mailbox reservation modules for OMAP1 |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006-2009 Nokia Corporation | 4 | * Copyright (C) 2006-2009 Nokia Corporation |
| 5 | * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | 5 | * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> |
| @@ -9,13 +9,10 @@ | |||
| 9 | * for more details. | 9 | * for more details. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/resource.h> | ||
| 14 | #include <linux/interrupt.h> | 12 | #include <linux/interrupt.h> |
| 15 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 16 | #include <linux/io.h> | 14 | #include <linux/io.h> |
| 17 | #include <plat/mailbox.h> | 15 | #include <plat/mailbox.h> |
| 18 | #include <mach/irqs.h> | ||
| 19 | 16 | ||
| 20 | #define MAILBOX_ARM2DSP1 0x00 | 17 | #define MAILBOX_ARM2DSP1 0x00 |
| 21 | #define MAILBOX_ARM2DSP1b 0x04 | 18 | #define MAILBOX_ARM2DSP1b 0x04 |
| @@ -83,7 +80,7 @@ static int omap1_mbox_fifo_full(struct omap_mbox *mbox) | |||
| 83 | struct omap_mbox1_fifo *fifo = | 80 | struct omap_mbox1_fifo *fifo = |
| 84 | &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo; | 81 | &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo; |
| 85 | 82 | ||
| 86 | return (mbox_read_reg(fifo->flag)); | 83 | return mbox_read_reg(fifo->flag); |
| 87 | } | 84 | } |
| 88 | 85 | ||
| 89 | /* irq */ | 86 | /* irq */ |
| @@ -141,47 +138,37 @@ struct omap_mbox mbox_dsp_info = { | |||
| 141 | .ops = &omap1_mbox_ops, | 138 | .ops = &omap1_mbox_ops, |
| 142 | .priv = &omap1_mbox_dsp_priv, | 139 | .priv = &omap1_mbox_dsp_priv, |
| 143 | }; | 140 | }; |
| 144 | EXPORT_SYMBOL(mbox_dsp_info); | 141 | |
| 142 | struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL }; | ||
| 145 | 143 | ||
| 146 | static int __devinit omap1_mbox_probe(struct platform_device *pdev) | 144 | static int __devinit omap1_mbox_probe(struct platform_device *pdev) |
| 147 | { | 145 | { |
| 148 | struct resource *res; | 146 | struct resource *mem; |
| 147 | int ret; | ||
| 148 | int i; | ||
| 149 | struct omap_mbox **list; | ||
| 149 | 150 | ||
| 150 | if (pdev->num_resources != 2) { | 151 | list = omap1_mboxes; |
| 151 | dev_err(&pdev->dev, "invalid number of resources: %d\n", | 152 | list[0]->irq = platform_get_irq_byname(pdev, "dsp"); |
| 152 | pdev->num_resources); | ||
| 153 | return -ENODEV; | ||
| 154 | } | ||
| 155 | 153 | ||
| 156 | /* MBOX base */ | 154 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 157 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 155 | mbox_base = ioremap(mem->start, resource_size(mem)); |
| 158 | if (unlikely(!res)) { | 156 | if (!mbox_base) |
| 159 | dev_err(&pdev->dev, "invalid mem resource\n"); | 157 | return -ENOMEM; |
| 160 | return -ENODEV; | ||
| 161 | } | ||
| 162 | 158 | ||
| 163 | mbox_base = ioremap(res->start, resource_size(res)); | 159 | ret = omap_mbox_register(&pdev->dev, list); |
| 164 | if (!mbox_base) { | 160 | if (ret) { |
| 165 | dev_err(&pdev->dev, "ioremap failed\n"); | ||
| 166 | return -ENODEV; | ||
| 167 | } | ||
| 168 | |||
| 169 | /* DSP IRQ */ | ||
| 170 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | ||
| 171 | if (unlikely(!res)) { | ||
| 172 | dev_err(&pdev->dev, "invalid irq resource\n"); | ||
| 173 | iounmap(mbox_base); | 161 | iounmap(mbox_base); |
| 174 | return -ENODEV; | 162 | return ret; |
| 175 | } | 163 | } |
| 176 | mbox_dsp_info.irq = res->start; | ||
| 177 | 164 | ||
| 178 | return omap_mbox_register(&pdev->dev, &mbox_dsp_info); | 165 | return 0; |
| 179 | } | 166 | } |
| 180 | 167 | ||
| 181 | static int __devexit omap1_mbox_remove(struct platform_device *pdev) | 168 | static int __devexit omap1_mbox_remove(struct platform_device *pdev) |
| 182 | { | 169 | { |
| 183 | omap_mbox_unregister(&mbox_dsp_info); | 170 | omap_mbox_unregister(); |
| 184 | 171 | iounmap(mbox_base); | |
| 185 | return 0; | 172 | return 0; |
| 186 | } | 173 | } |
| 187 | 174 | ||
| @@ -189,7 +176,7 @@ static struct platform_driver omap1_mbox_driver = { | |||
| 189 | .probe = omap1_mbox_probe, | 176 | .probe = omap1_mbox_probe, |
| 190 | .remove = __devexit_p(omap1_mbox_remove), | 177 | .remove = __devexit_p(omap1_mbox_remove), |
| 191 | .driver = { | 178 | .driver = { |
| 192 | .name = "omap1-mailbox", | 179 | .name = "omap-mailbox", |
| 193 | }, | 180 | }, |
| 194 | }; | 181 | }; |
| 195 | 182 | ||
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index e9bdff192f82..b3a796a6da03 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c | |||
| @@ -23,7 +23,6 @@ | |||
| 23 | #include <plat/mux.h> | 23 | #include <plat/mux.h> |
| 24 | #include <plat/cpu.h> | 24 | #include <plat/cpu.h> |
| 25 | #include <plat/mcbsp.h> | 25 | #include <plat/mcbsp.h> |
| 26 | #include <plat/dsp_common.h> | ||
| 27 | 26 | ||
| 28 | #define DPS_RSTCT2_PER_EN (1 << 0) | 27 | #define DPS_RSTCT2_PER_EN (1 << 0) |
| 29 | #define DSP_RSTCT2_WD_PER_EN (1 << 1) | 28 | #define DSP_RSTCT2_WD_PER_EN (1 << 1) |
| @@ -46,7 +45,6 @@ static void omap1_mcbsp_request(unsigned int id) | |||
| 46 | clk_enable(api_clk); | 45 | clk_enable(api_clk); |
| 47 | clk_enable(dsp_clk); | 46 | clk_enable(dsp_clk); |
| 48 | 47 | ||
| 49 | omap_dsp_request_mem(); | ||
| 50 | /* | 48 | /* |
| 51 | * DSP external peripheral reset | 49 | * DSP external peripheral reset |
| 52 | * FIXME: This should be moved to dsp code | 50 | * FIXME: This should be moved to dsp code |
| @@ -62,7 +60,6 @@ static void omap1_mcbsp_free(unsigned int id) | |||
| 62 | { | 60 | { |
| 63 | if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { | 61 | if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { |
| 64 | if (--dsp_use == 0) { | 62 | if (--dsp_use == 0) { |
| 65 | omap_dsp_release_mem(); | ||
| 66 | if (!IS_ERR(api_clk)) { | 63 | if (!IS_ERR(api_clk)) { |
| 67 | clk_disable(api_clk); | 64 | clk_disable(api_clk); |
| 68 | clk_put(api_clk); | 65 | clk_put(api_clk); |
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 84341377232d..7835add00344 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c | |||
| @@ -70,6 +70,10 @@ MUX_CFG_7XX("SPI_7XX_3", 6, 13, 4, 12, 1, 0) | |||
| 70 | MUX_CFG_7XX("SPI_7XX_4", 6, 17, 4, 16, 1, 0) | 70 | MUX_CFG_7XX("SPI_7XX_4", 6, 17, 4, 16, 1, 0) |
| 71 | MUX_CFG_7XX("SPI_7XX_5", 8, 25, 0, 24, 0, 0) | 71 | MUX_CFG_7XX("SPI_7XX_5", 8, 25, 0, 24, 0, 0) |
| 72 | MUX_CFG_7XX("SPI_7XX_6", 9, 5, 0, 4, 0, 0) | 72 | MUX_CFG_7XX("SPI_7XX_6", 9, 5, 0, 4, 0, 0) |
| 73 | |||
| 74 | /* UART pins */ | ||
| 75 | MUX_CFG_7XX("UART_7XX_1", 3, 21, 0, 20, 0, 0) | ||
| 76 | MUX_CFG_7XX("UART_7XX_2", 8, 1, 6, 0, 0, 0) | ||
| 73 | }; | 77 | }; |
| 74 | #define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins) | 78 | #define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins) |
| 75 | #else | 79 | #else |
| @@ -440,7 +444,7 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) | |||
| 440 | } | 444 | } |
| 441 | #endif | 445 | #endif |
| 442 | 446 | ||
| 443 | #ifdef CONFIG_OMAP_MUX_ERRORS | 447 | #ifdef CONFIG_OMAP_MUX_WARNINGS |
| 444 | return warn ? -ETXTBSY : 0; | 448 | return warn ? -ETXTBSY : 0; |
| 445 | #else | 449 | #else |
| 446 | return 0; | 450 | return 0; |
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index 349de90194e3..b78d0749f13d 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c | |||
| @@ -122,6 +122,13 @@ void __init omap_serial_init(void) | |||
| 122 | 122 | ||
| 123 | for (i = 0; i < ARRAY_SIZE(serial_platform_data) - 1; i++) { | 123 | for (i = 0; i < ARRAY_SIZE(serial_platform_data) - 1; i++) { |
| 124 | 124 | ||
| 125 | /* Don't look at UARTs higher than 2 for omap7xx */ | ||
| 126 | if (cpu_is_omap7xx() && i > 1) { | ||
| 127 | serial_platform_data[i].membase = NULL; | ||
| 128 | serial_platform_data[i].mapbase = 0; | ||
| 129 | continue; | ||
| 130 | } | ||
| 131 | |||
| 125 | /* Static mapping, never released */ | 132 | /* Static mapping, never released */ |
| 126 | serial_platform_data[i].membase = | 133 | serial_platform_data[i].membase = |
| 127 | ioremap(serial_platform_data[i].mapbase, SZ_2K); | 134 | ioremap(serial_platform_data[i].mapbase, SZ_2K); |
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c new file mode 100644 index 000000000000..19de03b074e3 --- /dev/null +++ b/arch/arm/mach-omap1/usb.c | |||
| @@ -0,0 +1,530 @@ | |||
| 1 | /* | ||
| 2 | * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/module.h> | ||
| 22 | #include <linux/kernel.h> | ||
| 23 | #include <linux/init.h> | ||
| 24 | #include <linux/platform_device.h> | ||
| 25 | #include <linux/io.h> | ||
| 26 | |||
| 27 | #include <asm/irq.h> | ||
| 28 | |||
| 29 | #include <plat/mux.h> | ||
| 30 | #include <plat/usb.h> | ||
| 31 | |||
| 32 | /* These routines should handle the standard chip-specific modes | ||
| 33 | * for usb0/1/2 ports, covering basic mux and transceiver setup. | ||
| 34 | * | ||
| 35 | * Some board-*.c files will need to set up additional mux options, | ||
| 36 | * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup. | ||
| 37 | */ | ||
| 38 | |||
| 39 | /* TESTED ON: | ||
| 40 | * - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables | ||
| 41 | * - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables | ||
| 42 | * - 5912 OSK UDC, with *nonstandard* A-to-A cable | ||
| 43 | * - 1510 Innovator UDC with bundled usb0 cable | ||
| 44 | * - 1510 Innovator OHCI with bundled usb1/usb2 cable | ||
| 45 | * - 1510 Innovator OHCI with custom usb0 cable, feeding 5V VBUS | ||
| 46 | * - 1710 custom development board using alternate pin group | ||
| 47 | * - 1710 H3 (with usb1 mini-AB) using standard Mini-B or OTG cables | ||
| 48 | */ | ||
| 49 | |||
| 50 | #define INT_USB_IRQ_GEN IH2_BASE + 20 | ||
| 51 | #define INT_USB_IRQ_NISO IH2_BASE + 30 | ||
| 52 | #define INT_USB_IRQ_ISO IH2_BASE + 29 | ||
| 53 | #define INT_USB_IRQ_HGEN INT_USB_HHC_1 | ||
| 54 | #define INT_USB_IRQ_OTG IH2_BASE + 8 | ||
| 55 | |||
| 56 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 57 | |||
| 58 | static struct resource udc_resources[] = { | ||
| 59 | /* order is significant! */ | ||
| 60 | { /* registers */ | ||
| 61 | .start = UDC_BASE, | ||
| 62 | .end = UDC_BASE + 0xff, | ||
| 63 | .flags = IORESOURCE_MEM, | ||
| 64 | }, { /* general IRQ */ | ||
| 65 | .start = INT_USB_IRQ_GEN, | ||
| 66 | .flags = IORESOURCE_IRQ, | ||
| 67 | }, { /* PIO IRQ */ | ||
| 68 | .start = INT_USB_IRQ_NISO, | ||
| 69 | .flags = IORESOURCE_IRQ, | ||
| 70 | }, { /* SOF IRQ */ | ||
| 71 | .start = INT_USB_IRQ_ISO, | ||
| 72 | .flags = IORESOURCE_IRQ, | ||
| 73 | }, | ||
| 74 | }; | ||
| 75 | |||
| 76 | static u64 udc_dmamask = ~(u32)0; | ||
| 77 | |||
| 78 | static struct platform_device udc_device = { | ||
| 79 | .name = "omap_udc", | ||
| 80 | .id = -1, | ||
| 81 | .dev = { | ||
| 82 | .dma_mask = &udc_dmamask, | ||
| 83 | .coherent_dma_mask = 0xffffffff, | ||
| 84 | }, | ||
| 85 | .num_resources = ARRAY_SIZE(udc_resources), | ||
| 86 | .resource = udc_resources, | ||
| 87 | }; | ||
| 88 | |||
| 89 | static inline void udc_device_init(struct omap_usb_config *pdata) | ||
| 90 | { | ||
| 91 | /* IRQ numbers for omap7xx */ | ||
| 92 | if(cpu_is_omap7xx()) { | ||
| 93 | udc_resources[1].start = INT_7XX_USB_GENI; | ||
| 94 | udc_resources[2].start = INT_7XX_USB_NON_ISO; | ||
| 95 | udc_resources[3].start = INT_7XX_USB_ISO; | ||
| 96 | } | ||
| 97 | pdata->udc_device = &udc_device; | ||
| 98 | } | ||
| 99 | |||
| 100 | #else | ||
| 101 | |||
| 102 | static inline void udc_device_init(struct omap_usb_config *pdata) | ||
| 103 | { | ||
| 104 | } | ||
| 105 | |||
| 106 | #endif | ||
| 107 | |||
| 108 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 109 | |||
| 110 | /* The dmamask must be set for OHCI to work */ | ||
| 111 | static u64 ohci_dmamask = ~(u32)0; | ||
| 112 | |||
| 113 | static struct resource ohci_resources[] = { | ||
| 114 | { | ||
| 115 | .start = OMAP_OHCI_BASE, | ||
| 116 | .end = OMAP_OHCI_BASE + 0xff, | ||
| 117 | .flags = IORESOURCE_MEM, | ||
| 118 | }, | ||
| 119 | { | ||
| 120 | .start = INT_USB_IRQ_HGEN, | ||
| 121 | .flags = IORESOURCE_IRQ, | ||
| 122 | }, | ||
| 123 | }; | ||
| 124 | |||
| 125 | static struct platform_device ohci_device = { | ||
| 126 | .name = "ohci", | ||
| 127 | .id = -1, | ||
| 128 | .dev = { | ||
| 129 | .dma_mask = &ohci_dmamask, | ||
| 130 | .coherent_dma_mask = 0xffffffff, | ||
| 131 | }, | ||
| 132 | .num_resources = ARRAY_SIZE(ohci_resources), | ||
| 133 | .resource = ohci_resources, | ||
| 134 | }; | ||
| 135 | |||
| 136 | static inline void ohci_device_init(struct omap_usb_config *pdata) | ||
| 137 | { | ||
| 138 | if (cpu_is_omap7xx()) | ||
| 139 | ohci_resources[1].start = INT_7XX_USB_HHC_1; | ||
| 140 | pdata->ohci_device = &ohci_device; | ||
| 141 | } | ||
| 142 | |||
| 143 | #else | ||
| 144 | |||
| 145 | static inline void ohci_device_init(struct omap_usb_config *pdata) | ||
| 146 | { | ||
| 147 | } | ||
| 148 | |||
| 149 | #endif | ||
| 150 | |||
| 151 | #if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG) | ||
| 152 | |||
| 153 | static struct resource otg_resources[] = { | ||
| 154 | /* order is significant! */ | ||
| 155 | { | ||
| 156 | .start = OTG_BASE, | ||
| 157 | .end = OTG_BASE + 0xff, | ||
| 158 | .flags = IORESOURCE_MEM, | ||
| 159 | }, { | ||
| 160 | .start = INT_USB_IRQ_OTG, | ||
| 161 | .flags = IORESOURCE_IRQ, | ||
| 162 | }, | ||
| 163 | }; | ||
| 164 | |||
| 165 | static struct platform_device otg_device = { | ||
| 166 | .name = "omap_otg", | ||
| 167 | .id = -1, | ||
| 168 | .num_resources = ARRAY_SIZE(otg_resources), | ||
| 169 | .resource = otg_resources, | ||
| 170 | }; | ||
| 171 | |||
| 172 | static inline void otg_device_init(struct omap_usb_config *pdata) | ||
| 173 | { | ||
| 174 | if (cpu_is_omap7xx()) | ||
| 175 | otg_resources[1].start = INT_7XX_USB_OTG; | ||
| 176 | pdata->otg_device = &otg_device; | ||
| 177 | } | ||
| 178 | |||
| 179 | #else | ||
| 180 | |||
| 181 | static inline void otg_device_init(struct omap_usb_config *pdata) | ||
| 182 | { | ||
| 183 | } | ||
| 184 | |||
| 185 | #endif | ||
| 186 | |||
| 187 | u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device) | ||
| 188 | { | ||
| 189 | u32 syscon1 = 0; | ||
| 190 | |||
| 191 | if (nwires == 0) { | ||
| 192 | if (!cpu_is_omap15xx()) { | ||
| 193 | u32 l; | ||
| 194 | |||
| 195 | /* pulldown D+/D- */ | ||
| 196 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 197 | l &= ~(3 << 1); | ||
| 198 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 199 | } | ||
| 200 | return 0; | ||
| 201 | } | ||
| 202 | |||
| 203 | if (is_device) { | ||
| 204 | if (cpu_is_omap7xx()) { | ||
| 205 | omap_cfg_reg(AA17_7XX_USB_DM); | ||
| 206 | omap_cfg_reg(W16_7XX_USB_PU_EN); | ||
| 207 | omap_cfg_reg(W17_7XX_USB_VBUSI); | ||
| 208 | omap_cfg_reg(W18_7XX_USB_DMCK_OUT); | ||
| 209 | omap_cfg_reg(W19_7XX_USB_DCRST); | ||
| 210 | } else | ||
| 211 | omap_cfg_reg(W4_USB_PUEN); | ||
| 212 | } | ||
| 213 | |||
| 214 | if (nwires == 2) { | ||
| 215 | u32 l; | ||
| 216 | |||
| 217 | // omap_cfg_reg(P9_USB_DP); | ||
| 218 | // omap_cfg_reg(R8_USB_DM); | ||
| 219 | |||
| 220 | if (cpu_is_omap15xx()) { | ||
| 221 | /* This works on 1510-Innovator */ | ||
| 222 | return 0; | ||
| 223 | } | ||
| 224 | |||
| 225 | /* NOTES: | ||
| 226 | * - peripheral should configure VBUS detection! | ||
| 227 | * - only peripherals may use the internal D+/D- pulldowns | ||
| 228 | * - OTG support on this port not yet written | ||
| 229 | */ | ||
| 230 | |||
| 231 | /* Don't do this for omap7xx -- it causes USB to not work correctly */ | ||
| 232 | if (!cpu_is_omap7xx()) { | ||
| 233 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 234 | l &= ~(7 << 4); | ||
| 235 | if (!is_device) | ||
| 236 | l |= (3 << 1); | ||
| 237 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 238 | } | ||
| 239 | |||
| 240 | return 3 << 16; | ||
| 241 | } | ||
| 242 | |||
| 243 | /* alternate pin config, external transceiver */ | ||
| 244 | if (cpu_is_omap15xx()) { | ||
| 245 | printk(KERN_ERR "no usb0 alt pin config on 15xx\n"); | ||
| 246 | return 0; | ||
| 247 | } | ||
| 248 | |||
| 249 | omap_cfg_reg(V6_USB0_TXD); | ||
| 250 | omap_cfg_reg(W9_USB0_TXEN); | ||
| 251 | omap_cfg_reg(W5_USB0_SE0); | ||
| 252 | if (nwires != 3) | ||
| 253 | omap_cfg_reg(Y5_USB0_RCV); | ||
| 254 | |||
| 255 | /* NOTE: SPEED and SUSP aren't configured here. OTG hosts | ||
| 256 | * may be able to use I2C requests to set those bits along | ||
| 257 | * with VBUS switching and overcurrent detection. | ||
| 258 | */ | ||
| 259 | |||
| 260 | if (nwires != 6) { | ||
| 261 | u32 l; | ||
| 262 | |||
| 263 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 264 | l &= ~CONF_USB2_UNI_R; | ||
| 265 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 266 | } | ||
| 267 | |||
| 268 | switch (nwires) { | ||
| 269 | case 3: | ||
| 270 | syscon1 = 2; | ||
| 271 | break; | ||
| 272 | case 4: | ||
| 273 | syscon1 = 1; | ||
| 274 | break; | ||
| 275 | case 6: | ||
| 276 | syscon1 = 3; | ||
| 277 | { | ||
| 278 | u32 l; | ||
| 279 | |||
| 280 | omap_cfg_reg(AA9_USB0_VP); | ||
| 281 | omap_cfg_reg(R9_USB0_VM); | ||
| 282 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 283 | l |= CONF_USB2_UNI_R; | ||
| 284 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 285 | } | ||
| 286 | break; | ||
| 287 | default: | ||
| 288 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | ||
| 289 | 0, nwires); | ||
| 290 | } | ||
| 291 | |||
| 292 | return syscon1 << 16; | ||
| 293 | } | ||
| 294 | |||
| 295 | u32 __init omap1_usb1_init(unsigned nwires) | ||
| 296 | { | ||
| 297 | u32 syscon1 = 0; | ||
| 298 | |||
| 299 | if (!cpu_is_omap15xx() && nwires != 6) { | ||
| 300 | u32 l; | ||
| 301 | |||
| 302 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 303 | l &= ~CONF_USB1_UNI_R; | ||
| 304 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 305 | } | ||
| 306 | if (nwires == 0) | ||
| 307 | return 0; | ||
| 308 | |||
| 309 | /* external transceiver */ | ||
| 310 | omap_cfg_reg(USB1_TXD); | ||
| 311 | omap_cfg_reg(USB1_TXEN); | ||
| 312 | if (nwires != 3) | ||
| 313 | omap_cfg_reg(USB1_RCV); | ||
| 314 | |||
| 315 | if (cpu_is_omap15xx()) { | ||
| 316 | omap_cfg_reg(USB1_SEO); | ||
| 317 | omap_cfg_reg(USB1_SPEED); | ||
| 318 | // SUSP | ||
| 319 | } else if (cpu_is_omap1610() || cpu_is_omap5912()) { | ||
| 320 | omap_cfg_reg(W13_1610_USB1_SE0); | ||
| 321 | omap_cfg_reg(R13_1610_USB1_SPEED); | ||
| 322 | // SUSP | ||
| 323 | } else if (cpu_is_omap1710()) { | ||
| 324 | omap_cfg_reg(R13_1710_USB1_SE0); | ||
| 325 | // SUSP | ||
| 326 | } else { | ||
| 327 | pr_debug("usb%d cpu unrecognized\n", 1); | ||
| 328 | return 0; | ||
| 329 | } | ||
| 330 | |||
| 331 | switch (nwires) { | ||
| 332 | case 2: | ||
| 333 | goto bad; | ||
| 334 | case 3: | ||
| 335 | syscon1 = 2; | ||
| 336 | break; | ||
| 337 | case 4: | ||
| 338 | syscon1 = 1; | ||
| 339 | break; | ||
| 340 | case 6: | ||
| 341 | syscon1 = 3; | ||
| 342 | omap_cfg_reg(USB1_VP); | ||
| 343 | omap_cfg_reg(USB1_VM); | ||
| 344 | if (!cpu_is_omap15xx()) { | ||
| 345 | u32 l; | ||
| 346 | |||
| 347 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 348 | l |= CONF_USB1_UNI_R; | ||
| 349 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 350 | } | ||
| 351 | break; | ||
| 352 | default: | ||
| 353 | bad: | ||
| 354 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | ||
| 355 | 1, nwires); | ||
| 356 | } | ||
| 357 | |||
| 358 | return syscon1 << 20; | ||
| 359 | } | ||
| 360 | |||
| 361 | u32 __init omap1_usb2_init(unsigned nwires, unsigned alt_pingroup) | ||
| 362 | { | ||
| 363 | u32 syscon1 = 0; | ||
| 364 | |||
| 365 | /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */ | ||
| 366 | if (alt_pingroup || nwires == 0) | ||
| 367 | return 0; | ||
| 368 | |||
| 369 | if (!cpu_is_omap15xx() && nwires != 6) { | ||
| 370 | u32 l; | ||
| 371 | |||
| 372 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 373 | l &= ~CONF_USB2_UNI_R; | ||
| 374 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 375 | } | ||
| 376 | |||
| 377 | /* external transceiver */ | ||
| 378 | if (cpu_is_omap15xx()) { | ||
| 379 | omap_cfg_reg(USB2_TXD); | ||
| 380 | omap_cfg_reg(USB2_TXEN); | ||
| 381 | omap_cfg_reg(USB2_SEO); | ||
| 382 | if (nwires != 3) | ||
| 383 | omap_cfg_reg(USB2_RCV); | ||
| 384 | /* there is no USB2_SPEED */ | ||
| 385 | } else if (cpu_is_omap16xx()) { | ||
| 386 | omap_cfg_reg(V6_USB2_TXD); | ||
| 387 | omap_cfg_reg(W9_USB2_TXEN); | ||
| 388 | omap_cfg_reg(W5_USB2_SE0); | ||
| 389 | if (nwires != 3) | ||
| 390 | omap_cfg_reg(Y5_USB2_RCV); | ||
| 391 | // FIXME omap_cfg_reg(USB2_SPEED); | ||
| 392 | } else { | ||
| 393 | pr_debug("usb%d cpu unrecognized\n", 1); | ||
| 394 | return 0; | ||
| 395 | } | ||
| 396 | |||
| 397 | // omap_cfg_reg(USB2_SUSP); | ||
| 398 | |||
| 399 | switch (nwires) { | ||
| 400 | case 2: | ||
| 401 | goto bad; | ||
| 402 | case 3: | ||
| 403 | syscon1 = 2; | ||
| 404 | break; | ||
| 405 | case 4: | ||
| 406 | syscon1 = 1; | ||
| 407 | break; | ||
| 408 | case 5: | ||
| 409 | goto bad; | ||
| 410 | case 6: | ||
| 411 | syscon1 = 3; | ||
| 412 | if (cpu_is_omap15xx()) { | ||
| 413 | omap_cfg_reg(USB2_VP); | ||
| 414 | omap_cfg_reg(USB2_VM); | ||
| 415 | } else { | ||
| 416 | u32 l; | ||
| 417 | |||
| 418 | omap_cfg_reg(AA9_USB2_VP); | ||
| 419 | omap_cfg_reg(R9_USB2_VM); | ||
| 420 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 421 | l |= CONF_USB2_UNI_R; | ||
| 422 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 423 | } | ||
| 424 | break; | ||
| 425 | default: | ||
| 426 | bad: | ||
| 427 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | ||
| 428 | 2, nwires); | ||
| 429 | } | ||
| 430 | |||
| 431 | return syscon1 << 24; | ||
| 432 | } | ||
| 433 | |||
| 434 | #ifdef CONFIG_ARCH_OMAP15XX | ||
| 435 | |||
| 436 | /* ULPD_DPLL_CTRL */ | ||
| 437 | #define DPLL_IOB (1 << 13) | ||
| 438 | #define DPLL_PLL_ENABLE (1 << 4) | ||
| 439 | #define DPLL_LOCK (1 << 0) | ||
| 440 | |||
| 441 | /* ULPD_APLL_CTRL */ | ||
| 442 | #define APLL_NDPLL_SWITCH (1 << 0) | ||
| 443 | |||
| 444 | static void __init omap_1510_usb_init(struct omap_usb_config *config) | ||
| 445 | { | ||
| 446 | unsigned int val; | ||
| 447 | u16 w; | ||
| 448 | |||
| 449 | config->usb0_init(config->pins[0], is_usb0_device(config)); | ||
| 450 | config->usb1_init(config->pins[1]); | ||
| 451 | config->usb2_init(config->pins[2], 0); | ||
| 452 | |||
| 453 | val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1); | ||
| 454 | val |= (config->hmc_mode << 1); | ||
| 455 | omap_writel(val, MOD_CONF_CTRL_0); | ||
| 456 | |||
| 457 | printk("USB: hmc %d", config->hmc_mode); | ||
| 458 | if (config->pins[0]) | ||
| 459 | printk(", usb0 %d wires%s", config->pins[0], | ||
| 460 | is_usb0_device(config) ? " (dev)" : ""); | ||
| 461 | if (config->pins[1]) | ||
| 462 | printk(", usb1 %d wires", config->pins[1]); | ||
| 463 | if (config->pins[2]) | ||
| 464 | printk(", usb2 %d wires", config->pins[2]); | ||
| 465 | printk("\n"); | ||
| 466 | |||
| 467 | /* use DPLL for 48 MHz function clock */ | ||
| 468 | pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL), | ||
| 469 | omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ)); | ||
| 470 | |||
| 471 | w = omap_readw(ULPD_APLL_CTRL); | ||
| 472 | w &= ~APLL_NDPLL_SWITCH; | ||
| 473 | omap_writew(w, ULPD_APLL_CTRL); | ||
| 474 | |||
| 475 | w = omap_readw(ULPD_DPLL_CTRL); | ||
| 476 | w |= DPLL_IOB | DPLL_PLL_ENABLE; | ||
| 477 | omap_writew(w, ULPD_DPLL_CTRL); | ||
| 478 | |||
| 479 | w = omap_readw(ULPD_SOFT_REQ); | ||
| 480 | w |= SOFT_UDC_REQ | SOFT_DPLL_REQ; | ||
| 481 | omap_writew(w, ULPD_SOFT_REQ); | ||
| 482 | |||
| 483 | while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK)) | ||
| 484 | cpu_relax(); | ||
| 485 | |||
| 486 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 487 | if (config->register_dev) { | ||
| 488 | int status; | ||
| 489 | |||
| 490 | udc_device.dev.platform_data = config; | ||
| 491 | status = platform_device_register(&udc_device); | ||
| 492 | if (status) | ||
| 493 | pr_debug("can't register UDC device, %d\n", status); | ||
| 494 | /* udc driver gates 48MHz by D+ pullup */ | ||
| 495 | } | ||
| 496 | #endif | ||
| 497 | |||
| 498 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 499 | if (config->register_host) { | ||
| 500 | int status; | ||
| 501 | |||
| 502 | ohci_device.dev.platform_data = config; | ||
| 503 | status = platform_device_register(&ohci_device); | ||
| 504 | if (status) | ||
| 505 | pr_debug("can't register OHCI device, %d\n", status); | ||
| 506 | /* hcd explicitly gates 48MHz */ | ||
| 507 | } | ||
| 508 | #endif | ||
| 509 | } | ||
| 510 | |||
| 511 | #else | ||
| 512 | static inline void omap_1510_usb_init(struct omap_usb_config *config) {} | ||
| 513 | #endif | ||
| 514 | |||
| 515 | void __init omap1_usb_init(struct omap_usb_config *pdata) | ||
| 516 | { | ||
| 517 | pdata->usb0_init = omap1_usb0_init; | ||
| 518 | pdata->usb1_init = omap1_usb1_init; | ||
| 519 | pdata->usb2_init = omap1_usb2_init; | ||
| 520 | udc_device_init(pdata); | ||
| 521 | ohci_device_init(pdata); | ||
| 522 | otg_device_init(pdata); | ||
| 523 | |||
| 524 | if (cpu_is_omap7xx() || cpu_is_omap16xx()) | ||
| 525 | omap_otg_init(pdata); | ||
| 526 | else if (cpu_is_omap15xx()) | ||
| 527 | omap_1510_usb_init(pdata); | ||
| 528 | else | ||
| 529 | printk(KERN_ERR "USB: No init for your chip yet\n"); | ||
| 530 | } | ||
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index b31b6f123122..b48bacf0a7aa 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
| @@ -1,22 +1,77 @@ | |||
| 1 | if ARCH_OMAP2PLUS | ||
| 2 | |||
| 3 | menu "TI OMAP2/3/4 Specific Features" | ||
| 4 | |||
| 5 | config ARCH_OMAP2PLUS_TYPICAL | ||
| 6 | bool "Typical OMAP configuration" | ||
| 7 | default y | ||
| 8 | select AEABI | ||
| 9 | select REGULATOR | ||
| 10 | select PM | ||
| 11 | select PM_RUNTIME | ||
| 12 | select VFP | ||
| 13 | select NEON if ARCH_OMAP3 || ARCH_OMAP4 | ||
| 14 | select SERIAL_8250 | ||
| 15 | select SERIAL_CORE_CONSOLE | ||
| 16 | select SERIAL_8250_CONSOLE | ||
| 17 | select I2C | ||
| 18 | select I2C_OMAP | ||
| 19 | select MFD | ||
| 20 | select MENELAUS if ARCH_OMAP2 | ||
| 21 | select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 | ||
| 22 | select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 | ||
| 23 | help | ||
| 24 | Compile a kernel suitable for booting most boards | ||
| 25 | |||
| 26 | config ARCH_OMAP2 | ||
| 27 | bool "TI OMAP2" | ||
| 28 | depends on ARCH_OMAP2PLUS | ||
| 29 | default y | ||
| 30 | select CPU_V6 | ||
| 31 | |||
| 32 | config ARCH_OMAP3 | ||
| 33 | bool "TI OMAP3" | ||
| 34 | depends on ARCH_OMAP2PLUS | ||
| 35 | default y | ||
| 36 | select CPU_V7 | ||
| 37 | select USB_ARCH_HAS_EHCI | ||
| 38 | select ARM_L1_CACHE_SHIFT_6 | ||
| 39 | |||
| 40 | config ARCH_OMAP4 | ||
| 41 | bool "TI OMAP4" | ||
| 42 | default y | ||
| 43 | depends on ARCH_OMAP2PLUS | ||
| 44 | select CPU_V7 | ||
| 45 | select ARM_GIC | ||
| 46 | |||
| 1 | comment "OMAP Core Type" | 47 | comment "OMAP Core Type" |
| 2 | depends on ARCH_OMAP2 | 48 | depends on ARCH_OMAP2 |
| 3 | 49 | ||
| 4 | config ARCH_OMAP2420 | 50 | config ARCH_OMAP2420 |
| 5 | bool "OMAP2420 support" | 51 | bool "OMAP2420 support" |
| 6 | depends on ARCH_OMAP2 | 52 | depends on ARCH_OMAP2 |
| 53 | default y | ||
| 7 | select OMAP_DM_TIMER | 54 | select OMAP_DM_TIMER |
| 8 | select ARCH_OMAP_OTG | 55 | select ARCH_OMAP_OTG |
| 9 | 56 | ||
| 10 | config ARCH_OMAP2430 | 57 | config ARCH_OMAP2430 |
| 11 | bool "OMAP2430 support" | 58 | bool "OMAP2430 support" |
| 12 | depends on ARCH_OMAP2 | 59 | depends on ARCH_OMAP2 |
| 60 | default y | ||
| 13 | select ARCH_OMAP_OTG | 61 | select ARCH_OMAP_OTG |
| 14 | 62 | ||
| 15 | config ARCH_OMAP3430 | 63 | config ARCH_OMAP3430 |
| 16 | bool "OMAP3430 support" | 64 | bool "OMAP3430 support" |
| 17 | depends on ARCH_OMAP3 | 65 | depends on ARCH_OMAP3 |
| 66 | default y | ||
| 18 | select ARCH_OMAP_OTG | 67 | select ARCH_OMAP_OTG |
| 19 | 68 | ||
| 69 | config OMAP_PACKAGE_ZAF | ||
| 70 | bool | ||
| 71 | |||
| 72 | config OMAP_PACKAGE_ZAC | ||
| 73 | bool | ||
| 74 | |||
| 20 | config OMAP_PACKAGE_CBC | 75 | config OMAP_PACKAGE_CBC |
| 21 | bool | 76 | bool |
| 22 | 77 | ||
| @@ -35,6 +90,7 @@ comment "OMAP Board Type" | |||
| 35 | config MACH_OMAP_GENERIC | 90 | config MACH_OMAP_GENERIC |
| 36 | bool "Generic OMAP board" | 91 | bool "Generic OMAP board" |
| 37 | depends on ARCH_OMAP2 | 92 | depends on ARCH_OMAP2 |
| 93 | default y | ||
| 38 | 94 | ||
| 39 | config MACH_OMAP2_TUSB6010 | 95 | config MACH_OMAP2_TUSB6010 |
| 40 | bool | 96 | bool |
| @@ -44,60 +100,75 @@ config MACH_OMAP2_TUSB6010 | |||
| 44 | config MACH_OMAP_H4 | 100 | config MACH_OMAP_H4 |
| 45 | bool "OMAP 2420 H4 board" | 101 | bool "OMAP 2420 H4 board" |
| 46 | depends on ARCH_OMAP2 | 102 | depends on ARCH_OMAP2 |
| 103 | default y | ||
| 104 | select OMAP_PACKAGE_ZAF | ||
| 47 | select OMAP_DEBUG_DEVICES | 105 | select OMAP_DEBUG_DEVICES |
| 48 | 106 | ||
| 49 | config MACH_OMAP_APOLLON | 107 | config MACH_OMAP_APOLLON |
| 50 | bool "OMAP 2420 Apollon board" | 108 | bool "OMAP 2420 Apollon board" |
| 51 | depends on ARCH_OMAP2 | 109 | depends on ARCH_OMAP2 |
| 110 | default y | ||
| 111 | select OMAP_PACKAGE_ZAC | ||
| 52 | 112 | ||
| 53 | config MACH_OMAP_2430SDP | 113 | config MACH_OMAP_2430SDP |
| 54 | bool "OMAP 2430 SDP board" | 114 | bool "OMAP 2430 SDP board" |
| 55 | depends on ARCH_OMAP2 | 115 | depends on ARCH_OMAP2 |
| 116 | default y | ||
| 117 | select OMAP_PACKAGE_ZAC | ||
| 56 | 118 | ||
| 57 | config MACH_OMAP3_BEAGLE | 119 | config MACH_OMAP3_BEAGLE |
| 58 | bool "OMAP3 BEAGLE board" | 120 | bool "OMAP3 BEAGLE board" |
| 59 | depends on ARCH_OMAP3 | 121 | depends on ARCH_OMAP3 |
| 122 | default y | ||
| 60 | select OMAP_PACKAGE_CBB | 123 | select OMAP_PACKAGE_CBB |
| 61 | 124 | ||
| 62 | config MACH_DEVKIT8000 | 125 | config MACH_DEVKIT8000 |
| 63 | bool "DEVKIT8000 board" | 126 | bool "DEVKIT8000 board" |
| 64 | depends on ARCH_OMAP3 | 127 | depends on ARCH_OMAP3 |
| 128 | default y | ||
| 65 | select OMAP_PACKAGE_CUS | 129 | select OMAP_PACKAGE_CUS |
| 66 | select OMAP_MUX | 130 | select OMAP_MUX |
| 67 | 131 | ||
| 68 | config MACH_OMAP_LDP | 132 | config MACH_OMAP_LDP |
| 69 | bool "OMAP3 LDP board" | 133 | bool "OMAP3 LDP board" |
| 70 | depends on ARCH_OMAP3 | 134 | depends on ARCH_OMAP3 |
| 135 | default y | ||
| 71 | select OMAP_PACKAGE_CBB | 136 | select OMAP_PACKAGE_CBB |
| 72 | 137 | ||
| 73 | config MACH_OVERO | 138 | config MACH_OVERO |
| 74 | bool "Gumstix Overo board" | 139 | bool "Gumstix Overo board" |
| 75 | depends on ARCH_OMAP3 | 140 | depends on ARCH_OMAP3 |
| 141 | default y | ||
| 76 | select OMAP_PACKAGE_CBB | 142 | select OMAP_PACKAGE_CBB |
| 77 | 143 | ||
| 78 | config MACH_OMAP3EVM | 144 | config MACH_OMAP3EVM |
| 79 | bool "OMAP 3530 EVM board" | 145 | bool "OMAP 3530 EVM board" |
| 80 | depends on ARCH_OMAP3 | 146 | depends on ARCH_OMAP3 |
| 147 | default y | ||
| 81 | select OMAP_PACKAGE_CBB | 148 | select OMAP_PACKAGE_CBB |
| 82 | 149 | ||
| 83 | config MACH_OMAP3517EVM | 150 | config MACH_OMAP3517EVM |
| 84 | bool "OMAP3517/ AM3517 EVM board" | 151 | bool "OMAP3517/ AM3517 EVM board" |
| 85 | depends on ARCH_OMAP3 | 152 | depends on ARCH_OMAP3 |
| 153 | default y | ||
| 86 | select OMAP_PACKAGE_CBB | 154 | select OMAP_PACKAGE_CBB |
| 87 | 155 | ||
| 88 | config MACH_OMAP3_PANDORA | 156 | config MACH_OMAP3_PANDORA |
| 89 | bool "OMAP3 Pandora" | 157 | bool "OMAP3 Pandora" |
| 90 | depends on ARCH_OMAP3 | 158 | depends on ARCH_OMAP3 |
| 159 | default y | ||
| 91 | select OMAP_PACKAGE_CBB | 160 | select OMAP_PACKAGE_CBB |
| 92 | 161 | ||
| 93 | config MACH_OMAP3_TOUCHBOOK | 162 | config MACH_OMAP3_TOUCHBOOK |
| 94 | bool "OMAP3 Touch Book" | 163 | bool "OMAP3 Touch Book" |
| 95 | depends on ARCH_OMAP3 | 164 | depends on ARCH_OMAP3 |
| 165 | default y | ||
| 96 | select BACKLIGHT_CLASS_DEVICE | 166 | select BACKLIGHT_CLASS_DEVICE |
| 97 | 167 | ||
| 98 | config MACH_OMAP_3430SDP | 168 | config MACH_OMAP_3430SDP |
| 99 | bool "OMAP 3430 SDP board" | 169 | bool "OMAP 3430 SDP board" |
| 100 | depends on ARCH_OMAP3 | 170 | depends on ARCH_OMAP3 |
| 171 | default y | ||
| 101 | select OMAP_PACKAGE_CBB | 172 | select OMAP_PACKAGE_CBB |
| 102 | 173 | ||
| 103 | config MACH_NOKIA_N800 | 174 | config MACH_NOKIA_N800 |
| @@ -112,6 +183,8 @@ config MACH_NOKIA_N810_WIMAX | |||
| 112 | config MACH_NOKIA_N8X0 | 183 | config MACH_NOKIA_N8X0 |
| 113 | bool "Nokia N800/N810" | 184 | bool "Nokia N800/N810" |
| 114 | depends on ARCH_OMAP2420 | 185 | depends on ARCH_OMAP2420 |
| 186 | default y | ||
| 187 | select OMAP_PACKAGE_ZAC | ||
| 115 | select MACH_NOKIA_N800 | 188 | select MACH_NOKIA_N800 |
| 116 | select MACH_NOKIA_N810 | 189 | select MACH_NOKIA_N810 |
| 117 | select MACH_NOKIA_N810_WIMAX | 190 | select MACH_NOKIA_N810_WIMAX |
| @@ -119,42 +192,55 @@ config MACH_NOKIA_N8X0 | |||
| 119 | config MACH_NOKIA_RX51 | 192 | config MACH_NOKIA_RX51 |
| 120 | bool "Nokia RX-51 board" | 193 | bool "Nokia RX-51 board" |
| 121 | depends on ARCH_OMAP3 | 194 | depends on ARCH_OMAP3 |
| 195 | default y | ||
| 122 | select OMAP_PACKAGE_CBB | 196 | select OMAP_PACKAGE_CBB |
| 123 | 197 | ||
| 124 | config MACH_OMAP_ZOOM2 | 198 | config MACH_OMAP_ZOOM2 |
| 125 | bool "OMAP3 Zoom2 board" | 199 | bool "OMAP3 Zoom2 board" |
| 126 | depends on ARCH_OMAP3 | 200 | depends on ARCH_OMAP3 |
| 201 | default y | ||
| 127 | select OMAP_PACKAGE_CBB | 202 | select OMAP_PACKAGE_CBB |
| 128 | 203 | ||
| 129 | config MACH_OMAP_ZOOM3 | 204 | config MACH_OMAP_ZOOM3 |
| 130 | bool "OMAP3630 Zoom3 board" | 205 | bool "OMAP3630 Zoom3 board" |
| 131 | depends on ARCH_OMAP3 | 206 | depends on ARCH_OMAP3 |
| 207 | default y | ||
| 132 | select OMAP_PACKAGE_CBP | 208 | select OMAP_PACKAGE_CBP |
| 133 | 209 | ||
| 134 | config MACH_CM_T35 | 210 | config MACH_CM_T35 |
| 135 | bool "CompuLab CM-T35 module" | 211 | bool "CompuLab CM-T35 module" |
| 136 | depends on ARCH_OMAP3 | 212 | depends on ARCH_OMAP3 |
| 213 | default y | ||
| 137 | select OMAP_PACKAGE_CUS | 214 | select OMAP_PACKAGE_CUS |
| 138 | select OMAP_MUX | 215 | select OMAP_MUX |
| 139 | 216 | ||
| 140 | config MACH_IGEP0020 | 217 | config MACH_IGEP0020 |
| 141 | bool "IGEP v2 board" | 218 | bool "IGEP v2 board" |
| 142 | depends on ARCH_OMAP3 | 219 | depends on ARCH_OMAP3 |
| 220 | default y | ||
| 143 | select OMAP_PACKAGE_CBB | 221 | select OMAP_PACKAGE_CBB |
| 144 | 222 | ||
| 145 | config MACH_SBC3530 | 223 | config MACH_SBC3530 |
| 146 | bool "OMAP3 SBC STALKER board" | 224 | bool "OMAP3 SBC STALKER board" |
| 147 | depends on ARCH_OMAP3 | 225 | depends on ARCH_OMAP3 |
| 226 | default y | ||
| 148 | select OMAP_PACKAGE_CUS | 227 | select OMAP_PACKAGE_CUS |
| 149 | select OMAP_MUX | 228 | select OMAP_MUX |
| 150 | 229 | ||
| 151 | config MACH_OMAP_3630SDP | 230 | config MACH_OMAP_3630SDP |
| 152 | bool "OMAP3630 SDP board" | 231 | bool "OMAP3630 SDP board" |
| 153 | depends on ARCH_OMAP3 | 232 | depends on ARCH_OMAP3 |
| 233 | default y | ||
| 154 | select OMAP_PACKAGE_CBP | 234 | select OMAP_PACKAGE_CBP |
| 155 | 235 | ||
| 156 | config MACH_OMAP_4430SDP | 236 | config MACH_OMAP_4430SDP |
| 157 | bool "OMAP 4430 SDP board" | 237 | bool "OMAP 4430 SDP board" |
| 238 | default y | ||
| 239 | depends on ARCH_OMAP4 | ||
| 240 | |||
| 241 | config MACH_OMAP4_PANDA | ||
| 242 | bool "OMAP4 Panda Board" | ||
| 243 | default y | ||
| 158 | depends on ARCH_OMAP4 | 244 | depends on ARCH_OMAP4 |
| 159 | 245 | ||
| 160 | config OMAP3_EMU | 246 | config OMAP3_EMU |
| @@ -176,3 +262,6 @@ config OMAP3_SDRC_AC_TIMING | |||
| 176 | wish to say no. Selecting yes without understanding what is | 262 | wish to say no. Selecting yes without understanding what is |
| 177 | going on could result in system crashes; | 263 | going on could result in system crashes; |
| 178 | 264 | ||
| 265 | endmenu | ||
| 266 | |||
| 267 | endif | ||
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ea52b034e963..63b2d8859c3c 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o | 6 | obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o |
| 7 | 7 | ||
| 8 | omap-2-3-common = irq.o sdrc.o | 8 | omap-2-3-common = irq.o sdrc.o |
| 9 | hwmod-common = omap_hwmod.o \ | 9 | hwmod-common = omap_hwmod.o \ |
| @@ -15,13 +15,14 @@ clock-common = clock.o clock_common_data.o \ | |||
| 15 | 15 | ||
| 16 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) | 16 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) |
| 17 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) | 17 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) |
| 18 | obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) | 18 | obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) $(hwmod-common) |
| 19 | 19 | ||
| 20 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o | 20 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o |
| 21 | 21 | ||
| 22 | # SMP support ONLY available for OMAP4 | 22 | # SMP support ONLY available for OMAP4 |
| 23 | obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o | 23 | obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o |
| 24 | obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o | 24 | obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o |
| 25 | obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o | ||
| 25 | obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o | 26 | obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o |
| 26 | 27 | ||
| 27 | AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a | 28 | AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a |
| @@ -36,6 +37,8 @@ AFLAGS_sram243x.o :=-Wa,-march=armv6 | |||
| 36 | AFLAGS_sram34xx.o :=-Wa,-march=armv7-a | 37 | AFLAGS_sram34xx.o :=-Wa,-march=armv7-a |
| 37 | 38 | ||
| 38 | # Pin multiplexing | 39 | # Pin multiplexing |
| 40 | obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o | ||
| 41 | obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o | ||
| 39 | obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o | 42 | obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o |
| 40 | 43 | ||
| 41 | # SMS/SDRC | 44 | # SMS/SDRC |
| @@ -47,6 +50,7 @@ ifeq ($(CONFIG_PM),y) | |||
| 47 | obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o | 50 | obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o |
| 48 | obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o | 51 | obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o |
| 49 | obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o | 52 | obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o |
| 53 | obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o | ||
| 50 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o | 54 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o |
| 51 | 55 | ||
| 52 | AFLAGS_sleep24xx.o :=-Wa,-march=armv6 | 56 | AFLAGS_sleep24xx.o :=-Wa,-march=armv6 |
| @@ -89,7 +93,10 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o | |||
| 89 | obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o | 93 | obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o |
| 90 | mailbox_mach-objs := mailbox.o | 94 | mailbox_mach-objs := mailbox.o |
| 91 | 95 | ||
| 92 | obj-$(CONFIG_OMAP_IOMMU) := iommu2.o omap-iommu.o | 96 | obj-$(CONFIG_OMAP_IOMMU) += iommu2.o |
| 97 | |||
| 98 | iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o | ||
| 99 | obj-y += $(iommu-m) $(iommu-y) | ||
| 93 | 100 | ||
| 94 | i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o | 101 | i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o |
| 95 | obj-y += $(i2c-omap-m) $(i2c-omap-y) | 102 | obj-y += $(i2c-omap-m) $(i2c-omap-y) |
| @@ -105,6 +112,7 @@ obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \ | |||
| 105 | obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o \ | 112 | obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o \ |
| 106 | hsmmc.o | 113 | hsmmc.o |
| 107 | obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ | 114 | obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ |
| 115 | board-flash.o \ | ||
| 108 | hsmmc.o | 116 | hsmmc.o |
| 109 | obj-$(CONFIG_MACH_OVERO) += board-overo.o \ | 117 | obj-$(CONFIG_MACH_OVERO) += board-overo.o \ |
| 110 | hsmmc.o | 118 | hsmmc.o |
| @@ -114,7 +122,7 @@ obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \ | |||
| 114 | hsmmc.o | 122 | hsmmc.o |
| 115 | obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \ | 123 | obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \ |
| 116 | hsmmc.o \ | 124 | hsmmc.o \ |
| 117 | board-sdp-flash.o | 125 | board-flash.o |
| 118 | obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o | 126 | obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o |
| 119 | obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ | 127 | obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ |
| 120 | board-rx51-sdram.o \ | 128 | board-rx51-sdram.o \ |
| @@ -123,14 +131,17 @@ obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ | |||
| 123 | hsmmc.o | 131 | hsmmc.o |
| 124 | obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ | 132 | obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ |
| 125 | board-zoom-peripherals.o \ | 133 | board-zoom-peripherals.o \ |
| 134 | board-flash.o \ | ||
| 126 | hsmmc.o \ | 135 | hsmmc.o \ |
| 127 | board-zoom-debugboard.o | 136 | board-zoom-debugboard.o |
| 128 | obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom3.o \ | 137 | obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom3.o \ |
| 129 | board-zoom-peripherals.o \ | 138 | board-zoom-peripherals.o \ |
| 139 | board-flash.o \ | ||
| 130 | hsmmc.o \ | 140 | hsmmc.o \ |
| 131 | board-zoom-debugboard.o | 141 | board-zoom-debugboard.o |
| 132 | obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \ | 142 | obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \ |
| 133 | board-zoom-peripherals.o \ | 143 | board-zoom-peripherals.o \ |
| 144 | board-flash.o \ | ||
| 134 | hsmmc.o | 145 | hsmmc.o |
| 135 | obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ | 146 | obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ |
| 136 | hsmmc.o | 147 | hsmmc.o |
| @@ -140,12 +151,16 @@ obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ | |||
| 140 | hsmmc.o | 151 | hsmmc.o |
| 141 | obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ | 152 | obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ |
| 142 | hsmmc.o | 153 | hsmmc.o |
| 154 | obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \ | ||
| 155 | hsmmc.o | ||
| 143 | 156 | ||
| 144 | obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o | 157 | obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o |
| 145 | 158 | ||
| 146 | obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \ | 159 | obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \ |
| 147 | hsmmc.o | 160 | hsmmc.o |
| 148 | # Platform specific device init code | 161 | # Platform specific device init code |
| 162 | usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o | ||
| 163 | obj-y += $(usbfs-m) $(usbfs-y) | ||
| 149 | obj-y += usb-musb.o | 164 | obj-y += usb-musb.o |
| 150 | obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o | 165 | obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o |
| 151 | obj-y += usb-ehci.o | 166 | obj-y += usb-ehci.o |
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 42f49f785c93..8538e4131d27 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c | |||
| @@ -31,13 +31,13 @@ | |||
| 31 | #include <asm/mach/map.h> | 31 | #include <asm/mach/map.h> |
| 32 | 32 | ||
| 33 | #include <mach/gpio.h> | 33 | #include <mach/gpio.h> |
| 34 | #include <plat/mux.h> | ||
| 35 | #include <plat/board.h> | 34 | #include <plat/board.h> |
| 36 | #include <plat/common.h> | 35 | #include <plat/common.h> |
| 37 | #include <plat/gpmc.h> | 36 | #include <plat/gpmc.h> |
| 38 | #include <plat/usb.h> | 37 | #include <plat/usb.h> |
| 39 | #include <plat/gpmc-smc91x.h> | 38 | #include <plat/gpmc-smc91x.h> |
| 40 | 39 | ||
| 40 | #include "mux.h" | ||
| 41 | #include "hsmmc.h" | 41 | #include "hsmmc.h" |
| 42 | 42 | ||
| 43 | #define SDP2430_CS0_BASE 0x04000000 | 43 | #define SDP2430_CS0_BASE 0x04000000 |
| @@ -122,11 +122,7 @@ static struct omap_smc91x_platform_data board_smc91x_data = { | |||
| 122 | 122 | ||
| 123 | static void __init board_smc91x_init(void) | 123 | static void __init board_smc91x_init(void) |
| 124 | { | 124 | { |
| 125 | if (omap_rev() > OMAP3430_REV_ES1_0) | 125 | omap_mux_init_gpio(149, OMAP_PIN_INPUT); |
| 126 | board_smc91x_data.gpio_irq = 6; | ||
| 127 | else | ||
| 128 | board_smc91x_data.gpio_irq = 29; | ||
| 129 | |||
| 130 | gpmc_smc91x_init(&board_smc91x_data); | 126 | gpmc_smc91x_init(&board_smc91x_data); |
| 131 | } | 127 | } |
| 132 | 128 | ||
| @@ -217,17 +213,30 @@ static struct omap_usb_config sdp2430_usb_config __initdata = { | |||
| 217 | .pins[0] = 3, | 213 | .pins[0] = 3, |
| 218 | }; | 214 | }; |
| 219 | 215 | ||
| 216 | #ifdef CONFIG_OMAP_MUX | ||
| 217 | static struct omap_board_mux board_mux[] __initdata = { | ||
| 218 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 219 | }; | ||
| 220 | #else | ||
| 221 | #define board_mux NULL | ||
| 222 | #endif | ||
| 223 | |||
| 220 | static void __init omap_2430sdp_init(void) | 224 | static void __init omap_2430sdp_init(void) |
| 221 | { | 225 | { |
| 222 | int ret; | 226 | int ret; |
| 223 | 227 | ||
| 228 | omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC); | ||
| 229 | |||
| 224 | omap2430_i2c_init(); | 230 | omap2430_i2c_init(); |
| 225 | 231 | ||
| 226 | platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); | 232 | platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); |
| 227 | omap_serial_init(); | 233 | omap_serial_init(); |
| 228 | omap2_hsmmc_init(mmc); | 234 | omap2_hsmmc_init(mmc); |
| 229 | omap_usb_init(&sdp2430_usb_config); | 235 | omap2_usbfs_init(&sdp2430_usb_config); |
| 236 | |||
| 237 | omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP); | ||
| 230 | usb_musb_init(&musb_board_data); | 238 | usb_musb_init(&musb_board_data); |
| 239 | |||
| 231 | board_smc91x_init(); | 240 | board_smc91x_init(); |
| 232 | 241 | ||
| 233 | /* Turn off secondary LCD backlight */ | 242 | /* Turn off secondary LCD backlight */ |
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index dd9c03171a19..67b95b5f1a2f 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c | |||
| @@ -41,7 +41,7 @@ | |||
| 41 | #include <plat/control.h> | 41 | #include <plat/control.h> |
| 42 | #include <plat/gpmc-smc91x.h> | 42 | #include <plat/gpmc-smc91x.h> |
| 43 | 43 | ||
| 44 | #include <mach/board-sdp.h> | 44 | #include <mach/board-flash.h> |
| 45 | 45 | ||
| 46 | #include "mux.h" | 46 | #include "mux.h" |
| 47 | #include "sdram-qimonda-hyb18m512160af-6.h" | 47 | #include "sdram-qimonda-hyb18m512160af-6.h" |
| @@ -667,6 +667,18 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 667 | #define board_mux NULL | 667 | #define board_mux NULL |
| 668 | #endif | 668 | #endif |
| 669 | 669 | ||
| 670 | /* | ||
| 671 | * SDP3430 V2 Board CS organization | ||
| 672 | * Different from SDP3430 V1. Now 4 switches used to specify CS | ||
| 673 | * | ||
| 674 | * See also the Switch S8 settings in the comments. | ||
| 675 | */ | ||
| 676 | static char chip_sel_3430[][GPMC_CS_NUM] = { | ||
| 677 | {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */ | ||
| 678 | {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */ | ||
| 679 | {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */ | ||
| 680 | }; | ||
| 681 | |||
| 670 | static struct mtd_partition sdp_nor_partitions[] = { | 682 | static struct mtd_partition sdp_nor_partitions[] = { |
| 671 | /* bootloader (U-Boot, etc) in first sector */ | 683 | /* bootloader (U-Boot, etc) in first sector */ |
| 672 | { | 684 | { |
| @@ -797,24 +809,18 @@ static void __init omap_3430sdp_init(void) | |||
| 797 | omap_serial_init(); | 809 | omap_serial_init(); |
| 798 | usb_musb_init(&musb_board_data); | 810 | usb_musb_init(&musb_board_data); |
| 799 | board_smc91x_init(); | 811 | board_smc91x_init(); |
| 800 | sdp_flash_init(sdp_flash_partitions); | 812 | board_flash_init(sdp_flash_partitions, chip_sel_3430); |
| 801 | sdp3430_display_init(); | 813 | sdp3430_display_init(); |
| 802 | enable_board_wakeup_source(); | 814 | enable_board_wakeup_source(); |
| 803 | usb_ehci_init(&ehci_pdata); | 815 | usb_ehci_init(&ehci_pdata); |
| 804 | } | 816 | } |
| 805 | 817 | ||
| 806 | static void __init omap_3430sdp_map_io(void) | ||
| 807 | { | ||
| 808 | omap2_set_globals_343x(); | ||
| 809 | omap34xx_map_common_io(); | ||
| 810 | } | ||
| 811 | |||
| 812 | MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") | 818 | MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") |
| 813 | /* Maintainer: Syed Khasim - Texas Instruments Inc */ | 819 | /* Maintainer: Syed Khasim - Texas Instruments Inc */ |
| 814 | .phys_io = 0x48000000, | 820 | .phys_io = 0x48000000, |
| 815 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, | 821 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
| 816 | .boot_params = 0x80000100, | 822 | .boot_params = 0x80000100, |
| 817 | .map_io = omap_3430sdp_map_io, | 823 | .map_io = omap3_map_io, |
| 818 | .reserve = omap_reserve, | 824 | .reserve = omap_reserve, |
| 819 | .init_irq = omap_3430sdp_init_irq, | 825 | .init_irq = omap_3430sdp_init_irq, |
| 820 | .init_machine = omap_3430sdp_init, | 826 | .init_machine = omap_3430sdp_init, |
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 57290fb3fcd7..b359c3f7bb39 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c | |||
| @@ -18,10 +18,10 @@ | |||
| 18 | #include <plat/common.h> | 18 | #include <plat/common.h> |
| 19 | #include <plat/board.h> | 19 | #include <plat/board.h> |
| 20 | #include <plat/gpmc-smc91x.h> | 20 | #include <plat/gpmc-smc91x.h> |
| 21 | #include <plat/mux.h> | ||
| 22 | #include <plat/usb.h> | 21 | #include <plat/usb.h> |
| 23 | 22 | ||
| 24 | #include <mach/board-zoom.h> | 23 | #include <mach/board-zoom.h> |
| 24 | #include <mach/board-flash.h> | ||
| 25 | 25 | ||
| 26 | #include "mux.h" | 26 | #include "mux.h" |
| 27 | #include "sdram-hynix-h8mbx00u0mer-0em.h" | 27 | #include "sdram-hynix-h8mbx00u0mer-0em.h" |
| @@ -66,12 +66,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | |||
| 66 | .reset_gpio_port[2] = -EINVAL | 66 | .reset_gpio_port[2] = -EINVAL |
| 67 | }; | 67 | }; |
| 68 | 68 | ||
| 69 | static void __init omap_sdp_map_io(void) | ||
| 70 | { | ||
| 71 | omap2_set_globals_36xx(); | ||
| 72 | omap34xx_map_common_io(); | ||
| 73 | } | ||
| 74 | |||
| 75 | static struct omap_board_config_kernel sdp_config[] __initdata = { | 69 | static struct omap_board_config_kernel sdp_config[] __initdata = { |
| 76 | }; | 70 | }; |
| 77 | 71 | ||
| @@ -93,12 +87,131 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 93 | #define board_mux NULL | 87 | #define board_mux NULL |
| 94 | #endif | 88 | #endif |
| 95 | 89 | ||
| 90 | /* | ||
| 91 | * SDP3630 CS organization | ||
| 92 | * See also the Switch S8 settings in the comments. | ||
| 93 | */ | ||
| 94 | static char chip_sel_sdp[][GPMC_CS_NUM] = { | ||
| 95 | {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */ | ||
| 96 | {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */ | ||
| 97 | {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */ | ||
| 98 | }; | ||
| 99 | |||
| 100 | static struct mtd_partition sdp_nor_partitions[] = { | ||
| 101 | /* bootloader (U-Boot, etc) in first sector */ | ||
| 102 | { | ||
| 103 | .name = "Bootloader-NOR", | ||
| 104 | .offset = 0, | ||
| 105 | .size = SZ_256K, | ||
| 106 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 107 | }, | ||
| 108 | /* bootloader params in the next sector */ | ||
| 109 | { | ||
| 110 | .name = "Params-NOR", | ||
| 111 | .offset = MTDPART_OFS_APPEND, | ||
| 112 | .size = SZ_256K, | ||
| 113 | .mask_flags = 0, | ||
| 114 | }, | ||
| 115 | /* kernel */ | ||
| 116 | { | ||
| 117 | .name = "Kernel-NOR", | ||
| 118 | .offset = MTDPART_OFS_APPEND, | ||
| 119 | .size = SZ_2M, | ||
| 120 | .mask_flags = 0 | ||
| 121 | }, | ||
| 122 | /* file system */ | ||
| 123 | { | ||
| 124 | .name = "Filesystem-NOR", | ||
| 125 | .offset = MTDPART_OFS_APPEND, | ||
| 126 | .size = MTDPART_SIZ_FULL, | ||
| 127 | .mask_flags = 0 | ||
| 128 | } | ||
| 129 | }; | ||
| 130 | |||
| 131 | static struct mtd_partition sdp_onenand_partitions[] = { | ||
| 132 | { | ||
| 133 | .name = "X-Loader-OneNAND", | ||
| 134 | .offset = 0, | ||
| 135 | .size = 4 * (64 * 2048), | ||
| 136 | .mask_flags = MTD_WRITEABLE /* force read-only */ | ||
| 137 | }, | ||
| 138 | { | ||
| 139 | .name = "U-Boot-OneNAND", | ||
| 140 | .offset = MTDPART_OFS_APPEND, | ||
| 141 | .size = 2 * (64 * 2048), | ||
| 142 | .mask_flags = MTD_WRITEABLE /* force read-only */ | ||
| 143 | }, | ||
| 144 | { | ||
| 145 | .name = "U-Boot Environment-OneNAND", | ||
| 146 | .offset = MTDPART_OFS_APPEND, | ||
| 147 | .size = 1 * (64 * 2048), | ||
| 148 | }, | ||
| 149 | { | ||
| 150 | .name = "Kernel-OneNAND", | ||
| 151 | .offset = MTDPART_OFS_APPEND, | ||
| 152 | .size = 16 * (64 * 2048), | ||
| 153 | }, | ||
| 154 | { | ||
| 155 | .name = "File System-OneNAND", | ||
| 156 | .offset = MTDPART_OFS_APPEND, | ||
| 157 | .size = MTDPART_SIZ_FULL, | ||
| 158 | }, | ||
| 159 | }; | ||
| 160 | |||
| 161 | static struct mtd_partition sdp_nand_partitions[] = { | ||
| 162 | /* All the partition sizes are listed in terms of NAND block size */ | ||
| 163 | { | ||
| 164 | .name = "X-Loader-NAND", | ||
| 165 | .offset = 0, | ||
| 166 | .size = 4 * (64 * 2048), | ||
| 167 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 168 | }, | ||
| 169 | { | ||
| 170 | .name = "U-Boot-NAND", | ||
| 171 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | ||
| 172 | .size = 10 * (64 * 2048), | ||
| 173 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 174 | }, | ||
| 175 | { | ||
| 176 | .name = "Boot Env-NAND", | ||
| 177 | |||
| 178 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ | ||
| 179 | .size = 6 * (64 * 2048), | ||
| 180 | }, | ||
| 181 | { | ||
| 182 | .name = "Kernel-NAND", | ||
| 183 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ | ||
| 184 | .size = 40 * (64 * 2048), | ||
| 185 | }, | ||
| 186 | { | ||
| 187 | .name = "File System - NAND", | ||
| 188 | .size = MTDPART_SIZ_FULL, | ||
| 189 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ | ||
| 190 | }, | ||
| 191 | }; | ||
| 192 | |||
| 193 | static struct flash_partitions sdp_flash_partitions[] = { | ||
| 194 | { | ||
| 195 | .parts = sdp_nor_partitions, | ||
| 196 | .nr_parts = ARRAY_SIZE(sdp_nor_partitions), | ||
| 197 | }, | ||
| 198 | { | ||
| 199 | .parts = sdp_onenand_partitions, | ||
| 200 | .nr_parts = ARRAY_SIZE(sdp_onenand_partitions), | ||
| 201 | }, | ||
| 202 | { | ||
| 203 | .parts = sdp_nand_partitions, | ||
| 204 | .nr_parts = ARRAY_SIZE(sdp_nand_partitions), | ||
| 205 | }, | ||
| 206 | }; | ||
| 207 | |||
| 96 | static void __init omap_sdp_init(void) | 208 | static void __init omap_sdp_init(void) |
| 97 | { | 209 | { |
| 98 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); | 210 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); |
| 99 | omap_serial_init(); | 211 | omap_serial_init(); |
| 100 | zoom_peripherals_init(); | 212 | zoom_peripherals_init(); |
| 101 | board_smc91x_init(); | 213 | board_smc91x_init(); |
| 214 | board_flash_init(sdp_flash_partitions, chip_sel_sdp); | ||
| 102 | enable_board_wakeup_source(); | 215 | enable_board_wakeup_source(); |
| 103 | usb_ehci_init(&ehci_pdata); | 216 | usb_ehci_init(&ehci_pdata); |
| 104 | } | 217 | } |
| @@ -107,7 +220,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") | |||
| 107 | .phys_io = 0x48000000, | 220 | .phys_io = 0x48000000, |
| 108 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, | 221 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
| 109 | .boot_params = 0x80000100, | 222 | .boot_params = 0x80000100, |
| 110 | .map_io = omap_sdp_map_io, | 223 | .map_io = omap3_map_io, |
| 111 | .reserve = omap_reserve, | 224 | .reserve = omap_reserve, |
| 112 | .init_irq = omap_sdp_init_irq, | 225 | .init_irq = omap_sdp_init_irq, |
| 113 | .init_machine = omap_sdp_init, | 226 | .init_machine = omap_sdp_init, |
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 4bb2c5d151ec..9447644774c2 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c | |||
| @@ -21,6 +21,7 @@ | |||
| 21 | #include <linux/spi/spi.h> | 21 | #include <linux/spi/spi.h> |
| 22 | #include <linux/i2c/twl.h> | 22 | #include <linux/i2c/twl.h> |
| 23 | #include <linux/regulator/machine.h> | 23 | #include <linux/regulator/machine.h> |
| 24 | #include <linux/leds.h> | ||
| 24 | 25 | ||
| 25 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 26 | #include <mach/omap4-common.h> | 27 | #include <mach/omap4-common.h> |
| @@ -40,6 +41,54 @@ | |||
| 40 | #define ETH_KS8851_POWER_ON 48 | 41 | #define ETH_KS8851_POWER_ON 48 |
| 41 | #define ETH_KS8851_QUART 138 | 42 | #define ETH_KS8851_QUART 138 |
| 42 | 43 | ||
| 44 | static struct gpio_led sdp4430_gpio_leds[] = { | ||
| 45 | { | ||
| 46 | .name = "omap4:green:debug0", | ||
| 47 | .gpio = 61, | ||
| 48 | }, | ||
| 49 | { | ||
| 50 | .name = "omap4:green:debug1", | ||
| 51 | .gpio = 30, | ||
| 52 | }, | ||
| 53 | { | ||
| 54 | .name = "omap4:green:debug2", | ||
| 55 | .gpio = 7, | ||
| 56 | }, | ||
| 57 | { | ||
| 58 | .name = "omap4:green:debug3", | ||
| 59 | .gpio = 8, | ||
| 60 | }, | ||
| 61 | { | ||
| 62 | .name = "omap4:green:debug4", | ||
| 63 | .gpio = 50, | ||
| 64 | }, | ||
| 65 | { | ||
| 66 | .name = "omap4:blue:user", | ||
| 67 | .gpio = 169, | ||
| 68 | }, | ||
| 69 | { | ||
| 70 | .name = "omap4:red:user", | ||
| 71 | .gpio = 170, | ||
| 72 | }, | ||
| 73 | { | ||
| 74 | .name = "omap4:green:user", | ||
| 75 | .gpio = 139, | ||
| 76 | }, | ||
| 77 | |||
| 78 | }; | ||
| 79 | |||
| 80 | static struct gpio_led_platform_data sdp4430_led_data = { | ||
| 81 | .leds = sdp4430_gpio_leds, | ||
| 82 | .num_leds = ARRAY_SIZE(sdp4430_gpio_leds), | ||
| 83 | }; | ||
| 84 | |||
| 85 | static struct platform_device sdp4430_leds_gpio = { | ||
| 86 | .name = "leds-gpio", | ||
| 87 | .id = -1, | ||
| 88 | .dev = { | ||
| 89 | .platform_data = &sdp4430_led_data, | ||
| 90 | }, | ||
| 91 | }; | ||
| 43 | static struct spi_board_info sdp4430_spi_board_info[] __initdata = { | 92 | static struct spi_board_info sdp4430_spi_board_info[] __initdata = { |
| 44 | { | 93 | { |
| 45 | .modalias = "ks8851", | 94 | .modalias = "ks8851", |
| @@ -112,6 +161,7 @@ static struct platform_device sdp4430_lcd_device = { | |||
| 112 | 161 | ||
| 113 | static struct platform_device *sdp4430_devices[] __initdata = { | 162 | static struct platform_device *sdp4430_devices[] __initdata = { |
| 114 | &sdp4430_lcd_device, | 163 | &sdp4430_lcd_device, |
| 164 | &sdp4430_leds_gpio, | ||
| 115 | }; | 165 | }; |
| 116 | 166 | ||
| 117 | static struct omap_lcd_config sdp4430_lcd_config __initdata = { | 167 | static struct omap_lcd_config sdp4430_lcd_config __initdata = { |
| @@ -156,14 +206,16 @@ static struct omap2_hsmmc_info mmc[] = { | |||
| 156 | {} /* Terminator */ | 206 | {} /* Terminator */ |
| 157 | }; | 207 | }; |
| 158 | 208 | ||
| 159 | static struct regulator_consumer_supply sdp4430_vmmc_supply[] = { | 209 | static struct regulator_consumer_supply sdp4430_vaux_supply[] = { |
| 160 | { | 210 | { |
| 161 | .supply = "vmmc", | 211 | .supply = "vmmc", |
| 162 | .dev_name = "mmci-omap-hs.0", | 212 | .dev_name = "mmci-omap-hs.1", |
| 163 | }, | 213 | }, |
| 214 | }; | ||
| 215 | static struct regulator_consumer_supply sdp4430_vmmc_supply[] = { | ||
| 164 | { | 216 | { |
| 165 | .supply = "vmmc", | 217 | .supply = "vmmc", |
| 166 | .dev_name = "mmci-omap-hs.1", | 218 | .dev_name = "mmci-omap-hs.0", |
| 167 | }, | 219 | }, |
| 168 | }; | 220 | }; |
| 169 | 221 | ||
| @@ -210,6 +262,8 @@ static struct regulator_init_data sdp4430_vaux1 = { | |||
| 210 | | REGULATOR_CHANGE_MODE | 262 | | REGULATOR_CHANGE_MODE |
| 211 | | REGULATOR_CHANGE_STATUS, | 263 | | REGULATOR_CHANGE_STATUS, |
| 212 | }, | 264 | }, |
| 265 | .num_consumer_supplies = 1, | ||
| 266 | .consumer_supplies = sdp4430_vaux_supply, | ||
| 213 | }; | 267 | }; |
| 214 | 268 | ||
| 215 | static struct regulator_init_data sdp4430_vaux2 = { | 269 | static struct regulator_init_data sdp4430_vaux2 = { |
| @@ -250,7 +304,7 @@ static struct regulator_init_data sdp4430_vmmc = { | |||
| 250 | | REGULATOR_CHANGE_MODE | 304 | | REGULATOR_CHANGE_MODE |
| 251 | | REGULATOR_CHANGE_STATUS, | 305 | | REGULATOR_CHANGE_STATUS, |
| 252 | }, | 306 | }, |
| 253 | .num_consumer_supplies = 2, | 307 | .num_consumer_supplies = 1, |
| 254 | .consumer_supplies = sdp4430_vmmc_supply, | 308 | .consumer_supplies = sdp4430_vmmc_supply, |
| 255 | }; | 309 | }; |
| 256 | 310 | ||
| @@ -353,6 +407,11 @@ static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = { | |||
| 353 | .platform_data = &sdp4430_twldata, | 407 | .platform_data = &sdp4430_twldata, |
| 354 | }, | 408 | }, |
| 355 | }; | 409 | }; |
| 410 | static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = { | ||
| 411 | { | ||
| 412 | I2C_BOARD_INFO("tmp105", 0x48), | ||
| 413 | }, | ||
| 414 | }; | ||
| 356 | static int __init omap4_i2c_init(void) | 415 | static int __init omap4_i2c_init(void) |
| 357 | { | 416 | { |
| 358 | /* | 417 | /* |
| @@ -362,7 +421,8 @@ static int __init omap4_i2c_init(void) | |||
| 362 | omap_register_i2c_bus(1, 400, sdp4430_i2c_boardinfo, | 421 | omap_register_i2c_bus(1, 400, sdp4430_i2c_boardinfo, |
| 363 | ARRAY_SIZE(sdp4430_i2c_boardinfo)); | 422 | ARRAY_SIZE(sdp4430_i2c_boardinfo)); |
| 364 | omap_register_i2c_bus(2, 400, NULL, 0); | 423 | omap_register_i2c_bus(2, 400, NULL, 0); |
| 365 | omap_register_i2c_bus(3, 400, NULL, 0); | 424 | omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, |
| 425 | ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); | ||
| 366 | omap_register_i2c_bus(4, 400, NULL, 0); | 426 | omap_register_i2c_bus(4, 400, NULL, 0); |
| 367 | return 0; | 427 | return 0; |
| 368 | } | 428 | } |
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 7da92defcde0..4d0f58592864 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c | |||
| @@ -461,17 +461,11 @@ static void __init am3517_evm_init(void) | |||
| 461 | am3517_evm_ethernet_init(&am3517_evm_emac_pdata); | 461 | am3517_evm_ethernet_init(&am3517_evm_emac_pdata); |
| 462 | } | 462 | } |
| 463 | 463 | ||
| 464 | static void __init am3517_evm_map_io(void) | ||
| 465 | { | ||
| 466 | omap2_set_globals_343x(); | ||
| 467 | omap34xx_map_common_io(); | ||
| 468 | } | ||
| 469 | |||
| 470 | MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") | 464 | MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") |
| 471 | .phys_io = 0x48000000, | 465 | .phys_io = 0x48000000, |
| 472 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 466 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, |
| 473 | .boot_params = 0x80000100, | 467 | .boot_params = 0x80000100, |
| 474 | .map_io = am3517_evm_map_io, | 468 | .map_io = omap3_map_io, |
| 475 | .reserve = omap_reserve, | 469 | .reserve = omap_reserve, |
| 476 | .init_irq = am3517_evm_init_irq, | 470 | .init_irq = am3517_evm_init_irq, |
| 477 | .init_machine = am3517_evm_init, | 471 | .init_machine = am3517_evm_init, |
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index bd75642aee65..c6421a72514a 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c | |||
| @@ -35,13 +35,14 @@ | |||
| 35 | 35 | ||
| 36 | #include <mach/gpio.h> | 36 | #include <mach/gpio.h> |
| 37 | #include <plat/led.h> | 37 | #include <plat/led.h> |
| 38 | #include <plat/mux.h> | ||
| 39 | #include <plat/usb.h> | 38 | #include <plat/usb.h> |
| 40 | #include <plat/board.h> | 39 | #include <plat/board.h> |
| 41 | #include <plat/common.h> | 40 | #include <plat/common.h> |
| 42 | #include <plat/gpmc.h> | 41 | #include <plat/gpmc.h> |
| 43 | #include <plat/control.h> | 42 | #include <plat/control.h> |
| 44 | 43 | ||
| 44 | #include "mux.h" | ||
| 45 | |||
| 45 | /* LED & Switch macros */ | 46 | /* LED & Switch macros */ |
| 46 | #define LED0_GPIO13 13 | 47 | #define LED0_GPIO13 13 |
| 47 | #define LED1_GPIO14 14 | 48 | #define LED1_GPIO14 14 |
| @@ -244,7 +245,7 @@ static inline void __init apollon_init_smc91x(void) | |||
| 244 | apollon_smc91x_resources[0].end = base + 0x30f; | 245 | apollon_smc91x_resources[0].end = base + 0x30f; |
| 245 | udelay(100); | 246 | udelay(100); |
| 246 | 247 | ||
| 247 | omap_cfg_reg(W4__24XX_GPIO74); | 248 | omap_mux_init_gpio(74, 0); |
| 248 | if (gpio_request(APOLLON_ETHR_GPIO_IRQ, "SMC91x irq") < 0) { | 249 | if (gpio_request(APOLLON_ETHR_GPIO_IRQ, "SMC91x irq") < 0) { |
| 249 | printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", | 250 | printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", |
| 250 | APOLLON_ETHR_GPIO_IRQ); | 251 | APOLLON_ETHR_GPIO_IRQ); |
| @@ -286,15 +287,15 @@ static void __init omap_apollon_init_irq(void) | |||
| 286 | static void __init apollon_led_init(void) | 287 | static void __init apollon_led_init(void) |
| 287 | { | 288 | { |
| 288 | /* LED0 - AA10 */ | 289 | /* LED0 - AA10 */ |
| 289 | omap_cfg_reg(AA10_242X_GPIO13); | 290 | omap_mux_init_signal("vlynq_clk.gpio_13", 0); |
| 290 | gpio_request(LED0_GPIO13, "LED0"); | 291 | gpio_request(LED0_GPIO13, "LED0"); |
| 291 | gpio_direction_output(LED0_GPIO13, 0); | 292 | gpio_direction_output(LED0_GPIO13, 0); |
| 292 | /* LED1 - AA6 */ | 293 | /* LED1 - AA6 */ |
| 293 | omap_cfg_reg(AA6_242X_GPIO14); | 294 | omap_mux_init_signal("vlynq_rx1.gpio_14", 0); |
| 294 | gpio_request(LED1_GPIO14, "LED1"); | 295 | gpio_request(LED1_GPIO14, "LED1"); |
| 295 | gpio_direction_output(LED1_GPIO14, 0); | 296 | gpio_direction_output(LED1_GPIO14, 0); |
| 296 | /* LED2 - AA4 */ | 297 | /* LED2 - AA4 */ |
| 297 | omap_cfg_reg(AA4_242X_GPIO15); | 298 | omap_mux_init_signal("vlynq_rx0.gpio_15", 0); |
| 298 | gpio_request(LED2_GPIO15, "LED2"); | 299 | gpio_request(LED2_GPIO15, "LED2"); |
| 299 | gpio_direction_output(LED2_GPIO15, 0); | 300 | gpio_direction_output(LED2_GPIO15, 0); |
| 300 | } | 301 | } |
| @@ -303,22 +304,35 @@ static void __init apollon_usb_init(void) | |||
| 303 | { | 304 | { |
| 304 | /* USB device */ | 305 | /* USB device */ |
| 305 | /* DEVICE_SUSPEND */ | 306 | /* DEVICE_SUSPEND */ |
| 306 | omap_cfg_reg(P21_242X_GPIO12); | 307 | omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0); |
| 307 | gpio_request(12, "USB suspend"); | 308 | gpio_request(12, "USB suspend"); |
| 308 | gpio_direction_output(12, 0); | 309 | gpio_direction_output(12, 0); |
| 309 | omap_usb_init(&apollon_usb_config); | 310 | omap2_usbfs_init(&apollon_usb_config); |
| 310 | } | 311 | } |
| 311 | 312 | ||
| 313 | #ifdef CONFIG_OMAP_MUX | ||
| 314 | static struct omap_board_mux board_mux[] __initdata = { | ||
| 315 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 316 | }; | ||
| 317 | #else | ||
| 318 | #define board_mux NULL | ||
| 319 | #endif | ||
| 320 | |||
| 312 | static void __init omap_apollon_init(void) | 321 | static void __init omap_apollon_init(void) |
| 313 | { | 322 | { |
| 314 | u32 v; | 323 | u32 v; |
| 315 | 324 | ||
| 325 | omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); | ||
| 326 | |||
| 316 | apollon_led_init(); | 327 | apollon_led_init(); |
| 317 | apollon_flash_init(); | 328 | apollon_flash_init(); |
| 318 | apollon_usb_init(); | 329 | apollon_usb_init(); |
| 319 | 330 | ||
| 320 | /* REVISIT: where's the correct place */ | 331 | /* REVISIT: where's the correct place */ |
| 321 | omap_cfg_reg(W19_24XX_SYS_NIRQ); | 332 | omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP); |
| 333 | |||
| 334 | /* LCD PWR_EN */ | ||
| 335 | omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP); | ||
| 322 | 336 | ||
| 323 | /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */ | 337 | /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */ |
| 324 | v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | 338 | v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); |
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index bc4c3f807068..e10bc109415c 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c | |||
| @@ -61,8 +61,6 @@ | |||
| 61 | #define SB_T35_SMSC911X_GPIO 65 | 61 | #define SB_T35_SMSC911X_GPIO 65 |
| 62 | 62 | ||
| 63 | #define NAND_BLOCK_SIZE SZ_128K | 63 | #define NAND_BLOCK_SIZE SZ_128K |
| 64 | #define GPMC_CS0_BASE 0x60 | ||
| 65 | #define GPMC_CS0_BASE_ADDR (OMAP34XX_GPMC_VIRT + GPMC_CS0_BASE) | ||
| 66 | 64 | ||
| 67 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | 65 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) |
| 68 | #include <linux/smsc911x.h> | 66 | #include <linux/smsc911x.h> |
| @@ -223,28 +221,12 @@ static struct omap_nand_platform_data cm_t35_nand_data = { | |||
| 223 | .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions), | 221 | .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions), |
| 224 | .dma_channel = -1, /* disable DMA in OMAP NAND driver */ | 222 | .dma_channel = -1, /* disable DMA in OMAP NAND driver */ |
| 225 | .cs = 0, | 223 | .cs = 0, |
| 226 | .gpmc_cs_baseaddr = (void __iomem *)GPMC_CS0_BASE_ADDR, | ||
| 227 | .gpmc_baseaddr = (void __iomem *)OMAP34XX_GPMC_VIRT, | ||
| 228 | 224 | ||
| 229 | }; | 225 | }; |
| 230 | 226 | ||
| 231 | static struct resource cm_t35_nand_resource = { | ||
| 232 | .flags = IORESOURCE_MEM, | ||
| 233 | }; | ||
| 234 | |||
| 235 | static struct platform_device cm_t35_nand_device = { | ||
| 236 | .name = "omap2-nand", | ||
| 237 | .id = -1, | ||
| 238 | .num_resources = 1, | ||
| 239 | .resource = &cm_t35_nand_resource, | ||
| 240 | .dev = { | ||
| 241 | .platform_data = &cm_t35_nand_data, | ||
| 242 | }, | ||
| 243 | }; | ||
| 244 | |||
| 245 | static void __init cm_t35_init_nand(void) | 227 | static void __init cm_t35_init_nand(void) |
| 246 | { | 228 | { |
| 247 | if (platform_device_register(&cm_t35_nand_device) < 0) | 229 | if (gpmc_nand_init(&cm_t35_nand_data) < 0) |
| 248 | pr_err("CM-T35: Unable to register NAND device\n"); | 230 | pr_err("CM-T35: Unable to register NAND device\n"); |
| 249 | } | 231 | } |
| 250 | #else | 232 | #else |
| @@ -708,12 +690,6 @@ static void __init cm_t35_init_irq(void) | |||
| 708 | omap_gpio_init(); | 690 | omap_gpio_init(); |
| 709 | } | 691 | } |
| 710 | 692 | ||
| 711 | static void __init cm_t35_map_io(void) | ||
| 712 | { | ||
| 713 | omap2_set_globals_343x(); | ||
| 714 | omap34xx_map_common_io(); | ||
| 715 | } | ||
| 716 | |||
| 717 | static struct omap_board_mux board_mux[] __initdata = { | 693 | static struct omap_board_mux board_mux[] __initdata = { |
| 718 | /* nCS and IRQ for CM-T35 ethernet */ | 694 | /* nCS and IRQ for CM-T35 ethernet */ |
| 719 | OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0), | 695 | OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0), |
| @@ -836,7 +812,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35") | |||
| 836 | .phys_io = 0x48000000, | 812 | .phys_io = 0x48000000, |
| 837 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 813 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, |
| 838 | .boot_params = 0x80000100, | 814 | .boot_params = 0x80000100, |
| 839 | .map_io = cm_t35_map_io, | 815 | .map_io = omap3_map_io, |
| 840 | .reserve = omap_reserve, | 816 | .reserve = omap_reserve, |
| 841 | .init_irq = cm_t35_init_irq, | 817 | .init_irq = cm_t35_init_irq, |
| 842 | .init_machine = cm_t35_init, | 818 | .init_machine = cm_t35_init, |
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 922b7464807f..a07086d6a0b2 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | #include <linux/i2c/twl.h> | 33 | #include <linux/i2c/twl.h> |
| 34 | 34 | ||
| 35 | #include <mach/hardware.h> | 35 | #include <mach/hardware.h> |
| 36 | #include <mach/id.h> | ||
| 36 | #include <asm/mach-types.h> | 37 | #include <asm/mach-types.h> |
| 37 | #include <asm/mach/arch.h> | 38 | #include <asm/mach/arch.h> |
| 38 | #include <asm/mach/map.h> | 39 | #include <asm/mach/map.h> |
| @@ -58,9 +59,6 @@ | |||
| 58 | #include "mux.h" | 59 | #include "mux.h" |
| 59 | #include "hsmmc.h" | 60 | #include "hsmmc.h" |
| 60 | 61 | ||
| 61 | #define GPMC_CS0_BASE 0x60 | ||
| 62 | #define GPMC_CS_SIZE 0x30 | ||
| 63 | |||
| 64 | #define NAND_BLOCK_SIZE SZ_128K | 62 | #define NAND_BLOCK_SIZE SZ_128K |
| 65 | 63 | ||
| 66 | #define OMAP_DM9000_GPIO_IRQ 25 | 64 | #define OMAP_DM9000_GPIO_IRQ 25 |
| @@ -104,20 +102,6 @@ static struct omap_nand_platform_data devkit8000_nand_data = { | |||
| 104 | .dma_channel = -1, /* disable DMA in OMAP NAND driver */ | 102 | .dma_channel = -1, /* disable DMA in OMAP NAND driver */ |
| 105 | }; | 103 | }; |
| 106 | 104 | ||
| 107 | static struct resource devkit8000_nand_resource = { | ||
| 108 | .flags = IORESOURCE_MEM, | ||
| 109 | }; | ||
| 110 | |||
| 111 | static struct platform_device devkit8000_nand_device = { | ||
| 112 | .name = "omap2-nand", | ||
| 113 | .id = -1, | ||
| 114 | .dev = { | ||
| 115 | .platform_data = &devkit8000_nand_data, | ||
| 116 | }, | ||
| 117 | .num_resources = 1, | ||
| 118 | .resource = &devkit8000_nand_resource, | ||
| 119 | }; | ||
| 120 | |||
| 121 | static struct omap2_hsmmc_info mmc[] = { | 105 | static struct omap2_hsmmc_info mmc[] = { |
| 122 | { | 106 | { |
| 123 | .mmc = 1, | 107 | .mmc = 1, |
| @@ -126,54 +110,50 @@ static struct omap2_hsmmc_info mmc[] = { | |||
| 126 | }, | 110 | }, |
| 127 | {} /* Terminator */ | 111 | {} /* Terminator */ |
| 128 | }; | 112 | }; |
| 129 | static struct omap_board_config_kernel devkit8000_config[] __initdata = { | ||
| 130 | }; | ||
| 131 | 113 | ||
| 132 | static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev) | 114 | static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev) |
| 133 | { | 115 | { |
| 134 | twl_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80, REG_GPIODATADIR1); | 116 | twl_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80, REG_GPIODATADIR1); |
| 135 | twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0); | 117 | twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0); |
| 136 | 118 | ||
| 119 | if (gpio_is_valid(dssdev->reset_gpio)) | ||
| 120 | gpio_set_value(dssdev->reset_gpio, 1); | ||
| 137 | return 0; | 121 | return 0; |
| 138 | } | 122 | } |
| 139 | 123 | ||
| 140 | static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev) | 124 | static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev) |
| 141 | { | 125 | { |
| 126 | if (gpio_is_valid(dssdev->reset_gpio)) | ||
| 127 | gpio_set_value(dssdev->reset_gpio, 0); | ||
| 142 | } | 128 | } |
| 129 | |||
| 143 | static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev) | 130 | static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev) |
| 144 | { | 131 | { |
| 132 | if (gpio_is_valid(dssdev->reset_gpio)) | ||
| 133 | gpio_set_value(dssdev->reset_gpio, 1); | ||
| 145 | return 0; | 134 | return 0; |
| 146 | } | 135 | } |
| 147 | 136 | ||
| 148 | static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev) | 137 | static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev) |
| 149 | { | 138 | { |
| 139 | if (gpio_is_valid(dssdev->reset_gpio)) | ||
| 140 | gpio_set_value(dssdev->reset_gpio, 0); | ||
| 150 | } | 141 | } |
| 151 | 142 | ||
| 152 | static int devkit8000_panel_enable_tv(struct omap_dss_device *dssdev) | 143 | static struct regulator_consumer_supply devkit8000_vmmc1_supply = |
| 153 | { | 144 | REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); |
| 154 | 145 | ||
| 155 | return 0; | ||
| 156 | } | ||
| 157 | |||
| 158 | static void devkit8000_panel_disable_tv(struct omap_dss_device *dssdev) | ||
| 159 | { | ||
| 160 | } | ||
| 161 | |||
| 162 | |||
| 163 | static struct regulator_consumer_supply devkit8000_vmmc1_supply = { | ||
| 164 | .supply = "vmmc", | ||
| 165 | }; | ||
| 166 | |||
| 167 | static struct regulator_consumer_supply devkit8000_vsim_supply = { | ||
| 168 | .supply = "vmmc_aux", | ||
| 169 | }; | ||
| 170 | 146 | ||
| 147 | /* ads7846 on SPI */ | ||
| 148 | static struct regulator_consumer_supply devkit8000_vio_supply = | ||
| 149 | REGULATOR_SUPPLY("vcc", "spi2.0"); | ||
| 171 | 150 | ||
| 172 | static struct omap_dss_device devkit8000_lcd_device = { | 151 | static struct omap_dss_device devkit8000_lcd_device = { |
| 173 | .name = "lcd", | 152 | .name = "lcd", |
| 174 | .driver_name = "innolux_at_panel", | 153 | .driver_name = "generic_panel", |
| 175 | .type = OMAP_DISPLAY_TYPE_DPI, | 154 | .type = OMAP_DISPLAY_TYPE_DPI, |
| 176 | .phy.dpi.data_lines = 24, | 155 | .phy.dpi.data_lines = 24, |
| 156 | .reset_gpio = -EINVAL, /* will be replaced */ | ||
| 177 | .platform_enable = devkit8000_panel_enable_lcd, | 157 | .platform_enable = devkit8000_panel_enable_lcd, |
| 178 | .platform_disable = devkit8000_panel_disable_lcd, | 158 | .platform_disable = devkit8000_panel_disable_lcd, |
| 179 | }; | 159 | }; |
| @@ -182,6 +162,7 @@ static struct omap_dss_device devkit8000_dvi_device = { | |||
| 182 | .driver_name = "generic_panel", | 162 | .driver_name = "generic_panel", |
| 183 | .type = OMAP_DISPLAY_TYPE_DPI, | 163 | .type = OMAP_DISPLAY_TYPE_DPI, |
| 184 | .phy.dpi.data_lines = 24, | 164 | .phy.dpi.data_lines = 24, |
| 165 | .reset_gpio = -EINVAL, /* will be replaced */ | ||
| 185 | .platform_enable = devkit8000_panel_enable_dvi, | 166 | .platform_enable = devkit8000_panel_enable_dvi, |
| 186 | .platform_disable = devkit8000_panel_disable_dvi, | 167 | .platform_disable = devkit8000_panel_disable_dvi, |
| 187 | }; | 168 | }; |
| @@ -191,8 +172,6 @@ static struct omap_dss_device devkit8000_tv_device = { | |||
| 191 | .driver_name = "venc", | 172 | .driver_name = "venc", |
| 192 | .type = OMAP_DISPLAY_TYPE_VENC, | 173 | .type = OMAP_DISPLAY_TYPE_VENC, |
| 193 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | 174 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, |
| 194 | .platform_enable = devkit8000_panel_enable_tv, | ||
| 195 | .platform_disable = devkit8000_panel_disable_tv, | ||
| 196 | }; | 175 | }; |
| 197 | 176 | ||
| 198 | 177 | ||
| @@ -216,10 +195,8 @@ static struct platform_device devkit8000_dss_device = { | |||
| 216 | }, | 195 | }, |
| 217 | }; | 196 | }; |
| 218 | 197 | ||
| 219 | static struct regulator_consumer_supply devkit8000_vdda_dac_supply = { | 198 | static struct regulator_consumer_supply devkit8000_vdda_dac_supply = |
| 220 | .supply = "vdda_dac", | 199 | REGULATOR_SUPPLY("vdda_dac", "omapdss"); |
| 221 | .dev = &devkit8000_dss_device.dev, | ||
| 222 | }; | ||
| 223 | 200 | ||
| 224 | static int board_keymap[] = { | 201 | static int board_keymap[] = { |
| 225 | KEY(0, 0, KEY_1), | 202 | KEY(0, 0, KEY_1), |
| @@ -266,7 +243,21 @@ static int devkit8000_twl_gpio_setup(struct device *dev, | |||
| 266 | 243 | ||
| 267 | /* link regulators to MMC adapters */ | 244 | /* link regulators to MMC adapters */ |
| 268 | devkit8000_vmmc1_supply.dev = mmc[0].dev; | 245 | devkit8000_vmmc1_supply.dev = mmc[0].dev; |
| 269 | devkit8000_vsim_supply.dev = mmc[0].dev; | 246 | |
| 247 | /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ | ||
| 248 | gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; | ||
| 249 | |||
| 250 | /* gpio + 1 is "LCD_PWREN" (out, active high) */ | ||
| 251 | devkit8000_lcd_device.reset_gpio = gpio + 1; | ||
| 252 | gpio_request(devkit8000_lcd_device.reset_gpio, "LCD_PWREN"); | ||
| 253 | /* Disable until needed */ | ||
| 254 | gpio_direction_output(devkit8000_lcd_device.reset_gpio, 0); | ||
| 255 | |||
| 256 | /* gpio + 7 is "DVI_PD" (out, active low) */ | ||
| 257 | devkit8000_dvi_device.reset_gpio = gpio + 7; | ||
| 258 | gpio_request(devkit8000_dvi_device.reset_gpio, "DVI PowerDown"); | ||
| 259 | /* Disable until needed */ | ||
| 260 | gpio_direction_output(devkit8000_dvi_device.reset_gpio, 0); | ||
| 270 | 261 | ||
| 271 | return 0; | 262 | return 0; |
| 272 | } | 263 | } |
| @@ -282,16 +273,8 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = { | |||
| 282 | .setup = devkit8000_twl_gpio_setup, | 273 | .setup = devkit8000_twl_gpio_setup, |
| 283 | }; | 274 | }; |
| 284 | 275 | ||
| 285 | static struct regulator_consumer_supply devkit8000_vpll2_supplies[] = { | 276 | static struct regulator_consumer_supply devkit8000_vpll1_supply = |
| 286 | { | 277 | REGULATOR_SUPPLY("vdds_dsi", "omapdss"); |
| 287 | .supply = "vdvi", | ||
| 288 | .dev = &devkit8000_lcd_device.dev, | ||
| 289 | }, | ||
| 290 | { | ||
| 291 | .supply = "vdds_dsi", | ||
| 292 | .dev = &devkit8000_dss_device.dev, | ||
| 293 | } | ||
| 294 | }; | ||
| 295 | 278 | ||
| 296 | /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ | 279 | /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ |
| 297 | static struct regulator_init_data devkit8000_vmmc1 = { | 280 | static struct regulator_init_data devkit8000_vmmc1 = { |
| @@ -308,21 +291,6 @@ static struct regulator_init_data devkit8000_vmmc1 = { | |||
| 308 | .consumer_supplies = &devkit8000_vmmc1_supply, | 291 | .consumer_supplies = &devkit8000_vmmc1_supply, |
| 309 | }; | 292 | }; |
| 310 | 293 | ||
| 311 | /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ | ||
| 312 | static struct regulator_init_data devkit8000_vsim = { | ||
| 313 | .constraints = { | ||
| 314 | .min_uV = 1800000, | ||
| 315 | .max_uV = 3000000, | ||
| 316 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 317 | | REGULATOR_MODE_STANDBY, | ||
| 318 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 319 | | REGULATOR_CHANGE_MODE | ||
| 320 | | REGULATOR_CHANGE_STATUS, | ||
| 321 | }, | ||
| 322 | .num_consumer_supplies = 1, | ||
| 323 | .consumer_supplies = &devkit8000_vsim_supply, | ||
| 324 | }; | ||
| 325 | |||
| 326 | /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ | 294 | /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ |
| 327 | static struct regulator_init_data devkit8000_vdac = { | 295 | static struct regulator_init_data devkit8000_vdac = { |
| 328 | .constraints = { | 296 | .constraints = { |
| @@ -337,10 +305,9 @@ static struct regulator_init_data devkit8000_vdac = { | |||
| 337 | .consumer_supplies = &devkit8000_vdda_dac_supply, | 305 | .consumer_supplies = &devkit8000_vdda_dac_supply, |
| 338 | }; | 306 | }; |
| 339 | 307 | ||
| 340 | /* VPLL2 for digital video outputs */ | 308 | /* VPLL1 for digital video outputs */ |
| 341 | static struct regulator_init_data devkit8000_vpll2 = { | 309 | static struct regulator_init_data devkit8000_vpll1 = { |
| 342 | .constraints = { | 310 | .constraints = { |
| 343 | .name = "VDVI", | ||
| 344 | .min_uV = 1800000, | 311 | .min_uV = 1800000, |
| 345 | .max_uV = 1800000, | 312 | .max_uV = 1800000, |
| 346 | .valid_modes_mask = REGULATOR_MODE_NORMAL | 313 | .valid_modes_mask = REGULATOR_MODE_NORMAL |
| @@ -348,8 +315,23 @@ static struct regulator_init_data devkit8000_vpll2 = { | |||
| 348 | .valid_ops_mask = REGULATOR_CHANGE_MODE | 315 | .valid_ops_mask = REGULATOR_CHANGE_MODE |
| 349 | | REGULATOR_CHANGE_STATUS, | 316 | | REGULATOR_CHANGE_STATUS, |
| 350 | }, | 317 | }, |
| 351 | .num_consumer_supplies = ARRAY_SIZE(devkit8000_vpll2_supplies), | 318 | .num_consumer_supplies = 1, |
| 352 | .consumer_supplies = devkit8000_vpll2_supplies, | 319 | .consumer_supplies = &devkit8000_vpll1_supply, |
| 320 | }; | ||
| 321 | |||
| 322 | /* VAUX4 for ads7846 and nubs */ | ||
| 323 | static struct regulator_init_data devkit8000_vio = { | ||
| 324 | .constraints = { | ||
| 325 | .min_uV = 1800000, | ||
| 326 | .max_uV = 1800000, | ||
| 327 | .apply_uV = true, | ||
| 328 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 329 | | REGULATOR_MODE_STANDBY, | ||
| 330 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 331 | | REGULATOR_CHANGE_STATUS, | ||
| 332 | }, | ||
| 333 | .num_consumer_supplies = 1, | ||
| 334 | .consumer_supplies = &devkit8000_vio_supply, | ||
| 353 | }; | 335 | }; |
| 354 | 336 | ||
| 355 | static struct twl4030_usb_data devkit8000_usb_data = { | 337 | static struct twl4030_usb_data devkit8000_usb_data = { |
| @@ -374,15 +356,15 @@ static struct twl4030_platform_data devkit8000_twldata = { | |||
| 374 | .gpio = &devkit8000_gpio_data, | 356 | .gpio = &devkit8000_gpio_data, |
| 375 | .codec = &devkit8000_codec_data, | 357 | .codec = &devkit8000_codec_data, |
| 376 | .vmmc1 = &devkit8000_vmmc1, | 358 | .vmmc1 = &devkit8000_vmmc1, |
| 377 | .vsim = &devkit8000_vsim, | ||
| 378 | .vdac = &devkit8000_vdac, | 359 | .vdac = &devkit8000_vdac, |
| 379 | .vpll2 = &devkit8000_vpll2, | 360 | .vpll1 = &devkit8000_vpll1, |
| 361 | .vio = &devkit8000_vio, | ||
| 380 | .keypad = &devkit8000_kp_data, | 362 | .keypad = &devkit8000_kp_data, |
| 381 | }; | 363 | }; |
| 382 | 364 | ||
| 383 | static struct i2c_board_info __initdata devkit8000_i2c_boardinfo[] = { | 365 | static struct i2c_board_info __initdata devkit8000_i2c_boardinfo[] = { |
| 384 | { | 366 | { |
| 385 | I2C_BOARD_INFO("twl4030", 0x48), | 367 | I2C_BOARD_INFO("tps65930", 0x48), |
| 386 | .flags = I2C_CLIENT_WAKE, | 368 | .flags = I2C_CLIENT_WAKE, |
| 387 | .irq = INT_34XX_SYS_NIRQ, | 369 | .irq = INT_34XX_SYS_NIRQ, |
| 388 | .platform_data = &devkit8000_twldata, | 370 | .platform_data = &devkit8000_twldata, |
| @@ -464,8 +446,6 @@ static struct platform_device keys_gpio = { | |||
| 464 | 446 | ||
| 465 | static void __init devkit8000_init_irq(void) | 447 | static void __init devkit8000_init_irq(void) |
| 466 | { | 448 | { |
| 467 | omap_board_config = devkit8000_config; | ||
| 468 | omap_board_config_size = ARRAY_SIZE(devkit8000_config); | ||
| 469 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, | 449 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, |
| 470 | mt46h32m32lf6_sdrc_params); | 450 | mt46h32m32lf6_sdrc_params); |
| 471 | omap_init_irq(); | 451 | omap_init_irq(); |
| @@ -560,6 +540,9 @@ static struct platform_device omap_dm9000_dev = { | |||
| 560 | 540 | ||
| 561 | static void __init omap_dm9000_init(void) | 541 | static void __init omap_dm9000_init(void) |
| 562 | { | 542 | { |
| 543 | unsigned char *eth_addr = omap_dm9000_platdata.dev_addr; | ||
| 544 | struct omap_die_id odi; | ||
| 545 | |||
| 563 | if (gpio_request(OMAP_DM9000_GPIO_IRQ, "dm9000 irq") < 0) { | 546 | if (gpio_request(OMAP_DM9000_GPIO_IRQ, "dm9000 irq") < 0) { |
| 564 | printk(KERN_ERR "Failed to request GPIO%d for dm9000 IRQ\n", | 547 | printk(KERN_ERR "Failed to request GPIO%d for dm9000 IRQ\n", |
| 565 | OMAP_DM9000_GPIO_IRQ); | 548 | OMAP_DM9000_GPIO_IRQ); |
| @@ -567,6 +550,16 @@ static void __init omap_dm9000_init(void) | |||
| 567 | } | 550 | } |
| 568 | 551 | ||
| 569 | gpio_direction_input(OMAP_DM9000_GPIO_IRQ); | 552 | gpio_direction_input(OMAP_DM9000_GPIO_IRQ); |
| 553 | |||
| 554 | /* init the mac address using DIE id */ | ||
| 555 | omap_get_die_id(&odi); | ||
| 556 | |||
| 557 | eth_addr[0] = 0x02; /* locally administered */ | ||
| 558 | eth_addr[1] = odi.id_1 & 0xff; | ||
| 559 | eth_addr[2] = (odi.id_0 & 0xff000000) >> 24; | ||
| 560 | eth_addr[3] = (odi.id_0 & 0x00ff0000) >> 16; | ||
| 561 | eth_addr[4] = (odi.id_0 & 0x0000ff00) >> 8; | ||
| 562 | eth_addr[5] = (odi.id_0 & 0x000000ff); | ||
| 570 | } | 563 | } |
| 571 | 564 | ||
| 572 | static struct platform_device *devkit8000_devices[] __initdata = { | 565 | static struct platform_device *devkit8000_devices[] __initdata = { |
| @@ -581,8 +574,6 @@ static void __init devkit8000_flash_init(void) | |||
| 581 | u8 cs = 0; | 574 | u8 cs = 0; |
| 582 | u8 nandcs = GPMC_CS_NUM + 1; | 575 | u8 nandcs = GPMC_CS_NUM + 1; |
| 583 | 576 | ||
| 584 | u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; | ||
| 585 | |||
| 586 | /* find out the chip-select on which NAND exists */ | 577 | /* find out the chip-select on which NAND exists */ |
| 587 | while (cs < GPMC_CS_NUM) { | 578 | while (cs < GPMC_CS_NUM) { |
| 588 | u32 ret = 0; | 579 | u32 ret = 0; |
| @@ -604,13 +595,9 @@ static void __init devkit8000_flash_init(void) | |||
| 604 | 595 | ||
| 605 | if (nandcs < GPMC_CS_NUM) { | 596 | if (nandcs < GPMC_CS_NUM) { |
| 606 | devkit8000_nand_data.cs = nandcs; | 597 | devkit8000_nand_data.cs = nandcs; |
| 607 | devkit8000_nand_data.gpmc_cs_baseaddr = (void *) | ||
| 608 | (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); | ||
| 609 | devkit8000_nand_data.gpmc_baseaddr = (void *) | ||
| 610 | (gpmc_base_add); | ||
| 611 | 598 | ||
| 612 | printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); | 599 | printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); |
| 613 | if (platform_device_register(&devkit8000_nand_device) < 0) | 600 | if (gpmc_nand_init(&devkit8000_nand_data) < 0) |
| 614 | printk(KERN_ERR "Unable to register NAND device\n"); | 601 | printk(KERN_ERR "Unable to register NAND device\n"); |
| 615 | } | 602 | } |
| 616 | } | 603 | } |
| @@ -797,8 +784,6 @@ static void __init devkit8000_init(void) | |||
| 797 | devkit8000_i2c_init(); | 784 | devkit8000_i2c_init(); |
| 798 | platform_add_devices(devkit8000_devices, | 785 | platform_add_devices(devkit8000_devices, |
| 799 | ARRAY_SIZE(devkit8000_devices)); | 786 | ARRAY_SIZE(devkit8000_devices)); |
| 800 | omap_board_config = devkit8000_config; | ||
| 801 | omap_board_config_size = ARRAY_SIZE(devkit8000_config); | ||
| 802 | 787 | ||
| 803 | spi_register_board_info(devkit8000_spi_board_info, | 788 | spi_register_board_info(devkit8000_spi_board_info, |
| 804 | ARRAY_SIZE(devkit8000_spi_board_info)); | 789 | ARRAY_SIZE(devkit8000_spi_board_info)); |
| @@ -814,17 +799,11 @@ static void __init devkit8000_init(void) | |||
| 814 | omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); | 799 | omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); |
| 815 | } | 800 | } |
| 816 | 801 | ||
| 817 | static void __init devkit8000_map_io(void) | ||
| 818 | { | ||
| 819 | omap2_set_globals_343x(); | ||
| 820 | omap34xx_map_common_io(); | ||
| 821 | } | ||
| 822 | |||
| 823 | MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") | 802 | MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") |
| 824 | .phys_io = 0x48000000, | 803 | .phys_io = 0x48000000, |
| 825 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 804 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, |
| 826 | .boot_params = 0x80000100, | 805 | .boot_params = 0x80000100, |
| 827 | .map_io = devkit8000_map_io, | 806 | .map_io = omap3_map_io, |
| 828 | .reserve = omap_reserve, | 807 | .reserve = omap_reserve, |
| 829 | .init_irq = devkit8000_init_irq, | 808 | .init_irq = devkit8000_init_irq, |
| 830 | .init_machine = devkit8000_init, | 809 | .init_machine = devkit8000_init, |
diff --git a/arch/arm/mach-omap2/board-sdp-flash.c b/arch/arm/mach-omap2/board-flash.c index 2d026328e385..ac834aa7abf6 100644 --- a/arch/arm/mach-omap2/board-sdp-flash.c +++ b/arch/arm/mach-omap2/board-flash.c | |||
| @@ -21,7 +21,7 @@ | |||
| 21 | #include <plat/nand.h> | 21 | #include <plat/nand.h> |
| 22 | #include <plat/onenand.h> | 22 | #include <plat/onenand.h> |
| 23 | #include <plat/tc.h> | 23 | #include <plat/tc.h> |
| 24 | #include <mach/board-sdp.h> | 24 | #include <mach/board-flash.h> |
| 25 | 25 | ||
| 26 | #define REG_FPGA_REV 0x10 | 26 | #define REG_FPGA_REV 0x10 |
| 27 | #define REG_FPGA_DIP_SWITCH_INPUT2 0x60 | 27 | #define REG_FPGA_DIP_SWITCH_INPUT2 0x60 |
| @@ -29,72 +29,53 @@ | |||
| 29 | 29 | ||
| 30 | #define DEBUG_BASE 0x08000000 /* debug board */ | 30 | #define DEBUG_BASE 0x08000000 /* debug board */ |
| 31 | 31 | ||
| 32 | #define PDC_NOR 1 | ||
| 33 | #define PDC_NAND 2 | ||
| 34 | #define PDC_ONENAND 3 | ||
| 35 | #define DBG_MPDB 4 | ||
| 36 | |||
| 37 | /* various memory sizes */ | 32 | /* various memory sizes */ |
| 38 | #define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */ | 33 | #define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */ |
| 39 | #define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */ | 34 | #define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */ |
| 40 | 35 | ||
| 41 | /* | 36 | static struct physmap_flash_data board_nor_data = { |
| 42 | * SDP3430 V2 Board CS organization | ||
| 43 | * Different from SDP3430 V1. Now 4 switches used to specify CS | ||
| 44 | * | ||
| 45 | * See also the Switch S8 settings in the comments. | ||
| 46 | * | ||
| 47 | * REVISIT: Add support for 2430 SDP | ||
| 48 | */ | ||
| 49 | static const unsigned char chip_sel_sdp[][GPMC_CS_NUM] = { | ||
| 50 | {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */ | ||
| 51 | {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */ | ||
| 52 | {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */ | ||
| 53 | }; | ||
| 54 | |||
| 55 | static struct physmap_flash_data sdp_nor_data = { | ||
| 56 | .width = 2, | 37 | .width = 2, |
| 57 | }; | 38 | }; |
| 58 | 39 | ||
| 59 | static struct resource sdp_nor_resource = { | 40 | static struct resource board_nor_resource = { |
| 60 | .flags = IORESOURCE_MEM, | 41 | .flags = IORESOURCE_MEM, |
| 61 | }; | 42 | }; |
| 62 | 43 | ||
| 63 | static struct platform_device sdp_nor_device = { | 44 | static struct platform_device board_nor_device = { |
| 64 | .name = "physmap-flash", | 45 | .name = "physmap-flash", |
| 65 | .id = 0, | 46 | .id = 0, |
| 66 | .dev = { | 47 | .dev = { |
| 67 | .platform_data = &sdp_nor_data, | 48 | .platform_data = &board_nor_data, |
| 68 | }, | 49 | }, |
| 69 | .num_resources = 1, | 50 | .num_resources = 1, |
| 70 | .resource = &sdp_nor_resource, | 51 | .resource = &board_nor_resource, |
| 71 | }; | 52 | }; |
| 72 | 53 | ||
| 73 | static void | 54 | static void |
| 74 | __init board_nor_init(struct flash_partitions sdp_nor_parts, u8 cs) | 55 | __init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs) |
| 75 | { | 56 | { |
| 76 | int err; | 57 | int err; |
| 77 | 58 | ||
| 78 | sdp_nor_data.parts = sdp_nor_parts.parts; | 59 | board_nor_data.parts = nor_parts; |
| 79 | sdp_nor_data.nr_parts = sdp_nor_parts.nr_parts; | 60 | board_nor_data.nr_parts = nr_parts; |
| 80 | 61 | ||
| 81 | /* Configure start address and size of NOR device */ | 62 | /* Configure start address and size of NOR device */ |
| 82 | if (omap_rev() >= OMAP3430_REV_ES1_0) { | 63 | if (omap_rev() >= OMAP3430_REV_ES1_0) { |
| 83 | err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1, | 64 | err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1, |
| 84 | (unsigned long *)&sdp_nor_resource.start); | 65 | (unsigned long *)&board_nor_resource.start); |
| 85 | sdp_nor_resource.end = sdp_nor_resource.start | 66 | board_nor_resource.end = board_nor_resource.start |
| 86 | + FLASH_SIZE_SDPV2 - 1; | 67 | + FLASH_SIZE_SDPV2 - 1; |
| 87 | } else { | 68 | } else { |
| 88 | err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1, | 69 | err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1, |
| 89 | (unsigned long *)&sdp_nor_resource.start); | 70 | (unsigned long *)&board_nor_resource.start); |
| 90 | sdp_nor_resource.end = sdp_nor_resource.start | 71 | board_nor_resource.end = board_nor_resource.start |
| 91 | + FLASH_SIZE_SDPV1 - 1; | 72 | + FLASH_SIZE_SDPV1 - 1; |
| 92 | } | 73 | } |
| 93 | if (err < 0) { | 74 | if (err < 0) { |
| 94 | printk(KERN_ERR "NOR: Can't request GPMC CS\n"); | 75 | printk(KERN_ERR "NOR: Can't request GPMC CS\n"); |
| 95 | return; | 76 | return; |
| 96 | } | 77 | } |
| 97 | if (platform_device_register(&sdp_nor_device) < 0) | 78 | if (platform_device_register(&board_nor_device) < 0) |
| 98 | printk(KERN_ERR "Unable to register NOR device\n"); | 79 | printk(KERN_ERR "Unable to register NOR device\n"); |
| 99 | } | 80 | } |
| 100 | 81 | ||
| @@ -105,17 +86,18 @@ static struct omap_onenand_platform_data board_onenand_data = { | |||
| 105 | }; | 86 | }; |
| 106 | 87 | ||
| 107 | static void | 88 | static void |
| 108 | __init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs) | 89 | __init board_onenand_init(struct mtd_partition *onenand_parts, |
| 90 | u8 nr_parts, u8 cs) | ||
| 109 | { | 91 | { |
| 110 | board_onenand_data.cs = cs; | 92 | board_onenand_data.cs = cs; |
| 111 | board_onenand_data.parts = sdp_onenand_parts.parts; | 93 | board_onenand_data.parts = onenand_parts; |
| 112 | board_onenand_data.nr_parts = sdp_onenand_parts.nr_parts; | 94 | board_onenand_data.nr_parts = nr_parts; |
| 113 | 95 | ||
| 114 | gpmc_onenand_init(&board_onenand_data); | 96 | gpmc_onenand_init(&board_onenand_data); |
| 115 | } | 97 | } |
| 116 | #else | 98 | #else |
| 117 | static void | 99 | static void |
| 118 | __init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs) | 100 | __init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs) |
| 119 | { | 101 | { |
| 120 | } | 102 | } |
| 121 | #endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */ | 103 | #endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */ |
| @@ -147,7 +129,7 @@ static struct gpmc_timings nand_timings = { | |||
| 147 | .wr_data_mux_bus = 0, | 129 | .wr_data_mux_bus = 0, |
| 148 | }; | 130 | }; |
| 149 | 131 | ||
| 150 | static struct omap_nand_platform_data sdp_nand_data = { | 132 | static struct omap_nand_platform_data board_nand_data = { |
| 151 | .nand_setup = NULL, | 133 | .nand_setup = NULL, |
| 152 | .gpmc_t = &nand_timings, | 134 | .gpmc_t = &nand_timings, |
| 153 | .dma_channel = -1, /* disable DMA in OMAP NAND driver */ | 135 | .dma_channel = -1, /* disable DMA in OMAP NAND driver */ |
| @@ -155,23 +137,18 @@ static struct omap_nand_platform_data sdp_nand_data = { | |||
| 155 | .devsize = 0, /* '0' for 8-bit, '1' for 16-bit device */ | 137 | .devsize = 0, /* '0' for 8-bit, '1' for 16-bit device */ |
| 156 | }; | 138 | }; |
| 157 | 139 | ||
| 158 | static void | 140 | void |
| 159 | __init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs) | 141 | __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) |
| 160 | { | 142 | { |
| 161 | sdp_nand_data.cs = cs; | 143 | board_nand_data.cs = cs; |
| 162 | sdp_nand_data.parts = sdp_nand_parts.parts; | 144 | board_nand_data.parts = nand_parts; |
| 163 | sdp_nand_data.nr_parts = sdp_nand_parts.nr_parts; | 145 | board_nand_data.nr_parts = nr_parts; |
| 164 | 146 | ||
| 165 | sdp_nand_data.gpmc_cs_baseaddr = (void *)(OMAP34XX_GPMC_VIRT + | 147 | gpmc_nand_init(&board_nand_data); |
| 166 | GPMC_CS0_BASE + | ||
| 167 | cs * GPMC_CS_SIZE); | ||
| 168 | sdp_nand_data.gpmc_baseaddr = (void *) (OMAP34XX_GPMC_VIRT); | ||
| 169 | |||
| 170 | gpmc_nand_init(&sdp_nand_data); | ||
| 171 | } | 148 | } |
| 172 | #else | 149 | #else |
| 173 | static void | 150 | void |
| 174 | __init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs) | 151 | __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) |
| 175 | { | 152 | { |
| 176 | } | 153 | } |
| 177 | #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ | 154 | #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ |
| @@ -215,7 +192,8 @@ unmap: | |||
| 215 | * | 192 | * |
| 216 | * @return - void. | 193 | * @return - void. |
| 217 | */ | 194 | */ |
| 218 | void __init sdp_flash_init(struct flash_partitions sdp_partition_info[]) | 195 | void board_flash_init(struct flash_partitions partition_info[], |
| 196 | char chip_sel_board[][GPMC_CS_NUM]) | ||
| 219 | { | 197 | { |
| 220 | u8 cs = 0; | 198 | u8 cs = 0; |
| 221 | u8 norcs = GPMC_CS_NUM + 1; | 199 | u8 norcs = GPMC_CS_NUM + 1; |
| @@ -232,7 +210,7 @@ void __init sdp_flash_init(struct flash_partitions sdp_partition_info[]) | |||
| 232 | printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs); | 210 | printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs); |
| 233 | return; | 211 | return; |
| 234 | } | 212 | } |
| 235 | config_sel = (unsigned char *)(chip_sel_sdp[idx]); | 213 | config_sel = (unsigned char *)(chip_sel_board[idx]); |
| 236 | 214 | ||
| 237 | while (cs < GPMC_CS_NUM) { | 215 | while (cs < GPMC_CS_NUM) { |
| 238 | switch (config_sel[cs]) { | 216 | switch (config_sel[cs]) { |
| @@ -256,17 +234,20 @@ void __init sdp_flash_init(struct flash_partitions sdp_partition_info[]) | |||
| 256 | printk(KERN_INFO "NOR: Unable to find configuration " | 234 | printk(KERN_INFO "NOR: Unable to find configuration " |
| 257 | "in GPMC\n"); | 235 | "in GPMC\n"); |
| 258 | else | 236 | else |
| 259 | board_nor_init(sdp_partition_info[0], norcs); | 237 | board_nor_init(partition_info[0].parts, |
| 238 | partition_info[0].nr_parts, norcs); | ||
| 260 | 239 | ||
| 261 | if (onenandcs > GPMC_CS_NUM) | 240 | if (onenandcs > GPMC_CS_NUM) |
| 262 | printk(KERN_INFO "OneNAND: Unable to find configuration " | 241 | printk(KERN_INFO "OneNAND: Unable to find configuration " |
| 263 | "in GPMC\n"); | 242 | "in GPMC\n"); |
| 264 | else | 243 | else |
| 265 | board_onenand_init(sdp_partition_info[1], onenandcs); | 244 | board_onenand_init(partition_info[1].parts, |
| 245 | partition_info[1].nr_parts, onenandcs); | ||
| 266 | 246 | ||
| 267 | if (nandcs > GPMC_CS_NUM) | 247 | if (nandcs > GPMC_CS_NUM) |
| 268 | printk(KERN_INFO "NAND: Unable to find configuration " | 248 | printk(KERN_INFO "NAND: Unable to find configuration " |
| 269 | "in GPMC\n"); | 249 | "in GPMC\n"); |
| 270 | else | 250 | else |
| 271 | board_nand_init(sdp_partition_info[2], nandcs); | 251 | board_nand_init(partition_info[2].parts, |
| 252 | partition_info[2].nr_parts, nandcs); | ||
| 272 | } | 253 | } |
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 9242902d3a43..3482b99e8c86 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c | |||
| @@ -26,7 +26,6 @@ | |||
| 26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| 27 | 27 | ||
| 28 | #include <mach/gpio.h> | 28 | #include <mach/gpio.h> |
| 29 | #include <plat/mux.h> | ||
| 30 | #include <plat/usb.h> | 29 | #include <plat/usb.h> |
| 31 | #include <plat/board.h> | 30 | #include <plat/board.h> |
| 32 | #include <plat/common.h> | 31 | #include <plat/common.h> |
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 16703fdb3515..e09bd686389f 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c | |||
| @@ -33,7 +33,6 @@ | |||
| 33 | 33 | ||
| 34 | #include <plat/control.h> | 34 | #include <plat/control.h> |
| 35 | #include <mach/gpio.h> | 35 | #include <mach/gpio.h> |
| 36 | #include <plat/mux.h> | ||
| 37 | #include <plat/usb.h> | 36 | #include <plat/usb.h> |
| 38 | #include <plat/board.h> | 37 | #include <plat/board.h> |
| 39 | #include <plat/common.h> | 38 | #include <plat/common.h> |
| @@ -42,6 +41,8 @@ | |||
| 42 | #include <plat/dma.h> | 41 | #include <plat/dma.h> |
| 43 | #include <plat/gpmc.h> | 42 | #include <plat/gpmc.h> |
| 44 | 43 | ||
| 44 | #include "mux.h" | ||
| 45 | |||
| 45 | #define H4_FLASH_CS 0 | 46 | #define H4_FLASH_CS 0 |
| 46 | #define H4_SMC91X_CS 1 | 47 | #define H4_SMC91X_CS 1 |
| 47 | 48 | ||
| @@ -246,7 +247,7 @@ static inline void __init h4_init_debug(void) | |||
| 246 | 247 | ||
| 247 | udelay(100); | 248 | udelay(100); |
| 248 | 249 | ||
| 249 | omap_cfg_reg(M15_24XX_GPIO92); | 250 | omap_mux_init_gpio(92, 0); |
| 250 | if (debug_card_init(cs_mem_base, H4_ETHR_GPIO_IRQ) < 0) | 251 | if (debug_card_init(cs_mem_base, H4_ETHR_GPIO_IRQ) < 0) |
| 251 | gpmc_cs_free(eth_cs); | 252 | gpmc_cs_free(eth_cs); |
| 252 | 253 | ||
| @@ -272,27 +273,6 @@ static struct omap_lcd_config h4_lcd_config __initdata = { | |||
| 272 | }; | 273 | }; |
| 273 | 274 | ||
| 274 | static struct omap_usb_config h4_usb_config __initdata = { | 275 | static struct omap_usb_config h4_usb_config __initdata = { |
| 275 | #ifdef CONFIG_MACH_OMAP2_H4_USB1 | ||
| 276 | /* NOTE: usb1 could also be used with 3 wire signaling */ | ||
| 277 | .pins[1] = 4, | ||
| 278 | #endif | ||
| 279 | |||
| 280 | #ifdef CONFIG_MACH_OMAP_H4_OTG | ||
| 281 | /* S1.10 ON -- USB OTG port | ||
| 282 | * usb0 switched to Mini-AB port and isp1301 transceiver; | ||
| 283 | * S2.POS3 = OFF, S2.POS4 = ON ... to allow battery charging | ||
| 284 | */ | ||
| 285 | .otg = 1, | ||
| 286 | .pins[0] = 4, | ||
| 287 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 288 | /* use OTG cable, or standard A-to-MiniB */ | ||
| 289 | .hmc_mode = 0x14, /* 0:dev/otg 1:host 2:disable */ | ||
| 290 | #elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 291 | /* use OTG cable, or NONSTANDARD (B-to-MiniB) */ | ||
| 292 | .hmc_mode = 0x11, /* 0:host 1:host 2:disable */ | ||
| 293 | #endif /* XX */ | ||
| 294 | |||
| 295 | #else | ||
| 296 | /* S1.10 OFF -- usb "download port" | 276 | /* S1.10 OFF -- usb "download port" |
| 297 | * usb0 switched to Mini-B port and isp1105 transceiver; | 277 | * usb0 switched to Mini-B port and isp1105 transceiver; |
| 298 | * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging | 278 | * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging |
| @@ -301,7 +281,6 @@ static struct omap_usb_config h4_usb_config __initdata = { | |||
| 301 | .pins[0] = 3, | 281 | .pins[0] = 3, |
| 302 | /* .hmc_mode = 0x14,*/ /* 0:dev 1:host 2:disable */ | 282 | /* .hmc_mode = 0x14,*/ /* 0:dev 1:host 2:disable */ |
| 303 | .hmc_mode = 0x00, /* 0:dev|otg 1:disable 2:disable */ | 283 | .hmc_mode = 0x00, /* 0:dev|otg 1:disable 2:disable */ |
| 304 | #endif | ||
| 305 | }; | 284 | }; |
| 306 | 285 | ||
| 307 | static struct omap_board_config_kernel h4_config[] = { | 286 | static struct omap_board_config_kernel h4_config[] = { |
| @@ -338,31 +317,54 @@ static struct i2c_board_info __initdata h4_i2c_board_info[] = { | |||
| 338 | }, | 317 | }, |
| 339 | }; | 318 | }; |
| 340 | 319 | ||
| 320 | #ifdef CONFIG_OMAP_MUX | ||
| 321 | static struct omap_board_mux board_mux[] __initdata = { | ||
| 322 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 323 | }; | ||
| 324 | #else | ||
| 325 | #define board_mux NULL | ||
| 326 | #endif | ||
| 327 | |||
| 341 | static void __init omap_h4_init(void) | 328 | static void __init omap_h4_init(void) |
| 342 | { | 329 | { |
| 330 | omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF); | ||
| 331 | |||
| 343 | /* | 332 | /* |
| 344 | * Make sure the serial ports are muxed on at this point. | 333 | * Make sure the serial ports are muxed on at this point. |
| 345 | * You have to mux them off in device drivers later on | 334 | * You have to mux them off in device drivers later on |
| 346 | * if not needed. | 335 | * if not needed. |
| 347 | */ | 336 | */ |
| 348 | #if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE) | ||
| 349 | omap_cfg_reg(K15_24XX_UART3_TX); | ||
| 350 | omap_cfg_reg(K14_24XX_UART3_RX); | ||
| 351 | #endif | ||
| 352 | 337 | ||
| 353 | #if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE) | 338 | #if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE) |
| 339 | omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP); | ||
| 340 | omap_mux_init_gpio(89, OMAP_PULL_ENA | OMAP_PULL_UP); | ||
| 341 | omap_mux_init_gpio(124, OMAP_PULL_ENA | OMAP_PULL_UP); | ||
| 342 | omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP); | ||
| 354 | if (omap_has_menelaus()) { | 343 | if (omap_has_menelaus()) { |
| 344 | omap_mux_init_signal("sdrc_a14.gpio0", | ||
| 345 | OMAP_PULL_ENA | OMAP_PULL_UP); | ||
| 346 | omap_mux_init_signal("vlynq_rx0.gpio_15", 0); | ||
| 347 | omap_mux_init_signal("gpio_98", 0); | ||
| 355 | row_gpios[5] = 0; | 348 | row_gpios[5] = 0; |
| 356 | col_gpios[2] = 15; | 349 | col_gpios[2] = 15; |
| 357 | col_gpios[6] = 18; | 350 | col_gpios[6] = 18; |
| 351 | } else { | ||
| 352 | omap_mux_init_signal("gpio_96", OMAP_PULL_ENA | OMAP_PULL_UP); | ||
| 353 | omap_mux_init_signal("gpio_100", 0); | ||
| 354 | omap_mux_init_signal("gpio_98", 0); | ||
| 358 | } | 355 | } |
| 356 | omap_mux_init_signal("gpio_90", 0); | ||
| 357 | omap_mux_init_signal("gpio_91", 0); | ||
| 358 | omap_mux_init_signal("gpio_36", 0); | ||
| 359 | omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0); | ||
| 360 | omap_mux_init_signal("gpio_97", 0); | ||
| 359 | #endif | 361 | #endif |
| 360 | 362 | ||
| 361 | i2c_register_board_info(1, h4_i2c_board_info, | 363 | i2c_register_board_info(1, h4_i2c_board_info, |
| 362 | ARRAY_SIZE(h4_i2c_board_info)); | 364 | ARRAY_SIZE(h4_i2c_board_info)); |
| 363 | 365 | ||
| 364 | platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); | 366 | platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); |
| 365 | omap_usb_init(&h4_usb_config); | 367 | omap2_usbfs_init(&h4_usb_config); |
| 366 | omap_serial_init(); | 368 | omap_serial_init(); |
| 367 | } | 369 | } |
| 368 | 370 | ||
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 759e39d1a702..175f04339761 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c | |||
| @@ -532,17 +532,11 @@ static void __init igep2_init(void) | |||
| 532 | pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NRESET\n"); | 532 | pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NRESET\n"); |
| 533 | } | 533 | } |
| 534 | 534 | ||
| 535 | static void __init igep2_map_io(void) | ||
| 536 | { | ||
| 537 | omap2_set_globals_343x(); | ||
| 538 | omap34xx_map_common_io(); | ||
| 539 | } | ||
| 540 | |||
| 541 | MACHINE_START(IGEP0020, "IGEP v2 board") | 535 | MACHINE_START(IGEP0020, "IGEP v2 board") |
| 542 | .phys_io = 0x48000000, | 536 | .phys_io = 0x48000000, |
| 543 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, | 537 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
| 544 | .boot_params = 0x80000100, | 538 | .boot_params = 0x80000100, |
| 545 | .map_io = igep2_map_io, | 539 | .map_io = omap3_map_io, |
| 546 | .reserve = omap_reserve, | 540 | .reserve = omap_reserve, |
| 547 | .init_irq = igep2_init_irq, | 541 | .init_irq = igep2_init_irq, |
| 548 | .init_machine = igep2_init, | 542 | .init_machine = igep2_init, |
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 9cd2669113e4..00d9b13b01c5 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c | |||
| @@ -38,6 +38,7 @@ | |||
| 38 | #include <plat/board.h> | 38 | #include <plat/board.h> |
| 39 | #include <plat/common.h> | 39 | #include <plat/common.h> |
| 40 | #include <plat/gpmc.h> | 40 | #include <plat/gpmc.h> |
| 41 | #include <mach/board-zoom.h> | ||
| 41 | 42 | ||
| 42 | #include <asm/delay.h> | 43 | #include <asm/delay.h> |
| 43 | #include <plat/control.h> | 44 | #include <plat/control.h> |
| @@ -388,6 +389,38 @@ static struct omap_musb_board_data musb_board_data = { | |||
| 388 | .power = 100, | 389 | .power = 100, |
| 389 | }; | 390 | }; |
| 390 | 391 | ||
| 392 | static struct mtd_partition ldp_nand_partitions[] = { | ||
| 393 | /* All the partition sizes are listed in terms of NAND block size */ | ||
| 394 | { | ||
| 395 | .name = "X-Loader-NAND", | ||
| 396 | .offset = 0, | ||
| 397 | .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ | ||
| 398 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 399 | }, | ||
| 400 | { | ||
| 401 | .name = "U-Boot-NAND", | ||
| 402 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | ||
| 403 | .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ | ||
| 404 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 405 | }, | ||
| 406 | { | ||
| 407 | .name = "Boot Env-NAND", | ||
| 408 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ | ||
| 409 | .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ | ||
| 410 | }, | ||
| 411 | { | ||
| 412 | .name = "Kernel-NAND", | ||
| 413 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ | ||
| 414 | .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ | ||
| 415 | }, | ||
| 416 | { | ||
| 417 | .name = "File System - NAND", | ||
| 418 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ | ||
| 419 | .size = MTDPART_SIZ_FULL, /* 96MB, 0x6000000 */ | ||
| 420 | }, | ||
| 421 | |||
| 422 | }; | ||
| 423 | |||
| 391 | static void __init omap_ldp_init(void) | 424 | static void __init omap_ldp_init(void) |
| 392 | { | 425 | { |
| 393 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 426 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| @@ -400,23 +433,19 @@ static void __init omap_ldp_init(void) | |||
| 400 | ads7846_dev_init(); | 433 | ads7846_dev_init(); |
| 401 | omap_serial_init(); | 434 | omap_serial_init(); |
| 402 | usb_musb_init(&musb_board_data); | 435 | usb_musb_init(&musb_board_data); |
| 436 | board_nand_init(ldp_nand_partitions, | ||
| 437 | ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS); | ||
| 403 | 438 | ||
| 404 | omap2_hsmmc_init(mmc); | 439 | omap2_hsmmc_init(mmc); |
| 405 | /* link regulators to MMC adapters */ | 440 | /* link regulators to MMC adapters */ |
| 406 | ldp_vmmc1_supply.dev = mmc[0].dev; | 441 | ldp_vmmc1_supply.dev = mmc[0].dev; |
| 407 | } | 442 | } |
| 408 | 443 | ||
| 409 | static void __init omap_ldp_map_io(void) | ||
| 410 | { | ||
| 411 | omap2_set_globals_343x(); | ||
| 412 | omap34xx_map_common_io(); | ||
| 413 | } | ||
| 414 | |||
| 415 | MACHINE_START(OMAP_LDP, "OMAP LDP board") | 444 | MACHINE_START(OMAP_LDP, "OMAP LDP board") |
| 416 | .phys_io = 0x48000000, | 445 | .phys_io = 0x48000000, |
| 417 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, | 446 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
| 418 | .boot_params = 0x80000100, | 447 | .boot_params = 0x80000100, |
| 419 | .map_io = omap_ldp_map_io, | 448 | .map_io = omap3_map_io, |
| 420 | .reserve = omap_reserve, | 449 | .reserve = omap_reserve, |
| 421 | .init_irq = omap_ldp_init_irq, | 450 | .init_irq = omap_ldp_init_irq, |
| 422 | .init_machine = omap_ldp_init, | 451 | .init_machine = omap_ldp_init, |
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 2565ff08a221..a3e2b49aa39f 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c | |||
| @@ -33,6 +33,8 @@ | |||
| 33 | #include <plat/mmc.h> | 33 | #include <plat/mmc.h> |
| 34 | #include <plat/serial.h> | 34 | #include <plat/serial.h> |
| 35 | 35 | ||
| 36 | #include "mux.h" | ||
| 37 | |||
| 36 | static int slot1_cover_open; | 38 | static int slot1_cover_open; |
| 37 | static int slot2_cover_open; | 39 | static int slot2_cover_open; |
| 38 | static struct device *mmc_device; | 40 | static struct device *mmc_device; |
| @@ -649,8 +651,17 @@ static void __init n8x0_init_irq(void) | |||
| 649 | omap_gpio_init(); | 651 | omap_gpio_init(); |
| 650 | } | 652 | } |
| 651 | 653 | ||
| 654 | #ifdef CONFIG_OMAP_MUX | ||
| 655 | static struct omap_board_mux board_mux[] __initdata = { | ||
| 656 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 657 | }; | ||
| 658 | #else | ||
| 659 | #define board_mux NULL | ||
| 660 | #endif | ||
| 661 | |||
| 652 | static void __init n8x0_init_machine(void) | 662 | static void __init n8x0_init_machine(void) |
| 653 | { | 663 | { |
| 664 | omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); | ||
| 654 | /* FIXME: add n810 spi devices */ | 665 | /* FIXME: add n810 spi devices */ |
| 655 | spi_register_board_info(n800_spi_board_info, | 666 | spi_register_board_info(n800_spi_board_info, |
| 656 | ARRAY_SIZE(n800_spi_board_info)); | 667 | ARRAY_SIZE(n800_spi_board_info)); |
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 0ab0c26db4dd..87969c7df652 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c | |||
| @@ -48,9 +48,6 @@ | |||
| 48 | #include "mux.h" | 48 | #include "mux.h" |
| 49 | #include "hsmmc.h" | 49 | #include "hsmmc.h" |
| 50 | 50 | ||
| 51 | #define GPMC_CS0_BASE 0x60 | ||
| 52 | #define GPMC_CS_SIZE 0x30 | ||
| 53 | |||
| 54 | #define NAND_BLOCK_SIZE SZ_128K | 51 | #define NAND_BLOCK_SIZE SZ_128K |
| 55 | 52 | ||
| 56 | static struct mtd_partition omap3beagle_nand_partitions[] = { | 53 | static struct mtd_partition omap3beagle_nand_partitions[] = { |
| @@ -93,20 +90,6 @@ static struct omap_nand_platform_data omap3beagle_nand_data = { | |||
| 93 | .dev_ready = NULL, | 90 | .dev_ready = NULL, |
| 94 | }; | 91 | }; |
| 95 | 92 | ||
| 96 | static struct resource omap3beagle_nand_resource = { | ||
| 97 | .flags = IORESOURCE_MEM, | ||
| 98 | }; | ||
| 99 | |||
| 100 | static struct platform_device omap3beagle_nand_device = { | ||
| 101 | .name = "omap2-nand", | ||
| 102 | .id = -1, | ||
| 103 | .dev = { | ||
| 104 | .platform_data = &omap3beagle_nand_data, | ||
| 105 | }, | ||
| 106 | .num_resources = 1, | ||
| 107 | .resource = &omap3beagle_nand_resource, | ||
| 108 | }; | ||
| 109 | |||
| 110 | /* DSS */ | 93 | /* DSS */ |
| 111 | 94 | ||
| 112 | static int beagle_enable_dvi(struct omap_dss_device *dssdev) | 95 | static int beagle_enable_dvi(struct omap_dss_device *dssdev) |
| @@ -424,8 +407,6 @@ static void __init omap3beagle_flash_init(void) | |||
| 424 | u8 cs = 0; | 407 | u8 cs = 0; |
| 425 | u8 nandcs = GPMC_CS_NUM + 1; | 408 | u8 nandcs = GPMC_CS_NUM + 1; |
| 426 | 409 | ||
| 427 | u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; | ||
| 428 | |||
| 429 | /* find out the chip-select on which NAND exists */ | 410 | /* find out the chip-select on which NAND exists */ |
| 430 | while (cs < GPMC_CS_NUM) { | 411 | while (cs < GPMC_CS_NUM) { |
| 431 | u32 ret = 0; | 412 | u32 ret = 0; |
| @@ -447,12 +428,9 @@ static void __init omap3beagle_flash_init(void) | |||
| 447 | 428 | ||
| 448 | if (nandcs < GPMC_CS_NUM) { | 429 | if (nandcs < GPMC_CS_NUM) { |
| 449 | omap3beagle_nand_data.cs = nandcs; | 430 | omap3beagle_nand_data.cs = nandcs; |
| 450 | omap3beagle_nand_data.gpmc_cs_baseaddr = (void *) | ||
| 451 | (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); | ||
| 452 | omap3beagle_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add); | ||
| 453 | 431 | ||
| 454 | printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); | 432 | printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); |
| 455 | if (platform_device_register(&omap3beagle_nand_device) < 0) | 433 | if (gpmc_nand_init(&omap3beagle_nand_data) < 0) |
| 456 | printk(KERN_ERR "Unable to register NAND device\n"); | 434 | printk(KERN_ERR "Unable to register NAND device\n"); |
| 457 | } | 435 | } |
| 458 | } | 436 | } |
| @@ -507,18 +485,12 @@ static void __init omap3_beagle_init(void) | |||
| 507 | beagle_display_init(); | 485 | beagle_display_init(); |
| 508 | } | 486 | } |
| 509 | 487 | ||
| 510 | static void __init omap3_beagle_map_io(void) | ||
| 511 | { | ||
| 512 | omap2_set_globals_343x(); | ||
| 513 | omap34xx_map_common_io(); | ||
| 514 | } | ||
| 515 | |||
| 516 | MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") | 488 | MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") |
| 517 | /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ | 489 | /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ |
| 518 | .phys_io = 0x48000000, | 490 | .phys_io = 0x48000000, |
| 519 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, | 491 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
| 520 | .boot_params = 0x80000100, | 492 | .boot_params = 0x80000100, |
| 521 | .map_io = omap3_beagle_map_io, | 493 | .map_io = omap3_map_io, |
| 522 | .reserve = omap_reserve, | 494 | .reserve = omap_reserve, |
| 523 | .init_irq = omap3_beagle_init_irq, | 495 | .init_irq = omap3_beagle_init_irq, |
| 524 | .init_machine = omap3_beagle_init, | 496 | .init_machine = omap3_beagle_init, |
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index a3d2e285e116..6494dbdfc391 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c | |||
| @@ -715,18 +715,12 @@ static void __init omap3_evm_init(void) | |||
| 715 | omap3_evm_display_init(); | 715 | omap3_evm_display_init(); |
| 716 | } | 716 | } |
| 717 | 717 | ||
| 718 | static void __init omap3_evm_map_io(void) | ||
| 719 | { | ||
| 720 | omap2_set_globals_343x(); | ||
| 721 | omap34xx_map_common_io(); | ||
| 722 | } | ||
| 723 | |||
| 724 | MACHINE_START(OMAP3EVM, "OMAP3 EVM") | 718 | MACHINE_START(OMAP3EVM, "OMAP3 EVM") |
| 725 | /* Maintainer: Syed Mohammed Khasim - Texas Instruments */ | 719 | /* Maintainer: Syed Mohammed Khasim - Texas Instruments */ |
| 726 | .phys_io = 0x48000000, | 720 | .phys_io = 0x48000000, |
| 727 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, | 721 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
| 728 | .boot_params = 0x80000100, | 722 | .boot_params = 0x80000100, |
| 729 | .map_io = omap3_evm_map_io, | 723 | .map_io = omap3_map_io, |
| 730 | .reserve = omap_reserve, | 724 | .reserve = omap_reserve, |
| 731 | .init_irq = omap3_evm_init_irq, | 725 | .init_irq = omap3_evm_init_irq, |
| 732 | .init_machine = omap3_evm_init, | 726 | .init_machine = omap3_evm_init, |
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index c0f4f12eba54..55836fa35060 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c | |||
| @@ -25,6 +25,9 @@ | |||
| 25 | #include <linux/spi/ads7846.h> | 25 | #include <linux/spi/ads7846.h> |
| 26 | #include <linux/regulator/machine.h> | 26 | #include <linux/regulator/machine.h> |
| 27 | #include <linux/i2c/twl.h> | 27 | #include <linux/i2c/twl.h> |
| 28 | #include <linux/spi/wl12xx.h> | ||
| 29 | #include <linux/mtd/partitions.h> | ||
| 30 | #include <linux/mtd/nand.h> | ||
| 28 | #include <linux/leds.h> | 31 | #include <linux/leds.h> |
| 29 | #include <linux/input.h> | 32 | #include <linux/input.h> |
| 30 | #include <linux/input/matrix_keypad.h> | 33 | #include <linux/input/matrix_keypad.h> |
| @@ -41,15 +44,49 @@ | |||
| 41 | #include <plat/mcspi.h> | 44 | #include <plat/mcspi.h> |
| 42 | #include <plat/usb.h> | 45 | #include <plat/usb.h> |
| 43 | #include <plat/display.h> | 46 | #include <plat/display.h> |
| 47 | #include <plat/nand.h> | ||
| 44 | 48 | ||
| 45 | #include "mux.h" | 49 | #include "mux.h" |
| 46 | #include "sdram-micron-mt46h32m32lf-6.h" | 50 | #include "sdram-micron-mt46h32m32lf-6.h" |
| 47 | #include "hsmmc.h" | 51 | #include "hsmmc.h" |
| 48 | 52 | ||
| 53 | #define PANDORA_WIFI_IRQ_GPIO 21 | ||
| 54 | #define PANDORA_WIFI_NRESET_GPIO 23 | ||
| 49 | #define OMAP3_PANDORA_TS_GPIO 94 | 55 | #define OMAP3_PANDORA_TS_GPIO 94 |
| 50 | 56 | ||
| 51 | /* hardware debounce: (value + 1) * 31us */ | 57 | #define NAND_BLOCK_SIZE SZ_128K |
| 52 | #define GPIO_DEBOUNCE_TIME 127 | 58 | |
| 59 | static struct mtd_partition omap3pandora_nand_partitions[] = { | ||
| 60 | { | ||
| 61 | .name = "xloader", | ||
| 62 | .offset = 0, | ||
| 63 | .size = 4 * NAND_BLOCK_SIZE, | ||
| 64 | .mask_flags = MTD_WRITEABLE | ||
| 65 | }, { | ||
| 66 | .name = "uboot", | ||
| 67 | .offset = MTDPART_OFS_APPEND, | ||
| 68 | .size = 15 * NAND_BLOCK_SIZE, | ||
| 69 | }, { | ||
| 70 | .name = "uboot-env", | ||
| 71 | .offset = MTDPART_OFS_APPEND, | ||
| 72 | .size = 1 * NAND_BLOCK_SIZE, | ||
| 73 | }, { | ||
| 74 | .name = "boot", | ||
| 75 | .offset = MTDPART_OFS_APPEND, | ||
| 76 | .size = 80 * NAND_BLOCK_SIZE, | ||
| 77 | }, { | ||
| 78 | .name = "rootfs", | ||
| 79 | .offset = MTDPART_OFS_APPEND, | ||
| 80 | .size = MTDPART_SIZ_FULL, | ||
| 81 | }, | ||
| 82 | }; | ||
| 83 | |||
| 84 | static struct omap_nand_platform_data pandora_nand_data = { | ||
| 85 | .cs = 0, | ||
| 86 | .devsize = 1, /* '0' for 8-bit, '1' for 16-bit device */ | ||
| 87 | .parts = omap3pandora_nand_partitions, | ||
| 88 | .nr_parts = ARRAY_SIZE(omap3pandora_nand_partitions), | ||
| 89 | }; | ||
| 53 | 90 | ||
| 54 | static struct gpio_led pandora_gpio_leds[] = { | 91 | static struct gpio_led pandora_gpio_leds[] = { |
| 55 | { | 92 | { |
| @@ -88,6 +125,7 @@ static struct platform_device pandora_leds_gpio = { | |||
| 88 | .type = ev_type, \ | 125 | .type = ev_type, \ |
| 89 | .code = ev_code, \ | 126 | .code = ev_code, \ |
| 90 | .active_low = act_low, \ | 127 | .active_low = act_low, \ |
| 128 | .debounce_interval = 4, \ | ||
| 91 | .desc = "btn " descr, \ | 129 | .desc = "btn " descr, \ |
| 92 | } | 130 | } |
| 93 | 131 | ||
| @@ -99,14 +137,14 @@ static struct gpio_keys_button pandora_gpio_keys[] = { | |||
| 99 | GPIO_BUTTON_LOW(103, KEY_DOWN, "down"), | 137 | GPIO_BUTTON_LOW(103, KEY_DOWN, "down"), |
| 100 | GPIO_BUTTON_LOW(96, KEY_LEFT, "left"), | 138 | GPIO_BUTTON_LOW(96, KEY_LEFT, "left"), |
| 101 | GPIO_BUTTON_LOW(98, KEY_RIGHT, "right"), | 139 | GPIO_BUTTON_LOW(98, KEY_RIGHT, "right"), |
| 102 | GPIO_BUTTON_LOW(109, KEY_KP1, "game 1"), | 140 | GPIO_BUTTON_LOW(109, KEY_PAGEUP, "game 1"), |
| 103 | GPIO_BUTTON_LOW(111, KEY_KP2, "game 2"), | 141 | GPIO_BUTTON_LOW(111, KEY_END, "game 2"), |
| 104 | GPIO_BUTTON_LOW(106, KEY_KP3, "game 3"), | 142 | GPIO_BUTTON_LOW(106, KEY_PAGEDOWN, "game 3"), |
| 105 | GPIO_BUTTON_LOW(101, KEY_KP4, "game 4"), | 143 | GPIO_BUTTON_LOW(101, KEY_HOME, "game 4"), |
| 106 | GPIO_BUTTON_LOW(102, BTN_TL, "l"), | 144 | GPIO_BUTTON_LOW(102, KEY_RIGHTSHIFT, "l"), |
| 107 | GPIO_BUTTON_LOW(97, BTN_TL2, "l2"), | 145 | GPIO_BUTTON_LOW(97, KEY_KPPLUS, "l2"), |
| 108 | GPIO_BUTTON_LOW(105, BTN_TR, "r"), | 146 | GPIO_BUTTON_LOW(105, KEY_RIGHTCTRL, "r"), |
| 109 | GPIO_BUTTON_LOW(107, BTN_TR2, "r2"), | 147 | GPIO_BUTTON_LOW(107, KEY_KPMINUS, "r2"), |
| 110 | GPIO_BUTTON_LOW(104, KEY_LEFTCTRL, "ctrl"), | 148 | GPIO_BUTTON_LOW(104, KEY_LEFTCTRL, "ctrl"), |
| 111 | GPIO_BUTTON_LOW(99, KEY_MENU, "menu"), | 149 | GPIO_BUTTON_LOW(99, KEY_MENU, "menu"), |
| 112 | GPIO_BUTTON_LOW(176, KEY_COFFEE, "hold"), | 150 | GPIO_BUTTON_LOW(176, KEY_COFFEE, "hold"), |
| @@ -127,14 +165,7 @@ static struct platform_device pandora_keys_gpio = { | |||
| 127 | }, | 165 | }, |
| 128 | }; | 166 | }; |
| 129 | 167 | ||
| 130 | static void __init pandora_keys_gpio_init(void) | 168 | static const uint32_t board_keymap[] = { |
| 131 | { | ||
| 132 | /* set debounce time for GPIO banks 4 and 6 */ | ||
| 133 | gpio_set_debounce(32 * 3, GPIO_DEBOUNCE_TIME); | ||
| 134 | gpio_set_debounce(32 * 5, GPIO_DEBOUNCE_TIME); | ||
| 135 | } | ||
| 136 | |||
| 137 | static int board_keymap[] = { | ||
| 138 | /* row, col, code */ | 169 | /* row, col, code */ |
| 139 | KEY(0, 0, KEY_9), | 170 | KEY(0, 0, KEY_9), |
| 140 | KEY(0, 1, KEY_8), | 171 | KEY(0, 1, KEY_8), |
| @@ -255,12 +286,33 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = { | |||
| 255 | static int omap3pandora_twl_gpio_setup(struct device *dev, | 286 | static int omap3pandora_twl_gpio_setup(struct device *dev, |
| 256 | unsigned gpio, unsigned ngpio) | 287 | unsigned gpio, unsigned ngpio) |
| 257 | { | 288 | { |
| 289 | int ret, gpio_32khz; | ||
| 290 | |||
| 258 | /* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */ | 291 | /* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */ |
| 259 | omap3pandora_mmc[0].gpio_cd = gpio + 0; | 292 | omap3pandora_mmc[0].gpio_cd = gpio + 0; |
| 260 | omap3pandora_mmc[1].gpio_cd = gpio + 1; | 293 | omap3pandora_mmc[1].gpio_cd = gpio + 1; |
| 261 | omap2_hsmmc_init(omap3pandora_mmc); | 294 | omap2_hsmmc_init(omap3pandora_mmc); |
| 262 | 295 | ||
| 296 | /* gpio + 13 drives 32kHz buffer for wifi module */ | ||
| 297 | gpio_32khz = gpio + 13; | ||
| 298 | ret = gpio_request(gpio_32khz, "wifi 32kHz"); | ||
| 299 | if (ret < 0) { | ||
| 300 | pr_err("Cannot get GPIO line %d, ret=%d\n", gpio_32khz, ret); | ||
| 301 | goto fail; | ||
| 302 | } | ||
| 303 | |||
| 304 | ret = gpio_direction_output(gpio_32khz, 1); | ||
| 305 | if (ret < 0) { | ||
| 306 | pr_err("Cannot set GPIO line %d, ret=%d\n", gpio_32khz, ret); | ||
| 307 | goto fail_direction; | ||
| 308 | } | ||
| 309 | |||
| 263 | return 0; | 310 | return 0; |
| 311 | |||
| 312 | fail_direction: | ||
| 313 | gpio_free(gpio_32khz); | ||
| 314 | fail: | ||
| 315 | return -ENODEV; | ||
| 264 | } | 316 | } |
| 265 | 317 | ||
| 266 | static struct twl4030_gpio_platform_data omap3pandora_gpio_data = { | 318 | static struct twl4030_gpio_platform_data omap3pandora_gpio_data = { |
| @@ -539,10 +591,67 @@ static void __init omap3pandora_init_irq(void) | |||
| 539 | omap_gpio_init(); | 591 | omap_gpio_init(); |
| 540 | } | 592 | } |
| 541 | 593 | ||
| 594 | static void pandora_wl1251_set_power(bool enable) | ||
| 595 | { | ||
| 596 | /* | ||
| 597 | * Keep power always on until wl1251_sdio driver learns to re-init | ||
| 598 | * the chip after powering it down and back up. | ||
| 599 | */ | ||
| 600 | } | ||
| 601 | |||
| 602 | static struct wl12xx_platform_data pandora_wl1251_pdata = { | ||
| 603 | .set_power = pandora_wl1251_set_power, | ||
| 604 | .use_eeprom = true, | ||
| 605 | }; | ||
| 606 | |||
| 607 | static struct platform_device pandora_wl1251_data = { | ||
| 608 | .name = "wl1251_data", | ||
| 609 | .id = -1, | ||
| 610 | .dev = { | ||
| 611 | .platform_data = &pandora_wl1251_pdata, | ||
| 612 | }, | ||
| 613 | }; | ||
| 614 | |||
| 615 | static void pandora_wl1251_init(void) | ||
| 616 | { | ||
| 617 | int ret; | ||
| 618 | |||
| 619 | ret = gpio_request(PANDORA_WIFI_IRQ_GPIO, "wl1251 irq"); | ||
| 620 | if (ret < 0) | ||
| 621 | goto fail; | ||
| 622 | |||
| 623 | ret = gpio_direction_input(PANDORA_WIFI_IRQ_GPIO); | ||
| 624 | if (ret < 0) | ||
| 625 | goto fail_irq; | ||
| 626 | |||
| 627 | pandora_wl1251_pdata.irq = gpio_to_irq(PANDORA_WIFI_IRQ_GPIO); | ||
| 628 | if (pandora_wl1251_pdata.irq < 0) | ||
| 629 | goto fail_irq; | ||
| 630 | |||
| 631 | ret = gpio_request(PANDORA_WIFI_NRESET_GPIO, "wl1251 nreset"); | ||
| 632 | if (ret < 0) | ||
| 633 | goto fail_irq; | ||
| 634 | |||
| 635 | /* start powered so that it probes with MMC subsystem */ | ||
| 636 | ret = gpio_direction_output(PANDORA_WIFI_NRESET_GPIO, 1); | ||
| 637 | if (ret < 0) | ||
| 638 | goto fail_nreset; | ||
| 639 | |||
| 640 | return; | ||
| 641 | |||
| 642 | fail_nreset: | ||
| 643 | gpio_free(PANDORA_WIFI_NRESET_GPIO); | ||
| 644 | fail_irq: | ||
| 645 | gpio_free(PANDORA_WIFI_IRQ_GPIO); | ||
| 646 | fail: | ||
| 647 | printk(KERN_ERR "wl1251 board initialisation failed\n"); | ||
| 648 | } | ||
| 649 | |||
| 542 | static struct platform_device *omap3pandora_devices[] __initdata = { | 650 | static struct platform_device *omap3pandora_devices[] __initdata = { |
| 543 | &pandora_leds_gpio, | 651 | &pandora_leds_gpio, |
| 544 | &pandora_keys_gpio, | 652 | &pandora_keys_gpio, |
| 545 | &pandora_dss_device, | 653 | &pandora_dss_device, |
| 654 | &pandora_wl1251_data, | ||
| 546 | }; | 655 | }; |
| 547 | 656 | ||
| 548 | static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | 657 | static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { |
| @@ -575,6 +684,7 @@ static void __init omap3pandora_init(void) | |||
| 575 | { | 684 | { |
| 576 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 685 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| 577 | omap3pandora_i2c_init(); | 686 | omap3pandora_i2c_init(); |
| 687 | pandora_wl1251_init(); | ||
| 578 | platform_add_devices(omap3pandora_devices, | 688 | platform_add_devices(omap3pandora_devices, |
| 579 | ARRAY_SIZE(omap3pandora_devices)); | 689 | ARRAY_SIZE(omap3pandora_devices)); |
| 580 | omap_serial_init(); | 690 | omap_serial_init(); |
| @@ -582,25 +692,19 @@ static void __init omap3pandora_init(void) | |||
| 582 | ARRAY_SIZE(omap3pandora_spi_board_info)); | 692 | ARRAY_SIZE(omap3pandora_spi_board_info)); |
| 583 | omap3pandora_ads7846_init(); | 693 | omap3pandora_ads7846_init(); |
| 584 | usb_ehci_init(&ehci_pdata); | 694 | usb_ehci_init(&ehci_pdata); |
| 585 | pandora_keys_gpio_init(); | ||
| 586 | usb_musb_init(&musb_board_data); | 695 | usb_musb_init(&musb_board_data); |
| 696 | gpmc_nand_init(&pandora_nand_data); | ||
| 587 | 697 | ||
| 588 | /* Ensure SDRC pins are mux'd for self-refresh */ | 698 | /* Ensure SDRC pins are mux'd for self-refresh */ |
| 589 | omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); | 699 | omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); |
| 590 | omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); | 700 | omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); |
| 591 | } | 701 | } |
| 592 | 702 | ||
| 593 | static void __init omap3pandora_map_io(void) | ||
| 594 | { | ||
| 595 | omap2_set_globals_343x(); | ||
| 596 | omap34xx_map_common_io(); | ||
| 597 | } | ||
| 598 | |||
| 599 | MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") | 703 | MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") |
| 600 | .phys_io = 0x48000000, | 704 | .phys_io = 0x48000000, |
| 601 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, | 705 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
| 602 | .boot_params = 0x80000100, | 706 | .boot_params = 0x80000100, |
| 603 | .map_io = omap3pandora_map_io, | 707 | .map_io = omap3_map_io, |
| 604 | .reserve = omap_reserve, | 708 | .reserve = omap_reserve, |
| 605 | .init_irq = omap3pandora_init_irq, | 709 | .init_irq = omap3pandora_init_irq, |
| 606 | .init_machine = omap3pandora_init, | 710 | .init_machine = omap3pandora_init, |
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index a04cffd691c5..bcd01d278c65 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c | |||
| @@ -652,18 +652,12 @@ static void __init omap3_stalker_init(void) | |||
| 652 | omap_mux_init_signal("sdr_cke1", OMAP_PIN_OUTPUT); | 652 | omap_mux_init_signal("sdr_cke1", OMAP_PIN_OUTPUT); |
| 653 | } | 653 | } |
| 654 | 654 | ||
| 655 | static void __init omap3_stalker_map_io(void) | ||
| 656 | { | ||
| 657 | omap2_set_globals_343x(); | ||
| 658 | omap34xx_map_common_io(); | ||
| 659 | } | ||
| 660 | |||
| 661 | MACHINE_START(SBC3530, "OMAP3 STALKER") | 655 | MACHINE_START(SBC3530, "OMAP3 STALKER") |
| 662 | /* Maintainer: Jason Lam -lzg@ema-tech.com */ | 656 | /* Maintainer: Jason Lam -lzg@ema-tech.com */ |
| 663 | .phys_io = 0x48000000, | 657 | .phys_io = 0x48000000, |
| 664 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, | 658 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
| 665 | .boot_params = 0x80000100, | 659 | .boot_params = 0x80000100, |
| 666 | .map_io = omap3_stalker_map_io, | 660 | .map_io = omap3_map_io, |
| 667 | .init_irq = omap3_stalker_init_irq, | 661 | .init_irq = omap3_stalker_init_irq, |
| 668 | .init_machine = omap3_stalker_init, | 662 | .init_machine = omap3_stalker_init, |
| 669 | .timer = &omap_timer, | 663 | .timer = &omap_timer, |
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index f05b867c5851..663c62d271e8 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c | |||
| @@ -54,9 +54,6 @@ | |||
| 54 | 54 | ||
| 55 | #include <asm/setup.h> | 55 | #include <asm/setup.h> |
| 56 | 56 | ||
| 57 | #define GPMC_CS0_BASE 0x60 | ||
| 58 | #define GPMC_CS_SIZE 0x30 | ||
| 59 | |||
| 60 | #define NAND_BLOCK_SIZE SZ_128K | 57 | #define NAND_BLOCK_SIZE SZ_128K |
| 61 | 58 | ||
| 62 | #define OMAP3_AC_GPIO 136 | 59 | #define OMAP3_AC_GPIO 136 |
| @@ -106,20 +103,6 @@ static struct omap_nand_platform_data omap3touchbook_nand_data = { | |||
| 106 | .dev_ready = NULL, | 103 | .dev_ready = NULL, |
| 107 | }; | 104 | }; |
| 108 | 105 | ||
| 109 | static struct resource omap3touchbook_nand_resource = { | ||
| 110 | .flags = IORESOURCE_MEM, | ||
| 111 | }; | ||
| 112 | |||
| 113 | static struct platform_device omap3touchbook_nand_device = { | ||
| 114 | .name = "omap2-nand", | ||
| 115 | .id = -1, | ||
| 116 | .dev = { | ||
| 117 | .platform_data = &omap3touchbook_nand_data, | ||
| 118 | }, | ||
| 119 | .num_resources = 1, | ||
| 120 | .resource = &omap3touchbook_nand_resource, | ||
| 121 | }; | ||
| 122 | |||
| 123 | #include "sdram-micron-mt46h32m32lf-6.h" | 106 | #include "sdram-micron-mt46h32m32lf-6.h" |
| 124 | 107 | ||
| 125 | static struct omap2_hsmmc_info mmc[] = { | 108 | static struct omap2_hsmmc_info mmc[] = { |
| @@ -458,8 +441,6 @@ static void __init omap3touchbook_flash_init(void) | |||
| 458 | u8 cs = 0; | 441 | u8 cs = 0; |
| 459 | u8 nandcs = GPMC_CS_NUM + 1; | 442 | u8 nandcs = GPMC_CS_NUM + 1; |
| 460 | 443 | ||
| 461 | u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; | ||
| 462 | |||
| 463 | /* find out the chip-select on which NAND exists */ | 444 | /* find out the chip-select on which NAND exists */ |
| 464 | while (cs < GPMC_CS_NUM) { | 445 | while (cs < GPMC_CS_NUM) { |
| 465 | u32 ret = 0; | 446 | u32 ret = 0; |
| @@ -481,13 +462,9 @@ static void __init omap3touchbook_flash_init(void) | |||
| 481 | 462 | ||
| 482 | if (nandcs < GPMC_CS_NUM) { | 463 | if (nandcs < GPMC_CS_NUM) { |
| 483 | omap3touchbook_nand_data.cs = nandcs; | 464 | omap3touchbook_nand_data.cs = nandcs; |
| 484 | omap3touchbook_nand_data.gpmc_cs_baseaddr = (void *) | ||
| 485 | (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); | ||
| 486 | omap3touchbook_nand_data.gpmc_baseaddr = | ||
| 487 | (void *) (gpmc_base_add); | ||
| 488 | 465 | ||
| 489 | printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); | 466 | printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); |
| 490 | if (platform_device_register(&omap3touchbook_nand_device) < 0) | 467 | if (gpmc_nand_init(&omap3touchbook_nand_data) < 0) |
| 491 | printk(KERN_ERR "Unable to register NAND device\n"); | 468 | printk(KERN_ERR "Unable to register NAND device\n"); |
| 492 | } | 469 | } |
| 493 | } | 470 | } |
| @@ -559,18 +536,12 @@ static void __init omap3_touchbook_init(void) | |||
| 559 | omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); | 536 | omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); |
| 560 | } | 537 | } |
| 561 | 538 | ||
| 562 | static void __init omap3_touchbook_map_io(void) | ||
| 563 | { | ||
| 564 | omap2_set_globals_343x(); | ||
| 565 | omap34xx_map_common_io(); | ||
| 566 | } | ||
| 567 | |||
| 568 | MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") | 539 | MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") |
| 569 | /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */ | 540 | /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */ |
| 570 | .phys_io = 0x48000000, | 541 | .phys_io = 0x48000000, |
| 571 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | 542 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, |
| 572 | .boot_params = 0x80000100, | 543 | .boot_params = 0x80000100, |
| 573 | .map_io = omap3_touchbook_map_io, | 544 | .map_io = omap3_map_io, |
| 574 | .reserve = omap_reserve, | 545 | .reserve = omap_reserve, |
| 575 | .init_irq = omap3_touchbook_init_irq, | 546 | .init_irq = omap3_touchbook_init_irq, |
| 576 | .init_machine = omap3_touchbook_init, | 547 | .init_machine = omap3_touchbook_init, |
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c new file mode 100644 index 000000000000..c03d1d56db56 --- /dev/null +++ b/arch/arm/mach-omap2/board-omap4panda.c | |||
| @@ -0,0 +1,304 @@ | |||
| 1 | /* | ||
| 2 | * Board support file for OMAP4430 based PandaBoard. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments | ||
| 5 | * | ||
| 6 | * Author: David Anders <x0132446@ti.com> | ||
| 7 | * | ||
| 8 | * Based on mach-omap2/board-4430sdp.c | ||
| 9 | * | ||
| 10 | * Author: Santosh Shilimkar <santosh.shilimkar@ti.com> | ||
| 11 | * | ||
| 12 | * Based on mach-omap2/board-3430sdp.c | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | #include <linux/platform_device.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | #include <linux/gpio.h> | ||
| 24 | #include <linux/usb/otg.h> | ||
| 25 | #include <linux/i2c/twl.h> | ||
| 26 | #include <linux/regulator/machine.h> | ||
| 27 | |||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <mach/omap4-common.h> | ||
| 30 | #include <asm/mach-types.h> | ||
| 31 | #include <asm/mach/arch.h> | ||
| 32 | #include <asm/mach/map.h> | ||
| 33 | |||
| 34 | #include <plat/board.h> | ||
| 35 | #include <plat/common.h> | ||
| 36 | #include <plat/control.h> | ||
| 37 | #include <plat/timer-gp.h> | ||
| 38 | #include <plat/usb.h> | ||
| 39 | #include <plat/mmc.h> | ||
| 40 | #include "hsmmc.h" | ||
| 41 | |||
| 42 | |||
| 43 | static void __init omap4_panda_init_irq(void) | ||
| 44 | { | ||
| 45 | omap2_init_common_hw(NULL, NULL); | ||
| 46 | gic_init_irq(); | ||
| 47 | omap_gpio_init(); | ||
| 48 | } | ||
| 49 | |||
| 50 | static struct omap_musb_board_data musb_board_data = { | ||
| 51 | .interface_type = MUSB_INTERFACE_UTMI, | ||
| 52 | .mode = MUSB_PERIPHERAL, | ||
| 53 | .power = 100, | ||
| 54 | }; | ||
| 55 | |||
| 56 | static struct omap2_hsmmc_info mmc[] = { | ||
| 57 | { | ||
| 58 | .mmc = 1, | ||
| 59 | .wires = 8, | ||
| 60 | .gpio_wp = -EINVAL, | ||
| 61 | }, | ||
| 62 | {} /* Terminator */ | ||
| 63 | }; | ||
| 64 | |||
| 65 | static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = { | ||
| 66 | { | ||
| 67 | .supply = "vmmc", | ||
| 68 | .dev_name = "mmci-omap-hs.0", | ||
| 69 | }, | ||
| 70 | { | ||
| 71 | .supply = "vmmc", | ||
| 72 | .dev_name = "mmci-omap-hs.1", | ||
| 73 | }, | ||
| 74 | }; | ||
| 75 | |||
| 76 | static int omap4_twl6030_hsmmc_late_init(struct device *dev) | ||
| 77 | { | ||
| 78 | int ret = 0; | ||
| 79 | struct platform_device *pdev = container_of(dev, | ||
| 80 | struct platform_device, dev); | ||
| 81 | struct omap_mmc_platform_data *pdata = dev->platform_data; | ||
| 82 | |||
| 83 | /* Setting MMC1 Card detect Irq */ | ||
| 84 | if (pdev->id == 0) | ||
| 85 | pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE + | ||
| 86 | MMCDETECT_INTR_OFFSET; | ||
| 87 | return ret; | ||
| 88 | } | ||
| 89 | |||
| 90 | static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) | ||
| 91 | { | ||
| 92 | struct omap_mmc_platform_data *pdata = dev->platform_data; | ||
| 93 | |||
| 94 | pdata->init = omap4_twl6030_hsmmc_late_init; | ||
| 95 | } | ||
| 96 | |||
| 97 | static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) | ||
| 98 | { | ||
| 99 | struct omap2_hsmmc_info *c; | ||
| 100 | |||
| 101 | omap2_hsmmc_init(controllers); | ||
| 102 | for (c = controllers; c->mmc; c++) | ||
| 103 | omap4_twl6030_hsmmc_set_late_init(c->dev); | ||
| 104 | |||
| 105 | return 0; | ||
| 106 | } | ||
| 107 | |||
| 108 | static struct regulator_init_data omap4_panda_vaux1 = { | ||
| 109 | .constraints = { | ||
| 110 | .min_uV = 1000000, | ||
| 111 | .max_uV = 3000000, | ||
| 112 | .apply_uV = true, | ||
| 113 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 114 | | REGULATOR_MODE_STANDBY, | ||
| 115 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 116 | | REGULATOR_CHANGE_MODE | ||
| 117 | | REGULATOR_CHANGE_STATUS, | ||
| 118 | }, | ||
| 119 | }; | ||
| 120 | |||
| 121 | static struct regulator_init_data omap4_panda_vaux2 = { | ||
| 122 | .constraints = { | ||
| 123 | .min_uV = 1200000, | ||
| 124 | .max_uV = 2800000, | ||
| 125 | .apply_uV = true, | ||
| 126 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 127 | | REGULATOR_MODE_STANDBY, | ||
| 128 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 129 | | REGULATOR_CHANGE_MODE | ||
| 130 | | REGULATOR_CHANGE_STATUS, | ||
| 131 | }, | ||
| 132 | }; | ||
| 133 | |||
| 134 | static struct regulator_init_data omap4_panda_vaux3 = { | ||
| 135 | .constraints = { | ||
| 136 | .min_uV = 1000000, | ||
| 137 | .max_uV = 3000000, | ||
| 138 | .apply_uV = true, | ||
| 139 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 140 | | REGULATOR_MODE_STANDBY, | ||
| 141 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 142 | | REGULATOR_CHANGE_MODE | ||
| 143 | | REGULATOR_CHANGE_STATUS, | ||
| 144 | }, | ||
| 145 | }; | ||
| 146 | |||
| 147 | /* VMMC1 for MMC1 card */ | ||
| 148 | static struct regulator_init_data omap4_panda_vmmc = { | ||
| 149 | .constraints = { | ||
| 150 | .min_uV = 1200000, | ||
| 151 | .max_uV = 3000000, | ||
| 152 | .apply_uV = true, | ||
| 153 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 154 | | REGULATOR_MODE_STANDBY, | ||
| 155 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 156 | | REGULATOR_CHANGE_MODE | ||
| 157 | | REGULATOR_CHANGE_STATUS, | ||
| 158 | }, | ||
| 159 | .num_consumer_supplies = 2, | ||
| 160 | .consumer_supplies = omap4_panda_vmmc_supply, | ||
| 161 | }; | ||
| 162 | |||
| 163 | static struct regulator_init_data omap4_panda_vpp = { | ||
| 164 | .constraints = { | ||
| 165 | .min_uV = 1800000, | ||
| 166 | .max_uV = 2500000, | ||
| 167 | .apply_uV = true, | ||
| 168 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 169 | | REGULATOR_MODE_STANDBY, | ||
| 170 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 171 | | REGULATOR_CHANGE_MODE | ||
| 172 | | REGULATOR_CHANGE_STATUS, | ||
| 173 | }, | ||
| 174 | }; | ||
| 175 | |||
| 176 | static struct regulator_init_data omap4_panda_vusim = { | ||
| 177 | .constraints = { | ||
| 178 | .min_uV = 1200000, | ||
| 179 | .max_uV = 2900000, | ||
| 180 | .apply_uV = true, | ||
| 181 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 182 | | REGULATOR_MODE_STANDBY, | ||
| 183 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 184 | | REGULATOR_CHANGE_MODE | ||
| 185 | | REGULATOR_CHANGE_STATUS, | ||
| 186 | }, | ||
| 187 | }; | ||
| 188 | |||
| 189 | static struct regulator_init_data omap4_panda_vana = { | ||
| 190 | .constraints = { | ||
| 191 | .min_uV = 2100000, | ||
| 192 | .max_uV = 2100000, | ||
| 193 | .apply_uV = true, | ||
| 194 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 195 | | REGULATOR_MODE_STANDBY, | ||
| 196 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 197 | | REGULATOR_CHANGE_STATUS, | ||
| 198 | }, | ||
| 199 | }; | ||
| 200 | |||
| 201 | static struct regulator_init_data omap4_panda_vcxio = { | ||
| 202 | .constraints = { | ||
| 203 | .min_uV = 1800000, | ||
| 204 | .max_uV = 1800000, | ||
| 205 | .apply_uV = true, | ||
| 206 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 207 | | REGULATOR_MODE_STANDBY, | ||
| 208 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 209 | | REGULATOR_CHANGE_STATUS, | ||
| 210 | }, | ||
| 211 | }; | ||
| 212 | |||
| 213 | static struct regulator_init_data omap4_panda_vdac = { | ||
| 214 | .constraints = { | ||
| 215 | .min_uV = 1800000, | ||
| 216 | .max_uV = 1800000, | ||
| 217 | .apply_uV = true, | ||
| 218 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 219 | | REGULATOR_MODE_STANDBY, | ||
| 220 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 221 | | REGULATOR_CHANGE_STATUS, | ||
| 222 | }, | ||
| 223 | }; | ||
| 224 | |||
| 225 | static struct regulator_init_data omap4_panda_vusb = { | ||
| 226 | .constraints = { | ||
| 227 | .min_uV = 3300000, | ||
| 228 | .max_uV = 3300000, | ||
| 229 | .apply_uV = true, | ||
| 230 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 231 | | REGULATOR_MODE_STANDBY, | ||
| 232 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 233 | | REGULATOR_CHANGE_STATUS, | ||
| 234 | }, | ||
| 235 | }; | ||
| 236 | |||
| 237 | static struct twl4030_platform_data omap4_panda_twldata = { | ||
| 238 | .irq_base = TWL6030_IRQ_BASE, | ||
| 239 | .irq_end = TWL6030_IRQ_END, | ||
| 240 | |||
| 241 | /* Regulators */ | ||
| 242 | .vmmc = &omap4_panda_vmmc, | ||
| 243 | .vpp = &omap4_panda_vpp, | ||
| 244 | .vusim = &omap4_panda_vusim, | ||
| 245 | .vana = &omap4_panda_vana, | ||
| 246 | .vcxio = &omap4_panda_vcxio, | ||
| 247 | .vdac = &omap4_panda_vdac, | ||
| 248 | .vusb = &omap4_panda_vusb, | ||
| 249 | .vaux1 = &omap4_panda_vaux1, | ||
| 250 | .vaux2 = &omap4_panda_vaux2, | ||
| 251 | .vaux3 = &omap4_panda_vaux3, | ||
| 252 | }; | ||
| 253 | |||
| 254 | static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = { | ||
| 255 | { | ||
| 256 | I2C_BOARD_INFO("twl6030", 0x48), | ||
| 257 | .flags = I2C_CLIENT_WAKE, | ||
| 258 | .irq = OMAP44XX_IRQ_SYS_1N, | ||
| 259 | .platform_data = &omap4_panda_twldata, | ||
| 260 | }, | ||
| 261 | }; | ||
| 262 | static int __init omap4_panda_i2c_init(void) | ||
| 263 | { | ||
| 264 | /* | ||
| 265 | * Phoenix Audio IC needs I2C1 to | ||
| 266 | * start with 400 KHz or less | ||
| 267 | */ | ||
| 268 | omap_register_i2c_bus(1, 400, omap4_panda_i2c_boardinfo, | ||
| 269 | ARRAY_SIZE(omap4_panda_i2c_boardinfo)); | ||
| 270 | omap_register_i2c_bus(2, 400, NULL, 0); | ||
| 271 | omap_register_i2c_bus(3, 400, NULL, 0); | ||
| 272 | omap_register_i2c_bus(4, 400, NULL, 0); | ||
| 273 | return 0; | ||
| 274 | } | ||
| 275 | static void __init omap4_panda_init(void) | ||
| 276 | { | ||
| 277 | int status; | ||
| 278 | |||
| 279 | omap4_panda_i2c_init(); | ||
| 280 | omap_serial_init(); | ||
| 281 | omap4_twl6030_hsmmc_init(mmc); | ||
| 282 | /* OMAP4 Panda uses internal transceiver so register nop transceiver */ | ||
| 283 | usb_nop_xceiv_register(); | ||
| 284 | /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ | ||
| 285 | if (!cpu_is_omap44xx()) | ||
| 286 | usb_musb_init(&musb_board_data); | ||
| 287 | } | ||
| 288 | |||
| 289 | static void __init omap4_panda_map_io(void) | ||
| 290 | { | ||
| 291 | omap2_set_globals_443x(); | ||
| 292 | omap44xx_map_common_io(); | ||
| 293 | } | ||
| 294 | |||
| 295 | MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") | ||
| 296 | /* Maintainer: David Anders - Texas Instruments Inc */ | ||
| 297 | .phys_io = 0x48000000, | ||
| 298 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, | ||
| 299 | .boot_params = 0x80000100, | ||
| 300 | .map_io = omap4_panda_map_io, | ||
| 301 | .init_irq = omap4_panda_init_irq, | ||
| 302 | .init_machine = omap4_panda_init, | ||
| 303 | .timer = &omap_timer, | ||
| 304 | MACHINE_END | ||
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 87acb2f198ec..4c4843618350 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c | |||
| @@ -58,8 +58,6 @@ | |||
| 58 | #define OVERO_GPIO_USBH_NRESET 183 | 58 | #define OVERO_GPIO_USBH_NRESET 183 |
| 59 | 59 | ||
| 60 | #define NAND_BLOCK_SIZE SZ_128K | 60 | #define NAND_BLOCK_SIZE SZ_128K |
| 61 | #define GPMC_CS0_BASE 0x60 | ||
| 62 | #define GPMC_CS_SIZE 0x30 | ||
| 63 | 61 | ||
| 64 | #define OVERO_SMSC911X_CS 5 | 62 | #define OVERO_SMSC911X_CS 5 |
| 65 | #define OVERO_SMSC911X_GPIO 176 | 63 | #define OVERO_SMSC911X_GPIO 176 |
| @@ -166,9 +164,26 @@ static struct platform_device overo_smsc911x_device = { | |||
| 166 | }, | 164 | }, |
| 167 | }; | 165 | }; |
| 168 | 166 | ||
| 167 | static struct platform_device overo_smsc911x2_device = { | ||
| 168 | .name = "smsc911x", | ||
| 169 | .id = 1, | ||
| 170 | .num_resources = ARRAY_SIZE(overo_smsc911x2_resources), | ||
| 171 | .resource = overo_smsc911x2_resources, | ||
| 172 | .dev = { | ||
| 173 | .platform_data = &overo_smsc911x_config, | ||
| 174 | }, | ||
| 175 | }; | ||
| 176 | |||
| 177 | static struct platform_device *smsc911x_devices[] = { | ||
| 178 | &overo_smsc911x_device, | ||
| 179 | &overo_smsc911x2_device, | ||
| 180 | }; | ||
| 181 | |||
| 169 | static inline void __init overo_init_smsc911x(void) | 182 | static inline void __init overo_init_smsc911x(void) |
| 170 | { | 183 | { |
| 171 | unsigned long cs_mem_base; | 184 | unsigned long cs_mem_base, cs_mem_base2; |
| 185 | |||
| 186 | /* set up first smsc911x chip */ | ||
| 172 | 187 | ||
| 173 | if (gpmc_cs_request(OVERO_SMSC911X_CS, SZ_16M, &cs_mem_base) < 0) { | 188 | if (gpmc_cs_request(OVERO_SMSC911X_CS, SZ_16M, &cs_mem_base) < 0) { |
| 174 | printk(KERN_ERR "Failed request for GPMC mem for smsc911x\n"); | 189 | printk(KERN_ERR "Failed request for GPMC mem for smsc911x\n"); |
| @@ -189,7 +204,28 @@ static inline void __init overo_init_smsc911x(void) | |||
| 189 | overo_smsc911x_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X_GPIO); | 204 | overo_smsc911x_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X_GPIO); |
| 190 | overo_smsc911x_resources[1].end = 0; | 205 | overo_smsc911x_resources[1].end = 0; |
| 191 | 206 | ||
| 192 | platform_device_register(&overo_smsc911x_device); | 207 | /* set up second smsc911x chip */ |
| 208 | |||
| 209 | if (gpmc_cs_request(OVERO_SMSC911X2_CS, SZ_16M, &cs_mem_base2) < 0) { | ||
| 210 | printk(KERN_ERR "Failed request for GPMC mem for smsc911x2\n"); | ||
| 211 | return; | ||
| 212 | } | ||
| 213 | |||
| 214 | overo_smsc911x2_resources[0].start = cs_mem_base2 + 0x0; | ||
| 215 | overo_smsc911x2_resources[0].end = cs_mem_base2 + 0xff; | ||
| 216 | |||
| 217 | if ((gpio_request(OVERO_SMSC911X2_GPIO, "SMSC911X2 IRQ") == 0) && | ||
| 218 | (gpio_direction_input(OVERO_SMSC911X2_GPIO) == 0)) { | ||
| 219 | gpio_export(OVERO_SMSC911X2_GPIO, 0); | ||
| 220 | } else { | ||
| 221 | printk(KERN_ERR "could not obtain gpio for SMSC911X2 IRQ\n"); | ||
| 222 | return; | ||
| 223 | } | ||
| 224 | |||
| 225 | overo_smsc911x2_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X2_GPIO); | ||
| 226 | overo_smsc911x2_resources[1].end = 0; | ||
| 227 | |||
| 228 | platform_add_devices(smsc911x_devices, ARRAY_SIZE(smsc911x_devices)); | ||
| 193 | } | 229 | } |
| 194 | 230 | ||
| 195 | #else | 231 | #else |
| @@ -231,28 +267,11 @@ static struct omap_nand_platform_data overo_nand_data = { | |||
| 231 | .dma_channel = -1, /* disable DMA in OMAP NAND driver */ | 267 | .dma_channel = -1, /* disable DMA in OMAP NAND driver */ |
| 232 | }; | 268 | }; |
| 233 | 269 | ||
| 234 | static struct resource overo_nand_resource = { | ||
| 235 | .flags = IORESOURCE_MEM, | ||
| 236 | }; | ||
| 237 | |||
| 238 | static struct platform_device overo_nand_device = { | ||
| 239 | .name = "omap2-nand", | ||
| 240 | .id = -1, | ||
| 241 | .dev = { | ||
| 242 | .platform_data = &overo_nand_data, | ||
| 243 | }, | ||
| 244 | .num_resources = 1, | ||
| 245 | .resource = &overo_nand_resource, | ||
| 246 | }; | ||
| 247 | |||
| 248 | |||
| 249 | static void __init overo_flash_init(void) | 270 | static void __init overo_flash_init(void) |
| 250 | { | 271 | { |
| 251 | u8 cs = 0; | 272 | u8 cs = 0; |
| 252 | u8 nandcs = GPMC_CS_NUM + 1; | 273 | u8 nandcs = GPMC_CS_NUM + 1; |
| 253 | 274 | ||
| 254 | u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; | ||
| 255 | |||
| 256 | /* find out the chip-select on which NAND exists */ | 275 | /* find out the chip-select on which NAND exists */ |
| 257 | while (cs < GPMC_CS_NUM) { | 276 | while (cs < GPMC_CS_NUM) { |
| 258 | u32 ret = 0; | 277 | u32 ret = 0; |
| @@ -274,12 +293,9 @@ static void __init overo_flash_init(void) | |||
| 274 | 293 | ||
| 275 | if (nandcs < GPMC_CS_NUM) { | 294 | if (nandcs < GPMC_CS_NUM) { |
| 276 | overo_nand_data.cs = nandcs; | 295 | overo_nand_data.cs = nandcs; |
| 277 | overo_nand_data.gpmc_cs_baseaddr = (void *) | ||
| 278 | (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); | ||
| 279 | overo_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add); | ||
| 280 | 296 | ||
| 281 | printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); | 297 | printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); |
| 282 | if (platform_device_register(&overo_nand_device) < 0) | 298 | if (gpmc_nand_init(&overo_nand_data) < 0) |
| 283 | printk(KERN_ERR "Unable to register NAND device\n"); | 299 | printk(KERN_ERR "Unable to register NAND device\n"); |
| 284 | } | 300 | } |
| 285 | } | 301 | } |
| @@ -484,17 +500,11 @@ static void __init overo_init(void) | |||
| 484 | "OVERO_GPIO_USBH_CPEN\n"); | 500 | "OVERO_GPIO_USBH_CPEN\n"); |
| 485 | } | 501 | } |
| 486 | 502 | ||
| 487 | static void __init overo_map_io(void) | ||
| 488 | { | ||
| 489 | omap2_set_globals_343x(); | ||
| 490 | omap34xx_map_common_io(); | ||
| 491 | } | ||
| 492 | |||
| 493 | MACHINE_START(OVERO, "Gumstix Overo") | 503 | MACHINE_START(OVERO, "Gumstix Overo") |
| 494 | .phys_io = 0x48000000, | 504 | .phys_io = 0x48000000, |
| 495 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, | 505 | .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, |
| 496 | .boot_params = 0x80000100, | 506 | .boot_params = 0x80000100, |
| 497 | .map_io = overo_map_io, | 507 | .map_io = omap3_map_io, |
| 498 | .reserve = omap_reserve, | 508 | .reserve = omap_reserve, |
| 499 | .init_irq = overo_init_irq, | 509 | .init_irq = overo_init_irq, |
| 500 | .init_machine = overo_init, | 510 | .init_machine = overo_init, |
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 03483920ed6e..9a5eb87425fc 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | #include <linux/mmc/host.h> | 25 | #include <linux/mmc/host.h> |
| 26 | 26 | ||
| 27 | #include <plat/mcspi.h> | 27 | #include <plat/mcspi.h> |
| 28 | #include <plat/mux.h> | ||
| 29 | #include <plat/board.h> | 28 | #include <plat/board.h> |
| 30 | #include <plat/common.h> | 29 | #include <plat/common.h> |
| 31 | #include <plat/dma.h> | 30 | #include <plat/dma.h> |
| @@ -33,6 +32,11 @@ | |||
| 33 | #include <plat/onenand.h> | 32 | #include <plat/onenand.h> |
| 34 | #include <plat/gpmc-smc91x.h> | 33 | #include <plat/gpmc-smc91x.h> |
| 35 | 34 | ||
| 35 | #include <sound/tlv320aic3x.h> | ||
| 36 | #include <sound/tpa6130a2-plat.h> | ||
| 37 | |||
| 38 | #include <../drivers/staging/iio/light/tsl2563.h> | ||
| 39 | |||
| 36 | #include "mux.h" | 40 | #include "mux.h" |
| 37 | #include "hsmmc.h" | 41 | #include "hsmmc.h" |
| 38 | 42 | ||
| @@ -51,6 +55,12 @@ enum { | |||
| 51 | 55 | ||
| 52 | static struct wl12xx_platform_data wl1251_pdata; | 56 | static struct wl12xx_platform_data wl1251_pdata; |
| 53 | 57 | ||
| 58 | #if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE) | ||
| 59 | static struct tsl2563_platform_data rx51_tsl2563_platform_data = { | ||
| 60 | .cover_comp_gain = 16, | ||
| 61 | }; | ||
| 62 | #endif | ||
| 63 | |||
| 54 | static struct omap2_mcspi_device_config wl1251_mcspi_config = { | 64 | static struct omap2_mcspi_device_config wl1251_mcspi_config = { |
| 55 | .turbo_mode = 0, | 65 | .turbo_mode = 0, |
| 56 | .single_channel = 1, | 66 | .single_channel = 1, |
| @@ -311,48 +321,29 @@ static struct omap2_hsmmc_info mmc[] __initdata = { | |||
| 311 | {} /* Terminator */ | 321 | {} /* Terminator */ |
| 312 | }; | 322 | }; |
| 313 | 323 | ||
| 314 | static struct regulator_consumer_supply rx51_vmmc1_supply = { | 324 | static struct regulator_consumer_supply rx51_vmmc1_supply = |
| 315 | .supply = "vmmc", | 325 | REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); |
| 316 | .dev_name = "mmci-omap-hs.0", | ||
| 317 | }; | ||
| 318 | 326 | ||
| 319 | static struct regulator_consumer_supply rx51_vaux3_supply = { | 327 | static struct regulator_consumer_supply rx51_vaux3_supply = |
| 320 | .supply = "vmmc", | 328 | REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); |
| 321 | .dev_name = "mmci-omap-hs.1", | ||
| 322 | }; | ||
| 323 | 329 | ||
| 324 | static struct regulator_consumer_supply rx51_vsim_supply = { | 330 | static struct regulator_consumer_supply rx51_vsim_supply = |
| 325 | .supply = "vmmc_aux", | 331 | REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); |
| 326 | .dev_name = "mmci-omap-hs.1", | ||
| 327 | }; | ||
| 328 | 332 | ||
| 329 | static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { | 333 | static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { |
| 330 | /* tlv320aic3x analog supplies */ | 334 | /* tlv320aic3x analog supplies */ |
| 331 | { | 335 | REGULATOR_SUPPLY("AVDD", "2-0018"), |
| 332 | .supply = "AVDD", | 336 | REGULATOR_SUPPLY("DRVDD", "2-0018"), |
| 333 | .dev_name = "2-0018", | 337 | /* tpa6130a2 */ |
| 334 | }, | 338 | REGULATOR_SUPPLY("Vdd", "2-0060"), |
| 335 | { | ||
| 336 | .supply = "DRVDD", | ||
| 337 | .dev_name = "2-0018", | ||
| 338 | }, | ||
| 339 | /* Keep vmmc as last item. It is not iterated for newer boards */ | 339 | /* Keep vmmc as last item. It is not iterated for newer boards */ |
| 340 | { | 340 | REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), |
| 341 | .supply = "vmmc", | ||
| 342 | .dev_name = "mmci-omap-hs.1", | ||
| 343 | }, | ||
| 344 | }; | 341 | }; |
| 345 | 342 | ||
| 346 | static struct regulator_consumer_supply rx51_vio_supplies[] = { | 343 | static struct regulator_consumer_supply rx51_vio_supplies[] = { |
| 347 | /* tlv320aic3x digital supplies */ | 344 | /* tlv320aic3x digital supplies */ |
| 348 | { | 345 | REGULATOR_SUPPLY("IOVDD", "2-0018"), |
| 349 | .supply = "IOVDD", | 346 | REGULATOR_SUPPLY("DVDD", "2-0018"), |
| 350 | .dev_name = "2-0018" | ||
| 351 | }, | ||
| 352 | { | ||
| 353 | .supply = "DVDD", | ||
| 354 | .dev_name = "2-0018" | ||
| 355 | }, | ||
| 356 | }; | 347 | }; |
| 357 | 348 | ||
| 358 | #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) | 349 | #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) |
| @@ -373,6 +364,7 @@ static struct regulator_init_data rx51_vaux1 = { | |||
| 373 | .name = "V28", | 364 | .name = "V28", |
| 374 | .min_uV = 2800000, | 365 | .min_uV = 2800000, |
| 375 | .max_uV = 2800000, | 366 | .max_uV = 2800000, |
| 367 | .always_on = true, /* due battery cover sensor */ | ||
| 376 | .valid_modes_mask = REGULATOR_MODE_NORMAL | 368 | .valid_modes_mask = REGULATOR_MODE_NORMAL |
| 377 | | REGULATOR_MODE_STANDBY, | 369 | | REGULATOR_MODE_STANDBY, |
| 378 | .valid_ops_mask = REGULATOR_CHANGE_MODE | 370 | .valid_ops_mask = REGULATOR_CHANGE_MODE |
| @@ -718,6 +710,15 @@ static struct twl4030_platform_data rx51_twldata __initdata = { | |||
| 718 | .vio = &rx51_vio, | 710 | .vio = &rx51_vio, |
| 719 | }; | 711 | }; |
| 720 | 712 | ||
| 713 | static struct aic3x_pdata rx51_aic3x_data __initdata = { | ||
| 714 | .gpio_reset = 60, | ||
| 715 | }; | ||
| 716 | |||
| 717 | static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = { | ||
| 718 | .id = TPA6130A2, | ||
| 719 | .power_gpio = 98, | ||
| 720 | }; | ||
| 721 | |||
| 721 | static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { | 722 | static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { |
| 722 | { | 723 | { |
| 723 | I2C_BOARD_INFO("twl5030", 0x48), | 724 | I2C_BOARD_INFO("twl5030", 0x48), |
| @@ -730,7 +731,18 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { | |||
| 730 | static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = { | 731 | static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = { |
| 731 | { | 732 | { |
| 732 | I2C_BOARD_INFO("tlv320aic3x", 0x18), | 733 | I2C_BOARD_INFO("tlv320aic3x", 0x18), |
| 734 | .platform_data = &rx51_aic3x_data, | ||
| 735 | }, | ||
| 736 | #if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE) | ||
| 737 | { | ||
| 738 | I2C_BOARD_INFO("tsl2563", 0x29), | ||
| 739 | .platform_data = &rx51_tsl2563_platform_data, | ||
| 733 | }, | 740 | }, |
| 741 | #endif | ||
| 742 | { | ||
| 743 | I2C_BOARD_INFO("tpa6130a2", 0x60), | ||
| 744 | .platform_data = &rx51_tpa6130a2_data, | ||
| 745 | } | ||
| 734 | }; | 746 | }; |
| 735 | 747 | ||
| 736 | static int __init rx51_i2c_init(void) | 748 | static int __init rx51_i2c_init(void) |
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c index b743a4f42649..5a1005ba9815 100644 --- a/arch/arm/mach-omap2/board-rx51-video.c +++ b/arch/arm/mach-omap2/board-rx51-video.c | |||
| @@ -16,7 +16,6 @@ | |||
| 16 | #include <linux/mm.h> | 16 | #include <linux/mm.h> |
| 17 | 17 | ||
| 18 | #include <asm/mach-types.h> | 18 | #include <asm/mach-types.h> |
| 19 | #include <plat/mux.h> | ||
| 20 | #include <plat/display.h> | 19 | #include <plat/display.h> |
| 21 | #include <plat/vram.h> | 20 | #include <plat/vram.h> |
| 22 | #include <plat/mcspi.h> | 21 | #include <plat/mcspi.h> |
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 3bd956f9e19f..a58e8cb1a7fc 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c | |||
| @@ -143,7 +143,7 @@ static void __init rx51_init(void) | |||
| 143 | 143 | ||
| 144 | static void __init rx51_map_io(void) | 144 | static void __init rx51_map_io(void) |
| 145 | { | 145 | { |
| 146 | omap2_set_globals_343x(); | 146 | omap2_set_globals_3xxx(); |
| 147 | rx51_video_mem_init(); | 147 | rx51_video_mem_init(); |
| 148 | omap34xx_map_common_io(); | 148 | omap34xx_map_common_io(); |
| 149 | } | 149 | } |
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index ffe188cb18e9..3ad9ecf7f5e2 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c | |||
| @@ -71,30 +71,80 @@ static struct twl4030_platform_data zoom2_twldata = { | |||
| 71 | 71 | ||
| 72 | #ifdef CONFIG_OMAP_MUX | 72 | #ifdef CONFIG_OMAP_MUX |
| 73 | static struct omap_board_mux board_mux[] __initdata = { | 73 | static struct omap_board_mux board_mux[] __initdata = { |
| 74 | /* WLAN IRQ - GPIO 162 */ | ||
| 75 | OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), | ||
| 76 | /* WLAN POWER ENABLE - GPIO 101 */ | ||
| 77 | OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | ||
| 78 | /* WLAN SDIO: MMC3 CMD */ | ||
| 79 | OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), | ||
| 80 | /* WLAN SDIO: MMC3 CLK */ | ||
| 81 | OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 82 | /* WLAN SDIO: MMC3 DAT[0-3] */ | ||
| 83 | OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 84 | OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 85 | OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 86 | OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 74 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 87 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 75 | }; | 88 | }; |
| 76 | #else | 89 | #else |
| 77 | #define board_mux NULL | 90 | #define board_mux NULL |
| 78 | #endif | 91 | #endif |
| 79 | 92 | ||
| 93 | static struct mtd_partition zoom_nand_partitions[] = { | ||
| 94 | /* All the partition sizes are listed in terms of NAND block size */ | ||
| 95 | { | ||
| 96 | .name = "X-Loader-NAND", | ||
| 97 | .offset = 0, | ||
| 98 | .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ | ||
| 99 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 100 | }, | ||
| 101 | { | ||
| 102 | .name = "U-Boot-NAND", | ||
| 103 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | ||
| 104 | .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ | ||
| 105 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 106 | }, | ||
| 107 | { | ||
| 108 | .name = "Boot Env-NAND", | ||
| 109 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ | ||
| 110 | .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ | ||
| 111 | }, | ||
| 112 | { | ||
| 113 | .name = "Kernel-NAND", | ||
| 114 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ | ||
| 115 | .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ | ||
| 116 | }, | ||
| 117 | { | ||
| 118 | .name = "system", | ||
| 119 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ | ||
| 120 | .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */ | ||
| 121 | }, | ||
| 122 | { | ||
| 123 | .name = "userdata", | ||
| 124 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/ | ||
| 125 | .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ | ||
| 126 | }, | ||
| 127 | { | ||
| 128 | .name = "cache", | ||
| 129 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/ | ||
| 130 | .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ | ||
| 131 | }, | ||
| 132 | }; | ||
| 133 | |||
| 80 | static void __init omap_zoom2_init(void) | 134 | static void __init omap_zoom2_init(void) |
| 81 | { | 135 | { |
| 82 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 136 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| 83 | zoom_peripherals_init(); | 137 | zoom_peripherals_init(); |
| 138 | board_nand_init(zoom_nand_partitions, | ||
| 139 | ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); | ||
| 84 | zoom_debugboard_init(); | 140 | zoom_debugboard_init(); |
| 85 | } | 141 | } |
| 86 | 142 | ||
| 87 | static void __init omap_zoom2_map_io(void) | ||
| 88 | { | ||
| 89 | omap2_set_globals_343x(); | ||
| 90 | omap34xx_map_common_io(); | ||
| 91 | } | ||
| 92 | |||
| 93 | MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") | 143 | MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") |
| 94 | .phys_io = ZOOM_UART_BASE, | 144 | .phys_io = ZOOM_UART_BASE, |
| 95 | .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc, | 145 | .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc, |
| 96 | .boot_params = 0x80000100, | 146 | .boot_params = 0x80000100, |
| 97 | .map_io = omap_zoom2_map_io, | 147 | .map_io = omap3_map_io, |
| 98 | .reserve = omap_reserve, | 148 | .reserve = omap_reserve, |
| 99 | .init_irq = omap_zoom2_init_irq, | 149 | .init_irq = omap_zoom2_init_irq, |
| 100 | .init_machine = omap_zoom2_init, | 150 | .init_machine = omap_zoom2_init, |
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c index 5b605eba3e7b..6ca0b8341615 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom3.c | |||
| @@ -25,15 +25,50 @@ | |||
| 25 | #include "mux.h" | 25 | #include "mux.h" |
| 26 | #include "sdram-hynix-h8mbx00u0mer-0em.h" | 26 | #include "sdram-hynix-h8mbx00u0mer-0em.h" |
| 27 | 27 | ||
| 28 | static void __init omap_zoom_map_io(void) | ||
| 29 | { | ||
| 30 | omap2_set_globals_36xx(); | ||
| 31 | omap34xx_map_common_io(); | ||
| 32 | } | ||
| 33 | |||
| 34 | static struct omap_board_config_kernel zoom_config[] __initdata = { | 28 | static struct omap_board_config_kernel zoom_config[] __initdata = { |
| 35 | }; | 29 | }; |
| 36 | 30 | ||
| 31 | static struct mtd_partition zoom_nand_partitions[] = { | ||
| 32 | /* All the partition sizes are listed in terms of NAND block size */ | ||
| 33 | { | ||
| 34 | .name = "X-Loader-NAND", | ||
| 35 | .offset = 0, | ||
| 36 | .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ | ||
| 37 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 38 | }, | ||
| 39 | { | ||
| 40 | .name = "U-Boot-NAND", | ||
| 41 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | ||
| 42 | .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ | ||
| 43 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 44 | }, | ||
| 45 | { | ||
| 46 | .name = "Boot Env-NAND", | ||
| 47 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ | ||
| 48 | .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ | ||
| 49 | }, | ||
| 50 | { | ||
| 51 | .name = "Kernel-NAND", | ||
| 52 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ | ||
| 53 | .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ | ||
| 54 | }, | ||
| 55 | { | ||
| 56 | .name = "system", | ||
| 57 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ | ||
| 58 | .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */ | ||
| 59 | }, | ||
| 60 | { | ||
| 61 | .name = "userdata", | ||
| 62 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/ | ||
| 63 | .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ | ||
| 64 | }, | ||
| 65 | { | ||
| 66 | .name = "cache", | ||
| 67 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/ | ||
| 68 | .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ | ||
| 69 | }, | ||
| 70 | }; | ||
| 71 | |||
| 37 | static void __init omap_zoom_init_irq(void) | 72 | static void __init omap_zoom_init_irq(void) |
| 38 | { | 73 | { |
| 39 | omap_board_config = zoom_config; | 74 | omap_board_config = zoom_config; |
| @@ -46,6 +81,19 @@ static void __init omap_zoom_init_irq(void) | |||
| 46 | 81 | ||
| 47 | #ifdef CONFIG_OMAP_MUX | 82 | #ifdef CONFIG_OMAP_MUX |
| 48 | static struct omap_board_mux board_mux[] __initdata = { | 83 | static struct omap_board_mux board_mux[] __initdata = { |
| 84 | /* WLAN IRQ - GPIO 162 */ | ||
| 85 | OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), | ||
| 86 | /* WLAN POWER ENABLE - GPIO 101 */ | ||
| 87 | OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | ||
| 88 | /* WLAN SDIO: MMC3 CMD */ | ||
| 89 | OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), | ||
| 90 | /* WLAN SDIO: MMC3 CLK */ | ||
| 91 | OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 92 | /* WLAN SDIO: MMC3 DAT[0-3] */ | ||
| 93 | OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 94 | OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 95 | OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 96 | OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 49 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 97 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 50 | }; | 98 | }; |
| 51 | #else | 99 | #else |
| @@ -66,6 +114,8 @@ static void __init omap_zoom_init(void) | |||
| 66 | { | 114 | { |
| 67 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); | 115 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); |
| 68 | zoom_peripherals_init(); | 116 | zoom_peripherals_init(); |
| 117 | board_nand_init(zoom_nand_partitions, | ||
| 118 | ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); | ||
| 69 | zoom_debugboard_init(); | 119 | zoom_debugboard_init(); |
| 70 | 120 | ||
| 71 | omap_mux_init_gpio(64, OMAP_PIN_OUTPUT); | 121 | omap_mux_init_gpio(64, OMAP_PIN_OUTPUT); |
| @@ -76,7 +126,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") | |||
| 76 | .phys_io = ZOOM_UART_BASE, | 126 | .phys_io = ZOOM_UART_BASE, |
| 77 | .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc, | 127 | .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc, |
| 78 | .boot_params = 0x80000100, | 128 | .boot_params = 0x80000100, |
| 79 | .map_io = omap_zoom_map_io, | 129 | .map_io = omap3_map_io, |
| 80 | .reserve = omap_reserve, | 130 | .reserve = omap_reserve, |
| 81 | .init_irq = omap_zoom_init_irq, | 131 | .init_irq = omap_zoom_init_irq, |
| 82 | .init_machine = omap_zoom_init, | 132 | .init_machine = omap_zoom_init, |
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index d33744117ce2..138646deac89 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c | |||
| @@ -1408,7 +1408,7 @@ static struct clk ts_fck = { | |||
| 1408 | 1408 | ||
| 1409 | static struct clk usbtll_fck = { | 1409 | static struct clk usbtll_fck = { |
| 1410 | .name = "usbtll_fck", | 1410 | .name = "usbtll_fck", |
| 1411 | .ops = &clkops_omap2_dflt, | 1411 | .ops = &clkops_omap2_dflt_wait, |
| 1412 | .parent = &dpll5_m2_ck, | 1412 | .parent = &dpll5_m2_ck, |
| 1413 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | 1413 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1414 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | 1414 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c index 2d83565d2be2..721c3b66740a 100644 --- a/arch/arm/mach-omap2/cm.c +++ b/arch/arm/mach-omap2/cm.c | |||
| @@ -50,15 +50,15 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) | |||
| 50 | 50 | ||
| 51 | cm_idlest_reg = cm_idlest_offs[idlest_id - 1]; | 51 | cm_idlest_reg = cm_idlest_offs[idlest_id - 1]; |
| 52 | 52 | ||
| 53 | mask = 1 << idlest_shift; | ||
| 54 | |||
| 53 | if (cpu_is_omap24xx()) | 55 | if (cpu_is_omap24xx()) |
| 54 | ena = idlest_shift; | 56 | ena = mask; |
| 55 | else if (cpu_is_omap34xx()) | 57 | else if (cpu_is_omap34xx()) |
| 56 | ena = 0; | 58 | ena = 0; |
| 57 | else | 59 | else |
| 58 | BUG(); | 60 | BUG(); |
| 59 | 61 | ||
| 60 | mask = 1 << idlest_shift; | ||
| 61 | |||
| 62 | /* XXX should be OMAP2 CM */ | 62 | /* XXX should be OMAP2 CM */ |
| 63 | omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), | 63 | omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), |
| 64 | MAX_MODULE_READY_TIME, i); | 64 | MAX_MODULE_READY_TIME, i); |
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 03e6c9ed82a4..2dbb265bedd4 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | #include <plat/control.h> | 25 | #include <plat/control.h> |
| 26 | #include <plat/tc.h> | 26 | #include <plat/tc.h> |
| 27 | #include <plat/board.h> | 27 | #include <plat/board.h> |
| 28 | #include <plat/mux.h> | ||
| 29 | #include <mach/gpio.h> | 28 | #include <mach/gpio.h> |
| 30 | #include <plat/mmc.h> | 29 | #include <plat/mmc.h> |
| 31 | #include <plat/dma.h> | 30 | #include <plat/dma.h> |
| @@ -153,10 +152,12 @@ static struct resource omap2_mbox_resources[] = { | |||
| 153 | { | 152 | { |
| 154 | .start = INT_24XX_MAIL_U0_MPU, | 153 | .start = INT_24XX_MAIL_U0_MPU, |
| 155 | .flags = IORESOURCE_IRQ, | 154 | .flags = IORESOURCE_IRQ, |
| 155 | .name = "dsp", | ||
| 156 | }, | 156 | }, |
| 157 | { | 157 | { |
| 158 | .start = INT_24XX_MAIL_U3_MPU, | 158 | .start = INT_24XX_MAIL_U3_MPU, |
| 159 | .flags = IORESOURCE_IRQ, | 159 | .flags = IORESOURCE_IRQ, |
| 160 | .name = "iva", | ||
| 160 | }, | 161 | }, |
| 161 | }; | 162 | }; |
| 162 | static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources); | 163 | static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources); |
| @@ -175,6 +176,7 @@ static struct resource omap3_mbox_resources[] = { | |||
| 175 | { | 176 | { |
| 176 | .start = INT_24XX_MAIL_U0_MPU, | 177 | .start = INT_24XX_MAIL_U0_MPU, |
| 177 | .flags = IORESOURCE_IRQ, | 178 | .flags = IORESOURCE_IRQ, |
| 179 | .name = "dsp", | ||
| 178 | }, | 180 | }, |
| 179 | }; | 181 | }; |
| 180 | static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources); | 182 | static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources); |
| @@ -196,6 +198,7 @@ static struct resource omap4_mbox_resources[] = { | |||
| 196 | { | 198 | { |
| 197 | .start = OMAP44XX_IRQ_MAIL_U0, | 199 | .start = OMAP44XX_IRQ_MAIL_U0, |
| 198 | .flags = IORESOURCE_IRQ, | 200 | .flags = IORESOURCE_IRQ, |
| 201 | .name = "mbox", | ||
| 199 | }, | 202 | }, |
| 200 | }; | 203 | }; |
| 201 | static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); | 204 | static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); |
| @@ -205,7 +208,7 @@ static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); | |||
| 205 | #endif | 208 | #endif |
| 206 | 209 | ||
| 207 | static struct platform_device mbox_device = { | 210 | static struct platform_device mbox_device = { |
| 208 | .name = "omap2-mailbox", | 211 | .name = "omap-mailbox", |
| 209 | .id = -1, | 212 | .id = -1, |
| 210 | }; | 213 | }; |
| 211 | 214 | ||
| @@ -230,64 +233,7 @@ static inline void omap_init_mbox(void) | |||
| 230 | static inline void omap_init_mbox(void) { } | 233 | static inline void omap_init_mbox(void) { } |
| 231 | #endif /* CONFIG_OMAP_MBOX_FWK */ | 234 | #endif /* CONFIG_OMAP_MBOX_FWK */ |
| 232 | 235 | ||
| 233 | #if defined(CONFIG_OMAP_STI) | ||
| 234 | |||
| 235 | #if defined(CONFIG_ARCH_OMAP2) | ||
| 236 | |||
| 237 | #define OMAP2_STI_BASE 0x48068000 | ||
| 238 | #define OMAP2_STI_CHANNEL_BASE 0x54000000 | ||
| 239 | #define OMAP2_STI_IRQ 4 | ||
| 240 | |||
| 241 | static struct resource sti_resources[] = { | ||
| 242 | { | ||
| 243 | .start = OMAP2_STI_BASE, | ||
| 244 | .end = OMAP2_STI_BASE + 0x7ff, | ||
| 245 | .flags = IORESOURCE_MEM, | ||
| 246 | }, | ||
| 247 | { | ||
| 248 | .start = OMAP2_STI_CHANNEL_BASE, | ||
| 249 | .end = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1, | ||
| 250 | .flags = IORESOURCE_MEM, | ||
| 251 | }, | ||
| 252 | { | ||
| 253 | .start = OMAP2_STI_IRQ, | ||
| 254 | .flags = IORESOURCE_IRQ, | ||
| 255 | } | ||
| 256 | }; | ||
| 257 | #elif defined(CONFIG_ARCH_OMAP3) | ||
| 258 | |||
| 259 | #define OMAP3_SDTI_BASE 0x54500000 | ||
| 260 | #define OMAP3_SDTI_CHANNEL_BASE 0x54600000 | ||
| 261 | |||
| 262 | static struct resource sti_resources[] = { | ||
| 263 | { | ||
| 264 | .start = OMAP3_SDTI_BASE, | ||
| 265 | .end = OMAP3_SDTI_BASE + 0xFFF, | ||
| 266 | .flags = IORESOURCE_MEM, | ||
| 267 | }, | ||
| 268 | { | ||
| 269 | .start = OMAP3_SDTI_CHANNEL_BASE, | ||
| 270 | .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1, | ||
| 271 | .flags = IORESOURCE_MEM, | ||
| 272 | } | ||
| 273 | }; | ||
| 274 | |||
| 275 | #endif | ||
| 276 | |||
| 277 | static struct platform_device sti_device = { | ||
| 278 | .name = "sti", | ||
| 279 | .id = -1, | ||
| 280 | .num_resources = ARRAY_SIZE(sti_resources), | ||
| 281 | .resource = sti_resources, | ||
| 282 | }; | ||
| 283 | |||
| 284 | static inline void omap_init_sti(void) | ||
| 285 | { | ||
| 286 | platform_device_register(&sti_device); | ||
| 287 | } | ||
| 288 | #else | ||
| 289 | static inline void omap_init_sti(void) {} | 236 | static inline void omap_init_sti(void) {} |
| 290 | #endif | ||
| 291 | 237 | ||
| 292 | #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) | 238 | #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) |
| 293 | 239 | ||
| @@ -672,19 +618,19 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, | |||
| 672 | OMAP_PIN_INPUT_PULLUP); | 618 | OMAP_PIN_INPUT_PULLUP); |
| 673 | 619 | ||
| 674 | if (cpu_is_omap2420() && controller_nr == 0) { | 620 | if (cpu_is_omap2420() && controller_nr == 0) { |
| 675 | omap_cfg_reg(H18_24XX_MMC_CMD); | 621 | omap_mux_init_signal("sdmmc_cmd", 0); |
| 676 | omap_cfg_reg(H15_24XX_MMC_CLKI); | 622 | omap_mux_init_signal("sdmmc_clki", 0); |
| 677 | omap_cfg_reg(G19_24XX_MMC_CLKO); | 623 | omap_mux_init_signal("sdmmc_clko", 0); |
| 678 | omap_cfg_reg(F20_24XX_MMC_DAT0); | 624 | omap_mux_init_signal("sdmmc_dat0", 0); |
| 679 | omap_cfg_reg(F19_24XX_MMC_DAT_DIR0); | 625 | omap_mux_init_signal("sdmmc_dat_dir0", 0); |
| 680 | omap_cfg_reg(G18_24XX_MMC_CMD_DIR); | 626 | omap_mux_init_signal("sdmmc_cmd_dir", 0); |
| 681 | if (mmc_controller->slots[0].wires == 4) { | 627 | if (mmc_controller->slots[0].wires == 4) { |
| 682 | omap_cfg_reg(H14_24XX_MMC_DAT1); | 628 | omap_mux_init_signal("sdmmc_dat1", 0); |
| 683 | omap_cfg_reg(E19_24XX_MMC_DAT2); | 629 | omap_mux_init_signal("sdmmc_dat2", 0); |
| 684 | omap_cfg_reg(D19_24XX_MMC_DAT3); | 630 | omap_mux_init_signal("sdmmc_dat3", 0); |
| 685 | omap_cfg_reg(E20_24XX_MMC_DAT_DIR1); | 631 | omap_mux_init_signal("sdmmc_dat_dir1", 0); |
| 686 | omap_cfg_reg(F18_24XX_MMC_DAT_DIR2); | 632 | omap_mux_init_signal("sdmmc_dat_dir2", 0); |
| 687 | omap_cfg_reg(E18_24XX_MMC_DAT_DIR3); | 633 | omap_mux_init_signal("sdmmc_dat_dir3", 0); |
| 688 | } | 634 | } |
| 689 | 635 | ||
| 690 | /* | 636 | /* |
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index e57fb29ff855..722209601927 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c | |||
| @@ -19,8 +19,6 @@ | |||
| 19 | #include <plat/board.h> | 19 | #include <plat/board.h> |
| 20 | #include <plat/gpmc.h> | 20 | #include <plat/gpmc.h> |
| 21 | 21 | ||
| 22 | #define WR_RD_PIN_MONITORING 0x00600000 | ||
| 23 | |||
| 24 | static struct omap_nand_platform_data *gpmc_nand_data; | 22 | static struct omap_nand_platform_data *gpmc_nand_data; |
| 25 | 23 | ||
| 26 | static struct resource gpmc_nand_resource = { | 24 | static struct resource gpmc_nand_resource = { |
| @@ -71,10 +69,10 @@ static int omap2_nand_gpmc_retime(void) | |||
| 71 | t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); | 69 | t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); |
| 72 | 70 | ||
| 73 | /* Configure GPMC */ | 71 | /* Configure GPMC */ |
| 74 | gpmc_cs_write_reg(gpmc_nand_data->cs, GPMC_CS_CONFIG1, | 72 | gpmc_cs_configure(gpmc_nand_data->cs, |
| 75 | GPMC_CONFIG1_DEVICESIZE(gpmc_nand_data->devsize) | | 73 | GPMC_CONFIG_DEV_SIZE, gpmc_nand_data->devsize); |
| 76 | GPMC_CONFIG1_DEVICETYPE_NAND); | 74 | gpmc_cs_configure(gpmc_nand_data->cs, |
| 77 | 75 | GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); | |
| 78 | err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); | 76 | err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); |
| 79 | if (err) | 77 | if (err) |
| 80 | return err; | 78 | return err; |
| @@ -82,27 +80,13 @@ static int omap2_nand_gpmc_retime(void) | |||
| 82 | return 0; | 80 | return 0; |
| 83 | } | 81 | } |
| 84 | 82 | ||
| 85 | static int gpmc_nand_setup(void) | ||
| 86 | { | ||
| 87 | struct device *dev = &gpmc_nand_device.dev; | ||
| 88 | |||
| 89 | /* Set timings in GPMC */ | ||
| 90 | if (omap2_nand_gpmc_retime() < 0) { | ||
| 91 | dev_err(dev, "Unable to set gpmc timings\n"); | ||
| 92 | return -EINVAL; | ||
| 93 | } | ||
| 94 | |||
| 95 | return 0; | ||
| 96 | } | ||
| 97 | |||
| 98 | int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) | 83 | int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) |
| 99 | { | 84 | { |
| 100 | unsigned int val; | ||
| 101 | int err = 0; | 85 | int err = 0; |
| 102 | struct device *dev = &gpmc_nand_device.dev; | 86 | struct device *dev = &gpmc_nand_device.dev; |
| 103 | 87 | ||
| 104 | gpmc_nand_data = _nand_data; | 88 | gpmc_nand_data = _nand_data; |
| 105 | gpmc_nand_data->nand_setup = gpmc_nand_setup; | 89 | gpmc_nand_data->nand_setup = omap2_nand_gpmc_retime; |
| 106 | gpmc_nand_device.dev.platform_data = gpmc_nand_data; | 90 | gpmc_nand_device.dev.platform_data = gpmc_nand_data; |
| 107 | 91 | ||
| 108 | err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, | 92 | err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, |
| @@ -112,19 +96,16 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) | |||
| 112 | return err; | 96 | return err; |
| 113 | } | 97 | } |
| 114 | 98 | ||
| 115 | err = gpmc_nand_setup(); | 99 | /* Set timings in GPMC */ |
| 100 | err = omap2_nand_gpmc_retime(); | ||
| 116 | if (err < 0) { | 101 | if (err < 0) { |
| 117 | dev_err(dev, "NAND platform setup failed: %d\n", err); | 102 | dev_err(dev, "Unable to set gpmc timings: %d\n", err); |
| 118 | return err; | 103 | return err; |
| 119 | } | 104 | } |
| 120 | 105 | ||
| 121 | /* Enable RD PIN Monitoring Reg */ | 106 | /* Enable RD PIN Monitoring Reg */ |
| 122 | if (gpmc_nand_data->dev_ready) { | 107 | if (gpmc_nand_data->dev_ready) { |
| 123 | val = gpmc_cs_read_reg(gpmc_nand_data->cs, | 108 | gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1); |
| 124 | GPMC_CS_CONFIG1); | ||
| 125 | val |= WR_RD_PIN_MONITORING; | ||
| 126 | gpmc_cs_write_reg(gpmc_nand_data->cs, | ||
| 127 | GPMC_CS_CONFIG1, val); | ||
| 128 | } | 109 | } |
| 129 | 110 | ||
| 130 | err = platform_device_register(&gpmc_nand_device); | 111 | err = platform_device_register(&gpmc_nand_device); |
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 5bc3ca03551c..f46933bc9373 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
| @@ -46,8 +46,9 @@ | |||
| 46 | #define GPMC_ECC_CONFIG 0x1f4 | 46 | #define GPMC_ECC_CONFIG 0x1f4 |
| 47 | #define GPMC_ECC_CONTROL 0x1f8 | 47 | #define GPMC_ECC_CONTROL 0x1f8 |
| 48 | #define GPMC_ECC_SIZE_CONFIG 0x1fc | 48 | #define GPMC_ECC_SIZE_CONFIG 0x1fc |
| 49 | #define GPMC_ECC1_RESULT 0x200 | ||
| 49 | 50 | ||
| 50 | #define GPMC_CS0 0x60 | 51 | #define GPMC_CS0_OFFSET 0x60 |
| 51 | #define GPMC_CS_SIZE 0x30 | 52 | #define GPMC_CS_SIZE 0x30 |
| 52 | 53 | ||
| 53 | #define GPMC_MEM_START 0x00000000 | 54 | #define GPMC_MEM_START 0x00000000 |
| @@ -92,7 +93,8 @@ struct omap3_gpmc_regs { | |||
| 92 | static struct resource gpmc_mem_root; | 93 | static struct resource gpmc_mem_root; |
| 93 | static struct resource gpmc_cs_mem[GPMC_CS_NUM]; | 94 | static struct resource gpmc_cs_mem[GPMC_CS_NUM]; |
| 94 | static DEFINE_SPINLOCK(gpmc_mem_lock); | 95 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
| 95 | static unsigned gpmc_cs_map; | 96 | static unsigned int gpmc_cs_map; /* flag for cs which are initialized */ |
| 97 | static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */ | ||
| 96 | 98 | ||
| 97 | static void __iomem *gpmc_base; | 99 | static void __iomem *gpmc_base; |
| 98 | 100 | ||
| @@ -108,11 +110,27 @@ static u32 gpmc_read_reg(int idx) | |||
| 108 | return __raw_readl(gpmc_base + idx); | 110 | return __raw_readl(gpmc_base + idx); |
| 109 | } | 111 | } |
| 110 | 112 | ||
| 113 | static void gpmc_cs_write_byte(int cs, int idx, u8 val) | ||
| 114 | { | ||
| 115 | void __iomem *reg_addr; | ||
| 116 | |||
| 117 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; | ||
| 118 | __raw_writeb(val, reg_addr); | ||
| 119 | } | ||
| 120 | |||
| 121 | static u8 gpmc_cs_read_byte(int cs, int idx) | ||
| 122 | { | ||
| 123 | void __iomem *reg_addr; | ||
| 124 | |||
| 125 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; | ||
| 126 | return __raw_readb(reg_addr); | ||
| 127 | } | ||
| 128 | |||
| 111 | void gpmc_cs_write_reg(int cs, int idx, u32 val) | 129 | void gpmc_cs_write_reg(int cs, int idx, u32 val) |
| 112 | { | 130 | { |
| 113 | void __iomem *reg_addr; | 131 | void __iomem *reg_addr; |
| 114 | 132 | ||
| 115 | reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx; | 133 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
| 116 | __raw_writel(val, reg_addr); | 134 | __raw_writel(val, reg_addr); |
| 117 | } | 135 | } |
| 118 | 136 | ||
| @@ -120,7 +138,7 @@ u32 gpmc_cs_read_reg(int cs, int idx) | |||
| 120 | { | 138 | { |
| 121 | void __iomem *reg_addr; | 139 | void __iomem *reg_addr; |
| 122 | 140 | ||
| 123 | reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx; | 141 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
| 124 | return __raw_readl(reg_addr); | 142 | return __raw_readl(reg_addr); |
| 125 | } | 143 | } |
| 126 | 144 | ||
| @@ -419,8 +437,157 @@ void gpmc_cs_free(int cs) | |||
| 419 | EXPORT_SYMBOL(gpmc_cs_free); | 437 | EXPORT_SYMBOL(gpmc_cs_free); |
| 420 | 438 | ||
| 421 | /** | 439 | /** |
| 440 | * gpmc_read_status - read access request to get the different gpmc status | ||
| 441 | * @cmd: command type | ||
| 442 | * @return status | ||
| 443 | */ | ||
| 444 | int gpmc_read_status(int cmd) | ||
| 445 | { | ||
| 446 | int status = -EINVAL; | ||
| 447 | u32 regval = 0; | ||
| 448 | |||
| 449 | switch (cmd) { | ||
| 450 | case GPMC_GET_IRQ_STATUS: | ||
| 451 | status = gpmc_read_reg(GPMC_IRQSTATUS); | ||
| 452 | break; | ||
| 453 | |||
| 454 | case GPMC_PREFETCH_FIFO_CNT: | ||
| 455 | regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); | ||
| 456 | status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval); | ||
| 457 | break; | ||
| 458 | |||
| 459 | case GPMC_PREFETCH_COUNT: | ||
| 460 | regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); | ||
| 461 | status = GPMC_PREFETCH_STATUS_COUNT(regval); | ||
| 462 | break; | ||
| 463 | |||
| 464 | case GPMC_STATUS_BUFFER: | ||
| 465 | regval = gpmc_read_reg(GPMC_STATUS); | ||
| 466 | /* 1 : buffer is available to write */ | ||
| 467 | status = regval & GPMC_STATUS_BUFF_EMPTY; | ||
| 468 | break; | ||
| 469 | |||
| 470 | default: | ||
| 471 | printk(KERN_ERR "gpmc_read_status: Not supported\n"); | ||
| 472 | } | ||
| 473 | return status; | ||
| 474 | } | ||
| 475 | EXPORT_SYMBOL(gpmc_read_status); | ||
| 476 | |||
| 477 | /** | ||
| 478 | * gpmc_cs_configure - write request to configure gpmc | ||
| 479 | * @cs: chip select number | ||
| 480 | * @cmd: command type | ||
| 481 | * @wval: value to write | ||
| 482 | * @return status of the operation | ||
| 483 | */ | ||
| 484 | int gpmc_cs_configure(int cs, int cmd, int wval) | ||
| 485 | { | ||
| 486 | int err = 0; | ||
| 487 | u32 regval = 0; | ||
| 488 | |||
| 489 | switch (cmd) { | ||
| 490 | case GPMC_SET_IRQ_STATUS: | ||
| 491 | gpmc_write_reg(GPMC_IRQSTATUS, wval); | ||
| 492 | break; | ||
| 493 | |||
| 494 | case GPMC_CONFIG_WP: | ||
| 495 | regval = gpmc_read_reg(GPMC_CONFIG); | ||
| 496 | if (wval) | ||
| 497 | regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ | ||
| 498 | else | ||
| 499 | regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ | ||
| 500 | gpmc_write_reg(GPMC_CONFIG, regval); | ||
| 501 | break; | ||
| 502 | |||
| 503 | case GPMC_CONFIG_RDY_BSY: | ||
| 504 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | ||
| 505 | if (wval) | ||
| 506 | regval |= WR_RD_PIN_MONITORING; | ||
| 507 | else | ||
| 508 | regval &= ~WR_RD_PIN_MONITORING; | ||
| 509 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | ||
| 510 | break; | ||
| 511 | |||
| 512 | case GPMC_CONFIG_DEV_SIZE: | ||
| 513 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | ||
| 514 | regval |= GPMC_CONFIG1_DEVICESIZE(wval); | ||
| 515 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | ||
| 516 | break; | ||
| 517 | |||
| 518 | case GPMC_CONFIG_DEV_TYPE: | ||
| 519 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | ||
| 520 | regval |= GPMC_CONFIG1_DEVICETYPE(wval); | ||
| 521 | if (wval == GPMC_DEVICETYPE_NOR) | ||
| 522 | regval |= GPMC_CONFIG1_MUXADDDATA; | ||
| 523 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | ||
| 524 | break; | ||
| 525 | |||
| 526 | default: | ||
| 527 | printk(KERN_ERR "gpmc_configure_cs: Not supported\n"); | ||
| 528 | err = -EINVAL; | ||
| 529 | } | ||
| 530 | |||
| 531 | return err; | ||
| 532 | } | ||
| 533 | EXPORT_SYMBOL(gpmc_cs_configure); | ||
| 534 | |||
| 535 | /** | ||
| 536 | * gpmc_nand_read - nand specific read access request | ||
| 537 | * @cs: chip select number | ||
| 538 | * @cmd: command type | ||
| 539 | */ | ||
| 540 | int gpmc_nand_read(int cs, int cmd) | ||
| 541 | { | ||
| 542 | int rval = -EINVAL; | ||
| 543 | |||
| 544 | switch (cmd) { | ||
| 545 | case GPMC_NAND_DATA: | ||
| 546 | rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA); | ||
| 547 | break; | ||
| 548 | |||
| 549 | default: | ||
| 550 | printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n"); | ||
| 551 | } | ||
| 552 | return rval; | ||
| 553 | } | ||
| 554 | EXPORT_SYMBOL(gpmc_nand_read); | ||
| 555 | |||
| 556 | /** | ||
| 557 | * gpmc_nand_write - nand specific write request | ||
| 558 | * @cs: chip select number | ||
| 559 | * @cmd: command type | ||
| 560 | * @wval: value to write | ||
| 561 | */ | ||
| 562 | int gpmc_nand_write(int cs, int cmd, int wval) | ||
| 563 | { | ||
| 564 | int err = 0; | ||
| 565 | |||
| 566 | switch (cmd) { | ||
| 567 | case GPMC_NAND_COMMAND: | ||
| 568 | gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval); | ||
| 569 | break; | ||
| 570 | |||
| 571 | case GPMC_NAND_ADDRESS: | ||
| 572 | gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval); | ||
| 573 | break; | ||
| 574 | |||
| 575 | case GPMC_NAND_DATA: | ||
| 576 | gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval); | ||
| 577 | |||
| 578 | default: | ||
| 579 | printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n"); | ||
| 580 | err = -EINVAL; | ||
| 581 | } | ||
| 582 | return err; | ||
| 583 | } | ||
| 584 | EXPORT_SYMBOL(gpmc_nand_write); | ||
| 585 | |||
| 586 | |||
| 587 | |||
| 588 | /** | ||
| 422 | * gpmc_prefetch_enable - configures and starts prefetch transfer | 589 | * gpmc_prefetch_enable - configures and starts prefetch transfer |
| 423 | * @cs: nand cs (chip select) number | 590 | * @cs: cs (chip select) number |
| 424 | * @dma_mode: dma mode enable (1) or disable (0) | 591 | * @dma_mode: dma mode enable (1) or disable (0) |
| 425 | * @u32_count: number of bytes to be transferred | 592 | * @u32_count: number of bytes to be transferred |
| 426 | * @is_write: prefetch read(0) or write post(1) mode | 593 | * @is_write: prefetch read(0) or write post(1) mode |
| @@ -428,7 +595,6 @@ EXPORT_SYMBOL(gpmc_cs_free); | |||
| 428 | int gpmc_prefetch_enable(int cs, int dma_mode, | 595 | int gpmc_prefetch_enable(int cs, int dma_mode, |
| 429 | unsigned int u32_count, int is_write) | 596 | unsigned int u32_count, int is_write) |
| 430 | { | 597 | { |
| 431 | uint32_t prefetch_config1; | ||
| 432 | 598 | ||
| 433 | if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { | 599 | if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { |
| 434 | /* Set the amount of bytes to be prefetched */ | 600 | /* Set the amount of bytes to be prefetched */ |
| @@ -437,17 +603,17 @@ int gpmc_prefetch_enable(int cs, int dma_mode, | |||
| 437 | /* Set dma/mpu mode, the prefetch read / post write and | 603 | /* Set dma/mpu mode, the prefetch read / post write and |
| 438 | * enable the engine. Set which cs is has requested for. | 604 | * enable the engine. Set which cs is has requested for. |
| 439 | */ | 605 | */ |
| 440 | prefetch_config1 = ((cs << CS_NUM_SHIFT) | | 606 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) | |
| 441 | PREFETCH_FIFOTHRESHOLD | | 607 | PREFETCH_FIFOTHRESHOLD | |
| 442 | ENABLE_PREFETCH | | 608 | ENABLE_PREFETCH | |
| 443 | (dma_mode << DMA_MPU_MODE) | | 609 | (dma_mode << DMA_MPU_MODE) | |
| 444 | (0x1 & is_write)); | 610 | (0x1 & is_write))); |
| 445 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1); | 611 | |
| 612 | /* Start the prefetch engine */ | ||
| 613 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1); | ||
| 446 | } else { | 614 | } else { |
| 447 | return -EBUSY; | 615 | return -EBUSY; |
| 448 | } | 616 | } |
| 449 | /* Start the prefetch engine */ | ||
| 450 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1); | ||
| 451 | 617 | ||
| 452 | return 0; | 618 | return 0; |
| 453 | } | 619 | } |
| @@ -456,24 +622,24 @@ EXPORT_SYMBOL(gpmc_prefetch_enable); | |||
| 456 | /** | 622 | /** |
| 457 | * gpmc_prefetch_reset - disables and stops the prefetch engine | 623 | * gpmc_prefetch_reset - disables and stops the prefetch engine |
| 458 | */ | 624 | */ |
| 459 | void gpmc_prefetch_reset(void) | 625 | int gpmc_prefetch_reset(int cs) |
| 460 | { | 626 | { |
| 627 | u32 config1; | ||
| 628 | |||
| 629 | /* check if the same module/cs is trying to reset */ | ||
| 630 | config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | ||
| 631 | if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs) | ||
| 632 | return -EINVAL; | ||
| 633 | |||
| 461 | /* Stop the PFPW engine */ | 634 | /* Stop the PFPW engine */ |
| 462 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0); | 635 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0); |
| 463 | 636 | ||
| 464 | /* Reset/disable the PFPW engine */ | 637 | /* Reset/disable the PFPW engine */ |
| 465 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0); | 638 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0); |
| 466 | } | ||
| 467 | EXPORT_SYMBOL(gpmc_prefetch_reset); | ||
| 468 | 639 | ||
| 469 | /** | 640 | return 0; |
| 470 | * gpmc_prefetch_status - reads prefetch status of engine | ||
| 471 | */ | ||
| 472 | int gpmc_prefetch_status(void) | ||
| 473 | { | ||
| 474 | return gpmc_read_reg(GPMC_PREFETCH_STATUS); | ||
| 475 | } | 641 | } |
| 476 | EXPORT_SYMBOL(gpmc_prefetch_status); | 642 | EXPORT_SYMBOL(gpmc_prefetch_reset); |
| 477 | 643 | ||
| 478 | static void __init gpmc_mem_init(void) | 644 | static void __init gpmc_mem_init(void) |
| 479 | { | 645 | { |
| @@ -615,3 +781,79 @@ void omap3_gpmc_restore_context(void) | |||
| 615 | } | 781 | } |
| 616 | } | 782 | } |
| 617 | #endif /* CONFIG_ARCH_OMAP3 */ | 783 | #endif /* CONFIG_ARCH_OMAP3 */ |
| 784 | |||
| 785 | /** | ||
| 786 | * gpmc_enable_hwecc - enable hardware ecc functionality | ||
| 787 | * @cs: chip select number | ||
| 788 | * @mode: read/write mode | ||
| 789 | * @dev_width: device bus width(1 for x16, 0 for x8) | ||
| 790 | * @ecc_size: bytes for which ECC will be generated | ||
| 791 | */ | ||
| 792 | int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size) | ||
| 793 | { | ||
| 794 | unsigned int val; | ||
| 795 | |||
| 796 | /* check if ecc module is in used */ | ||
| 797 | if (gpmc_ecc_used != -EINVAL) | ||
| 798 | return -EINVAL; | ||
| 799 | |||
| 800 | gpmc_ecc_used = cs; | ||
| 801 | |||
| 802 | /* clear ecc and enable bits */ | ||
| 803 | val = ((0x00000001<<8) | 0x00000001); | ||
| 804 | gpmc_write_reg(GPMC_ECC_CONTROL, val); | ||
| 805 | |||
| 806 | /* program ecc and result sizes */ | ||
| 807 | val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F)); | ||
| 808 | gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val); | ||
| 809 | |||
| 810 | switch (mode) { | ||
| 811 | case GPMC_ECC_READ: | ||
| 812 | gpmc_write_reg(GPMC_ECC_CONTROL, 0x101); | ||
| 813 | break; | ||
| 814 | case GPMC_ECC_READSYN: | ||
| 815 | gpmc_write_reg(GPMC_ECC_CONTROL, 0x100); | ||
| 816 | break; | ||
| 817 | case GPMC_ECC_WRITE: | ||
| 818 | gpmc_write_reg(GPMC_ECC_CONTROL, 0x101); | ||
| 819 | break; | ||
| 820 | default: | ||
| 821 | printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode); | ||
| 822 | break; | ||
| 823 | } | ||
| 824 | |||
| 825 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ | ||
| 826 | val = (dev_width << 7) | (cs << 1) | (0x1); | ||
| 827 | gpmc_write_reg(GPMC_ECC_CONFIG, val); | ||
| 828 | return 0; | ||
| 829 | } | ||
| 830 | |||
| 831 | /** | ||
| 832 | * gpmc_calculate_ecc - generate non-inverted ecc bytes | ||
| 833 | * @cs: chip select number | ||
| 834 | * @dat: data pointer over which ecc is computed | ||
| 835 | * @ecc_code: ecc code buffer | ||
| 836 | * | ||
| 837 | * Using non-inverted ECC is considered ugly since writing a blank | ||
| 838 | * page (padding) will clear the ECC bytes. This is not a problem as long | ||
| 839 | * no one is trying to write data on the seemingly unused page. Reading | ||
| 840 | * an erased page will produce an ECC mismatch between generated and read | ||
| 841 | * ECC bytes that has to be dealt with separately. | ||
| 842 | */ | ||
| 843 | int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code) | ||
| 844 | { | ||
| 845 | unsigned int val = 0x0; | ||
| 846 | |||
| 847 | if (gpmc_ecc_used != cs) | ||
| 848 | return -EINVAL; | ||
| 849 | |||
| 850 | /* read ecc result */ | ||
| 851 | val = gpmc_read_reg(GPMC_ECC1_RESULT); | ||
| 852 | *ecc_code++ = val; /* P128e, ..., P1e */ | ||
| 853 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | ||
| 854 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | ||
| 855 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | ||
| 856 | |||
| 857 | gpmc_ecc_used = -EINVAL; | ||
| 858 | return 0; | ||
| 859 | } | ||
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c index 7951ae1447ee..79c478c4cb1c 100644 --- a/arch/arm/mach-omap2/i2c.c +++ b/arch/arm/mach-omap2/i2c.c | |||
| @@ -21,32 +21,19 @@ | |||
| 21 | 21 | ||
| 22 | #include <plat/cpu.h> | 22 | #include <plat/cpu.h> |
| 23 | #include <plat/i2c.h> | 23 | #include <plat/i2c.h> |
| 24 | #include <plat/mux.h> | ||
| 25 | 24 | ||
| 26 | #include "mux.h" | 25 | #include "mux.h" |
| 27 | 26 | ||
| 28 | void __init omap2_i2c_mux_pins(int bus_id) | 27 | void __init omap2_i2c_mux_pins(int bus_id) |
| 29 | { | 28 | { |
| 30 | if (cpu_is_omap24xx()) { | 29 | char mux_name[sizeof("i2c2_scl.i2c2_scl")]; |
| 31 | const int omap24xx_pins[][2] = { | ||
| 32 | { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA }, | ||
| 33 | { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA }, | ||
| 34 | }; | ||
| 35 | int scl, sda; | ||
| 36 | |||
| 37 | scl = omap24xx_pins[bus_id - 1][0]; | ||
| 38 | sda = omap24xx_pins[bus_id - 1][1]; | ||
| 39 | omap_cfg_reg(sda); | ||
| 40 | omap_cfg_reg(scl); | ||
| 41 | } | ||
| 42 | 30 | ||
| 43 | /* First I2C bus is not muxable */ | 31 | /* First I2C bus is not muxable */ |
| 44 | if (cpu_is_omap34xx() && bus_id > 1) { | 32 | if (bus_id == 1) |
| 45 | char mux_name[sizeof("i2c2_scl.i2c2_scl")]; | 33 | return; |
| 46 | 34 | ||
| 47 | sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id); | 35 | sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id); |
| 48 | omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); | 36 | omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); |
| 49 | sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id); | 37 | sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id); |
| 50 | omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); | 38 | omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); |
| 51 | } | ||
| 52 | } | 39 | } |
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 37b8a1a4adf8..e8256a2ed8e7 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c | |||
| @@ -25,6 +25,8 @@ | |||
| 25 | #include <plat/control.h> | 25 | #include <plat/control.h> |
| 26 | #include <plat/cpu.h> | 26 | #include <plat/cpu.h> |
| 27 | 27 | ||
| 28 | #include <mach/id.h> | ||
| 29 | |||
| 28 | static struct omap_chip_id omap_chip; | 30 | static struct omap_chip_id omap_chip; |
| 29 | static unsigned int omap_revision; | 31 | static unsigned int omap_revision; |
| 30 | 32 | ||
| @@ -102,30 +104,36 @@ static struct omap_id omap_ids[] __initdata = { | |||
| 102 | static void __iomem *tap_base; | 104 | static void __iomem *tap_base; |
| 103 | static u16 tap_prod_id; | 105 | static u16 tap_prod_id; |
| 104 | 106 | ||
| 105 | void __init omap24xx_check_revision(void) | 107 | void omap_get_die_id(struct omap_die_id *odi) |
| 108 | { | ||
| 109 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); | ||
| 110 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); | ||
| 111 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); | ||
| 112 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); | ||
| 113 | } | ||
| 114 | |||
| 115 | static void __init omap24xx_check_revision(void) | ||
| 106 | { | 116 | { |
| 107 | int i, j; | 117 | int i, j; |
| 108 | u32 idcode, prod_id; | 118 | u32 idcode, prod_id; |
| 109 | u16 hawkeye; | 119 | u16 hawkeye; |
| 110 | u8 dev_type, rev; | 120 | u8 dev_type, rev; |
| 121 | struct omap_die_id odi; | ||
| 111 | 122 | ||
| 112 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | 123 | idcode = read_tap_reg(OMAP_TAP_IDCODE); |
| 113 | prod_id = read_tap_reg(tap_prod_id); | 124 | prod_id = read_tap_reg(tap_prod_id); |
| 114 | hawkeye = (idcode >> 12) & 0xffff; | 125 | hawkeye = (idcode >> 12) & 0xffff; |
| 115 | rev = (idcode >> 28) & 0x0f; | 126 | rev = (idcode >> 28) & 0x0f; |
| 116 | dev_type = (prod_id >> 16) & 0x0f; | 127 | dev_type = (prod_id >> 16) & 0x0f; |
| 128 | omap_get_die_id(&odi); | ||
| 117 | 129 | ||
| 118 | pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", | 130 | pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", |
| 119 | idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); | 131 | idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); |
| 120 | pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", | 132 | pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); |
| 121 | read_tap_reg(OMAP_TAP_DIE_ID_0)); | ||
| 122 | pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", | 133 | pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", |
| 123 | read_tap_reg(OMAP_TAP_DIE_ID_1), | 134 | odi.id_1, (odi.id_1 >> 28) & 0xf); |
| 124 | (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf); | 135 | pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); |
| 125 | pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", | 136 | pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); |
| 126 | read_tap_reg(OMAP_TAP_DIE_ID_2)); | ||
| 127 | pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", | ||
| 128 | read_tap_reg(OMAP_TAP_DIE_ID_3)); | ||
| 129 | pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", | 137 | pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", |
| 130 | prod_id, dev_type); | 138 | prod_id, dev_type); |
| 131 | 139 | ||
| @@ -164,7 +172,7 @@ void __init omap24xx_check_revision(void) | |||
| 164 | omap3_features |= OMAP3_HAS_ ##feat; \ | 172 | omap3_features |= OMAP3_HAS_ ##feat; \ |
| 165 | } | 173 | } |
| 166 | 174 | ||
| 167 | void __init omap3_check_features(void) | 175 | static void __init omap3_check_features(void) |
| 168 | { | 176 | { |
| 169 | u32 status; | 177 | u32 status; |
| 170 | 178 | ||
| @@ -179,6 +187,8 @@ void __init omap3_check_features(void) | |||
| 179 | OMAP3_CHECK_FEATURE(status, ISP); | 187 | OMAP3_CHECK_FEATURE(status, ISP); |
| 180 | if (cpu_is_omap3630()) | 188 | if (cpu_is_omap3630()) |
| 181 | omap3_features |= OMAP3_HAS_192MHZ_CLK; | 189 | omap3_features |= OMAP3_HAS_192MHZ_CLK; |
| 190 | if (!cpu_is_omap3505() && !cpu_is_omap3517()) | ||
| 191 | omap3_features |= OMAP3_HAS_IO_WAKEUP; | ||
| 182 | 192 | ||
| 183 | /* | 193 | /* |
| 184 | * TODO: Get additional info (where applicable) | 194 | * TODO: Get additional info (where applicable) |
| @@ -186,7 +196,7 @@ void __init omap3_check_features(void) | |||
| 186 | */ | 196 | */ |
| 187 | } | 197 | } |
| 188 | 198 | ||
| 189 | void __init omap3_check_revision(void) | 199 | static void __init omap3_check_revision(void) |
| 190 | { | 200 | { |
| 191 | u32 cpuid, idcode; | 201 | u32 cpuid, idcode; |
| 192 | u16 hawkeye; | 202 | u16 hawkeye; |
| @@ -259,15 +269,31 @@ void __init omap3_check_revision(void) | |||
| 259 | omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; | 269 | omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; |
| 260 | break; | 270 | break; |
| 261 | case 0xb891: | 271 | case 0xb891: |
| 262 | /* FALLTHROUGH */ | 272 | /* Handle 36xx devices */ |
| 273 | omap_chip.oc |= CHIP_IS_OMAP3630ES1; | ||
| 274 | |||
| 275 | switch(rev) { | ||
| 276 | case 0: /* Take care of early samples */ | ||
| 277 | omap_revision = OMAP3630_REV_ES1_0; | ||
| 278 | break; | ||
| 279 | case 1: | ||
| 280 | omap_revision = OMAP3630_REV_ES1_1; | ||
| 281 | omap_chip.oc |= CHIP_IS_OMAP3630ES1_1; | ||
| 282 | break; | ||
| 283 | case 2: | ||
| 284 | default: | ||
| 285 | omap_revision = OMAP3630_REV_ES1_2; | ||
| 286 | omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; | ||
| 287 | break; | ||
| 288 | } | ||
| 263 | default: | 289 | default: |
| 264 | /* Unknown default to latest silicon rev as default*/ | 290 | /* Unknown default to latest silicon rev as default*/ |
| 265 | omap_revision = OMAP3630_REV_ES1_0; | 291 | omap_revision = OMAP3630_REV_ES1_2; |
| 266 | omap_chip.oc |= CHIP_IS_OMAP3630ES1; | 292 | omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; |
| 267 | } | 293 | } |
| 268 | } | 294 | } |
| 269 | 295 | ||
| 270 | void __init omap4_check_revision(void) | 296 | static void __init omap4_check_revision(void) |
| 271 | { | 297 | { |
| 272 | u32 idcode; | 298 | u32 idcode; |
| 273 | u16 hawkeye; | 299 | u16 hawkeye; |
| @@ -297,7 +323,7 @@ void __init omap4_check_revision(void) | |||
| 297 | if (omap3_has_ ##feat()) \ | 323 | if (omap3_has_ ##feat()) \ |
| 298 | printk(#feat" "); | 324 | printk(#feat" "); |
| 299 | 325 | ||
| 300 | void __init omap3_cpuinfo(void) | 326 | static void __init omap3_cpuinfo(void) |
| 301 | { | 327 | { |
| 302 | u8 rev = GET_OMAP_REVISION(); | 328 | u8 rev = GET_OMAP_REVISION(); |
| 303 | char cpu_name[16], cpu_rev[16]; | 329 | char cpu_name[16], cpu_rev[16]; |
| @@ -339,6 +365,12 @@ void __init omap3_cpuinfo(void) | |||
| 339 | case OMAP_REVBITS_00: | 365 | case OMAP_REVBITS_00: |
| 340 | strcpy(cpu_rev, "1.0"); | 366 | strcpy(cpu_rev, "1.0"); |
| 341 | break; | 367 | break; |
| 368 | case OMAP_REVBITS_01: | ||
| 369 | strcpy(cpu_rev, "1.1"); | ||
| 370 | break; | ||
| 371 | case OMAP_REVBITS_02: | ||
| 372 | strcpy(cpu_rev, "1.2"); | ||
| 373 | break; | ||
| 342 | case OMAP_REVBITS_10: | 374 | case OMAP_REVBITS_10: |
| 343 | strcpy(cpu_rev, "2.0"); | 375 | strcpy(cpu_rev, "2.0"); |
| 344 | break; | 376 | break; |
diff --git a/arch/arm/mach-omap2/include/mach/board-sdp.h b/arch/arm/mach-omap2/include/mach/board-flash.h index 465169c0908a..b2242ae2bb6f 100644 --- a/arch/arm/mach-omap2/include/mach/board-sdp.h +++ b/arch/arm/mach-omap2/include/mach/board-flash.h | |||
| @@ -12,10 +12,17 @@ | |||
| 12 | */ | 12 | */ |
| 13 | #include <linux/mtd/mtd.h> | 13 | #include <linux/mtd/mtd.h> |
| 14 | #include <linux/mtd/partitions.h> | 14 | #include <linux/mtd/partitions.h> |
| 15 | #include <plat/gpmc.h> | ||
| 16 | |||
| 17 | #define PDC_NOR 1 | ||
| 18 | #define PDC_NAND 2 | ||
| 19 | #define PDC_ONENAND 3 | ||
| 20 | #define DBG_MPDB 4 | ||
| 15 | 21 | ||
| 16 | struct flash_partitions { | 22 | struct flash_partitions { |
| 17 | struct mtd_partition *parts; | 23 | struct mtd_partition *parts; |
| 18 | int nr_parts; | 24 | int nr_parts; |
| 19 | }; | 25 | }; |
| 20 | 26 | ||
| 21 | extern void sdp_flash_init(struct flash_partitions []); | 27 | extern void board_flash_init(struct flash_partitions [], |
| 28 | char chip_sel[][GPMC_CS_NUM]); | ||
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h index c93b29e21b78..3af69d2c3dcd 100644 --- a/arch/arm/mach-omap2/include/mach/board-zoom.h +++ b/arch/arm/mach-omap2/include/mach/board-zoom.h | |||
| @@ -1,5 +1,11 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Defines for zoom boards | 2 | * Defines for zoom boards |
| 3 | */ | 3 | */ |
| 4 | #include <linux/mtd/mtd.h> | ||
| 5 | #include <linux/mtd/partitions.h> | ||
| 6 | |||
| 7 | #define ZOOM_NAND_CS 0 | ||
| 8 | |||
| 9 | extern void __init board_nand_init(struct mtd_partition *, u8 nr_parts, u8 cs); | ||
| 4 | extern int __init zoom_debugboard_init(void); | 10 | extern int __init zoom_debugboard_init(void); |
| 5 | extern void __init zoom_peripherals_init(void); | 11 | extern void __init zoom_peripherals_init(void); |
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index 35b24409a0c8..09331bbbda52 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S | |||
| @@ -36,7 +36,7 @@ omap_uart_lsr: .word 0 | |||
| 36 | /* Use omap_uart_phys/virt if already configured */ | 36 | /* Use omap_uart_phys/virt if already configured */ |
| 37 | 10: mrc p15, 0, \rx, c1, c0 | 37 | 10: mrc p15, 0, \rx, c1, c0 |
| 38 | tst \rx, #1 @ MMU enabled? | 38 | tst \rx, #1 @ MMU enabled? |
| 39 | ldreq \rx, =omap_uart_phys @ physical base address | 39 | ldreq \rx, =__virt_to_phys(omap_uart_phys) @ physical base address |
| 40 | ldrne \rx, =omap_uart_virt @ virtual base address | 40 | ldrne \rx, =omap_uart_virt @ virtual base address |
| 41 | ldr \rx, [\rx, #0] | 41 | ldr \rx, [\rx, #0] |
| 42 | cmp \rx, #0 @ is port configured? | 42 | cmp \rx, #0 @ is port configured? |
| @@ -89,26 +89,36 @@ omap_uart_lsr: .word 0 | |||
| 89 | 44: mov \rx, #UART_OFFSET(OMAP4_UART4_BASE) | 89 | 44: mov \rx, #UART_OFFSET(OMAP4_UART4_BASE) |
| 90 | b 98f | 90 | b 98f |
| 91 | 95: ldr \rx, =ZOOM_UART_BASE | 91 | 95: ldr \rx, =ZOOM_UART_BASE |
| 92 | ldr \tmp, =omap_uart_phys | 92 | mrc p15, 0, \tmp, c1, c0 |
| 93 | tst \tmp, #1 @ MMU enabled? | ||
| 94 | ldreq \tmp, =__virt_to_phys(omap_uart_phys) | ||
| 95 | ldrne \tmp, =omap_uart_phys | ||
| 93 | str \rx, [\tmp, #0] | 96 | str \rx, [\tmp, #0] |
| 94 | ldr \rx, =ZOOM_UART_VIRT | 97 | ldr \rx, =ZOOM_UART_VIRT |
| 95 | ldr \tmp, =omap_uart_virt | 98 | ldreq \tmp, =__virt_to_phys(omap_uart_virt) |
| 99 | ldrne \tmp, =omap_uart_virt | ||
| 96 | str \rx, [\tmp, #0] | 100 | str \rx, [\tmp, #0] |
| 97 | mov \rx, #(UART_LSR << ZOOM_PORT_SHIFT) | 101 | mov \rx, #(UART_LSR << ZOOM_PORT_SHIFT) |
| 98 | ldr \tmp, =omap_uart_lsr | 102 | ldreq \tmp, =__virt_to_phys(omap_uart_lsr) |
| 103 | ldrne \tmp, =omap_uart_lsr | ||
| 99 | str \rx, [\tmp, #0] | 104 | str \rx, [\tmp, #0] |
| 100 | b 10b | 105 | b 10b |
| 101 | 106 | ||
| 102 | /* Store both phys and virt address for the uart */ | 107 | /* Store both phys and virt address for the uart */ |
| 103 | 98: add \rx, \rx, #0x48000000 @ phys base | 108 | 98: add \rx, \rx, #0x48000000 @ phys base |
| 104 | ldr \tmp, =omap_uart_phys | 109 | mrc p15, 0, \tmp, c1, c0 |
| 110 | tst \tmp, #1 @ MMU enabled? | ||
| 111 | ldreq \tmp, =__virt_to_phys(omap_uart_phys) | ||
| 112 | ldrne \tmp, =omap_uart_phys | ||
| 105 | str \rx, [\tmp, #0] | 113 | str \rx, [\tmp, #0] |
| 106 | sub \rx, \rx, #0x48000000 @ phys base | 114 | sub \rx, \rx, #0x48000000 @ phys base |
| 107 | add \rx, \rx, #0xfa000000 @ virt base | 115 | add \rx, \rx, #0xfa000000 @ virt base |
| 108 | ldr \tmp, =omap_uart_virt | 116 | ldreq \tmp, =__virt_to_phys(omap_uart_virt) |
| 117 | ldrne \tmp, =omap_uart_virt | ||
| 109 | str \rx, [\tmp, #0] | 118 | str \rx, [\tmp, #0] |
| 110 | mov \rx, #(UART_LSR << OMAP_PORT_SHIFT) | 119 | mov \rx, #(UART_LSR << OMAP_PORT_SHIFT) |
| 111 | ldr \tmp, =omap_uart_lsr | 120 | ldreq \tmp, =__virt_to_phys(omap_uart_lsr) |
| 121 | ldrne \tmp, =omap_uart_lsr | ||
| 112 | str \rx, [\tmp, #0] | 122 | str \rx, [\tmp, #0] |
| 113 | 123 | ||
| 114 | b 10b | 124 | b 10b |
| @@ -120,7 +130,10 @@ omap_uart_lsr: .word 0 | |||
| 120 | .endm | 130 | .endm |
| 121 | 131 | ||
| 122 | .macro busyuart,rd,rx | 132 | .macro busyuart,rd,rx |
| 123 | 1001: ldr \rd, =omap_uart_lsr | 133 | 1001: mrc p15, 0, \rd, c1, c0 |
| 134 | tst \rd, #1 @ MMU enabled? | ||
| 135 | ldreq \rd, =__virt_to_phys(omap_uart_lsr) | ||
| 136 | ldrne \rd, =omap_uart_lsr | ||
| 124 | ldr \rd, [\rd, #0] | 137 | ldr \rd, [\rd, #0] |
| 125 | ldrb \rd, [\rx, \rd] | 138 | ldrb \rd, [\rx, \rd] |
| 126 | and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE) | 139 | and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE) |
diff --git a/arch/arm/mach-omap2/include/mach/id.h b/arch/arm/mach-omap2/include/mach/id.h new file mode 100644 index 000000000000..02ed3aa56f1e --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/id.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2 CPU identification code | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Kan-Ru Chen <kanru@0xlab.org> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #ifndef OMAP2_ARCH_ID_H | ||
| 11 | #define OMAP2_ARCH_ID_H | ||
| 12 | |||
| 13 | struct omap_die_id { | ||
| 14 | u32 id_0; | ||
| 15 | u32 id_1; | ||
| 16 | u32 id_2; | ||
| 17 | u32 id_3; | ||
| 18 | }; | ||
| 19 | |||
| 20 | void omap_get_die_id(struct omap_die_id *odi); | ||
| 21 | |||
| 22 | #endif | ||
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h index 423af3a6dd31..2744dfee1ff4 100644 --- a/arch/arm/mach-omap2/include/mach/omap4-common.h +++ b/arch/arm/mach-omap2/include/mach/omap4-common.h | |||
| @@ -13,6 +13,13 @@ | |||
| 13 | #ifndef OMAP_ARCH_OMAP4_COMMON_H | 13 | #ifndef OMAP_ARCH_OMAP4_COMMON_H |
| 14 | #define OMAP_ARCH_OMAP4_COMMON_H | 14 | #define OMAP_ARCH_OMAP4_COMMON_H |
| 15 | 15 | ||
| 16 | /* | ||
| 17 | * wfi used in low power code. Directly opcode is used instead | ||
| 18 | * of instruction to avoid mulit-omap build break | ||
| 19 | */ | ||
| 20 | #define do_wfi() \ | ||
| 21 | __asm__ __volatile__ (".word 0xe320f003" : : : "memory") | ||
| 22 | |||
| 16 | #ifdef CONFIG_CACHE_L2X0 | 23 | #ifdef CONFIG_CACHE_L2X0 |
| 17 | extern void __iomem *l2cache_base; | 24 | extern void __iomem *l2cache_base; |
| 18 | #endif | 25 | #endif |
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 4e1f53d0b880..b9ea70bce563 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
| @@ -28,7 +28,6 @@ | |||
| 28 | 28 | ||
| 29 | #include <asm/mach/map.h> | 29 | #include <asm/mach/map.h> |
| 30 | 30 | ||
| 31 | #include <plat/mux.h> | ||
| 32 | #include <plat/sram.h> | 31 | #include <plat/sram.h> |
| 33 | #include <plat/sdrc.h> | 32 | #include <plat/sdrc.h> |
| 34 | #include <plat/gpmc.h> | 33 | #include <plat/gpmc.h> |
| @@ -44,6 +43,7 @@ | |||
| 44 | 43 | ||
| 45 | #include <plat/clockdomain.h> | 44 | #include <plat/clockdomain.h> |
| 46 | #include "clockdomains.h" | 45 | #include "clockdomains.h" |
| 46 | |||
| 47 | #include <plat/omap_hwmod.h> | 47 | #include <plat/omap_hwmod.h> |
| 48 | 48 | ||
| 49 | /* | 49 | /* |
| @@ -313,6 +313,8 @@ static int __init _omap2_init_reprogram_sdrc(void) | |||
| 313 | void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, | 313 | void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, |
| 314 | struct omap_sdrc_params *sdrc_cs1) | 314 | struct omap_sdrc_params *sdrc_cs1) |
| 315 | { | 315 | { |
| 316 | u8 skip_setup_idle = 0; | ||
| 317 | |||
| 316 | pwrdm_init(powerdomains_omap); | 318 | pwrdm_init(powerdomains_omap); |
| 317 | clkdm_init(clockdomains_omap, clkdm_autodeps); | 319 | clkdm_init(clockdomains_omap, clkdm_autodeps); |
| 318 | if (cpu_is_omap242x()) | 320 | if (cpu_is_omap242x()) |
| @@ -321,7 +323,6 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, | |||
| 321 | omap2430_hwmod_init(); | 323 | omap2430_hwmod_init(); |
| 322 | else if (cpu_is_omap34xx()) | 324 | else if (cpu_is_omap34xx()) |
| 323 | omap3xxx_hwmod_init(); | 325 | omap3xxx_hwmod_init(); |
| 324 | omap2_mux_init(); | ||
| 325 | /* The OPP tables have to be registered before a clk init */ | 326 | /* The OPP tables have to be registered before a clk init */ |
| 326 | omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); | 327 | omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); |
| 327 | 328 | ||
| @@ -337,9 +338,13 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, | |||
| 337 | pr_err("Could not init clock framework - unknown CPU\n"); | 338 | pr_err("Could not init clock framework - unknown CPU\n"); |
| 338 | 339 | ||
| 339 | omap_serial_early_init(); | 340 | omap_serial_early_init(); |
| 341 | |||
| 342 | #ifndef CONFIG_PM_RUNTIME | ||
| 343 | skip_setup_idle = 1; | ||
| 344 | #endif | ||
| 340 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */ | 345 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */ |
| 341 | omap_hwmod_late_init(); | 346 | omap_hwmod_late_init(skip_setup_idle); |
| 342 | omap_pm_if_init(); | 347 | |
| 343 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | 348 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
| 344 | omap2_sdrc_init(sdrc_cs0, sdrc_cs1); | 349 | omap2_sdrc_init(sdrc_cs0, sdrc_cs1); |
| 345 | _omap2_init_reprogram_sdrc(); | 350 | _omap2_init_reprogram_sdrc(); |
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c index e82da680d908..14ee686b6492 100644 --- a/arch/arm/mach-omap2/iommu2.c +++ b/arch/arm/mach-omap2/iommu2.c | |||
| @@ -44,9 +44,13 @@ | |||
| 44 | #define MMU_IRQ_EMUMISS (1 << 2) | 44 | #define MMU_IRQ_EMUMISS (1 << 2) |
| 45 | #define MMU_IRQ_TRANSLATIONFAULT (1 << 1) | 45 | #define MMU_IRQ_TRANSLATIONFAULT (1 << 1) |
| 46 | #define MMU_IRQ_TLBMISS (1 << 0) | 46 | #define MMU_IRQ_TLBMISS (1 << 0) |
| 47 | #define MMU_IRQ_MASK \ | 47 | |
| 48 | (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \ | 48 | #define __MMU_IRQ_FAULT \ |
| 49 | MMU_IRQ_TRANSLATIONFAULT) | 49 | (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT) |
| 50 | #define MMU_IRQ_MASK \ | ||
| 51 | (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS) | ||
| 52 | #define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT) | ||
| 53 | #define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS) | ||
| 50 | 54 | ||
| 51 | /* MMU_CNTL */ | 55 | /* MMU_CNTL */ |
| 52 | #define MMU_CNTL_SHIFT 1 | 56 | #define MMU_CNTL_SHIFT 1 |
| @@ -61,6 +65,26 @@ | |||
| 61 | ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ | 65 | ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ |
| 62 | ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) | 66 | ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) |
| 63 | 67 | ||
| 68 | |||
| 69 | static void __iommu_set_twl(struct iommu *obj, bool on) | ||
| 70 | { | ||
| 71 | u32 l = iommu_read_reg(obj, MMU_CNTL); | ||
| 72 | |||
| 73 | if (on) | ||
| 74 | iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); | ||
| 75 | else | ||
| 76 | iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE); | ||
| 77 | |||
| 78 | l &= ~MMU_CNTL_MASK; | ||
| 79 | if (on) | ||
| 80 | l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); | ||
| 81 | else | ||
| 82 | l |= (MMU_CNTL_MMU_EN); | ||
| 83 | |||
| 84 | iommu_write_reg(obj, l, MMU_CNTL); | ||
| 85 | } | ||
| 86 | |||
| 87 | |||
| 64 | static int omap2_iommu_enable(struct iommu *obj) | 88 | static int omap2_iommu_enable(struct iommu *obj) |
| 65 | { | 89 | { |
| 66 | u32 l, pa; | 90 | u32 l, pa; |
| @@ -96,13 +120,9 @@ static int omap2_iommu_enable(struct iommu *obj) | |||
| 96 | l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE); | 120 | l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE); |
| 97 | iommu_write_reg(obj, l, MMU_SYSCONFIG); | 121 | iommu_write_reg(obj, l, MMU_SYSCONFIG); |
| 98 | 122 | ||
| 99 | iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE); | ||
| 100 | iommu_write_reg(obj, pa, MMU_TTB); | 123 | iommu_write_reg(obj, pa, MMU_TTB); |
| 101 | 124 | ||
| 102 | l = iommu_read_reg(obj, MMU_CNTL); | 125 | __iommu_set_twl(obj, true); |
| 103 | l &= ~MMU_CNTL_MASK; | ||
| 104 | l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); | ||
| 105 | iommu_write_reg(obj, l, MMU_CNTL); | ||
| 106 | 126 | ||
| 107 | return 0; | 127 | return 0; |
| 108 | } | 128 | } |
| @@ -118,6 +138,11 @@ static void omap2_iommu_disable(struct iommu *obj) | |||
| 118 | dev_dbg(obj->dev, "%s is shutting down\n", obj->name); | 138 | dev_dbg(obj->dev, "%s is shutting down\n", obj->name); |
| 119 | } | 139 | } |
| 120 | 140 | ||
| 141 | static void omap2_iommu_set_twl(struct iommu *obj, bool on) | ||
| 142 | { | ||
| 143 | __iommu_set_twl(obj, false); | ||
| 144 | } | ||
| 145 | |||
| 121 | static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) | 146 | static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) |
| 122 | { | 147 | { |
| 123 | int i; | 148 | int i; |
| @@ -147,7 +172,7 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) | |||
| 147 | printk("\n"); | 172 | printk("\n"); |
| 148 | 173 | ||
| 149 | iommu_write_reg(obj, stat, MMU_IRQSTATUS); | 174 | iommu_write_reg(obj, stat, MMU_IRQSTATUS); |
| 150 | omap2_iommu_disable(obj); | 175 | |
| 151 | return stat; | 176 | return stat; |
| 152 | } | 177 | } |
| 153 | 178 | ||
| @@ -300,6 +325,7 @@ static const struct iommu_functions omap2_iommu_ops = { | |||
| 300 | 325 | ||
| 301 | .enable = omap2_iommu_enable, | 326 | .enable = omap2_iommu_enable, |
| 302 | .disable = omap2_iommu_disable, | 327 | .disable = omap2_iommu_disable, |
| 328 | .set_twl = omap2_iommu_set_twl, | ||
| 303 | .fault_isr = omap2_iommu_fault_isr, | 329 | .fault_isr = omap2_iommu_fault_isr, |
| 304 | 330 | ||
| 305 | .tlb_read_cr = omap2_tlb_read_cr, | 331 | .tlb_read_cr = omap2_tlb_read_cr, |
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 318f3638653c..42dbfa46e656 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c | |||
| @@ -10,7 +10,6 @@ | |||
| 10 | * for more details. | 10 | * for more details. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/clk.h> | 13 | #include <linux/clk.h> |
| 15 | #include <linux/err.h> | 14 | #include <linux/err.h> |
| 16 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
| @@ -18,8 +17,6 @@ | |||
| 18 | #include <plat/mailbox.h> | 17 | #include <plat/mailbox.h> |
| 19 | #include <mach/irqs.h> | 18 | #include <mach/irqs.h> |
| 20 | 19 | ||
| 21 | #define DRV_NAME "omap2-mailbox" | ||
| 22 | |||
| 23 | #define MAILBOX_REVISION 0x000 | 20 | #define MAILBOX_REVISION 0x000 |
| 24 | #define MAILBOX_SYSCONFIG 0x010 | 21 | #define MAILBOX_SYSCONFIG 0x010 |
| 25 | #define MAILBOX_SYSSTATUS 0x014 | 22 | #define MAILBOX_SYSSTATUS 0x014 |
| @@ -131,7 +128,7 @@ static int omap2_mbox_startup(struct omap_mbox *mbox) | |||
| 131 | } | 128 | } |
| 132 | 129 | ||
| 133 | l = mbox_read_reg(MAILBOX_REVISION); | 130 | l = mbox_read_reg(MAILBOX_REVISION); |
| 134 | pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); | 131 | pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); |
| 135 | 132 | ||
| 136 | if (cpu_is_omap44xx()) | 133 | if (cpu_is_omap44xx()) |
| 137 | l = OMAP4_SMARTIDLE; | 134 | l = OMAP4_SMARTIDLE; |
| @@ -283,6 +280,8 @@ static struct omap_mbox_ops omap2_mbox_ops = { | |||
| 283 | */ | 280 | */ |
| 284 | 281 | ||
| 285 | /* FIXME: the following structs should be filled automatically by the user id */ | 282 | /* FIXME: the following structs should be filled automatically by the user id */ |
| 283 | |||
| 284 | #if defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_ARCH_OMAP2420) | ||
| 286 | /* DSP */ | 285 | /* DSP */ |
| 287 | static struct omap_mbox2_priv omap2_mbox_dsp_priv = { | 286 | static struct omap_mbox2_priv omap2_mbox_dsp_priv = { |
| 288 | .tx_fifo = { | 287 | .tx_fifo = { |
| @@ -300,10 +299,46 @@ static struct omap_mbox2_priv omap2_mbox_dsp_priv = { | |||
| 300 | .irqdisable = MAILBOX_IRQENABLE(0), | 299 | .irqdisable = MAILBOX_IRQENABLE(0), |
| 301 | }; | 300 | }; |
| 302 | 301 | ||
| 302 | struct omap_mbox mbox_dsp_info = { | ||
| 303 | .name = "dsp", | ||
| 304 | .ops = &omap2_mbox_ops, | ||
| 305 | .priv = &omap2_mbox_dsp_priv, | ||
| 306 | }; | ||
| 307 | #endif | ||
| 308 | |||
| 309 | #if defined(CONFIG_ARCH_OMAP3430) | ||
| 310 | struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL }; | ||
| 311 | #endif | ||
| 312 | |||
| 313 | #if defined(CONFIG_ARCH_OMAP2420) | ||
| 314 | /* IVA */ | ||
| 315 | static struct omap_mbox2_priv omap2_mbox_iva_priv = { | ||
| 316 | .tx_fifo = { | ||
| 317 | .msg = MAILBOX_MESSAGE(2), | ||
| 318 | .fifo_stat = MAILBOX_FIFOSTATUS(2), | ||
| 319 | }, | ||
| 320 | .rx_fifo = { | ||
| 321 | .msg = MAILBOX_MESSAGE(3), | ||
| 322 | .msg_stat = MAILBOX_MSGSTATUS(3), | ||
| 323 | }, | ||
| 324 | .irqenable = MAILBOX_IRQENABLE(3), | ||
| 325 | .irqstatus = MAILBOX_IRQSTATUS(3), | ||
| 326 | .notfull_bit = MAILBOX_IRQ_NOTFULL(2), | ||
| 327 | .newmsg_bit = MAILBOX_IRQ_NEWMSG(3), | ||
| 328 | .irqdisable = MAILBOX_IRQENABLE(3), | ||
| 329 | }; | ||
| 330 | |||
| 331 | static struct omap_mbox mbox_iva_info = { | ||
| 332 | .name = "iva", | ||
| 333 | .ops = &omap2_mbox_ops, | ||
| 334 | .priv = &omap2_mbox_iva_priv, | ||
| 335 | }; | ||
| 303 | 336 | ||
| 337 | struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL }; | ||
| 338 | #endif | ||
| 304 | 339 | ||
| 305 | /* OMAP4 specific data structure. Use the cpu_is_omap4xxx() | 340 | #if defined(CONFIG_ARCH_OMAP4) |
| 306 | to use this*/ | 341 | /* OMAP4 */ |
| 307 | static struct omap_mbox2_priv omap2_mbox_1_priv = { | 342 | static struct omap_mbox2_priv omap2_mbox_1_priv = { |
| 308 | .tx_fifo = { | 343 | .tx_fifo = { |
| 309 | .msg = MAILBOX_MESSAGE(0), | 344 | .msg = MAILBOX_MESSAGE(0), |
| @@ -325,14 +360,6 @@ struct omap_mbox mbox_1_info = { | |||
| 325 | .ops = &omap2_mbox_ops, | 360 | .ops = &omap2_mbox_ops, |
| 326 | .priv = &omap2_mbox_1_priv, | 361 | .priv = &omap2_mbox_1_priv, |
| 327 | }; | 362 | }; |
| 328 | EXPORT_SYMBOL(mbox_1_info); | ||
| 329 | |||
| 330 | struct omap_mbox mbox_dsp_info = { | ||
| 331 | .name = "dsp", | ||
| 332 | .ops = &omap2_mbox_ops, | ||
| 333 | .priv = &omap2_mbox_dsp_priv, | ||
| 334 | }; | ||
| 335 | EXPORT_SYMBOL(mbox_dsp_info); | ||
| 336 | 363 | ||
| 337 | static struct omap_mbox2_priv omap2_mbox_2_priv = { | 364 | static struct omap_mbox2_priv omap2_mbox_2_priv = { |
| 338 | .tx_fifo = { | 365 | .tx_fifo = { |
| @@ -355,110 +382,64 @@ struct omap_mbox mbox_2_info = { | |||
| 355 | .ops = &omap2_mbox_ops, | 382 | .ops = &omap2_mbox_ops, |
| 356 | .priv = &omap2_mbox_2_priv, | 383 | .priv = &omap2_mbox_2_priv, |
| 357 | }; | 384 | }; |
| 358 | EXPORT_SYMBOL(mbox_2_info); | ||
| 359 | |||
| 360 | |||
| 361 | #if defined(CONFIG_ARCH_OMAP2420) /* IVA */ | ||
| 362 | static struct omap_mbox2_priv omap2_mbox_iva_priv = { | ||
| 363 | .tx_fifo = { | ||
| 364 | .msg = MAILBOX_MESSAGE(2), | ||
| 365 | .fifo_stat = MAILBOX_FIFOSTATUS(2), | ||
| 366 | }, | ||
| 367 | .rx_fifo = { | ||
| 368 | .msg = MAILBOX_MESSAGE(3), | ||
| 369 | .msg_stat = MAILBOX_MSGSTATUS(3), | ||
| 370 | }, | ||
| 371 | .irqenable = MAILBOX_IRQENABLE(3), | ||
| 372 | .irqstatus = MAILBOX_IRQSTATUS(3), | ||
| 373 | .notfull_bit = MAILBOX_IRQ_NOTFULL(2), | ||
| 374 | .newmsg_bit = MAILBOX_IRQ_NEWMSG(3), | ||
| 375 | .irqdisable = MAILBOX_IRQENABLE(3), | ||
| 376 | }; | ||
| 377 | 385 | ||
| 378 | static struct omap_mbox mbox_iva_info = { | 386 | struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL }; |
| 379 | .name = "iva", | ||
| 380 | .ops = &omap2_mbox_ops, | ||
| 381 | .priv = &omap2_mbox_iva_priv, | ||
| 382 | }; | ||
| 383 | #endif | 387 | #endif |
| 384 | 388 | ||
| 385 | static int __devinit omap2_mbox_probe(struct platform_device *pdev) | 389 | static int __devinit omap2_mbox_probe(struct platform_device *pdev) |
| 386 | { | 390 | { |
| 387 | struct resource *res; | 391 | struct resource *mem; |
| 388 | int ret; | 392 | int ret; |
| 393 | struct omap_mbox **list; | ||
| 389 | 394 | ||
| 390 | /* MBOX base */ | 395 | if (false) |
| 391 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 396 | ; |
| 392 | if (unlikely(!res)) { | 397 | #if defined(CONFIG_ARCH_OMAP3430) |
| 393 | dev_err(&pdev->dev, "invalid mem resource\n"); | 398 | else if (cpu_is_omap3430()) { |
| 394 | return -ENODEV; | 399 | list = omap3_mboxes; |
| 400 | |||
| 401 | list[0]->irq = platform_get_irq_byname(pdev, "dsp"); | ||
| 395 | } | 402 | } |
| 396 | mbox_base = ioremap(res->start, resource_size(res)); | 403 | #endif |
| 397 | if (!mbox_base) | 404 | #if defined(CONFIG_ARCH_OMAP2420) |
| 398 | return -ENOMEM; | 405 | else if (cpu_is_omap2420()) { |
| 406 | list = omap2_mboxes; | ||
| 399 | 407 | ||
| 400 | /* DSP or IVA2 IRQ */ | 408 | list[0]->irq = platform_get_irq_byname(pdev, "dsp"); |
| 401 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | 409 | list[1]->irq = platform_get_irq_byname(pdev, "iva"); |
| 410 | } | ||
| 411 | #endif | ||
| 412 | #if defined(CONFIG_ARCH_OMAP4) | ||
| 413 | else if (cpu_is_omap44xx()) { | ||
| 414 | list = omap4_mboxes; | ||
| 402 | 415 | ||
| 403 | if (unlikely(!res)) { | 416 | list[0]->irq = list[1]->irq = |
| 404 | dev_err(&pdev->dev, "invalid irq resource\n"); | 417 | platform_get_irq_byname(pdev, "mbox"); |
| 405 | ret = -ENODEV; | ||
| 406 | goto err_dsp; | ||
| 407 | } | 418 | } |
| 408 | if (cpu_is_omap44xx()) { | 419 | #endif |
| 409 | mbox_1_info.irq = res->start; | 420 | else { |
| 410 | ret = omap_mbox_register(&pdev->dev, &mbox_1_info); | 421 | pr_err("%s: platform not supported\n", __func__); |
| 411 | } else { | 422 | return -ENODEV; |
| 412 | mbox_dsp_info.irq = res->start; | ||
| 413 | ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info); | ||
| 414 | } | 423 | } |
| 415 | if (ret) | ||
| 416 | goto err_dsp; | ||
| 417 | 424 | ||
| 418 | if (cpu_is_omap44xx()) { | 425 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 419 | mbox_2_info.irq = res->start; | 426 | mbox_base = ioremap(mem->start, resource_size(mem)); |
| 420 | ret = omap_mbox_register(&pdev->dev, &mbox_2_info); | 427 | if (!mbox_base) |
| 421 | if (ret) { | 428 | return -ENOMEM; |
| 422 | omap_mbox_unregister(&mbox_1_info); | 429 | |
| 423 | goto err_dsp; | 430 | ret = omap_mbox_register(&pdev->dev, list); |
| 424 | } | 431 | if (ret) { |
| 425 | } | 432 | iounmap(mbox_base); |
| 426 | #if defined(CONFIG_ARCH_OMAP2420) /* IVA */ | 433 | return ret; |
| 427 | if (cpu_is_omap2420()) { | ||
| 428 | /* IVA IRQ */ | ||
| 429 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | ||
| 430 | if (unlikely(!res)) { | ||
| 431 | dev_err(&pdev->dev, "invalid irq resource\n"); | ||
| 432 | ret = -ENODEV; | ||
| 433 | omap_mbox_unregister(&mbox_dsp_info); | ||
| 434 | goto err_dsp; | ||
| 435 | } | ||
| 436 | mbox_iva_info.irq = res->start; | ||
| 437 | ret = omap_mbox_register(&pdev->dev, &mbox_iva_info); | ||
| 438 | if (ret) { | ||
| 439 | omap_mbox_unregister(&mbox_dsp_info); | ||
| 440 | goto err_dsp; | ||
| 441 | } | ||
| 442 | } | 434 | } |
| 443 | #endif | ||
| 444 | return 0; | 435 | return 0; |
| 445 | 436 | ||
| 446 | err_dsp: | ||
| 447 | iounmap(mbox_base); | ||
| 448 | return ret; | 437 | return ret; |
| 449 | } | 438 | } |
| 450 | 439 | ||
| 451 | static int __devexit omap2_mbox_remove(struct platform_device *pdev) | 440 | static int __devexit omap2_mbox_remove(struct platform_device *pdev) |
| 452 | { | 441 | { |
| 453 | #if defined(CONFIG_ARCH_OMAP2420) | 442 | omap_mbox_unregister(); |
| 454 | omap_mbox_unregister(&mbox_iva_info); | ||
| 455 | #endif | ||
| 456 | |||
| 457 | if (cpu_is_omap44xx()) { | ||
| 458 | omap_mbox_unregister(&mbox_2_info); | ||
| 459 | omap_mbox_unregister(&mbox_1_info); | ||
| 460 | } else | ||
| 461 | omap_mbox_unregister(&mbox_dsp_info); | ||
| 462 | iounmap(mbox_base); | 443 | iounmap(mbox_base); |
| 463 | return 0; | 444 | return 0; |
| 464 | } | 445 | } |
| @@ -467,7 +448,7 @@ static struct platform_driver omap2_mbox_driver = { | |||
| 467 | .probe = omap2_mbox_probe, | 448 | .probe = omap2_mbox_probe, |
| 468 | .remove = __devexit_p(omap2_mbox_remove), | 449 | .remove = __devexit_p(omap2_mbox_remove), |
| 469 | .driver = { | 450 | .driver = { |
| 470 | .name = DRV_NAME, | 451 | .name = "omap-mailbox", |
| 471 | }, | 452 | }, |
| 472 | }; | 453 | }; |
| 473 | 454 | ||
| @@ -486,5 +467,6 @@ module_exit(omap2_mbox_exit); | |||
| 486 | 467 | ||
| 487 | MODULE_LICENSE("GPL v2"); | 468 | MODULE_LICENSE("GPL v2"); |
| 488 | MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions"); | 469 | MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions"); |
| 489 | MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt"); | 470 | MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>"); |
| 490 | MODULE_ALIAS("platform:"DRV_NAME); | 471 | MODULE_AUTHOR("Paul Mundt"); |
| 472 | MODULE_ALIAS("platform:omap2-mailbox"); | ||
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 8fb5e5345557..467aae245781 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c | |||
| @@ -20,17 +20,18 @@ | |||
| 20 | 20 | ||
| 21 | #include <mach/irqs.h> | 21 | #include <mach/irqs.h> |
| 22 | #include <plat/dma.h> | 22 | #include <plat/dma.h> |
| 23 | #include <plat/mux.h> | ||
| 24 | #include <plat/cpu.h> | 23 | #include <plat/cpu.h> |
| 25 | #include <plat/mcbsp.h> | 24 | #include <plat/mcbsp.h> |
| 26 | 25 | ||
| 26 | #include "mux.h" | ||
| 27 | |||
| 27 | static void omap2_mcbsp2_mux_setup(void) | 28 | static void omap2_mcbsp2_mux_setup(void) |
| 28 | { | 29 | { |
| 29 | omap_cfg_reg(Y15_24XX_MCBSP2_CLKX); | 30 | omap_mux_init_signal("eac_ac_sclk.mcbsp2_clkx", OMAP_PULL_ENA); |
| 30 | omap_cfg_reg(R14_24XX_MCBSP2_FSX); | 31 | omap_mux_init_signal("eac_ac_fs.mcbsp2_fsx", OMAP_PULL_ENA); |
| 31 | omap_cfg_reg(W15_24XX_MCBSP2_DR); | 32 | omap_mux_init_signal("eac_ac_din.mcbsp2_dr", OMAP_PULL_ENA); |
| 32 | omap_cfg_reg(V15_24XX_MCBSP2_DX); | 33 | omap_mux_init_signal("eac_ac_dout.mcbsp2_dx", OMAP_PULL_ENA); |
| 33 | omap_cfg_reg(V14_24XX_GPIO117); | 34 | omap_mux_init_gpio(117, OMAP_PULL_ENA); |
| 34 | /* | 35 | /* |
| 35 | * TODO: Need to add MUX settings for OMAP 2430 SDP | 36 | * TODO: Need to add MUX settings for OMAP 2430 SDP |
| 36 | */ | 37 | */ |
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 8b3d26935a39..ab403b2ed26b 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c | |||
| @@ -37,12 +37,12 @@ | |||
| 37 | #include <asm/system.h> | 37 | #include <asm/system.h> |
| 38 | 38 | ||
| 39 | #include <plat/control.h> | 39 | #include <plat/control.h> |
| 40 | #include <plat/mux.h> | ||
| 41 | 40 | ||
| 42 | #include "mux.h" | 41 | #include "mux.h" |
| 43 | 42 | ||
| 44 | #define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ | 43 | #define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ |
| 45 | #define OMAP_MUX_BASE_SZ 0x5ca | 44 | #define OMAP_MUX_BASE_SZ 0x5ca |
| 45 | #define MUXABLE_GPIO_MODE3 BIT(0) | ||
| 46 | 46 | ||
| 47 | struct omap_mux_entry { | 47 | struct omap_mux_entry { |
| 48 | struct omap_mux mux; | 48 | struct omap_mux mux; |
| @@ -51,6 +51,7 @@ struct omap_mux_entry { | |||
| 51 | 51 | ||
| 52 | static unsigned long mux_phys; | 52 | static unsigned long mux_phys; |
| 53 | static void __iomem *mux_base; | 53 | static void __iomem *mux_base; |
| 54 | static u8 omap_mux_flags; | ||
| 54 | 55 | ||
| 55 | u16 omap_mux_read(u16 reg) | 56 | u16 omap_mux_read(u16 reg) |
| 56 | { | 57 | { |
| @@ -76,301 +77,6 @@ void omap_mux_write_array(struct omap_board_mux *board_mux) | |||
| 76 | } | 77 | } |
| 77 | } | 78 | } |
| 78 | 79 | ||
| 79 | #if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_OMAP_MUX) | ||
| 80 | |||
| 81 | static struct omap_mux_cfg arch_mux_cfg; | ||
| 82 | |||
| 83 | /* NOTE: See mux.h for the enumeration */ | ||
| 84 | |||
| 85 | static struct pin_config __initdata_or_module omap24xx_pins[] = { | ||
| 86 | /* | ||
| 87 | * description mux mux pull pull debug | ||
| 88 | * offset mode ena type | ||
| 89 | */ | ||
| 90 | |||
| 91 | /* 24xx I2C */ | ||
| 92 | MUX_CFG_24XX("M19_24XX_I2C1_SCL", 0x111, 0, 0, 0, 1) | ||
| 93 | MUX_CFG_24XX("L15_24XX_I2C1_SDA", 0x112, 0, 0, 0, 1) | ||
| 94 | MUX_CFG_24XX("J15_24XX_I2C2_SCL", 0x113, 0, 0, 1, 1) | ||
| 95 | MUX_CFG_24XX("H19_24XX_I2C2_SDA", 0x114, 0, 0, 0, 1) | ||
| 96 | |||
| 97 | /* Menelaus interrupt */ | ||
| 98 | MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1) | ||
| 99 | |||
| 100 | /* 24xx clocks */ | ||
| 101 | MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1) | ||
| 102 | |||
| 103 | /* 24xx GPMC chipselects, wait pin monitoring */ | ||
| 104 | MUX_CFG_24XX("E2_GPMC_NCS2", 0x08e, 0, 1, 1, 1) | ||
| 105 | MUX_CFG_24XX("L2_GPMC_NCS7", 0x093, 0, 1, 1, 1) | ||
| 106 | MUX_CFG_24XX("L3_GPMC_WAIT0", 0x09a, 0, 1, 1, 1) | ||
| 107 | MUX_CFG_24XX("N7_GPMC_WAIT1", 0x09b, 0, 1, 1, 1) | ||
| 108 | MUX_CFG_24XX("M1_GPMC_WAIT2", 0x09c, 0, 1, 1, 1) | ||
| 109 | MUX_CFG_24XX("P1_GPMC_WAIT3", 0x09d, 0, 1, 1, 1) | ||
| 110 | |||
| 111 | /* 24xx McBSP */ | ||
| 112 | MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX", 0x124, 1, 1, 0, 1) | ||
| 113 | MUX_CFG_24XX("R14_24XX_MCBSP2_FSX", 0x125, 1, 1, 0, 1) | ||
| 114 | MUX_CFG_24XX("W15_24XX_MCBSP2_DR", 0x126, 1, 1, 0, 1) | ||
| 115 | MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1) | ||
| 116 | |||
| 117 | /* 24xx GPIO */ | ||
| 118 | MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1) | ||
| 119 | MUX_CFG_24XX("P21_242X_GPIO12", 0x0ca, 3, 0, 0, 1) | ||
| 120 | MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1) | ||
| 121 | MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1) | ||
| 122 | MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1) | ||
| 123 | MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1) | ||
| 124 | MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1) | ||
| 125 | MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1) | ||
| 126 | MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1) | ||
| 127 | MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) | ||
| 128 | MUX_CFG_24XX("N15_24XX_GPIO85", 0x103, 3, 0, 0, 1) | ||
| 129 | MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1) | ||
| 130 | MUX_CFG_24XX("P20_24XX_GPIO93", 0x10b, 3, 0, 0, 1) | ||
| 131 | MUX_CFG_24XX("P18_24XX_GPIO95", 0x10d, 3, 0, 0, 1) | ||
| 132 | MUX_CFG_24XX("M18_24XX_GPIO96", 0x10e, 3, 0, 0, 1) | ||
| 133 | MUX_CFG_24XX("L14_24XX_GPIO97", 0x10f, 3, 0, 0, 1) | ||
| 134 | MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1) | ||
| 135 | MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1) | ||
| 136 | MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1) | ||
| 137 | |||
| 138 | /* 242x DBG GPIO */ | ||
| 139 | MUX_CFG_24XX("V4_242X_GPIO49", 0xd3, 3, 0, 0, 1) | ||
| 140 | MUX_CFG_24XX("W2_242X_GPIO50", 0xd4, 3, 0, 0, 1) | ||
| 141 | MUX_CFG_24XX("U4_242X_GPIO51", 0xd5, 3, 0, 0, 1) | ||
| 142 | MUX_CFG_24XX("V3_242X_GPIO52", 0xd6, 3, 0, 0, 1) | ||
| 143 | MUX_CFG_24XX("V2_242X_GPIO53", 0xd7, 3, 0, 0, 1) | ||
| 144 | MUX_CFG_24XX("V6_242X_GPIO53", 0xcf, 3, 0, 0, 1) | ||
| 145 | MUX_CFG_24XX("T4_242X_GPIO54", 0xd8, 3, 0, 0, 1) | ||
| 146 | MUX_CFG_24XX("Y4_242X_GPIO54", 0xd0, 3, 0, 0, 1) | ||
| 147 | MUX_CFG_24XX("T3_242X_GPIO55", 0xd9, 3, 0, 0, 1) | ||
| 148 | MUX_CFG_24XX("U2_242X_GPIO56", 0xda, 3, 0, 0, 1) | ||
| 149 | |||
| 150 | /* 24xx external DMA requests */ | ||
| 151 | MUX_CFG_24XX("AA10_242X_DMAREQ0", 0x0e5, 2, 0, 0, 1) | ||
| 152 | MUX_CFG_24XX("AA6_242X_DMAREQ1", 0x0e6, 2, 0, 0, 1) | ||
| 153 | MUX_CFG_24XX("E4_242X_DMAREQ2", 0x074, 2, 0, 0, 1) | ||
| 154 | MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1) | ||
| 155 | MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1) | ||
| 156 | MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1) | ||
| 157 | |||
| 158 | /* UART3 */ | ||
| 159 | MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1) | ||
| 160 | MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1) | ||
| 161 | |||
| 162 | /* MMC/SDIO */ | ||
| 163 | MUX_CFG_24XX("G19_24XX_MMC_CLKO", 0x0f3, 0, 0, 0, 1) | ||
| 164 | MUX_CFG_24XX("H18_24XX_MMC_CMD", 0x0f4, 0, 0, 0, 1) | ||
| 165 | MUX_CFG_24XX("F20_24XX_MMC_DAT0", 0x0f5, 0, 0, 0, 1) | ||
| 166 | MUX_CFG_24XX("H14_24XX_MMC_DAT1", 0x0f6, 0, 0, 0, 1) | ||
| 167 | MUX_CFG_24XX("E19_24XX_MMC_DAT2", 0x0f7, 0, 0, 0, 1) | ||
| 168 | MUX_CFG_24XX("D19_24XX_MMC_DAT3", 0x0f8, 0, 0, 0, 1) | ||
| 169 | MUX_CFG_24XX("F19_24XX_MMC_DAT_DIR0", 0x0f9, 0, 0, 0, 1) | ||
| 170 | MUX_CFG_24XX("E20_24XX_MMC_DAT_DIR1", 0x0fa, 0, 0, 0, 1) | ||
| 171 | MUX_CFG_24XX("F18_24XX_MMC_DAT_DIR2", 0x0fb, 0, 0, 0, 1) | ||
| 172 | MUX_CFG_24XX("E18_24XX_MMC_DAT_DIR3", 0x0fc, 0, 0, 0, 1) | ||
| 173 | MUX_CFG_24XX("G18_24XX_MMC_CMD_DIR", 0x0fd, 0, 0, 0, 1) | ||
| 174 | MUX_CFG_24XX("H15_24XX_MMC_CLKI", 0x0fe, 0, 0, 0, 1) | ||
| 175 | |||
| 176 | /* Full speed USB */ | ||
| 177 | MUX_CFG_24XX("J20_24XX_USB0_PUEN", 0x11d, 0, 0, 0, 1) | ||
| 178 | MUX_CFG_24XX("J19_24XX_USB0_VP", 0x11e, 0, 0, 0, 1) | ||
| 179 | MUX_CFG_24XX("K20_24XX_USB0_VM", 0x11f, 0, 0, 0, 1) | ||
| 180 | MUX_CFG_24XX("J18_24XX_USB0_RCV", 0x120, 0, 0, 0, 1) | ||
| 181 | MUX_CFG_24XX("K19_24XX_USB0_TXEN", 0x121, 0, 0, 0, 1) | ||
| 182 | MUX_CFG_24XX("J14_24XX_USB0_SE0", 0x122, 0, 0, 0, 1) | ||
| 183 | MUX_CFG_24XX("K18_24XX_USB0_DAT", 0x123, 0, 0, 0, 1) | ||
| 184 | |||
| 185 | MUX_CFG_24XX("N14_24XX_USB1_SE0", 0x0ed, 2, 0, 0, 1) | ||
| 186 | MUX_CFG_24XX("W12_24XX_USB1_SE0", 0x0dd, 3, 0, 0, 1) | ||
| 187 | MUX_CFG_24XX("P15_24XX_USB1_DAT", 0x0ee, 2, 0, 0, 1) | ||
| 188 | MUX_CFG_24XX("R13_24XX_USB1_DAT", 0x0e0, 3, 0, 0, 1) | ||
| 189 | MUX_CFG_24XX("W20_24XX_USB1_TXEN", 0x0ec, 2, 0, 0, 1) | ||
| 190 | MUX_CFG_24XX("P13_24XX_USB1_TXEN", 0x0df, 3, 0, 0, 1) | ||
| 191 | MUX_CFG_24XX("V19_24XX_USB1_RCV", 0x0eb, 2, 0, 0, 1) | ||
| 192 | MUX_CFG_24XX("V12_24XX_USB1_RCV", 0x0de, 3, 0, 0, 1) | ||
| 193 | |||
| 194 | MUX_CFG_24XX("AA10_24XX_USB2_SE0", 0x0e5, 2, 0, 0, 1) | ||
| 195 | MUX_CFG_24XX("Y11_24XX_USB2_DAT", 0x0e8, 2, 0, 0, 1) | ||
| 196 | MUX_CFG_24XX("AA12_24XX_USB2_TXEN", 0x0e9, 2, 0, 0, 1) | ||
| 197 | MUX_CFG_24XX("AA6_24XX_USB2_RCV", 0x0e6, 2, 0, 0, 1) | ||
| 198 | MUX_CFG_24XX("AA4_24XX_USB2_TLLSE0", 0x0e7, 2, 0, 0, 1) | ||
| 199 | |||
| 200 | /* Keypad GPIO*/ | ||
| 201 | MUX_CFG_24XX("T19_24XX_KBR0", 0x106, 3, 1, 1, 1) | ||
| 202 | MUX_CFG_24XX("R19_24XX_KBR1", 0x107, 3, 1, 1, 1) | ||
| 203 | MUX_CFG_24XX("V18_24XX_KBR2", 0x139, 3, 1, 1, 1) | ||
| 204 | MUX_CFG_24XX("M21_24XX_KBR3", 0xc9, 3, 1, 1, 1) | ||
| 205 | MUX_CFG_24XX("E5__24XX_KBR4", 0x138, 3, 1, 1, 1) | ||
| 206 | MUX_CFG_24XX("M18_24XX_KBR5", 0x10e, 3, 1, 1, 1) | ||
| 207 | MUX_CFG_24XX("R20_24XX_KBC0", 0x108, 3, 0, 0, 1) | ||
| 208 | MUX_CFG_24XX("M14_24XX_KBC1", 0x109, 3, 0, 0, 1) | ||
| 209 | MUX_CFG_24XX("H19_24XX_KBC2", 0x114, 3, 0, 0, 1) | ||
| 210 | MUX_CFG_24XX("V17_24XX_KBC3", 0x135, 3, 0, 0, 1) | ||
| 211 | MUX_CFG_24XX("P21_24XX_KBC4", 0xca, 3, 0, 0, 1) | ||
| 212 | MUX_CFG_24XX("L14_24XX_KBC5", 0x10f, 3, 0, 0, 1) | ||
| 213 | MUX_CFG_24XX("N19_24XX_KBC6", 0x110, 3, 0, 0, 1) | ||
| 214 | |||
| 215 | /* 24xx Menelaus Keypad GPIO */ | ||
| 216 | MUX_CFG_24XX("B3__24XX_KBR5", 0x30, 3, 1, 1, 1) | ||
| 217 | MUX_CFG_24XX("AA4_24XX_KBC2", 0xe7, 3, 0, 0, 1) | ||
| 218 | MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1) | ||
| 219 | |||
| 220 | /* 2430 USB */ | ||
| 221 | MUX_CFG_24XX("AD9_2430_USB0_PUEN", 0x133, 4, 0, 0, 1) | ||
| 222 | MUX_CFG_24XX("Y11_2430_USB0_VP", 0x134, 4, 0, 0, 1) | ||
| 223 | MUX_CFG_24XX("AD7_2430_USB0_VM", 0x135, 4, 0, 0, 1) | ||
| 224 | MUX_CFG_24XX("AE7_2430_USB0_RCV", 0x136, 4, 0, 0, 1) | ||
| 225 | MUX_CFG_24XX("AD4_2430_USB0_TXEN", 0x137, 4, 0, 0, 1) | ||
| 226 | MUX_CFG_24XX("AF9_2430_USB0_SE0", 0x138, 4, 0, 0, 1) | ||
| 227 | MUX_CFG_24XX("AE6_2430_USB0_DAT", 0x139, 4, 0, 0, 1) | ||
| 228 | MUX_CFG_24XX("AD24_2430_USB1_SE0", 0x107, 2, 0, 0, 1) | ||
| 229 | MUX_CFG_24XX("AB24_2430_USB1_RCV", 0x108, 2, 0, 0, 1) | ||
| 230 | MUX_CFG_24XX("Y25_2430_USB1_TXEN", 0x109, 2, 0, 0, 1) | ||
| 231 | MUX_CFG_24XX("AA26_2430_USB1_DAT", 0x10A, 2, 0, 0, 1) | ||
| 232 | |||
| 233 | /* 2430 HS-USB */ | ||
| 234 | MUX_CFG_24XX("AD9_2430_USB0HS_DATA3", 0x133, 0, 0, 0, 1) | ||
| 235 | MUX_CFG_24XX("Y11_2430_USB0HS_DATA4", 0x134, 0, 0, 0, 1) | ||
| 236 | MUX_CFG_24XX("AD7_2430_USB0HS_DATA5", 0x135, 0, 0, 0, 1) | ||
| 237 | MUX_CFG_24XX("AE7_2430_USB0HS_DATA6", 0x136, 0, 0, 0, 1) | ||
| 238 | MUX_CFG_24XX("AD4_2430_USB0HS_DATA2", 0x137, 0, 0, 0, 1) | ||
| 239 | MUX_CFG_24XX("AF9_2430_USB0HS_DATA0", 0x138, 0, 0, 0, 1) | ||
| 240 | MUX_CFG_24XX("AE6_2430_USB0HS_DATA1", 0x139, 0, 0, 0, 1) | ||
| 241 | MUX_CFG_24XX("AE8_2430_USB0HS_CLK", 0x13A, 0, 0, 0, 1) | ||
| 242 | MUX_CFG_24XX("AD8_2430_USB0HS_DIR", 0x13B, 0, 0, 0, 1) | ||
| 243 | MUX_CFG_24XX("AE5_2430_USB0HS_STP", 0x13c, 0, 1, 1, 1) | ||
| 244 | MUX_CFG_24XX("AE9_2430_USB0HS_NXT", 0x13D, 0, 0, 0, 1) | ||
| 245 | MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1) | ||
| 246 | |||
| 247 | /* 2430 McBSP */ | ||
| 248 | MUX_CFG_24XX("AD6_2430_MCBSP_CLKS", 0x011E, 0, 0, 0, 1) | ||
| 249 | |||
| 250 | MUX_CFG_24XX("AB2_2430_MCBSP1_CLKR", 0x011A, 0, 0, 0, 1) | ||
| 251 | MUX_CFG_24XX("AD5_2430_MCBSP1_FSR", 0x011B, 0, 0, 0, 1) | ||
| 252 | MUX_CFG_24XX("AA1_2430_MCBSP1_DX", 0x011C, 0, 0, 0, 1) | ||
| 253 | MUX_CFG_24XX("AF3_2430_MCBSP1_DR", 0x011D, 0, 0, 0, 1) | ||
| 254 | MUX_CFG_24XX("AB3_2430_MCBSP1_FSX", 0x011F, 0, 0, 0, 1) | ||
| 255 | MUX_CFG_24XX("Y9_2430_MCBSP1_CLKX", 0x0120, 0, 0, 0, 1) | ||
| 256 | |||
| 257 | MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1) | ||
| 258 | MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1) | ||
| 259 | MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1) | ||
| 260 | MUX_CFG_24XX("AD13_2430_MCBSP2_DR", 0x0131, 1, 0, 0, 1) | ||
| 261 | MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0, 0, 0, 1) | ||
| 262 | MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1) | ||
| 263 | MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1) | ||
| 264 | MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1) | ||
| 265 | |||
| 266 | MUX_CFG_24XX("AC9_2430_MCBSP3_CLKX", 0x0103, 0, 0, 0, 1) | ||
| 267 | MUX_CFG_24XX("AE4_2430_MCBSP3_FSX", 0x0104, 0, 0, 0, 1) | ||
| 268 | MUX_CFG_24XX("AE2_2430_MCBSP3_DR", 0x0105, 0, 0, 0, 1) | ||
| 269 | MUX_CFG_24XX("AF4_2430_MCBSP3_DX", 0x0106, 0, 0, 0, 1) | ||
| 270 | |||
| 271 | MUX_CFG_24XX("N3_2430_MCBSP4_CLKX", 0x010B, 1, 0, 0, 1) | ||
| 272 | MUX_CFG_24XX("AD23_2430_MCBSP4_DR", 0x010C, 1, 0, 0, 1) | ||
| 273 | MUX_CFG_24XX("AB25_2430_MCBSP4_DX", 0x010D, 1, 0, 0, 1) | ||
| 274 | MUX_CFG_24XX("AC25_2430_MCBSP4_FSX", 0x010E, 1, 0, 0, 1) | ||
| 275 | |||
| 276 | MUX_CFG_24XX("AE16_2430_MCBSP5_CLKX", 0x00ED, 1, 0, 0, 1) | ||
| 277 | MUX_CFG_24XX("AF12_2430_MCBSP5_FSX", 0x00ED, 1, 0, 0, 1) | ||
| 278 | MUX_CFG_24XX("K7_2430_MCBSP5_DX", 0x00EF, 1, 0, 0, 1) | ||
| 279 | MUX_CFG_24XX("M1_2430_MCBSP5_DR", 0x00F0, 1, 0, 0, 1) | ||
| 280 | |||
| 281 | /* 2430 MCSPI1 */ | ||
| 282 | MUX_CFG_24XX("Y18_2430_MCSPI1_CLK", 0x010F, 0, 0, 0, 1) | ||
| 283 | MUX_CFG_24XX("AD15_2430_MCSPI1_SIMO", 0x0110, 0, 0, 0, 1) | ||
| 284 | MUX_CFG_24XX("AE17_2430_MCSPI1_SOMI", 0x0111, 0, 0, 0, 1) | ||
| 285 | MUX_CFG_24XX("U1_2430_MCSPI1_CS0", 0x0112, 0, 0, 0, 1) | ||
| 286 | |||
| 287 | /* Touchscreen GPIO */ | ||
| 288 | MUX_CFG_24XX("AF19_2430_GPIO_85", 0x0113, 3, 0, 0, 1) | ||
| 289 | |||
| 290 | }; | ||
| 291 | |||
| 292 | #define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins) | ||
| 293 | |||
| 294 | #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) | ||
| 295 | |||
| 296 | static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg) | ||
| 297 | { | ||
| 298 | u16 orig; | ||
| 299 | u8 warn = 0, debug = 0; | ||
| 300 | |||
| 301 | orig = omap_mux_read(cfg->mux_reg - OMAP_MUX_BASE_OFFSET); | ||
| 302 | |||
| 303 | #ifdef CONFIG_OMAP_MUX_DEBUG | ||
| 304 | debug = cfg->debug; | ||
| 305 | #endif | ||
| 306 | warn = (orig != reg); | ||
| 307 | if (debug || warn) | ||
| 308 | printk(KERN_WARNING | ||
| 309 | "MUX: setup %s (0x%p): 0x%04x -> 0x%04x\n", | ||
| 310 | cfg->name, omap_ctrl_base_get() + cfg->mux_reg, | ||
| 311 | orig, reg); | ||
| 312 | } | ||
| 313 | #else | ||
| 314 | #define omap2_cfg_debug(x, y) do {} while (0) | ||
| 315 | #endif | ||
| 316 | |||
| 317 | static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) | ||
| 318 | { | ||
| 319 | static DEFINE_SPINLOCK(mux_spin_lock); | ||
| 320 | unsigned long flags; | ||
| 321 | u8 reg = 0; | ||
| 322 | |||
| 323 | spin_lock_irqsave(&mux_spin_lock, flags); | ||
| 324 | reg |= cfg->mask & 0x7; | ||
| 325 | if (cfg->pull_val) | ||
| 326 | reg |= OMAP2_PULL_ENA; | ||
| 327 | if (cfg->pu_pd_val) | ||
| 328 | reg |= OMAP2_PULL_UP; | ||
| 329 | omap2_cfg_debug(cfg, reg); | ||
| 330 | omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET); | ||
| 331 | spin_unlock_irqrestore(&mux_spin_lock, flags); | ||
| 332 | |||
| 333 | return 0; | ||
| 334 | } | ||
| 335 | |||
| 336 | int __init omap2_mux_init(void) | ||
| 337 | { | ||
| 338 | u32 mux_pbase; | ||
| 339 | |||
| 340 | if (cpu_is_omap2420()) | ||
| 341 | mux_pbase = OMAP2420_CTRL_BASE + OMAP_MUX_BASE_OFFSET; | ||
| 342 | else if (cpu_is_omap2430()) | ||
| 343 | mux_pbase = OMAP243X_CTRL_BASE + OMAP_MUX_BASE_OFFSET; | ||
| 344 | else | ||
| 345 | return -ENODEV; | ||
| 346 | |||
| 347 | mux_base = ioremap(mux_pbase, OMAP_MUX_BASE_SZ); | ||
| 348 | if (!mux_base) { | ||
| 349 | printk(KERN_ERR "mux: Could not ioremap\n"); | ||
| 350 | return -ENODEV; | ||
| 351 | } | ||
| 352 | |||
| 353 | if (cpu_is_omap24xx()) { | ||
| 354 | arch_mux_cfg.pins = omap24xx_pins; | ||
| 355 | arch_mux_cfg.size = OMAP24XX_PINS_SZ; | ||
| 356 | arch_mux_cfg.cfg_reg = omap24xx_cfg_reg; | ||
| 357 | |||
| 358 | return omap_mux_register(&arch_mux_cfg); | ||
| 359 | } | ||
| 360 | |||
| 361 | return 0; | ||
| 362 | } | ||
| 363 | |||
| 364 | #else | ||
| 365 | int __init omap2_mux_init(void) | ||
| 366 | { | ||
| 367 | return 0; | ||
| 368 | } | ||
| 369 | #endif /* CONFIG_OMAP_MUX */ | ||
| 370 | |||
| 371 | /*----------------------------------------------------------------------------*/ | ||
| 372 | |||
| 373 | #ifdef CONFIG_ARCH_OMAP3 | ||
| 374 | static LIST_HEAD(muxmodes); | 80 | static LIST_HEAD(muxmodes); |
| 375 | static DEFINE_MUTEX(muxmode_mutex); | 81 | static DEFINE_MUTEX(muxmode_mutex); |
| 376 | 82 | ||
| @@ -381,6 +87,9 @@ static char *omap_mux_options; | |||
| 381 | int __init omap_mux_init_gpio(int gpio, int val) | 87 | int __init omap_mux_init_gpio(int gpio, int val) |
| 382 | { | 88 | { |
| 383 | struct omap_mux_entry *e; | 89 | struct omap_mux_entry *e; |
| 90 | struct omap_mux *gpio_mux; | ||
| 91 | u16 old_mode; | ||
| 92 | u16 mux_mode; | ||
| 384 | int found = 0; | 93 | int found = 0; |
| 385 | 94 | ||
| 386 | if (!gpio) | 95 | if (!gpio) |
| @@ -389,31 +98,33 @@ int __init omap_mux_init_gpio(int gpio, int val) | |||
| 389 | list_for_each_entry(e, &muxmodes, node) { | 98 | list_for_each_entry(e, &muxmodes, node) { |
| 390 | struct omap_mux *m = &e->mux; | 99 | struct omap_mux *m = &e->mux; |
| 391 | if (gpio == m->gpio) { | 100 | if (gpio == m->gpio) { |
| 392 | u16 old_mode; | 101 | gpio_mux = m; |
| 393 | u16 mux_mode; | ||
| 394 | |||
| 395 | old_mode = omap_mux_read(m->reg_offset); | ||
| 396 | mux_mode = val & ~(OMAP_MUX_NR_MODES - 1); | ||
| 397 | mux_mode |= OMAP_MUX_MODE4; | ||
| 398 | printk(KERN_DEBUG "mux: Setting signal " | ||
| 399 | "%s.gpio%i 0x%04x -> 0x%04x\n", | ||
| 400 | m->muxnames[0], gpio, old_mode, mux_mode); | ||
| 401 | omap_mux_write(mux_mode, m->reg_offset); | ||
| 402 | found++; | 102 | found++; |
| 403 | } | 103 | } |
| 404 | } | 104 | } |
| 405 | 105 | ||
| 406 | if (found == 1) | 106 | if (found == 0) { |
| 407 | return 0; | 107 | printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); |
| 108 | return -ENODEV; | ||
| 109 | } | ||
| 408 | 110 | ||
| 409 | if (found > 1) { | 111 | if (found > 1) { |
| 410 | printk(KERN_ERR "mux: Multiple gpio paths for gpio%i\n", gpio); | 112 | printk(KERN_INFO "mux: Multiple gpio paths (%d) for gpio%i\n", |
| 113 | found, gpio); | ||
| 411 | return -EINVAL; | 114 | return -EINVAL; |
| 412 | } | 115 | } |
| 413 | 116 | ||
| 414 | printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); | 117 | old_mode = omap_mux_read(gpio_mux->reg_offset); |
| 118 | mux_mode = val & ~(OMAP_MUX_NR_MODES - 1); | ||
| 119 | if (omap_mux_flags & MUXABLE_GPIO_MODE3) | ||
| 120 | mux_mode |= OMAP_MUX_MODE3; | ||
| 121 | else | ||
| 122 | mux_mode |= OMAP_MUX_MODE4; | ||
| 123 | printk(KERN_DEBUG "mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", | ||
| 124 | gpio_mux->muxnames[0], gpio, old_mode, mux_mode); | ||
| 125 | omap_mux_write(mux_mode, gpio_mux->reg_offset); | ||
| 415 | 126 | ||
| 416 | return -ENODEV; | 127 | return 0; |
| 417 | } | 128 | } |
| 418 | 129 | ||
| 419 | int __init omap_mux_init_signal(char *muxname, int val) | 130 | int __init omap_mux_init_signal(char *muxname, int val) |
| @@ -1032,6 +743,9 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size, | |||
| 1032 | return -ENODEV; | 743 | return -ENODEV; |
| 1033 | } | 744 | } |
| 1034 | 745 | ||
| 746 | if (cpu_is_omap24xx()) | ||
| 747 | omap_mux_flags = MUXABLE_GPIO_MODE3; | ||
| 748 | |||
| 1035 | omap_mux_init_package(superset, package_subset, package_balls); | 749 | omap_mux_init_package(superset, package_subset, package_balls); |
| 1036 | omap_mux_init_list(superset); | 750 | omap_mux_init_list(superset); |
| 1037 | omap_mux_init_signals(board_mux); | 751 | omap_mux_init_signals(board_mux); |
| @@ -1039,5 +753,3 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size, | |||
| 1039 | return 0; | 753 | return 0; |
| 1040 | } | 754 | } |
| 1041 | 755 | ||
| 1042 | #endif /* CONFIG_ARCH_OMAP3 */ | ||
| 1043 | |||
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index 480abc56e605..a8e040c2c7e9 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h | |||
| @@ -7,6 +7,8 @@ | |||
| 7 | * published by the Free Software Foundation. | 7 | * published by the Free Software Foundation. |
| 8 | */ | 8 | */ |
| 9 | 9 | ||
| 10 | #include "mux2420.h" | ||
| 11 | #include "mux2430.h" | ||
| 10 | #include "mux34xx.h" | 12 | #include "mux34xx.h" |
| 11 | 13 | ||
| 12 | #define OMAP_MUX_TERMINATOR 0xffff | 14 | #define OMAP_MUX_TERMINATOR 0xffff |
| @@ -56,10 +58,12 @@ | |||
| 56 | 58 | ||
| 57 | /* Flags for omap_mux_init */ | 59 | /* Flags for omap_mux_init */ |
| 58 | #define OMAP_PACKAGE_MASK 0xffff | 60 | #define OMAP_PACKAGE_MASK 0xffff |
| 59 | #define OMAP_PACKAGE_CBP 4 /* 515-pin 0.40 0.50 */ | 61 | #define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */ |
| 60 | #define OMAP_PACKAGE_CUS 3 /* 423-pin 0.65 */ | 62 | #define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ |
| 61 | #define OMAP_PACKAGE_CBB 2 /* 515-pin 0.40 0.50 */ | 63 | #define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */ |
| 62 | #define OMAP_PACKAGE_CBC 1 /* 515-pin 0.50 0.65 */ | 64 | #define OMAP_PACKAGE_CBC 3 /* 515-pin 0.50 0.65 */ |
| 65 | #define OMAP_PACKAGE_ZAC 2 /* 24xx 447-pin POP */ | ||
| 66 | #define OMAP_PACKAGE_ZAF 1 /* 2420 447-pin SIP */ | ||
| 63 | 67 | ||
| 64 | 68 | ||
| 65 | #define OMAP_MUX_NR_MODES 8 /* Available modes */ | 69 | #define OMAP_MUX_NR_MODES 8 /* Available modes */ |
| @@ -102,7 +106,7 @@ struct omap_board_mux { | |||
| 102 | u16 value; | 106 | u16 value; |
| 103 | }; | 107 | }; |
| 104 | 108 | ||
| 105 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP3) | 109 | #if defined(CONFIG_OMAP_MUX) |
| 106 | 110 | ||
| 107 | /** | 111 | /** |
| 108 | * omap_mux_init_gpio - initialize a signal based on the GPIO number | 112 | * omap_mux_init_gpio - initialize a signal based on the GPIO number |
| @@ -171,6 +175,20 @@ void omap_mux_write(u16 val, u16 mux_offset); | |||
| 171 | void omap_mux_write_array(struct omap_board_mux *board_mux); | 175 | void omap_mux_write_array(struct omap_board_mux *board_mux); |
| 172 | 176 | ||
| 173 | /** | 177 | /** |
| 178 | * omap2420_mux_init() - initialize mux system with board specific set | ||
| 179 | * @board_mux: Board specific mux table | ||
| 180 | * @flags: OMAP package type used for the board | ||
| 181 | */ | ||
| 182 | int omap2420_mux_init(struct omap_board_mux *board_mux, int flags); | ||
| 183 | |||
| 184 | /** | ||
| 185 | * omap2430_mux_init() - initialize mux system with board specific set | ||
| 186 | * @board_mux: Board specific mux table | ||
| 187 | * @flags: OMAP package type used for the board | ||
| 188 | */ | ||
| 189 | int omap2430_mux_init(struct omap_board_mux *board_mux, int flags); | ||
| 190 | |||
| 191 | /** | ||
| 174 | * omap3_mux_init() - initialize mux system with board specific set | 192 | * omap3_mux_init() - initialize mux system with board specific set |
| 175 | * @board_mux: Board specific mux table | 193 | * @board_mux: Board specific mux table |
| 176 | * @flags: OMAP package type used for the board | 194 | * @flags: OMAP package type used for the board |
diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c new file mode 100644 index 000000000000..fdb04a7eb8aa --- /dev/null +++ b/arch/arm/mach-omap2/mux2420.c | |||
| @@ -0,0 +1,688 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Nokia | ||
| 3 | * Copyright (C) 2010 Texas Instruments | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/module.h> | ||
| 11 | #include <linux/init.h> | ||
| 12 | |||
| 13 | #include "mux.h" | ||
| 14 | |||
| 15 | #ifdef CONFIG_OMAP_MUX | ||
| 16 | |||
| 17 | #define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ | ||
| 18 | { \ | ||
| 19 | .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \ | ||
| 20 | .gpio = (g), \ | ||
| 21 | .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ | ||
| 22 | } | ||
| 23 | |||
| 24 | #else | ||
| 25 | |||
| 26 | #define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ | ||
| 27 | { \ | ||
| 28 | .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \ | ||
| 29 | .gpio = (g), \ | ||
| 30 | } | ||
| 31 | |||
| 32 | #endif | ||
| 33 | |||
| 34 | #define _OMAP2420_BALLENTRY(M0, bb, bt) \ | ||
| 35 | { \ | ||
| 36 | .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \ | ||
| 37 | .balls = { bb, bt }, \ | ||
| 38 | } | ||
| 39 | |||
| 40 | /* | ||
| 41 | * Superset of all mux modes for omap2420 | ||
| 42 | */ | ||
| 43 | static struct omap_mux __initdata omap2420_muxmodes[] = { | ||
| 44 | _OMAP2420_MUXENTRY(CAM_D0, 54, | ||
| 45 | "cam_d0", "hw_dbg2", "sti_dout", "gpio_54", | ||
| 46 | NULL, NULL, "etk_d2", NULL), | ||
| 47 | _OMAP2420_MUXENTRY(CAM_D1, 53, | ||
| 48 | "cam_d1", "hw_dbg3", "sti_din", "gpio_53", | ||
| 49 | NULL, NULL, "etk_d3", NULL), | ||
| 50 | _OMAP2420_MUXENTRY(CAM_D2, 52, | ||
| 51 | "cam_d2", "hw_dbg4", "mcbsp1_clkx", "gpio_52", | ||
| 52 | NULL, NULL, "etk_d4", NULL), | ||
| 53 | _OMAP2420_MUXENTRY(CAM_D3, 51, | ||
| 54 | "cam_d3", "hw_dbg5", "mcbsp1_dr", "gpio_51", | ||
| 55 | NULL, NULL, "etk_d5", NULL), | ||
| 56 | _OMAP2420_MUXENTRY(CAM_D4, 50, | ||
| 57 | "cam_d4", "hw_dbg6", "mcbsp1_fsr", "gpio_50", | ||
| 58 | NULL, NULL, "etk_d6", NULL), | ||
| 59 | _OMAP2420_MUXENTRY(CAM_D5, 49, | ||
| 60 | "cam_d5", "hw_dbg7", "mcbsp1_clkr", "gpio_49", | ||
| 61 | NULL, NULL, "etk_d7", NULL), | ||
| 62 | _OMAP2420_MUXENTRY(CAM_D6, 0, | ||
| 63 | "cam_d6", "hw_dbg8", NULL, NULL, | ||
| 64 | NULL, NULL, "etk_d8", NULL), | ||
| 65 | _OMAP2420_MUXENTRY(CAM_D7, 0, | ||
| 66 | "cam_d7", "hw_dbg9", NULL, NULL, | ||
| 67 | NULL, NULL, "etk_d9", NULL), | ||
| 68 | _OMAP2420_MUXENTRY(CAM_D8, 54, | ||
| 69 | "cam_d8", "hw_dbg10", NULL, "gpio_54", | ||
| 70 | NULL, NULL, "etk_d10", NULL), | ||
| 71 | _OMAP2420_MUXENTRY(CAM_D9, 53, | ||
| 72 | "cam_d9", "hw_dbg11", NULL, "gpio_53", | ||
| 73 | NULL, NULL, "etk_d11", NULL), | ||
| 74 | _OMAP2420_MUXENTRY(CAM_HS, 55, | ||
| 75 | "cam_hs", "hw_dbg1", "mcbsp1_dx", "gpio_55", | ||
| 76 | NULL, NULL, "etk_d1", NULL), | ||
| 77 | _OMAP2420_MUXENTRY(CAM_LCLK, 57, | ||
| 78 | "cam_lclk", NULL, "mcbsp_clks", "gpio_57", | ||
| 79 | NULL, NULL, "etk_c1", NULL), | ||
| 80 | _OMAP2420_MUXENTRY(CAM_VS, 56, | ||
| 81 | "cam_vs", "hw_dbg0", "mcbsp1_fsx", "gpio_56", | ||
| 82 | NULL, NULL, "etk_d0", NULL), | ||
| 83 | _OMAP2420_MUXENTRY(CAM_XCLK, 0, | ||
| 84 | "cam_xclk", NULL, "sti_clk", NULL, | ||
| 85 | NULL, NULL, "etk_c2", NULL), | ||
| 86 | _OMAP2420_MUXENTRY(DSS_ACBIAS, 48, | ||
| 87 | "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48", | ||
| 88 | NULL, NULL, NULL, NULL), | ||
| 89 | _OMAP2420_MUXENTRY(DSS_DATA10, 40, | ||
| 90 | "dss_data10", NULL, NULL, "gpio_40", | ||
| 91 | NULL, NULL, NULL, NULL), | ||
| 92 | _OMAP2420_MUXENTRY(DSS_DATA11, 41, | ||
| 93 | "dss_data11", NULL, NULL, "gpio_41", | ||
| 94 | NULL, NULL, NULL, NULL), | ||
| 95 | _OMAP2420_MUXENTRY(DSS_DATA12, 42, | ||
| 96 | "dss_data12", NULL, NULL, "gpio_42", | ||
| 97 | NULL, NULL, NULL, NULL), | ||
| 98 | _OMAP2420_MUXENTRY(DSS_DATA13, 43, | ||
| 99 | "dss_data13", NULL, NULL, "gpio_43", | ||
| 100 | NULL, NULL, NULL, NULL), | ||
| 101 | _OMAP2420_MUXENTRY(DSS_DATA14, 44, | ||
| 102 | "dss_data14", NULL, NULL, "gpio_44", | ||
| 103 | NULL, NULL, NULL, NULL), | ||
| 104 | _OMAP2420_MUXENTRY(DSS_DATA15, 45, | ||
| 105 | "dss_data15", NULL, NULL, "gpio_45", | ||
| 106 | NULL, NULL, NULL, NULL), | ||
| 107 | _OMAP2420_MUXENTRY(DSS_DATA16, 46, | ||
| 108 | "dss_data16", NULL, NULL, "gpio_46", | ||
| 109 | NULL, NULL, NULL, NULL), | ||
| 110 | _OMAP2420_MUXENTRY(DSS_DATA17, 47, | ||
| 111 | "dss_data17", NULL, NULL, "gpio_47", | ||
| 112 | NULL, NULL, NULL, NULL), | ||
| 113 | _OMAP2420_MUXENTRY(DSS_DATA8, 38, | ||
| 114 | "dss_data8", NULL, NULL, "gpio_38", | ||
| 115 | NULL, NULL, NULL, NULL), | ||
| 116 | _OMAP2420_MUXENTRY(DSS_DATA9, 39, | ||
| 117 | "dss_data9", NULL, NULL, "gpio_39", | ||
| 118 | NULL, NULL, NULL, NULL), | ||
| 119 | _OMAP2420_MUXENTRY(EAC_AC_DIN, 115, | ||
| 120 | "eac_ac_din", "mcbsp2_dr", NULL, "gpio_115", | ||
| 121 | NULL, NULL, NULL, NULL), | ||
| 122 | _OMAP2420_MUXENTRY(EAC_AC_DOUT, 116, | ||
| 123 | "eac_ac_dout", "mcbsp2_dx", NULL, "gpio_116", | ||
| 124 | NULL, NULL, NULL, NULL), | ||
| 125 | _OMAP2420_MUXENTRY(EAC_AC_FS, 114, | ||
| 126 | "eac_ac_fs", "mcbsp2_fsx", NULL, "gpio_114", | ||
| 127 | NULL, NULL, NULL, NULL), | ||
| 128 | _OMAP2420_MUXENTRY(EAC_AC_MCLK, 117, | ||
| 129 | "eac_ac_mclk", NULL, NULL, "gpio_117", | ||
| 130 | NULL, NULL, NULL, NULL), | ||
| 131 | _OMAP2420_MUXENTRY(EAC_AC_RST, 118, | ||
| 132 | "eac_ac_rst", "eac_bt_din", NULL, "gpio_118", | ||
| 133 | NULL, NULL, NULL, NULL), | ||
| 134 | _OMAP2420_MUXENTRY(EAC_AC_SCLK, 113, | ||
| 135 | "eac_ac_sclk", "mcbsp2_clkx", NULL, "gpio_113", | ||
| 136 | NULL, NULL, NULL, NULL), | ||
| 137 | _OMAP2420_MUXENTRY(EAC_BT_DIN, 73, | ||
| 138 | "eac_bt_din", NULL, NULL, "gpio_73", | ||
| 139 | NULL, NULL, "etk_d9", NULL), | ||
| 140 | _OMAP2420_MUXENTRY(EAC_BT_DOUT, 74, | ||
| 141 | "eac_bt_dout", NULL, "sti_clk", "gpio_74", | ||
| 142 | NULL, NULL, "etk_d8", NULL), | ||
| 143 | _OMAP2420_MUXENTRY(EAC_BT_FS, 72, | ||
| 144 | "eac_bt_fs", NULL, NULL, "gpio_72", | ||
| 145 | NULL, NULL, "etk_d10", NULL), | ||
| 146 | _OMAP2420_MUXENTRY(EAC_BT_SCLK, 71, | ||
| 147 | "eac_bt_sclk", NULL, NULL, "gpio_71", | ||
| 148 | NULL, NULL, "etk_d11", NULL), | ||
| 149 | _OMAP2420_MUXENTRY(GPIO_119, 119, | ||
| 150 | "gpio_119", NULL, "sti_din", "gpio_119", | ||
| 151 | NULL, "sys_boot0", "etk_d12", NULL), | ||
| 152 | _OMAP2420_MUXENTRY(GPIO_120, 120, | ||
| 153 | "gpio_120", NULL, "sti_dout", "gpio_120", | ||
| 154 | "cam_d9", "sys_boot1", "etk_d13", NULL), | ||
| 155 | _OMAP2420_MUXENTRY(GPIO_121, 121, | ||
| 156 | "gpio_121", NULL, NULL, "gpio_121", | ||
| 157 | "jtag_emu2", "sys_boot2", "etk_d14", NULL), | ||
| 158 | _OMAP2420_MUXENTRY(GPIO_122, 122, | ||
| 159 | "gpio_122", NULL, NULL, "gpio_122", | ||
| 160 | "jtag_emu3", "sys_boot3", "etk_d15", NULL), | ||
| 161 | _OMAP2420_MUXENTRY(GPIO_124, 124, | ||
| 162 | "gpio_124", NULL, NULL, "gpio_124", | ||
| 163 | NULL, "sys_boot5", NULL, NULL), | ||
| 164 | _OMAP2420_MUXENTRY(GPIO_125, 125, | ||
| 165 | "gpio_125", "sys_jtagsel1", "sys_jtagsel2", "gpio_125", | ||
| 166 | NULL, NULL, NULL, NULL), | ||
| 167 | _OMAP2420_MUXENTRY(GPIO_36, 36, | ||
| 168 | "gpio_36", NULL, NULL, "gpio_36", | ||
| 169 | NULL, "sys_boot4", NULL, NULL), | ||
| 170 | _OMAP2420_MUXENTRY(GPIO_62, 62, | ||
| 171 | "gpio_62", "uart1_rx", "usb1_dat", "gpio_62", | ||
| 172 | NULL, NULL, NULL, NULL), | ||
| 173 | _OMAP2420_MUXENTRY(GPIO_6, 6, | ||
| 174 | "gpio_6", "tv_detpulse", NULL, "gpio_6", | ||
| 175 | NULL, NULL, NULL, NULL), | ||
| 176 | _OMAP2420_MUXENTRY(GPMC_A10, 3, | ||
| 177 | "gpmc_a10", NULL, "sys_ndmareq5", "gpio_3", | ||
| 178 | NULL, NULL, NULL, NULL), | ||
| 179 | _OMAP2420_MUXENTRY(GPMC_A1, 12, | ||
| 180 | "gpmc_a1", "dss_data18", NULL, "gpio_12", | ||
| 181 | NULL, NULL, NULL, NULL), | ||
| 182 | _OMAP2420_MUXENTRY(GPMC_A2, 11, | ||
| 183 | "gpmc_a2", "dss_data19", NULL, "gpio_11", | ||
| 184 | NULL, NULL, NULL, NULL), | ||
| 185 | _OMAP2420_MUXENTRY(GPMC_A3, 10, | ||
| 186 | "gpmc_a3", "dss_data20", NULL, "gpio_10", | ||
| 187 | NULL, NULL, NULL, NULL), | ||
| 188 | _OMAP2420_MUXENTRY(GPMC_A4, 9, | ||
| 189 | "gpmc_a4", "dss_data21", NULL, "gpio_9", | ||
| 190 | NULL, NULL, NULL, NULL), | ||
| 191 | _OMAP2420_MUXENTRY(GPMC_A5, 8, | ||
| 192 | "gpmc_a5", "dss_data22", NULL, "gpio_8", | ||
| 193 | NULL, NULL, NULL, NULL), | ||
| 194 | _OMAP2420_MUXENTRY(GPMC_A6, 7, | ||
| 195 | "gpmc_a6", "dss_data23", NULL, "gpio_7", | ||
| 196 | NULL, NULL, NULL, NULL), | ||
| 197 | _OMAP2420_MUXENTRY(GPMC_A7, 6, | ||
| 198 | "gpmc_a7", NULL, "sys_ndmareq2", "gpio_6", | ||
| 199 | NULL, NULL, NULL, NULL), | ||
| 200 | _OMAP2420_MUXENTRY(GPMC_A8, 5, | ||
| 201 | "gpmc_a8", NULL, "sys_ndmareq3", "gpio_5", | ||
| 202 | NULL, NULL, NULL, NULL), | ||
| 203 | _OMAP2420_MUXENTRY(GPMC_A9, 4, | ||
| 204 | "gpmc_a9", NULL, "sys_ndmareq4", "gpio_4", | ||
| 205 | NULL, NULL, NULL, NULL), | ||
| 206 | _OMAP2420_MUXENTRY(GPMC_CLK, 21, | ||
| 207 | "gpmc_clk", NULL, NULL, "gpio_21", | ||
| 208 | NULL, NULL, NULL, NULL), | ||
| 209 | _OMAP2420_MUXENTRY(GPMC_D10, 18, | ||
| 210 | "gpmc_d10", "ssi2_rdy_rx", NULL, "gpio_18", | ||
| 211 | NULL, NULL, NULL, NULL), | ||
| 212 | _OMAP2420_MUXENTRY(GPMC_D11, 17, | ||
| 213 | "gpmc_d11", "ssi2_flag_rx", NULL, "gpio_17", | ||
| 214 | NULL, NULL, NULL, NULL), | ||
| 215 | _OMAP2420_MUXENTRY(GPMC_D12, 16, | ||
| 216 | "gpmc_d12", "ssi2_dat_rx", NULL, "gpio_16", | ||
| 217 | NULL, NULL, NULL, NULL), | ||
| 218 | _OMAP2420_MUXENTRY(GPMC_D13, 15, | ||
| 219 | "gpmc_d13", "ssi2_rdy_tx", NULL, "gpio_15", | ||
| 220 | NULL, NULL, NULL, NULL), | ||
| 221 | _OMAP2420_MUXENTRY(GPMC_D14, 14, | ||
| 222 | "gpmc_d14", "ssi2_flag_tx", NULL, "gpio_14", | ||
| 223 | NULL, NULL, NULL, NULL), | ||
| 224 | _OMAP2420_MUXENTRY(GPMC_D15, 13, | ||
| 225 | "gpmc_d15", "ssi2_dat_tx", NULL, "gpio_13", | ||
| 226 | NULL, NULL, NULL, NULL), | ||
| 227 | _OMAP2420_MUXENTRY(GPMC_D8, 20, | ||
| 228 | "gpmc_d8", NULL, NULL, "gpio_20", | ||
| 229 | NULL, NULL, NULL, NULL), | ||
| 230 | _OMAP2420_MUXENTRY(GPMC_D9, 19, | ||
| 231 | "gpmc_d9", "ssi2_wake", NULL, "gpio_19", | ||
| 232 | NULL, NULL, NULL, NULL), | ||
| 233 | _OMAP2420_MUXENTRY(GPMC_NBE0, 29, | ||
| 234 | "gpmc_nbe0", NULL, NULL, "gpio_29", | ||
| 235 | NULL, NULL, NULL, NULL), | ||
| 236 | _OMAP2420_MUXENTRY(GPMC_NBE1, 30, | ||
| 237 | "gpmc_nbe1", NULL, NULL, "gpio_30", | ||
| 238 | NULL, NULL, NULL, NULL), | ||
| 239 | _OMAP2420_MUXENTRY(GPMC_NCS1, 22, | ||
| 240 | "gpmc_ncs1", NULL, NULL, "gpio_22", | ||
| 241 | NULL, NULL, NULL, NULL), | ||
| 242 | _OMAP2420_MUXENTRY(GPMC_NCS2, 23, | ||
| 243 | "gpmc_ncs2", NULL, NULL, "gpio_23", | ||
| 244 | NULL, NULL, NULL, NULL), | ||
| 245 | _OMAP2420_MUXENTRY(GPMC_NCS3, 24, | ||
| 246 | "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24", | ||
| 247 | NULL, NULL, NULL, NULL), | ||
| 248 | _OMAP2420_MUXENTRY(GPMC_NCS4, 25, | ||
| 249 | "gpmc_ncs4", NULL, NULL, "gpio_25", | ||
| 250 | NULL, NULL, NULL, NULL), | ||
| 251 | _OMAP2420_MUXENTRY(GPMC_NCS5, 26, | ||
| 252 | "gpmc_ncs5", NULL, NULL, "gpio_26", | ||
| 253 | NULL, NULL, NULL, NULL), | ||
| 254 | _OMAP2420_MUXENTRY(GPMC_NCS6, 27, | ||
| 255 | "gpmc_ncs6", NULL, NULL, "gpio_27", | ||
| 256 | NULL, NULL, NULL, NULL), | ||
| 257 | _OMAP2420_MUXENTRY(GPMC_NCS7, 28, | ||
| 258 | "gpmc_ncs7", "gpmc_io_dir", "gpio_28", NULL, | ||
| 259 | NULL, NULL, NULL, NULL), | ||
| 260 | _OMAP2420_MUXENTRY(GPMC_NWP, 31, | ||
| 261 | "gpmc_nwp", NULL, NULL, "gpio_31", | ||
| 262 | NULL, NULL, NULL, NULL), | ||
| 263 | _OMAP2420_MUXENTRY(GPMC_WAIT1, 33, | ||
| 264 | "gpmc_wait1", NULL, NULL, "gpio_33", | ||
| 265 | NULL, NULL, NULL, NULL), | ||
| 266 | _OMAP2420_MUXENTRY(GPMC_WAIT2, 34, | ||
| 267 | "gpmc_wait2", NULL, NULL, "gpio_34", | ||
| 268 | NULL, NULL, NULL, NULL), | ||
| 269 | _OMAP2420_MUXENTRY(GPMC_WAIT3, 35, | ||
| 270 | "gpmc_wait3", NULL, NULL, "gpio_35", | ||
| 271 | NULL, NULL, NULL, NULL), | ||
| 272 | _OMAP2420_MUXENTRY(HDQ_SIO, 101, | ||
| 273 | "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101", | ||
| 274 | NULL, NULL, NULL, NULL), | ||
| 275 | _OMAP2420_MUXENTRY(I2C2_SCL, 99, | ||
| 276 | "i2c2_scl", NULL, "gpt9_pwm_evt", "gpio_99", | ||
| 277 | NULL, NULL, NULL, NULL), | ||
| 278 | _OMAP2420_MUXENTRY(I2C2_SDA, 100, | ||
| 279 | "i2c2_sda", NULL, "spi2_ncs1", "gpio_100", | ||
| 280 | NULL, NULL, NULL, NULL), | ||
| 281 | _OMAP2420_MUXENTRY(JTAG_EMU0, 127, | ||
| 282 | "jtag_emu0", NULL, NULL, "gpio_127", | ||
| 283 | NULL, NULL, NULL, NULL), | ||
| 284 | _OMAP2420_MUXENTRY(JTAG_EMU1, 126, | ||
| 285 | "jtag_emu1", NULL, NULL, "gpio_126", | ||
| 286 | NULL, NULL, NULL, NULL), | ||
| 287 | _OMAP2420_MUXENTRY(MCBSP1_CLKR, 92, | ||
| 288 | "mcbsp1_clkr", "ssi2_dat_tx", "vlynq_tx1", "gpio_92", | ||
| 289 | NULL, NULL, NULL, NULL), | ||
| 290 | _OMAP2420_MUXENTRY(MCBSP1_CLKX, 98, | ||
| 291 | "mcbsp1_clkx", "ssi2_wake", "vlynq_nla", "gpio_98", | ||
| 292 | NULL, NULL, NULL, NULL), | ||
| 293 | _OMAP2420_MUXENTRY(MCBSP1_DR, 95, | ||
| 294 | "mcbsp1_dr", "ssi2_dat_rx", "vlynq_rx1", "gpio_95", | ||
| 295 | NULL, NULL, NULL, NULL), | ||
| 296 | _OMAP2420_MUXENTRY(MCBSP1_DX, 94, | ||
| 297 | "mcbsp1_dx", "ssi2_rdy_tx", "vlynq_clk", "gpio_94", | ||
| 298 | NULL, NULL, NULL, NULL), | ||
| 299 | _OMAP2420_MUXENTRY(MCBSP1_FSR, 93, | ||
| 300 | "mcbsp1_fsr", "ssi2_flag_tx", "vlynq_tx0", "gpio_93", | ||
| 301 | "spi2_ncs1", NULL, NULL, NULL), | ||
| 302 | _OMAP2420_MUXENTRY(MCBSP1_FSX, 97, | ||
| 303 | "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97", | ||
| 304 | NULL, NULL, NULL, NULL), | ||
| 305 | _OMAP2420_MUXENTRY(MCBSP2_CLKX, 12, | ||
| 306 | "mcbsp2_clkx", NULL, "dss_data23", "gpio_12", | ||
| 307 | NULL, NULL, NULL, NULL), | ||
| 308 | _OMAP2420_MUXENTRY(MCBSP2_DR, 11, | ||
| 309 | "mcbsp2_dr", NULL, "dss_data22", "gpio_11", | ||
| 310 | NULL, NULL, NULL, NULL), | ||
| 311 | _OMAP2420_MUXENTRY(MCBSP_CLKS, 96, | ||
| 312 | "mcbsp_clks", "ssi2_flag_rx", "vlynq_rx0", "gpio_96", | ||
| 313 | NULL, NULL, NULL, NULL), | ||
| 314 | _OMAP2420_MUXENTRY(MMC_CLKI, 59, | ||
| 315 | "sdmmc_clki", "ms_clki", NULL, "gpio_59", | ||
| 316 | NULL, NULL, NULL, NULL), | ||
| 317 | _OMAP2420_MUXENTRY(MMC_CLKO, 0, | ||
| 318 | "sdmmc_clko", "ms_clko", NULL, NULL, | ||
| 319 | NULL, NULL, NULL, NULL), | ||
| 320 | _OMAP2420_MUXENTRY(MMC_CMD_DIR, 8, | ||
| 321 | "sdmmc_cmd_dir", NULL, NULL, "gpio_8", | ||
| 322 | NULL, NULL, NULL, NULL), | ||
| 323 | _OMAP2420_MUXENTRY(MMC_CMD, 0, | ||
| 324 | "sdmmc_cmd", "ms_bs", NULL, NULL, | ||
| 325 | NULL, NULL, NULL, NULL), | ||
| 326 | _OMAP2420_MUXENTRY(MMC_DAT_DIR0, 7, | ||
| 327 | "sdmmc_dat_dir0", "ms_dat0_dir", NULL, "gpio_7", | ||
| 328 | NULL, NULL, NULL, NULL), | ||
| 329 | _OMAP2420_MUXENTRY(MMC_DAT0, 0, | ||
| 330 | "sdmmc_dat0", "ms_dat0", NULL, NULL, | ||
| 331 | NULL, NULL, NULL, NULL), | ||
| 332 | _OMAP2420_MUXENTRY(MMC_DAT_DIR1, 78, | ||
| 333 | "sdmmc_dat_dir1", "ms_datu_dir", "uart2_rts", "gpio_78", | ||
| 334 | NULL, NULL, NULL, NULL), | ||
| 335 | _OMAP2420_MUXENTRY(MMC_DAT1, 75, | ||
| 336 | "sdmmc_dat1", "ms_dat1", NULL, "gpio_75", | ||
| 337 | NULL, NULL, NULL, NULL), | ||
| 338 | _OMAP2420_MUXENTRY(MMC_DAT_DIR2, 79, | ||
| 339 | "sdmmc_dat_dir2", "ms_datu_dir", "uart2_tx", "gpio_79", | ||
| 340 | NULL, NULL, NULL, NULL), | ||
| 341 | _OMAP2420_MUXENTRY(MMC_DAT2, 76, | ||
| 342 | "sdmmc_dat2", "ms_dat2", "uart2_cts", "gpio_76", | ||
| 343 | NULL, NULL, NULL, NULL), | ||
| 344 | _OMAP2420_MUXENTRY(MMC_DAT_DIR3, 80, | ||
| 345 | "sdmmc_dat_dir3", "ms_datu_dir", "uart2_rx", "gpio_80", | ||
| 346 | NULL, NULL, NULL, NULL), | ||
| 347 | _OMAP2420_MUXENTRY(MMC_DAT3, 77, | ||
| 348 | "sdmmc_dat3", "ms_dat3", NULL, "gpio_77", | ||
| 349 | NULL, NULL, NULL, NULL), | ||
| 350 | _OMAP2420_MUXENTRY(SDRC_A12, 2, | ||
| 351 | "sdrc_a12", NULL, NULL, "gpio_2", | ||
| 352 | NULL, NULL, NULL, NULL), | ||
| 353 | _OMAP2420_MUXENTRY(SDRC_A13, 1, | ||
| 354 | "sdrc_a13", NULL, NULL, "gpio_1", | ||
| 355 | NULL, NULL, NULL, NULL), | ||
| 356 | _OMAP2420_MUXENTRY(SDRC_A14, 0, | ||
| 357 | "sdrc_a14", NULL, NULL, "gpio_0", | ||
| 358 | NULL, NULL, NULL, NULL), | ||
| 359 | _OMAP2420_MUXENTRY(SDRC_CKE1, 38, | ||
| 360 | "sdrc_cke1", NULL, NULL, "gpio_38", | ||
| 361 | NULL, NULL, NULL, NULL), | ||
| 362 | _OMAP2420_MUXENTRY(SDRC_NCS1, 37, | ||
| 363 | "sdrc_ncs1", NULL, NULL, "gpio_37", | ||
| 364 | NULL, NULL, NULL, NULL), | ||
| 365 | _OMAP2420_MUXENTRY(SPI1_CLK, 81, | ||
| 366 | "spi1_clk", NULL, NULL, "gpio_81", | ||
| 367 | NULL, NULL, NULL, NULL), | ||
| 368 | _OMAP2420_MUXENTRY(SPI1_NCS0, 84, | ||
| 369 | "spi1_ncs0", NULL, NULL, "gpio_84", | ||
| 370 | NULL, NULL, NULL, NULL), | ||
| 371 | _OMAP2420_MUXENTRY(SPI1_NCS1, 85, | ||
| 372 | "spi1_ncs1", NULL, NULL, "gpio_85", | ||
| 373 | NULL, NULL, NULL, NULL), | ||
| 374 | _OMAP2420_MUXENTRY(SPI1_NCS2, 86, | ||
| 375 | "spi1_ncs2", NULL, NULL, "gpio_86", | ||
| 376 | NULL, NULL, NULL, NULL), | ||
| 377 | _OMAP2420_MUXENTRY(SPI1_NCS3, 87, | ||
| 378 | "spi1_ncs3", NULL, NULL, "gpio_87", | ||
| 379 | NULL, NULL, NULL, NULL), | ||
| 380 | _OMAP2420_MUXENTRY(SPI1_SIMO, 82, | ||
| 381 | "spi1_simo", NULL, NULL, "gpio_82", | ||
| 382 | NULL, NULL, NULL, NULL), | ||
| 383 | _OMAP2420_MUXENTRY(SPI1_SOMI, 83, | ||
| 384 | "spi1_somi", NULL, NULL, "gpio_83", | ||
| 385 | NULL, NULL, NULL, NULL), | ||
| 386 | _OMAP2420_MUXENTRY(SPI2_CLK, 88, | ||
| 387 | "spi2_clk", NULL, NULL, "gpio_88", | ||
| 388 | NULL, NULL, NULL, NULL), | ||
| 389 | _OMAP2420_MUXENTRY(SPI2_NCS0, 91, | ||
| 390 | "spi2_ncs0", "gpt12_pwm_evt", NULL, "gpio_91", | ||
| 391 | NULL, NULL, NULL, NULL), | ||
| 392 | _OMAP2420_MUXENTRY(SPI2_SIMO, 89, | ||
| 393 | "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89", | ||
| 394 | NULL, NULL, NULL, NULL), | ||
| 395 | _OMAP2420_MUXENTRY(SPI2_SOMI, 90, | ||
| 396 | "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90", | ||
| 397 | NULL, NULL, NULL, NULL), | ||
| 398 | _OMAP2420_MUXENTRY(SSI1_DAT_RX, 63, | ||
| 399 | "ssi1_dat_rx", "eac_md_sclk", NULL, "gpio_63", | ||
| 400 | NULL, NULL, NULL, NULL), | ||
| 401 | _OMAP2420_MUXENTRY(SSI1_DAT_TX, 59, | ||
| 402 | "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59", | ||
| 403 | NULL, NULL, NULL, NULL), | ||
| 404 | _OMAP2420_MUXENTRY(SSI1_FLAG_RX, 64, | ||
| 405 | "ssi1_flag_rx", "eac_md_din", NULL, "gpio_64", | ||
| 406 | NULL, NULL, NULL, NULL), | ||
| 407 | _OMAP2420_MUXENTRY(SSI1_FLAG_TX, 25, | ||
| 408 | "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_25", | ||
| 409 | NULL, NULL, NULL, NULL), | ||
| 410 | _OMAP2420_MUXENTRY(SSI1_RDY_RX, 65, | ||
| 411 | "ssi1_rdy_rx", "eac_md_dout", NULL, "gpio_65", | ||
| 412 | NULL, NULL, NULL, NULL), | ||
| 413 | _OMAP2420_MUXENTRY(SSI1_RDY_TX, 61, | ||
| 414 | "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61", | ||
| 415 | NULL, NULL, NULL, NULL), | ||
| 416 | _OMAP2420_MUXENTRY(SSI1_WAKE, 66, | ||
| 417 | "ssi1_wake", "eac_md_fs", NULL, "gpio_66", | ||
| 418 | NULL, NULL, NULL, NULL), | ||
| 419 | _OMAP2420_MUXENTRY(SYS_CLKOUT, 123, | ||
| 420 | "sys_clkout", NULL, NULL, "gpio_123", | ||
| 421 | NULL, NULL, NULL, NULL), | ||
| 422 | _OMAP2420_MUXENTRY(SYS_CLKREQ, 52, | ||
| 423 | "sys_clkreq", NULL, NULL, "gpio_52", | ||
| 424 | NULL, NULL, NULL, NULL), | ||
| 425 | _OMAP2420_MUXENTRY(SYS_NIRQ, 60, | ||
| 426 | "sys_nirq", NULL, NULL, "gpio_60", | ||
| 427 | NULL, NULL, NULL, NULL), | ||
| 428 | _OMAP2420_MUXENTRY(UART1_CTS, 32, | ||
| 429 | "uart1_cts", NULL, "dss_data18", "gpio_32", | ||
| 430 | NULL, NULL, NULL, NULL), | ||
| 431 | _OMAP2420_MUXENTRY(UART1_RTS, 8, | ||
| 432 | "uart1_rts", NULL, "dss_data19", "gpio_8", | ||
| 433 | NULL, NULL, NULL, NULL), | ||
| 434 | _OMAP2420_MUXENTRY(UART1_RX, 10, | ||
| 435 | "uart1_rx", NULL, "dss_data21", "gpio_10", | ||
| 436 | NULL, NULL, NULL, NULL), | ||
| 437 | _OMAP2420_MUXENTRY(UART1_TX, 9, | ||
| 438 | "uart1_tx", NULL, "dss_data20", "gpio_9", | ||
| 439 | NULL, NULL, NULL, NULL), | ||
| 440 | _OMAP2420_MUXENTRY(UART2_CTS, 67, | ||
| 441 | "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67", | ||
| 442 | NULL, NULL, NULL, NULL), | ||
| 443 | _OMAP2420_MUXENTRY(UART2_RTS, 68, | ||
| 444 | "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68", | ||
| 445 | NULL, NULL, NULL, NULL), | ||
| 446 | _OMAP2420_MUXENTRY(UART2_RX, 70, | ||
| 447 | "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70", | ||
| 448 | NULL, NULL, NULL, NULL), | ||
| 449 | _OMAP2420_MUXENTRY(UART2_TX, 69, | ||
| 450 | "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69", | ||
| 451 | NULL, NULL, NULL, NULL), | ||
| 452 | _OMAP2420_MUXENTRY(UART3_CTS_RCTX, 102, | ||
| 453 | "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102", | ||
| 454 | NULL, NULL, NULL, NULL), | ||
| 455 | _OMAP2420_MUXENTRY(UART3_RTS_SD, 103, | ||
| 456 | "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103", | ||
| 457 | NULL, NULL, NULL, NULL), | ||
| 458 | _OMAP2420_MUXENTRY(UART3_RX_IRRX, 105, | ||
| 459 | "uart3_rx_irrx", NULL, NULL, "gpio_105", | ||
| 460 | NULL, NULL, NULL, NULL), | ||
| 461 | _OMAP2420_MUXENTRY(UART3_TX_IRTX, 104, | ||
| 462 | "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104", | ||
| 463 | NULL, NULL, NULL, NULL), | ||
| 464 | _OMAP2420_MUXENTRY(USB0_DAT, 112, | ||
| 465 | "usb0_dat", "uart3_rx_irrx", "uart2_rx", "gpio_112", | ||
| 466 | "uart2_tx", NULL, NULL, NULL), | ||
| 467 | _OMAP2420_MUXENTRY(USB0_PUEN, 106, | ||
| 468 | "usb0_puen", "mcbsp2_dx", NULL, "gpio_106", | ||
| 469 | NULL, NULL, NULL, NULL), | ||
| 470 | _OMAP2420_MUXENTRY(USB0_RCV, 109, | ||
| 471 | "usb0_rcv", "mcbsp2_fsx", NULL, "gpio_109", | ||
| 472 | "uart2_cts", NULL, NULL, NULL), | ||
| 473 | _OMAP2420_MUXENTRY(USB0_SE0, 111, | ||
| 474 | "usb0_se0", "uart3_tx_irtx", "uart2_tx", "gpio_111", | ||
| 475 | "uart2_rx", NULL, NULL, NULL), | ||
| 476 | _OMAP2420_MUXENTRY(USB0_TXEN, 110, | ||
| 477 | "usb0_txen", "uart3_cts_rctx", "uart2_cts", "gpio_110", | ||
| 478 | NULL, NULL, NULL, NULL), | ||
| 479 | _OMAP2420_MUXENTRY(USB0_VM, 108, | ||
| 480 | "usb0_vm", "mcbsp2_clkx", NULL, "gpio_108", | ||
| 481 | "uart2_rx", NULL, NULL, NULL), | ||
| 482 | _OMAP2420_MUXENTRY(USB0_VP, 107, | ||
| 483 | "usb0_vp", "mcbsp2_dr", NULL, "gpio_107", | ||
| 484 | NULL, NULL, NULL, NULL), | ||
| 485 | _OMAP2420_MUXENTRY(VLYNQ_CLK, 13, | ||
| 486 | "vlynq_clk", "usb2_se0", "sys_ndmareq0", "gpio_13", | ||
| 487 | NULL, NULL, NULL, NULL), | ||
| 488 | _OMAP2420_MUXENTRY(VLYNQ_NLA, 58, | ||
| 489 | "vlynq_nla", NULL, NULL, "gpio_58", | ||
| 490 | "cam_d6", NULL, NULL, NULL), | ||
| 491 | _OMAP2420_MUXENTRY(VLYNQ_RX0, 15, | ||
| 492 | "vlynq_rx0", "usb2_tllse0", NULL, "gpio_15", | ||
| 493 | "cam_d7", NULL, NULL, NULL), | ||
| 494 | _OMAP2420_MUXENTRY(VLYNQ_RX1, 14, | ||
| 495 | "vlynq_rx1", "usb2_rcv", "sys_ndmareq1", "gpio_14", | ||
| 496 | "cam_d8", NULL, NULL, NULL), | ||
| 497 | _OMAP2420_MUXENTRY(VLYNQ_TX0, 17, | ||
| 498 | "vlynq_tx0", "usb2_txen", NULL, "gpio_17", | ||
| 499 | NULL, NULL, NULL, NULL), | ||
| 500 | _OMAP2420_MUXENTRY(VLYNQ_TX1, 16, | ||
| 501 | "vlynq_tx1", "usb2_dat", "sys_clkout2", "gpio_16", | ||
| 502 | NULL, NULL, NULL, NULL), | ||
| 503 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 504 | }; | ||
| 505 | |||
| 506 | /* | ||
| 507 | * Balls for 447-pin POP package | ||
| 508 | */ | ||
| 509 | #ifdef CONFIG_DEBUG_FS | ||
| 510 | struct omap_ball __initdata omap2420_pop_ball[] = { | ||
| 511 | _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL), | ||
| 512 | _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL), | ||
| 513 | _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL), | ||
| 514 | _OMAP2420_BALLENTRY(CAM_D3, "ab3", NULL), | ||
| 515 | _OMAP2420_BALLENTRY(CAM_D4, "v2", NULL), | ||
| 516 | _OMAP2420_BALLENTRY(CAM_D5, "ad3", NULL), | ||
| 517 | _OMAP2420_BALLENTRY(CAM_D6, "aa4", NULL), | ||
| 518 | _OMAP2420_BALLENTRY(CAM_D7, "ab4", NULL), | ||
| 519 | _OMAP2420_BALLENTRY(CAM_D8, "ac6", NULL), | ||
| 520 | _OMAP2420_BALLENTRY(CAM_D9, "ac7", NULL), | ||
| 521 | _OMAP2420_BALLENTRY(CAM_HS, "v4", NULL), | ||
| 522 | _OMAP2420_BALLENTRY(CAM_LCLK, "ad6", NULL), | ||
| 523 | _OMAP2420_BALLENTRY(CAM_VS, "p7", NULL), | ||
| 524 | _OMAP2420_BALLENTRY(CAM_XCLK, "w4", NULL), | ||
| 525 | _OMAP2420_BALLENTRY(DSS_ACBIAS, "ae8", NULL), | ||
| 526 | _OMAP2420_BALLENTRY(DSS_DATA10, "ac12", NULL), | ||
| 527 | _OMAP2420_BALLENTRY(DSS_DATA11, "ae11", NULL), | ||
| 528 | _OMAP2420_BALLENTRY(DSS_DATA12, "ae13", NULL), | ||
| 529 | _OMAP2420_BALLENTRY(DSS_DATA13, "ad13", NULL), | ||
| 530 | _OMAP2420_BALLENTRY(DSS_DATA14, "ac13", NULL), | ||
| 531 | _OMAP2420_BALLENTRY(DSS_DATA15, "y12", NULL), | ||
| 532 | _OMAP2420_BALLENTRY(DSS_DATA16, "ad14", NULL), | ||
| 533 | _OMAP2420_BALLENTRY(DSS_DATA17, "y13", NULL), | ||
| 534 | _OMAP2420_BALLENTRY(DSS_DATA8, "ad11", NULL), | ||
| 535 | _OMAP2420_BALLENTRY(DSS_DATA9, "ad12", NULL), | ||
| 536 | _OMAP2420_BALLENTRY(EAC_AC_DIN, "ad19", NULL), | ||
| 537 | _OMAP2420_BALLENTRY(EAC_AC_DOUT, "af22", NULL), | ||
| 538 | _OMAP2420_BALLENTRY(EAC_AC_FS, "ad16", NULL), | ||
| 539 | _OMAP2420_BALLENTRY(EAC_AC_MCLK, "y17", NULL), | ||
| 540 | _OMAP2420_BALLENTRY(EAC_AC_RST, "ae22", NULL), | ||
| 541 | _OMAP2420_BALLENTRY(EAC_AC_SCLK, "ac18", NULL), | ||
| 542 | _OMAP2420_BALLENTRY(EAC_BT_DIN, "u8", NULL), | ||
| 543 | _OMAP2420_BALLENTRY(EAC_BT_DOUT, "ad5", NULL), | ||
| 544 | _OMAP2420_BALLENTRY(EAC_BT_FS, "w7", NULL), | ||
| 545 | _OMAP2420_BALLENTRY(EAC_BT_SCLK, "ad4", NULL), | ||
| 546 | _OMAP2420_BALLENTRY(GPIO_119, "af6", NULL), | ||
| 547 | _OMAP2420_BALLENTRY(GPIO_120, "af4", NULL), | ||
| 548 | _OMAP2420_BALLENTRY(GPIO_121, "ae6", NULL), | ||
| 549 | _OMAP2420_BALLENTRY(GPIO_122, "w3", NULL), | ||
| 550 | _OMAP2420_BALLENTRY(GPIO_124, "y19", NULL), | ||
| 551 | _OMAP2420_BALLENTRY(GPIO_125, "ae24", NULL), | ||
| 552 | _OMAP2420_BALLENTRY(GPIO_36, "y18", NULL), | ||
| 553 | _OMAP2420_BALLENTRY(GPIO_6, "d6", NULL), | ||
| 554 | _OMAP2420_BALLENTRY(GPIO_62, "ad18", NULL), | ||
| 555 | _OMAP2420_BALLENTRY(GPMC_A1, "m8", NULL), | ||
| 556 | _OMAP2420_BALLENTRY(GPMC_A10, "d5", NULL), | ||
| 557 | _OMAP2420_BALLENTRY(GPMC_A2, "w9", NULL), | ||
| 558 | _OMAP2420_BALLENTRY(GPMC_A3, "af10", NULL), | ||
| 559 | _OMAP2420_BALLENTRY(GPMC_A4, "w8", NULL), | ||
| 560 | _OMAP2420_BALLENTRY(GPMC_A5, "ae16", NULL), | ||
| 561 | _OMAP2420_BALLENTRY(GPMC_A6, "af9", NULL), | ||
| 562 | _OMAP2420_BALLENTRY(GPMC_A7, "e4", NULL), | ||
| 563 | _OMAP2420_BALLENTRY(GPMC_A8, "j7", NULL), | ||
| 564 | _OMAP2420_BALLENTRY(GPMC_A9, "ae18", NULL), | ||
| 565 | _OMAP2420_BALLENTRY(GPMC_CLK, "p1", "l1"), | ||
| 566 | _OMAP2420_BALLENTRY(GPMC_D10, "t1", "n1"), | ||
| 567 | _OMAP2420_BALLENTRY(GPMC_D11, "u2", "p2"), | ||
| 568 | _OMAP2420_BALLENTRY(GPMC_D12, "u1", "p1"), | ||
| 569 | _OMAP2420_BALLENTRY(GPMC_D13, "p2", "m1"), | ||
| 570 | _OMAP2420_BALLENTRY(GPMC_D14, "h2", "j2"), | ||
| 571 | _OMAP2420_BALLENTRY(GPMC_D15, "h1", "k2"), | ||
| 572 | _OMAP2420_BALLENTRY(GPMC_D8, "v1", "r1"), | ||
| 573 | _OMAP2420_BALLENTRY(GPMC_D9, "y1", "t1"), | ||
| 574 | _OMAP2420_BALLENTRY(GPMC_NBE0, "af12", "aa10"), | ||
| 575 | _OMAP2420_BALLENTRY(GPMC_NBE1, "u3", NULL), | ||
| 576 | _OMAP2420_BALLENTRY(GPMC_NCS1, "af14", "w1"), | ||
| 577 | _OMAP2420_BALLENTRY(GPMC_NCS2, "g4", NULL), | ||
| 578 | _OMAP2420_BALLENTRY(GPMC_NCS3, "t8", NULL), | ||
| 579 | _OMAP2420_BALLENTRY(GPMC_NCS4, "h8", NULL), | ||
| 580 | _OMAP2420_BALLENTRY(GPMC_NCS5, "k3", NULL), | ||
| 581 | _OMAP2420_BALLENTRY(GPMC_NCS6, "m7", NULL), | ||
| 582 | _OMAP2420_BALLENTRY(GPMC_NCS7, "p3", NULL), | ||
| 583 | _OMAP2420_BALLENTRY(GPMC_NWP, "ae15", "y5"), | ||
| 584 | _OMAP2420_BALLENTRY(GPMC_WAIT1, "ae20", "y8"), | ||
| 585 | _OMAP2420_BALLENTRY(GPMC_WAIT2, "n2", NULL), | ||
| 586 | _OMAP2420_BALLENTRY(GPMC_WAIT3, "t4", NULL), | ||
| 587 | _OMAP2420_BALLENTRY(HDQ_SIO, "t23", NULL), | ||
| 588 | _OMAP2420_BALLENTRY(I2C2_SCL, "l2", NULL), | ||
| 589 | _OMAP2420_BALLENTRY(I2C2_SDA, "k19", NULL), | ||
| 590 | _OMAP2420_BALLENTRY(JTAG_EMU0, "n24", NULL), | ||
| 591 | _OMAP2420_BALLENTRY(JTAG_EMU1, "ac22", NULL), | ||
| 592 | _OMAP2420_BALLENTRY(MCBSP1_CLKR, "y24", NULL), | ||
| 593 | _OMAP2420_BALLENTRY(MCBSP1_CLKX, "t19", NULL), | ||
| 594 | _OMAP2420_BALLENTRY(MCBSP1_DR, "u23", NULL), | ||
| 595 | _OMAP2420_BALLENTRY(MCBSP1_DX, "r24", NULL), | ||
| 596 | _OMAP2420_BALLENTRY(MCBSP1_FSR, "r20", NULL), | ||
| 597 | _OMAP2420_BALLENTRY(MCBSP1_FSX, "r23", NULL), | ||
| 598 | _OMAP2420_BALLENTRY(MCBSP2_CLKX, "t24", NULL), | ||
| 599 | _OMAP2420_BALLENTRY(MCBSP2_DR, "p20", NULL), | ||
| 600 | _OMAP2420_BALLENTRY(MCBSP_CLKS, "p23", NULL), | ||
| 601 | _OMAP2420_BALLENTRY(MMC_CLKI, "c23", NULL), | ||
| 602 | _OMAP2420_BALLENTRY(MMC_CLKO, "h23", NULL), | ||
| 603 | _OMAP2420_BALLENTRY(MMC_CMD, "j23", NULL), | ||
| 604 | _OMAP2420_BALLENTRY(MMC_CMD_DIR, "j24", NULL), | ||
| 605 | _OMAP2420_BALLENTRY(MMC_DAT0, "h17", NULL), | ||
| 606 | _OMAP2420_BALLENTRY(MMC_DAT_DIR0, "f23", NULL), | ||
| 607 | _OMAP2420_BALLENTRY(MMC_DAT1, "g19", NULL), | ||
| 608 | _OMAP2420_BALLENTRY(MMC_DAT_DIR1, "d23", NULL), | ||
| 609 | _OMAP2420_BALLENTRY(MMC_DAT2, "h20", NULL), | ||
| 610 | _OMAP2420_BALLENTRY(MMC_DAT_DIR2, "g23", NULL), | ||
| 611 | _OMAP2420_BALLENTRY(MMC_DAT3, "d24", NULL), | ||
| 612 | _OMAP2420_BALLENTRY(MMC_DAT_DIR3, "e23", NULL), | ||
| 613 | _OMAP2420_BALLENTRY(SDRC_A12, "w26", "r21"), | ||
| 614 | _OMAP2420_BALLENTRY(SDRC_A13, "w25", "aa15"), | ||
| 615 | _OMAP2420_BALLENTRY(SDRC_A14, "aa26", "y12"), | ||
| 616 | _OMAP2420_BALLENTRY(SDRC_CKE1, "ae25", "y13"), | ||
| 617 | _OMAP2420_BALLENTRY(SDRC_NCS1, "y25", "t20"), | ||
| 618 | _OMAP2420_BALLENTRY(SPI1_CLK, "y23", NULL), | ||
| 619 | _OMAP2420_BALLENTRY(SPI1_NCS0, "w24", NULL), | ||
| 620 | _OMAP2420_BALLENTRY(SPI1_NCS1, "w23", NULL), | ||
| 621 | _OMAP2420_BALLENTRY(SPI1_NCS2, "v23", NULL), | ||
| 622 | _OMAP2420_BALLENTRY(SPI1_NCS3, "u20", NULL), | ||
| 623 | _OMAP2420_BALLENTRY(SPI1_SIMO, "h10", NULL), | ||
| 624 | _OMAP2420_BALLENTRY(SPI1_SOMI, "v19", NULL), | ||
| 625 | _OMAP2420_BALLENTRY(SPI2_CLK, "v24", NULL), | ||
| 626 | _OMAP2420_BALLENTRY(SPI2_NCS0, "aa24", NULL), | ||
| 627 | _OMAP2420_BALLENTRY(SPI2_SIMO, "u24", NULL), | ||
| 628 | _OMAP2420_BALLENTRY(SPI2_SOMI, "v25", NULL), | ||
| 629 | _OMAP2420_BALLENTRY(SSI1_DAT_RX, "w15", NULL), | ||
| 630 | _OMAP2420_BALLENTRY(SSI1_DAT_TX, "w13", NULL), | ||
| 631 | _OMAP2420_BALLENTRY(SSI1_FLAG_RX, "af11", NULL), | ||
| 632 | _OMAP2420_BALLENTRY(SSI1_FLAG_TX, "ac15", NULL), | ||
| 633 | _OMAP2420_BALLENTRY(SSI1_RDY_RX, "ac16", NULL), | ||
| 634 | _OMAP2420_BALLENTRY(SSI1_RDY_TX, "af15", NULL), | ||
| 635 | _OMAP2420_BALLENTRY(SSI1_WAKE, "ad15", NULL), | ||
| 636 | _OMAP2420_BALLENTRY(SYS_CLKOUT, "ae19", NULL), | ||
| 637 | _OMAP2420_BALLENTRY(SYS_CLKREQ, "ad20", NULL), | ||
| 638 | _OMAP2420_BALLENTRY(SYS_NIRQ, "y20", NULL), | ||
| 639 | _OMAP2420_BALLENTRY(UART1_CTS, "g20", NULL), | ||
| 640 | _OMAP2420_BALLENTRY(UART1_RTS, "k20", NULL), | ||
| 641 | _OMAP2420_BALLENTRY(UART1_RX, "t20", NULL), | ||
| 642 | _OMAP2420_BALLENTRY(UART1_TX, "h12", NULL), | ||
| 643 | _OMAP2420_BALLENTRY(UART2_CTS, "ac24", NULL), | ||
| 644 | _OMAP2420_BALLENTRY(UART2_RTS, "w20", NULL), | ||
| 645 | _OMAP2420_BALLENTRY(UART2_RX, "ad24", NULL), | ||
| 646 | _OMAP2420_BALLENTRY(UART2_TX, "ab24", NULL), | ||
| 647 | _OMAP2420_BALLENTRY(UART3_CTS_RCTX, "k24", NULL), | ||
| 648 | _OMAP2420_BALLENTRY(UART3_RTS_SD, "m20", NULL), | ||
| 649 | _OMAP2420_BALLENTRY(UART3_RX_IRRX, "h24", NULL), | ||
| 650 | _OMAP2420_BALLENTRY(UART3_TX_IRTX, "g24", NULL), | ||
| 651 | _OMAP2420_BALLENTRY(USB0_DAT, "j25", NULL), | ||
| 652 | _OMAP2420_BALLENTRY(USB0_PUEN, "l23", NULL), | ||
| 653 | _OMAP2420_BALLENTRY(USB0_RCV, "k23", NULL), | ||
| 654 | _OMAP2420_BALLENTRY(USB0_SE0, "l24", NULL), | ||
| 655 | _OMAP2420_BALLENTRY(USB0_TXEN, "m24", NULL), | ||
| 656 | _OMAP2420_BALLENTRY(USB0_VM, "n23", NULL), | ||
| 657 | _OMAP2420_BALLENTRY(USB0_VP, "m23", NULL), | ||
| 658 | _OMAP2420_BALLENTRY(VLYNQ_CLK, "w12", NULL), | ||
| 659 | _OMAP2420_BALLENTRY(VLYNQ_NLA, "ae10", NULL), | ||
| 660 | _OMAP2420_BALLENTRY(VLYNQ_RX0, "ad7", NULL), | ||
| 661 | _OMAP2420_BALLENTRY(VLYNQ_RX1, "w10", NULL), | ||
| 662 | _OMAP2420_BALLENTRY(VLYNQ_TX0, "y15", NULL), | ||
| 663 | _OMAP2420_BALLENTRY(VLYNQ_TX1, "w14", NULL), | ||
| 664 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 665 | }; | ||
| 666 | #else | ||
| 667 | #define omap2420_pop_ball NULL | ||
| 668 | #endif | ||
| 669 | |||
| 670 | int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags) | ||
| 671 | { | ||
| 672 | struct omap_ball *package_balls = NULL; | ||
| 673 | |||
| 674 | switch (flags & OMAP_PACKAGE_MASK) { | ||
| 675 | case OMAP_PACKAGE_ZAC: | ||
| 676 | package_balls = omap2420_pop_ball; | ||
| 677 | break; | ||
| 678 | case OMAP_PACKAGE_ZAF: | ||
| 679 | /* REVISIT: Please add data */ | ||
| 680 | default: | ||
| 681 | pr_warning("mux: No ball data available for omap2420 package\n"); | ||
| 682 | } | ||
| 683 | |||
| 684 | return omap_mux_init(OMAP2420_CONTROL_PADCONF_MUX_PBASE, | ||
| 685 | OMAP2420_CONTROL_PADCONF_MUX_SIZE, | ||
| 686 | omap2420_muxmodes, NULL, board_subset, | ||
| 687 | package_balls); | ||
| 688 | } | ||
diff --git a/arch/arm/mach-omap2/mux2420.h b/arch/arm/mach-omap2/mux2420.h new file mode 100644 index 000000000000..0f555aa847b5 --- /dev/null +++ b/arch/arm/mach-omap2/mux2420.h | |||
| @@ -0,0 +1,282 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Nokia | ||
| 3 | * Copyright (C) 2009 Texas Instruments | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define OMAP2420_CONTROL_PADCONF_MUX_PBASE 0x48000030LU | ||
| 11 | |||
| 12 | #define OMAP2420_MUX(mode0, mux_value) \ | ||
| 13 | { \ | ||
| 14 | .reg_offset = (OMAP2420_CONTROL_PADCONF_##mode0##_OFFSET), \ | ||
| 15 | .value = (mux_value), \ | ||
| 16 | } | ||
| 17 | |||
| 18 | /* | ||
| 19 | * OMAP2420 CONTROL_PADCONF* register offsets for pin-muxing | ||
| 20 | * | ||
| 21 | * Extracted from the TRM. Add 0x48000030 to these values to get the | ||
| 22 | * absolute addresses. The name in the macro is the mode-0 name of | ||
| 23 | * the pin. NOTE: These registers are 8-bits wide. | ||
| 24 | */ | ||
| 25 | #define OMAP2420_CONTROL_PADCONF_SDRC_A14_OFFSET 0x000 | ||
| 26 | #define OMAP2420_CONTROL_PADCONF_SDRC_A13_OFFSET 0x001 | ||
| 27 | #define OMAP2420_CONTROL_PADCONF_SDRC_A12_OFFSET 0x002 | ||
| 28 | #define OMAP2420_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x003 | ||
| 29 | #define OMAP2420_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x004 | ||
| 30 | #define OMAP2420_CONTROL_PADCONF_SDRC_A11_OFFSET 0x005 | ||
| 31 | #define OMAP2420_CONTROL_PADCONF_SDRC_A10_OFFSET 0x006 | ||
| 32 | #define OMAP2420_CONTROL_PADCONF_SDRC_A9_OFFSET 0x007 | ||
| 33 | #define OMAP2420_CONTROL_PADCONF_SDRC_A8_OFFSET 0x008 | ||
| 34 | #define OMAP2420_CONTROL_PADCONF_SDRC_A7_OFFSET 0x009 | ||
| 35 | #define OMAP2420_CONTROL_PADCONF_SDRC_A6_OFFSET 0x00a | ||
| 36 | #define OMAP2420_CONTROL_PADCONF_SDRC_A5_OFFSET 0x00b | ||
| 37 | #define OMAP2420_CONTROL_PADCONF_SDRC_A4_OFFSET 0x00c | ||
| 38 | #define OMAP2420_CONTROL_PADCONF_SDRC_A3_OFFSET 0x00d | ||
| 39 | #define OMAP2420_CONTROL_PADCONF_SDRC_A2_OFFSET 0x00e | ||
| 40 | #define OMAP2420_CONTROL_PADCONF_SDRC_A1_OFFSET 0x00f | ||
| 41 | #define OMAP2420_CONTROL_PADCONF_SDRC_A0_OFFSET 0x010 | ||
| 42 | #define OMAP2420_CONTROL_PADCONF_SDRC_D31_OFFSET 0x021 | ||
| 43 | #define OMAP2420_CONTROL_PADCONF_SDRC_D30_OFFSET 0x022 | ||
| 44 | #define OMAP2420_CONTROL_PADCONF_SDRC_D29_OFFSET 0x023 | ||
| 45 | #define OMAP2420_CONTROL_PADCONF_SDRC_D28_OFFSET 0x024 | ||
| 46 | #define OMAP2420_CONTROL_PADCONF_SDRC_D27_OFFSET 0x025 | ||
| 47 | #define OMAP2420_CONTROL_PADCONF_SDRC_D26_OFFSET 0x026 | ||
| 48 | #define OMAP2420_CONTROL_PADCONF_SDRC_D25_OFFSET 0x027 | ||
| 49 | #define OMAP2420_CONTROL_PADCONF_SDRC_D24_OFFSET 0x028 | ||
| 50 | #define OMAP2420_CONTROL_PADCONF_SDRC_D23_OFFSET 0x029 | ||
| 51 | #define OMAP2420_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02a | ||
| 52 | #define OMAP2420_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02b | ||
| 53 | #define OMAP2420_CONTROL_PADCONF_SDRC_D20_OFFSET 0x02c | ||
| 54 | #define OMAP2420_CONTROL_PADCONF_SDRC_D19_OFFSET 0x02d | ||
| 55 | #define OMAP2420_CONTROL_PADCONF_SDRC_D18_OFFSET 0x02e | ||
| 56 | #define OMAP2420_CONTROL_PADCONF_SDRC_D17_OFFSET 0x02f | ||
| 57 | #define OMAP2420_CONTROL_PADCONF_SDRC_D16_OFFSET 0x030 | ||
| 58 | #define OMAP2420_CONTROL_PADCONF_SDRC_D15_OFFSET 0x031 | ||
| 59 | #define OMAP2420_CONTROL_PADCONF_SDRC_D14_OFFSET 0x032 | ||
| 60 | #define OMAP2420_CONTROL_PADCONF_SDRC_D13_OFFSET 0x033 | ||
| 61 | #define OMAP2420_CONTROL_PADCONF_SDRC_D12_OFFSET 0x034 | ||
| 62 | #define OMAP2420_CONTROL_PADCONF_SDRC_D11_OFFSET 0x035 | ||
| 63 | #define OMAP2420_CONTROL_PADCONF_SDRC_D10_OFFSET 0x036 | ||
| 64 | #define OMAP2420_CONTROL_PADCONF_SDRC_D9_OFFSET 0x037 | ||
| 65 | #define OMAP2420_CONTROL_PADCONF_SDRC_D8_OFFSET 0x038 | ||
| 66 | #define OMAP2420_CONTROL_PADCONF_SDRC_D7_OFFSET 0x039 | ||
| 67 | #define OMAP2420_CONTROL_PADCONF_SDRC_D6_OFFSET 0x03a | ||
| 68 | #define OMAP2420_CONTROL_PADCONF_SDRC_D5_OFFSET 0x03b | ||
| 69 | #define OMAP2420_CONTROL_PADCONF_SDRC_D4_OFFSET 0x03c | ||
| 70 | #define OMAP2420_CONTROL_PADCONF_SDRC_D3_OFFSET 0x03d | ||
| 71 | #define OMAP2420_CONTROL_PADCONF_SDRC_D2_OFFSET 0x03e | ||
| 72 | #define OMAP2420_CONTROL_PADCONF_SDRC_D1_OFFSET 0x03f | ||
| 73 | #define OMAP2420_CONTROL_PADCONF_SDRC_D0_OFFSET 0x040 | ||
| 74 | #define OMAP2420_CONTROL_PADCONF_GPMC_A10_OFFSET 0x041 | ||
| 75 | #define OMAP2420_CONTROL_PADCONF_GPMC_A9_OFFSET 0x042 | ||
| 76 | #define OMAP2420_CONTROL_PADCONF_GPMC_A8_OFFSET 0x043 | ||
| 77 | #define OMAP2420_CONTROL_PADCONF_GPMC_A7_OFFSET 0x044 | ||
| 78 | #define OMAP2420_CONTROL_PADCONF_GPMC_A6_OFFSET 0x045 | ||
| 79 | #define OMAP2420_CONTROL_PADCONF_GPMC_A5_OFFSET 0x046 | ||
| 80 | #define OMAP2420_CONTROL_PADCONF_GPMC_A4_OFFSET 0x047 | ||
| 81 | #define OMAP2420_CONTROL_PADCONF_GPMC_A3_OFFSET 0x048 | ||
| 82 | #define OMAP2420_CONTROL_PADCONF_GPMC_A2_OFFSET 0x049 | ||
| 83 | #define OMAP2420_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a | ||
| 84 | #define OMAP2420_CONTROL_PADCONF_GPMC_D15_OFFSET 0x04b | ||
| 85 | #define OMAP2420_CONTROL_PADCONF_GPMC_D14_OFFSET 0x04c | ||
| 86 | #define OMAP2420_CONTROL_PADCONF_GPMC_D13_OFFSET 0x04d | ||
| 87 | #define OMAP2420_CONTROL_PADCONF_GPMC_D12_OFFSET 0x04e | ||
| 88 | #define OMAP2420_CONTROL_PADCONF_GPMC_D11_OFFSET 0x04f | ||
| 89 | #define OMAP2420_CONTROL_PADCONF_GPMC_D10_OFFSET 0x050 | ||
| 90 | #define OMAP2420_CONTROL_PADCONF_GPMC_D9_OFFSET 0x051 | ||
| 91 | #define OMAP2420_CONTROL_PADCONF_GPMC_D8_OFFSET 0x052 | ||
| 92 | #define OMAP2420_CONTROL_PADCONF_GPMC_D7_OFFSET 0x053 | ||
| 93 | #define OMAP2420_CONTROL_PADCONF_GPMC_D6_OFFSET 0x054 | ||
| 94 | #define OMAP2420_CONTROL_PADCONF_GPMC_D5_OFFSET 0x055 | ||
| 95 | #define OMAP2420_CONTROL_PADCONF_GPMC_D4_OFFSET 0x056 | ||
| 96 | #define OMAP2420_CONTROL_PADCONF_GPMC_D3_OFFSET 0x057 | ||
| 97 | #define OMAP2420_CONTROL_PADCONF_GPMC_D2_OFFSET 0x058 | ||
| 98 | #define OMAP2420_CONTROL_PADCONF_GPMC_D1_OFFSET 0x059 | ||
| 99 | #define OMAP2420_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05a | ||
| 100 | #define OMAP2420_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x05b | ||
| 101 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x05c | ||
| 102 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x05d | ||
| 103 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x05e | ||
| 104 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x05f | ||
| 105 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x060 | ||
| 106 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x061 | ||
| 107 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x062 | ||
| 108 | #define OMAP2420_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x063 | ||
| 109 | #define OMAP2420_CONTROL_PADCONF_GPMC_NALE_ALE_OFFSET 0x064 | ||
| 110 | #define OMAP2420_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x065 | ||
| 111 | #define OMAP2420_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x066 | ||
| 112 | #define OMAP2420_CONTROL_PADCONF_GPMC_NBE0_OFFSET 0x067 | ||
| 113 | #define OMAP2420_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x068 | ||
| 114 | #define OMAP2420_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x069 | ||
| 115 | #define OMAP2420_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x06a | ||
| 116 | #define OMAP2420_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x06b | ||
| 117 | #define OMAP2420_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x06c | ||
| 118 | #define OMAP2420_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x06d | ||
| 119 | #define OMAP2420_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x06e | ||
| 120 | #define OMAP2420_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x06f | ||
| 121 | #define OMAP2420_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x070 | ||
| 122 | #define OMAP2420_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x071 | ||
| 123 | #define OMAP2420_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x072 | ||
| 124 | #define OMAP2420_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x073 | ||
| 125 | #define OMAP2420_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x074 | ||
| 126 | #define OMAP2420_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x075 | ||
| 127 | #define OMAP2420_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x076 | ||
| 128 | #define OMAP2420_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x077 | ||
| 129 | #define OMAP2420_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x078 | ||
| 130 | #define OMAP2420_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x079 | ||
| 131 | #define OMAP2420_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x07a | ||
| 132 | #define OMAP2420_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x07f | ||
| 133 | #define OMAP2420_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x080 | ||
| 134 | #define OMAP2420_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x081 | ||
| 135 | #define OMAP2420_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x082 | ||
| 136 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x083 | ||
| 137 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x084 | ||
| 138 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x085 | ||
| 139 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x086 | ||
| 140 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x087 | ||
| 141 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x088 | ||
| 142 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x089 | ||
| 143 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x08a | ||
| 144 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x08b | ||
| 145 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x08c | ||
| 146 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x08d | ||
| 147 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x08e | ||
| 148 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x08f | ||
| 149 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x090 | ||
| 150 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x091 | ||
| 151 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x092 | ||
| 152 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x093 | ||
| 153 | #define OMAP2420_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x094 | ||
| 154 | #define OMAP2420_CONTROL_PADCONF_UART1_CTS_OFFSET 0x095 | ||
| 155 | #define OMAP2420_CONTROL_PADCONF_UART1_RTS_OFFSET 0x096 | ||
| 156 | #define OMAP2420_CONTROL_PADCONF_UART1_TX_OFFSET 0x097 | ||
| 157 | #define OMAP2420_CONTROL_PADCONF_UART1_RX_OFFSET 0x098 | ||
| 158 | #define OMAP2420_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x099 | ||
| 159 | #define OMAP2420_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x09a | ||
| 160 | #define OMAP2420_CONTROL_PADCONF_DSS_PCL_OFFSET 0x09b | ||
| 161 | #define OMAP2420_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x09c | ||
| 162 | #define OMAP2420_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x09d | ||
| 163 | #define OMAP2420_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x09e | ||
| 164 | #define OMAP2420_CONTROL_PADCONF_CAM_D9_OFFSET 0x09f | ||
| 165 | #define OMAP2420_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a0 | ||
| 166 | #define OMAP2420_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a1 | ||
| 167 | #define OMAP2420_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a2 | ||
| 168 | #define OMAP2420_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a3 | ||
| 169 | #define OMAP2420_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a4 | ||
| 170 | #define OMAP2420_CONTROL_PADCONF_CAM_D3_OFFSET 0x0a5 | ||
| 171 | #define OMAP2420_CONTROL_PADCONF_CAM_D2_OFFSET 0x0a6 | ||
| 172 | #define OMAP2420_CONTROL_PADCONF_CAM_D1_OFFSET 0x0a7 | ||
| 173 | #define OMAP2420_CONTROL_PADCONF_CAM_D0_OFFSET 0x0a8 | ||
| 174 | #define OMAP2420_CONTROL_PADCONF_CAM_HS_OFFSET 0x0a9 | ||
| 175 | #define OMAP2420_CONTROL_PADCONF_CAM_VS_OFFSET 0x0aa | ||
| 176 | #define OMAP2420_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0ab | ||
| 177 | #define OMAP2420_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0ac | ||
| 178 | #define OMAP2420_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0ad | ||
| 179 | #define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0ae | ||
| 180 | #define OMAP2420_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0af | ||
| 181 | #define OMAP2420_CONTROL_PADCONF_GPIO_62_OFFSET 0x0b0 | ||
| 182 | #define OMAP2420_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0b1 | ||
| 183 | #define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0b2 | ||
| 184 | #define OMAP2420_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0b3 | ||
| 185 | #define OMAP2420_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0b4 | ||
| 186 | #define OMAP2420_CONTROL_PADCONF_VLYNQ_CLK_OFFSET 0x0b5 | ||
| 187 | #define OMAP2420_CONTROL_PADCONF_VLYNQ_RX1_OFFSET 0x0b6 | ||
| 188 | #define OMAP2420_CONTROL_PADCONF_VLYNQ_RX0_OFFSET 0x0b7 | ||
| 189 | #define OMAP2420_CONTROL_PADCONF_VLYNQ_TX1_OFFSET 0x0b8 | ||
| 190 | #define OMAP2420_CONTROL_PADCONF_VLYNQ_TX0_OFFSET 0x0b9 | ||
| 191 | #define OMAP2420_CONTROL_PADCONF_VLYNQ_NLA_OFFSET 0x0ba | ||
| 192 | #define OMAP2420_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0bb | ||
| 193 | #define OMAP2420_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0bc | ||
| 194 | #define OMAP2420_CONTROL_PADCONF_UART2_TX_OFFSET 0x0bd | ||
| 195 | #define OMAP2420_CONTROL_PADCONF_UART2_RX_OFFSET 0x0be | ||
| 196 | #define OMAP2420_CONTROL_PADCONF_EAC_BT_SCLK_OFFSET 0x0bf | ||
| 197 | #define OMAP2420_CONTROL_PADCONF_EAC_BT_FS_OFFSET 0x0c0 | ||
| 198 | #define OMAP2420_CONTROL_PADCONF_EAC_BT_DIN_OFFSET 0x0c1 | ||
| 199 | #define OMAP2420_CONTROL_PADCONF_EAC_BT_DOUT_OFFSET 0x0c2 | ||
| 200 | #define OMAP2420_CONTROL_PADCONF_MMC_CLKO_OFFSET 0x0c3 | ||
| 201 | #define OMAP2420_CONTROL_PADCONF_MMC_CMD_OFFSET 0x0c4 | ||
| 202 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT0_OFFSET 0x0c5 | ||
| 203 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT1_OFFSET 0x0c6 | ||
| 204 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT2_OFFSET 0x0c7 | ||
| 205 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT3_OFFSET 0x0c8 | ||
| 206 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR0_OFFSET 0x0c9 | ||
| 207 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR1_OFFSET 0x0ca | ||
| 208 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR2_OFFSET 0x0cb | ||
| 209 | #define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR3_OFFSET 0x0cc | ||
| 210 | #define OMAP2420_CONTROL_PADCONF_MMC_CMD_DIR_OFFSET 0x0cd | ||
| 211 | #define OMAP2420_CONTROL_PADCONF_MMC_CLKI_OFFSET 0x0ce | ||
| 212 | #define OMAP2420_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0cf | ||
| 213 | #define OMAP2420_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0d0 | ||
| 214 | #define OMAP2420_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0d1 | ||
| 215 | #define OMAP2420_CONTROL_PADCONF_SPI1_NCS0_OFFSET 0x0d2 | ||
| 216 | #define OMAP2420_CONTROL_PADCONF_SPI1_NCS1_OFFSET 0x0d3 | ||
| 217 | #define OMAP2420_CONTROL_PADCONF_SPI1_NCS2_OFFSET 0x0d4 | ||
| 218 | #define OMAP2420_CONTROL_PADCONF_SPI1_NCS3_OFFSET 0x0d5 | ||
| 219 | #define OMAP2420_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0d6 | ||
| 220 | #define OMAP2420_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0d7 | ||
| 221 | #define OMAP2420_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0d8 | ||
| 222 | #define OMAP2420_CONTROL_PADCONF_SPI2_NCS0_OFFSET 0x0d9 | ||
| 223 | #define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0da | ||
| 224 | #define OMAP2420_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0db | ||
| 225 | #define OMAP2420_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0dc | ||
| 226 | #define OMAP2420_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0dd | ||
| 227 | #define OMAP2420_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0de | ||
| 228 | #define OMAP2420_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0df | ||
| 229 | #define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0e0 | ||
| 230 | #define OMAP2420_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0e1 | ||
| 231 | #define OMAP2420_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0e2 | ||
| 232 | #define OMAP2420_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0e3 | ||
| 233 | #define OMAP2420_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0e4 | ||
| 234 | #define OMAP2420_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0e5 | ||
| 235 | #define OMAP2420_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0e6 | ||
| 236 | #define OMAP2420_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0e7 | ||
| 237 | #define OMAP2420_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0e8 | ||
| 238 | #define OMAP2420_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0e9 | ||
| 239 | #define OMAP2420_CONTROL_PADCONF_TV_CVBS_OFFSET 0x0ea | ||
| 240 | #define OMAP2420_CONTROL_PADCONF_TV_VREF_OFFSET 0x0eb | ||
| 241 | #define OMAP2420_CONTROL_PADCONF_TV_RREF_OFFSET 0x0ec | ||
| 242 | #define OMAP2420_CONTROL_PADCONF_USB0_PUEN_OFFSET 0x0ed | ||
| 243 | #define OMAP2420_CONTROL_PADCONF_USB0_VP_OFFSET 0x0ee | ||
| 244 | #define OMAP2420_CONTROL_PADCONF_USB0_VM_OFFSET 0x0ef | ||
| 245 | #define OMAP2420_CONTROL_PADCONF_USB0_RCV_OFFSET 0x0f0 | ||
| 246 | #define OMAP2420_CONTROL_PADCONF_USB0_TXEN_OFFSET 0x0f1 | ||
| 247 | #define OMAP2420_CONTROL_PADCONF_USB0_SE0_OFFSET 0x0f2 | ||
| 248 | #define OMAP2420_CONTROL_PADCONF_USB0_DAT_OFFSET 0x0f3 | ||
| 249 | #define OMAP2420_CONTROL_PADCONF_EAC_AC_SCLK_OFFSET 0x0f4 | ||
| 250 | #define OMAP2420_CONTROL_PADCONF_EAC_AC_FS_OFFSET 0x0f5 | ||
| 251 | #define OMAP2420_CONTROL_PADCONF_EAC_AC_DIN_OFFSET 0x0f6 | ||
| 252 | #define OMAP2420_CONTROL_PADCONF_EAC_AC_DOUT_OFFSET 0x0f7 | ||
| 253 | #define OMAP2420_CONTROL_PADCONF_EAC_AC_MCLK_OFFSET 0x0f8 | ||
| 254 | #define OMAP2420_CONTROL_PADCONF_EAC_AC_RST_OFFSET 0x0f9 | ||
| 255 | #define OMAP2420_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x0fa | ||
| 256 | #define OMAP2420_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x0fb | ||
| 257 | #define OMAP2420_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x0fc | ||
| 258 | #define OMAP2420_CONTROL_PADCONF_SYS_NV_OFFSET 0x0fd | ||
| 259 | #define OMAP2420_CONTROL_PADCONF_GPIO_119_OFFSET 0x0fe | ||
| 260 | #define OMAP2420_CONTROL_PADCONF_GPIO_120_OFFSET 0x0ff | ||
| 261 | #define OMAP2420_CONTROL_PADCONF_GPIO_121_OFFSET 0x100 | ||
| 262 | #define OMAP2420_CONTROL_PADCONF_GPIO_122_OFFSET 0x101 | ||
| 263 | #define OMAP2420_CONTROL_PADCONF_SYS_32K_OFFSET 0x102 | ||
| 264 | #define OMAP2420_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x103 | ||
| 265 | #define OMAP2420_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x104 | ||
| 266 | #define OMAP2420_CONTROL_PADCONF_GPIO_36_OFFSET 0x105 | ||
| 267 | #define OMAP2420_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x106 | ||
| 268 | #define OMAP2420_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x107 | ||
| 269 | #define OMAP2420_CONTROL_PADCONF_GPIO_6_OFFSET 0x108 | ||
| 270 | #define OMAP2420_CONTROL_PADCONF_GPIO_124_OFFSET 0x109 | ||
| 271 | #define OMAP2420_CONTROL_PADCONF_GPIO_125_OFFSET 0x10a | ||
| 272 | #define OMAP2420_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x10b | ||
| 273 | #define OMAP2420_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x10c | ||
| 274 | #define OMAP2420_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x10d | ||
| 275 | #define OMAP2420_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x10e | ||
| 276 | #define OMAP2420_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x10f | ||
| 277 | #define OMAP2420_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x110 | ||
| 278 | #define OMAP2420_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x111 | ||
| 279 | #define OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x112 | ||
| 280 | |||
| 281 | #define OMAP2420_CONTROL_PADCONF_MUX_SIZE \ | ||
| 282 | (OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x1) | ||
diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c new file mode 100644 index 000000000000..7dcaaa8af32a --- /dev/null +++ b/arch/arm/mach-omap2/mux2430.c | |||
| @@ -0,0 +1,791 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Nokia | ||
| 3 | * Copyright (C) 2010 Texas Instruments | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/module.h> | ||
| 11 | #include <linux/init.h> | ||
| 12 | |||
| 13 | #include "mux.h" | ||
| 14 | |||
| 15 | #ifdef CONFIG_OMAP_MUX | ||
| 16 | |||
| 17 | #define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ | ||
| 18 | { \ | ||
| 19 | .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \ | ||
| 20 | .gpio = (g), \ | ||
| 21 | .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ | ||
| 22 | } | ||
| 23 | |||
| 24 | #else | ||
| 25 | |||
| 26 | #define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ | ||
| 27 | { \ | ||
| 28 | .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \ | ||
| 29 | .gpio = (g), \ | ||
| 30 | } | ||
| 31 | |||
| 32 | #endif | ||
| 33 | |||
| 34 | #define _OMAP2430_BALLENTRY(M0, bb, bt) \ | ||
| 35 | { \ | ||
| 36 | .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \ | ||
| 37 | .balls = { bb, bt }, \ | ||
| 38 | } | ||
| 39 | |||
| 40 | /* | ||
| 41 | * Superset of all mux modes for omap2430 | ||
| 42 | */ | ||
| 43 | static struct omap_mux __initdata omap2430_muxmodes[] = { | ||
| 44 | _OMAP2430_MUXENTRY(CAM_D0, 133, | ||
| 45 | "cam_d0", "hw_dbg0", "sti_dout", "gpio_133", | ||
| 46 | NULL, NULL, "etk_d2", "safe_mode"), | ||
| 47 | _OMAP2430_MUXENTRY(CAM_D10, 146, | ||
| 48 | "cam_d10", NULL, NULL, "gpio_146", | ||
| 49 | NULL, NULL, "etk_d12", "safe_mode"), | ||
| 50 | _OMAP2430_MUXENTRY(CAM_D11, 145, | ||
| 51 | "cam_d11", NULL, NULL, "gpio_145", | ||
| 52 | NULL, NULL, "etk_d13", "safe_mode"), | ||
| 53 | _OMAP2430_MUXENTRY(CAM_D1, 132, | ||
| 54 | "cam_d1", "hw_dbg1", "sti_din", "gpio_132", | ||
| 55 | NULL, NULL, "etk_d3", "safe_mode"), | ||
| 56 | _OMAP2430_MUXENTRY(CAM_D2, 129, | ||
| 57 | "cam_d2", "hw_dbg2", "mcbsp1_clkx", "gpio_129", | ||
| 58 | NULL, NULL, "etk_d4", "safe_mode"), | ||
| 59 | _OMAP2430_MUXENTRY(CAM_D3, 128, | ||
| 60 | "cam_d3", "hw_dbg3", "mcbsp1_dr", "gpio_128", | ||
| 61 | NULL, NULL, "etk_d5", "safe_mode"), | ||
| 62 | _OMAP2430_MUXENTRY(CAM_D4, 143, | ||
| 63 | "cam_d4", "hw_dbg4", "mcbsp1_fsr", "gpio_143", | ||
| 64 | NULL, NULL, "etk_d6", "safe_mode"), | ||
| 65 | _OMAP2430_MUXENTRY(CAM_D5, 112, | ||
| 66 | "cam_d5", "hw_dbg5", "mcbsp1_clkr", "gpio_112", | ||
| 67 | NULL, NULL, "etk_d7", "safe_mode"), | ||
| 68 | _OMAP2430_MUXENTRY(CAM_D6, 137, | ||
| 69 | "cam_d6", "hw_dbg6", NULL, "gpio_137", | ||
| 70 | NULL, NULL, "etk_d8", "safe_mode"), | ||
| 71 | _OMAP2430_MUXENTRY(CAM_D7, 136, | ||
| 72 | "cam_d7", "hw_dbg7", NULL, "gpio_136", | ||
| 73 | NULL, NULL, "etk_d9", "safe_mode"), | ||
| 74 | _OMAP2430_MUXENTRY(CAM_D8, 135, | ||
| 75 | "cam_d8", "hw_dbg8", NULL, "gpio_135", | ||
| 76 | NULL, NULL, "etk_d10", "safe_mode"), | ||
| 77 | _OMAP2430_MUXENTRY(CAM_D9, 134, | ||
| 78 | "cam_d9", "hw_dbg9", NULL, "gpio_134", | ||
| 79 | NULL, NULL, "etk_d11", "safe_mode"), | ||
| 80 | _OMAP2430_MUXENTRY(CAM_HS, 11, | ||
| 81 | "cam_hs", "hw_dbg10", "mcbsp1_dx", "gpio_11", | ||
| 82 | NULL, NULL, "etk_d1", "safe_mode"), | ||
| 83 | _OMAP2430_MUXENTRY(CAM_LCLK, 0, | ||
| 84 | "cam_lclk", NULL, "mcbsp_clks", NULL, | ||
| 85 | NULL, NULL, "etk_c1", "safe_mode"), | ||
| 86 | _OMAP2430_MUXENTRY(CAM_VS, 12, | ||
| 87 | "cam_vs", "hw_dbg11", "mcbsp1_fsx", "gpio_12", | ||
| 88 | NULL, NULL, "etk_d0", "safe_mode"), | ||
| 89 | _OMAP2430_MUXENTRY(CAM_XCLK, 0, | ||
| 90 | "cam_xclk", NULL, "sti_clk", NULL, | ||
| 91 | NULL, NULL, "etk_c2", NULL), | ||
| 92 | _OMAP2430_MUXENTRY(DSS_ACBIAS, 48, | ||
| 93 | "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48", | ||
| 94 | NULL, NULL, NULL, "safe_mode"), | ||
| 95 | _OMAP2430_MUXENTRY(DSS_DATA0, 40, | ||
| 96 | "dss_data0", "uart1_cts", NULL, "gpio_40", | ||
| 97 | NULL, NULL, NULL, "safe_mode"), | ||
| 98 | _OMAP2430_MUXENTRY(DSS_DATA10, 128, | ||
| 99 | "dss_data10", "sdi_data1n", NULL, "gpio_128", | ||
| 100 | NULL, NULL, NULL, "safe_mode"), | ||
| 101 | _OMAP2430_MUXENTRY(DSS_DATA11, 129, | ||
| 102 | "dss_data11", "sdi_data1p", NULL, "gpio_129", | ||
| 103 | NULL, NULL, NULL, "safe_mode"), | ||
| 104 | _OMAP2430_MUXENTRY(DSS_DATA12, 130, | ||
| 105 | "dss_data12", "sdi_data2n", NULL, "gpio_130", | ||
| 106 | NULL, NULL, NULL, "safe_mode"), | ||
| 107 | _OMAP2430_MUXENTRY(DSS_DATA13, 131, | ||
| 108 | "dss_data13", "sdi_data2p", NULL, "gpio_131", | ||
| 109 | NULL, NULL, NULL, "safe_mode"), | ||
| 110 | _OMAP2430_MUXENTRY(DSS_DATA14, 132, | ||
| 111 | "dss_data14", "sdi_data3n", NULL, "gpio_132", | ||
| 112 | NULL, NULL, NULL, "safe_mode"), | ||
| 113 | _OMAP2430_MUXENTRY(DSS_DATA15, 133, | ||
| 114 | "dss_data15", "sdi_data3p", NULL, "gpio_133", | ||
| 115 | NULL, NULL, NULL, "safe_mode"), | ||
| 116 | _OMAP2430_MUXENTRY(DSS_DATA16, 46, | ||
| 117 | "dss_data16", NULL, NULL, "gpio_46", | ||
| 118 | NULL, NULL, NULL, "safe_mode"), | ||
| 119 | _OMAP2430_MUXENTRY(DSS_DATA17, 47, | ||
| 120 | "dss_data17", NULL, NULL, "gpio_47", | ||
| 121 | NULL, NULL, NULL, "safe_mode"), | ||
| 122 | _OMAP2430_MUXENTRY(DSS_DATA1, 41, | ||
| 123 | "dss_data1", "uart1_rts", NULL, "gpio_41", | ||
| 124 | NULL, NULL, NULL, "safe_mode"), | ||
| 125 | _OMAP2430_MUXENTRY(DSS_DATA2, 42, | ||
| 126 | "dss_data2", "uart1_tx", NULL, "gpio_42", | ||
| 127 | NULL, NULL, NULL, "safe_mode"), | ||
| 128 | _OMAP2430_MUXENTRY(DSS_DATA3, 43, | ||
| 129 | "dss_data3", "uart1_rx", NULL, "gpio_43", | ||
| 130 | NULL, NULL, NULL, "safe_mode"), | ||
| 131 | _OMAP2430_MUXENTRY(DSS_DATA4, 44, | ||
| 132 | "dss_data4", "uart3_rx_irrx", NULL, "gpio_44", | ||
| 133 | NULL, NULL, NULL, "safe_mode"), | ||
| 134 | _OMAP2430_MUXENTRY(DSS_DATA5, 45, | ||
| 135 | "dss_data5", "uart3_tx_irtx", NULL, "gpio_45", | ||
| 136 | NULL, NULL, NULL, "safe_mode"), | ||
| 137 | _OMAP2430_MUXENTRY(DSS_DATA6, 144, | ||
| 138 | "dss_data6", NULL, NULL, "gpio_144", | ||
| 139 | NULL, NULL, NULL, "safe_mode"), | ||
| 140 | _OMAP2430_MUXENTRY(DSS_DATA7, 147, | ||
| 141 | "dss_data7", NULL, NULL, "gpio_147", | ||
| 142 | NULL, NULL, NULL, "safe_mode"), | ||
| 143 | _OMAP2430_MUXENTRY(DSS_DATA8, 38, | ||
| 144 | "dss_data8", NULL, NULL, "gpio_38", | ||
| 145 | NULL, NULL, NULL, "safe_mode"), | ||
| 146 | _OMAP2430_MUXENTRY(DSS_DATA9, 39, | ||
| 147 | "dss_data9", NULL, NULL, "gpio_39", | ||
| 148 | NULL, NULL, NULL, "safe_mode"), | ||
| 149 | _OMAP2430_MUXENTRY(DSS_HSYNC, 110, | ||
| 150 | "dss_hsync", NULL, NULL, "gpio_110", | ||
| 151 | NULL, NULL, NULL, "safe_mode"), | ||
| 152 | _OMAP2430_MUXENTRY(GPIO_113, 113, | ||
| 153 | "gpio_113", "mcbsp2_clkx", NULL, "gpio_113", | ||
| 154 | NULL, NULL, NULL, "safe_mode"), | ||
| 155 | _OMAP2430_MUXENTRY(GPIO_114, 114, | ||
| 156 | "gpio_114", "mcbsp2_fsx", NULL, "gpio_114", | ||
| 157 | NULL, NULL, NULL, "safe_mode"), | ||
| 158 | _OMAP2430_MUXENTRY(GPIO_115, 115, | ||
| 159 | "gpio_115", "mcbsp2_dr", NULL, "gpio_115", | ||
| 160 | NULL, NULL, NULL, "safe_mode"), | ||
| 161 | _OMAP2430_MUXENTRY(GPIO_116, 116, | ||
| 162 | "gpio_116", "mcbsp2_dx", NULL, "gpio_116", | ||
| 163 | NULL, NULL, NULL, "safe_mode"), | ||
| 164 | _OMAP2430_MUXENTRY(GPIO_128, 128, | ||
| 165 | "gpio_128", NULL, "sti_din", "gpio_128", | ||
| 166 | NULL, "sys_boot0", NULL, "safe_mode"), | ||
| 167 | _OMAP2430_MUXENTRY(GPIO_129, 129, | ||
| 168 | "gpio_129", NULL, "sti_dout", "gpio_129", | ||
| 169 | NULL, "sys_boot1", NULL, "safe_mode"), | ||
| 170 | _OMAP2430_MUXENTRY(GPIO_130, 130, | ||
| 171 | "gpio_130", NULL, NULL, "gpio_130", | ||
| 172 | "jtag_emu2", "sys_boot2", NULL, "safe_mode"), | ||
| 173 | _OMAP2430_MUXENTRY(GPIO_131, 131, | ||
| 174 | "gpio_131", NULL, NULL, "gpio_131", | ||
| 175 | "jtag_emu3", "sys_boot3", NULL, "safe_mode"), | ||
| 176 | _OMAP2430_MUXENTRY(GPIO_132, 132, | ||
| 177 | "gpio_132", NULL, NULL, "gpio_132", | ||
| 178 | NULL, "sys_boot4", NULL, "safe_mode"), | ||
| 179 | _OMAP2430_MUXENTRY(GPIO_133, 133, | ||
| 180 | "gpio_133", NULL, NULL, "gpio_133", | ||
| 181 | NULL, "sys_boot5", NULL, "safe_mode"), | ||
| 182 | _OMAP2430_MUXENTRY(GPIO_134, 134, | ||
| 183 | "gpio_134", "ccp_datn", NULL, "gpio_134", | ||
| 184 | NULL, NULL, NULL, "safe_mode"), | ||
| 185 | _OMAP2430_MUXENTRY(GPIO_135, 135, | ||
| 186 | "gpio_135", "ccp_datp", NULL, "gpio_135", | ||
| 187 | NULL, NULL, NULL, "safe_mode"), | ||
| 188 | _OMAP2430_MUXENTRY(GPIO_136, 136, | ||
| 189 | "gpio_136", "ccp_clkn", NULL, "gpio_136", | ||
| 190 | NULL, NULL, NULL, "safe_mode"), | ||
| 191 | _OMAP2430_MUXENTRY(GPIO_137, 137, | ||
| 192 | "gpio_137", "ccp_clkp", NULL, "gpio_137", | ||
| 193 | NULL, NULL, NULL, "safe_mode"), | ||
| 194 | _OMAP2430_MUXENTRY(GPIO_138, 138, | ||
| 195 | "gpio_138", "spi3_clk", NULL, "gpio_138", | ||
| 196 | NULL, NULL, NULL, "safe_mode"), | ||
| 197 | _OMAP2430_MUXENTRY(GPIO_139, 139, | ||
| 198 | "gpio_139", "spi3_cs0", "sys_ndmareq3", "gpio_139", | ||
| 199 | NULL, NULL, NULL, "safe_mode"), | ||
| 200 | _OMAP2430_MUXENTRY(GPIO_140, 140, | ||
| 201 | "gpio_140", "spi3_simo", "sys_ndmareq4", "gpio_140", | ||
| 202 | NULL, NULL, "etk_d14", "safe_mode"), | ||
| 203 | _OMAP2430_MUXENTRY(GPIO_141, 141, | ||
| 204 | "gpio_141", "spi3_somi", NULL, "gpio_141", | ||
| 205 | NULL, NULL, NULL, "safe_mode"), | ||
| 206 | _OMAP2430_MUXENTRY(GPIO_142, 142, | ||
| 207 | "gpio_142", "spi3_cs1", "sys_ndmareq2", "gpio_142", | ||
| 208 | NULL, NULL, "etk_d15", "safe_mode"), | ||
| 209 | _OMAP2430_MUXENTRY(GPIO_148, 148, | ||
| 210 | "gpio_148", "mcbsp5_fsx", NULL, "gpio_148", | ||
| 211 | NULL, NULL, NULL, "safe_mode"), | ||
| 212 | _OMAP2430_MUXENTRY(GPIO_149, 149, | ||
| 213 | "gpio_149", "mcbsp5_dx", NULL, "gpio_149", | ||
| 214 | NULL, NULL, NULL, "safe_mode"), | ||
| 215 | _OMAP2430_MUXENTRY(GPIO_150, 150, | ||
| 216 | "gpio_150", "mcbsp5_dr", NULL, "gpio_150", | ||
| 217 | NULL, NULL, NULL, "safe_mode"), | ||
| 218 | _OMAP2430_MUXENTRY(GPIO_151, 151, | ||
| 219 | "gpio_151", "sys_pwrok", NULL, "gpio_151", | ||
| 220 | NULL, NULL, NULL, "safe_mode"), | ||
| 221 | _OMAP2430_MUXENTRY(GPIO_152, 152, | ||
| 222 | "gpio_152", "uart1_cts", "sys_ndmareq1", "gpio_152", | ||
| 223 | NULL, NULL, NULL, "safe_mode"), | ||
| 224 | _OMAP2430_MUXENTRY(GPIO_153, 153, | ||
| 225 | "gpio_153", "uart1_rx", "sys_ndmareq0", "gpio_153", | ||
| 226 | NULL, NULL, NULL, "safe_mode"), | ||
| 227 | _OMAP2430_MUXENTRY(GPIO_154, 154, | ||
| 228 | "gpio_154", "mcbsp5_clkx", NULL, "gpio_154", | ||
| 229 | NULL, NULL, NULL, "safe_mode"), | ||
| 230 | _OMAP2430_MUXENTRY(GPIO_63, 63, | ||
| 231 | "gpio_63", "mcbsp4_clkx", NULL, "gpio_63", | ||
| 232 | NULL, NULL, NULL, "safe_mode"), | ||
| 233 | _OMAP2430_MUXENTRY(GPIO_78, 78, | ||
| 234 | "gpio_78", NULL, "uart2_rts", "gpio_78", | ||
| 235 | "uart3_rts_sd", NULL, NULL, "safe_mode"), | ||
| 236 | _OMAP2430_MUXENTRY(GPIO_79, 79, | ||
| 237 | "gpio_79", "secure_indicator", "uart2_tx", "gpio_79", | ||
| 238 | "uart3_tx_irtx", NULL, NULL, "safe_mode"), | ||
| 239 | _OMAP2430_MUXENTRY(GPIO_7, 7, | ||
| 240 | "gpio_7", NULL, "uart2_cts", "gpio_7", | ||
| 241 | "uart3_cts_rctx", NULL, NULL, "safe_mode"), | ||
| 242 | _OMAP2430_MUXENTRY(GPIO_80, 80, | ||
| 243 | "gpio_80", NULL, "uart2_rx", "gpio_80", | ||
| 244 | "uart3_rx_irrx", NULL, NULL, "safe_mode"), | ||
| 245 | _OMAP2430_MUXENTRY(GPMC_A10, 3, | ||
| 246 | "gpmc_a10", NULL, "sys_ndmareq0", "gpio_3", | ||
| 247 | NULL, NULL, NULL, "safe_mode"), | ||
| 248 | _OMAP2430_MUXENTRY(GPMC_A1, 31, | ||
| 249 | "gpmc_a1", NULL, NULL, "gpio_31", | ||
| 250 | NULL, NULL, NULL, "safe_mode"), | ||
| 251 | _OMAP2430_MUXENTRY(GPMC_A2, 30, | ||
| 252 | "gpmc_a2", NULL, NULL, "gpio_30", | ||
| 253 | NULL, NULL, NULL, "safe_mode"), | ||
| 254 | _OMAP2430_MUXENTRY(GPMC_A3, 29, | ||
| 255 | "gpmc_a3", NULL, NULL, "gpio_29", | ||
| 256 | NULL, NULL, NULL, "safe_mode"), | ||
| 257 | _OMAP2430_MUXENTRY(GPMC_A4, 49, | ||
| 258 | "gpmc_a4", NULL, NULL, "gpio_49", | ||
| 259 | NULL, NULL, NULL, "safe_mode"), | ||
| 260 | _OMAP2430_MUXENTRY(GPMC_A5, 53, | ||
| 261 | "gpmc_a5", NULL, NULL, "gpio_53", | ||
| 262 | NULL, NULL, NULL, "safe_mode"), | ||
| 263 | _OMAP2430_MUXENTRY(GPMC_A6, 52, | ||
| 264 | "gpmc_a6", NULL, NULL, "gpio_52", | ||
| 265 | NULL, NULL, NULL, "safe_mode"), | ||
| 266 | _OMAP2430_MUXENTRY(GPMC_A7, 6, | ||
| 267 | "gpmc_a7", NULL, NULL, "gpio_6", | ||
| 268 | NULL, NULL, NULL, "safe_mode"), | ||
| 269 | _OMAP2430_MUXENTRY(GPMC_A8, 5, | ||
| 270 | "gpmc_a8", NULL, NULL, "gpio_5", | ||
| 271 | NULL, NULL, NULL, "safe_mode"), | ||
| 272 | _OMAP2430_MUXENTRY(GPMC_A9, 4, | ||
| 273 | "gpmc_a9", NULL, "sys_ndmareq1", "gpio_4", | ||
| 274 | NULL, NULL, NULL, "safe_mode"), | ||
| 275 | _OMAP2430_MUXENTRY(GPMC_CLK, 21, | ||
| 276 | "gpmc_clk", NULL, NULL, "gpio_21", | ||
| 277 | NULL, NULL, NULL, "safe_mode"), | ||
| 278 | _OMAP2430_MUXENTRY(GPMC_D10, 18, | ||
| 279 | "gpmc_d10", NULL, NULL, "gpio_18", | ||
| 280 | NULL, NULL, NULL, "safe_mode"), | ||
| 281 | _OMAP2430_MUXENTRY(GPMC_D11, 57, | ||
| 282 | "gpmc_d11", NULL, NULL, "gpio_57", | ||
| 283 | NULL, NULL, NULL, "safe_mode"), | ||
| 284 | _OMAP2430_MUXENTRY(GPMC_D12, 77, | ||
| 285 | "gpmc_d12", NULL, NULL, "gpio_77", | ||
| 286 | NULL, NULL, NULL, "safe_mode"), | ||
| 287 | _OMAP2430_MUXENTRY(GPMC_D13, 76, | ||
| 288 | "gpmc_d13", NULL, NULL, "gpio_76", | ||
| 289 | NULL, NULL, NULL, "safe_mode"), | ||
| 290 | _OMAP2430_MUXENTRY(GPMC_D14, 55, | ||
| 291 | "gpmc_d14", NULL, NULL, "gpio_55", | ||
| 292 | NULL, NULL, NULL, "safe_mode"), | ||
| 293 | _OMAP2430_MUXENTRY(GPMC_D15, 54, | ||
| 294 | "gpmc_d15", NULL, NULL, "gpio_54", | ||
| 295 | NULL, NULL, NULL, "safe_mode"), | ||
| 296 | _OMAP2430_MUXENTRY(GPMC_D8, 20, | ||
| 297 | "gpmc_d8", NULL, NULL, "gpio_20", | ||
| 298 | NULL, NULL, NULL, "safe_mode"), | ||
| 299 | _OMAP2430_MUXENTRY(GPMC_D9, 19, | ||
| 300 | "gpmc_d9", NULL, NULL, "gpio_19", | ||
| 301 | NULL, NULL, NULL, "safe_mode"), | ||
| 302 | _OMAP2430_MUXENTRY(GPMC_NCS1, 22, | ||
| 303 | "gpmc_ncs1", NULL, NULL, "gpio_22", | ||
| 304 | NULL, NULL, NULL, "safe_mode"), | ||
| 305 | _OMAP2430_MUXENTRY(GPMC_NCS2, 23, | ||
| 306 | "gpmc_ncs2", NULL, NULL, "gpio_23", | ||
| 307 | NULL, NULL, NULL, "safe_mode"), | ||
| 308 | _OMAP2430_MUXENTRY(GPMC_NCS3, 24, | ||
| 309 | "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24", | ||
| 310 | NULL, NULL, NULL, "safe_mode"), | ||
| 311 | _OMAP2430_MUXENTRY(GPMC_NCS4, 25, | ||
| 312 | "gpmc_ncs4", NULL, NULL, "gpio_25", | ||
| 313 | NULL, NULL, NULL, "safe_mode"), | ||
| 314 | _OMAP2430_MUXENTRY(GPMC_NCS5, 26, | ||
| 315 | "gpmc_ncs5", NULL, NULL, "gpio_26", | ||
| 316 | NULL, NULL, NULL, "safe_mode"), | ||
| 317 | _OMAP2430_MUXENTRY(GPMC_NCS6, 27, | ||
| 318 | "gpmc_ncs6", NULL, NULL, "gpio_27", | ||
| 319 | NULL, NULL, NULL, "safe_mode"), | ||
| 320 | _OMAP2430_MUXENTRY(GPMC_NCS7, 28, | ||
| 321 | "gpmc_ncs7", "gpmc_io_dir", NULL, "gpio_28", | ||
| 322 | NULL, NULL, NULL, "safe_mode"), | ||
| 323 | _OMAP2430_MUXENTRY(GPMC_WAIT1, 33, | ||
| 324 | "gpmc_wait1", NULL, NULL, "gpio_33", | ||
| 325 | NULL, NULL, NULL, "safe_mode"), | ||
| 326 | _OMAP2430_MUXENTRY(GPMC_WAIT2, 34, | ||
| 327 | "gpmc_wait2", NULL, NULL, "gpio_34", | ||
| 328 | NULL, NULL, NULL, "safe_mode"), | ||
| 329 | _OMAP2430_MUXENTRY(GPMC_WAIT3, 35, | ||
| 330 | "gpmc_wait3", NULL, NULL, "gpio_35", | ||
| 331 | NULL, NULL, NULL, "safe_mode"), | ||
| 332 | _OMAP2430_MUXENTRY(HDQ_SIO, 101, | ||
| 333 | "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101", | ||
| 334 | "uart3_rx_irrx", NULL, NULL, "safe_mode"), | ||
| 335 | _OMAP2430_MUXENTRY(I2C1_SCL, 50, | ||
| 336 | "i2c1_scl", NULL, NULL, "gpio_50", | ||
| 337 | NULL, NULL, NULL, "safe_mode"), | ||
| 338 | _OMAP2430_MUXENTRY(I2C1_SDA, 51, | ||
| 339 | "i2c1_sda", NULL, NULL, "gpio_51", | ||
| 340 | NULL, NULL, NULL, "safe_mode"), | ||
| 341 | _OMAP2430_MUXENTRY(I2C2_SCL, 99, | ||
| 342 | "i2c2_scl", NULL, NULL, "gpio_99", | ||
| 343 | NULL, NULL, NULL, "safe_mode"), | ||
| 344 | _OMAP2430_MUXENTRY(I2C2_SDA, 100, | ||
| 345 | "i2c2_sda", NULL, NULL, "gpio_100", | ||
| 346 | NULL, NULL, NULL, "safe_mode"), | ||
| 347 | _OMAP2430_MUXENTRY(JTAG_EMU0, 127, | ||
| 348 | "jtag_emu0", "secure_indicator", NULL, "gpio_127", | ||
| 349 | NULL, NULL, NULL, "safe_mode"), | ||
| 350 | _OMAP2430_MUXENTRY(JTAG_EMU1, 126, | ||
| 351 | "jtag_emu1", NULL, NULL, "gpio_126", | ||
| 352 | NULL, NULL, NULL, "safe_mode"), | ||
| 353 | _OMAP2430_MUXENTRY(MCBSP1_CLKR, 92, | ||
| 354 | "mcbsp1_clkr", "ssi2_dat_tx", NULL, "gpio_92", | ||
| 355 | NULL, NULL, NULL, "safe_mode"), | ||
| 356 | _OMAP2430_MUXENTRY(MCBSP1_CLKX, 98, | ||
| 357 | "mcbsp1_clkx", "ssi2_wake", NULL, "gpio_98", | ||
| 358 | NULL, NULL, NULL, "safe_mode"), | ||
| 359 | _OMAP2430_MUXENTRY(MCBSP1_DR, 95, | ||
| 360 | "mcbsp1_dr", "ssi2_dat_rx", NULL, "gpio_95", | ||
| 361 | NULL, NULL, NULL, "safe_mode"), | ||
| 362 | _OMAP2430_MUXENTRY(MCBSP1_DX, 94, | ||
| 363 | "mcbsp1_dx", "ssi2_rdy_tx", NULL, "gpio_94", | ||
| 364 | NULL, NULL, NULL, "safe_mode"), | ||
| 365 | _OMAP2430_MUXENTRY(MCBSP1_FSR, 93, | ||
| 366 | "mcbsp1_fsr", "ssi2_flag_tx", NULL, "gpio_93", | ||
| 367 | "spi2_cs1", NULL, NULL, "safe_mode"), | ||
| 368 | _OMAP2430_MUXENTRY(MCBSP1_FSX, 97, | ||
| 369 | "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97", | ||
| 370 | NULL, NULL, NULL, "safe_mode"), | ||
| 371 | _OMAP2430_MUXENTRY(MCBSP2_CLKX, 147, | ||
| 372 | "mcbsp2_clkx", "sdi_clkp", "dss_data23", "gpio_147", | ||
| 373 | NULL, NULL, NULL, "safe_mode"), | ||
| 374 | _OMAP2430_MUXENTRY(MCBSP2_DR, 144, | ||
| 375 | "mcbsp2_dr", "sdi_clkn", "dss_data22", "gpio_144", | ||
| 376 | NULL, NULL, NULL, "safe_mode"), | ||
| 377 | _OMAP2430_MUXENTRY(MCBSP3_CLKX, 71, | ||
| 378 | "mcbsp3_clkx", NULL, NULL, "gpio_71", | ||
| 379 | NULL, NULL, NULL, "safe_mode"), | ||
| 380 | _OMAP2430_MUXENTRY(MCBSP3_DR, 73, | ||
| 381 | "mcbsp3_dr", NULL, NULL, "gpio_73", | ||
| 382 | NULL, NULL, NULL, "safe_mode"), | ||
| 383 | _OMAP2430_MUXENTRY(MCBSP3_DX, 74, | ||
| 384 | "mcbsp3_dx", NULL, "sti_clk", "gpio_74", | ||
| 385 | NULL, NULL, NULL, "safe_mode"), | ||
| 386 | _OMAP2430_MUXENTRY(MCBSP3_FSX, 72, | ||
| 387 | "mcbsp3_fsx", NULL, NULL, "gpio_72", | ||
| 388 | NULL, NULL, NULL, "safe_mode"), | ||
| 389 | _OMAP2430_MUXENTRY(MCBSP_CLKS, 96, | ||
| 390 | "mcbsp_clks", "ssi2_flag_rx", NULL, "gpio_96", | ||
| 391 | NULL, NULL, NULL, "safe_mode"), | ||
| 392 | _OMAP2430_MUXENTRY(SDMMC1_CLKO, 0, | ||
| 393 | "sdmmc1_clko", "ms_clko", NULL, NULL, | ||
| 394 | NULL, "hw_dbg9", "hw_dbg3", "safe_mode"), | ||
| 395 | _OMAP2430_MUXENTRY(SDMMC1_CMD, 0, | ||
| 396 | "sdmmc1_cmd", "ms_bs", NULL, NULL, | ||
| 397 | NULL, "hw_dbg8", "hw_dbg2", "safe_mode"), | ||
| 398 | _OMAP2430_MUXENTRY(SDMMC1_DAT0, 0, | ||
| 399 | "sdmmc1_dat0", "ms_dat0", NULL, NULL, | ||
| 400 | NULL, "hw_dbg7", "hw_dbg1", "safe_mode"), | ||
| 401 | _OMAP2430_MUXENTRY(SDMMC1_DAT1, 75, | ||
| 402 | "sdmmc1_dat1", "ms_dat1", NULL, "gpio_75", | ||
| 403 | NULL, "hw_dbg6", "hw_dbg0", "safe_mode"), | ||
| 404 | _OMAP2430_MUXENTRY(SDMMC1_DAT2, 0, | ||
| 405 | "sdmmc1_dat2", "ms_dat2", NULL, NULL, | ||
| 406 | NULL, "hw_dbg5", "hw_dbg10", "safe_mode"), | ||
| 407 | _OMAP2430_MUXENTRY(SDMMC1_DAT3, 0, | ||
| 408 | "sdmmc1_dat3", "ms_dat3", NULL, NULL, | ||
| 409 | NULL, "hw_dbg4", "hw_dbg11", "safe_mode"), | ||
| 410 | _OMAP2430_MUXENTRY(SDMMC2_CLKO, 13, | ||
| 411 | "sdmmc2_clko", NULL, NULL, "gpio_13", | ||
| 412 | NULL, "spi3_clk", NULL, "safe_mode"), | ||
| 413 | _OMAP2430_MUXENTRY(SDMMC2_CMD, 15, | ||
| 414 | "sdmmc2_cmd", "usb2_rcv", NULL, "gpio_15", | ||
| 415 | NULL, "spi3_simo", NULL, "safe_mode"), | ||
| 416 | _OMAP2430_MUXENTRY(SDMMC2_DAT0, 16, | ||
| 417 | "sdmmc2_dat0", "usb2_tllse0", NULL, "gpio_16", | ||
| 418 | NULL, "spi3_somi", NULL, "safe_mode"), | ||
| 419 | _OMAP2430_MUXENTRY(SDMMC2_DAT1, 58, | ||
| 420 | "sdmmc2_dat1", "usb2_txen", NULL, "gpio_58", | ||
| 421 | NULL, NULL, NULL, "safe_mode"), | ||
| 422 | _OMAP2430_MUXENTRY(SDMMC2_DAT2, 17, | ||
| 423 | "sdmmc2_dat2", "usb2_dat", NULL, "gpio_17", | ||
| 424 | NULL, "spi3_cs1", NULL, "safe_mode"), | ||
| 425 | _OMAP2430_MUXENTRY(SDMMC2_DAT3, 14, | ||
| 426 | "sdmmc2_dat3", "usb2_se0", NULL, "gpio_14", | ||
| 427 | NULL, "spi3_cs0", NULL, "safe_mode"), | ||
| 428 | _OMAP2430_MUXENTRY(SDRC_A12, 2, | ||
| 429 | "sdrc_a12", NULL, NULL, "gpio_2", | ||
| 430 | NULL, NULL, NULL, "safe_mode"), | ||
| 431 | _OMAP2430_MUXENTRY(SDRC_A13, 1, | ||
| 432 | "sdrc_a13", NULL, NULL, "gpio_1", | ||
| 433 | NULL, NULL, NULL, "safe_mode"), | ||
| 434 | _OMAP2430_MUXENTRY(SDRC_A14, 0, | ||
| 435 | "sdrc_a14", NULL, NULL, "gpio_0", | ||
| 436 | NULL, NULL, NULL, "safe_mode"), | ||
| 437 | _OMAP2430_MUXENTRY(SDRC_CKE1, 36, | ||
| 438 | "sdrc_cke1", NULL, NULL, "gpio_36", | ||
| 439 | NULL, NULL, NULL, "safe_mode"), | ||
| 440 | _OMAP2430_MUXENTRY(SDRC_NCS1, 37, | ||
| 441 | "sdrc_ncs1", NULL, NULL, "gpio_37", | ||
| 442 | NULL, NULL, NULL, "safe_mode"), | ||
| 443 | _OMAP2430_MUXENTRY(SPI1_CLK, 81, | ||
| 444 | "spi1_clk", NULL, NULL, "gpio_81", | ||
| 445 | NULL, NULL, NULL, "safe_mode"), | ||
| 446 | _OMAP2430_MUXENTRY(SPI1_CS0, 84, | ||
| 447 | "spi1_cs0", NULL, NULL, "gpio_84", | ||
| 448 | NULL, NULL, NULL, "safe_mode"), | ||
| 449 | _OMAP2430_MUXENTRY(SPI1_CS1, 85, | ||
| 450 | "spi1_cs1", NULL, NULL, "gpio_85", | ||
| 451 | NULL, NULL, NULL, "safe_mode"), | ||
| 452 | _OMAP2430_MUXENTRY(SPI1_CS2, 86, | ||
| 453 | "spi1_cs2", NULL, NULL, "gpio_86", | ||
| 454 | NULL, NULL, NULL, "safe_mode"), | ||
| 455 | _OMAP2430_MUXENTRY(SPI1_CS3, 87, | ||
| 456 | "spi1_cs3", "spi2_cs1", NULL, "gpio_87", | ||
| 457 | NULL, NULL, NULL, "safe_mode"), | ||
| 458 | _OMAP2430_MUXENTRY(SPI1_SIMO, 82, | ||
| 459 | "spi1_simo", NULL, NULL, "gpio_82", | ||
| 460 | NULL, NULL, NULL, "safe_mode"), | ||
| 461 | _OMAP2430_MUXENTRY(SPI1_SOMI, 83, | ||
| 462 | "spi1_somi", NULL, NULL, "gpio_83", | ||
| 463 | NULL, NULL, NULL, "safe_mode"), | ||
| 464 | _OMAP2430_MUXENTRY(SPI2_CLK, 88, | ||
| 465 | "spi2_clk", "gpt9_pwm_evt", NULL, "gpio_88", | ||
| 466 | NULL, NULL, NULL, "safe_mode"), | ||
| 467 | _OMAP2430_MUXENTRY(SPI2_CS0, 91, | ||
| 468 | "spi2_cs0", "gpt12_pwm_evt", NULL, "gpio_91", | ||
| 469 | NULL, NULL, NULL, "safe_mode"), | ||
| 470 | _OMAP2430_MUXENTRY(SPI2_SIMO, 89, | ||
| 471 | "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89", | ||
| 472 | NULL, NULL, NULL, "safe_mode"), | ||
| 473 | _OMAP2430_MUXENTRY(SPI2_SOMI, 90, | ||
| 474 | "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90", | ||
| 475 | NULL, NULL, NULL, "safe_mode"), | ||
| 476 | _OMAP2430_MUXENTRY(SSI1_DAT_RX, 62, | ||
| 477 | "ssi1_dat_rx", "uart1_rx", "usb1_dat", "gpio_62", | ||
| 478 | NULL, NULL, NULL, "safe_mode"), | ||
| 479 | _OMAP2430_MUXENTRY(SSI1_DAT_TX, 59, | ||
| 480 | "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59", | ||
| 481 | NULL, NULL, NULL, "safe_mode"), | ||
| 482 | _OMAP2430_MUXENTRY(SSI1_FLAG_RX, 64, | ||
| 483 | "ssi1_flag_rx", "mcbsp4_dr", NULL, "gpio_64", | ||
| 484 | NULL, NULL, NULL, "safe_mode"), | ||
| 485 | _OMAP2430_MUXENTRY(SSI1_FLAG_TX, 60, | ||
| 486 | "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_60", | ||
| 487 | NULL, NULL, NULL, "safe_mode"), | ||
| 488 | _OMAP2430_MUXENTRY(SSI1_RDY_RX, 65, | ||
| 489 | "ssi1_rdy_rx", "mcbsp4_dx", NULL, "gpio_65", | ||
| 490 | NULL, NULL, NULL, "safe_mode"), | ||
| 491 | _OMAP2430_MUXENTRY(SSI1_RDY_TX, 61, | ||
| 492 | "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61", | ||
| 493 | NULL, NULL, NULL, "safe_mode"), | ||
| 494 | _OMAP2430_MUXENTRY(SSI1_WAKE, 66, | ||
| 495 | "ssi1_wake", "mcbsp4_fsx", NULL, "gpio_66", | ||
| 496 | NULL, NULL, NULL, "safe_mode"), | ||
| 497 | _OMAP2430_MUXENTRY(SYS_CLKOUT, 111, | ||
| 498 | "sys_clkout", NULL, NULL, "gpio_111", | ||
| 499 | NULL, NULL, NULL, "safe_mode"), | ||
| 500 | _OMAP2430_MUXENTRY(SYS_DRM_MSECURE, 118, | ||
| 501 | "sys_drm_msecure", NULL, "sys_ndmareq6", "gpio_118", | ||
| 502 | NULL, NULL, NULL, "safe_mode"), | ||
| 503 | _OMAP2430_MUXENTRY(SYS_NIRQ0, 56, | ||
| 504 | "sys_nirq0", NULL, NULL, "gpio_56", | ||
| 505 | NULL, NULL, NULL, "safe_mode"), | ||
| 506 | _OMAP2430_MUXENTRY(SYS_NIRQ1, 125, | ||
| 507 | "sys_nirq1", NULL, "sys_ndmareq5", "gpio_125", | ||
| 508 | NULL, NULL, NULL, "safe_mode"), | ||
| 509 | _OMAP2430_MUXENTRY(UART1_CTS, 32, | ||
| 510 | "uart1_cts", "sdi_vsync", "dss_data18", "gpio_32", | ||
| 511 | "mcbsp5_clkx", NULL, NULL, "safe_mode"), | ||
| 512 | _OMAP2430_MUXENTRY(UART1_RTS, 8, | ||
| 513 | "uart1_rts", "sdi_hsync", "dss_data19", "gpio_8", | ||
| 514 | "mcbsp5_fsx", NULL, NULL, "safe_mode"), | ||
| 515 | _OMAP2430_MUXENTRY(UART1_RX, 10, | ||
| 516 | "uart1_rx", "sdi_stp", "dss_data21", "gpio_10", | ||
| 517 | "mcbsp5_dr", NULL, NULL, "safe_mode"), | ||
| 518 | _OMAP2430_MUXENTRY(UART1_TX, 9, | ||
| 519 | "uart1_tx", "sdi_den", "dss_data20", "gpio_9", | ||
| 520 | "mcbsp5_dx", NULL, NULL, "safe_mode"), | ||
| 521 | _OMAP2430_MUXENTRY(UART2_CTS, 67, | ||
| 522 | "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67", | ||
| 523 | NULL, NULL, NULL, "safe_mode"), | ||
| 524 | _OMAP2430_MUXENTRY(UART2_RTS, 68, | ||
| 525 | "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68", | ||
| 526 | NULL, NULL, NULL, "safe_mode"), | ||
| 527 | _OMAP2430_MUXENTRY(UART2_RX, 70, | ||
| 528 | "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70", | ||
| 529 | NULL, NULL, NULL, "safe_mode"), | ||
| 530 | _OMAP2430_MUXENTRY(UART2_TX, 69, | ||
| 531 | "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69", | ||
| 532 | NULL, NULL, NULL, "safe_mode"), | ||
| 533 | _OMAP2430_MUXENTRY(UART3_CTS_RCTX, 102, | ||
| 534 | "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102", | ||
| 535 | NULL, NULL, NULL, "safe_mode"), | ||
| 536 | _OMAP2430_MUXENTRY(UART3_RTS_SD, 103, | ||
| 537 | "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103", | ||
| 538 | NULL, NULL, NULL, "safe_mode"), | ||
| 539 | _OMAP2430_MUXENTRY(UART3_RX_IRRX, 105, | ||
| 540 | "uart3_rx_irrx", NULL, NULL, "gpio_105", | ||
| 541 | NULL, NULL, NULL, "safe_mode"), | ||
| 542 | _OMAP2430_MUXENTRY(UART3_TX_IRTX, 104, | ||
| 543 | "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104", | ||
| 544 | NULL, NULL, NULL, "safe_mode"), | ||
| 545 | _OMAP2430_MUXENTRY(USB0HS_CLK, 120, | ||
| 546 | "usb0hs_clk", NULL, NULL, "gpio_120", | ||
| 547 | NULL, NULL, NULL, "safe_mode"), | ||
| 548 | _OMAP2430_MUXENTRY(USB0HS_DATA0, 0, | ||
| 549 | "usb0hs_data0", "uart3_tx_irtx", NULL, NULL, | ||
| 550 | "usb0_txen", NULL, NULL, "safe_mode"), | ||
| 551 | _OMAP2430_MUXENTRY(USB0HS_DATA1, 0, | ||
| 552 | "usb0hs_data1", "uart3_rx_irrx", NULL, NULL, | ||
| 553 | "usb0_dat", NULL, NULL, "safe_mode"), | ||
| 554 | _OMAP2430_MUXENTRY(USB0HS_DATA2, 0, | ||
| 555 | "usb0hs_data2", "uart3_rts_sd", NULL, NULL, | ||
| 556 | "usb0_se0", NULL, NULL, "safe_mode"), | ||
| 557 | _OMAP2430_MUXENTRY(USB0HS_DATA3, 106, | ||
| 558 | "usb0hs_data3", NULL, "uart3_cts_rctx", "gpio_106", | ||
| 559 | "usb0_puen", NULL, NULL, "safe_mode"), | ||
| 560 | _OMAP2430_MUXENTRY(USB0HS_DATA4, 107, | ||
| 561 | "usb0hs_data4", "mcbsp2_dr", NULL, "gpio_107", | ||
| 562 | "usb0_vp", NULL, NULL, "safe_mode"), | ||
| 563 | _OMAP2430_MUXENTRY(USB0HS_DATA5, 108, | ||
| 564 | "usb0hs_data5", "mcbsp2_dx", NULL, "gpio_108", | ||
| 565 | "usb0_vm", NULL, NULL, "safe_mode"), | ||
| 566 | _OMAP2430_MUXENTRY(USB0HS_DATA6, 109, | ||
| 567 | "usb0hs_data6", "mcbsp2_fsx", NULL, "gpio_109", | ||
| 568 | "usb0_rcv", NULL, NULL, "safe_mode"), | ||
| 569 | _OMAP2430_MUXENTRY(USB0HS_DATA7, 124, | ||
| 570 | "usb0hs_data7", "mcbsp2_clkx", NULL, "gpio_124", | ||
| 571 | NULL, NULL, NULL, "safe_mode"), | ||
| 572 | _OMAP2430_MUXENTRY(USB0HS_DIR, 121, | ||
| 573 | "usb0hs_dir", NULL, NULL, "gpio_121", | ||
| 574 | NULL, NULL, NULL, "safe_mode"), | ||
| 575 | _OMAP2430_MUXENTRY(USB0HS_NXT, 123, | ||
| 576 | "usb0hs_nxt", NULL, NULL, "gpio_123", | ||
| 577 | NULL, NULL, NULL, "safe_mode"), | ||
| 578 | _OMAP2430_MUXENTRY(USB0HS_STP, 122, | ||
| 579 | "usb0hs_stp", NULL, NULL, "gpio_122", | ||
| 580 | NULL, NULL, NULL, "safe_mode"), | ||
| 581 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 582 | }; | ||
| 583 | |||
| 584 | /* | ||
| 585 | * Balls for POP package | ||
| 586 | * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom) | ||
| 587 | */ | ||
| 588 | #ifdef CONFIG_DEBUG_FS | ||
| 589 | struct omap_ball __initdata omap2430_pop_ball[] = { | ||
| 590 | _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL), | ||
| 591 | _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL), | ||
| 592 | _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL), | ||
| 593 | _OMAP2430_BALLENTRY(CAM_D11, "w3", NULL), | ||
| 594 | _OMAP2430_BALLENTRY(CAM_D2, "r2", NULL), | ||
| 595 | _OMAP2430_BALLENTRY(CAM_D3, "u3", NULL), | ||
| 596 | _OMAP2430_BALLENTRY(CAM_D4, "u2", NULL), | ||
| 597 | _OMAP2430_BALLENTRY(CAM_D5, "v1", NULL), | ||
| 598 | _OMAP2430_BALLENTRY(CAM_D6, "t3", NULL), | ||
| 599 | _OMAP2430_BALLENTRY(CAM_D7, "r3", NULL), | ||
| 600 | _OMAP2430_BALLENTRY(CAM_D8, "u7", NULL), | ||
| 601 | _OMAP2430_BALLENTRY(CAM_D9, "t7", NULL), | ||
| 602 | _OMAP2430_BALLENTRY(CAM_HS, "p2", NULL), | ||
| 603 | _OMAP2430_BALLENTRY(CAM_LCLK, "r7", NULL), | ||
| 604 | _OMAP2430_BALLENTRY(CAM_VS, "n2", NULL), | ||
| 605 | _OMAP2430_BALLENTRY(CAM_XCLK, "p3", NULL), | ||
| 606 | _OMAP2430_BALLENTRY(DSS_ACBIAS, "y3", NULL), | ||
| 607 | _OMAP2430_BALLENTRY(DSS_DATA0, "v8", NULL), | ||
| 608 | _OMAP2430_BALLENTRY(DSS_DATA1, "w1", NULL), | ||
| 609 | _OMAP2430_BALLENTRY(DSS_DATA10, "k25", NULL), | ||
| 610 | _OMAP2430_BALLENTRY(DSS_DATA11, "j25", NULL), | ||
| 611 | _OMAP2430_BALLENTRY(DSS_DATA12, "k24", NULL), | ||
| 612 | _OMAP2430_BALLENTRY(DSS_DATA13, "j24", NULL), | ||
| 613 | _OMAP2430_BALLENTRY(DSS_DATA14, "h25", NULL), | ||
| 614 | _OMAP2430_BALLENTRY(DSS_DATA15, "g25", NULL), | ||
| 615 | _OMAP2430_BALLENTRY(DSS_DATA16, "ac3", NULL), | ||
| 616 | _OMAP2430_BALLENTRY(DSS_DATA17, "y7", NULL), | ||
| 617 | _OMAP2430_BALLENTRY(DSS_DATA2, "u8", NULL), | ||
| 618 | _OMAP2430_BALLENTRY(DSS_DATA3, "u4", NULL), | ||
| 619 | _OMAP2430_BALLENTRY(DSS_DATA4, "v3", NULL), | ||
| 620 | _OMAP2430_BALLENTRY(DSS_DATA5, "aa4", NULL), | ||
| 621 | _OMAP2430_BALLENTRY(DSS_DATA6, "w8", NULL), | ||
| 622 | _OMAP2430_BALLENTRY(DSS_DATA7, "y1", NULL), | ||
| 623 | _OMAP2430_BALLENTRY(DSS_DATA8, "aa2", NULL), | ||
| 624 | _OMAP2430_BALLENTRY(DSS_DATA9, "ab4", NULL), | ||
| 625 | _OMAP2430_BALLENTRY(DSS_HSYNC, "v2", NULL), | ||
| 626 | _OMAP2430_BALLENTRY(GPIO_113, "ad16", NULL), | ||
| 627 | _OMAP2430_BALLENTRY(GPIO_114, "ac10", NULL), | ||
| 628 | _OMAP2430_BALLENTRY(GPIO_115, "ad13", NULL), | ||
| 629 | _OMAP2430_BALLENTRY(GPIO_116, "ae15", NULL), | ||
| 630 | _OMAP2430_BALLENTRY(GPIO_128, "p1", NULL), | ||
| 631 | _OMAP2430_BALLENTRY(GPIO_129, "r1", NULL), | ||
| 632 | _OMAP2430_BALLENTRY(GPIO_130, "p7", NULL), | ||
| 633 | _OMAP2430_BALLENTRY(GPIO_131, "l8", NULL), | ||
| 634 | _OMAP2430_BALLENTRY(GPIO_132, "w24", NULL), | ||
| 635 | _OMAP2430_BALLENTRY(GPIO_133, "aa24", NULL), | ||
| 636 | _OMAP2430_BALLENTRY(GPIO_134, "ae12", NULL), | ||
| 637 | _OMAP2430_BALLENTRY(GPIO_135, "ae11", NULL), | ||
| 638 | _OMAP2430_BALLENTRY(GPIO_136, "ad12", NULL), | ||
| 639 | _OMAP2430_BALLENTRY(GPIO_137, "ad11", NULL), | ||
| 640 | _OMAP2430_BALLENTRY(GPIO_138, "y12", NULL), | ||
| 641 | _OMAP2430_BALLENTRY(GPIO_139, "ad17", NULL), | ||
| 642 | _OMAP2430_BALLENTRY(GPIO_140, "l7", NULL), | ||
| 643 | _OMAP2430_BALLENTRY(GPIO_141, "ac24", NULL), | ||
| 644 | _OMAP2430_BALLENTRY(GPIO_142, "m3", NULL), | ||
| 645 | _OMAP2430_BALLENTRY(GPIO_148, "af12", NULL), | ||
| 646 | _OMAP2430_BALLENTRY(GPIO_149, "k7", NULL), | ||
| 647 | _OMAP2430_BALLENTRY(GPIO_150, "m1", NULL), | ||
| 648 | _OMAP2430_BALLENTRY(GPIO_151, "ad14", NULL), | ||
| 649 | _OMAP2430_BALLENTRY(GPIO_152, "ad18", NULL), | ||
| 650 | _OMAP2430_BALLENTRY(GPIO_153, "u24", NULL), | ||
| 651 | _OMAP2430_BALLENTRY(GPIO_154, "ae16", NULL), | ||
| 652 | _OMAP2430_BALLENTRY(GPIO_63, "n3", NULL), | ||
| 653 | _OMAP2430_BALLENTRY(GPIO_7, "ac23", NULL), | ||
| 654 | _OMAP2430_BALLENTRY(GPIO_78, "ad10", NULL), | ||
| 655 | _OMAP2430_BALLENTRY(GPIO_79, "ae10", NULL), | ||
| 656 | _OMAP2430_BALLENTRY(GPIO_80, "ae13", NULL), | ||
| 657 | _OMAP2430_BALLENTRY(GPMC_A1, "a9", NULL), | ||
| 658 | _OMAP2430_BALLENTRY(GPMC_A10, "g12", NULL), | ||
| 659 | _OMAP2430_BALLENTRY(GPMC_A2, "b8", NULL), | ||
| 660 | _OMAP2430_BALLENTRY(GPMC_A3, "g10", NULL), | ||
| 661 | _OMAP2430_BALLENTRY(GPMC_A4, "g11", NULL), | ||
| 662 | _OMAP2430_BALLENTRY(GPMC_A5, "a10", NULL), | ||
| 663 | _OMAP2430_BALLENTRY(GPMC_A6, "g13", NULL), | ||
| 664 | _OMAP2430_BALLENTRY(GPMC_A7, "a6", NULL), | ||
| 665 | _OMAP2430_BALLENTRY(GPMC_A8, "h1", NULL), | ||
| 666 | _OMAP2430_BALLENTRY(GPMC_A9, "c8", NULL), | ||
| 667 | _OMAP2430_BALLENTRY(GPMC_CLK, "n1", "l1"), | ||
| 668 | _OMAP2430_BALLENTRY(GPMC_D10, "d1", "n1"), | ||
| 669 | _OMAP2430_BALLENTRY(GPMC_D11, "d2", "p2"), | ||
| 670 | _OMAP2430_BALLENTRY(GPMC_D12, "e1", "p1"), | ||
| 671 | _OMAP2430_BALLENTRY(GPMC_D13, "e3", "m1"), | ||
| 672 | _OMAP2430_BALLENTRY(GPMC_D14, "c7", "j2"), | ||
| 673 | _OMAP2430_BALLENTRY(GPMC_D15, "f3", "k2"), | ||
| 674 | _OMAP2430_BALLENTRY(GPMC_D8, "e2", "r1"), | ||
| 675 | _OMAP2430_BALLENTRY(GPMC_D9, "ab1", "t1"), | ||
| 676 | _OMAP2430_BALLENTRY(GPMC_NCS1, "ac1", "w1"), | ||
| 677 | _OMAP2430_BALLENTRY(GPMC_NCS2, "c6", NULL), | ||
| 678 | _OMAP2430_BALLENTRY(GPMC_NCS3, "b9", NULL), | ||
| 679 | _OMAP2430_BALLENTRY(GPMC_NCS4, "b4", NULL), | ||
| 680 | _OMAP2430_BALLENTRY(GPMC_NCS5, "a4", NULL), | ||
| 681 | _OMAP2430_BALLENTRY(GPMC_NCS6, "f1", NULL), | ||
| 682 | _OMAP2430_BALLENTRY(GPMC_NCS7, "a7", NULL), | ||
| 683 | _OMAP2430_BALLENTRY(GPMC_WAIT1, "j1", "y8"), | ||
| 684 | _OMAP2430_BALLENTRY(GPMC_WAIT2, "b7", NULL), | ||
| 685 | _OMAP2430_BALLENTRY(GPMC_WAIT3, "g14", NULL), | ||
| 686 | _OMAP2430_BALLENTRY(HDQ_SIO, "h20", NULL), | ||
| 687 | _OMAP2430_BALLENTRY(I2C1_SCL, "y17", NULL), | ||
| 688 | _OMAP2430_BALLENTRY(I2C1_SDA, "ac19", NULL), | ||
| 689 | _OMAP2430_BALLENTRY(I2C2_SCL, "n7", NULL), | ||
| 690 | _OMAP2430_BALLENTRY(I2C2_SDA, "m4", NULL), | ||
| 691 | _OMAP2430_BALLENTRY(JTAG_EMU0, "e25", NULL), | ||
| 692 | _OMAP2430_BALLENTRY(JTAG_EMU1, "e24", NULL), | ||
| 693 | _OMAP2430_BALLENTRY(MCBSP1_CLKR, "ab2", NULL), | ||
| 694 | _OMAP2430_BALLENTRY(MCBSP1_CLKX, "y9", NULL), | ||
| 695 | _OMAP2430_BALLENTRY(MCBSP1_DR, "af3", NULL), | ||
| 696 | _OMAP2430_BALLENTRY(MCBSP1_DX, "aa1", NULL), | ||
| 697 | _OMAP2430_BALLENTRY(MCBSP1_FSR, "ad5", NULL), | ||
| 698 | _OMAP2430_BALLENTRY(MCBSP1_FSX, "ab3", NULL), | ||
| 699 | _OMAP2430_BALLENTRY(MCBSP2_CLKX, "j26", NULL), | ||
| 700 | _OMAP2430_BALLENTRY(MCBSP2_DR, "k26", NULL), | ||
| 701 | _OMAP2430_BALLENTRY(MCBSP3_CLKX, "ac9", NULL), | ||
| 702 | _OMAP2430_BALLENTRY(MCBSP3_DR, "ae2", NULL), | ||
| 703 | _OMAP2430_BALLENTRY(MCBSP3_DX, "af4", NULL), | ||
| 704 | _OMAP2430_BALLENTRY(MCBSP3_FSX, "ae4", NULL), | ||
| 705 | _OMAP2430_BALLENTRY(MCBSP_CLKS, "ad6", NULL), | ||
| 706 | _OMAP2430_BALLENTRY(SDMMC1_CLKO, "n23", NULL), | ||
| 707 | _OMAP2430_BALLENTRY(SDMMC1_CMD, "l23", NULL), | ||
| 708 | _OMAP2430_BALLENTRY(SDMMC1_DAT0, "m24", NULL), | ||
| 709 | _OMAP2430_BALLENTRY(SDMMC1_DAT1, "p23", NULL), | ||
| 710 | _OMAP2430_BALLENTRY(SDMMC1_DAT2, "t20", NULL), | ||
| 711 | _OMAP2430_BALLENTRY(SDMMC1_DAT3, "r20", NULL), | ||
| 712 | _OMAP2430_BALLENTRY(SDMMC2_CLKO, "v26", NULL), | ||
| 713 | _OMAP2430_BALLENTRY(SDMMC2_CMD, "w20", NULL), | ||
| 714 | _OMAP2430_BALLENTRY(SDMMC2_DAT0, "v23", NULL), | ||
| 715 | _OMAP2430_BALLENTRY(SDMMC2_DAT1, "y24", NULL), | ||
| 716 | _OMAP2430_BALLENTRY(SDMMC2_DAT2, "v25", NULL), | ||
| 717 | _OMAP2430_BALLENTRY(SDMMC2_DAT3, "v24", NULL), | ||
| 718 | _OMAP2430_BALLENTRY(SDRC_A12, "w26", "r21"), | ||
| 719 | _OMAP2430_BALLENTRY(SDRC_A13, "af20", "aa15"), | ||
| 720 | _OMAP2430_BALLENTRY(SDRC_A14, "af16", "y12"), | ||
| 721 | _OMAP2430_BALLENTRY(SDRC_CKE1, "af15", "y13"), | ||
| 722 | _OMAP2430_BALLENTRY(SDRC_NCS1, "aa25", "t20"), | ||
| 723 | _OMAP2430_BALLENTRY(SPI1_CLK, "y18", NULL), | ||
| 724 | _OMAP2430_BALLENTRY(SPI1_CS0, "u1", NULL), | ||
| 725 | _OMAP2430_BALLENTRY(SPI1_CS1, "af19", NULL), | ||
| 726 | _OMAP2430_BALLENTRY(SPI1_CS2, "ae19", NULL), | ||
| 727 | _OMAP2430_BALLENTRY(SPI1_CS3, "h24", NULL), | ||
| 728 | _OMAP2430_BALLENTRY(SPI1_SIMO, "ad15", NULL), | ||
| 729 | _OMAP2430_BALLENTRY(SPI1_SOMI, "ae17", NULL), | ||
| 730 | _OMAP2430_BALLENTRY(SPI2_CLK, "y20", NULL), | ||
| 731 | _OMAP2430_BALLENTRY(SPI2_CS0, "y19", NULL), | ||
| 732 | _OMAP2430_BALLENTRY(SPI2_SIMO, "ac20", NULL), | ||
| 733 | _OMAP2430_BALLENTRY(SPI2_SOMI, "ad19", NULL), | ||
| 734 | _OMAP2430_BALLENTRY(SSI1_DAT_RX, "aa26", NULL), | ||
| 735 | _OMAP2430_BALLENTRY(SSI1_DAT_TX, "ad24", NULL), | ||
| 736 | _OMAP2430_BALLENTRY(SSI1_FLAG_RX, "ad23", NULL), | ||
| 737 | _OMAP2430_BALLENTRY(SSI1_FLAG_TX, "ab24", NULL), | ||
| 738 | _OMAP2430_BALLENTRY(SSI1_RDY_RX, "ab25", NULL), | ||
| 739 | _OMAP2430_BALLENTRY(SSI1_RDY_TX, "y25", NULL), | ||
| 740 | _OMAP2430_BALLENTRY(SSI1_WAKE, "ac25", NULL), | ||
| 741 | _OMAP2430_BALLENTRY(SYS_CLKOUT, "r25", NULL), | ||
| 742 | _OMAP2430_BALLENTRY(SYS_DRM_MSECURE, "ae3", NULL), | ||
| 743 | _OMAP2430_BALLENTRY(SYS_NIRQ0, "w25", NULL), | ||
| 744 | _OMAP2430_BALLENTRY(SYS_NIRQ1, "ad21", NULL), | ||
| 745 | _OMAP2430_BALLENTRY(UART1_CTS, "p24", NULL), | ||
| 746 | _OMAP2430_BALLENTRY(UART1_RTS, "p25", NULL), | ||
| 747 | _OMAP2430_BALLENTRY(UART1_RX, "n24", NULL), | ||
| 748 | _OMAP2430_BALLENTRY(UART1_TX, "r24", NULL), | ||
| 749 | _OMAP2430_BALLENTRY(UART2_CTS, "u25", NULL), | ||
| 750 | _OMAP2430_BALLENTRY(UART2_RTS, "t23", NULL), | ||
| 751 | _OMAP2430_BALLENTRY(UART2_RX, "t24", NULL), | ||
| 752 | _OMAP2430_BALLENTRY(UART2_TX, "u20", NULL), | ||
| 753 | _OMAP2430_BALLENTRY(UART3_CTS_RCTX, "m2", NULL), | ||
| 754 | _OMAP2430_BALLENTRY(UART3_RTS_SD, "k2", NULL), | ||
| 755 | _OMAP2430_BALLENTRY(UART3_RX_IRRX, "l3", NULL), | ||
| 756 | _OMAP2430_BALLENTRY(UART3_TX_IRTX, "l2", NULL), | ||
| 757 | _OMAP2430_BALLENTRY(USB0HS_CLK, "ae8", NULL), | ||
| 758 | _OMAP2430_BALLENTRY(USB0HS_DATA0, "ad4", NULL), | ||
| 759 | _OMAP2430_BALLENTRY(USB0HS_DATA1, "ae6", NULL), | ||
| 760 | _OMAP2430_BALLENTRY(USB0HS_DATA2, "af9", NULL), | ||
| 761 | _OMAP2430_BALLENTRY(USB0HS_DATA3, "ad9", NULL), | ||
| 762 | _OMAP2430_BALLENTRY(USB0HS_DATA4, "y11", NULL), | ||
| 763 | _OMAP2430_BALLENTRY(USB0HS_DATA5, "ad7", NULL), | ||
| 764 | _OMAP2430_BALLENTRY(USB0HS_DATA6, "ae7", NULL), | ||
| 765 | _OMAP2430_BALLENTRY(USB0HS_DATA7, "ac7", NULL), | ||
| 766 | _OMAP2430_BALLENTRY(USB0HS_DIR, "ad8", NULL), | ||
| 767 | _OMAP2430_BALLENTRY(USB0HS_NXT, "ae9", NULL), | ||
| 768 | _OMAP2430_BALLENTRY(USB0HS_STP, "ae5", NULL), | ||
| 769 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 770 | }; | ||
| 771 | #else | ||
| 772 | #define omap2430_pop_ball NULL | ||
| 773 | #endif | ||
| 774 | |||
| 775 | int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags) | ||
| 776 | { | ||
| 777 | struct omap_ball *package_balls = NULL; | ||
| 778 | |||
| 779 | switch (flags & OMAP_PACKAGE_MASK) { | ||
| 780 | case OMAP_PACKAGE_ZAC: | ||
| 781 | package_balls = omap2430_pop_ball; | ||
| 782 | break; | ||
| 783 | default: | ||
| 784 | pr_warning("mux: No ball data available for omap2420 package\n"); | ||
| 785 | } | ||
| 786 | |||
| 787 | return omap_mux_init(OMAP2430_CONTROL_PADCONF_MUX_PBASE, | ||
| 788 | OMAP2430_CONTROL_PADCONF_MUX_SIZE, | ||
| 789 | omap2430_muxmodes, NULL, board_subset, | ||
| 790 | package_balls); | ||
| 791 | } | ||
diff --git a/arch/arm/mach-omap2/mux2430.h b/arch/arm/mach-omap2/mux2430.h new file mode 100644 index 000000000000..adbea0d03e08 --- /dev/null +++ b/arch/arm/mach-omap2/mux2430.h | |||
| @@ -0,0 +1,370 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Nokia | ||
| 3 | * Copyright (C) 2009 Texas Instruments | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define OMAP2430_CONTROL_PADCONF_MUX_PBASE 0x49002030LU | ||
| 11 | |||
| 12 | #define OMAP2430_MUX(mode0, mux_value) \ | ||
| 13 | { \ | ||
| 14 | .reg_offset = (OMAP2430_CONTROL_PADCONF_##mode0##_OFFSET), \ | ||
| 15 | .value = (mux_value), \ | ||
| 16 | } | ||
| 17 | |||
| 18 | /* | ||
| 19 | * OMAP2430 CONTROL_PADCONF* register offsets for pin-muxing | ||
| 20 | * | ||
| 21 | * Extracted from the TRM. Add 0x49002030 to these values to get the | ||
| 22 | * absolute addresses. The name in the macro is the mode-0 name of | ||
| 23 | * the pin. NOTE: These registers are 8-bits wide. | ||
| 24 | * | ||
| 25 | * Note that these defines use SDMMC instead of MMC for compability | ||
| 26 | * with signal names used in 3630. | ||
| 27 | */ | ||
| 28 | #define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x000 | ||
| 29 | #define OMAP2430_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x001 | ||
| 30 | #define OMAP2430_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x002 | ||
| 31 | #define OMAP2430_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x003 | ||
| 32 | #define OMAP2430_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x004 | ||
| 33 | #define OMAP2430_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x005 | ||
| 34 | #define OMAP2430_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x006 | ||
| 35 | #define OMAP2430_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x007 | ||
| 36 | #define OMAP2430_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x008 | ||
| 37 | #define OMAP2430_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x009 | ||
| 38 | #define OMAP2430_CONTROL_PADCONF_GPMC_NOE_NRE_OFFSET 0x00a | ||
| 39 | #define OMAP2430_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x00b | ||
| 40 | #define OMAP2430_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x00c | ||
| 41 | #define OMAP2430_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x00d | ||
| 42 | #define OMAP2430_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x00e | ||
| 43 | #define OMAP2430_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x00f | ||
| 44 | #define OMAP2430_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x010 | ||
| 45 | #define OMAP2430_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x011 | ||
| 46 | #define OMAP2430_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x012 | ||
| 47 | #define OMAP2430_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x013 | ||
| 48 | #define OMAP2430_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x014 | ||
| 49 | #define OMAP2430_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x015 | ||
| 50 | #define OMAP2430_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x016 | ||
| 51 | #define OMAP2430_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x017 | ||
| 52 | #define OMAP2430_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x018 | ||
| 53 | #define OMAP2430_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x019 | ||
| 54 | #define OMAP2430_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x01a | ||
| 55 | #define OMAP2430_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x01b | ||
| 56 | #define OMAP2430_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x01c | ||
| 57 | #define OMAP2430_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x01d | ||
| 58 | #define OMAP2430_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x01e | ||
| 59 | #define OMAP2430_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x01f | ||
| 60 | #define OMAP2430_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x020 | ||
| 61 | #define OMAP2430_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x021 | ||
| 62 | #define OMAP2430_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x022 | ||
| 63 | #define OMAP2430_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x023 | ||
| 64 | #define OMAP2430_CONTROL_PADCONF_SDRC_A14_OFFSET 0x024 | ||
| 65 | #define OMAP2430_CONTROL_PADCONF_SDRC_A13_OFFSET 0x025 | ||
| 66 | #define OMAP2430_CONTROL_PADCONF_SDRC_A12_OFFSET 0x026 | ||
| 67 | #define OMAP2430_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x027 | ||
| 68 | #define OMAP2430_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x028 | ||
| 69 | #define OMAP2430_CONTROL_PADCONF_SDRC_A11_OFFSET 0x029 | ||
| 70 | #define OMAP2430_CONTROL_PADCONF_SDRC_A10_OFFSET 0x02a | ||
| 71 | #define OMAP2430_CONTROL_PADCONF_SDRC_A9_OFFSET 0x02b | ||
| 72 | #define OMAP2430_CONTROL_PADCONF_SDRC_A8_OFFSET 0x02c | ||
| 73 | #define OMAP2430_CONTROL_PADCONF_SDRC_A7_OFFSET 0x02d | ||
| 74 | #define OMAP2430_CONTROL_PADCONF_SDRC_A6_OFFSET 0x02e | ||
| 75 | #define OMAP2430_CONTROL_PADCONF_SDRC_A5_OFFSET 0x02f | ||
| 76 | #define OMAP2430_CONTROL_PADCONF_SDRC_A4_OFFSET 0x030 | ||
| 77 | #define OMAP2430_CONTROL_PADCONF_SDRC_A3_OFFSET 0x031 | ||
| 78 | #define OMAP2430_CONTROL_PADCONF_SDRC_A2_OFFSET 0x032 | ||
| 79 | #define OMAP2430_CONTROL_PADCONF_SDRC_A1_OFFSET 0x033 | ||
| 80 | #define OMAP2430_CONTROL_PADCONF_SDRC_A0_OFFSET 0x034 | ||
| 81 | #define OMAP2430_CONTROL_PADCONF_SDRC_D31_OFFSET 0x035 | ||
| 82 | #define OMAP2430_CONTROL_PADCONF_SDRC_D30_OFFSET 0x036 | ||
| 83 | #define OMAP2430_CONTROL_PADCONF_SDRC_D29_OFFSET 0x037 | ||
| 84 | #define OMAP2430_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038 | ||
| 85 | #define OMAP2430_CONTROL_PADCONF_SDRC_D27_OFFSET 0x039 | ||
| 86 | #define OMAP2430_CONTROL_PADCONF_SDRC_D26_OFFSET 0x03a | ||
| 87 | #define OMAP2430_CONTROL_PADCONF_SDRC_D25_OFFSET 0x03b | ||
| 88 | #define OMAP2430_CONTROL_PADCONF_SDRC_D24_OFFSET 0x03c | ||
| 89 | #define OMAP2430_CONTROL_PADCONF_SDRC_D23_OFFSET 0x03d | ||
| 90 | #define OMAP2430_CONTROL_PADCONF_SDRC_D22_OFFSET 0x03e | ||
| 91 | #define OMAP2430_CONTROL_PADCONF_SDRC_D21_OFFSET 0x03f | ||
| 92 | #define OMAP2430_CONTROL_PADCONF_SDRC_D20_OFFSET 0x040 | ||
| 93 | #define OMAP2430_CONTROL_PADCONF_SDRC_D19_OFFSET 0x041 | ||
| 94 | #define OMAP2430_CONTROL_PADCONF_SDRC_D18_OFFSET 0x042 | ||
| 95 | #define OMAP2430_CONTROL_PADCONF_SDRC_D17_OFFSET 0x043 | ||
| 96 | #define OMAP2430_CONTROL_PADCONF_SDRC_D16_OFFSET 0x044 | ||
| 97 | #define OMAP2430_CONTROL_PADCONF_SDRC_D15_OFFSET 0x045 | ||
| 98 | #define OMAP2430_CONTROL_PADCONF_SDRC_D14_OFFSET 0x046 | ||
| 99 | #define OMAP2430_CONTROL_PADCONF_SDRC_D13_OFFSET 0x047 | ||
| 100 | #define OMAP2430_CONTROL_PADCONF_SDRC_D12_OFFSET 0x048 | ||
| 101 | #define OMAP2430_CONTROL_PADCONF_SDRC_D11_OFFSET 0x049 | ||
| 102 | #define OMAP2430_CONTROL_PADCONF_SDRC_D10_OFFSET 0x04a | ||
| 103 | #define OMAP2430_CONTROL_PADCONF_SDRC_D9_OFFSET 0x04b | ||
| 104 | #define OMAP2430_CONTROL_PADCONF_SDRC_D8_OFFSET 0x04c | ||
| 105 | #define OMAP2430_CONTROL_PADCONF_SDRC_D7_OFFSET 0x04d | ||
| 106 | #define OMAP2430_CONTROL_PADCONF_SDRC_D6_OFFSET 0x04e | ||
| 107 | #define OMAP2430_CONTROL_PADCONF_SDRC_D5_OFFSET 0x04f | ||
| 108 | #define OMAP2430_CONTROL_PADCONF_SDRC_D4_OFFSET 0x050 | ||
| 109 | #define OMAP2430_CONTROL_PADCONF_SDRC_D3_OFFSET 0x051 | ||
| 110 | #define OMAP2430_CONTROL_PADCONF_SDRC_D2_OFFSET 0x052 | ||
| 111 | #define OMAP2430_CONTROL_PADCONF_SDRC_D1_OFFSET 0x053 | ||
| 112 | #define OMAP2430_CONTROL_PADCONF_SDRC_D0_OFFSET 0x054 | ||
| 113 | #define OMAP2430_CONTROL_PADCONF_GPMC_A10_OFFSET 0x055 | ||
| 114 | #define OMAP2430_CONTROL_PADCONF_GPMC_A9_OFFSET 0x056 | ||
| 115 | #define OMAP2430_CONTROL_PADCONF_GPMC_A8_OFFSET 0x057 | ||
| 116 | #define OMAP2430_CONTROL_PADCONF_GPMC_A7_OFFSET 0x058 | ||
| 117 | #define OMAP2430_CONTROL_PADCONF_GPMC_A6_OFFSET 0x059 | ||
| 118 | #define OMAP2430_CONTROL_PADCONF_GPMC_A5_OFFSET 0x05a | ||
| 119 | #define OMAP2430_CONTROL_PADCONF_GPMC_A4_OFFSET 0x05b | ||
| 120 | #define OMAP2430_CONTROL_PADCONF_GPMC_A3_OFFSET 0x05c | ||
| 121 | #define OMAP2430_CONTROL_PADCONF_GPMC_A2_OFFSET 0x05d | ||
| 122 | #define OMAP2430_CONTROL_PADCONF_GPMC_A1_OFFSET 0x05e | ||
| 123 | #define OMAP2430_CONTROL_PADCONF_GPMC_D15_OFFSET 0x05f | ||
| 124 | #define OMAP2430_CONTROL_PADCONF_GPMC_D14_OFFSET 0x060 | ||
| 125 | #define OMAP2430_CONTROL_PADCONF_GPMC_D13_OFFSET 0x061 | ||
| 126 | #define OMAP2430_CONTROL_PADCONF_GPMC_D12_OFFSET 0x062 | ||
| 127 | #define OMAP2430_CONTROL_PADCONF_GPMC_D11_OFFSET 0x063 | ||
| 128 | #define OMAP2430_CONTROL_PADCONF_GPMC_D10_OFFSET 0x064 | ||
| 129 | #define OMAP2430_CONTROL_PADCONF_GPMC_D9_OFFSET 0x065 | ||
| 130 | #define OMAP2430_CONTROL_PADCONF_GPMC_D8_OFFSET 0x066 | ||
| 131 | #define OMAP2430_CONTROL_PADCONF_GPMC_D7_OFFSET 0x067 | ||
| 132 | #define OMAP2430_CONTROL_PADCONF_GPMC_D6_OFFSET 0x068 | ||
| 133 | #define OMAP2430_CONTROL_PADCONF_GPMC_D5_OFFSET 0x069 | ||
| 134 | #define OMAP2430_CONTROL_PADCONF_GPMC_D4_OFFSET 0x06a | ||
| 135 | #define OMAP2430_CONTROL_PADCONF_GPMC_D3_OFFSET 0x06b | ||
| 136 | #define OMAP2430_CONTROL_PADCONF_GPMC_D2_OFFSET 0x06c | ||
| 137 | #define OMAP2430_CONTROL_PADCONF_GPMC_D1_OFFSET 0x06d | ||
| 138 | #define OMAP2430_CONTROL_PADCONF_GPMC_D0_OFFSET 0x06e | ||
| 139 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x06f | ||
| 140 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x070 | ||
| 141 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x071 | ||
| 142 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x072 | ||
| 143 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x073 | ||
| 144 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x074 | ||
| 145 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x075 | ||
| 146 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x076 | ||
| 147 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x077 | ||
| 148 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x078 | ||
| 149 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x079 | ||
| 150 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x07a | ||
| 151 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x07b | ||
| 152 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x07c | ||
| 153 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x07d | ||
| 154 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x07e | ||
| 155 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x07f | ||
| 156 | #define OMAP2430_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x080 | ||
| 157 | #define OMAP2430_CONTROL_PADCONF_UART1_CTS_OFFSET 0x081 | ||
| 158 | #define OMAP2430_CONTROL_PADCONF_UART1_RTS_OFFSET 0x082 | ||
| 159 | #define OMAP2430_CONTROL_PADCONF_UART1_TX_OFFSET 0x083 | ||
| 160 | #define OMAP2430_CONTROL_PADCONF_UART1_RX_OFFSET 0x084 | ||
| 161 | #define OMAP2430_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x085 | ||
| 162 | #define OMAP2430_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x086 | ||
| 163 | #define OMAP2430_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x087 | ||
| 164 | #define OMAP2430_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x088 | ||
| 165 | #define OMAP2430_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x089 | ||
| 166 | #define OMAP2430_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x08a | ||
| 167 | #define OMAP2430_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x08b | ||
| 168 | #define OMAP2430_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x08c | ||
| 169 | #define OMAP2430_CONTROL_PADCONF_SYS_NIRQ0_OFFSET 0x08d | ||
| 170 | #define OMAP2430_CONTROL_PADCONF_SYS_NIRQ1_OFFSET 0x08e | ||
| 171 | #define OMAP2430_CONTROL_PADCONF_SYS_VMODE_OFFSET 0x08f | ||
| 172 | #define OMAP2430_CONTROL_PADCONF_GPIO_128_OFFSET 0x090 | ||
| 173 | #define OMAP2430_CONTROL_PADCONF_GPIO_129_OFFSET 0x091 | ||
| 174 | #define OMAP2430_CONTROL_PADCONF_GPIO_130_OFFSET 0x092 | ||
| 175 | #define OMAP2430_CONTROL_PADCONF_GPIO_131_OFFSET 0x093 | ||
| 176 | #define OMAP2430_CONTROL_PADCONF_SYS_32K_OFFSET 0x094 | ||
| 177 | #define OMAP2430_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x095 | ||
| 178 | #define OMAP2430_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x096 | ||
| 179 | #define OMAP2430_CONTROL_PADCONF_GPIO_132_OFFSET 0x097 | ||
| 180 | #define OMAP2430_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x098 | ||
| 181 | #define OMAP2430_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x099 | ||
| 182 | #define OMAP2430_CONTROL_PADCONF_GPIO_151_OFFSET 0x09a | ||
| 183 | #define OMAP2430_CONTROL_PADCONF_GPIO_133_OFFSET 0x09b | ||
| 184 | #define OMAP2430_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x09c | ||
| 185 | #define OMAP2430_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x09d | ||
| 186 | #define OMAP2430_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x09e | ||
| 187 | #define OMAP2430_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x09f | ||
| 188 | #define OMAP2430_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x0a0 | ||
| 189 | #define OMAP2430_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x0a1 | ||
| 190 | #define OMAP2430_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x0a2 | ||
| 191 | #define OMAP2430_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x0a3 | ||
| 192 | #define OMAP2430_CONTROL_PADCONF_CAM_D9_OFFSET 0x0a4 | ||
| 193 | #define OMAP2430_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a5 | ||
| 194 | #define OMAP2430_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a6 | ||
| 195 | #define OMAP2430_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a7 | ||
| 196 | #define OMAP2430_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a8 | ||
| 197 | #define OMAP2430_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a9 | ||
| 198 | #define OMAP2430_CONTROL_PADCONF_CAM_D3_OFFSET 0x0aa | ||
| 199 | #define OMAP2430_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ab | ||
| 200 | #define OMAP2430_CONTROL_PADCONF_CAM_D1_OFFSET 0x0ac | ||
| 201 | #define OMAP2430_CONTROL_PADCONF_CAM_D0_OFFSET 0x0ad | ||
| 202 | #define OMAP2430_CONTROL_PADCONF_CAM_HS_OFFSET 0x0ae | ||
| 203 | #define OMAP2430_CONTROL_PADCONF_CAM_VS_OFFSET 0x0af | ||
| 204 | #define OMAP2430_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0b0 | ||
| 205 | #define OMAP2430_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0b1 | ||
| 206 | #define OMAP2430_CONTROL_PADCONF_CAM_D11_OFFSET 0x0b2 | ||
| 207 | #define OMAP2430_CONTROL_PADCONF_CAM_D10_OFFSET 0x0b3 | ||
| 208 | #define OMAP2430_CONTROL_PADCONF_GPIO_134_OFFSET 0x0b4 | ||
| 209 | #define OMAP2430_CONTROL_PADCONF_GPIO_135_OFFSET 0x0b5 | ||
| 210 | #define OMAP2430_CONTROL_PADCONF_GPIO_136_OFFSET 0x0b6 | ||
| 211 | #define OMAP2430_CONTROL_PADCONF_GPIO_137_OFFSET 0x0b7 | ||
| 212 | #define OMAP2430_CONTROL_PADCONF_GPIO_138_OFFSET 0x0b8 | ||
| 213 | #define OMAP2430_CONTROL_PADCONF_GPIO_139_OFFSET 0x0b9 | ||
| 214 | #define OMAP2430_CONTROL_PADCONF_GPIO_140_OFFSET 0x0ba | ||
| 215 | #define OMAP2430_CONTROL_PADCONF_GPIO_141_OFFSET 0x0bb | ||
| 216 | #define OMAP2430_CONTROL_PADCONF_GPIO_142_OFFSET 0x0bc | ||
| 217 | #define OMAP2430_CONTROL_PADCONF_GPIO_154_OFFSET 0x0bd | ||
| 218 | #define OMAP2430_CONTROL_PADCONF_GPIO_148_OFFSET 0x0be | ||
| 219 | #define OMAP2430_CONTROL_PADCONF_GPIO_149_OFFSET 0x0bf | ||
| 220 | #define OMAP2430_CONTROL_PADCONF_GPIO_150_OFFSET 0x0c0 | ||
| 221 | #define OMAP2430_CONTROL_PADCONF_GPIO_152_OFFSET 0x0c1 | ||
| 222 | #define OMAP2430_CONTROL_PADCONF_GPIO_153_OFFSET 0x0c2 | ||
| 223 | #define OMAP2430_CONTROL_PADCONF_SDMMC1_CLKO_OFFSET 0x0c3 | ||
| 224 | #define OMAP2430_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x0c4 | ||
| 225 | #define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x0c5 | ||
| 226 | #define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x0c6 | ||
| 227 | #define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x0c7 | ||
| 228 | #define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x0c8 | ||
| 229 | #define OMAP2430_CONTROL_PADCONF_SDMMC2_CLKO_OFFSET 0x0c9 | ||
| 230 | #define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x0ca | ||
| 231 | #define OMAP2430_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x0cb | ||
| 232 | #define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x0cc | ||
| 233 | #define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x0cd | ||
| 234 | #define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x0ce | ||
| 235 | #define OMAP2430_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0cf | ||
| 236 | #define OMAP2430_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0d0 | ||
| 237 | #define OMAP2430_CONTROL_PADCONF_UART2_TX_OFFSET 0x0d1 | ||
| 238 | #define OMAP2430_CONTROL_PADCONF_UART2_RX_OFFSET 0x0d2 | ||
| 239 | #define OMAP2430_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x0d3 | ||
| 240 | #define OMAP2430_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x0d4 | ||
| 241 | #define OMAP2430_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x0d5 | ||
| 242 | #define OMAP2430_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x0d6 | ||
| 243 | #define OMAP2430_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0d7 | ||
| 244 | #define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0d8 | ||
| 245 | #define OMAP2430_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0d9 | ||
| 246 | #define OMAP2430_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0da | ||
| 247 | #define OMAP2430_CONTROL_PADCONF_GPIO_63_OFFSET 0x0db | ||
| 248 | #define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0dc | ||
| 249 | #define OMAP2430_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0dd | ||
| 250 | #define OMAP2430_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0de | ||
| 251 | #define OMAP2430_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0df | ||
| 252 | #define OMAP2430_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0e0 | ||
| 253 | #define OMAP2430_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0e1 | ||
| 254 | #define OMAP2430_CONTROL_PADCONF_SPI1_CS0_OFFSET 0x0e2 | ||
| 255 | #define OMAP2430_CONTROL_PADCONF_SPI1_CS1_OFFSET 0x0e3 | ||
| 256 | #define OMAP2430_CONTROL_PADCONF_SPI1_CS2_OFFSET 0x0e4 | ||
| 257 | #define OMAP2430_CONTROL_PADCONF_SPI1_CS3_OFFSET 0x0e5 | ||
| 258 | #define OMAP2430_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0e6 | ||
| 259 | #define OMAP2430_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0e7 | ||
| 260 | #define OMAP2430_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0e8 | ||
| 261 | #define OMAP2430_CONTROL_PADCONF_SPI2_CS0_OFFSET 0x0e9 | ||
| 262 | #define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0ea | ||
| 263 | #define OMAP2430_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0eb | ||
| 264 | #define OMAP2430_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0ec | ||
| 265 | #define OMAP2430_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0ed | ||
| 266 | #define OMAP2430_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0ee | ||
| 267 | #define OMAP2430_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0ef | ||
| 268 | #define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0f0 | ||
| 269 | #define OMAP2430_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0f1 | ||
| 270 | #define OMAP2430_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0f2 | ||
| 271 | #define OMAP2430_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0f3 | ||
| 272 | #define OMAP2430_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0f4 | ||
| 273 | #define OMAP2430_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0f5 | ||
| 274 | #define OMAP2430_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0f6 | ||
| 275 | #define OMAP2430_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0f7 | ||
| 276 | #define OMAP2430_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0f8 | ||
| 277 | #define OMAP2430_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0f9 | ||
| 278 | #define OMAP2430_CONTROL_PADCONF_GPIO_7_OFFSET 0x0fa | ||
| 279 | #define OMAP2430_CONTROL_PADCONF_GPIO_78_OFFSET 0x0fb | ||
| 280 | #define OMAP2430_CONTROL_PADCONF_GPIO_79_OFFSET 0x0fc | ||
| 281 | #define OMAP2430_CONTROL_PADCONF_GPIO_80_OFFSET 0x0fd | ||
| 282 | #define OMAP2430_CONTROL_PADCONF_GPIO_113_OFFSET 0x0fe | ||
| 283 | #define OMAP2430_CONTROL_PADCONF_GPIO_114_OFFSET 0x0ff | ||
| 284 | #define OMAP2430_CONTROL_PADCONF_GPIO_115_OFFSET 0x100 | ||
| 285 | #define OMAP2430_CONTROL_PADCONF_GPIO_116_OFFSET 0x101 | ||
| 286 | #define OMAP2430_CONTROL_PADCONF_SYS_DRM_MSECURE_OFFSET 0x102 | ||
| 287 | #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA3_OFFSET 0x103 | ||
| 288 | #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA4_OFFSET 0x104 | ||
| 289 | #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA5_OFFSET 0x105 | ||
| 290 | #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA6_OFFSET 0x106 | ||
| 291 | #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA2_OFFSET 0x107 | ||
| 292 | #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA0_OFFSET 0x108 | ||
| 293 | #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA1_OFFSET 0x109 | ||
| 294 | #define OMAP2430_CONTROL_PADCONF_USB0HS_CLK_OFFSET 0x10a | ||
| 295 | #define OMAP2430_CONTROL_PADCONF_USB0HS_DIR_OFFSET 0x10b | ||
| 296 | #define OMAP2430_CONTROL_PADCONF_USB0HS_STP_OFFSET 0x10c | ||
| 297 | #define OMAP2430_CONTROL_PADCONF_USB0HS_NXT_OFFSET 0x10d | ||
| 298 | #define OMAP2430_CONTROL_PADCONF_USB0HS_DATA7_OFFSET 0x10e | ||
| 299 | #define OMAP2430_CONTROL_PADCONF_TV_OUT_OFFSET 0x10f | ||
| 300 | #define OMAP2430_CONTROL_PADCONF_TV_VREF_OFFSET 0x110 | ||
| 301 | #define OMAP2430_CONTROL_PADCONF_TV_RSET_OFFSET 0x111 | ||
| 302 | #define OMAP2430_CONTROL_PADCONF_TV_VFB_OFFSET 0x112 | ||
| 303 | #define OMAP2430_CONTROL_PADCONF_TV_DACOUT_OFFSET 0x113 | ||
| 304 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD0_OFFSET 0x114 | ||
| 305 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD1_OFFSET 0x115 | ||
| 306 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD2_OFFSET 0x116 | ||
| 307 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD3_OFFSET 0x117 | ||
| 308 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD4_OFFSET 0x118 | ||
| 309 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD5_OFFSET 0x119 | ||
| 310 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD6_OFFSET 0x11a | ||
| 311 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD7_OFFSET 0x11b | ||
| 312 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD8_OFFSET 0x11c | ||
| 313 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD9_OFFSET 0x11d | ||
| 314 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD10_OFFSET 0x11e | ||
| 315 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD11_OFFSET 0x11f | ||
| 316 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD12_OFFSET 0x120 | ||
| 317 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD13_OFFSET 0x121 | ||
| 318 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD14_OFFSET 0x122 | ||
| 319 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD15_OFFSET 0x123 | ||
| 320 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD16_OFFSET 0x124 | ||
| 321 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD17_OFFSET 0x125 | ||
| 322 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD18_OFFSET 0x126 | ||
| 323 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD19_OFFSET 0x127 | ||
| 324 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD20_OFFSET 0x128 | ||
| 325 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD21_OFFSET 0x129 | ||
| 326 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD22_OFFSET 0x12a | ||
| 327 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD23_OFFSET 0x12b | ||
| 328 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD24_OFFSET 0x12c | ||
| 329 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD25_OFFSET 0x12d | ||
| 330 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD26_OFFSET 0x12e | ||
| 331 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD27_OFFSET 0x12f | ||
| 332 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD28_OFFSET 0x130 | ||
| 333 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD29_OFFSET 0x131 | ||
| 334 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD30_OFFSET 0x132 | ||
| 335 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD31_OFFSET 0x133 | ||
| 336 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD32_OFFSET 0x134 | ||
| 337 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD33_OFFSET 0x135 | ||
| 338 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD34_OFFSET 0x136 | ||
| 339 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD35_OFFSET 0x137 | ||
| 340 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD36_OFFSET 0x138 | ||
| 341 | #define OMAP2430_CONTROL_PADCONF_AD2DMCAD37_OFFSET 0x139 | ||
| 342 | #define OMAP2430_CONTROL_PADCONF_AD2DMWRITE_OFFSET 0x13a | ||
| 343 | #define OMAP2430_CONTROL_PADCONF_D2DCLK26MI_OFFSET 0x13b | ||
| 344 | #define OMAP2430_CONTROL_PADCONF_D2DNRESPWRON1_OFFSET 0x13c | ||
| 345 | #define OMAP2430_CONTROL_PADCONF_D2DNRESWARM_OFFSET 0x13d | ||
| 346 | #define OMAP2430_CONTROL_PADCONF_D2DARM9NIRQ_OFFSET 0x13e | ||
| 347 | #define OMAP2430_CONTROL_PADCONF_D2DUMA2P6FIQ_OFFSET 0x13f | ||
| 348 | #define OMAP2430_CONTROL_PADCONF_D2DSPINT_OFFSET 0x140 | ||
| 349 | #define OMAP2430_CONTROL_PADCONF_D2DFRINT_OFFSET 0x141 | ||
| 350 | #define OMAP2430_CONTROL_PADCONF_D2DDMAREQ0_OFFSET 0x142 | ||
| 351 | #define OMAP2430_CONTROL_PADCONF_D2DDMAREQ1_OFFSET 0x143 | ||
| 352 | #define OMAP2430_CONTROL_PADCONF_D2DDMAREQ2_OFFSET 0x144 | ||
| 353 | #define OMAP2430_CONTROL_PADCONF_D2DDMAREQ3_OFFSET 0x145 | ||
| 354 | #define OMAP2430_CONTROL_PADCONF_D2DN3GTRST_OFFSET 0x146 | ||
| 355 | #define OMAP2430_CONTROL_PADCONF_D2DN3GTDI_OFFSET 0x147 | ||
| 356 | #define OMAP2430_CONTROL_PADCONF_D2DN3GTDO_OFFSET 0x148 | ||
| 357 | #define OMAP2430_CONTROL_PADCONF_D2DN3GTMS_OFFSET 0x149 | ||
| 358 | #define OMAP2430_CONTROL_PADCONF_D2DN3GTCK_OFFSET 0x14a | ||
| 359 | #define OMAP2430_CONTROL_PADCONF_D2DN3GRTCK_OFFSET 0x14b | ||
| 360 | #define OMAP2430_CONTROL_PADCONF_D2DMSTDBY_OFFSET 0x14c | ||
| 361 | #define OMAP2430_CONTROL_PADCONF_AD2DSREAD_OFFSET 0x14d | ||
| 362 | #define OMAP2430_CONTROL_PADCONF_D2DSWAKEUP_OFFSET 0x14e | ||
| 363 | #define OMAP2430_CONTROL_PADCONF_D2DIDLEREQ_OFFSET 0x14f | ||
| 364 | #define OMAP2430_CONTROL_PADCONF_D2DIDLEACK_OFFSET 0x150 | ||
| 365 | #define OMAP2430_CONTROL_PADCONF_D2DSPARE0_OFFSET 0x151 | ||
| 366 | #define OMAP2430_CONTROL_PADCONF_AD2DSWRITE_OFFSET 0x152 | ||
| 367 | #define OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET 0x153 | ||
| 368 | |||
| 369 | #define OMAP2430_CONTROL_PADCONF_MUX_SIZE \ | ||
| 370 | (OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET + 0x1) | ||
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c index 2ff4dce95ee8..f64d7eea3451 100644 --- a/arch/arm/mach-omap2/mux34xx.c +++ b/arch/arm/mach-omap2/mux34xx.c | |||
| @@ -2032,19 +2032,19 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags) | |||
| 2032 | struct omap_ball *package_balls; | 2032 | struct omap_ball *package_balls; |
| 2033 | 2033 | ||
| 2034 | switch (flags & OMAP_PACKAGE_MASK) { | 2034 | switch (flags & OMAP_PACKAGE_MASK) { |
| 2035 | case (OMAP_PACKAGE_CBC): | 2035 | case OMAP_PACKAGE_CBC: |
| 2036 | package_subset = omap3_cbc_subset; | 2036 | package_subset = omap3_cbc_subset; |
| 2037 | package_balls = omap3_cbc_ball; | 2037 | package_balls = omap3_cbc_ball; |
| 2038 | break; | 2038 | break; |
| 2039 | case (OMAP_PACKAGE_CBB): | 2039 | case OMAP_PACKAGE_CBB: |
| 2040 | package_subset = omap3_cbb_subset; | 2040 | package_subset = omap3_cbb_subset; |
| 2041 | package_balls = omap3_cbb_ball; | 2041 | package_balls = omap3_cbb_ball; |
| 2042 | break; | 2042 | break; |
| 2043 | case (OMAP_PACKAGE_CUS): | 2043 | case OMAP_PACKAGE_CUS: |
| 2044 | package_subset = omap3_cus_subset; | 2044 | package_subset = omap3_cus_subset; |
| 2045 | package_balls = omap3_cus_ball; | 2045 | package_balls = omap3_cus_ball; |
| 2046 | break; | 2046 | break; |
| 2047 | case (OMAP_PACKAGE_CBP): | 2047 | case OMAP_PACKAGE_CBP: |
| 2048 | package_subset = omap36xx_cbp_subset; | 2048 | package_subset = omap36xx_cbp_subset; |
| 2049 | package_balls = omap36xx_cbp_ball; | 2049 | package_balls = omap36xx_cbp_ball; |
| 2050 | break; | 2050 | break; |
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index ef0e7a00dd6c..6ae937a06cc1 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S | |||
| @@ -47,19 +47,3 @@ hold: ldr r12,=0x103 | |||
| 47 | b secondary_startup | 47 | b secondary_startup |
| 48 | END(omap_secondary_startup) | 48 | END(omap_secondary_startup) |
| 49 | 49 | ||
| 50 | |||
| 51 | ENTRY(omap_modify_auxcoreboot0) | ||
| 52 | stmfd sp!, {r1-r12, lr} | ||
| 53 | ldr r12, =0x104 | ||
| 54 | dsb | ||
| 55 | smc #0 | ||
| 56 | ldmfd sp!, {r1-r12, pc} | ||
| 57 | END(omap_modify_auxcoreboot0) | ||
| 58 | |||
| 59 | ENTRY(omap_auxcoreboot_addr) | ||
| 60 | stmfd sp!, {r2-r12, lr} | ||
| 61 | ldr r12, =0x105 | ||
| 62 | dsb | ||
| 63 | smc #0 | ||
| 64 | ldmfd sp!, {r2-r12, pc} | ||
| 65 | END(omap_auxcoreboot_addr) | ||
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c new file mode 100644 index 000000000000..6cee456ca542 --- /dev/null +++ b/arch/arm/mach-omap2/omap-hotplug.c | |||
| @@ -0,0 +1,79 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 SMP cpu-hotplug support | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 5 | * Author: | ||
| 6 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | ||
| 7 | * | ||
| 8 | * Platform file needed for the OMAP4 SMP. This file is based on arm | ||
| 9 | * realview smp platform. | ||
| 10 | * Copyright (c) 2002 ARM Limited. | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/errno.h> | ||
| 19 | #include <linux/smp.h> | ||
| 20 | #include <linux/completion.h> | ||
| 21 | |||
| 22 | #include <asm/cacheflush.h> | ||
| 23 | #include <mach/omap4-common.h> | ||
| 24 | |||
| 25 | static DECLARE_COMPLETION(cpu_killed); | ||
| 26 | |||
| 27 | int platform_cpu_kill(unsigned int cpu) | ||
| 28 | { | ||
| 29 | return wait_for_completion_timeout(&cpu_killed, 5000); | ||
| 30 | } | ||
| 31 | |||
| 32 | /* | ||
| 33 | * platform-specific code to shutdown a CPU | ||
| 34 | * Called with IRQs disabled | ||
| 35 | */ | ||
| 36 | void platform_cpu_die(unsigned int cpu) | ||
| 37 | { | ||
| 38 | unsigned int this_cpu = hard_smp_processor_id(); | ||
| 39 | |||
| 40 | if (cpu != this_cpu) { | ||
| 41 | pr_crit("platform_cpu_die running on %u, should be %u\n", | ||
| 42 | this_cpu, cpu); | ||
| 43 | BUG(); | ||
| 44 | } | ||
| 45 | pr_notice("CPU%u: shutdown\n", cpu); | ||
| 46 | complete(&cpu_killed); | ||
| 47 | flush_cache_all(); | ||
| 48 | dsb(); | ||
| 49 | |||
| 50 | /* | ||
| 51 | * we're ready for shutdown now, so do it | ||
| 52 | */ | ||
| 53 | if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0) | ||
| 54 | printk(KERN_CRIT "Secure clear status failed\n"); | ||
| 55 | |||
| 56 | for (;;) { | ||
| 57 | /* | ||
| 58 | * Execute WFI | ||
| 59 | */ | ||
| 60 | do_wfi(); | ||
| 61 | |||
| 62 | if (omap_read_auxcoreboot0() == cpu) { | ||
| 63 | /* | ||
| 64 | * OK, proper wakeup, we're done | ||
| 65 | */ | ||
| 66 | break; | ||
| 67 | } | ||
| 68 | pr_debug("CPU%u: spurious wakeup call\n", cpu); | ||
| 69 | } | ||
| 70 | } | ||
| 71 | |||
| 72 | int platform_cpu_disable(unsigned int cpu) | ||
| 73 | { | ||
| 74 | /* | ||
| 75 | * we don't allow CPU 0 to be shutdown (it is still too special | ||
| 76 | * e.g. clock tick interrupts) | ||
| 77 | */ | ||
| 78 | return cpu == 0 ? -EPERM : 0; | ||
| 79 | } | ||
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index eb9bee73e0cb..f5a1aad1a5c0 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c | |||
| @@ -59,7 +59,7 @@ static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES]; | |||
| 59 | static struct iommu_device omap4_devices[] = { | 59 | static struct iommu_device omap4_devices[] = { |
| 60 | { | 60 | { |
| 61 | .base = OMAP4_MMU1_BASE, | 61 | .base = OMAP4_MMU1_BASE, |
| 62 | .irq = INT_44XX_DUCATI_MMU_IRQ, | 62 | .irq = OMAP44XX_IRQ_DUCATI_MMU, |
| 63 | .pdata = { | 63 | .pdata = { |
| 64 | .name = "ducati", | 64 | .name = "ducati", |
| 65 | .nr_tlb_entries = 32, | 65 | .nr_tlb_entries = 32, |
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 1cf52313759e..af3c20c8d3f9 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c | |||
| @@ -73,9 +73,10 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
| 73 | * the AuxCoreBoot1 register is updated with cpu state | 73 | * the AuxCoreBoot1 register is updated with cpu state |
| 74 | * A barrier is added to ensure that write buffer is drained | 74 | * A barrier is added to ensure that write buffer is drained |
| 75 | */ | 75 | */ |
| 76 | omap_modify_auxcoreboot0(0x200, 0x0); | 76 | omap_modify_auxcoreboot0(0x200, 0xfffffdff); |
| 77 | flush_cache_all(); | 77 | flush_cache_all(); |
| 78 | smp_wmb(); | 78 | smp_wmb(); |
| 79 | smp_cross_call(cpumask_of(cpu)); | ||
| 79 | 80 | ||
| 80 | /* | 81 | /* |
| 81 | * Now the secondary core is starting up let it run its | 82 | * Now the secondary core is starting up let it run its |
diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S index f61c7771ca47..1980dc31a1a2 100644 --- a/arch/arm/mach-omap2/omap44xx-smc.S +++ b/arch/arm/mach-omap2/omap44xx-smc.S | |||
| @@ -30,3 +30,28 @@ ENTRY(omap_smc1) | |||
| 30 | smc #0 | 30 | smc #0 |
| 31 | ldmfd sp!, {r2-r12, pc} | 31 | ldmfd sp!, {r2-r12, pc} |
| 32 | END(omap_smc1) | 32 | END(omap_smc1) |
| 33 | |||
| 34 | ENTRY(omap_modify_auxcoreboot0) | ||
| 35 | stmfd sp!, {r1-r12, lr} | ||
| 36 | ldr r12, =0x104 | ||
| 37 | dsb | ||
| 38 | smc #0 | ||
| 39 | ldmfd sp!, {r1-r12, pc} | ||
| 40 | END(omap_modify_auxcoreboot0) | ||
| 41 | |||
| 42 | ENTRY(omap_auxcoreboot_addr) | ||
| 43 | stmfd sp!, {r2-r12, lr} | ||
| 44 | ldr r12, =0x105 | ||
| 45 | dsb | ||
| 46 | smc #0 | ||
| 47 | ldmfd sp!, {r2-r12, pc} | ||
| 48 | END(omap_auxcoreboot_addr) | ||
| 49 | |||
| 50 | ENTRY(omap_read_auxcoreboot0) | ||
| 51 | stmfd sp!, {r2-r12, lr} | ||
| 52 | ldr r12, =0x103 | ||
| 53 | dsb | ||
| 54 | smc #0 | ||
| 55 | mov r0, r0, lsr #9 | ||
| 56 | ldmfd sp!, {r2-r12, pc} | ||
| 57 | END(omap_read_auxcoreboot0) | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index b7a4133267d8..cb911d7d1a3c 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * omap_hwmod implementation for OMAP2/3/4 | 2 | * omap_hwmod implementation for OMAP2/3/4 |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
| 5 | * | 5 | * |
| 6 | * Paul Walmsley, Benoît Cousson, Kevin Hilman | 6 | * Paul Walmsley, Benoît Cousson, Kevin Hilman |
| 7 | * | 7 | * |
| @@ -423,7 +423,7 @@ static int _init_main_clk(struct omap_hwmod *oh) | |||
| 423 | } | 423 | } |
| 424 | 424 | ||
| 425 | /** | 425 | /** |
| 426 | * _init_interface_clk - get a struct clk * for the the hwmod's interface clks | 426 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
| 427 | * @oh: struct omap_hwmod * | 427 | * @oh: struct omap_hwmod * |
| 428 | * | 428 | * |
| 429 | * Called from _init_clocks(). Populates the @oh OCP slave interface | 429 | * Called from _init_clocks(). Populates the @oh OCP slave interface |
| @@ -764,6 +764,7 @@ static struct omap_hwmod *_lookup(const char *name) | |||
| 764 | /** | 764 | /** |
| 765 | * _init_clocks - clk_get() all clocks associated with this hwmod | 765 | * _init_clocks - clk_get() all clocks associated with this hwmod |
| 766 | * @oh: struct omap_hwmod * | 766 | * @oh: struct omap_hwmod * |
| 767 | * @data: not used; pass NULL | ||
| 767 | * | 768 | * |
| 768 | * Called by omap_hwmod_late_init() (after omap2_clk_init()). | 769 | * Called by omap_hwmod_late_init() (after omap2_clk_init()). |
| 769 | * Resolves all clock names embedded in the hwmod. Must be called | 770 | * Resolves all clock names embedded in the hwmod. Must be called |
| @@ -771,7 +772,7 @@ static struct omap_hwmod *_lookup(const char *name) | |||
| 771 | * has not yet been registered or if the clocks have already been | 772 | * has not yet been registered or if the clocks have already been |
| 772 | * initialized, 0 on success, or a non-zero error on failure. | 773 | * initialized, 0 on success, or a non-zero error on failure. |
| 773 | */ | 774 | */ |
| 774 | static int _init_clocks(struct omap_hwmod *oh) | 775 | static int _init_clocks(struct omap_hwmod *oh, void *data) |
| 775 | { | 776 | { |
| 776 | int ret = 0; | 777 | int ret = 0; |
| 777 | 778 | ||
| @@ -886,7 +887,7 @@ static int _reset(struct omap_hwmod *oh) | |||
| 886 | } | 887 | } |
| 887 | 888 | ||
| 888 | /** | 889 | /** |
| 889 | * _enable - enable an omap_hwmod | 890 | * _omap_hwmod_enable - enable an omap_hwmod |
| 890 | * @oh: struct omap_hwmod * | 891 | * @oh: struct omap_hwmod * |
| 891 | * | 892 | * |
| 892 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | 893 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's |
| @@ -894,7 +895,7 @@ static int _reset(struct omap_hwmod *oh) | |||
| 894 | * Returns -EINVAL if the hwmod is in the wrong state or passes along | 895 | * Returns -EINVAL if the hwmod is in the wrong state or passes along |
| 895 | * the return value of _wait_target_ready(). | 896 | * the return value of _wait_target_ready(). |
| 896 | */ | 897 | */ |
| 897 | static int _enable(struct omap_hwmod *oh) | 898 | int _omap_hwmod_enable(struct omap_hwmod *oh) |
| 898 | { | 899 | { |
| 899 | int r; | 900 | int r; |
| 900 | 901 | ||
| @@ -939,7 +940,7 @@ static int _enable(struct omap_hwmod *oh) | |||
| 939 | * no further work. Returns -EINVAL if the hwmod is in the wrong | 940 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
| 940 | * state or returns 0. | 941 | * state or returns 0. |
| 941 | */ | 942 | */ |
| 942 | static int _idle(struct omap_hwmod *oh) | 943 | int _omap_hwmod_idle(struct omap_hwmod *oh) |
| 943 | { | 944 | { |
| 944 | if (oh->_state != _HWMOD_STATE_ENABLED) { | 945 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
| 945 | WARN(1, "omap_hwmod: %s: idle state can only be entered from " | 946 | WARN(1, "omap_hwmod: %s: idle state can only be entered from " |
| @@ -996,19 +997,25 @@ static int _shutdown(struct omap_hwmod *oh) | |||
| 996 | /** | 997 | /** |
| 997 | * _setup - do initial configuration of omap_hwmod | 998 | * _setup - do initial configuration of omap_hwmod |
| 998 | * @oh: struct omap_hwmod * | 999 | * @oh: struct omap_hwmod * |
| 1000 | * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1 | ||
| 999 | * | 1001 | * |
| 1000 | * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh | 1002 | * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh |
| 1001 | * OCP_SYSCONFIG register. Must be called with omap_hwmod_mutex | 1003 | * OCP_SYSCONFIG register. Must be called with omap_hwmod_mutex held. |
| 1002 | * held. Returns -EINVAL if the hwmod is in the wrong state or returns | 1004 | * @skip_setup_idle is intended to be used on a system that will not |
| 1003 | * 0. | 1005 | * call omap_hwmod_enable() to enable devices (e.g., a system without |
| 1006 | * PM runtime). Returns -EINVAL if the hwmod is in the wrong state or | ||
| 1007 | * returns 0. | ||
| 1004 | */ | 1008 | */ |
| 1005 | static int _setup(struct omap_hwmod *oh) | 1009 | static int _setup(struct omap_hwmod *oh, void *data) |
| 1006 | { | 1010 | { |
| 1007 | int i, r; | 1011 | int i, r; |
| 1012 | u8 skip_setup_idle; | ||
| 1008 | 1013 | ||
| 1009 | if (!oh) | 1014 | if (!oh || !data) |
| 1010 | return -EINVAL; | 1015 | return -EINVAL; |
| 1011 | 1016 | ||
| 1017 | skip_setup_idle = *(u8 *)data; | ||
| 1018 | |||
| 1012 | /* Set iclk autoidle mode */ | 1019 | /* Set iclk autoidle mode */ |
| 1013 | if (oh->slaves_cnt > 0) { | 1020 | if (oh->slaves_cnt > 0) { |
| 1014 | for (i = 0; i < oh->slaves_cnt; i++) { | 1021 | for (i = 0; i < oh->slaves_cnt; i++) { |
| @@ -1029,7 +1036,7 @@ static int _setup(struct omap_hwmod *oh) | |||
| 1029 | 1036 | ||
| 1030 | oh->_state = _HWMOD_STATE_INITIALIZED; | 1037 | oh->_state = _HWMOD_STATE_INITIALIZED; |
| 1031 | 1038 | ||
| 1032 | r = _enable(oh); | 1039 | r = _omap_hwmod_enable(oh); |
| 1033 | if (r) { | 1040 | if (r) { |
| 1034 | pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", | 1041 | pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", |
| 1035 | oh->name, oh->_state); | 1042 | oh->name, oh->_state); |
| @@ -1041,7 +1048,7 @@ static int _setup(struct omap_hwmod *oh) | |||
| 1041 | * XXX Do the OCP_SYSCONFIG bits need to be | 1048 | * XXX Do the OCP_SYSCONFIG bits need to be |
| 1042 | * reprogrammed after a reset? If not, then this can | 1049 | * reprogrammed after a reset? If not, then this can |
| 1043 | * be removed. If they do, then probably the | 1050 | * be removed. If they do, then probably the |
| 1044 | * _enable() function should be split to avoid the | 1051 | * _omap_hwmod_enable() function should be split to avoid the |
| 1045 | * rewrite of the OCP_SYSCONFIG register. | 1052 | * rewrite of the OCP_SYSCONFIG register. |
| 1046 | */ | 1053 | */ |
| 1047 | if (oh->class->sysc) { | 1054 | if (oh->class->sysc) { |
| @@ -1050,8 +1057,8 @@ static int _setup(struct omap_hwmod *oh) | |||
| 1050 | } | 1057 | } |
| 1051 | } | 1058 | } |
| 1052 | 1059 | ||
| 1053 | if (!(oh->flags & HWMOD_INIT_NO_IDLE)) | 1060 | if (!(oh->flags & HWMOD_INIT_NO_IDLE) && !skip_setup_idle) |
| 1054 | _idle(oh); | 1061 | _omap_hwmod_idle(oh); |
| 1055 | 1062 | ||
| 1056 | return 0; | 1063 | return 0; |
| 1057 | } | 1064 | } |
| @@ -1062,14 +1069,29 @@ static int _setup(struct omap_hwmod *oh) | |||
| 1062 | 1069 | ||
| 1063 | u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs) | 1070 | u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs) |
| 1064 | { | 1071 | { |
| 1065 | return __raw_readl(oh->_rt_va + reg_offs); | 1072 | return __raw_readl(oh->_mpu_rt_va + reg_offs); |
| 1066 | } | 1073 | } |
| 1067 | 1074 | ||
| 1068 | void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs) | 1075 | void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs) |
| 1069 | { | 1076 | { |
| 1070 | __raw_writel(v, oh->_rt_va + reg_offs); | 1077 | __raw_writel(v, oh->_mpu_rt_va + reg_offs); |
| 1071 | } | 1078 | } |
| 1072 | 1079 | ||
| 1080 | /** | ||
| 1081 | * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode | ||
| 1082 | * @oh: struct omap_hwmod * | ||
| 1083 | * @idlemode: SIDLEMODE field bits (shifted to bit 0) | ||
| 1084 | * | ||
| 1085 | * Sets the IP block's OCP slave idlemode in hardware, and updates our | ||
| 1086 | * local copy. Intended to be used by drivers that have some erratum | ||
| 1087 | * that requires direct manipulation of the SIDLEMODE bits. Returns | ||
| 1088 | * -EINVAL if @oh is null, or passes along the return value from | ||
| 1089 | * _set_slave_idlemode(). | ||
| 1090 | * | ||
| 1091 | * XXX Does this function have any current users? If not, we should | ||
| 1092 | * remove it; it is better to let the rest of the hwmod code handle this. | ||
| 1093 | * Any users of this function should be scrutinized carefully. | ||
| 1094 | */ | ||
| 1073 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) | 1095 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) |
| 1074 | { | 1096 | { |
| 1075 | u32 v; | 1097 | u32 v; |
| @@ -1124,7 +1146,7 @@ int omap_hwmod_register(struct omap_hwmod *oh) | |||
| 1124 | ms_id = _find_mpu_port_index(oh); | 1146 | ms_id = _find_mpu_port_index(oh); |
| 1125 | if (!IS_ERR_VALUE(ms_id)) { | 1147 | if (!IS_ERR_VALUE(ms_id)) { |
| 1126 | oh->_mpu_port_index = ms_id; | 1148 | oh->_mpu_port_index = ms_id; |
| 1127 | oh->_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); | 1149 | oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); |
| 1128 | } else { | 1150 | } else { |
| 1129 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | 1151 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; |
| 1130 | } | 1152 | } |
| @@ -1164,6 +1186,7 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name) | |||
| 1164 | /** | 1186 | /** |
| 1165 | * omap_hwmod_for_each - call function for each registered omap_hwmod | 1187 | * omap_hwmod_for_each - call function for each registered omap_hwmod |
| 1166 | * @fn: pointer to a callback function | 1188 | * @fn: pointer to a callback function |
| 1189 | * @data: void * data to pass to callback function | ||
| 1167 | * | 1190 | * |
| 1168 | * Call @fn for each registered omap_hwmod, passing @data to each | 1191 | * Call @fn for each registered omap_hwmod, passing @data to each |
| 1169 | * function. @fn must return 0 for success or any other value for | 1192 | * function. @fn must return 0 for success or any other value for |
| @@ -1172,7 +1195,8 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name) | |||
| 1172 | * caller of omap_hwmod_for_each(). @fn is called with | 1195 | * caller of omap_hwmod_for_each(). @fn is called with |
| 1173 | * omap_hwmod_for_each() held. | 1196 | * omap_hwmod_for_each() held. |
| 1174 | */ | 1197 | */ |
| 1175 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh)) | 1198 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
| 1199 | void *data) | ||
| 1176 | { | 1200 | { |
| 1177 | struct omap_hwmod *temp_oh; | 1201 | struct omap_hwmod *temp_oh; |
| 1178 | int ret; | 1202 | int ret; |
| @@ -1182,7 +1206,7 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh)) | |||
| 1182 | 1206 | ||
| 1183 | mutex_lock(&omap_hwmod_mutex); | 1207 | mutex_lock(&omap_hwmod_mutex); |
| 1184 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | 1208 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
| 1185 | ret = (*fn)(temp_oh); | 1209 | ret = (*fn)(temp_oh, data); |
| 1186 | if (ret) | 1210 | if (ret) |
| 1187 | break; | 1211 | break; |
| 1188 | } | 1212 | } |
| @@ -1229,24 +1253,28 @@ int omap_hwmod_init(struct omap_hwmod **ohs) | |||
| 1229 | 1253 | ||
| 1230 | /** | 1254 | /** |
| 1231 | * omap_hwmod_late_init - do some post-clock framework initialization | 1255 | * omap_hwmod_late_init - do some post-clock framework initialization |
| 1256 | * @skip_setup_idle: if 1, do not idle hwmods in _setup() | ||
| 1232 | * | 1257 | * |
| 1233 | * Must be called after omap2_clk_init(). Resolves the struct clk names | 1258 | * Must be called after omap2_clk_init(). Resolves the struct clk names |
| 1234 | * to struct clk pointers for each registered omap_hwmod. Also calls | 1259 | * to struct clk pointers for each registered omap_hwmod. Also calls |
| 1235 | * _setup() on each hwmod. Returns 0. | 1260 | * _setup() on each hwmod. Returns 0. |
| 1236 | */ | 1261 | */ |
| 1237 | int omap_hwmod_late_init(void) | 1262 | int omap_hwmod_late_init(u8 skip_setup_idle) |
| 1238 | { | 1263 | { |
| 1239 | int r; | 1264 | int r; |
| 1240 | 1265 | ||
| 1241 | /* XXX check return value */ | 1266 | /* XXX check return value */ |
| 1242 | r = omap_hwmod_for_each(_init_clocks); | 1267 | r = omap_hwmod_for_each(_init_clocks, NULL); |
| 1243 | WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n"); | 1268 | WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n"); |
| 1244 | 1269 | ||
| 1245 | mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME); | 1270 | mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME); |
| 1246 | WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", | 1271 | WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", |
| 1247 | MPU_INITIATOR_NAME); | 1272 | MPU_INITIATOR_NAME); |
| 1248 | 1273 | ||
| 1249 | omap_hwmod_for_each(_setup); | 1274 | if (skip_setup_idle) |
| 1275 | pr_debug("omap_hwmod: will leave hwmods enabled during setup\n"); | ||
| 1276 | |||
| 1277 | omap_hwmod_for_each(_setup, &skip_setup_idle); | ||
| 1250 | 1278 | ||
| 1251 | return 0; | 1279 | return 0; |
| 1252 | } | 1280 | } |
| @@ -1270,7 +1298,7 @@ int omap_hwmod_unregister(struct omap_hwmod *oh) | |||
| 1270 | pr_debug("omap_hwmod: %s: unregistering\n", oh->name); | 1298 | pr_debug("omap_hwmod: %s: unregistering\n", oh->name); |
| 1271 | 1299 | ||
| 1272 | mutex_lock(&omap_hwmod_mutex); | 1300 | mutex_lock(&omap_hwmod_mutex); |
| 1273 | iounmap(oh->_rt_va); | 1301 | iounmap(oh->_mpu_rt_va); |
| 1274 | list_del(&oh->node); | 1302 | list_del(&oh->node); |
| 1275 | mutex_unlock(&omap_hwmod_mutex); | 1303 | mutex_unlock(&omap_hwmod_mutex); |
| 1276 | 1304 | ||
| @@ -1292,12 +1320,13 @@ int omap_hwmod_enable(struct omap_hwmod *oh) | |||
| 1292 | return -EINVAL; | 1320 | return -EINVAL; |
| 1293 | 1321 | ||
| 1294 | mutex_lock(&omap_hwmod_mutex); | 1322 | mutex_lock(&omap_hwmod_mutex); |
| 1295 | r = _enable(oh); | 1323 | r = _omap_hwmod_enable(oh); |
| 1296 | mutex_unlock(&omap_hwmod_mutex); | 1324 | mutex_unlock(&omap_hwmod_mutex); |
| 1297 | 1325 | ||
| 1298 | return r; | 1326 | return r; |
| 1299 | } | 1327 | } |
| 1300 | 1328 | ||
| 1329 | |||
| 1301 | /** | 1330 | /** |
| 1302 | * omap_hwmod_idle - idle an omap_hwmod | 1331 | * omap_hwmod_idle - idle an omap_hwmod |
| 1303 | * @oh: struct omap_hwmod * | 1332 | * @oh: struct omap_hwmod * |
| @@ -1311,7 +1340,7 @@ int omap_hwmod_idle(struct omap_hwmod *oh) | |||
| 1311 | return -EINVAL; | 1340 | return -EINVAL; |
| 1312 | 1341 | ||
| 1313 | mutex_lock(&omap_hwmod_mutex); | 1342 | mutex_lock(&omap_hwmod_mutex); |
| 1314 | _idle(oh); | 1343 | _omap_hwmod_idle(oh); |
| 1315 | mutex_unlock(&omap_hwmod_mutex); | 1344 | mutex_unlock(&omap_hwmod_mutex); |
| 1316 | 1345 | ||
| 1317 | return 0; | 1346 | return 0; |
| @@ -1413,7 +1442,7 @@ int omap_hwmod_reset(struct omap_hwmod *oh) | |||
| 1413 | mutex_lock(&omap_hwmod_mutex); | 1442 | mutex_lock(&omap_hwmod_mutex); |
| 1414 | r = _reset(oh); | 1443 | r = _reset(oh); |
| 1415 | if (!r) | 1444 | if (!r) |
| 1416 | r = _enable(oh); | 1445 | r = _omap_hwmod_enable(oh); |
| 1417 | mutex_unlock(&omap_hwmod_mutex); | 1446 | mutex_unlock(&omap_hwmod_mutex); |
| 1418 | 1447 | ||
| 1419 | return r; | 1448 | return r; |
| @@ -1530,6 +1559,29 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |||
| 1530 | } | 1559 | } |
| 1531 | 1560 | ||
| 1532 | /** | 1561 | /** |
| 1562 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | ||
| 1563 | * @oh: struct omap_hwmod * | ||
| 1564 | * | ||
| 1565 | * Returns the virtual address corresponding to the beginning of the | ||
| 1566 | * module's register target, in the address range that is intended to | ||
| 1567 | * be used by the MPU. Returns the virtual address upon success or NULL | ||
| 1568 | * upon error. | ||
| 1569 | */ | ||
| 1570 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | ||
| 1571 | { | ||
| 1572 | if (!oh) | ||
| 1573 | return NULL; | ||
| 1574 | |||
| 1575 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | ||
| 1576 | return NULL; | ||
| 1577 | |||
| 1578 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | ||
| 1579 | return NULL; | ||
| 1580 | |||
| 1581 | return oh->_mpu_rt_va; | ||
| 1582 | } | ||
| 1583 | |||
| 1584 | /** | ||
| 1533 | * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh | 1585 | * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh |
| 1534 | * @oh: struct omap_hwmod * | 1586 | * @oh: struct omap_hwmod * |
| 1535 | * @init_oh: struct omap_hwmod * (initiator) | 1587 | * @init_oh: struct omap_hwmod * (initiator) |
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index e5530c51f77d..3cc768e8bc04 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c | |||
| @@ -30,42 +30,44 @@ | |||
| 30 | */ | 30 | */ |
| 31 | 31 | ||
| 32 | static struct omap_hwmod omap2420_mpu_hwmod; | 32 | static struct omap_hwmod omap2420_mpu_hwmod; |
| 33 | static struct omap_hwmod omap2420_l3_hwmod; | 33 | static struct omap_hwmod omap2420_iva_hwmod; |
| 34 | static struct omap_hwmod omap2420_l3_main_hwmod; | ||
| 34 | static struct omap_hwmod omap2420_l4_core_hwmod; | 35 | static struct omap_hwmod omap2420_l4_core_hwmod; |
| 35 | 36 | ||
| 36 | /* L3 -> L4_CORE interface */ | 37 | /* L3 -> L4_CORE interface */ |
| 37 | static struct omap_hwmod_ocp_if omap2420_l3__l4_core = { | 38 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { |
| 38 | .master = &omap2420_l3_hwmod, | 39 | .master = &omap2420_l3_main_hwmod, |
| 39 | .slave = &omap2420_l4_core_hwmod, | 40 | .slave = &omap2420_l4_core_hwmod, |
| 40 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 41 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 41 | }; | 42 | }; |
| 42 | 43 | ||
| 43 | /* MPU -> L3 interface */ | 44 | /* MPU -> L3 interface */ |
| 44 | static struct omap_hwmod_ocp_if omap2420_mpu__l3 = { | 45 | static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { |
| 45 | .master = &omap2420_mpu_hwmod, | 46 | .master = &omap2420_mpu_hwmod, |
| 46 | .slave = &omap2420_l3_hwmod, | 47 | .slave = &omap2420_l3_main_hwmod, |
| 47 | .user = OCP_USER_MPU, | 48 | .user = OCP_USER_MPU, |
| 48 | }; | 49 | }; |
| 49 | 50 | ||
| 50 | /* Slave interfaces on the L3 interconnect */ | 51 | /* Slave interfaces on the L3 interconnect */ |
| 51 | static struct omap_hwmod_ocp_if *omap2420_l3_slaves[] = { | 52 | static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { |
| 52 | &omap2420_mpu__l3, | 53 | &omap2420_mpu__l3_main, |
| 53 | }; | 54 | }; |
| 54 | 55 | ||
| 55 | /* Master interfaces on the L3 interconnect */ | 56 | /* Master interfaces on the L3 interconnect */ |
| 56 | static struct omap_hwmod_ocp_if *omap2420_l3_masters[] = { | 57 | static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { |
| 57 | &omap2420_l3__l4_core, | 58 | &omap2420_l3_main__l4_core, |
| 58 | }; | 59 | }; |
| 59 | 60 | ||
| 60 | /* L3 */ | 61 | /* L3 */ |
| 61 | static struct omap_hwmod omap2420_l3_hwmod = { | 62 | static struct omap_hwmod omap2420_l3_main_hwmod = { |
| 62 | .name = "l3_hwmod", | 63 | .name = "l3_main", |
| 63 | .class = &l3_hwmod_class, | 64 | .class = &l3_hwmod_class, |
| 64 | .masters = omap2420_l3_masters, | 65 | .masters = omap2420_l3_main_masters, |
| 65 | .masters_cnt = ARRAY_SIZE(omap2420_l3_masters), | 66 | .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), |
| 66 | .slaves = omap2420_l3_slaves, | 67 | .slaves = omap2420_l3_main_slaves, |
| 67 | .slaves_cnt = ARRAY_SIZE(omap2420_l3_slaves), | 68 | .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), |
| 68 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | 69 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 70 | .flags = HWMOD_NO_IDLEST, | ||
| 69 | }; | 71 | }; |
| 70 | 72 | ||
| 71 | static struct omap_hwmod omap2420_l4_wkup_hwmod; | 73 | static struct omap_hwmod omap2420_l4_wkup_hwmod; |
| @@ -79,7 +81,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { | |||
| 79 | 81 | ||
| 80 | /* Slave interfaces on the L4_CORE interconnect */ | 82 | /* Slave interfaces on the L4_CORE interconnect */ |
| 81 | static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { | 83 | static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { |
| 82 | &omap2420_l3__l4_core, | 84 | &omap2420_l3_main__l4_core, |
| 83 | }; | 85 | }; |
| 84 | 86 | ||
| 85 | /* Master interfaces on the L4_CORE interconnect */ | 87 | /* Master interfaces on the L4_CORE interconnect */ |
| @@ -89,13 +91,14 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { | |||
| 89 | 91 | ||
| 90 | /* L4 CORE */ | 92 | /* L4 CORE */ |
| 91 | static struct omap_hwmod omap2420_l4_core_hwmod = { | 93 | static struct omap_hwmod omap2420_l4_core_hwmod = { |
| 92 | .name = "l4_core_hwmod", | 94 | .name = "l4_core", |
| 93 | .class = &l4_hwmod_class, | 95 | .class = &l4_hwmod_class, |
| 94 | .masters = omap2420_l4_core_masters, | 96 | .masters = omap2420_l4_core_masters, |
| 95 | .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), | 97 | .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), |
| 96 | .slaves = omap2420_l4_core_slaves, | 98 | .slaves = omap2420_l4_core_slaves, |
| 97 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), | 99 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), |
| 98 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | 100 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 101 | .flags = HWMOD_NO_IDLEST, | ||
| 99 | }; | 102 | }; |
| 100 | 103 | ||
| 101 | /* Slave interfaces on the L4_WKUP interconnect */ | 104 | /* Slave interfaces on the L4_WKUP interconnect */ |
| @@ -109,18 +112,19 @@ static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { | |||
| 109 | 112 | ||
| 110 | /* L4 WKUP */ | 113 | /* L4 WKUP */ |
| 111 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { | 114 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { |
| 112 | .name = "l4_wkup_hwmod", | 115 | .name = "l4_wkup", |
| 113 | .class = &l4_hwmod_class, | 116 | .class = &l4_hwmod_class, |
| 114 | .masters = omap2420_l4_wkup_masters, | 117 | .masters = omap2420_l4_wkup_masters, |
| 115 | .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), | 118 | .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), |
| 116 | .slaves = omap2420_l4_wkup_slaves, | 119 | .slaves = omap2420_l4_wkup_slaves, |
| 117 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), | 120 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), |
| 118 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | 121 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 122 | .flags = HWMOD_NO_IDLEST, | ||
| 119 | }; | 123 | }; |
| 120 | 124 | ||
| 121 | /* Master interfaces on the MPU device */ | 125 | /* Master interfaces on the MPU device */ |
| 122 | static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { | 126 | static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { |
| 123 | &omap2420_mpu__l3, | 127 | &omap2420_mpu__l3_main, |
| 124 | }; | 128 | }; |
| 125 | 129 | ||
| 126 | /* MPU */ | 130 | /* MPU */ |
| @@ -133,11 +137,40 @@ static struct omap_hwmod omap2420_mpu_hwmod = { | |||
| 133 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 137 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 134 | }; | 138 | }; |
| 135 | 139 | ||
| 140 | /* | ||
| 141 | * IVA1 interface data | ||
| 142 | */ | ||
| 143 | |||
| 144 | /* IVA <- L3 interface */ | ||
| 145 | static struct omap_hwmod_ocp_if omap2420_l3__iva = { | ||
| 146 | .master = &omap2420_l3_main_hwmod, | ||
| 147 | .slave = &omap2420_iva_hwmod, | ||
| 148 | .clk = "iva1_ifck", | ||
| 149 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 150 | }; | ||
| 151 | |||
| 152 | static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { | ||
| 153 | &omap2420_l3__iva, | ||
| 154 | }; | ||
| 155 | |||
| 156 | /* | ||
| 157 | * IVA2 (IVA2) | ||
| 158 | */ | ||
| 159 | |||
| 160 | static struct omap_hwmod omap2420_iva_hwmod = { | ||
| 161 | .name = "iva", | ||
| 162 | .class = &iva_hwmod_class, | ||
| 163 | .masters = omap2420_iva_masters, | ||
| 164 | .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), | ||
| 165 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | ||
| 166 | }; | ||
| 167 | |||
| 136 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { | 168 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { |
| 137 | &omap2420_l3_hwmod, | 169 | &omap2420_l3_main_hwmod, |
| 138 | &omap2420_l4_core_hwmod, | 170 | &omap2420_l4_core_hwmod, |
| 139 | &omap2420_l4_wkup_hwmod, | 171 | &omap2420_l4_wkup_hwmod, |
| 140 | &omap2420_mpu_hwmod, | 172 | &omap2420_mpu_hwmod, |
| 173 | &omap2420_iva_hwmod, | ||
| 141 | NULL, | 174 | NULL, |
| 142 | }; | 175 | }; |
| 143 | 176 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 0852d954da40..4526628ed287 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c | |||
| @@ -30,47 +30,47 @@ | |||
| 30 | */ | 30 | */ |
| 31 | 31 | ||
| 32 | static struct omap_hwmod omap2430_mpu_hwmod; | 32 | static struct omap_hwmod omap2430_mpu_hwmod; |
| 33 | static struct omap_hwmod omap2430_l3_hwmod; | 33 | static struct omap_hwmod omap2430_iva_hwmod; |
| 34 | static struct omap_hwmod omap2430_l3_main_hwmod; | ||
| 34 | static struct omap_hwmod omap2430_l4_core_hwmod; | 35 | static struct omap_hwmod omap2430_l4_core_hwmod; |
| 35 | 36 | ||
| 36 | /* L3 -> L4_CORE interface */ | 37 | /* L3 -> L4_CORE interface */ |
| 37 | static struct omap_hwmod_ocp_if omap2430_l3__l4_core = { | 38 | static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { |
| 38 | .master = &omap2430_l3_hwmod, | 39 | .master = &omap2430_l3_main_hwmod, |
| 39 | .slave = &omap2430_l4_core_hwmod, | 40 | .slave = &omap2430_l4_core_hwmod, |
| 40 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 41 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 41 | }; | 42 | }; |
| 42 | 43 | ||
| 43 | /* MPU -> L3 interface */ | 44 | /* MPU -> L3 interface */ |
| 44 | static struct omap_hwmod_ocp_if omap2430_mpu__l3 = { | 45 | static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { |
| 45 | .master = &omap2430_mpu_hwmod, | 46 | .master = &omap2430_mpu_hwmod, |
| 46 | .slave = &omap2430_l3_hwmod, | 47 | .slave = &omap2430_l3_main_hwmod, |
| 47 | .user = OCP_USER_MPU, | 48 | .user = OCP_USER_MPU, |
| 48 | }; | 49 | }; |
| 49 | 50 | ||
| 50 | /* Slave interfaces on the L3 interconnect */ | 51 | /* Slave interfaces on the L3 interconnect */ |
| 51 | static struct omap_hwmod_ocp_if *omap2430_l3_slaves[] = { | 52 | static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { |
| 52 | &omap2430_mpu__l3, | 53 | &omap2430_mpu__l3_main, |
| 53 | }; | 54 | }; |
| 54 | 55 | ||
| 55 | /* Master interfaces on the L3 interconnect */ | 56 | /* Master interfaces on the L3 interconnect */ |
| 56 | static struct omap_hwmod_ocp_if *omap2430_l3_masters[] = { | 57 | static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { |
| 57 | &omap2430_l3__l4_core, | 58 | &omap2430_l3_main__l4_core, |
| 58 | }; | 59 | }; |
| 59 | 60 | ||
| 60 | /* L3 */ | 61 | /* L3 */ |
| 61 | static struct omap_hwmod omap2430_l3_hwmod = { | 62 | static struct omap_hwmod omap2430_l3_main_hwmod = { |
| 62 | .name = "l3_hwmod", | 63 | .name = "l3_main", |
| 63 | .class = &l3_hwmod_class, | 64 | .class = &l3_hwmod_class, |
| 64 | .masters = omap2430_l3_masters, | 65 | .masters = omap2430_l3_main_masters, |
| 65 | .masters_cnt = ARRAY_SIZE(omap2430_l3_masters), | 66 | .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), |
| 66 | .slaves = omap2430_l3_slaves, | 67 | .slaves = omap2430_l3_main_slaves, |
| 67 | .slaves_cnt = ARRAY_SIZE(omap2430_l3_slaves), | 68 | .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), |
| 68 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | 69 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| 70 | .flags = HWMOD_NO_IDLEST, | ||
| 69 | }; | 71 | }; |
| 70 | 72 | ||
| 71 | static struct omap_hwmod omap2430_l4_wkup_hwmod; | 73 | static struct omap_hwmod omap2430_l4_wkup_hwmod; |
| 72 | static struct omap_hwmod omap2430_mmc1_hwmod; | ||
| 73 | static struct omap_hwmod omap2430_mmc2_hwmod; | ||
| 74 | 74 | ||
| 75 | /* L4_CORE -> L4_WKUP interface */ | 75 | /* L4_CORE -> L4_WKUP interface */ |
| 76 | static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { | 76 | static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { |
| @@ -81,7 +81,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { | |||
| 81 | 81 | ||
| 82 | /* Slave interfaces on the L4_CORE interconnect */ | 82 | /* Slave interfaces on the L4_CORE interconnect */ |
| 83 | static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { | 83 | static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { |
| 84 | &omap2430_l3__l4_core, | 84 | &omap2430_l3_main__l4_core, |
| 85 | }; | 85 | }; |
| 86 | 86 | ||
| 87 | /* Master interfaces on the L4_CORE interconnect */ | 87 | /* Master interfaces on the L4_CORE interconnect */ |
| @@ -91,13 +91,14 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { | |||
| 91 | 91 | ||
| 92 | /* L4 CORE */ | 92 | /* L4 CORE */ |
| 93 | static struct omap_hwmod omap2430_l4_core_hwmod = { | 93 | static struct omap_hwmod omap2430_l4_core_hwmod = { |
| 94 | .name = "l4_core_hwmod", | 94 | .name = "l4_core", |
| 95 | .class = &l4_hwmod_class, | 95 | .class = &l4_hwmod_class, |
| 96 | .masters = omap2430_l4_core_masters, | 96 | .masters = omap2430_l4_core_masters, |
| 97 | .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), | 97 | .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), |
| 98 | .slaves = omap2430_l4_core_slaves, | 98 | .slaves = omap2430_l4_core_slaves, |
| 99 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), | 99 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), |
| 100 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | 100 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| 101 | .flags = HWMOD_NO_IDLEST, | ||
| 101 | }; | 102 | }; |
| 102 | 103 | ||
| 103 | /* Slave interfaces on the L4_WKUP interconnect */ | 104 | /* Slave interfaces on the L4_WKUP interconnect */ |
| @@ -111,18 +112,19 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { | |||
| 111 | 112 | ||
| 112 | /* L4 WKUP */ | 113 | /* L4 WKUP */ |
| 113 | static struct omap_hwmod omap2430_l4_wkup_hwmod = { | 114 | static struct omap_hwmod omap2430_l4_wkup_hwmod = { |
| 114 | .name = "l4_wkup_hwmod", | 115 | .name = "l4_wkup", |
| 115 | .class = &l4_hwmod_class, | 116 | .class = &l4_hwmod_class, |
| 116 | .masters = omap2430_l4_wkup_masters, | 117 | .masters = omap2430_l4_wkup_masters, |
| 117 | .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), | 118 | .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), |
| 118 | .slaves = omap2430_l4_wkup_slaves, | 119 | .slaves = omap2430_l4_wkup_slaves, |
| 119 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), | 120 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), |
| 120 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | 121 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| 122 | .flags = HWMOD_NO_IDLEST, | ||
| 121 | }; | 123 | }; |
| 122 | 124 | ||
| 123 | /* Master interfaces on the MPU device */ | 125 | /* Master interfaces on the MPU device */ |
| 124 | static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { | 126 | static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { |
| 125 | &omap2430_mpu__l3, | 127 | &omap2430_mpu__l3_main, |
| 126 | }; | 128 | }; |
| 127 | 129 | ||
| 128 | /* MPU */ | 130 | /* MPU */ |
| @@ -135,11 +137,40 @@ static struct omap_hwmod omap2430_mpu_hwmod = { | |||
| 135 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 137 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| 136 | }; | 138 | }; |
| 137 | 139 | ||
| 140 | /* | ||
| 141 | * IVA2_1 interface data | ||
| 142 | */ | ||
| 143 | |||
| 144 | /* IVA2 <- L3 interface */ | ||
| 145 | static struct omap_hwmod_ocp_if omap2430_l3__iva = { | ||
| 146 | .master = &omap2430_l3_main_hwmod, | ||
| 147 | .slave = &omap2430_iva_hwmod, | ||
| 148 | .clk = "dsp_fck", | ||
| 149 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 150 | }; | ||
| 151 | |||
| 152 | static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { | ||
| 153 | &omap2430_l3__iva, | ||
| 154 | }; | ||
| 155 | |||
| 156 | /* | ||
| 157 | * IVA2 (IVA2) | ||
| 158 | */ | ||
| 159 | |||
| 160 | static struct omap_hwmod omap2430_iva_hwmod = { | ||
| 161 | .name = "iva", | ||
| 162 | .class = &iva_hwmod_class, | ||
| 163 | .masters = omap2430_iva_masters, | ||
| 164 | .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), | ||
| 165 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | ||
| 166 | }; | ||
| 167 | |||
| 138 | static __initdata struct omap_hwmod *omap2430_hwmods[] = { | 168 | static __initdata struct omap_hwmod *omap2430_hwmods[] = { |
| 139 | &omap2430_l3_hwmod, | 169 | &omap2430_l3_main_hwmod, |
| 140 | &omap2430_l4_core_hwmod, | 170 | &omap2430_l4_core_hwmod, |
| 141 | &omap2430_l4_wkup_hwmod, | 171 | &omap2430_l4_wkup_hwmod, |
| 142 | &omap2430_mpu_hwmod, | 172 | &omap2430_mpu_hwmod, |
| 173 | &omap2430_iva_hwmod, | ||
| 143 | NULL, | 174 | NULL, |
| 144 | }; | 175 | }; |
| 145 | 176 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 39b0c0eaa37d..5d8eb58ba5e3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | |||
| @@ -32,51 +32,53 @@ | |||
| 32 | */ | 32 | */ |
| 33 | 33 | ||
| 34 | static struct omap_hwmod omap3xxx_mpu_hwmod; | 34 | static struct omap_hwmod omap3xxx_mpu_hwmod; |
| 35 | static struct omap_hwmod omap3xxx_l3_hwmod; | 35 | static struct omap_hwmod omap3xxx_iva_hwmod; |
| 36 | static struct omap_hwmod omap3xxx_l3_main_hwmod; | ||
| 36 | static struct omap_hwmod omap3xxx_l4_core_hwmod; | 37 | static struct omap_hwmod omap3xxx_l4_core_hwmod; |
| 37 | static struct omap_hwmod omap3xxx_l4_per_hwmod; | 38 | static struct omap_hwmod omap3xxx_l4_per_hwmod; |
| 38 | 39 | ||
| 39 | /* L3 -> L4_CORE interface */ | 40 | /* L3 -> L4_CORE interface */ |
| 40 | static struct omap_hwmod_ocp_if omap3xxx_l3__l4_core = { | 41 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { |
| 41 | .master = &omap3xxx_l3_hwmod, | 42 | .master = &omap3xxx_l3_main_hwmod, |
| 42 | .slave = &omap3xxx_l4_core_hwmod, | 43 | .slave = &omap3xxx_l4_core_hwmod, |
| 43 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 44 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 44 | }; | 45 | }; |
| 45 | 46 | ||
| 46 | /* L3 -> L4_PER interface */ | 47 | /* L3 -> L4_PER interface */ |
| 47 | static struct omap_hwmod_ocp_if omap3xxx_l3__l4_per = { | 48 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { |
| 48 | .master = &omap3xxx_l3_hwmod, | 49 | .master = &omap3xxx_l3_main_hwmod, |
| 49 | .slave = &omap3xxx_l4_per_hwmod, | 50 | .slave = &omap3xxx_l4_per_hwmod, |
| 50 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 51 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 51 | }; | 52 | }; |
| 52 | 53 | ||
| 53 | /* MPU -> L3 interface */ | 54 | /* MPU -> L3 interface */ |
| 54 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3 = { | 55 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { |
| 55 | .master = &omap3xxx_mpu_hwmod, | 56 | .master = &omap3xxx_mpu_hwmod, |
| 56 | .slave = &omap3xxx_l3_hwmod, | 57 | .slave = &omap3xxx_l3_main_hwmod, |
| 57 | .user = OCP_USER_MPU, | 58 | .user = OCP_USER_MPU, |
| 58 | }; | 59 | }; |
| 59 | 60 | ||
| 60 | /* Slave interfaces on the L3 interconnect */ | 61 | /* Slave interfaces on the L3 interconnect */ |
| 61 | static struct omap_hwmod_ocp_if *omap3xxx_l3_slaves[] = { | 62 | static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = { |
| 62 | &omap3xxx_mpu__l3, | 63 | &omap3xxx_mpu__l3_main, |
| 63 | }; | 64 | }; |
| 64 | 65 | ||
| 65 | /* Master interfaces on the L3 interconnect */ | 66 | /* Master interfaces on the L3 interconnect */ |
| 66 | static struct omap_hwmod_ocp_if *omap3xxx_l3_masters[] = { | 67 | static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { |
| 67 | &omap3xxx_l3__l4_core, | 68 | &omap3xxx_l3_main__l4_core, |
| 68 | &omap3xxx_l3__l4_per, | 69 | &omap3xxx_l3_main__l4_per, |
| 69 | }; | 70 | }; |
| 70 | 71 | ||
| 71 | /* L3 */ | 72 | /* L3 */ |
| 72 | static struct omap_hwmod omap3xxx_l3_hwmod = { | 73 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
| 73 | .name = "l3_hwmod", | 74 | .name = "l3_main", |
| 74 | .class = &l3_hwmod_class, | 75 | .class = &l3_hwmod_class, |
| 75 | .masters = omap3xxx_l3_masters, | 76 | .masters = omap3xxx_l3_main_masters, |
| 76 | .masters_cnt = ARRAY_SIZE(omap3xxx_l3_masters), | 77 | .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), |
| 77 | .slaves = omap3xxx_l3_slaves, | 78 | .slaves = omap3xxx_l3_main_slaves, |
| 78 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_slaves), | 79 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves), |
| 79 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | 80 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 81 | .flags = HWMOD_NO_IDLEST, | ||
| 80 | }; | 82 | }; |
| 81 | 83 | ||
| 82 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod; | 84 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod; |
| @@ -90,7 +92,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | |||
| 90 | 92 | ||
| 91 | /* Slave interfaces on the L4_CORE interconnect */ | 93 | /* Slave interfaces on the L4_CORE interconnect */ |
| 92 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { | 94 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { |
| 93 | &omap3xxx_l3__l4_core, | 95 | &omap3xxx_l3_main__l4_core, |
| 94 | }; | 96 | }; |
| 95 | 97 | ||
| 96 | /* Master interfaces on the L4_CORE interconnect */ | 98 | /* Master interfaces on the L4_CORE interconnect */ |
| @@ -100,18 +102,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { | |||
| 100 | 102 | ||
| 101 | /* L4 CORE */ | 103 | /* L4 CORE */ |
| 102 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | 104 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { |
| 103 | .name = "l4_core_hwmod", | 105 | .name = "l4_core", |
| 104 | .class = &l4_hwmod_class, | 106 | .class = &l4_hwmod_class, |
| 105 | .masters = omap3xxx_l4_core_masters, | 107 | .masters = omap3xxx_l4_core_masters, |
| 106 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters), | 108 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters), |
| 107 | .slaves = omap3xxx_l4_core_slaves, | 109 | .slaves = omap3xxx_l4_core_slaves, |
| 108 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), | 110 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), |
| 109 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | 111 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 112 | .flags = HWMOD_NO_IDLEST, | ||
| 110 | }; | 113 | }; |
| 111 | 114 | ||
| 112 | /* Slave interfaces on the L4_PER interconnect */ | 115 | /* Slave interfaces on the L4_PER interconnect */ |
| 113 | static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { | 116 | static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { |
| 114 | &omap3xxx_l3__l4_per, | 117 | &omap3xxx_l3_main__l4_per, |
| 115 | }; | 118 | }; |
| 116 | 119 | ||
| 117 | /* Master interfaces on the L4_PER interconnect */ | 120 | /* Master interfaces on the L4_PER interconnect */ |
| @@ -120,13 +123,14 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = { | |||
| 120 | 123 | ||
| 121 | /* L4 PER */ | 124 | /* L4 PER */ |
| 122 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | 125 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { |
| 123 | .name = "l4_per_hwmod", | 126 | .name = "l4_per", |
| 124 | .class = &l4_hwmod_class, | 127 | .class = &l4_hwmod_class, |
| 125 | .masters = omap3xxx_l4_per_masters, | 128 | .masters = omap3xxx_l4_per_masters, |
| 126 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters), | 129 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters), |
| 127 | .slaves = omap3xxx_l4_per_slaves, | 130 | .slaves = omap3xxx_l4_per_slaves, |
| 128 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), | 131 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), |
| 129 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | 132 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 133 | .flags = HWMOD_NO_IDLEST, | ||
| 130 | }; | 134 | }; |
| 131 | 135 | ||
| 132 | /* Slave interfaces on the L4_WKUP interconnect */ | 136 | /* Slave interfaces on the L4_WKUP interconnect */ |
| @@ -140,18 +144,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = { | |||
| 140 | 144 | ||
| 141 | /* L4 WKUP */ | 145 | /* L4 WKUP */ |
| 142 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | 146 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { |
| 143 | .name = "l4_wkup_hwmod", | 147 | .name = "l4_wkup", |
| 144 | .class = &l4_hwmod_class, | 148 | .class = &l4_hwmod_class, |
| 145 | .masters = omap3xxx_l4_wkup_masters, | 149 | .masters = omap3xxx_l4_wkup_masters, |
| 146 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters), | 150 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters), |
| 147 | .slaves = omap3xxx_l4_wkup_slaves, | 151 | .slaves = omap3xxx_l4_wkup_slaves, |
| 148 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), | 152 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), |
| 149 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | 153 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 154 | .flags = HWMOD_NO_IDLEST, | ||
| 150 | }; | 155 | }; |
| 151 | 156 | ||
| 152 | /* Master interfaces on the MPU device */ | 157 | /* Master interfaces on the MPU device */ |
| 153 | static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { | 158 | static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { |
| 154 | &omap3xxx_mpu__l3, | 159 | &omap3xxx_mpu__l3_main, |
| 155 | }; | 160 | }; |
| 156 | 161 | ||
| 157 | /* MPU */ | 162 | /* MPU */ |
| @@ -164,12 +169,41 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = { | |||
| 164 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 169 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 165 | }; | 170 | }; |
| 166 | 171 | ||
| 172 | /* | ||
| 173 | * IVA2_2 interface data | ||
| 174 | */ | ||
| 175 | |||
| 176 | /* IVA2 <- L3 interface */ | ||
| 177 | static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { | ||
| 178 | .master = &omap3xxx_l3_main_hwmod, | ||
| 179 | .slave = &omap3xxx_iva_hwmod, | ||
| 180 | .clk = "iva2_ck", | ||
| 181 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 182 | }; | ||
| 183 | |||
| 184 | static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = { | ||
| 185 | &omap3xxx_l3__iva, | ||
| 186 | }; | ||
| 187 | |||
| 188 | /* | ||
| 189 | * IVA2 (IVA2) | ||
| 190 | */ | ||
| 191 | |||
| 192 | static struct omap_hwmod omap3xxx_iva_hwmod = { | ||
| 193 | .name = "iva", | ||
| 194 | .class = &iva_hwmod_class, | ||
| 195 | .masters = omap3xxx_iva_masters, | ||
| 196 | .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), | ||
| 197 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
| 198 | }; | ||
| 199 | |||
| 167 | static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { | 200 | static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { |
| 168 | &omap3xxx_l3_hwmod, | 201 | &omap3xxx_l3_main_hwmod, |
| 169 | &omap3xxx_l4_core_hwmod, | 202 | &omap3xxx_l4_core_hwmod, |
| 170 | &omap3xxx_l4_per_hwmod, | 203 | &omap3xxx_l4_per_hwmod, |
| 171 | &omap3xxx_l4_wkup_hwmod, | 204 | &omap3xxx_l4_wkup_hwmod, |
| 172 | &omap3xxx_mpu_hwmod, | 205 | &omap3xxx_mpu_hwmod, |
| 206 | &omap3xxx_iva_hwmod, | ||
| 173 | NULL, | 207 | NULL, |
| 174 | }; | 208 | }; |
| 175 | 209 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c index 1e80b914fa1a..08a134243ecb 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c | |||
| @@ -66,3 +66,6 @@ struct omap_hwmod_class mpu_hwmod_class = { | |||
| 66 | .name = "mpu" | 66 | .name = "mpu" |
| 67 | }; | 67 | }; |
| 68 | 68 | ||
| 69 | struct omap_hwmod_class iva_hwmod_class = { | ||
| 70 | .name = "iva" | ||
| 71 | }; | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index 3645a28c7c27..c34e98bf1242 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h | |||
| @@ -20,5 +20,6 @@ | |||
| 20 | extern struct omap_hwmod_class l3_hwmod_class; | 20 | extern struct omap_hwmod_class l3_hwmod_class; |
| 21 | extern struct omap_hwmod_class l4_hwmod_class; | 21 | extern struct omap_hwmod_class l4_hwmod_class; |
| 22 | extern struct omap_hwmod_class mpu_hwmod_class; | 22 | extern struct omap_hwmod_class mpu_hwmod_class; |
| 23 | extern struct omap_hwmod_class iva_hwmod_class; | ||
| 23 | 24 | ||
| 24 | #endif | 25 | #endif |
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c new file mode 100644 index 000000000000..68f9f2e95891 --- /dev/null +++ b/arch/arm/mach-omap2/pm.c | |||
| @@ -0,0 +1,84 @@ | |||
| 1 | /* | ||
| 2 | * pm.c - Common OMAP2+ power management-related code | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <linux/err.h> | ||
| 16 | |||
| 17 | #include <plat/omap-pm.h> | ||
| 18 | #include <plat/omap_device.h> | ||
| 19 | #include <plat/common.h> | ||
| 20 | |||
| 21 | static struct omap_device_pm_latency *pm_lats; | ||
| 22 | |||
| 23 | static struct device *mpu_dev; | ||
| 24 | static struct device *dsp_dev; | ||
| 25 | static struct device *l3_dev; | ||
| 26 | |||
| 27 | struct device *omap2_get_mpuss_device(void) | ||
| 28 | { | ||
| 29 | WARN_ON_ONCE(!mpu_dev); | ||
| 30 | return mpu_dev; | ||
| 31 | } | ||
| 32 | |||
| 33 | struct device *omap2_get_dsp_device(void) | ||
| 34 | { | ||
| 35 | WARN_ON_ONCE(!dsp_dev); | ||
| 36 | return dsp_dev; | ||
| 37 | } | ||
| 38 | |||
| 39 | struct device *omap2_get_l3_device(void) | ||
| 40 | { | ||
| 41 | WARN_ON_ONCE(!l3_dev); | ||
| 42 | return l3_dev; | ||
| 43 | } | ||
| 44 | |||
| 45 | /* static int _init_omap_device(struct omap_hwmod *oh, void *user) */ | ||
| 46 | static int _init_omap_device(char *name, struct device **new_dev) | ||
| 47 | { | ||
| 48 | struct omap_hwmod *oh; | ||
| 49 | struct omap_device *od; | ||
| 50 | |||
| 51 | oh = omap_hwmod_lookup(name); | ||
| 52 | if (WARN(!oh, "%s: could not find omap_hwmod for %s\n", | ||
| 53 | __func__, name)) | ||
| 54 | return -ENODEV; | ||
| 55 | |||
| 56 | od = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false); | ||
| 57 | if (WARN(IS_ERR(od), "%s: could not build omap_device for %s\n", | ||
| 58 | __func__, name)) | ||
| 59 | return -ENODEV; | ||
| 60 | |||
| 61 | *new_dev = &od->pdev.dev; | ||
| 62 | |||
| 63 | return 0; | ||
| 64 | } | ||
| 65 | |||
| 66 | /* | ||
| 67 | * Build omap_devices for processors and bus. | ||
| 68 | */ | ||
| 69 | static void omap2_init_processor_devices(void) | ||
| 70 | { | ||
| 71 | _init_omap_device("mpu", &mpu_dev); | ||
| 72 | _init_omap_device("iva", &dsp_dev); | ||
| 73 | _init_omap_device("l3_main", &l3_dev); | ||
| 74 | } | ||
| 75 | |||
| 76 | static int __init omap2_common_pm_init(void) | ||
| 77 | { | ||
| 78 | omap2_init_processor_devices(); | ||
| 79 | omap_pm_if_init(); | ||
| 80 | |||
| 81 | return 0; | ||
| 82 | } | ||
| 83 | device_initcall(omap2_common_pm_init); | ||
| 84 | |||
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index e321281ab6e1..6aeedeacdad8 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c | |||
| @@ -39,7 +39,6 @@ | |||
| 39 | #include <plat/clock.h> | 39 | #include <plat/clock.h> |
| 40 | #include <plat/sram.h> | 40 | #include <plat/sram.h> |
| 41 | #include <plat/control.h> | 41 | #include <plat/control.h> |
| 42 | #include <plat/mux.h> | ||
| 43 | #include <plat/dma.h> | 42 | #include <plat/dma.h> |
| 44 | #include <plat/board.h> | 43 | #include <plat/board.h> |
| 45 | 44 | ||
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index b88737fd6cfe..fb4994ad622e 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
| @@ -385,8 +385,9 @@ void omap_sram_idle(void) | |||
| 385 | /* Enable IO-PAD and IO-CHAIN wakeups */ | 385 | /* Enable IO-PAD and IO-CHAIN wakeups */ |
| 386 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); | 386 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); |
| 387 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); | 387 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
| 388 | if (per_next_state < PWRDM_POWER_ON || | 388 | if (omap3_has_io_wakeup() && \ |
| 389 | core_next_state < PWRDM_POWER_ON) { | 389 | (per_next_state < PWRDM_POWER_ON || |
| 390 | core_next_state < PWRDM_POWER_ON)) { | ||
| 390 | prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); | 391 | prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); |
| 391 | omap3_enable_io_chain(); | 392 | omap3_enable_io_chain(); |
| 392 | } | 393 | } |
| @@ -479,7 +480,7 @@ void omap_sram_idle(void) | |||
| 479 | } | 480 | } |
| 480 | 481 | ||
| 481 | /* Disable IO-PAD and IO-CHAIN wakeup */ | 482 | /* Disable IO-PAD and IO-CHAIN wakeup */ |
| 482 | if (core_next_state < PWRDM_POWER_ON) { | 483 | if (omap3_has_io_wakeup() && core_next_state < PWRDM_POWER_ON) { |
| 483 | prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); | 484 | prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); |
| 484 | omap3_disable_io_chain(); | 485 | omap3_disable_io_chain(); |
| 485 | } | 486 | } |
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c new file mode 100644 index 000000000000..54544b4fc76b --- /dev/null +++ b/arch/arm/mach-omap2/pm44xx.c | |||
| @@ -0,0 +1,135 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 Power Management Routines | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 5 | * Rajendra Nayak <rnayak@ti.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/pm.h> | ||
| 13 | #include <linux/suspend.h> | ||
| 14 | #include <linux/module.h> | ||
| 15 | #include <linux/list.h> | ||
| 16 | #include <linux/err.h> | ||
| 17 | #include <linux/slab.h> | ||
| 18 | |||
| 19 | #include <plat/powerdomain.h> | ||
| 20 | #include <mach/omap4-common.h> | ||
| 21 | |||
| 22 | struct power_state { | ||
| 23 | struct powerdomain *pwrdm; | ||
| 24 | u32 next_state; | ||
| 25 | #ifdef CONFIG_SUSPEND | ||
| 26 | u32 saved_state; | ||
| 27 | #endif | ||
| 28 | struct list_head node; | ||
| 29 | }; | ||
| 30 | |||
| 31 | static LIST_HEAD(pwrst_list); | ||
| 32 | |||
| 33 | #ifdef CONFIG_SUSPEND | ||
| 34 | static int omap4_pm_prepare(void) | ||
| 35 | { | ||
| 36 | disable_hlt(); | ||
| 37 | return 0; | ||
| 38 | } | ||
| 39 | |||
| 40 | static int omap4_pm_suspend(void) | ||
| 41 | { | ||
| 42 | do_wfi(); | ||
| 43 | return 0; | ||
| 44 | } | ||
| 45 | |||
| 46 | static int omap4_pm_enter(suspend_state_t suspend_state) | ||
| 47 | { | ||
| 48 | int ret = 0; | ||
| 49 | |||
| 50 | switch (suspend_state) { | ||
| 51 | case PM_SUSPEND_STANDBY: | ||
| 52 | case PM_SUSPEND_MEM: | ||
| 53 | ret = omap4_pm_suspend(); | ||
| 54 | break; | ||
| 55 | default: | ||
| 56 | ret = -EINVAL; | ||
| 57 | } | ||
| 58 | |||
| 59 | return ret; | ||
| 60 | } | ||
| 61 | |||
| 62 | static void omap4_pm_finish(void) | ||
| 63 | { | ||
| 64 | enable_hlt(); | ||
| 65 | return; | ||
| 66 | } | ||
| 67 | |||
| 68 | static int omap4_pm_begin(suspend_state_t state) | ||
| 69 | { | ||
| 70 | return 0; | ||
| 71 | } | ||
| 72 | |||
| 73 | static void omap4_pm_end(void) | ||
| 74 | { | ||
| 75 | return; | ||
| 76 | } | ||
| 77 | |||
| 78 | static struct platform_suspend_ops omap_pm_ops = { | ||
| 79 | .begin = omap4_pm_begin, | ||
| 80 | .end = omap4_pm_end, | ||
| 81 | .prepare = omap4_pm_prepare, | ||
| 82 | .enter = omap4_pm_enter, | ||
| 83 | .finish = omap4_pm_finish, | ||
| 84 | .valid = suspend_valid_only_mem, | ||
| 85 | }; | ||
| 86 | #endif /* CONFIG_SUSPEND */ | ||
| 87 | |||
| 88 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) | ||
| 89 | { | ||
| 90 | struct power_state *pwrst; | ||
| 91 | |||
| 92 | if (!pwrdm->pwrsts) | ||
| 93 | return 0; | ||
| 94 | |||
| 95 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); | ||
| 96 | if (!pwrst) | ||
| 97 | return -ENOMEM; | ||
| 98 | pwrst->pwrdm = pwrdm; | ||
| 99 | pwrst->next_state = PWRDM_POWER_ON; | ||
| 100 | list_add(&pwrst->node, &pwrst_list); | ||
| 101 | |||
| 102 | return pwrdm_set_next_pwrst(pwrst->pwrdm, pwrst->next_state); | ||
| 103 | } | ||
| 104 | |||
| 105 | /** | ||
| 106 | * omap4_pm_init - Init routine for OMAP4 PM | ||
| 107 | * | ||
| 108 | * Initializes all powerdomain and clockdomain target states | ||
| 109 | * and all PRCM settings. | ||
| 110 | */ | ||
| 111 | static int __init omap4_pm_init(void) | ||
| 112 | { | ||
| 113 | int ret; | ||
| 114 | |||
| 115 | if (!cpu_is_omap44xx()) | ||
| 116 | return -ENODEV; | ||
| 117 | |||
| 118 | pr_err("Power Management for TI OMAP4.\n"); | ||
| 119 | |||
| 120 | #ifdef CONFIG_PM | ||
| 121 | ret = pwrdm_for_each(pwrdms_setup, NULL); | ||
| 122 | if (ret) { | ||
| 123 | pr_err("Failed to setup powerdomains\n"); | ||
| 124 | goto err2; | ||
| 125 | } | ||
| 126 | #endif | ||
| 127 | |||
| 128 | #ifdef CONFIG_SUSPEND | ||
| 129 | suspend_set_ops(&omap_pm_ops); | ||
| 130 | #endif /* CONFIG_SUSPEND */ | ||
| 131 | |||
| 132 | err2: | ||
| 133 | return ret; | ||
| 134 | } | ||
| 135 | late_initcall(omap4_pm_init); | ||
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index a2904aa7065e..6527ec30dc17 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c | |||
| @@ -875,6 +875,7 @@ int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) | |||
| 875 | break; | 875 | break; |
| 876 | case 4: | 876 | case 4: |
| 877 | m = OMAP_MEM4_RETSTATE_MASK; | 877 | m = OMAP_MEM4_RETSTATE_MASK; |
| 878 | break; | ||
| 878 | default: | 879 | default: |
| 879 | WARN_ON(1); /* should never happen */ | 880 | WARN_ON(1); /* should never happen */ |
| 880 | return -EEXIST; | 881 | return -EEXIST; |
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index bd87112beea8..fa904861668b 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h | |||
| @@ -75,12 +75,19 @@ static struct powerdomain mpu_3xxx_pwrdm = { | |||
| 75 | }, | 75 | }, |
| 76 | }; | 76 | }; |
| 77 | 77 | ||
| 78 | /* | ||
| 79 | * The USBTLL Save-and-Restore mechanism is broken on | ||
| 80 | * 3430s upto ES3.0 and 3630ES1.0. Hence this feature | ||
| 81 | * needs to be disabled on these chips. | ||
| 82 | * Refer: 3430 errata ID i459 and 3630 errata ID i579 | ||
| 83 | */ | ||
| 78 | static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { | 84 | static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { |
| 79 | .name = "core_pwrdm", | 85 | .name = "core_pwrdm", |
| 80 | .prcm_offs = CORE_MOD, | 86 | .prcm_offs = CORE_MOD, |
| 81 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | | 87 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | |
| 82 | CHIP_IS_OMAP3430ES2 | | 88 | CHIP_IS_OMAP3430ES2 | |
| 83 | CHIP_IS_OMAP3430ES3_0), | 89 | CHIP_IS_OMAP3430ES3_0 | |
| 90 | CHIP_IS_OMAP3630ES1), | ||
| 84 | .pwrsts = PWRSTS_OFF_RET_ON, | 91 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 85 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 92 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 86 | .banks = 2, | 93 | .banks = 2, |
| @@ -97,7 +104,8 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { | |||
| 97 | static struct powerdomain core_3xxx_es3_1_pwrdm = { | 104 | static struct powerdomain core_3xxx_es3_1_pwrdm = { |
| 98 | .name = "core_pwrdm", | 105 | .name = "core_pwrdm", |
| 99 | .prcm_offs = CORE_MOD, | 106 | .prcm_offs = CORE_MOD, |
| 100 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), | 107 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 | |
| 108 | CHIP_GE_OMAP3630ES1_1), | ||
| 101 | .pwrsts = PWRSTS_OFF_RET_ON, | 109 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 102 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 110 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 103 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ | 111 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ |
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 3771254dfa81..566e991ede81 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c | |||
| @@ -37,6 +37,9 @@ | |||
| 37 | #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 | 37 | #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 |
| 38 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ | 38 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ |
| 39 | 39 | ||
| 40 | #define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0) | ||
| 41 | #define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1) | ||
| 42 | |||
| 40 | /* | 43 | /* |
| 41 | * NOTE: By default the serial timeout is disabled as it causes lost characters | 44 | * NOTE: By default the serial timeout is disabled as it causes lost characters |
| 42 | * over the serial ports. This means that the UART clocks will stay on until | 45 | * over the serial ports. This means that the UART clocks will stay on until |
| @@ -64,6 +67,7 @@ struct omap_uart_state { | |||
| 64 | struct list_head node; | 67 | struct list_head node; |
| 65 | struct platform_device pdev; | 68 | struct platform_device pdev; |
| 66 | 69 | ||
| 70 | u32 errata; | ||
| 67 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) | 71 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
| 68 | int context_valid; | 72 | int context_valid; |
| 69 | 73 | ||
| @@ -74,6 +78,7 @@ struct omap_uart_state { | |||
| 74 | u16 sysc; | 78 | u16 sysc; |
| 75 | u16 scr; | 79 | u16 scr; |
| 76 | u16 wer; | 80 | u16 wer; |
| 81 | u16 mcr; | ||
| 77 | #endif | 82 | #endif |
| 78 | }; | 83 | }; |
| 79 | 84 | ||
| @@ -180,6 +185,42 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart) | |||
| 180 | 185 | ||
| 181 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) | 186 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) |
| 182 | 187 | ||
| 188 | /* | ||
| 189 | * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6) | ||
| 190 | * The access to uart register after MDR1 Access | ||
| 191 | * causes UART to corrupt data. | ||
| 192 | * | ||
| 193 | * Need a delay = | ||
| 194 | * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) | ||
| 195 | * give 10 times as much | ||
| 196 | */ | ||
| 197 | static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, | ||
| 198 | u8 fcr_val) | ||
| 199 | { | ||
| 200 | struct plat_serial8250_port *p = uart->p; | ||
| 201 | u8 timeout = 255; | ||
| 202 | |||
| 203 | serial_write_reg(p, UART_OMAP_MDR1, mdr1_val); | ||
| 204 | udelay(2); | ||
| 205 | serial_write_reg(p, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | | ||
| 206 | UART_FCR_CLEAR_RCVR); | ||
| 207 | /* | ||
| 208 | * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and | ||
| 209 | * TX_FIFO_E bit is 1. | ||
| 210 | */ | ||
| 211 | while (UART_LSR_THRE != (serial_read_reg(p, UART_LSR) & | ||
| 212 | (UART_LSR_THRE | UART_LSR_DR))) { | ||
| 213 | timeout--; | ||
| 214 | if (!timeout) { | ||
| 215 | /* Should *never* happen. we warn and carry on */ | ||
| 216 | dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n", | ||
| 217 | serial_read_reg(p, UART_LSR)); | ||
| 218 | break; | ||
| 219 | } | ||
| 220 | udelay(1); | ||
| 221 | } | ||
| 222 | } | ||
| 223 | |||
| 183 | static void omap_uart_save_context(struct omap_uart_state *uart) | 224 | static void omap_uart_save_context(struct omap_uart_state *uart) |
| 184 | { | 225 | { |
| 185 | u16 lcr = 0; | 226 | u16 lcr = 0; |
| @@ -197,6 +238,9 @@ static void omap_uart_save_context(struct omap_uart_state *uart) | |||
| 197 | uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); | 238 | uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); |
| 198 | uart->scr = serial_read_reg(p, UART_OMAP_SCR); | 239 | uart->scr = serial_read_reg(p, UART_OMAP_SCR); |
| 199 | uart->wer = serial_read_reg(p, UART_OMAP_WER); | 240 | uart->wer = serial_read_reg(p, UART_OMAP_WER); |
| 241 | serial_write_reg(p, UART_LCR, 0x80); | ||
| 242 | uart->mcr = serial_read_reg(p, UART_MCR); | ||
| 243 | serial_write_reg(p, UART_LCR, lcr); | ||
| 200 | 244 | ||
| 201 | uart->context_valid = 1; | 245 | uart->context_valid = 1; |
| 202 | } | 246 | } |
| @@ -214,7 +258,10 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) | |||
| 214 | 258 | ||
| 215 | uart->context_valid = 0; | 259 | uart->context_valid = 0; |
| 216 | 260 | ||
| 217 | serial_write_reg(p, UART_OMAP_MDR1, 0x7); | 261 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) |
| 262 | omap_uart_mdr1_errataset(uart, 0x07, 0xA0); | ||
| 263 | else | ||
| 264 | serial_write_reg(p, UART_OMAP_MDR1, 0x7); | ||
| 218 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ | 265 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ |
| 219 | efr = serial_read_reg(p, UART_EFR); | 266 | efr = serial_read_reg(p, UART_EFR); |
| 220 | serial_write_reg(p, UART_EFR, UART_EFR_ECB); | 267 | serial_write_reg(p, UART_EFR, UART_EFR_ECB); |
| @@ -225,14 +272,18 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) | |||
| 225 | serial_write_reg(p, UART_DLM, uart->dlh); | 272 | serial_write_reg(p, UART_DLM, uart->dlh); |
| 226 | serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ | 273 | serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ |
| 227 | serial_write_reg(p, UART_IER, uart->ier); | 274 | serial_write_reg(p, UART_IER, uart->ier); |
| 228 | serial_write_reg(p, UART_FCR, 0xA1); | 275 | serial_write_reg(p, UART_LCR, 0x80); |
| 276 | serial_write_reg(p, UART_MCR, uart->mcr); | ||
| 229 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ | 277 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ |
| 230 | serial_write_reg(p, UART_EFR, efr); | 278 | serial_write_reg(p, UART_EFR, efr); |
| 231 | serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); | 279 | serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); |
| 232 | serial_write_reg(p, UART_OMAP_SCR, uart->scr); | 280 | serial_write_reg(p, UART_OMAP_SCR, uart->scr); |
| 233 | serial_write_reg(p, UART_OMAP_WER, uart->wer); | 281 | serial_write_reg(p, UART_OMAP_WER, uart->wer); |
| 234 | serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); | 282 | serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); |
| 235 | serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ | 283 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) |
| 284 | omap_uart_mdr1_errataset(uart, 0x00, 0xA1); | ||
| 285 | else | ||
| 286 | serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ | ||
| 236 | } | 287 | } |
| 237 | #else | 288 | #else |
| 238 | static inline void omap_uart_save_context(struct omap_uart_state *uart) {} | 289 | static inline void omap_uart_save_context(struct omap_uart_state *uart) {} |
| @@ -489,8 +540,8 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) | |||
| 489 | } | 540 | } |
| 490 | uart->wk_mask = wk_mask; | 541 | uart->wk_mask = wk_mask; |
| 491 | } else { | 542 | } else { |
| 492 | uart->wk_en = 0; | 543 | uart->wk_en = NULL; |
| 493 | uart->wk_st = 0; | 544 | uart->wk_st = NULL; |
| 494 | uart->wk_mask = 0; | 545 | uart->wk_mask = 0; |
| 495 | uart->padconf = 0; | 546 | uart->padconf = 0; |
| 496 | } | 547 | } |
| @@ -552,7 +603,8 @@ static ssize_t sleep_timeout_store(struct device *dev, | |||
| 552 | return n; | 603 | return n; |
| 553 | } | 604 | } |
| 554 | 605 | ||
| 555 | DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store); | 606 | static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, |
| 607 | sleep_timeout_store); | ||
| 556 | #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) | 608 | #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) |
| 557 | #else | 609 | #else |
| 558 | static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} | 610 | static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} |
| @@ -749,14 +801,20 @@ void __init omap_serial_init_port(int port) | |||
| 749 | * omap3xxx: Never read empty UART fifo on UARTs | 801 | * omap3xxx: Never read empty UART fifo on UARTs |
| 750 | * with IP rev >=0x52 | 802 | * with IP rev >=0x52 |
| 751 | */ | 803 | */ |
| 752 | if (cpu_is_omap44xx()) { | 804 | if (cpu_is_omap44xx()) |
| 753 | uart->p->serial_in = serial_in_override; | 805 | uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; |
| 754 | uart->p->serial_out = serial_out_override; | 806 | else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) |
| 755 | } else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) | 807 | >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) |
| 756 | >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) { | 808 | uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; |
| 809 | |||
| 810 | if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) { | ||
| 757 | uart->p->serial_in = serial_in_override; | 811 | uart->p->serial_in = serial_in_override; |
| 758 | uart->p->serial_out = serial_out_override; | 812 | uart->p->serial_out = serial_out_override; |
| 759 | } | 813 | } |
| 814 | |||
| 815 | /* Enable the MDR1 errata for OMAP3 */ | ||
| 816 | if (cpu_is_omap34xx()) | ||
| 817 | uart->errata |= UART_ERRATA_i202_MDR1_ACCESS; | ||
| 760 | } | 818 | } |
| 761 | 819 | ||
| 762 | /** | 820 | /** |
diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c index d72d1ac30333..b11bf385d360 100644 --- a/arch/arm/mach-omap2/usb-ehci.c +++ b/arch/arm/mach-omap2/usb-ehci.c | |||
| @@ -23,7 +23,6 @@ | |||
| 23 | #include <linux/dma-mapping.h> | 23 | #include <linux/dma-mapping.h> |
| 24 | 24 | ||
| 25 | #include <asm/io.h> | 25 | #include <asm/io.h> |
| 26 | #include <plat/mux.h> | ||
| 27 | 26 | ||
| 28 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 29 | #include <mach/irqs.h> | 28 | #include <mach/irqs.h> |
diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c new file mode 100644 index 000000000000..a216d88b04b5 --- /dev/null +++ b/arch/arm/mach-omap2/usb-fs.c | |||
| @@ -0,0 +1,359 @@ | |||
| 1 | /* | ||
| 2 | * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/module.h> | ||
| 22 | #include <linux/kernel.h> | ||
| 23 | #include <linux/types.h> | ||
| 24 | #include <linux/errno.h> | ||
| 25 | #include <linux/init.h> | ||
| 26 | #include <linux/platform_device.h> | ||
| 27 | #include <linux/clk.h> | ||
| 28 | #include <linux/err.h> | ||
| 29 | |||
| 30 | #include <asm/irq.h> | ||
| 31 | |||
| 32 | #include <plat/control.h> | ||
| 33 | #include <plat/usb.h> | ||
| 34 | #include <plat/board.h> | ||
| 35 | |||
| 36 | #define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN | ||
| 37 | #define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO | ||
| 38 | #define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO | ||
| 39 | #define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN | ||
| 40 | #define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG | ||
| 41 | |||
| 42 | #include "mux.h" | ||
| 43 | |||
| 44 | #if defined(CONFIG_ARCH_OMAP2) | ||
| 45 | |||
| 46 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 47 | |||
| 48 | static struct resource udc_resources[] = { | ||
| 49 | /* order is significant! */ | ||
| 50 | { /* registers */ | ||
| 51 | .start = UDC_BASE, | ||
| 52 | .end = UDC_BASE + 0xff, | ||
| 53 | .flags = IORESOURCE_MEM, | ||
| 54 | }, { /* general IRQ */ | ||
| 55 | .start = INT_USB_IRQ_GEN, | ||
| 56 | .flags = IORESOURCE_IRQ, | ||
| 57 | }, { /* PIO IRQ */ | ||
| 58 | .start = INT_USB_IRQ_NISO, | ||
| 59 | .flags = IORESOURCE_IRQ, | ||
| 60 | }, { /* SOF IRQ */ | ||
| 61 | .start = INT_USB_IRQ_ISO, | ||
| 62 | .flags = IORESOURCE_IRQ, | ||
| 63 | }, | ||
| 64 | }; | ||
| 65 | |||
| 66 | static u64 udc_dmamask = ~(u32)0; | ||
| 67 | |||
| 68 | static struct platform_device udc_device = { | ||
| 69 | .name = "omap_udc", | ||
| 70 | .id = -1, | ||
| 71 | .dev = { | ||
| 72 | .dma_mask = &udc_dmamask, | ||
| 73 | .coherent_dma_mask = 0xffffffff, | ||
| 74 | }, | ||
| 75 | .num_resources = ARRAY_SIZE(udc_resources), | ||
| 76 | .resource = udc_resources, | ||
| 77 | }; | ||
| 78 | |||
| 79 | static inline void udc_device_init(struct omap_usb_config *pdata) | ||
| 80 | { | ||
| 81 | pdata->udc_device = &udc_device; | ||
| 82 | } | ||
| 83 | |||
| 84 | #else | ||
| 85 | |||
| 86 | static inline void udc_device_init(struct omap_usb_config *pdata) | ||
| 87 | { | ||
| 88 | } | ||
| 89 | |||
| 90 | #endif | ||
| 91 | |||
| 92 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 93 | |||
| 94 | /* The dmamask must be set for OHCI to work */ | ||
| 95 | static u64 ohci_dmamask = ~(u32)0; | ||
| 96 | |||
| 97 | static struct resource ohci_resources[] = { | ||
| 98 | { | ||
| 99 | .start = OMAP_OHCI_BASE, | ||
| 100 | .end = OMAP_OHCI_BASE + 0xff, | ||
| 101 | .flags = IORESOURCE_MEM, | ||
| 102 | }, | ||
| 103 | { | ||
| 104 | .start = INT_USB_IRQ_HGEN, | ||
| 105 | .flags = IORESOURCE_IRQ, | ||
| 106 | }, | ||
| 107 | }; | ||
| 108 | |||
| 109 | static struct platform_device ohci_device = { | ||
| 110 | .name = "ohci", | ||
| 111 | .id = -1, | ||
| 112 | .dev = { | ||
| 113 | .dma_mask = &ohci_dmamask, | ||
| 114 | .coherent_dma_mask = 0xffffffff, | ||
| 115 | }, | ||
| 116 | .num_resources = ARRAY_SIZE(ohci_resources), | ||
| 117 | .resource = ohci_resources, | ||
| 118 | }; | ||
| 119 | |||
| 120 | static inline void ohci_device_init(struct omap_usb_config *pdata) | ||
| 121 | { | ||
| 122 | pdata->ohci_device = &ohci_device; | ||
| 123 | } | ||
| 124 | |||
| 125 | #else | ||
| 126 | |||
| 127 | static inline void ohci_device_init(struct omap_usb_config *pdata) | ||
| 128 | { | ||
| 129 | } | ||
| 130 | |||
| 131 | #endif | ||
| 132 | |||
| 133 | #if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG) | ||
| 134 | |||
| 135 | static struct resource otg_resources[] = { | ||
| 136 | /* order is significant! */ | ||
| 137 | { | ||
| 138 | .start = OTG_BASE, | ||
| 139 | .end = OTG_BASE + 0xff, | ||
| 140 | .flags = IORESOURCE_MEM, | ||
| 141 | }, { | ||
| 142 | .start = INT_USB_IRQ_OTG, | ||
| 143 | .flags = IORESOURCE_IRQ, | ||
| 144 | }, | ||
| 145 | }; | ||
| 146 | |||
| 147 | static struct platform_device otg_device = { | ||
| 148 | .name = "omap_otg", | ||
| 149 | .id = -1, | ||
| 150 | .num_resources = ARRAY_SIZE(otg_resources), | ||
| 151 | .resource = otg_resources, | ||
| 152 | }; | ||
| 153 | |||
| 154 | static inline void otg_device_init(struct omap_usb_config *pdata) | ||
| 155 | { | ||
| 156 | pdata->otg_device = &otg_device; | ||
| 157 | } | ||
| 158 | |||
| 159 | #else | ||
| 160 | |||
| 161 | static inline void otg_device_init(struct omap_usb_config *pdata) | ||
| 162 | { | ||
| 163 | } | ||
| 164 | |||
| 165 | #endif | ||
| 166 | |||
| 167 | static void omap2_usb_devconf_clear(u8 port, u32 mask) | ||
| 168 | { | ||
| 169 | u32 r; | ||
| 170 | |||
| 171 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 172 | r &= ~USBTXWRMODEI(port, mask); | ||
| 173 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 174 | } | ||
| 175 | |||
| 176 | static void omap2_usb_devconf_set(u8 port, u32 mask) | ||
| 177 | { | ||
| 178 | u32 r; | ||
| 179 | |||
| 180 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 181 | r |= USBTXWRMODEI(port, mask); | ||
| 182 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 183 | } | ||
| 184 | |||
| 185 | static void omap2_usb2_disable_5pinbitll(void) | ||
| 186 | { | ||
| 187 | u32 r; | ||
| 188 | |||
| 189 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 190 | r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI); | ||
| 191 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 192 | } | ||
| 193 | |||
| 194 | static void omap2_usb2_enable_5pinunitll(void) | ||
| 195 | { | ||
| 196 | u32 r; | ||
| 197 | |||
| 198 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 199 | r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI; | ||
| 200 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 201 | } | ||
| 202 | |||
| 203 | static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device) | ||
| 204 | { | ||
| 205 | u32 syscon1 = 0; | ||
| 206 | |||
| 207 | omap2_usb_devconf_clear(0, USB_BIDIR_TLL); | ||
| 208 | |||
| 209 | if (nwires == 0) | ||
| 210 | return 0; | ||
| 211 | |||
| 212 | if (is_device) | ||
| 213 | omap_mux_init_signal("usb0_puen", 0); | ||
| 214 | |||
| 215 | omap_mux_init_signal("usb0_dat", 0); | ||
| 216 | omap_mux_init_signal("usb0_txen", 0); | ||
| 217 | omap_mux_init_signal("usb0_se0", 0); | ||
| 218 | if (nwires != 3) | ||
| 219 | omap_mux_init_signal("usb0_rcv", 0); | ||
| 220 | |||
| 221 | switch (nwires) { | ||
| 222 | case 3: | ||
| 223 | syscon1 = 2; | ||
| 224 | omap2_usb_devconf_set(0, USB_BIDIR); | ||
| 225 | break; | ||
| 226 | case 4: | ||
| 227 | syscon1 = 1; | ||
| 228 | omap2_usb_devconf_set(0, USB_BIDIR); | ||
| 229 | break; | ||
| 230 | case 6: | ||
| 231 | syscon1 = 3; | ||
| 232 | omap_mux_init_signal("usb0_vp", 0); | ||
| 233 | omap_mux_init_signal("usb0_vm", 0); | ||
| 234 | omap2_usb_devconf_set(0, USB_UNIDIR); | ||
| 235 | break; | ||
| 236 | default: | ||
| 237 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | ||
| 238 | 0, nwires); | ||
| 239 | } | ||
| 240 | |||
| 241 | return syscon1 << 16; | ||
| 242 | } | ||
| 243 | |||
| 244 | static u32 __init omap2_usb1_init(unsigned nwires) | ||
| 245 | { | ||
| 246 | u32 syscon1 = 0; | ||
| 247 | |||
| 248 | omap2_usb_devconf_clear(1, USB_BIDIR_TLL); | ||
| 249 | |||
| 250 | if (nwires == 0) | ||
| 251 | return 0; | ||
| 252 | |||
| 253 | /* NOTE: board-specific code must set up pin muxing for usb1, | ||
| 254 | * since each signal could come out on either of two balls. | ||
| 255 | */ | ||
| 256 | |||
| 257 | switch (nwires) { | ||
| 258 | case 2: | ||
| 259 | /* NOTE: board-specific code must override this setting if | ||
| 260 | * this TLL link is not using DP/DM | ||
| 261 | */ | ||
| 262 | syscon1 = 1; | ||
| 263 | omap2_usb_devconf_set(1, USB_BIDIR_TLL); | ||
| 264 | break; | ||
| 265 | case 3: | ||
| 266 | syscon1 = 2; | ||
| 267 | omap2_usb_devconf_set(1, USB_BIDIR); | ||
| 268 | break; | ||
| 269 | case 4: | ||
| 270 | syscon1 = 1; | ||
| 271 | omap2_usb_devconf_set(1, USB_BIDIR); | ||
| 272 | break; | ||
| 273 | case 6: | ||
| 274 | default: | ||
| 275 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | ||
| 276 | 1, nwires); | ||
| 277 | } | ||
| 278 | |||
| 279 | return syscon1 << 20; | ||
| 280 | } | ||
| 281 | |||
| 282 | static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup) | ||
| 283 | { | ||
| 284 | u32 syscon1 = 0; | ||
| 285 | |||
| 286 | omap2_usb2_disable_5pinbitll(); | ||
| 287 | alt_pingroup = 0; | ||
| 288 | |||
| 289 | /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */ | ||
| 290 | if (alt_pingroup || nwires == 0) | ||
| 291 | return 0; | ||
| 292 | |||
| 293 | omap_mux_init_signal("usb2_dat", 0); | ||
| 294 | omap_mux_init_signal("usb2_se0", 0); | ||
| 295 | if (nwires > 2) | ||
| 296 | omap_mux_init_signal("usb2_txen", 0); | ||
| 297 | if (nwires > 3) | ||
| 298 | omap_mux_init_signal("usb2_rcv", 0); | ||
| 299 | |||
| 300 | switch (nwires) { | ||
| 301 | case 2: | ||
| 302 | /* NOTE: board-specific code must override this setting if | ||
| 303 | * this TLL link is not using DP/DM | ||
| 304 | */ | ||
| 305 | syscon1 = 1; | ||
| 306 | omap2_usb_devconf_set(2, USB_BIDIR_TLL); | ||
| 307 | break; | ||
| 308 | case 3: | ||
| 309 | syscon1 = 2; | ||
| 310 | omap2_usb_devconf_set(2, USB_BIDIR); | ||
| 311 | break; | ||
| 312 | case 4: | ||
| 313 | syscon1 = 1; | ||
| 314 | omap2_usb_devconf_set(2, USB_BIDIR); | ||
| 315 | break; | ||
| 316 | case 5: | ||
| 317 | /* NOTE: board-specific code must mux this setting depending | ||
| 318 | * on TLL link using DP/DM. Something must also | ||
| 319 | * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED} | ||
| 320 | * 2420: hdq_sio.usb2_tllse0 or vlynq_rx0.usb2_tllse0 | ||
| 321 | * 2430: hdq_sio.usb2_tllse0 or sdmmc2_dat0.usb2_tllse0 | ||
| 322 | */ | ||
| 323 | |||
| 324 | syscon1 = 3; | ||
| 325 | omap2_usb2_enable_5pinunitll(); | ||
| 326 | break; | ||
| 327 | case 6: | ||
| 328 | default: | ||
| 329 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | ||
| 330 | 2, nwires); | ||
| 331 | } | ||
| 332 | |||
| 333 | return syscon1 << 24; | ||
| 334 | } | ||
| 335 | |||
| 336 | void __init omap2_usbfs_init(struct omap_usb_config *pdata) | ||
| 337 | { | ||
| 338 | struct clk *ick; | ||
| 339 | |||
| 340 | if (!cpu_is_omap24xx()) | ||
| 341 | return; | ||
| 342 | |||
| 343 | ick = clk_get(NULL, "usb_l4_ick"); | ||
| 344 | if (IS_ERR(ick)) | ||
| 345 | return; | ||
| 346 | |||
| 347 | clk_enable(ick); | ||
| 348 | pdata->usb0_init = omap2_usb0_init; | ||
| 349 | pdata->usb1_init = omap2_usb1_init; | ||
| 350 | pdata->usb2_init = omap2_usb2_init; | ||
| 351 | udc_device_init(pdata); | ||
| 352 | ohci_device_init(pdata); | ||
| 353 | otg_device_init(pdata); | ||
| 354 | omap_otg_init(pdata); | ||
| 355 | clk_disable(ick); | ||
| 356 | clk_put(ick); | ||
| 357 | } | ||
| 358 | |||
| 359 | #endif | ||
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 96f6787e00b2..33a5cde1c227 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c | |||
| @@ -28,7 +28,6 @@ | |||
| 28 | 28 | ||
| 29 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| 30 | #include <mach/irqs.h> | 30 | #include <mach/irqs.h> |
| 31 | #include <plat/mux.h> | ||
| 32 | #include <plat/usb.h> | 31 | #include <plat/usb.h> |
| 33 | 32 | ||
| 34 | #ifdef CONFIG_USB_MUSB_SOC | 33 | #ifdef CONFIG_USB_MUSB_SOC |
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index 10a2013c1104..64a0112b70a5 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c | |||
| @@ -17,8 +17,8 @@ | |||
| 17 | #include <linux/usb/musb.h> | 17 | #include <linux/usb/musb.h> |
| 18 | 18 | ||
| 19 | #include <plat/gpmc.h> | 19 | #include <plat/gpmc.h> |
| 20 | #include <plat/mux.h> | ||
| 21 | 20 | ||
| 21 | #include "mux.h" | ||
| 22 | 22 | ||
| 23 | static u8 async_cs, sync_cs; | 23 | static u8 async_cs, sync_cs; |
| 24 | static unsigned refclk_psec; | 24 | static unsigned refclk_psec; |
| @@ -325,17 +325,17 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data, | |||
| 325 | else { | 325 | else { |
| 326 | /* assume OMAP 2420 ES2.0 and later */ | 326 | /* assume OMAP 2420 ES2.0 and later */ |
| 327 | if (dmachan & (1 << 0)) | 327 | if (dmachan & (1 << 0)) |
| 328 | omap_cfg_reg(AA10_242X_DMAREQ0); | 328 | omap_mux_init_signal("sys_ndmareq0", 0); |
| 329 | if (dmachan & (1 << 1)) | 329 | if (dmachan & (1 << 1)) |
| 330 | omap_cfg_reg(AA6_242X_DMAREQ1); | 330 | omap_mux_init_signal("sys_ndmareq1", 0); |
| 331 | if (dmachan & (1 << 2)) | 331 | if (dmachan & (1 << 2)) |
| 332 | omap_cfg_reg(E4_242X_DMAREQ2); | 332 | omap_mux_init_signal("sys_ndmareq2", 0); |
| 333 | if (dmachan & (1 << 3)) | 333 | if (dmachan & (1 << 3)) |
| 334 | omap_cfg_reg(G4_242X_DMAREQ3); | 334 | omap_mux_init_signal("sys_ndmareq3", 0); |
| 335 | if (dmachan & (1 << 4)) | 335 | if (dmachan & (1 << 4)) |
| 336 | omap_cfg_reg(D3_242X_DMAREQ4); | 336 | omap_mux_init_signal("sys_ndmareq4", 0); |
| 337 | if (dmachan & (1 << 5)) | 337 | if (dmachan & (1 << 5)) |
| 338 | omap_cfg_reg(E3_242X_DMAREQ5); | 338 | omap_mux_init_signal("sys_ndmareq5", 0); |
| 339 | } | 339 | } |
| 340 | 340 | ||
| 341 | /* so far so good ... register the device */ | 341 | /* so far so good ... register the device */ |
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 78b49a626d06..e39a417a368d 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | if ARCH_OMAP | 1 | if ARCH_OMAP |
| 2 | 2 | ||
| 3 | menu "TI OMAP Implementations" | 3 | menu "TI OMAP Common Features" |
| 4 | 4 | ||
| 5 | config ARCH_OMAP_OTG | 5 | config ARCH_OMAP_OTG |
| 6 | bool | 6 | bool |
| @@ -21,24 +21,6 @@ config ARCH_OMAP2PLUS | |||
| 21 | help | 21 | help |
| 22 | "Systems based on omap24xx, omap34xx or omap44xx" | 22 | "Systems based on omap24xx, omap34xx or omap44xx" |
| 23 | 23 | ||
| 24 | config ARCH_OMAP2 | ||
| 25 | bool "TI OMAP2" | ||
| 26 | depends on ARCH_OMAP2PLUS | ||
| 27 | select CPU_V6 | ||
| 28 | |||
| 29 | config ARCH_OMAP3 | ||
| 30 | bool "TI OMAP3" | ||
| 31 | depends on ARCH_OMAP2PLUS | ||
| 32 | select CPU_V7 | ||
| 33 | select USB_ARCH_HAS_EHCI | ||
| 34 | select ARM_L1_CACHE_SHIFT_6 | ||
| 35 | |||
| 36 | config ARCH_OMAP4 | ||
| 37 | bool "TI OMAP4" | ||
| 38 | depends on ARCH_OMAP2PLUS | ||
| 39 | select CPU_V7 | ||
| 40 | select ARM_GIC | ||
| 41 | |||
| 42 | endchoice | 24 | endchoice |
| 43 | 25 | ||
| 44 | comment "OMAP Feature Selections" | 26 | comment "OMAP Feature Selections" |
| @@ -51,7 +33,7 @@ config OMAP_DEBUG_DEVICES | |||
| 51 | config OMAP_DEBUG_LEDS | 33 | config OMAP_DEBUG_LEDS |
| 52 | bool | 34 | bool |
| 53 | depends on OMAP_DEBUG_DEVICES | 35 | depends on OMAP_DEBUG_DEVICES |
| 54 | default y if LEDS || LEDS_OMAP_DEBUG | 36 | default y if LEDS |
| 55 | 37 | ||
| 56 | config OMAP_RESET_CLOCKS | 38 | config OMAP_RESET_CLOCKS |
| 57 | bool "Reset unused clocks during boot" | 39 | bool "Reset unused clocks during boot" |
| @@ -106,6 +88,15 @@ config OMAP_MBOX_FWK | |||
| 106 | Say Y here if you want to use OMAP Mailbox framework support for | 88 | Say Y here if you want to use OMAP Mailbox framework support for |
| 107 | DSP, IVA1.0 and IVA2 in OMAP1/2/3. | 89 | DSP, IVA1.0 and IVA2 in OMAP1/2/3. |
| 108 | 90 | ||
| 91 | config OMAP_MBOX_KFIFO_SIZE | ||
| 92 | int "Mailbox kfifo default buffer size (bytes)" | ||
| 93 | depends on OMAP_MBOX_FWK | ||
| 94 | default 256 | ||
| 95 | help | ||
| 96 | Specify the default size of mailbox's kfifo buffers (bytes). | ||
| 97 | This can also be changed at runtime (via the mbox_kfifo_size | ||
| 98 | module parameter). | ||
| 99 | |||
| 109 | config OMAP_IOMMU | 100 | config OMAP_IOMMU |
| 110 | tristate | 101 | tristate |
| 111 | 102 | ||
| @@ -120,7 +111,7 @@ config OMAP_IOMMU_DEBUG | |||
| 120 | 111 | ||
| 121 | choice | 112 | choice |
| 122 | prompt "System timer" | 113 | prompt "System timer" |
| 123 | default OMAP_MPU_TIMER | 114 | default OMAP_32K_TIMER if !ARCH_OMAP15XX |
| 124 | 115 | ||
| 125 | config OMAP_MPU_TIMER | 116 | config OMAP_MPU_TIMER |
| 126 | bool "Use mpu timer" | 117 | bool "Use mpu timer" |
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 98f01910c2cf..9405831b746a 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile | |||
| @@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o | |||
| 15 | # omap_device support (OMAP2+ only at the moment) | 15 | # omap_device support (OMAP2+ only at the moment) |
| 16 | obj-$(CONFIG_ARCH_OMAP2) += omap_device.o | 16 | obj-$(CONFIG_ARCH_OMAP2) += omap_device.o |
| 17 | obj-$(CONFIG_ARCH_OMAP3) += omap_device.o | 17 | obj-$(CONFIG_ARCH_OMAP3) += omap_device.o |
| 18 | obj-$(CONFIG_ARCH_OMAP4) += omap_device.o | ||
| 18 | 19 | ||
| 19 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o | 20 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o |
| 20 | obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o | 21 | obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o |
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index ebed82699eb2..3008e7104487 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c | |||
| @@ -317,18 +317,18 @@ static struct omap_globals omap3_globals = { | |||
| 317 | .uart1_phys = OMAP3_UART1_BASE, | 317 | .uart1_phys = OMAP3_UART1_BASE, |
| 318 | .uart2_phys = OMAP3_UART2_BASE, | 318 | .uart2_phys = OMAP3_UART2_BASE, |
| 319 | .uart3_phys = OMAP3_UART3_BASE, | 319 | .uart3_phys = OMAP3_UART3_BASE, |
| 320 | .uart4_phys = OMAP3_UART4_BASE, /* Only on 3630 */ | ||
| 320 | }; | 321 | }; |
| 321 | 322 | ||
| 322 | void __init omap2_set_globals_343x(void) | 323 | void __init omap2_set_globals_3xxx(void) |
| 323 | { | 324 | { |
| 324 | __omap2_set_globals(&omap3_globals); | 325 | __omap2_set_globals(&omap3_globals); |
| 325 | } | 326 | } |
| 326 | 327 | ||
| 327 | void __init omap2_set_globals_36xx(void) | 328 | void __init omap3_map_io(void) |
| 328 | { | 329 | { |
| 329 | omap3_globals.uart4_phys = OMAP3_UART4_BASE; | 330 | omap2_set_globals_3xxx(); |
| 330 | 331 | omap34xx_map_common_io(); | |
| 331 | __omap2_set_globals(&omap3_globals); | ||
| 332 | } | 332 | } |
| 333 | #endif | 333 | #endif |
| 334 | 334 | ||
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c index 53fcef7c5201..fc05b1022602 100644 --- a/arch/arm/plat-omap/debug-leds.c +++ b/arch/arm/plat-omap/debug-leds.c | |||
| @@ -39,7 +39,7 @@ static struct h2p2_dbg_fpga __iomem *fpga; | |||
| 39 | static u16 led_state, hw_led_state; | 39 | static u16 led_state, hw_led_state; |
| 40 | 40 | ||
| 41 | 41 | ||
| 42 | #ifdef CONFIG_LEDS_OMAP_DEBUG | 42 | #ifdef CONFIG_OMAP_DEBUG_LEDS |
| 43 | #define new_led_api() 1 | 43 | #define new_led_api() 1 |
| 44 | #else | 44 | #else |
| 45 | #define new_led_api() 0 | 45 | #define new_led_api() 0 |
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 95677d17cd1c..d1920be7833b 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c | |||
| @@ -24,135 +24,13 @@ | |||
| 24 | #include <plat/control.h> | 24 | #include <plat/control.h> |
| 25 | #include <plat/board.h> | 25 | #include <plat/board.h> |
| 26 | #include <plat/mmc.h> | 26 | #include <plat/mmc.h> |
| 27 | #include <plat/mux.h> | ||
| 28 | #include <mach/gpio.h> | 27 | #include <mach/gpio.h> |
| 29 | #include <plat/menelaus.h> | 28 | #include <plat/menelaus.h> |
| 30 | #include <plat/mcbsp.h> | 29 | #include <plat/mcbsp.h> |
| 31 | #include <plat/dsp_common.h> | ||
| 32 | #include <plat/omap44xx.h> | 30 | #include <plat/omap44xx.h> |
| 33 | 31 | ||
| 34 | #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) | ||
| 35 | |||
| 36 | static struct dsp_platform_data dsp_pdata = { | ||
| 37 | .kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list), | ||
| 38 | }; | ||
| 39 | |||
| 40 | static struct resource omap_dsp_resources[] = { | ||
| 41 | { | ||
| 42 | .name = "dsp_mmu", | ||
| 43 | .start = -1, | ||
| 44 | .flags = IORESOURCE_IRQ, | ||
| 45 | }, | ||
| 46 | }; | ||
| 47 | |||
| 48 | static struct platform_device omap_dsp_device = { | ||
| 49 | .name = "dsp", | ||
| 50 | .id = -1, | ||
| 51 | .num_resources = ARRAY_SIZE(omap_dsp_resources), | ||
| 52 | .resource = omap_dsp_resources, | ||
| 53 | .dev = { | ||
| 54 | .platform_data = &dsp_pdata, | ||
| 55 | }, | ||
| 56 | }; | ||
| 57 | |||
| 58 | static inline void omap_init_dsp(void) | ||
| 59 | { | ||
| 60 | struct resource *res; | ||
| 61 | int irq; | ||
| 62 | |||
| 63 | if (cpu_is_omap15xx()) | ||
| 64 | irq = INT_1510_DSP_MMU; | ||
| 65 | else if (cpu_is_omap16xx()) | ||
| 66 | irq = INT_1610_DSP_MMU; | ||
| 67 | else if (cpu_is_omap24xx()) | ||
| 68 | irq = INT_24XX_DSP_MMU; | ||
| 69 | |||
| 70 | res = platform_get_resource_byname(&omap_dsp_device, | ||
| 71 | IORESOURCE_IRQ, "dsp_mmu"); | ||
| 72 | res->start = irq; | ||
| 73 | |||
| 74 | platform_device_register(&omap_dsp_device); | ||
| 75 | } | ||
| 76 | |||
| 77 | int dsp_kfunc_device_register(struct dsp_kfunc_device *kdev) | ||
| 78 | { | ||
| 79 | static DEFINE_MUTEX(dsp_pdata_lock); | ||
| 80 | |||
| 81 | spin_lock_init(&kdev->lock); | ||
| 82 | |||
| 83 | mutex_lock(&dsp_pdata_lock); | ||
| 84 | list_add_tail(&kdev->entry, &dsp_pdata.kdev_list); | ||
| 85 | mutex_unlock(&dsp_pdata_lock); | ||
| 86 | |||
| 87 | return 0; | ||
| 88 | } | ||
| 89 | EXPORT_SYMBOL(dsp_kfunc_device_register); | ||
| 90 | |||
| 91 | #else | ||
| 92 | static inline void omap_init_dsp(void) { } | ||
| 93 | #endif /* CONFIG_OMAP_DSP */ | ||
| 94 | |||
| 95 | /*-------------------------------------------------------------------------*/ | 32 | /*-------------------------------------------------------------------------*/ |
| 96 | #if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE) | ||
| 97 | |||
| 98 | static void omap_init_kp(void) | ||
| 99 | { | ||
| 100 | /* 2430 and 34xx keypad is on TWL4030 */ | ||
| 101 | if (cpu_is_omap2430() || cpu_is_omap34xx()) | ||
| 102 | return; | ||
| 103 | 33 | ||
| 104 | if (machine_is_omap_h2() || machine_is_omap_h3()) { | ||
| 105 | omap_cfg_reg(F18_1610_KBC0); | ||
| 106 | omap_cfg_reg(D20_1610_KBC1); | ||
| 107 | omap_cfg_reg(D19_1610_KBC2); | ||
| 108 | omap_cfg_reg(E18_1610_KBC3); | ||
| 109 | omap_cfg_reg(C21_1610_KBC4); | ||
| 110 | |||
| 111 | omap_cfg_reg(G18_1610_KBR0); | ||
| 112 | omap_cfg_reg(F19_1610_KBR1); | ||
| 113 | omap_cfg_reg(H14_1610_KBR2); | ||
| 114 | omap_cfg_reg(E20_1610_KBR3); | ||
| 115 | omap_cfg_reg(E19_1610_KBR4); | ||
| 116 | omap_cfg_reg(N19_1610_KBR5); | ||
| 117 | } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { | ||
| 118 | omap_cfg_reg(E2_7XX_KBR0); | ||
| 119 | omap_cfg_reg(J7_7XX_KBR1); | ||
| 120 | omap_cfg_reg(E1_7XX_KBR2); | ||
| 121 | omap_cfg_reg(F3_7XX_KBR3); | ||
| 122 | omap_cfg_reg(D2_7XX_KBR4); | ||
| 123 | |||
| 124 | omap_cfg_reg(C2_7XX_KBC0); | ||
| 125 | omap_cfg_reg(D3_7XX_KBC1); | ||
| 126 | omap_cfg_reg(E4_7XX_KBC2); | ||
| 127 | omap_cfg_reg(F4_7XX_KBC3); | ||
| 128 | omap_cfg_reg(E3_7XX_KBC4); | ||
| 129 | } else if (machine_is_omap_h4()) { | ||
| 130 | omap_cfg_reg(T19_24XX_KBR0); | ||
| 131 | omap_cfg_reg(R19_24XX_KBR1); | ||
| 132 | omap_cfg_reg(V18_24XX_KBR2); | ||
| 133 | omap_cfg_reg(M21_24XX_KBR3); | ||
| 134 | omap_cfg_reg(E5__24XX_KBR4); | ||
| 135 | if (omap_has_menelaus()) { | ||
| 136 | omap_cfg_reg(B3__24XX_KBR5); | ||
| 137 | omap_cfg_reg(AA4_24XX_KBC2); | ||
| 138 | omap_cfg_reg(B13_24XX_KBC6); | ||
| 139 | } else { | ||
| 140 | omap_cfg_reg(M18_24XX_KBR5); | ||
| 141 | omap_cfg_reg(H19_24XX_KBC2); | ||
| 142 | omap_cfg_reg(N19_24XX_KBC6); | ||
| 143 | } | ||
| 144 | omap_cfg_reg(R20_24XX_KBC0); | ||
| 145 | omap_cfg_reg(M14_24XX_KBC1); | ||
| 146 | omap_cfg_reg(V17_24XX_KBC3); | ||
| 147 | omap_cfg_reg(P21_24XX_KBC4); | ||
| 148 | omap_cfg_reg(L14_24XX_KBC5); | ||
| 149 | } | ||
| 150 | } | ||
| 151 | #else | ||
| 152 | static inline void omap_init_kp(void) {} | ||
| 153 | #endif | ||
| 154 | |||
| 155 | /*-------------------------------------------------------------------------*/ | ||
| 156 | #if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE) | 34 | #if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE) |
| 157 | 35 | ||
| 158 | static struct platform_device **omap_mcbsp_devices; | 36 | static struct platform_device **omap_mcbsp_devices; |
| @@ -419,8 +297,6 @@ static int __init omap_init_devices(void) | |||
| 419 | /* please keep these calls, and their implementations above, | 297 | /* please keep these calls, and their implementations above, |
| 420 | * in alphabetical order so they're easier to sort through. | 298 | * in alphabetical order so they're easier to sort through. |
| 421 | */ | 299 | */ |
| 422 | omap_init_dsp(); | ||
| 423 | omap_init_kp(); | ||
| 424 | omap_init_rng(); | 300 | omap_init_rng(); |
| 425 | omap_init_mcpdm(); | 301 | omap_init_mcpdm(); |
| 426 | omap_init_uwire(); | 302 | omap_init_uwire(); |
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index f7f571e7987e..ec7eddf9e525 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c | |||
| @@ -290,7 +290,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, | |||
| 290 | val = dma_read(CCR(lch)); | 290 | val = dma_read(CCR(lch)); |
| 291 | 291 | ||
| 292 | /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ | 292 | /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ |
| 293 | val &= ~((3 << 19) | 0x1f); | 293 | val &= ~((1 << 23) | (3 << 19) | 0x1f); |
| 294 | val |= (dma_trigger & ~0x1f) << 14; | 294 | val |= (dma_trigger & ~0x1f) << 14; |
| 295 | val |= dma_trigger & 0x1f; | 295 | val |= dma_trigger & 0x1f; |
| 296 | 296 | ||
| @@ -304,11 +304,14 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, | |||
| 304 | else | 304 | else |
| 305 | val &= ~(1 << 18); | 305 | val &= ~(1 << 18); |
| 306 | 306 | ||
| 307 | if (src_or_dst_synch) | 307 | if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) { |
| 308 | val &= ~(1 << 24); /* dest synch */ | ||
| 309 | val |= (1 << 23); /* Prefetch */ | ||
| 310 | } else if (src_or_dst_synch) { | ||
| 308 | val |= 1 << 24; /* source synch */ | 311 | val |= 1 << 24; /* source synch */ |
| 309 | else | 312 | } else { |
| 310 | val &= ~(1 << 24); /* dest synch */ | 313 | val &= ~(1 << 24); /* dest synch */ |
| 311 | 314 | } | |
| 312 | dma_write(val, CCR(lch)); | 315 | dma_write(val, CCR(lch)); |
| 313 | } | 316 | } |
| 314 | 317 | ||
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 9b7e3545f325..7951eefe1a0e 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c | |||
| @@ -390,7 +390,9 @@ static inline int gpio_valid(int gpio) | |||
| 390 | return 0; | 390 | return 0; |
| 391 | if (cpu_is_omap7xx() && gpio < 192) | 391 | if (cpu_is_omap7xx() && gpio < 192) |
| 392 | return 0; | 392 | return 0; |
| 393 | if (cpu_is_omap24xx() && gpio < 128) | 393 | if (cpu_is_omap2420() && gpio < 128) |
| 394 | return 0; | ||
| 395 | if (cpu_is_omap2430() && gpio < 160) | ||
| 394 | return 0; | 396 | return 0; |
| 395 | if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) | 397 | if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) |
| 396 | return 0; | 398 | return 0; |
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index eec2b4993c69..a5ce4f0aad35 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c | |||
| @@ -138,6 +138,16 @@ static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id) | |||
| 138 | return platform_device_register(pdev); | 138 | return platform_device_register(pdev); |
| 139 | } | 139 | } |
| 140 | 140 | ||
| 141 | /* | ||
| 142 | * XXX This function is a temporary compatibility wrapper - only | ||
| 143 | * needed until the I2C driver can be converted to call | ||
| 144 | * omap_pm_set_max_dev_wakeup_lat() and handle a return code. | ||
| 145 | */ | ||
| 146 | static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t) | ||
| 147 | { | ||
| 148 | omap_pm_set_max_mpu_wakeup_lat(dev, t); | ||
| 149 | } | ||
| 150 | |||
| 141 | static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id) | 151 | static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id) |
| 142 | { | 152 | { |
| 143 | struct resource *res; | 153 | struct resource *res; |
| @@ -168,7 +178,7 @@ static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id) | |||
| 168 | struct omap_i2c_bus_platform_data *pd; | 178 | struct omap_i2c_bus_platform_data *pd; |
| 169 | 179 | ||
| 170 | pd = pdev->dev.platform_data; | 180 | pd = pdev->dev.platform_data; |
| 171 | pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat; | 181 | pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; |
| 172 | } | 182 | } |
| 173 | 183 | ||
| 174 | return platform_device_register(pdev); | 184 | return platform_device_register(pdev); |
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h index 5cd622039da0..3cf4fa25ab3d 100644 --- a/arch/arm/plat-omap/include/plat/board.h +++ b/arch/arm/plat-omap/include/plat/board.h | |||
| @@ -85,6 +85,14 @@ struct omap_usb_config { | |||
| 85 | * 6 == 6 wire unidirectional (or TLL) | 85 | * 6 == 6 wire unidirectional (or TLL) |
| 86 | */ | 86 | */ |
| 87 | u8 pins[3]; | 87 | u8 pins[3]; |
| 88 | |||
| 89 | struct platform_device *udc_device; | ||
| 90 | struct platform_device *ohci_device; | ||
| 91 | struct platform_device *otg_device; | ||
| 92 | |||
| 93 | u32 (*usb0_init)(unsigned nwires, unsigned is_device); | ||
| 94 | u32 (*usb1_init)(unsigned nwires); | ||
| 95 | u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup); | ||
| 88 | }; | 96 | }; |
| 89 | 97 | ||
| 90 | struct omap_lcd_config { | 98 | struct omap_lcd_config { |
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index dfc472ca0cc4..fef4696dcf67 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h | |||
| @@ -19,6 +19,22 @@ struct module; | |||
| 19 | struct clk; | 19 | struct clk; |
| 20 | struct clockdomain; | 20 | struct clockdomain; |
| 21 | 21 | ||
| 22 | /** | ||
| 23 | * struct clkops - some clock function pointers | ||
| 24 | * @enable: fn ptr that enables the current clock in hardware | ||
| 25 | * @disable: fn ptr that enables the current clock in hardware | ||
| 26 | * @find_idlest: function returning the IDLEST register for the clock's IP blk | ||
| 27 | * @find_companion: function returning the "companion" clk reg for the clock | ||
| 28 | * | ||
| 29 | * A "companion" clk is an accompanying clock to the one being queried | ||
| 30 | * that must be enabled for the IP module connected to the clock to | ||
| 31 | * become accessible by the hardware. Neither @find_idlest nor | ||
| 32 | * @find_companion should be needed; that information is IP | ||
| 33 | * block-specific; the hwmod code has been created to handle this, but | ||
| 34 | * until hwmod data is ready and drivers have been converted to use PM | ||
| 35 | * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and | ||
| 36 | * @find_companion must, unfortunately, remain. | ||
| 37 | */ | ||
| 22 | struct clkops { | 38 | struct clkops { |
| 23 | int (*enable)(struct clk *); | 39 | int (*enable)(struct clk *); |
| 24 | void (*disable)(struct clk *); | 40 | void (*disable)(struct clk *); |
| @@ -30,12 +46,45 @@ struct clkops { | |||
| 30 | 46 | ||
| 31 | #ifdef CONFIG_ARCH_OMAP2PLUS | 47 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 32 | 48 | ||
| 49 | /* struct clksel_rate.flags possibilities */ | ||
| 50 | #define RATE_IN_242X (1 << 0) | ||
| 51 | #define RATE_IN_243X (1 << 1) | ||
| 52 | #define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */ | ||
| 53 | #define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */ | ||
| 54 | #define RATE_IN_36XX (1 << 4) | ||
| 55 | #define RATE_IN_4430 (1 << 5) | ||
| 56 | |||
| 57 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) | ||
| 58 | #define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX) | ||
| 59 | |||
| 60 | /** | ||
| 61 | * struct clksel_rate - register bitfield values corresponding to clk divisors | ||
| 62 | * @val: register bitfield value (shifted to bit 0) | ||
| 63 | * @div: clock divisor corresponding to @val | ||
| 64 | * @flags: (see "struct clksel_rate.flags possibilities" above) | ||
| 65 | * | ||
| 66 | * @val should match the value of a read from struct clk.clksel_reg | ||
| 67 | * AND'ed with struct clk.clksel_mask, shifted right to bit 0. | ||
| 68 | * | ||
| 69 | * @div is the divisor that should be applied to the parent clock's rate | ||
| 70 | * to produce the current clock's rate. | ||
| 71 | * | ||
| 72 | * XXX @flags probably should be replaced with an struct omap_chip. | ||
| 73 | */ | ||
| 33 | struct clksel_rate { | 74 | struct clksel_rate { |
| 34 | u32 val; | 75 | u32 val; |
| 35 | u8 div; | 76 | u8 div; |
| 36 | u8 flags; | 77 | u8 flags; |
| 37 | }; | 78 | }; |
| 38 | 79 | ||
| 80 | /** | ||
| 81 | * struct clksel - available parent clocks, and a pointer to their divisors | ||
| 82 | * @parent: struct clk * to a possible parent clock | ||
| 83 | * @rates: available divisors for this parent clock | ||
| 84 | * | ||
| 85 | * A struct clksel is always associated with one or more struct clks | ||
| 86 | * and one or more struct clksel_rates. | ||
| 87 | */ | ||
| 39 | struct clksel { | 88 | struct clksel { |
| 40 | struct clk *parent; | 89 | struct clk *parent; |
| 41 | const struct clksel_rate *rates; | 90 | const struct clksel_rate *rates; |
| @@ -116,6 +165,60 @@ struct dpll_data { | |||
| 116 | 165 | ||
| 117 | #endif | 166 | #endif |
| 118 | 167 | ||
| 168 | /* struct clk.flags possibilities */ | ||
| 169 | #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ | ||
| 170 | #define CLOCK_IDLE_CONTROL (1 << 1) | ||
| 171 | #define CLOCK_NO_IDLE_PARENT (1 << 2) | ||
| 172 | #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ | ||
| 173 | #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ | ||
| 174 | |||
| 175 | /** | ||
| 176 | * struct clk - OMAP struct clk | ||
| 177 | * @node: list_head connecting this clock into the full clock list | ||
| 178 | * @ops: struct clkops * for this clock | ||
| 179 | * @name: the name of the clock in the hardware (used in hwmod data and debug) | ||
| 180 | * @parent: pointer to this clock's parent struct clk | ||
| 181 | * @children: list_head connecting to the child clks' @sibling list_heads | ||
| 182 | * @sibling: list_head connecting this clk to its parent clk's @children | ||
| 183 | * @rate: current clock rate | ||
| 184 | * @enable_reg: register to write to enable the clock (see @enable_bit) | ||
| 185 | * @recalc: fn ptr that returns the clock's current rate | ||
| 186 | * @set_rate: fn ptr that can change the clock's current rate | ||
| 187 | * @round_rate: fn ptr that can round the clock's current rate | ||
| 188 | * @init: fn ptr to do clock-specific initialization | ||
| 189 | * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) | ||
| 190 | * @usecount: number of users that have requested this clock to be enabled | ||
| 191 | * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div | ||
| 192 | * @flags: see "struct clk.flags possibilities" above | ||
| 193 | * @clksel_reg: for clksel clks, register va containing src/divisor select | ||
| 194 | * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector | ||
| 195 | * @clksel: for clksel clks, pointer to struct clksel for this clock | ||
| 196 | * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock | ||
| 197 | * @clkdm_name: clockdomain name that this clock is contained in | ||
| 198 | * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime | ||
| 199 | * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) | ||
| 200 | * @src_offset: bitshift for source selection bitfield (OMAP1 only) | ||
| 201 | * | ||
| 202 | * XXX @rate_offset, @src_offset should probably be removed and OMAP1 | ||
| 203 | * clock code converted to use clksel. | ||
| 204 | * | ||
| 205 | * XXX @usecount is poorly named. It should be "enable_count" or | ||
| 206 | * something similar. "users" in the description refers to kernel | ||
| 207 | * code (core code or drivers) that have called clk_enable() and not | ||
| 208 | * yet called clk_disable(); the usecount of parent clocks is also | ||
| 209 | * incremented by the clock code when clk_enable() is called on child | ||
| 210 | * clocks and decremented by the clock code when clk_disable() is | ||
| 211 | * called on child clocks. | ||
| 212 | * | ||
| 213 | * XXX @clkdm, @usecount, @children, @sibling should be marked for | ||
| 214 | * internal use only. | ||
| 215 | * | ||
| 216 | * @children and @sibling are used to optimize parent-to-child clock | ||
| 217 | * tree traversals. (child-to-parent traversals use @parent.) | ||
| 218 | * | ||
| 219 | * XXX The notion of the clock's current rate probably needs to be | ||
| 220 | * separated from the clock's target rate. | ||
| 221 | */ | ||
| 119 | struct clk { | 222 | struct clk { |
| 120 | struct list_head node; | 223 | struct list_head node; |
| 121 | const struct clkops *ops; | 224 | const struct clkops *ops; |
| @@ -129,8 +232,8 @@ struct clk { | |||
| 129 | int (*set_rate)(struct clk *, unsigned long); | 232 | int (*set_rate)(struct clk *, unsigned long); |
| 130 | long (*round_rate)(struct clk *, unsigned long); | 233 | long (*round_rate)(struct clk *, unsigned long); |
| 131 | void (*init)(struct clk *); | 234 | void (*init)(struct clk *); |
| 132 | __u8 enable_bit; | 235 | u8 enable_bit; |
| 133 | __s8 usecount; | 236 | s8 usecount; |
| 134 | u8 fixed_div; | 237 | u8 fixed_div; |
| 135 | u8 flags; | 238 | u8 flags; |
| 136 | #ifdef CONFIG_ARCH_OMAP2PLUS | 239 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| @@ -141,8 +244,8 @@ struct clk { | |||
| 141 | const char *clkdm_name; | 244 | const char *clkdm_name; |
| 142 | struct clockdomain *clkdm; | 245 | struct clockdomain *clkdm; |
| 143 | #else | 246 | #else |
| 144 | __u8 rate_offset; | 247 | u8 rate_offset; |
| 145 | __u8 src_offset; | 248 | u8 src_offset; |
| 146 | #endif | 249 | #endif |
| 147 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) | 250 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) |
| 148 | struct dentry *dent; /* For visible tree hierarchy */ | 251 | struct dentry *dent; /* For visible tree hierarchy */ |
| @@ -188,23 +291,4 @@ extern const struct clkops clkops_null; | |||
| 188 | 291 | ||
| 189 | extern struct clk dummy_ck; | 292 | extern struct clk dummy_ck; |
| 190 | 293 | ||
| 191 | /* Clock flags */ | ||
| 192 | #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ | ||
| 193 | #define CLOCK_IDLE_CONTROL (1 << 1) | ||
| 194 | #define CLOCK_NO_IDLE_PARENT (1 << 2) | ||
| 195 | #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ | ||
| 196 | #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ | ||
| 197 | |||
| 198 | /* Clksel_rate flags */ | ||
| 199 | #define RATE_IN_242X (1 << 0) | ||
| 200 | #define RATE_IN_243X (1 << 1) | ||
| 201 | #define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */ | ||
| 202 | #define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */ | ||
| 203 | #define RATE_IN_36XX (1 << 4) | ||
| 204 | #define RATE_IN_4430 (1 << 5) | ||
| 205 | |||
| 206 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) | ||
| 207 | |||
| 208 | #define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX) | ||
| 209 | |||
| 210 | #endif | 294 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 5e4afbee0fd7..9776b41ad76f 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h | |||
| @@ -58,8 +58,7 @@ struct omap_globals { | |||
| 58 | 58 | ||
| 59 | void omap2_set_globals_242x(void); | 59 | void omap2_set_globals_242x(void); |
| 60 | void omap2_set_globals_243x(void); | 60 | void omap2_set_globals_243x(void); |
| 61 | void omap2_set_globals_343x(void); | 61 | void omap2_set_globals_3xxx(void); |
| 62 | void omap2_set_globals_36xx(void); | ||
| 63 | void omap2_set_globals_443x(void); | 62 | void omap2_set_globals_443x(void); |
| 64 | 63 | ||
| 65 | /* These get called from omap2_set_globals_xxxx(), do not call these */ | 64 | /* These get called from omap2_set_globals_xxxx(), do not call these */ |
| @@ -69,6 +68,8 @@ void omap2_set_globals_control(struct omap_globals *); | |||
| 69 | void omap2_set_globals_prcm(struct omap_globals *); | 68 | void omap2_set_globals_prcm(struct omap_globals *); |
| 70 | void omap2_set_globals_uart(struct omap_globals *); | 69 | void omap2_set_globals_uart(struct omap_globals *); |
| 71 | 70 | ||
| 71 | void omap3_map_io(void); | ||
| 72 | |||
| 72 | /** | 73 | /** |
| 73 | * omap_test_timeout - busy-loop, testing a condition | 74 | * omap_test_timeout - busy-loop, testing a condition |
| 74 | * @cond: condition to test until it evaluates to true | 75 | * @cond: condition to test until it evaluates to true |
| @@ -89,4 +90,8 @@ void omap2_set_globals_uart(struct omap_globals *); | |||
| 89 | } \ | 90 | } \ |
| 90 | }) | 91 | }) |
| 91 | 92 | ||
| 93 | extern struct device *omap2_get_mpuss_device(void); | ||
| 94 | extern struct device *omap2_get_dsp_device(void); | ||
| 95 | extern struct device *omap2_get_l3_device(void); | ||
| 96 | |||
| 92 | #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ | 97 | #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ |
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 75141742300c..2e2ae530fced 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h | |||
| @@ -66,6 +66,8 @@ unsigned int omap_rev(void); | |||
| 66 | * family. This difference can be handled separately. | 66 | * family. This difference can be handled separately. |
| 67 | */ | 67 | */ |
| 68 | #define OMAP_REVBITS_00 0x00 | 68 | #define OMAP_REVBITS_00 0x00 |
| 69 | #define OMAP_REVBITS_01 0x01 | ||
| 70 | #define OMAP_REVBITS_02 0x02 | ||
| 69 | #define OMAP_REVBITS_10 0x10 | 71 | #define OMAP_REVBITS_10 0x10 |
| 70 | #define OMAP_REVBITS_20 0x20 | 72 | #define OMAP_REVBITS_20 0x20 |
| 71 | #define OMAP_REVBITS_30 0x30 | 73 | #define OMAP_REVBITS_30 0x30 |
| @@ -376,6 +378,8 @@ IS_OMAP_TYPE(3517, 0x3517) | |||
| 376 | #define OMAP3430_REV_ES3_1_2 0x34305034 | 378 | #define OMAP3430_REV_ES3_1_2 0x34305034 |
| 377 | 379 | ||
| 378 | #define OMAP3630_REV_ES1_0 0x36300034 | 380 | #define OMAP3630_REV_ES1_0 0x36300034 |
| 381 | #define OMAP3630_REV_ES1_1 0x36300134 | ||
| 382 | #define OMAP3630_REV_ES1_2 0x36300234 | ||
| 379 | 383 | ||
| 380 | #define OMAP35XX_CLASS 0x35000034 | 384 | #define OMAP35XX_CLASS 0x35000034 |
| 381 | #define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) | 385 | #define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) |
| @@ -411,6 +415,8 @@ IS_OMAP_TYPE(3517, 0x3517) | |||
| 411 | #define CHIP_IS_OMAP3430ES3_1 (1 << 6) | 415 | #define CHIP_IS_OMAP3430ES3_1 (1 << 6) |
| 412 | #define CHIP_IS_OMAP3630ES1 (1 << 7) | 416 | #define CHIP_IS_OMAP3630ES1 (1 << 7) |
| 413 | #define CHIP_IS_OMAP4430ES1 (1 << 8) | 417 | #define CHIP_IS_OMAP4430ES1 (1 << 8) |
| 418 | #define CHIP_IS_OMAP3630ES1_1 (1 << 9) | ||
| 419 | #define CHIP_IS_OMAP3630ES1_2 (1 << 10) | ||
| 414 | 420 | ||
| 415 | #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) | 421 | #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) |
| 416 | 422 | ||
| @@ -424,11 +430,12 @@ IS_OMAP_TYPE(3517, 0x3517) | |||
| 424 | */ | 430 | */ |
| 425 | #define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \ | 431 | #define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \ |
| 426 | CHIP_IS_OMAP3430ES3_0 | \ | 432 | CHIP_IS_OMAP3430ES3_0 | \ |
| 427 | CHIP_IS_OMAP3430ES3_1 | \ | 433 | CHIP_GE_OMAP3430ES3_1) |
| 428 | CHIP_IS_OMAP3630ES1) | ||
| 429 | #define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \ | 434 | #define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \ |
| 430 | CHIP_IS_OMAP3630ES1) | 435 | CHIP_IS_OMAP3630ES1 | \ |
| 431 | 436 | CHIP_GE_OMAP3630ES1_1) | |
| 437 | #define CHIP_GE_OMAP3630ES1_1 (CHIP_IS_OMAP3630ES1_1 | \ | ||
| 438 | CHIP_IS_OMAP3630ES1_2) | ||
| 432 | 439 | ||
| 433 | int omap_chip_is(struct omap_chip_id oci); | 440 | int omap_chip_is(struct omap_chip_id oci); |
| 434 | void omap2_check_revision(void); | 441 | void omap2_check_revision(void); |
| @@ -444,6 +451,7 @@ extern u32 omap3_features; | |||
| 444 | #define OMAP3_HAS_NEON BIT(3) | 451 | #define OMAP3_HAS_NEON BIT(3) |
| 445 | #define OMAP3_HAS_ISP BIT(4) | 452 | #define OMAP3_HAS_ISP BIT(4) |
| 446 | #define OMAP3_HAS_192MHZ_CLK BIT(5) | 453 | #define OMAP3_HAS_192MHZ_CLK BIT(5) |
| 454 | #define OMAP3_HAS_IO_WAKEUP BIT(6) | ||
| 447 | 455 | ||
| 448 | #define OMAP3_HAS_FEATURE(feat,flag) \ | 456 | #define OMAP3_HAS_FEATURE(feat,flag) \ |
| 449 | static inline unsigned int omap3_has_ ##feat(void) \ | 457 | static inline unsigned int omap3_has_ ##feat(void) \ |
| @@ -457,5 +465,6 @@ OMAP3_HAS_FEATURE(iva, IVA) | |||
| 457 | OMAP3_HAS_FEATURE(neon, NEON) | 465 | OMAP3_HAS_FEATURE(neon, NEON) |
| 458 | OMAP3_HAS_FEATURE(isp, ISP) | 466 | OMAP3_HAS_FEATURE(isp, ISP) |
| 459 | OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) | 467 | OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) |
| 468 | OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP) | ||
| 460 | 469 | ||
| 461 | #endif | 470 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index 02232ca2c37f..af3a03941add 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h | |||
| @@ -345,6 +345,7 @@ | |||
| 345 | #define OMAP_DMA_SYNC_BLOCK 0x02 | 345 | #define OMAP_DMA_SYNC_BLOCK 0x02 |
| 346 | #define OMAP_DMA_SYNC_PACKET 0x03 | 346 | #define OMAP_DMA_SYNC_PACKET 0x03 |
| 347 | 347 | ||
| 348 | #define OMAP_DMA_DST_SYNC_PREFETCH 0x02 | ||
| 348 | #define OMAP_DMA_SRC_SYNC 0x01 | 349 | #define OMAP_DMA_SRC_SYNC 0x01 |
| 349 | #define OMAP_DMA_DST_SYNC 0x00 | 350 | #define OMAP_DMA_DST_SYNC 0x00 |
| 350 | 351 | ||
diff --git a/arch/arm/plat-omap/include/plat/dsp_common.h b/arch/arm/plat-omap/include/plat/dsp_common.h deleted file mode 100644 index da97736f3efa..000000000000 --- a/arch/arm/plat-omap/include/plat/dsp_common.h +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1) | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved. | ||
| 5 | * | ||
| 6 | * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or | ||
| 9 | * modify it under the terms of the GNU General Public License | ||
| 10 | * version 2 as published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, but | ||
| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 15 | * General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | ||
| 20 | * 02110-1301 USA | ||
| 21 | * | ||
| 22 | */ | ||
| 23 | |||
| 24 | #ifndef ASM_ARCH_DSP_COMMON_H | ||
| 25 | #define ASM_ARCH_DSP_COMMON_H | ||
| 26 | |||
| 27 | #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK) | ||
| 28 | extern void omap_dsp_request_mpui(void); | ||
| 29 | extern void omap_dsp_release_mpui(void); | ||
| 30 | extern int omap_dsp_request_mem(void); | ||
| 31 | extern int omap_dsp_release_mem(void); | ||
| 32 | #else | ||
| 33 | static inline int omap_dsp_request_mem(void) | ||
| 34 | { | ||
| 35 | return 0; | ||
| 36 | } | ||
| 37 | #define omap_dsp_release_mem() do {} while (0) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #endif /* ASM_ARCH_DSP_COMMON_H */ | ||
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 145838a81ef6..9fd99b9e40ab 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h | |||
| @@ -25,10 +25,26 @@ | |||
| 25 | #define GPMC_CS_NAND_ADDRESS 0x20 | 25 | #define GPMC_CS_NAND_ADDRESS 0x20 |
| 26 | #define GPMC_CS_NAND_DATA 0x24 | 26 | #define GPMC_CS_NAND_DATA 0x24 |
| 27 | 27 | ||
| 28 | #define GPMC_CONFIG 0x50 | 28 | /* Control Commands */ |
| 29 | #define GPMC_STATUS 0x54 | 29 | #define GPMC_CONFIG_RDY_BSY 0x00000001 |
| 30 | #define GPMC_CS0_BASE 0x60 | 30 | #define GPMC_CONFIG_DEV_SIZE 0x00000002 |
| 31 | #define GPMC_CS_SIZE 0x30 | 31 | #define GPMC_CONFIG_DEV_TYPE 0x00000003 |
| 32 | #define GPMC_SET_IRQ_STATUS 0x00000004 | ||
| 33 | #define GPMC_CONFIG_WP 0x00000005 | ||
| 34 | |||
| 35 | #define GPMC_GET_IRQ_STATUS 0x00000006 | ||
| 36 | #define GPMC_PREFETCH_FIFO_CNT 0x00000007 /* bytes available in FIFO for r/w */ | ||
| 37 | #define GPMC_PREFETCH_COUNT 0x00000008 /* remaining bytes to be read/write*/ | ||
| 38 | #define GPMC_STATUS_BUFFER 0x00000009 /* 1: buffer is available to write */ | ||
| 39 | |||
| 40 | #define GPMC_NAND_COMMAND 0x0000000a | ||
| 41 | #define GPMC_NAND_ADDRESS 0x0000000b | ||
| 42 | #define GPMC_NAND_DATA 0x0000000c | ||
| 43 | |||
| 44 | /* ECC commands */ | ||
| 45 | #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ | ||
| 46 | #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ | ||
| 47 | #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */ | ||
| 32 | 48 | ||
| 33 | #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) | 49 | #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) |
| 34 | #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) | 50 | #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) |
| @@ -47,7 +63,6 @@ | |||
| 47 | #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) | 63 | #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) |
| 48 | #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) | 64 | #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) |
| 49 | #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) | 65 | #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) |
| 50 | #define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2) | ||
| 51 | #define GPMC_CONFIG1_MUXADDDATA (1 << 9) | 66 | #define GPMC_CONFIG1_MUXADDDATA (1 << 9) |
| 52 | #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) | 67 | #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) |
| 53 | #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) | 68 | #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) |
| @@ -56,6 +71,14 @@ | |||
| 56 | #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) | 71 | #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) |
| 57 | #define GPMC_CONFIG7_CSVALID (1 << 6) | 72 | #define GPMC_CONFIG7_CSVALID (1 << 6) |
| 58 | 73 | ||
| 74 | #define GPMC_DEVICETYPE_NOR 0 | ||
| 75 | #define GPMC_DEVICETYPE_NAND 2 | ||
| 76 | #define GPMC_CONFIG_WRITEPROTECT 0x00000010 | ||
| 77 | #define GPMC_STATUS_BUFF_EMPTY 0x00000001 | ||
| 78 | #define WR_RD_PIN_MONITORING 0x00600000 | ||
| 79 | #define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) | ||
| 80 | #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) | ||
| 81 | |||
| 59 | /* | 82 | /* |
| 60 | * Note that all values in this struct are in nanoseconds, while | 83 | * Note that all values in this struct are in nanoseconds, while |
| 61 | * the register values are in gpmc_fck cycles. | 84 | * the register values are in gpmc_fck cycles. |
| @@ -108,10 +131,15 @@ extern int gpmc_cs_set_reserved(int cs, int reserved); | |||
| 108 | extern int gpmc_cs_reserved(int cs); | 131 | extern int gpmc_cs_reserved(int cs); |
| 109 | extern int gpmc_prefetch_enable(int cs, int dma_mode, | 132 | extern int gpmc_prefetch_enable(int cs, int dma_mode, |
| 110 | unsigned int u32_count, int is_write); | 133 | unsigned int u32_count, int is_write); |
| 111 | extern void gpmc_prefetch_reset(void); | 134 | extern int gpmc_prefetch_reset(int cs); |
| 112 | extern int gpmc_prefetch_status(void); | ||
| 113 | extern void omap3_gpmc_save_context(void); | 135 | extern void omap3_gpmc_save_context(void); |
| 114 | extern void omap3_gpmc_restore_context(void); | 136 | extern void omap3_gpmc_restore_context(void); |
| 115 | extern void gpmc_init(void); | 137 | extern void gpmc_init(void); |
| 138 | extern int gpmc_read_status(int cmd); | ||
| 139 | extern int gpmc_cs_configure(int cs, int cmd, int wval); | ||
| 140 | extern int gpmc_nand_read(int cs, int cmd); | ||
| 141 | extern int gpmc_nand_write(int cs, int cmd, int wval); | ||
| 116 | 142 | ||
| 143 | int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size); | ||
| 144 | int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code); | ||
| 117 | #endif | 145 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h index 0752af9d099e..33c7d41cb6a5 100644 --- a/arch/arm/plat-omap/include/plat/iommu.h +++ b/arch/arm/plat-omap/include/plat/iommu.h | |||
| @@ -80,6 +80,7 @@ struct iommu_functions { | |||
| 80 | 80 | ||
| 81 | int (*enable)(struct iommu *obj); | 81 | int (*enable)(struct iommu *obj); |
| 82 | void (*disable)(struct iommu *obj); | 82 | void (*disable)(struct iommu *obj); |
| 83 | void (*set_twl)(struct iommu *obj, bool on); | ||
| 83 | u32 (*fault_isr)(struct iommu *obj, u32 *ra); | 84 | u32 (*fault_isr)(struct iommu *obj, u32 *ra); |
| 84 | 85 | ||
| 85 | void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr); | 86 | void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr); |
| @@ -143,6 +144,7 @@ extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e); | |||
| 143 | extern u32 iotlb_cr_to_virt(struct cr_regs *cr); | 144 | extern u32 iotlb_cr_to_virt(struct cr_regs *cr); |
| 144 | 145 | ||
| 145 | extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e); | 146 | extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e); |
| 147 | extern void iommu_set_twl(struct iommu *obj, bool on); | ||
| 146 | extern void flush_iotlb_page(struct iommu *obj, u32 da); | 148 | extern void flush_iotlb_page(struct iommu *obj, u32 da); |
| 147 | extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end); | 149 | extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end); |
| 148 | extern void flush_iotlb_all(struct iommu *obj); | 150 | extern void flush_iotlb_all(struct iommu *obj); |
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h index 729166b76a7c..997656552109 100644 --- a/arch/arm/plat-omap/include/plat/mailbox.h +++ b/arch/arm/plat-omap/include/plat/mailbox.h | |||
| @@ -3,10 +3,11 @@ | |||
| 3 | #ifndef MAILBOX_H | 3 | #ifndef MAILBOX_H |
| 4 | #define MAILBOX_H | 4 | #define MAILBOX_H |
| 5 | 5 | ||
| 6 | #include <linux/wait.h> | 6 | #include <linux/spinlock.h> |
| 7 | #include <linux/workqueue.h> | 7 | #include <linux/workqueue.h> |
| 8 | #include <linux/blkdev.h> | ||
| 9 | #include <linux/interrupt.h> | 8 | #include <linux/interrupt.h> |
| 9 | #include <linux/device.h> | ||
| 10 | #include <linux/kfifo.h> | ||
| 10 | 11 | ||
| 11 | typedef u32 mbox_msg_t; | 12 | typedef u32 mbox_msg_t; |
| 12 | struct omap_mbox; | 13 | struct omap_mbox; |
| @@ -42,7 +43,7 @@ struct omap_mbox_ops { | |||
| 42 | 43 | ||
| 43 | struct omap_mbox_queue { | 44 | struct omap_mbox_queue { |
| 44 | spinlock_t lock; | 45 | spinlock_t lock; |
| 45 | struct request_queue *queue; | 46 | struct kfifo fifo; |
| 46 | struct work_struct work; | 47 | struct work_struct work; |
| 47 | struct tasklet_struct tasklet; | 48 | struct tasklet_struct tasklet; |
| 48 | int (*callback)(void *); | 49 | int (*callback)(void *); |
| @@ -52,19 +53,10 @@ struct omap_mbox_queue { | |||
| 52 | struct omap_mbox { | 53 | struct omap_mbox { |
| 53 | char *name; | 54 | char *name; |
| 54 | unsigned int irq; | 55 | unsigned int irq; |
| 55 | |||
| 56 | struct omap_mbox_queue *txq, *rxq; | 56 | struct omap_mbox_queue *txq, *rxq; |
| 57 | |||
| 58 | struct omap_mbox_ops *ops; | 57 | struct omap_mbox_ops *ops; |
| 59 | |||
| 60 | mbox_msg_t seq_snd, seq_rcv; | ||
| 61 | |||
| 62 | struct device *dev; | 58 | struct device *dev; |
| 63 | |||
| 64 | struct omap_mbox *next; | ||
| 65 | void *priv; | 59 | void *priv; |
| 66 | |||
| 67 | void (*err_notify)(void); | ||
| 68 | }; | 60 | }; |
| 69 | 61 | ||
| 70 | int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg); | 62 | int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg); |
| @@ -73,8 +65,8 @@ void omap_mbox_init_seq(struct omap_mbox *); | |||
| 73 | struct omap_mbox *omap_mbox_get(const char *); | 65 | struct omap_mbox *omap_mbox_get(const char *); |
| 74 | void omap_mbox_put(struct omap_mbox *); | 66 | void omap_mbox_put(struct omap_mbox *); |
| 75 | 67 | ||
| 76 | int omap_mbox_register(struct device *parent, struct omap_mbox *); | 68 | int omap_mbox_register(struct device *parent, struct omap_mbox **); |
| 77 | int omap_mbox_unregister(struct omap_mbox *); | 69 | int omap_mbox_unregister(void); |
| 78 | 70 | ||
| 79 | static inline void omap_mbox_save_ctx(struct omap_mbox *mbox) | 71 | static inline void omap_mbox_save_ctx(struct omap_mbox *mbox) |
| 80 | { | 72 | { |
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h index c7472a28ce24..aeba71796ad9 100644 --- a/arch/arm/plat-omap/include/plat/mux.h +++ b/arch/arm/plat-omap/include/plat/mux.h | |||
| @@ -114,28 +114,11 @@ | |||
| 114 | PU_PD_REG(NA, 0) \ | 114 | PU_PD_REG(NA, 0) \ |
| 115 | }, | 115 | }, |
| 116 | 116 | ||
| 117 | #define MUX_CFG_24XX(desc, reg_offset, mode, \ | ||
| 118 | pull_en, pull_mode, dbg) \ | ||
| 119 | { \ | ||
| 120 | .name = desc, \ | ||
| 121 | .debug = dbg, \ | ||
| 122 | .mux_reg = reg_offset, \ | ||
| 123 | .mask = mode, \ | ||
| 124 | .pull_val = pull_en, \ | ||
| 125 | .pu_pd_val = pull_mode, \ | ||
| 126 | }, | ||
| 127 | |||
| 128 | /* 24xx/34xx mux bit defines */ | ||
| 129 | #define OMAP2_PULL_ENA (1 << 3) | ||
| 130 | #define OMAP2_PULL_UP (1 << 4) | ||
| 131 | #define OMAP2_ALTELECTRICALSEL (1 << 5) | ||
| 132 | |||
| 133 | struct pin_config { | 117 | struct pin_config { |
| 134 | char *name; | 118 | char *name; |
| 135 | const unsigned int mux_reg; | 119 | const unsigned int mux_reg; |
| 136 | unsigned char debug; | 120 | unsigned char debug; |
| 137 | 121 | ||
| 138 | #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2) | ||
| 139 | const unsigned char mask_offset; | 122 | const unsigned char mask_offset; |
| 140 | const unsigned char mask; | 123 | const unsigned char mask; |
| 141 | 124 | ||
| @@ -147,7 +130,6 @@ struct pin_config { | |||
| 147 | const char *pu_pd_name; | 130 | const char *pu_pd_name; |
| 148 | const unsigned int pu_pd_reg; | 131 | const unsigned int pu_pd_reg; |
| 149 | const unsigned char pu_pd_val; | 132 | const unsigned char pu_pd_val; |
| 150 | #endif | ||
| 151 | 133 | ||
| 152 | #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) | 134 | #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) |
| 153 | const char *mux_reg_name; | 135 | const char *mux_reg_name; |
| @@ -191,6 +173,10 @@ enum omap7xx_index { | |||
| 191 | SPI_7XX_4, | 173 | SPI_7XX_4, |
| 192 | SPI_7XX_5, | 174 | SPI_7XX_5, |
| 193 | SPI_7XX_6, | 175 | SPI_7XX_6, |
| 176 | |||
| 177 | /* UART */ | ||
| 178 | UART_7XX_1, | ||
| 179 | UART_7XX_2, | ||
| 194 | }; | 180 | }; |
| 195 | 181 | ||
| 196 | enum omap1xxx_index { | 182 | enum omap1xxx_index { |
| @@ -446,208 +432,6 @@ enum omap1xxx_index { | |||
| 446 | 432 | ||
| 447 | }; | 433 | }; |
| 448 | 434 | ||
| 449 | enum omap24xx_index { | ||
| 450 | /* 24xx I2C */ | ||
| 451 | M19_24XX_I2C1_SCL, | ||
| 452 | L15_24XX_I2C1_SDA, | ||
| 453 | J15_24XX_I2C2_SCL, | ||
| 454 | H19_24XX_I2C2_SDA, | ||
| 455 | |||
| 456 | /* 24xx Menelaus interrupt */ | ||
| 457 | W19_24XX_SYS_NIRQ, | ||
| 458 | |||
| 459 | /* 24xx clock */ | ||
| 460 | W14_24XX_SYS_CLKOUT, | ||
| 461 | |||
| 462 | /* 24xx GPMC chipselects, wait pin monitoring */ | ||
| 463 | E2_GPMC_NCS2, | ||
| 464 | L2_GPMC_NCS7, | ||
| 465 | L3_GPMC_WAIT0, | ||
| 466 | N7_GPMC_WAIT1, | ||
| 467 | M1_GPMC_WAIT2, | ||
| 468 | P1_GPMC_WAIT3, | ||
| 469 | |||
| 470 | /* 242X McBSP */ | ||
| 471 | Y15_24XX_MCBSP2_CLKX, | ||
| 472 | R14_24XX_MCBSP2_FSX, | ||
| 473 | W15_24XX_MCBSP2_DR, | ||
| 474 | V15_24XX_MCBSP2_DX, | ||
| 475 | |||
| 476 | /* 24xx GPIO */ | ||
| 477 | M21_242X_GPIO11, | ||
| 478 | P21_242X_GPIO12, | ||
| 479 | AA10_242X_GPIO13, | ||
| 480 | AA6_242X_GPIO14, | ||
| 481 | AA4_242X_GPIO15, | ||
| 482 | Y11_242X_GPIO16, | ||
| 483 | AA12_242X_GPIO17, | ||
| 484 | AA8_242X_GPIO58, | ||
| 485 | Y20_24XX_GPIO60, | ||
| 486 | W4__24XX_GPIO74, | ||
| 487 | N15_24XX_GPIO85, | ||
| 488 | M15_24XX_GPIO92, | ||
| 489 | P20_24XX_GPIO93, | ||
| 490 | P18_24XX_GPIO95, | ||
| 491 | M18_24XX_GPIO96, | ||
| 492 | L14_24XX_GPIO97, | ||
| 493 | J15_24XX_GPIO99, | ||
| 494 | V14_24XX_GPIO117, | ||
| 495 | P14_24XX_GPIO125, | ||
| 496 | |||
| 497 | /* 242x DBG GPIO */ | ||
| 498 | V4_242X_GPIO49, | ||
| 499 | W2_242X_GPIO50, | ||
| 500 | U4_242X_GPIO51, | ||
| 501 | V3_242X_GPIO52, | ||
| 502 | V2_242X_GPIO53, | ||
| 503 | V6_242X_GPIO53, | ||
| 504 | T4_242X_GPIO54, | ||
| 505 | Y4_242X_GPIO54, | ||
| 506 | T3_242X_GPIO55, | ||
| 507 | U2_242X_GPIO56, | ||
| 508 | |||
| 509 | /* 24xx external DMA requests */ | ||
| 510 | AA10_242X_DMAREQ0, | ||
| 511 | AA6_242X_DMAREQ1, | ||
| 512 | E4_242X_DMAREQ2, | ||
| 513 | G4_242X_DMAREQ3, | ||
| 514 | D3_242X_DMAREQ4, | ||
| 515 | E3_242X_DMAREQ5, | ||
| 516 | |||
| 517 | /* UART3 */ | ||
| 518 | K15_24XX_UART3_TX, | ||
| 519 | K14_24XX_UART3_RX, | ||
| 520 | |||
| 521 | /* MMC/SDIO */ | ||
| 522 | G19_24XX_MMC_CLKO, | ||
| 523 | H18_24XX_MMC_CMD, | ||
| 524 | F20_24XX_MMC_DAT0, | ||
| 525 | H14_24XX_MMC_DAT1, | ||
| 526 | E19_24XX_MMC_DAT2, | ||
| 527 | D19_24XX_MMC_DAT3, | ||
| 528 | F19_24XX_MMC_DAT_DIR0, | ||
| 529 | E20_24XX_MMC_DAT_DIR1, | ||
| 530 | F18_24XX_MMC_DAT_DIR2, | ||
| 531 | E18_24XX_MMC_DAT_DIR3, | ||
| 532 | G18_24XX_MMC_CMD_DIR, | ||
| 533 | H15_24XX_MMC_CLKI, | ||
| 534 | |||
| 535 | /* Full speed USB */ | ||
| 536 | J20_24XX_USB0_PUEN, | ||
| 537 | J19_24XX_USB0_VP, | ||
| 538 | K20_24XX_USB0_VM, | ||
| 539 | J18_24XX_USB0_RCV, | ||
| 540 | K19_24XX_USB0_TXEN, | ||
| 541 | J14_24XX_USB0_SE0, | ||
| 542 | K18_24XX_USB0_DAT, | ||
| 543 | |||
| 544 | N14_24XX_USB1_SE0, | ||
| 545 | W12_24XX_USB1_SE0, | ||
| 546 | P15_24XX_USB1_DAT, | ||
| 547 | R13_24XX_USB1_DAT, | ||
| 548 | W20_24XX_USB1_TXEN, | ||
| 549 | P13_24XX_USB1_TXEN, | ||
| 550 | V19_24XX_USB1_RCV, | ||
| 551 | V12_24XX_USB1_RCV, | ||
| 552 | |||
| 553 | AA10_24XX_USB2_SE0, | ||
| 554 | Y11_24XX_USB2_DAT, | ||
| 555 | AA12_24XX_USB2_TXEN, | ||
| 556 | AA6_24XX_USB2_RCV, | ||
| 557 | AA4_24XX_USB2_TLLSE0, | ||
| 558 | |||
| 559 | /* Keypad GPIO*/ | ||
| 560 | T19_24XX_KBR0, | ||
| 561 | R19_24XX_KBR1, | ||
| 562 | V18_24XX_KBR2, | ||
| 563 | M21_24XX_KBR3, | ||
| 564 | E5__24XX_KBR4, | ||
| 565 | M18_24XX_KBR5, | ||
| 566 | R20_24XX_KBC0, | ||
| 567 | M14_24XX_KBC1, | ||
| 568 | H19_24XX_KBC2, | ||
| 569 | V17_24XX_KBC3, | ||
| 570 | P21_24XX_KBC4, | ||
| 571 | L14_24XX_KBC5, | ||
| 572 | N19_24XX_KBC6, | ||
| 573 | |||
| 574 | /* 24xx Menelaus Keypad GPIO */ | ||
| 575 | B3__24XX_KBR5, | ||
| 576 | AA4_24XX_KBC2, | ||
| 577 | B13_24XX_KBC6, | ||
| 578 | |||
| 579 | /* 2430 USB */ | ||
| 580 | AD9_2430_USB0_PUEN, | ||
| 581 | Y11_2430_USB0_VP, | ||
| 582 | AD7_2430_USB0_VM, | ||
| 583 | AE7_2430_USB0_RCV, | ||
| 584 | AD4_2430_USB0_TXEN, | ||
| 585 | AF9_2430_USB0_SE0, | ||
| 586 | AE6_2430_USB0_DAT, | ||
| 587 | AD24_2430_USB1_SE0, | ||
| 588 | AB24_2430_USB1_RCV, | ||
| 589 | Y25_2430_USB1_TXEN, | ||
| 590 | AA26_2430_USB1_DAT, | ||
| 591 | |||
| 592 | /* 2430 HS-USB */ | ||
| 593 | AD9_2430_USB0HS_DATA3, | ||
| 594 | Y11_2430_USB0HS_DATA4, | ||
| 595 | AD7_2430_USB0HS_DATA5, | ||
| 596 | AE7_2430_USB0HS_DATA6, | ||
| 597 | AD4_2430_USB0HS_DATA2, | ||
| 598 | AF9_2430_USB0HS_DATA0, | ||
| 599 | AE6_2430_USB0HS_DATA1, | ||
| 600 | AE8_2430_USB0HS_CLK, | ||
| 601 | AD8_2430_USB0HS_DIR, | ||
| 602 | AE5_2430_USB0HS_STP, | ||
| 603 | AE9_2430_USB0HS_NXT, | ||
| 604 | AC7_2430_USB0HS_DATA7, | ||
| 605 | |||
| 606 | /* 2430 McBSP */ | ||
| 607 | AD6_2430_MCBSP_CLKS, | ||
| 608 | |||
| 609 | AB2_2430_MCBSP1_CLKR, | ||
| 610 | AD5_2430_MCBSP1_FSR, | ||
| 611 | AA1_2430_MCBSP1_DX, | ||
| 612 | AF3_2430_MCBSP1_DR, | ||
| 613 | AB3_2430_MCBSP1_FSX, | ||
| 614 | Y9_2430_MCBSP1_CLKX, | ||
| 615 | |||
| 616 | AC10_2430_MCBSP2_FSX, | ||
| 617 | AD16_2430_MCBSP2_CLX, | ||
| 618 | AE13_2430_MCBSP2_DX, | ||
| 619 | AD13_2430_MCBSP2_DR, | ||
| 620 | AC10_2430_MCBSP2_FSX_OFF, | ||
| 621 | AD16_2430_MCBSP2_CLX_OFF, | ||
| 622 | AE13_2430_MCBSP2_DX_OFF, | ||
| 623 | AD13_2430_MCBSP2_DR_OFF, | ||
| 624 | |||
| 625 | AC9_2430_MCBSP3_CLKX, | ||
| 626 | AE4_2430_MCBSP3_FSX, | ||
| 627 | AE2_2430_MCBSP3_DR, | ||
| 628 | AF4_2430_MCBSP3_DX, | ||
| 629 | |||
| 630 | N3_2430_MCBSP4_CLKX, | ||
| 631 | AD23_2430_MCBSP4_DR, | ||
| 632 | AB25_2430_MCBSP4_DX, | ||
| 633 | AC25_2430_MCBSP4_FSX, | ||
| 634 | |||
| 635 | AE16_2430_MCBSP5_CLKX, | ||
| 636 | AF12_2430_MCBSP5_FSX, | ||
| 637 | K7_2430_MCBSP5_DX, | ||
| 638 | M1_2430_MCBSP5_DR, | ||
| 639 | |||
| 640 | /* 2430 McSPI*/ | ||
| 641 | Y18_2430_MCSPI1_CLK, | ||
| 642 | AD15_2430_MCSPI1_SIMO, | ||
| 643 | AE17_2430_MCSPI1_SOMI, | ||
| 644 | U1_2430_MCSPI1_CS0, | ||
| 645 | |||
| 646 | /* Touchscreen GPIO */ | ||
| 647 | AF19_2430_GPIO_85, | ||
| 648 | |||
| 649 | }; | ||
| 650 | |||
| 651 | struct omap_mux_cfg { | 435 | struct omap_mux_cfg { |
| 652 | struct pin_config *pins; | 436 | struct pin_config *pins; |
| 653 | unsigned long size; | 437 | unsigned long size; |
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index f8efd5466b1d..6562cd082bb1 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h | |||
| @@ -21,13 +21,11 @@ struct omap_nand_platform_data { | |||
| 21 | int (*dev_ready)(struct omap_nand_platform_data *); | 21 | int (*dev_ready)(struct omap_nand_platform_data *); |
| 22 | int dma_channel; | 22 | int dma_channel; |
| 23 | unsigned long phys_base; | 23 | unsigned long phys_base; |
| 24 | void __iomem *gpmc_cs_baseaddr; | ||
| 25 | void __iomem *gpmc_baseaddr; | ||
| 26 | int devsize; | 24 | int devsize; |
| 27 | }; | 25 | }; |
| 28 | 26 | ||
| 29 | /* size (4 KiB) for IO mapping */ | 27 | /* minimum size for IO mapping */ |
| 30 | #define NAND_IO_SIZE SZ_4K | 28 | #define NAND_IO_SIZE 4 |
| 31 | 29 | ||
| 32 | #if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) | 30 | #if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) |
| 33 | extern int gpmc_nand_init(struct omap_nand_platform_data *d); | 31 | extern int gpmc_nand_init(struct omap_nand_platform_data *d); |
diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h index 3ee41d711492..728fbb9dd549 100644 --- a/arch/arm/plat-omap/include/plat/omap-pm.h +++ b/arch/arm/plat-omap/include/plat/omap-pm.h | |||
| @@ -1,8 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * omap-pm.h - OMAP power management interface | 2 | * omap-pm.h - OMAP power management interface |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2008-2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2008-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2008-2009 Nokia Corporation | 5 | * Copyright (C) 2008-2010 Nokia Corporation |
| 6 | * Paul Walmsley | 6 | * Paul Walmsley |
| 7 | * | 7 | * |
| 8 | * Interface developed by (in alphabetical order): Karthik Dasu, Jouni | 8 | * Interface developed by (in alphabetical order): Karthik Dasu, Jouni |
| @@ -16,6 +16,7 @@ | |||
| 16 | 16 | ||
| 17 | #include <linux/device.h> | 17 | #include <linux/device.h> |
| 18 | #include <linux/cpufreq.h> | 18 | #include <linux/cpufreq.h> |
| 19 | #include <linux/clk.h> | ||
| 19 | 20 | ||
| 20 | #include "powerdomain.h" | 21 | #include "powerdomain.h" |
| 21 | 22 | ||
| @@ -89,7 +90,7 @@ void omap_pm_if_exit(void); | |||
| 89 | * @t: maximum MPU wakeup latency in microseconds | 90 | * @t: maximum MPU wakeup latency in microseconds |
| 90 | * | 91 | * |
| 91 | * Request that the maximum interrupt latency for the MPU to be no | 92 | * Request that the maximum interrupt latency for the MPU to be no |
| 92 | * greater than 't' microseconds. "Interrupt latency" in this case is | 93 | * greater than @t microseconds. "Interrupt latency" in this case is |
| 93 | * defined as the elapsed time from the occurrence of a hardware or | 94 | * defined as the elapsed time from the occurrence of a hardware or |
| 94 | * timer interrupt to the time when the device driver's interrupt | 95 | * timer interrupt to the time when the device driver's interrupt |
| 95 | * service routine has been entered by the MPU. | 96 | * service routine has been entered by the MPU. |
| @@ -105,15 +106,19 @@ void omap_pm_if_exit(void); | |||
| 105 | * elapsed from when a device driver enables a hardware device with | 106 | * elapsed from when a device driver enables a hardware device with |
| 106 | * clk_enable(), to when the device is ready for register access or | 107 | * clk_enable(), to when the device is ready for register access or |
| 107 | * other use. To control this device wakeup latency, use | 108 | * other use. To control this device wakeup latency, use |
| 108 | * set_max_dev_wakeup_lat() | 109 | * omap_pm_set_max_dev_wakeup_lat() |
| 109 | * | 110 | * |
| 110 | * Multiple calls to set_max_mpu_wakeup_lat() will replace the | 111 | * Multiple calls to omap_pm_set_max_mpu_wakeup_lat() will replace the |
| 111 | * previous t value. To remove the latency target for the MPU, call | 112 | * previous t value. To remove the latency target for the MPU, call |
| 112 | * with t = -1. | 113 | * with t = -1. |
| 113 | * | 114 | * |
| 114 | * No return value. | 115 | * XXX This constraint will be deprecated soon in favor of the more |
| 116 | * general omap_pm_set_max_dev_wakeup_lat() | ||
| 117 | * | ||
| 118 | * Returns -EINVAL for an invalid argument, -ERANGE if the constraint | ||
| 119 | * is not satisfiable, or 0 upon success. | ||
| 115 | */ | 120 | */ |
| 116 | void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); | 121 | int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); |
| 117 | 122 | ||
| 118 | 123 | ||
| 119 | /** | 124 | /** |
| @@ -123,8 +128,8 @@ void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); | |||
| 123 | * @r: minimum throughput (in KiB/s) | 128 | * @r: minimum throughput (in KiB/s) |
| 124 | * | 129 | * |
| 125 | * Request that the minimum data throughput on the OCP interconnect | 130 | * Request that the minimum data throughput on the OCP interconnect |
| 126 | * attached to device 'dev' interconnect agent 'tbus_id' be no less | 131 | * attached to device @dev interconnect agent @tbus_id be no less |
| 127 | * than 'r' KiB/s. | 132 | * than @r KiB/s. |
| 128 | * | 133 | * |
| 129 | * It is expected that the OMAP PM or bus code will use this | 134 | * It is expected that the OMAP PM or bus code will use this |
| 130 | * information to set the interconnect clock to run at the lowest | 135 | * information to set the interconnect clock to run at the lowest |
| @@ -138,40 +143,44 @@ void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); | |||
| 138 | * code will also need to add an minimum L3 interconnect speed | 143 | * code will also need to add an minimum L3 interconnect speed |
| 139 | * constraint, | 144 | * constraint, |
| 140 | * | 145 | * |
| 141 | * Multiple calls to set_min_bus_tput() will replace the previous rate | 146 | * Multiple calls to omap_pm_set_min_bus_tput() will replace the |
| 142 | * value for this device. To remove the interconnect throughput | 147 | * previous rate value for this device. To remove the interconnect |
| 143 | * restriction for this device, call with r = 0. | 148 | * throughput restriction for this device, call with r = 0. |
| 144 | * | 149 | * |
| 145 | * No return value. | 150 | * Returns -EINVAL for an invalid argument, -ERANGE if the constraint |
| 151 | * is not satisfiable, or 0 upon success. | ||
| 146 | */ | 152 | */ |
| 147 | void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r); | 153 | int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r); |
| 148 | 154 | ||
| 149 | 155 | ||
| 150 | /** | 156 | /** |
| 151 | * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency | 157 | * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency |
| 152 | * @dev: struct device * | 158 | * @req_dev: struct device * requesting the constraint, or NULL if none |
| 159 | * @dev: struct device * to set the constraint one | ||
| 153 | * @t: maximum device wakeup latency in microseconds | 160 | * @t: maximum device wakeup latency in microseconds |
| 154 | * | 161 | * |
| 155 | * Request that the maximum amount of time necessary for a device to | 162 | * Request that the maximum amount of time necessary for a device @dev |
| 156 | * become accessible after its clocks are enabled should be no greater | 163 | * to become accessible after its clocks are enabled should be no |
| 157 | * than 't' microseconds. Specifically, this represents the time from | 164 | * greater than @t microseconds. Specifically, this represents the |
| 158 | * when a device driver enables device clocks with clk_enable(), to | 165 | * time from when a device driver enables device clocks with |
| 159 | * when the register reads and writes on the device will succeed. | 166 | * clk_enable(), to when the register reads and writes on the device |
| 160 | * This function should be called before clk_disable() is called, | 167 | * will succeed. This function should be called before clk_disable() |
| 161 | * since the power state transition decision may be made during | 168 | * is called, since the power state transition decision may be made |
| 162 | * clk_disable(). | 169 | * during clk_disable(). |
| 163 | * | 170 | * |
| 164 | * It is intended that underlying PM code will use this information to | 171 | * It is intended that underlying PM code will use this information to |
| 165 | * determine what power state to put the powerdomain enclosing this | 172 | * determine what power state to put the powerdomain enclosing this |
| 166 | * device into. | 173 | * device into. |
| 167 | * | 174 | * |
| 168 | * Multiple calls to set_max_dev_wakeup_lat() will replace the | 175 | * Multiple calls to omap_pm_set_max_dev_wakeup_lat() will replace the |
| 169 | * previous wakeup latency values for this device. To remove the wakeup | 176 | * previous wakeup latency values for this device. To remove the |
| 170 | * latency restriction for this device, call with t = -1. | 177 | * wakeup latency restriction for this device, call with t = -1. |
| 171 | * | 178 | * |
| 172 | * No return value. | 179 | * Returns -EINVAL for an invalid argument, -ERANGE if the constraint |
| 180 | * is not satisfiable, or 0 upon success. | ||
| 173 | */ | 181 | */ |
| 174 | void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t); | 182 | int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev, |
| 183 | long t); | ||
| 175 | 184 | ||
| 176 | 185 | ||
| 177 | /** | 186 | /** |
| @@ -198,10 +207,71 @@ void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t); | |||
| 198 | * value for this device. To remove the maximum DMA latency for this | 207 | * value for this device. To remove the maximum DMA latency for this |
| 199 | * device, call with t = -1. | 208 | * device, call with t = -1. |
| 200 | * | 209 | * |
| 201 | * No return value. | 210 | * Returns -EINVAL for an invalid argument, -ERANGE if the constraint |
| 211 | * is not satisfiable, or 0 upon success. | ||
| 202 | */ | 212 | */ |
| 203 | void omap_pm_set_max_sdma_lat(struct device *dev, long t); | 213 | int omap_pm_set_max_sdma_lat(struct device *dev, long t); |
| 214 | |||
| 204 | 215 | ||
| 216 | /** | ||
| 217 | * omap_pm_set_min_clk_rate - set minimum clock rate requested by @dev | ||
| 218 | * @dev: struct device * requesting the constraint | ||
| 219 | * @clk: struct clk * to set the minimum rate constraint on | ||
| 220 | * @r: minimum rate in Hz | ||
| 221 | * | ||
| 222 | * Request that the minimum clock rate on the device @dev's clk @clk | ||
| 223 | * be no less than @r Hz. | ||
| 224 | * | ||
| 225 | * It is expected that the OMAP PM code will use this information to | ||
| 226 | * find an OPP or clock setting that will satisfy this clock rate | ||
| 227 | * constraint, along with any other applicable system constraints on | ||
| 228 | * the clock rate or corresponding voltage, etc. | ||
| 229 | * | ||
| 230 | * omap_pm_set_min_clk_rate() differs from the clock code's | ||
| 231 | * clk_set_rate() in that it considers other constraints before taking | ||
| 232 | * any hardware action, and may change a system OPP rather than just a | ||
| 233 | * clock rate. clk_set_rate() is intended to be a low-level | ||
| 234 | * interface. | ||
| 235 | * | ||
| 236 | * omap_pm_set_min_clk_rate() is easily open to abuse. A better API | ||
| 237 | * would be something like "omap_pm_set_min_dev_performance()"; | ||
| 238 | * however, there is no easily-generalizable concept of performance | ||
| 239 | * that applies to all devices. Only a device (and possibly the | ||
| 240 | * device subsystem) has both the subsystem-specific knowledge, and | ||
| 241 | * the hardware IP block-specific knowledge, to translate a constraint | ||
| 242 | * on "touchscreen sampling accuracy" or "number of pixels or polygons | ||
| 243 | * rendered per second" to a clock rate. This translation can be | ||
| 244 | * dependent on the hardware IP block's revision, or firmware version, | ||
| 245 | * and the driver is the only code on the system that has this | ||
| 246 | * information and can know how to translate that into a clock rate. | ||
| 247 | * | ||
| 248 | * The intended use-case for this function is for userspace or other | ||
| 249 | * kernel code to communicate a particular performance requirement to | ||
| 250 | * a subsystem; then for the subsystem to communicate that requirement | ||
| 251 | * to something that is meaningful to the device driver; then for the | ||
| 252 | * device driver to convert that requirement to a clock rate, and to | ||
| 253 | * then call omap_pm_set_min_clk_rate(). | ||
| 254 | * | ||
| 255 | * Users of this function (such as device drivers) should not simply | ||
| 256 | * call this function with some high clock rate to ensure "high | ||
| 257 | * performance." Rather, the device driver should take a performance | ||
| 258 | * constraint from its subsystem, such as "render at least X polygons | ||
| 259 | * per second," and use some formula or table to convert that into a | ||
| 260 | * clock rate constraint given the hardware type and hardware | ||
| 261 | * revision. Device drivers or subsystems should not assume that they | ||
| 262 | * know how to make a power/performance tradeoff - some device use | ||
| 263 | * cases may tolerate a lower-fidelity device function for lower power | ||
| 264 | * consumption; others may demand a higher-fidelity device function, | ||
| 265 | * no matter what the power consumption. | ||
| 266 | * | ||
| 267 | * Multiple calls to omap_pm_set_min_clk_rate() will replace the | ||
| 268 | * previous rate value for the device @dev. To remove the minimum clock | ||
| 269 | * rate constraint for the device, call with r = 0. | ||
| 270 | * | ||
| 271 | * Returns -EINVAL for an invalid argument, -ERANGE if the constraint | ||
| 272 | * is not satisfiable, or 0 upon success. | ||
| 273 | */ | ||
| 274 | int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r); | ||
| 205 | 275 | ||
| 206 | /* | 276 | /* |
| 207 | * DSP Bridge-specific constraints | 277 | * DSP Bridge-specific constraints |
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index 3694b622c4ac..25cd9ac3b095 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h | |||
| @@ -101,6 +101,8 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, | |||
| 101 | int omap_device_register(struct omap_device *od); | 101 | int omap_device_register(struct omap_device *od); |
| 102 | int omap_early_device_register(struct omap_device *od); | 102 | int omap_early_device_register(struct omap_device *od); |
| 103 | 103 | ||
| 104 | void __iomem *omap_device_get_rt_va(struct omap_device *od); | ||
| 105 | |||
| 104 | /* OMAP PM interface */ | 106 | /* OMAP PM interface */ |
| 105 | int omap_device_align_pm_lat(struct platform_device *pdev, | 107 | int omap_device_align_pm_lat(struct platform_device *pdev, |
| 106 | u32 new_wakeup_lat_limit); | 108 | u32 new_wakeup_lat_limit); |
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 0eccc09ac4a9..a4e508dfaba2 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * omap_hwmod macros, structures | 2 | * omap_hwmod macros, structures |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
| 5 | * Paul Walmsley | 5 | * Paul Walmsley |
| 6 | * | 6 | * |
| 7 | * Created in collaboration with (alphabetical order): Benoît Cousson, | 7 | * Created in collaboration with (alphabetical order): Benoît Cousson, |
| @@ -419,7 +419,7 @@ struct omap_hwmod_class { | |||
| 419 | * @slaves: ptr to array of OCP ifs that this hwmod can respond on | 419 | * @slaves: ptr to array of OCP ifs that this hwmod can respond on |
| 420 | * @dev_attr: arbitrary device attributes that can be passed to the driver | 420 | * @dev_attr: arbitrary device attributes that can be passed to the driver |
| 421 | * @_sysc_cache: internal-use hwmod flags | 421 | * @_sysc_cache: internal-use hwmod flags |
| 422 | * @_rt_va: cached register target start address (internal use) | 422 | * @_mpu_rt_va: cached register target start address (internal use) |
| 423 | * @_mpu_port_index: cached MPU register target slave ID (internal use) | 423 | * @_mpu_port_index: cached MPU register target slave ID (internal use) |
| 424 | * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) | 424 | * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) |
| 425 | * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift | 425 | * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift |
| @@ -460,7 +460,7 @@ struct omap_hwmod { | |||
| 460 | struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ | 460 | struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ |
| 461 | void *dev_attr; | 461 | void *dev_attr; |
| 462 | u32 _sysc_cache; | 462 | u32 _sysc_cache; |
| 463 | void __iomem *_rt_va; | 463 | void __iomem *_mpu_rt_va; |
| 464 | struct list_head node; | 464 | struct list_head node; |
| 465 | u16 flags; | 465 | u16 flags; |
| 466 | u8 _mpu_port_index; | 466 | u8 _mpu_port_index; |
| @@ -482,11 +482,14 @@ int omap_hwmod_init(struct omap_hwmod **ohs); | |||
| 482 | int omap_hwmod_register(struct omap_hwmod *oh); | 482 | int omap_hwmod_register(struct omap_hwmod *oh); |
| 483 | int omap_hwmod_unregister(struct omap_hwmod *oh); | 483 | int omap_hwmod_unregister(struct omap_hwmod *oh); |
| 484 | struct omap_hwmod *omap_hwmod_lookup(const char *name); | 484 | struct omap_hwmod *omap_hwmod_lookup(const char *name); |
| 485 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh)); | 485 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
| 486 | int omap_hwmod_late_init(void); | 486 | void *data); |
| 487 | int omap_hwmod_late_init(u8 skip_setup_idle); | ||
| 487 | 488 | ||
| 488 | int omap_hwmod_enable(struct omap_hwmod *oh); | 489 | int omap_hwmod_enable(struct omap_hwmod *oh); |
| 490 | int _omap_hwmod_enable(struct omap_hwmod *oh); | ||
| 489 | int omap_hwmod_idle(struct omap_hwmod *oh); | 491 | int omap_hwmod_idle(struct omap_hwmod *oh); |
| 492 | int _omap_hwmod_idle(struct omap_hwmod *oh); | ||
| 490 | int omap_hwmod_shutdown(struct omap_hwmod *oh); | 493 | int omap_hwmod_shutdown(struct omap_hwmod *oh); |
| 491 | 494 | ||
| 492 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh); | 495 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh); |
| @@ -504,6 +507,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh); | |||
| 504 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); | 507 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); |
| 505 | 508 | ||
| 506 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); | 509 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); |
| 510 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh); | ||
| 507 | 511 | ||
| 508 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | 512 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, |
| 509 | struct omap_hwmod *init_oh); | 513 | struct omap_hwmod *init_oh); |
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h index 8983d54c4fd2..6a3ff65c0303 100644 --- a/arch/arm/plat-omap/include/plat/smp.h +++ b/arch/arm/plat-omap/include/plat/smp.h | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | extern void omap_secondary_startup(void); | 30 | extern void omap_secondary_startup(void); |
| 31 | extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); | 31 | extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); |
| 32 | extern void omap_auxcoreboot_addr(u32 cpu_addr); | 32 | extern void omap_auxcoreboot_addr(u32 cpu_addr); |
| 33 | extern u32 omap_read_auxcoreboot0(void); | ||
| 33 | 34 | ||
| 34 | /* | 35 | /* |
| 35 | * We use Soft IRQ1 as the IPI | 36 | * We use Soft IRQ1 as the IPI |
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index bbedd71943f6..ddf723be48dc 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h | |||
| @@ -25,6 +25,8 @@ | |||
| 25 | 25 | ||
| 26 | #include <plat/serial.h> | 26 | #include <plat/serial.h> |
| 27 | 27 | ||
| 28 | #define MDR1_MODE_MASK 0x07 | ||
| 29 | |||
| 28 | static volatile u8 *uart_base; | 30 | static volatile u8 *uart_base; |
| 29 | static int uart_shift; | 31 | static int uart_shift; |
| 30 | 32 | ||
| @@ -42,6 +44,10 @@ static void putc(int c) | |||
| 42 | if (!uart_base) | 44 | if (!uart_base) |
| 43 | return; | 45 | return; |
| 44 | 46 | ||
| 47 | /* Check for UART 16x mode */ | ||
| 48 | if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0) | ||
| 49 | return; | ||
| 50 | |||
| 45 | while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE)) | 51 | while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE)) |
| 46 | barrier(); | 52 | barrier(); |
| 47 | uart_base[UART_TX << uart_shift] = c; | 53 | uart_base[UART_TX << uart_shift] = c; |
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 98eef5360e6d..2a9427c8cc48 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h | |||
| @@ -81,7 +81,34 @@ extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata); | |||
| 81 | 81 | ||
| 82 | #endif | 82 | #endif |
| 83 | 83 | ||
| 84 | void omap_usb_init(struct omap_usb_config *pdata); | 84 | |
| 85 | /* | ||
| 86 | * FIXME correct answer depends on hmc_mode, | ||
| 87 | * as does (on omap1) any nonzero value for config->otg port number | ||
| 88 | */ | ||
| 89 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 90 | #define is_usb0_device(config) 1 | ||
| 91 | #else | ||
| 92 | #define is_usb0_device(config) 0 | ||
| 93 | #endif | ||
| 94 | |||
| 95 | void omap_otg_init(struct omap_usb_config *config); | ||
| 96 | |||
| 97 | #if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE) | ||
| 98 | void omap1_usb_init(struct omap_usb_config *pdata); | ||
| 99 | #else | ||
| 100 | static inline void omap1_usb_init(struct omap_usb_config *pdata) | ||
| 101 | { | ||
| 102 | } | ||
| 103 | #endif | ||
| 104 | |||
| 105 | #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE) | ||
| 106 | void omap2_usbfs_init(struct omap_usb_config *pdata); | ||
| 107 | #else | ||
| 108 | static inline omap2_usbfs_init(struct omap_usb_config *pdata) | ||
| 109 | { | ||
| 110 | } | ||
| 111 | #endif | ||
| 85 | 112 | ||
| 86 | /*-------------------------------------------------------------------------*/ | 113 | /*-------------------------------------------------------------------------*/ |
| 87 | 114 | ||
| @@ -192,4 +219,24 @@ void omap_usb_init(struct omap_usb_config *pdata); | |||
| 192 | # define USB0PUENACTLOI (1 << 16) | 219 | # define USB0PUENACTLOI (1 << 16) |
| 193 | # define USBSTANDBYCTRL (1 << 15) | 220 | # define USBSTANDBYCTRL (1 << 15) |
| 194 | 221 | ||
| 222 | #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB) | ||
| 223 | u32 omap1_usb0_init(unsigned nwires, unsigned is_device); | ||
| 224 | u32 omap1_usb1_init(unsigned nwires); | ||
| 225 | u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup); | ||
| 226 | #else | ||
| 227 | static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device) | ||
| 228 | { | ||
| 229 | return 0; | ||
| 230 | } | ||
| 231 | static inline u32 omap1_usb1_init(unsigned nwires) | ||
| 232 | { | ||
| 233 | return 0; | ||
| 234 | |||
| 235 | } | ||
| 236 | static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup) | ||
| 237 | { | ||
| 238 | return 0; | ||
| 239 | } | ||
| 240 | #endif | ||
| 241 | |||
| 195 | #endif /* __ASM_ARCH_OMAP_USB_H */ | 242 | #endif /* __ASM_ARCH_OMAP_USB_H */ |
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index bc094dbacee6..a202a2ce6e3d 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c | |||
| @@ -370,6 +370,23 @@ void flush_iotlb_all(struct iommu *obj) | |||
| 370 | } | 370 | } |
| 371 | EXPORT_SYMBOL_GPL(flush_iotlb_all); | 371 | EXPORT_SYMBOL_GPL(flush_iotlb_all); |
| 372 | 372 | ||
| 373 | /** | ||
| 374 | * iommu_set_twl - enable/disable table walking logic | ||
| 375 | * @obj: target iommu | ||
| 376 | * @on: enable/disable | ||
| 377 | * | ||
| 378 | * Function used to enable/disable TWL. If one wants to work | ||
| 379 | * exclusively with locked TLB entries and receive notifications | ||
| 380 | * for TLB miss then call this function to disable TWL. | ||
| 381 | */ | ||
| 382 | void iommu_set_twl(struct iommu *obj, bool on) | ||
| 383 | { | ||
| 384 | clk_enable(obj->clk); | ||
| 385 | arch_iommu->set_twl(obj, on); | ||
| 386 | clk_disable(obj->clk); | ||
| 387 | } | ||
| 388 | EXPORT_SYMBOL_GPL(iommu_set_twl); | ||
| 389 | |||
| 373 | #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) | 390 | #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) |
| 374 | 391 | ||
| 375 | ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes) | 392 | ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes) |
| @@ -653,7 +670,7 @@ void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | |||
| 653 | if (!*iopgd) | 670 | if (!*iopgd) |
| 654 | goto out; | 671 | goto out; |
| 655 | 672 | ||
| 656 | if (*iopgd & IOPGD_TABLE) | 673 | if (iopgd_is_table(*iopgd)) |
| 657 | iopte = iopte_offset(iopgd, da); | 674 | iopte = iopte_offset(iopgd, da); |
| 658 | out: | 675 | out: |
| 659 | *ppgd = iopgd; | 676 | *ppgd = iopgd; |
| @@ -670,7 +687,7 @@ static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da) | |||
| 670 | if (!*iopgd) | 687 | if (!*iopgd) |
| 671 | return 0; | 688 | return 0; |
| 672 | 689 | ||
| 673 | if (*iopgd & IOPGD_TABLE) { | 690 | if (iopgd_is_table(*iopgd)) { |
| 674 | int i; | 691 | int i; |
| 675 | u32 *iopte = iopte_offset(iopgd, da); | 692 | u32 *iopte = iopte_offset(iopgd, da); |
| 676 | 693 | ||
| @@ -745,7 +762,7 @@ static void iopgtable_clear_entry_all(struct iommu *obj) | |||
| 745 | if (!*iopgd) | 762 | if (!*iopgd) |
| 746 | continue; | 763 | continue; |
| 747 | 764 | ||
| 748 | if (*iopgd & IOPGD_TABLE) | 765 | if (iopgd_is_table(*iopgd)) |
| 749 | iopte_free(iopte_offset(iopgd, 0)); | 766 | iopte_free(iopte_offset(iopgd, 0)); |
| 750 | 767 | ||
| 751 | *iopgd = 0; | 768 | *iopgd = 0; |
| @@ -783,9 +800,11 @@ static irqreturn_t iommu_fault_handler(int irq, void *data) | |||
| 783 | if (!stat) | 800 | if (!stat) |
| 784 | return IRQ_HANDLED; | 801 | return IRQ_HANDLED; |
| 785 | 802 | ||
| 803 | iommu_disable(obj); | ||
| 804 | |||
| 786 | iopgd = iopgd_offset(obj, da); | 805 | iopgd = iopgd_offset(obj, da); |
| 787 | 806 | ||
| 788 | if (!(*iopgd & IOPGD_TABLE)) { | 807 | if (!iopgd_is_table(*iopgd)) { |
| 789 | dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__, | 808 | dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__, |
| 790 | da, iopgd, *iopgd); | 809 | da, iopgd, *iopgd); |
| 791 | return IRQ_NONE; | 810 | return IRQ_NONE; |
diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h index ab23b6a140fd..c3e93bb0911f 100644 --- a/arch/arm/plat-omap/iopgtable.h +++ b/arch/arm/plat-omap/iopgtable.h | |||
| @@ -63,6 +63,8 @@ | |||
| 63 | #define IOPGD_SECTION (2 << 0) | 63 | #define IOPGD_SECTION (2 << 0) |
| 64 | #define IOPGD_SUPER (1 << 18 | 2 << 0) | 64 | #define IOPGD_SUPER (1 << 18 | 2 << 0) |
| 65 | 65 | ||
| 66 | #define iopgd_is_table(x) (((x) & 3) == IOPGD_TABLE) | ||
| 67 | |||
| 66 | #define IOPTE_SMALL (2 << 0) | 68 | #define IOPTE_SMALL (2 << 0) |
| 67 | #define IOPTE_LARGE (1 << 0) | 69 | #define IOPTE_LARGE (1 << 0) |
| 68 | 70 | ||
| @@ -70,12 +72,12 @@ | |||
| 70 | #define iopgd_index(da) (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1)) | 72 | #define iopgd_index(da) (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1)) |
| 71 | #define iopgd_offset(obj, da) ((obj)->iopgd + iopgd_index(da)) | 73 | #define iopgd_offset(obj, da) ((obj)->iopgd + iopgd_index(da)) |
| 72 | 74 | ||
| 73 | #define iopte_paddr(iopgd) (*iopgd & ~((1 << 10) - 1)) | 75 | #define iopgd_page_paddr(iopgd) (*iopgd & ~((1 << 10) - 1)) |
| 74 | #define iopte_vaddr(iopgd) ((u32 *)phys_to_virt(iopte_paddr(iopgd))) | 76 | #define iopgd_page_vaddr(iopgd) ((u32 *)phys_to_virt(iopgd_page_paddr(iopgd))) |
| 75 | 77 | ||
| 76 | /* to find an entry in the second-level page table. */ | 78 | /* to find an entry in the second-level page table. */ |
| 77 | #define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1)) | 79 | #define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1)) |
| 78 | #define iopte_offset(iopgd, da) (iopte_vaddr(iopgd) + iopte_index(da)) | 80 | #define iopte_offset(iopgd, da) (iopgd_page_vaddr(iopgd) + iopte_index(da)) |
| 79 | 81 | ||
| 80 | static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, | 82 | static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, |
| 81 | u32 flags) | 83 | u32 flags) |
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index 08a2df766289..d2fafb892f7f 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c | |||
| @@ -21,19 +21,26 @@ | |||
| 21 | * | 21 | * |
| 22 | */ | 22 | */ |
| 23 | 23 | ||
| 24 | #include <linux/module.h> | ||
| 25 | #include <linux/interrupt.h> | 24 | #include <linux/interrupt.h> |
| 26 | #include <linux/device.h> | 25 | #include <linux/spinlock.h> |
| 26 | #include <linux/mutex.h> | ||
| 27 | #include <linux/delay.h> | 27 | #include <linux/delay.h> |
| 28 | #include <linux/slab.h> | 28 | #include <linux/slab.h> |
| 29 | #include <linux/kfifo.h> | ||
| 30 | #include <linux/err.h> | ||
| 29 | 31 | ||
| 30 | #include <plat/mailbox.h> | 32 | #include <plat/mailbox.h> |
| 31 | 33 | ||
| 32 | static struct workqueue_struct *mboxd; | 34 | static struct workqueue_struct *mboxd; |
| 33 | static struct omap_mbox *mboxes; | 35 | static struct omap_mbox **mboxes; |
| 34 | static DEFINE_RWLOCK(mboxes_lock); | 36 | static bool rq_full; |
| 35 | 37 | ||
| 36 | static int mbox_configured; | 38 | static int mbox_configured; |
| 39 | static DEFINE_MUTEX(mbox_configured_lock); | ||
| 40 | |||
| 41 | static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE; | ||
| 42 | module_param(mbox_kfifo_size, uint, S_IRUGO); | ||
| 43 | MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)"); | ||
| 37 | 44 | ||
| 38 | /* Mailbox FIFO handle functions */ | 45 | /* Mailbox FIFO handle functions */ |
| 39 | static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox) | 46 | static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox) |
| @@ -67,7 +74,7 @@ static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | |||
| 67 | /* | 74 | /* |
| 68 | * message sender | 75 | * message sender |
| 69 | */ | 76 | */ |
| 70 | static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg) | 77 | static int __mbox_poll_for_space(struct omap_mbox *mbox) |
| 71 | { | 78 | { |
| 72 | int ret = 0, i = 1000; | 79 | int ret = 0, i = 1000; |
| 73 | 80 | ||
| @@ -78,49 +85,50 @@ static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg) | |||
| 78 | return -1; | 85 | return -1; |
| 79 | udelay(1); | 86 | udelay(1); |
| 80 | } | 87 | } |
| 81 | mbox_fifo_write(mbox, msg); | ||
| 82 | return ret; | 88 | return ret; |
| 83 | } | 89 | } |
| 84 | 90 | ||
| 85 | |||
| 86 | int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg) | 91 | int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg) |
| 87 | { | 92 | { |
| 93 | struct omap_mbox_queue *mq = mbox->txq; | ||
| 94 | int ret = 0, len; | ||
| 88 | 95 | ||
| 89 | struct request *rq; | 96 | spin_lock(&mq->lock); |
| 90 | struct request_queue *q = mbox->txq->queue; | ||
| 91 | 97 | ||
| 92 | rq = blk_get_request(q, WRITE, GFP_ATOMIC); | 98 | if (kfifo_avail(&mq->fifo) < sizeof(msg)) { |
| 93 | if (unlikely(!rq)) | 99 | ret = -ENOMEM; |
| 94 | return -ENOMEM; | 100 | goto out; |
| 101 | } | ||
| 102 | |||
| 103 | len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); | ||
| 104 | WARN_ON(len != sizeof(msg)); | ||
| 95 | 105 | ||
| 96 | blk_insert_request(q, rq, 0, (void *) msg); | ||
| 97 | tasklet_schedule(&mbox->txq->tasklet); | 106 | tasklet_schedule(&mbox->txq->tasklet); |
| 98 | 107 | ||
| 99 | return 0; | 108 | out: |
| 109 | spin_unlock(&mq->lock); | ||
| 110 | return ret; | ||
| 100 | } | 111 | } |
| 101 | EXPORT_SYMBOL(omap_mbox_msg_send); | 112 | EXPORT_SYMBOL(omap_mbox_msg_send); |
| 102 | 113 | ||
| 103 | static void mbox_tx_tasklet(unsigned long tx_data) | 114 | static void mbox_tx_tasklet(unsigned long tx_data) |
| 104 | { | 115 | { |
| 105 | int ret; | ||
| 106 | struct request *rq; | ||
| 107 | struct omap_mbox *mbox = (struct omap_mbox *)tx_data; | 116 | struct omap_mbox *mbox = (struct omap_mbox *)tx_data; |
| 108 | struct request_queue *q = mbox->txq->queue; | 117 | struct omap_mbox_queue *mq = mbox->txq; |
| 109 | 118 | mbox_msg_t msg; | |
| 110 | while (1) { | 119 | int ret; |
| 111 | |||
| 112 | rq = blk_fetch_request(q); | ||
| 113 | |||
| 114 | if (!rq) | ||
| 115 | break; | ||
| 116 | 120 | ||
| 117 | ret = __mbox_msg_send(mbox, (mbox_msg_t)rq->special); | 121 | while (kfifo_len(&mq->fifo)) { |
| 118 | if (ret) { | 122 | if (__mbox_poll_for_space(mbox)) { |
| 119 | omap_mbox_enable_irq(mbox, IRQ_TX); | 123 | omap_mbox_enable_irq(mbox, IRQ_TX); |
| 120 | blk_requeue_request(q, rq); | 124 | break; |
| 121 | return; | ||
| 122 | } | 125 | } |
| 123 | blk_end_request_all(rq, 0); | 126 | |
| 127 | ret = kfifo_out(&mq->fifo, (unsigned char *)&msg, | ||
| 128 | sizeof(msg)); | ||
| 129 | WARN_ON(ret != sizeof(msg)); | ||
| 130 | |||
| 131 | mbox_fifo_write(mbox, msg); | ||
| 124 | } | 132 | } |
| 125 | } | 133 | } |
| 126 | 134 | ||
| @@ -131,36 +139,21 @@ static void mbox_rx_work(struct work_struct *work) | |||
| 131 | { | 139 | { |
| 132 | struct omap_mbox_queue *mq = | 140 | struct omap_mbox_queue *mq = |
| 133 | container_of(work, struct omap_mbox_queue, work); | 141 | container_of(work, struct omap_mbox_queue, work); |
| 134 | struct omap_mbox *mbox = mq->queue->queuedata; | ||
| 135 | struct request_queue *q = mbox->rxq->queue; | ||
| 136 | struct request *rq; | ||
| 137 | mbox_msg_t msg; | 142 | mbox_msg_t msg; |
| 138 | unsigned long flags; | 143 | int len; |
| 139 | 144 | ||
| 140 | while (1) { | 145 | while (kfifo_len(&mq->fifo) >= sizeof(msg)) { |
| 141 | spin_lock_irqsave(q->queue_lock, flags); | 146 | len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); |
| 142 | rq = blk_fetch_request(q); | 147 | WARN_ON(len != sizeof(msg)); |
| 143 | spin_unlock_irqrestore(q->queue_lock, flags); | ||
| 144 | if (!rq) | ||
| 145 | break; | ||
| 146 | 148 | ||
| 147 | msg = (mbox_msg_t)rq->special; | 149 | if (mq->callback) |
| 148 | blk_end_request_all(rq, 0); | 150 | mq->callback((void *)msg); |
| 149 | mbox->rxq->callback((void *)msg); | ||
| 150 | } | 151 | } |
| 151 | } | 152 | } |
| 152 | 153 | ||
| 153 | /* | 154 | /* |
| 154 | * Mailbox interrupt handler | 155 | * Mailbox interrupt handler |
| 155 | */ | 156 | */ |
| 156 | static void mbox_txq_fn(struct request_queue *q) | ||
| 157 | { | ||
| 158 | } | ||
| 159 | |||
| 160 | static void mbox_rxq_fn(struct request_queue *q) | ||
| 161 | { | ||
| 162 | } | ||
| 163 | |||
| 164 | static void __mbox_tx_interrupt(struct omap_mbox *mbox) | 157 | static void __mbox_tx_interrupt(struct omap_mbox *mbox) |
| 165 | { | 158 | { |
| 166 | omap_mbox_disable_irq(mbox, IRQ_TX); | 159 | omap_mbox_disable_irq(mbox, IRQ_TX); |
| @@ -170,19 +163,22 @@ static void __mbox_tx_interrupt(struct omap_mbox *mbox) | |||
| 170 | 163 | ||
| 171 | static void __mbox_rx_interrupt(struct omap_mbox *mbox) | 164 | static void __mbox_rx_interrupt(struct omap_mbox *mbox) |
| 172 | { | 165 | { |
| 173 | struct request *rq; | 166 | struct omap_mbox_queue *mq = mbox->rxq; |
| 174 | mbox_msg_t msg; | 167 | mbox_msg_t msg; |
| 175 | struct request_queue *q = mbox->rxq->queue; | 168 | int len; |
| 176 | 169 | ||
| 177 | while (!mbox_fifo_empty(mbox)) { | 170 | while (!mbox_fifo_empty(mbox)) { |
| 178 | rq = blk_get_request(q, WRITE, GFP_ATOMIC); | 171 | if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) { |
| 179 | if (unlikely(!rq)) | 172 | omap_mbox_disable_irq(mbox, IRQ_RX); |
| 173 | rq_full = true; | ||
| 180 | goto nomem; | 174 | goto nomem; |
| 175 | } | ||
| 181 | 176 | ||
| 182 | msg = mbox_fifo_read(mbox); | 177 | msg = mbox_fifo_read(mbox); |
| 183 | 178 | ||
| 179 | len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); | ||
| 180 | WARN_ON(len != sizeof(msg)); | ||
| 184 | 181 | ||
| 185 | blk_insert_request(q, rq, 0, (void *)msg); | ||
| 186 | if (mbox->ops->type == OMAP_MBOX_TYPE1) | 182 | if (mbox->ops->type == OMAP_MBOX_TYPE1) |
| 187 | break; | 183 | break; |
| 188 | } | 184 | } |
| @@ -207,11 +203,9 @@ static irqreturn_t mbox_interrupt(int irq, void *p) | |||
| 207 | } | 203 | } |
| 208 | 204 | ||
| 209 | static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, | 205 | static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, |
| 210 | request_fn_proc *proc, | ||
| 211 | void (*work) (struct work_struct *), | 206 | void (*work) (struct work_struct *), |
| 212 | void (*tasklet)(unsigned long)) | 207 | void (*tasklet)(unsigned long)) |
| 213 | { | 208 | { |
| 214 | struct request_queue *q; | ||
| 215 | struct omap_mbox_queue *mq; | 209 | struct omap_mbox_queue *mq; |
| 216 | 210 | ||
| 217 | mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL); | 211 | mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL); |
| @@ -220,11 +214,8 @@ static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, | |||
| 220 | 214 | ||
| 221 | spin_lock_init(&mq->lock); | 215 | spin_lock_init(&mq->lock); |
| 222 | 216 | ||
| 223 | q = blk_init_queue(proc, &mq->lock); | 217 | if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL)) |
| 224 | if (!q) | ||
| 225 | goto error; | 218 | goto error; |
| 226 | q->queuedata = mbox; | ||
| 227 | mq->queue = q; | ||
| 228 | 219 | ||
| 229 | if (work) | 220 | if (work) |
| 230 | INIT_WORK(&mq->work, work); | 221 | INIT_WORK(&mq->work, work); |
| @@ -239,7 +230,7 @@ error: | |||
| 239 | 230 | ||
| 240 | static void mbox_queue_free(struct omap_mbox_queue *q) | 231 | static void mbox_queue_free(struct omap_mbox_queue *q) |
| 241 | { | 232 | { |
| 242 | blk_cleanup_queue(q->queue); | 233 | kfifo_free(&q->fifo); |
| 243 | kfree(q); | 234 | kfree(q); |
| 244 | } | 235 | } |
| 245 | 236 | ||
| @@ -248,35 +239,35 @@ static int omap_mbox_startup(struct omap_mbox *mbox) | |||
| 248 | int ret = 0; | 239 | int ret = 0; |
| 249 | struct omap_mbox_queue *mq; | 240 | struct omap_mbox_queue *mq; |
| 250 | 241 | ||
| 251 | if (likely(mbox->ops->startup)) { | 242 | if (mbox->ops->startup) { |
| 252 | write_lock(&mboxes_lock); | 243 | mutex_lock(&mbox_configured_lock); |
| 253 | if (!mbox_configured) | 244 | if (!mbox_configured) |
| 254 | ret = mbox->ops->startup(mbox); | 245 | ret = mbox->ops->startup(mbox); |
| 255 | 246 | ||
| 256 | if (unlikely(ret)) { | 247 | if (ret) { |
| 257 | write_unlock(&mboxes_lock); | 248 | mutex_unlock(&mbox_configured_lock); |
| 258 | return ret; | 249 | return ret; |
| 259 | } | 250 | } |
| 260 | mbox_configured++; | 251 | mbox_configured++; |
| 261 | write_unlock(&mboxes_lock); | 252 | mutex_unlock(&mbox_configured_lock); |
| 262 | } | 253 | } |
| 263 | 254 | ||
| 264 | ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, | 255 | ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, |
| 265 | mbox->name, mbox); | 256 | mbox->name, mbox); |
| 266 | if (unlikely(ret)) { | 257 | if (ret) { |
| 267 | printk(KERN_ERR | 258 | printk(KERN_ERR |
| 268 | "failed to register mailbox interrupt:%d\n", ret); | 259 | "failed to register mailbox interrupt:%d\n", ret); |
| 269 | goto fail_request_irq; | 260 | goto fail_request_irq; |
| 270 | } | 261 | } |
| 271 | 262 | ||
| 272 | mq = mbox_queue_alloc(mbox, mbox_txq_fn, NULL, mbox_tx_tasklet); | 263 | mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet); |
| 273 | if (!mq) { | 264 | if (!mq) { |
| 274 | ret = -ENOMEM; | 265 | ret = -ENOMEM; |
| 275 | goto fail_alloc_txq; | 266 | goto fail_alloc_txq; |
| 276 | } | 267 | } |
| 277 | mbox->txq = mq; | 268 | mbox->txq = mq; |
| 278 | 269 | ||
| 279 | mq = mbox_queue_alloc(mbox, mbox_rxq_fn, mbox_rx_work, NULL); | 270 | mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL); |
| 280 | if (!mq) { | 271 | if (!mq) { |
| 281 | ret = -ENOMEM; | 272 | ret = -ENOMEM; |
| 282 | goto fail_alloc_rxq; | 273 | goto fail_alloc_rxq; |
| @@ -290,7 +281,7 @@ static int omap_mbox_startup(struct omap_mbox *mbox) | |||
| 290 | fail_alloc_txq: | 281 | fail_alloc_txq: |
| 291 | free_irq(mbox->irq, mbox); | 282 | free_irq(mbox->irq, mbox); |
| 292 | fail_request_irq: | 283 | fail_request_irq: |
| 293 | if (unlikely(mbox->ops->shutdown)) | 284 | if (mbox->ops->shutdown) |
| 294 | mbox->ops->shutdown(mbox); | 285 | mbox->ops->shutdown(mbox); |
| 295 | 286 | ||
| 296 | return ret; | 287 | return ret; |
| @@ -298,31 +289,20 @@ static int omap_mbox_startup(struct omap_mbox *mbox) | |||
| 298 | 289 | ||
| 299 | static void omap_mbox_fini(struct omap_mbox *mbox) | 290 | static void omap_mbox_fini(struct omap_mbox *mbox) |
| 300 | { | 291 | { |
| 292 | free_irq(mbox->irq, mbox); | ||
| 293 | tasklet_kill(&mbox->txq->tasklet); | ||
| 294 | flush_work(&mbox->rxq->work); | ||
| 301 | mbox_queue_free(mbox->txq); | 295 | mbox_queue_free(mbox->txq); |
| 302 | mbox_queue_free(mbox->rxq); | 296 | mbox_queue_free(mbox->rxq); |
| 303 | 297 | ||
| 304 | free_irq(mbox->irq, mbox); | 298 | if (mbox->ops->shutdown) { |
| 305 | 299 | mutex_lock(&mbox_configured_lock); | |
| 306 | if (unlikely(mbox->ops->shutdown)) { | ||
| 307 | write_lock(&mboxes_lock); | ||
| 308 | if (mbox_configured > 0) | 300 | if (mbox_configured > 0) |
| 309 | mbox_configured--; | 301 | mbox_configured--; |
| 310 | if (!mbox_configured) | 302 | if (!mbox_configured) |
| 311 | mbox->ops->shutdown(mbox); | 303 | mbox->ops->shutdown(mbox); |
| 312 | write_unlock(&mboxes_lock); | 304 | mutex_unlock(&mbox_configured_lock); |
| 313 | } | ||
| 314 | } | ||
| 315 | |||
| 316 | static struct omap_mbox **find_mboxes(const char *name) | ||
| 317 | { | ||
| 318 | struct omap_mbox **p; | ||
| 319 | |||
| 320 | for (p = &mboxes; *p; p = &(*p)->next) { | ||
| 321 | if (strcmp((*p)->name, name) == 0) | ||
| 322 | break; | ||
| 323 | } | 305 | } |
| 324 | |||
| 325 | return p; | ||
| 326 | } | 306 | } |
| 327 | 307 | ||
| 328 | struct omap_mbox *omap_mbox_get(const char *name) | 308 | struct omap_mbox *omap_mbox_get(const char *name) |
| @@ -330,14 +310,15 @@ struct omap_mbox *omap_mbox_get(const char *name) | |||
| 330 | struct omap_mbox *mbox; | 310 | struct omap_mbox *mbox; |
| 331 | int ret; | 311 | int ret; |
| 332 | 312 | ||
| 333 | read_lock(&mboxes_lock); | 313 | if (!mboxes) |
| 334 | mbox = *(find_mboxes(name)); | 314 | return ERR_PTR(-EINVAL); |
| 335 | if (mbox == NULL) { | ||
| 336 | read_unlock(&mboxes_lock); | ||
| 337 | return ERR_PTR(-ENOENT); | ||
| 338 | } | ||
| 339 | 315 | ||
| 340 | read_unlock(&mboxes_lock); | 316 | for (mbox = *mboxes; mbox; mbox++) |
| 317 | if (!strcmp(mbox->name, name)) | ||
| 318 | break; | ||
| 319 | |||
| 320 | if (!mbox) | ||
| 321 | return ERR_PTR(-ENOENT); | ||
| 341 | 322 | ||
| 342 | ret = omap_mbox_startup(mbox); | 323 | ret = omap_mbox_startup(mbox); |
| 343 | if (ret) | 324 | if (ret) |
| @@ -353,70 +334,77 @@ void omap_mbox_put(struct omap_mbox *mbox) | |||
| 353 | } | 334 | } |
| 354 | EXPORT_SYMBOL(omap_mbox_put); | 335 | EXPORT_SYMBOL(omap_mbox_put); |
| 355 | 336 | ||
| 356 | int omap_mbox_register(struct device *parent, struct omap_mbox *mbox) | 337 | static struct class omap_mbox_class = { .name = "mbox", }; |
| 338 | |||
| 339 | int omap_mbox_register(struct device *parent, struct omap_mbox **list) | ||
| 357 | { | 340 | { |
| 358 | int ret = 0; | 341 | int ret; |
| 359 | struct omap_mbox **tmp; | 342 | int i; |
| 360 | 343 | ||
| 361 | if (!mbox) | 344 | mboxes = list; |
| 345 | if (!mboxes) | ||
| 362 | return -EINVAL; | 346 | return -EINVAL; |
| 363 | if (mbox->next) | ||
| 364 | return -EBUSY; | ||
| 365 | |||
| 366 | write_lock(&mboxes_lock); | ||
| 367 | tmp = find_mboxes(mbox->name); | ||
| 368 | if (*tmp) { | ||
| 369 | ret = -EBUSY; | ||
| 370 | write_unlock(&mboxes_lock); | ||
| 371 | goto err_find; | ||
| 372 | } | ||
| 373 | *tmp = mbox; | ||
| 374 | write_unlock(&mboxes_lock); | ||
| 375 | 347 | ||
| 348 | for (i = 0; mboxes[i]; i++) { | ||
| 349 | struct omap_mbox *mbox = mboxes[i]; | ||
| 350 | mbox->dev = device_create(&omap_mbox_class, | ||
| 351 | parent, 0, mbox, "%s", mbox->name); | ||
| 352 | if (IS_ERR(mbox->dev)) { | ||
| 353 | ret = PTR_ERR(mbox->dev); | ||
| 354 | goto err_out; | ||
| 355 | } | ||
| 356 | } | ||
| 376 | return 0; | 357 | return 0; |
| 377 | 358 | ||
| 378 | err_find: | 359 | err_out: |
| 360 | while (i--) | ||
| 361 | device_unregister(mboxes[i]->dev); | ||
| 379 | return ret; | 362 | return ret; |
| 380 | } | 363 | } |
| 381 | EXPORT_SYMBOL(omap_mbox_register); | 364 | EXPORT_SYMBOL(omap_mbox_register); |
| 382 | 365 | ||
| 383 | int omap_mbox_unregister(struct omap_mbox *mbox) | 366 | int omap_mbox_unregister(void) |
| 384 | { | 367 | { |
| 385 | struct omap_mbox **tmp; | 368 | int i; |
| 386 | 369 | ||
| 387 | write_lock(&mboxes_lock); | 370 | if (!mboxes) |
| 388 | tmp = &mboxes; | 371 | return -EINVAL; |
| 389 | while (*tmp) { | ||
| 390 | if (mbox == *tmp) { | ||
| 391 | *tmp = mbox->next; | ||
| 392 | mbox->next = NULL; | ||
| 393 | write_unlock(&mboxes_lock); | ||
| 394 | return 0; | ||
| 395 | } | ||
| 396 | tmp = &(*tmp)->next; | ||
| 397 | } | ||
| 398 | write_unlock(&mboxes_lock); | ||
| 399 | 372 | ||
| 400 | return -EINVAL; | 373 | for (i = 0; mboxes[i]; i++) |
| 374 | device_unregister(mboxes[i]->dev); | ||
| 375 | mboxes = NULL; | ||
| 376 | return 0; | ||
| 401 | } | 377 | } |
| 402 | EXPORT_SYMBOL(omap_mbox_unregister); | 378 | EXPORT_SYMBOL(omap_mbox_unregister); |
| 403 | 379 | ||
| 404 | static int __init omap_mbox_init(void) | 380 | static int __init omap_mbox_init(void) |
| 405 | { | 381 | { |
| 382 | int err; | ||
| 383 | |||
| 384 | err = class_register(&omap_mbox_class); | ||
| 385 | if (err) | ||
| 386 | return err; | ||
| 387 | |||
| 406 | mboxd = create_workqueue("mboxd"); | 388 | mboxd = create_workqueue("mboxd"); |
| 407 | if (!mboxd) | 389 | if (!mboxd) |
| 408 | return -ENOMEM; | 390 | return -ENOMEM; |
| 409 | 391 | ||
| 392 | /* kfifo size sanity check: alignment and minimal size */ | ||
| 393 | mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t)); | ||
| 394 | mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(mbox_msg_t)); | ||
| 395 | |||
| 410 | return 0; | 396 | return 0; |
| 411 | } | 397 | } |
| 412 | module_init(omap_mbox_init); | 398 | subsys_initcall(omap_mbox_init); |
| 413 | 399 | ||
| 414 | static void __exit omap_mbox_exit(void) | 400 | static void __exit omap_mbox_exit(void) |
| 415 | { | 401 | { |
| 416 | destroy_workqueue(mboxd); | 402 | destroy_workqueue(mboxd); |
| 403 | class_unregister(&omap_mbox_class); | ||
| 417 | } | 404 | } |
| 418 | module_exit(omap_mbox_exit); | 405 | module_exit(omap_mbox_exit); |
| 419 | 406 | ||
| 420 | MODULE_LICENSE("GPL v2"); | 407 | MODULE_LICENSE("GPL v2"); |
| 421 | MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging"); | 408 | MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging"); |
| 422 | MODULE_AUTHOR("Toshihiro Kobayashi and Hiroshi DOYU"); | 409 | MODULE_AUTHOR("Toshihiro Kobayashi"); |
| 410 | MODULE_AUTHOR("Hiroshi DOYU"); | ||
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c index 06703635ace1..0d4aa0d5876c 100644 --- a/arch/arm/plat-omap/mux.c +++ b/arch/arm/plat-omap/mux.c | |||
| @@ -54,7 +54,7 @@ int __init_or_module omap_cfg_reg(const unsigned long index) | |||
| 54 | { | 54 | { |
| 55 | struct pin_config *reg; | 55 | struct pin_config *reg; |
| 56 | 56 | ||
| 57 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | 57 | if (!cpu_class_is_omap1()) { |
| 58 | printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n", | 58 | printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n", |
| 59 | index); | 59 | index); |
| 60 | WARN_ON(1); | 60 | WARN_ON(1); |
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c index 186bca82cfab..e129ce80c53b 100644 --- a/arch/arm/plat-omap/omap-pm-noop.c +++ b/arch/arm/plat-omap/omap-pm-noop.c | |||
| @@ -34,11 +34,11 @@ struct omap_opp *l3_opps; | |||
| 34 | * Device-driver-originated constraints (via board-*.c files) | 34 | * Device-driver-originated constraints (via board-*.c files) |
| 35 | */ | 35 | */ |
| 36 | 36 | ||
| 37 | void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t) | 37 | int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t) |
| 38 | { | 38 | { |
| 39 | if (!dev || t < -1) { | 39 | if (!dev || t < -1) { |
| 40 | WARN_ON(1); | 40 | WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); |
| 41 | return; | 41 | return -EINVAL; |
| 42 | }; | 42 | }; |
| 43 | 43 | ||
| 44 | if (t == -1) | 44 | if (t == -1) |
| @@ -58,14 +58,16 @@ void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t) | |||
| 58 | * | 58 | * |
| 59 | * TI CDP code can call constraint_set here. | 59 | * TI CDP code can call constraint_set here. |
| 60 | */ | 60 | */ |
| 61 | |||
| 62 | return 0; | ||
| 61 | } | 63 | } |
| 62 | 64 | ||
| 63 | void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r) | 65 | int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r) |
| 64 | { | 66 | { |
| 65 | if (!dev || (agent_id != OCP_INITIATOR_AGENT && | 67 | if (!dev || (agent_id != OCP_INITIATOR_AGENT && |
| 66 | agent_id != OCP_TARGET_AGENT)) { | 68 | agent_id != OCP_TARGET_AGENT)) { |
| 67 | WARN_ON(1); | 69 | WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); |
| 68 | return; | 70 | return -EINVAL; |
| 69 | }; | 71 | }; |
| 70 | 72 | ||
| 71 | if (r == 0) | 73 | if (r == 0) |
| @@ -83,13 +85,16 @@ void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r) | |||
| 83 | * | 85 | * |
| 84 | * TI CDP code can call constraint_set here on the VDD2 OPP. | 86 | * TI CDP code can call constraint_set here on the VDD2 OPP. |
| 85 | */ | 87 | */ |
| 88 | |||
| 89 | return 0; | ||
| 86 | } | 90 | } |
| 87 | 91 | ||
| 88 | void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t) | 92 | int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev, |
| 93 | long t) | ||
| 89 | { | 94 | { |
| 90 | if (!dev || t < -1) { | 95 | if (!req_dev || !dev || t < -1) { |
| 91 | WARN_ON(1); | 96 | WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); |
| 92 | return; | 97 | return -EINVAL; |
| 93 | }; | 98 | }; |
| 94 | 99 | ||
| 95 | if (t == -1) | 100 | if (t == -1) |
| @@ -111,13 +116,15 @@ void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t) | |||
| 111 | * | 116 | * |
| 112 | * TI CDP code can call constraint_set here. | 117 | * TI CDP code can call constraint_set here. |
| 113 | */ | 118 | */ |
| 119 | |||
| 120 | return 0; | ||
| 114 | } | 121 | } |
| 115 | 122 | ||
| 116 | void omap_pm_set_max_sdma_lat(struct device *dev, long t) | 123 | int omap_pm_set_max_sdma_lat(struct device *dev, long t) |
| 117 | { | 124 | { |
| 118 | if (!dev || t < -1) { | 125 | if (!dev || t < -1) { |
| 119 | WARN_ON(1); | 126 | WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); |
| 120 | return; | 127 | return -EINVAL; |
| 121 | }; | 128 | }; |
| 122 | 129 | ||
| 123 | if (t == -1) | 130 | if (t == -1) |
| @@ -139,8 +146,36 @@ void omap_pm_set_max_sdma_lat(struct device *dev, long t) | |||
| 139 | * TI CDP code can call constraint_set here. | 146 | * TI CDP code can call constraint_set here. |
| 140 | */ | 147 | */ |
| 141 | 148 | ||
| 149 | return 0; | ||
| 142 | } | 150 | } |
| 143 | 151 | ||
| 152 | int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r) | ||
| 153 | { | ||
| 154 | if (!dev || !c || r < 0) { | ||
| 155 | WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); | ||
| 156 | return -EINVAL; | ||
| 157 | } | ||
| 158 | |||
| 159 | if (r == 0) | ||
| 160 | pr_debug("OMAP PM: remove min clk rate constraint: " | ||
| 161 | "dev %s\n", dev_name(dev)); | ||
| 162 | else | ||
| 163 | pr_debug("OMAP PM: add min clk rate constraint: " | ||
| 164 | "dev %s, rate = %ld Hz\n", dev_name(dev), r); | ||
| 165 | |||
| 166 | /* | ||
| 167 | * Code in a real implementation should keep track of these | ||
| 168 | * constraints on the clock, and determine the highest minimum | ||
| 169 | * clock rate. It should iterate over each OPP and determine | ||
| 170 | * whether the OPP will result in a clock rate that would | ||
| 171 | * satisfy this constraint (and any other PM constraint in effect | ||
| 172 | * at that time). Once it finds the lowest-voltage OPP that | ||
| 173 | * meets those conditions, it should switch to it, or return | ||
| 174 | * an error if the code is not capable of doing so. | ||
| 175 | */ | ||
| 176 | |||
| 177 | return 0; | ||
| 178 | } | ||
| 144 | 179 | ||
| 145 | /* | 180 | /* |
| 146 | * DSP Bridge-specific constraints | 181 | * DSP Bridge-specific constraints |
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index f899603051ac..d2b160942ccc 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * omap_device implementation | 2 | * omap_device implementation |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
| 5 | * Paul Walmsley, Kevin Hilman | 5 | * Paul Walmsley, Kevin Hilman |
| 6 | * | 6 | * |
| 7 | * Developed in collaboration with (alphabetical order): Benoit | 7 | * Developed in collaboration with (alphabetical order): Benoit |
| @@ -90,8 +90,11 @@ | |||
| 90 | #define USE_WAKEUP_LAT 0 | 90 | #define USE_WAKEUP_LAT 0 |
| 91 | #define IGNORE_WAKEUP_LAT 1 | 91 | #define IGNORE_WAKEUP_LAT 1 |
| 92 | 92 | ||
| 93 | 93 | /* | |
| 94 | #define OMAP_DEVICE_MAGIC 0xf00dcafe | 94 | * OMAP_DEVICE_MAGIC: used to determine whether a struct omap_device |
| 95 | * obtained via container_of() is in fact a struct omap_device | ||
| 96 | */ | ||
| 97 | #define OMAP_DEVICE_MAGIC 0xf00dcafe | ||
| 95 | 98 | ||
| 96 | /* Private functions */ | 99 | /* Private functions */ |
| 97 | 100 | ||
| @@ -359,7 +362,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, | |||
| 359 | struct omap_device *od; | 362 | struct omap_device *od; |
| 360 | char *pdev_name2; | 363 | char *pdev_name2; |
| 361 | struct resource *res = NULL; | 364 | struct resource *res = NULL; |
| 362 | int res_count; | 365 | int i, res_count; |
| 363 | struct omap_hwmod **hwmods; | 366 | struct omap_hwmod **hwmods; |
| 364 | 367 | ||
| 365 | if (!ohs || oh_cnt == 0 || !pdev_name) | 368 | if (!ohs || oh_cnt == 0 || !pdev_name) |
| @@ -404,7 +407,9 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, | |||
| 404 | od->pdev.num_resources = res_count; | 407 | od->pdev.num_resources = res_count; |
| 405 | od->pdev.resource = res; | 408 | od->pdev.resource = res; |
| 406 | 409 | ||
| 407 | platform_device_add_data(&od->pdev, pdata, pdata_len); | 410 | ret = platform_device_add_data(&od->pdev, pdata, pdata_len); |
| 411 | if (ret) | ||
| 412 | goto odbs_exit4; | ||
| 408 | 413 | ||
| 409 | od->pm_lats = pm_lats; | 414 | od->pm_lats = pm_lats; |
| 410 | od->pm_lats_cnt = pm_lats_cnt; | 415 | od->pm_lats_cnt = pm_lats_cnt; |
| @@ -416,6 +421,9 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, | |||
| 416 | else | 421 | else |
| 417 | ret = omap_device_register(od); | 422 | ret = omap_device_register(od); |
| 418 | 423 | ||
| 424 | for (i = 0; i < oh_cnt; i++) | ||
| 425 | hwmods[i]->od = od; | ||
| 426 | |||
| 419 | if (ret) | 427 | if (ret) |
| 420 | goto odbs_exit4; | 428 | goto odbs_exit4; |
| 421 | 429 | ||
| @@ -652,6 +660,25 @@ struct powerdomain *omap_device_get_pwrdm(struct omap_device *od) | |||
| 652 | return omap_hwmod_get_pwrdm(od->hwmods[0]); | 660 | return omap_hwmod_get_pwrdm(od->hwmods[0]); |
| 653 | } | 661 | } |
| 654 | 662 | ||
| 663 | /** | ||
| 664 | * omap_device_get_mpu_rt_va - return the MPU's virtual addr for the hwmod base | ||
| 665 | * @od: struct omap_device * | ||
| 666 | * | ||
| 667 | * Return the MPU's virtual address for the base of the hwmod, from | ||
| 668 | * the ioremap() that the hwmod code does. Only valid if there is one | ||
| 669 | * hwmod associated with this device. Returns NULL if there are zero | ||
| 670 | * or more than one hwmods associated with this omap_device; | ||
| 671 | * otherwise, passes along the return value from | ||
| 672 | * omap_hwmod_get_mpu_rt_va(). | ||
| 673 | */ | ||
| 674 | void __iomem *omap_device_get_rt_va(struct omap_device *od) | ||
| 675 | { | ||
| 676 | if (od->hwmods_cnt != 1) | ||
| 677 | return NULL; | ||
| 678 | |||
| 679 | return omap_hwmod_get_mpu_rt_va(od->hwmods[0]); | ||
| 680 | } | ||
| 681 | |||
| 655 | /* | 682 | /* |
| 656 | * Public functions intended for use in omap_device_pm_latency | 683 | * Public functions intended for use in omap_device_pm_latency |
| 657 | * .activate_func and .deactivate_func function pointers | 684 | * .activate_func and .deactivate_func function pointers |
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c index d3bf17cd36f3..f3570884883e 100644 --- a/arch/arm/plat-omap/usb.c +++ b/arch/arm/plat-omap/usb.c | |||
| @@ -22,524 +22,13 @@ | |||
| 22 | 22 | ||
| 23 | #include <linux/module.h> | 23 | #include <linux/module.h> |
| 24 | #include <linux/kernel.h> | 24 | #include <linux/kernel.h> |
| 25 | #include <linux/types.h> | ||
| 26 | #include <linux/errno.h> | ||
| 27 | #include <linux/init.h> | 25 | #include <linux/init.h> |
| 28 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
| 29 | #include <linux/usb/otg.h> | ||
| 30 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 31 | 28 | ||
| 32 | #include <asm/irq.h> | ||
| 33 | #include <asm/system.h> | ||
| 34 | #include <mach/hardware.h> | ||
| 35 | |||
| 36 | #include <plat/control.h> | ||
| 37 | #include <plat/mux.h> | ||
| 38 | #include <plat/usb.h> | 29 | #include <plat/usb.h> |
| 39 | #include <plat/board.h> | 30 | #include <plat/board.h> |
| 40 | 31 | ||
| 41 | #ifdef CONFIG_ARCH_OMAP1 | ||
| 42 | |||
| 43 | #define INT_USB_IRQ_GEN IH2_BASE + 20 | ||
| 44 | #define INT_USB_IRQ_NISO IH2_BASE + 30 | ||
| 45 | #define INT_USB_IRQ_ISO IH2_BASE + 29 | ||
| 46 | #define INT_USB_IRQ_HGEN INT_USB_HHC_1 | ||
| 47 | #define INT_USB_IRQ_OTG IH2_BASE + 8 | ||
| 48 | |||
| 49 | #else | ||
| 50 | |||
| 51 | #define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN | ||
| 52 | #define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO | ||
| 53 | #define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO | ||
| 54 | #define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN | ||
| 55 | #define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG | ||
| 56 | |||
| 57 | #endif | ||
| 58 | |||
| 59 | |||
| 60 | /* These routines should handle the standard chip-specific modes | ||
| 61 | * for usb0/1/2 ports, covering basic mux and transceiver setup. | ||
| 62 | * | ||
| 63 | * Some board-*.c files will need to set up additional mux options, | ||
| 64 | * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup. | ||
| 65 | */ | ||
| 66 | |||
| 67 | /* TESTED ON: | ||
| 68 | * - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables | ||
| 69 | * - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables | ||
| 70 | * - 5912 OSK UDC, with *nonstandard* A-to-A cable | ||
| 71 | * - 1510 Innovator UDC with bundled usb0 cable | ||
| 72 | * - 1510 Innovator OHCI with bundled usb1/usb2 cable | ||
| 73 | * - 1510 Innovator OHCI with custom usb0 cable, feeding 5V VBUS | ||
| 74 | * - 1710 custom development board using alternate pin group | ||
| 75 | * - 1710 H3 (with usb1 mini-AB) using standard Mini-B or OTG cables | ||
| 76 | */ | ||
| 77 | |||
| 78 | /*-------------------------------------------------------------------------*/ | ||
| 79 | |||
| 80 | #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX) | ||
| 81 | |||
| 82 | static void omap2_usb_devconf_clear(u8 port, u32 mask) | ||
| 83 | { | ||
| 84 | u32 r; | ||
| 85 | |||
| 86 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 87 | r &= ~USBTXWRMODEI(port, mask); | ||
| 88 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 89 | } | ||
| 90 | |||
| 91 | static void omap2_usb_devconf_set(u8 port, u32 mask) | ||
| 92 | { | ||
| 93 | u32 r; | ||
| 94 | |||
| 95 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 96 | r |= USBTXWRMODEI(port, mask); | ||
| 97 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 98 | } | ||
| 99 | |||
| 100 | static void omap2_usb2_disable_5pinbitll(void) | ||
| 101 | { | ||
| 102 | u32 r; | ||
| 103 | |||
| 104 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 105 | r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI); | ||
| 106 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 107 | } | ||
| 108 | |||
| 109 | static void omap2_usb2_enable_5pinunitll(void) | ||
| 110 | { | ||
| 111 | u32 r; | ||
| 112 | |||
| 113 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 114 | r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI; | ||
| 115 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 116 | } | ||
| 117 | |||
| 118 | static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) | ||
| 119 | { | ||
| 120 | u32 syscon1 = 0; | ||
| 121 | |||
| 122 | if (cpu_is_omap24xx()) | ||
| 123 | omap2_usb_devconf_clear(0, USB_BIDIR_TLL); | ||
| 124 | |||
| 125 | if (nwires == 0) { | ||
| 126 | if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { | ||
| 127 | u32 l; | ||
| 128 | |||
| 129 | /* pulldown D+/D- */ | ||
| 130 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 131 | l &= ~(3 << 1); | ||
| 132 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 133 | } | ||
| 134 | return 0; | ||
| 135 | } | ||
| 136 | |||
| 137 | if (is_device) { | ||
| 138 | if (cpu_is_omap24xx()) | ||
| 139 | omap_cfg_reg(J20_24XX_USB0_PUEN); | ||
| 140 | else if (cpu_is_omap7xx()) { | ||
| 141 | omap_cfg_reg(AA17_7XX_USB_DM); | ||
| 142 | omap_cfg_reg(W16_7XX_USB_PU_EN); | ||
| 143 | omap_cfg_reg(W17_7XX_USB_VBUSI); | ||
| 144 | omap_cfg_reg(W18_7XX_USB_DMCK_OUT); | ||
| 145 | omap_cfg_reg(W19_7XX_USB_DCRST); | ||
| 146 | } else | ||
| 147 | omap_cfg_reg(W4_USB_PUEN); | ||
| 148 | } | ||
| 149 | |||
| 150 | /* internal transceiver (unavailable on 17xx, 24xx) */ | ||
| 151 | if (!cpu_class_is_omap2() && nwires == 2) { | ||
| 152 | u32 l; | ||
| 153 | |||
| 154 | // omap_cfg_reg(P9_USB_DP); | ||
| 155 | // omap_cfg_reg(R8_USB_DM); | ||
| 156 | |||
| 157 | if (cpu_is_omap15xx()) { | ||
| 158 | /* This works on 1510-Innovator */ | ||
| 159 | return 0; | ||
| 160 | } | ||
| 161 | |||
| 162 | /* NOTES: | ||
| 163 | * - peripheral should configure VBUS detection! | ||
| 164 | * - only peripherals may use the internal D+/D- pulldowns | ||
| 165 | * - OTG support on this port not yet written | ||
| 166 | */ | ||
| 167 | |||
| 168 | /* Don't do this for omap7xx -- it causes USB to not work correctly */ | ||
| 169 | if (!cpu_is_omap7xx()) { | ||
| 170 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 171 | l &= ~(7 << 4); | ||
| 172 | if (!is_device) | ||
| 173 | l |= (3 << 1); | ||
| 174 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 175 | } | ||
| 176 | |||
| 177 | return 3 << 16; | ||
| 178 | } | ||
| 179 | |||
| 180 | /* alternate pin config, external transceiver */ | ||
| 181 | if (cpu_is_omap15xx()) { | ||
| 182 | printk(KERN_ERR "no usb0 alt pin config on 15xx\n"); | ||
| 183 | return 0; | ||
| 184 | } | ||
| 185 | |||
| 186 | if (cpu_is_omap24xx()) { | ||
| 187 | omap_cfg_reg(K18_24XX_USB0_DAT); | ||
| 188 | omap_cfg_reg(K19_24XX_USB0_TXEN); | ||
| 189 | omap_cfg_reg(J14_24XX_USB0_SE0); | ||
| 190 | if (nwires != 3) | ||
| 191 | omap_cfg_reg(J18_24XX_USB0_RCV); | ||
| 192 | } else { | ||
| 193 | omap_cfg_reg(V6_USB0_TXD); | ||
| 194 | omap_cfg_reg(W9_USB0_TXEN); | ||
| 195 | omap_cfg_reg(W5_USB0_SE0); | ||
| 196 | if (nwires != 3) | ||
| 197 | omap_cfg_reg(Y5_USB0_RCV); | ||
| 198 | } | ||
| 199 | |||
| 200 | /* NOTE: SPEED and SUSP aren't configured here. OTG hosts | ||
| 201 | * may be able to use I2C requests to set those bits along | ||
| 202 | * with VBUS switching and overcurrent detection. | ||
| 203 | */ | ||
| 204 | |||
| 205 | if (cpu_class_is_omap1() && nwires != 6) { | ||
| 206 | u32 l; | ||
| 207 | |||
| 208 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 209 | l &= ~CONF_USB2_UNI_R; | ||
| 210 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 211 | } | ||
| 212 | |||
| 213 | switch (nwires) { | ||
| 214 | case 3: | ||
| 215 | syscon1 = 2; | ||
| 216 | if (cpu_is_omap24xx()) | ||
| 217 | omap2_usb_devconf_set(0, USB_BIDIR); | ||
| 218 | break; | ||
| 219 | case 4: | ||
| 220 | syscon1 = 1; | ||
| 221 | if (cpu_is_omap24xx()) | ||
| 222 | omap2_usb_devconf_set(0, USB_BIDIR); | ||
| 223 | break; | ||
| 224 | case 6: | ||
| 225 | syscon1 = 3; | ||
| 226 | if (cpu_is_omap24xx()) { | ||
| 227 | omap_cfg_reg(J19_24XX_USB0_VP); | ||
| 228 | omap_cfg_reg(K20_24XX_USB0_VM); | ||
| 229 | omap2_usb_devconf_set(0, USB_UNIDIR); | ||
| 230 | } else { | ||
| 231 | u32 l; | ||
| 232 | |||
| 233 | omap_cfg_reg(AA9_USB0_VP); | ||
| 234 | omap_cfg_reg(R9_USB0_VM); | ||
| 235 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 236 | l |= CONF_USB2_UNI_R; | ||
| 237 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 238 | } | ||
| 239 | break; | ||
| 240 | default: | ||
| 241 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | ||
| 242 | 0, nwires); | ||
| 243 | } | ||
| 244 | return syscon1 << 16; | ||
| 245 | } | ||
| 246 | |||
| 247 | static u32 __init omap_usb1_init(unsigned nwires) | ||
| 248 | { | ||
| 249 | u32 syscon1 = 0; | ||
| 250 | |||
| 251 | if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) { | ||
| 252 | u32 l; | ||
| 253 | |||
| 254 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 255 | l &= ~CONF_USB1_UNI_R; | ||
| 256 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 257 | } | ||
| 258 | if (cpu_is_omap24xx()) | ||
| 259 | omap2_usb_devconf_clear(1, USB_BIDIR_TLL); | ||
| 260 | |||
| 261 | if (nwires == 0) | ||
| 262 | return 0; | ||
| 263 | |||
| 264 | /* external transceiver */ | ||
| 265 | if (cpu_class_is_omap1()) { | ||
| 266 | omap_cfg_reg(USB1_TXD); | ||
| 267 | omap_cfg_reg(USB1_TXEN); | ||
| 268 | if (nwires != 3) | ||
| 269 | omap_cfg_reg(USB1_RCV); | ||
| 270 | } | ||
| 271 | |||
| 272 | if (cpu_is_omap15xx()) { | ||
| 273 | omap_cfg_reg(USB1_SEO); | ||
| 274 | omap_cfg_reg(USB1_SPEED); | ||
| 275 | // SUSP | ||
| 276 | } else if (cpu_is_omap1610() || cpu_is_omap5912()) { | ||
| 277 | omap_cfg_reg(W13_1610_USB1_SE0); | ||
| 278 | omap_cfg_reg(R13_1610_USB1_SPEED); | ||
| 279 | // SUSP | ||
| 280 | } else if (cpu_is_omap1710()) { | ||
| 281 | omap_cfg_reg(R13_1710_USB1_SE0); | ||
| 282 | // SUSP | ||
| 283 | } else if (cpu_is_omap24xx()) { | ||
| 284 | /* NOTE: board-specific code must set up pin muxing for usb1, | ||
| 285 | * since each signal could come out on either of two balls. | ||
| 286 | */ | ||
| 287 | } else { | ||
| 288 | pr_debug("usb%d cpu unrecognized\n", 1); | ||
| 289 | return 0; | ||
| 290 | } | ||
| 291 | |||
| 292 | switch (nwires) { | ||
| 293 | case 2: | ||
| 294 | if (!cpu_is_omap24xx()) | ||
| 295 | goto bad; | ||
| 296 | /* NOTE: board-specific code must override this setting if | ||
| 297 | * this TLL link is not using DP/DM | ||
| 298 | */ | ||
| 299 | syscon1 = 1; | ||
| 300 | omap2_usb_devconf_set(1, USB_BIDIR_TLL); | ||
| 301 | break; | ||
| 302 | case 3: | ||
| 303 | syscon1 = 2; | ||
| 304 | if (cpu_is_omap24xx()) | ||
| 305 | omap2_usb_devconf_set(1, USB_BIDIR); | ||
| 306 | break; | ||
| 307 | case 4: | ||
| 308 | syscon1 = 1; | ||
| 309 | if (cpu_is_omap24xx()) | ||
| 310 | omap2_usb_devconf_set(1, USB_BIDIR); | ||
| 311 | break; | ||
| 312 | case 6: | ||
| 313 | if (cpu_is_omap24xx()) | ||
| 314 | goto bad; | ||
| 315 | syscon1 = 3; | ||
| 316 | omap_cfg_reg(USB1_VP); | ||
| 317 | omap_cfg_reg(USB1_VM); | ||
| 318 | if (!cpu_is_omap15xx()) { | ||
| 319 | u32 l; | ||
| 320 | |||
| 321 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 322 | l |= CONF_USB1_UNI_R; | ||
| 323 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 324 | } | ||
| 325 | break; | ||
| 326 | default: | ||
| 327 | bad: | ||
| 328 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | ||
| 329 | 1, nwires); | ||
| 330 | } | ||
| 331 | return syscon1 << 20; | ||
| 332 | } | ||
| 333 | |||
| 334 | static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup) | ||
| 335 | { | ||
| 336 | u32 syscon1 = 0; | ||
| 337 | |||
| 338 | if (cpu_is_omap24xx()) { | ||
| 339 | omap2_usb2_disable_5pinbitll(); | ||
| 340 | alt_pingroup = 0; | ||
| 341 | } | ||
| 342 | |||
| 343 | /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */ | ||
| 344 | if (alt_pingroup || nwires == 0) | ||
| 345 | return 0; | ||
| 346 | |||
| 347 | if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) { | ||
| 348 | u32 l; | ||
| 349 | |||
| 350 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 351 | l &= ~CONF_USB2_UNI_R; | ||
| 352 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 353 | } | ||
| 354 | |||
| 355 | /* external transceiver */ | ||
| 356 | if (cpu_is_omap15xx()) { | ||
| 357 | omap_cfg_reg(USB2_TXD); | ||
| 358 | omap_cfg_reg(USB2_TXEN); | ||
| 359 | omap_cfg_reg(USB2_SEO); | ||
| 360 | if (nwires != 3) | ||
| 361 | omap_cfg_reg(USB2_RCV); | ||
| 362 | /* there is no USB2_SPEED */ | ||
| 363 | } else if (cpu_is_omap16xx()) { | ||
| 364 | omap_cfg_reg(V6_USB2_TXD); | ||
| 365 | omap_cfg_reg(W9_USB2_TXEN); | ||
| 366 | omap_cfg_reg(W5_USB2_SE0); | ||
| 367 | if (nwires != 3) | ||
| 368 | omap_cfg_reg(Y5_USB2_RCV); | ||
| 369 | // FIXME omap_cfg_reg(USB2_SPEED); | ||
| 370 | } else if (cpu_is_omap24xx()) { | ||
| 371 | omap_cfg_reg(Y11_24XX_USB2_DAT); | ||
| 372 | omap_cfg_reg(AA10_24XX_USB2_SE0); | ||
| 373 | if (nwires > 2) | ||
| 374 | omap_cfg_reg(AA12_24XX_USB2_TXEN); | ||
| 375 | if (nwires > 3) | ||
| 376 | omap_cfg_reg(AA6_24XX_USB2_RCV); | ||
| 377 | } else { | ||
| 378 | pr_debug("usb%d cpu unrecognized\n", 1); | ||
| 379 | return 0; | ||
| 380 | } | ||
| 381 | // if (cpu_class_is_omap1()) omap_cfg_reg(USB2_SUSP); | ||
| 382 | |||
| 383 | switch (nwires) { | ||
| 384 | case 2: | ||
| 385 | if (!cpu_is_omap24xx()) | ||
| 386 | goto bad; | ||
| 387 | /* NOTE: board-specific code must override this setting if | ||
| 388 | * this TLL link is not using DP/DM | ||
| 389 | */ | ||
| 390 | syscon1 = 1; | ||
| 391 | omap2_usb_devconf_set(2, USB_BIDIR_TLL); | ||
| 392 | break; | ||
| 393 | case 3: | ||
| 394 | syscon1 = 2; | ||
| 395 | if (cpu_is_omap24xx()) | ||
| 396 | omap2_usb_devconf_set(2, USB_BIDIR); | ||
| 397 | break; | ||
| 398 | case 4: | ||
| 399 | syscon1 = 1; | ||
| 400 | if (cpu_is_omap24xx()) | ||
| 401 | omap2_usb_devconf_set(2, USB_BIDIR); | ||
| 402 | break; | ||
| 403 | case 5: | ||
| 404 | if (!cpu_is_omap24xx()) | ||
| 405 | goto bad; | ||
| 406 | omap_cfg_reg(AA4_24XX_USB2_TLLSE0); | ||
| 407 | /* NOTE: board-specific code must override this setting if | ||
| 408 | * this TLL link is not using DP/DM. Something must also | ||
| 409 | * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED} | ||
| 410 | */ | ||
| 411 | syscon1 = 3; | ||
| 412 | omap2_usb2_enable_5pinunitll(); | ||
| 413 | break; | ||
| 414 | case 6: | ||
| 415 | if (cpu_is_omap24xx()) | ||
| 416 | goto bad; | ||
| 417 | syscon1 = 3; | ||
| 418 | if (cpu_is_omap15xx()) { | ||
| 419 | omap_cfg_reg(USB2_VP); | ||
| 420 | omap_cfg_reg(USB2_VM); | ||
| 421 | } else { | ||
| 422 | u32 l; | ||
| 423 | |||
| 424 | omap_cfg_reg(AA9_USB2_VP); | ||
| 425 | omap_cfg_reg(R9_USB2_VM); | ||
| 426 | l = omap_readl(USB_TRANSCEIVER_CTRL); | ||
| 427 | l |= CONF_USB2_UNI_R; | ||
| 428 | omap_writel(l, USB_TRANSCEIVER_CTRL); | ||
| 429 | } | ||
| 430 | break; | ||
| 431 | default: | ||
| 432 | bad: | ||
| 433 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | ||
| 434 | 2, nwires); | ||
| 435 | } | ||
| 436 | return syscon1 << 24; | ||
| 437 | } | ||
| 438 | |||
| 439 | #endif | ||
| 440 | |||
| 441 | /*-------------------------------------------------------------------------*/ | ||
| 442 | |||
| 443 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 444 | |||
| 445 | static struct resource udc_resources[] = { | ||
| 446 | /* order is significant! */ | ||
| 447 | { /* registers */ | ||
| 448 | .start = UDC_BASE, | ||
| 449 | .end = UDC_BASE + 0xff, | ||
| 450 | .flags = IORESOURCE_MEM, | ||
| 451 | }, { /* general IRQ */ | ||
| 452 | .start = INT_USB_IRQ_GEN, | ||
| 453 | .flags = IORESOURCE_IRQ, | ||
| 454 | }, { /* PIO IRQ */ | ||
| 455 | .start = INT_USB_IRQ_NISO, | ||
| 456 | .flags = IORESOURCE_IRQ, | ||
| 457 | }, { /* SOF IRQ */ | ||
| 458 | .start = INT_USB_IRQ_ISO, | ||
| 459 | .flags = IORESOURCE_IRQ, | ||
| 460 | }, | ||
| 461 | }; | ||
| 462 | |||
| 463 | static u64 udc_dmamask = ~(u32)0; | ||
| 464 | |||
| 465 | static struct platform_device udc_device = { | ||
| 466 | .name = "omap_udc", | ||
| 467 | .id = -1, | ||
| 468 | .dev = { | ||
| 469 | .dma_mask = &udc_dmamask, | ||
| 470 | .coherent_dma_mask = 0xffffffff, | ||
| 471 | }, | ||
| 472 | .num_resources = ARRAY_SIZE(udc_resources), | ||
| 473 | .resource = udc_resources, | ||
| 474 | }; | ||
| 475 | |||
| 476 | #endif | ||
| 477 | |||
| 478 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 479 | |||
| 480 | /* The dmamask must be set for OHCI to work */ | ||
| 481 | static u64 ohci_dmamask = ~(u32)0; | ||
| 482 | |||
| 483 | static struct resource ohci_resources[] = { | ||
| 484 | { | ||
| 485 | .start = OMAP_OHCI_BASE, | ||
| 486 | .end = OMAP_OHCI_BASE + 0xff, | ||
| 487 | .flags = IORESOURCE_MEM, | ||
| 488 | }, | ||
| 489 | { | ||
| 490 | .start = INT_USB_IRQ_HGEN, | ||
| 491 | .flags = IORESOURCE_IRQ, | ||
| 492 | }, | ||
| 493 | }; | ||
| 494 | |||
| 495 | static struct platform_device ohci_device = { | ||
| 496 | .name = "ohci", | ||
| 497 | .id = -1, | ||
| 498 | .dev = { | ||
| 499 | .dma_mask = &ohci_dmamask, | ||
| 500 | .coherent_dma_mask = 0xffffffff, | ||
| 501 | }, | ||
| 502 | .num_resources = ARRAY_SIZE(ohci_resources), | ||
| 503 | .resource = ohci_resources, | ||
| 504 | }; | ||
| 505 | |||
| 506 | #endif | ||
| 507 | |||
| 508 | #if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG) | ||
| 509 | |||
| 510 | static struct resource otg_resources[] = { | ||
| 511 | /* order is significant! */ | ||
| 512 | { | ||
| 513 | .start = OTG_BASE, | ||
| 514 | .end = OTG_BASE + 0xff, | ||
| 515 | .flags = IORESOURCE_MEM, | ||
| 516 | }, { | ||
| 517 | .start = INT_USB_IRQ_OTG, | ||
| 518 | .flags = IORESOURCE_IRQ, | ||
| 519 | }, | ||
| 520 | }; | ||
| 521 | |||
| 522 | static struct platform_device otg_device = { | ||
| 523 | .name = "omap_otg", | ||
| 524 | .id = -1, | ||
| 525 | .num_resources = ARRAY_SIZE(otg_resources), | ||
| 526 | .resource = otg_resources, | ||
| 527 | }; | ||
| 528 | |||
| 529 | #endif | ||
| 530 | |||
| 531 | /*-------------------------------------------------------------------------*/ | ||
| 532 | |||
| 533 | // FIXME correct answer depends on hmc_mode, | ||
| 534 | // as does (on omap1) any nonzero value for config->otg port number | ||
| 535 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 536 | #define is_usb0_device(config) 1 | ||
| 537 | #else | ||
| 538 | #define is_usb0_device(config) 0 | ||
| 539 | #endif | ||
| 540 | |||
| 541 | /*-------------------------------------------------------------------------*/ | ||
| 542 | |||
| 543 | #ifdef CONFIG_ARCH_OMAP_OTG | 32 | #ifdef CONFIG_ARCH_OMAP_OTG |
| 544 | 33 | ||
| 545 | void __init | 34 | void __init |
| @@ -560,9 +49,9 @@ omap_otg_init(struct omap_usb_config *config) | |||
| 560 | /* pin muxing and transceiver pinouts */ | 49 | /* pin muxing and transceiver pinouts */ |
| 561 | if (config->pins[0] > 2) /* alt pingroup 2 */ | 50 | if (config->pins[0] > 2) /* alt pingroup 2 */ |
| 562 | alt_pingroup = 1; | 51 | alt_pingroup = 1; |
| 563 | syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config)); | 52 | syscon |= config->usb0_init(config->pins[0], is_usb0_device(config)); |
| 564 | syscon |= omap_usb1_init(config->pins[1]); | 53 | syscon |= config->usb1_init(config->pins[1]); |
| 565 | syscon |= omap_usb2_init(config->pins[2], alt_pingroup); | 54 | syscon |= config->usb2_init(config->pins[2], alt_pingroup); |
| 566 | pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); | 55 | pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); |
| 567 | omap_writel(syscon, OTG_SYSCON_1); | 56 | omap_writel(syscon, OTG_SYSCON_1); |
| 568 | 57 | ||
| @@ -610,15 +99,11 @@ omap_otg_init(struct omap_usb_config *config) | |||
| 610 | 99 | ||
| 611 | #ifdef CONFIG_USB_GADGET_OMAP | 100 | #ifdef CONFIG_USB_GADGET_OMAP |
| 612 | if (config->otg || config->register_dev) { | 101 | if (config->otg || config->register_dev) { |
| 102 | struct platform_device *udc_device = config->udc_device; | ||
| 103 | |||
| 613 | syscon &= ~DEV_IDLE_EN; | 104 | syscon &= ~DEV_IDLE_EN; |
| 614 | udc_device.dev.platform_data = config; | 105 | udc_device->dev.platform_data = config; |
| 615 | /* IRQ numbers for omap7xx */ | 106 | status = platform_device_register(udc_device); |
| 616 | if(cpu_is_omap7xx()) { | ||
| 617 | udc_resources[1].start = INT_7XX_USB_GENI; | ||
| 618 | udc_resources[2].start = INT_7XX_USB_NON_ISO; | ||
| 619 | udc_resources[3].start = INT_7XX_USB_ISO; | ||
| 620 | } | ||
| 621 | status = platform_device_register(&udc_device); | ||
| 622 | if (status) | 107 | if (status) |
| 623 | pr_debug("can't register UDC device, %d\n", status); | 108 | pr_debug("can't register UDC device, %d\n", status); |
| 624 | } | 109 | } |
| @@ -626,11 +111,11 @@ omap_otg_init(struct omap_usb_config *config) | |||
| 626 | 111 | ||
| 627 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | 112 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) |
| 628 | if (config->otg || config->register_host) { | 113 | if (config->otg || config->register_host) { |
| 114 | struct platform_device *ohci_device = config->ohci_device; | ||
| 115 | |||
| 629 | syscon &= ~HST_IDLE_EN; | 116 | syscon &= ~HST_IDLE_EN; |
| 630 | ohci_device.dev.platform_data = config; | 117 | ohci_device->dev.platform_data = config; |
| 631 | if (cpu_is_omap7xx()) | 118 | status = platform_device_register(ohci_device); |
| 632 | ohci_resources[1].start = INT_7XX_USB_HHC_1; | ||
| 633 | status = platform_device_register(&ohci_device); | ||
| 634 | if (status) | 119 | if (status) |
| 635 | pr_debug("can't register OHCI device, %d\n", status); | 120 | pr_debug("can't register OHCI device, %d\n", status); |
| 636 | } | 121 | } |
| @@ -638,11 +123,11 @@ omap_otg_init(struct omap_usb_config *config) | |||
| 638 | 123 | ||
| 639 | #ifdef CONFIG_USB_OTG | 124 | #ifdef CONFIG_USB_OTG |
| 640 | if (config->otg) { | 125 | if (config->otg) { |
| 126 | struct platform_device *otg_device = config->otg_device; | ||
| 127 | |||
| 641 | syscon &= ~OTG_IDLE_EN; | 128 | syscon &= ~OTG_IDLE_EN; |
| 642 | otg_device.dev.platform_data = config; | 129 | otg_device->dev.platform_data = config; |
| 643 | if (cpu_is_omap7xx()) | 130 | status = platform_device_register(otg_device); |
| 644 | otg_resources[1].start = INT_7XX_USB_OTG; | ||
| 645 | status = platform_device_register(&otg_device); | ||
| 646 | if (status) | 131 | if (status) |
| 647 | pr_debug("can't register OTG device, %d\n", status); | 132 | pr_debug("can't register OTG device, %d\n", status); |
| 648 | } | 133 | } |
| @@ -654,102 +139,5 @@ omap_otg_init(struct omap_usb_config *config) | |||
| 654 | } | 139 | } |
| 655 | 140 | ||
| 656 | #else | 141 | #else |
| 657 | static inline void omap_otg_init(struct omap_usb_config *config) {} | 142 | void omap_otg_init(struct omap_usb_config *config) {} |
| 658 | #endif | ||
| 659 | |||
| 660 | /*-------------------------------------------------------------------------*/ | ||
| 661 | |||
| 662 | #ifdef CONFIG_ARCH_OMAP15XX | ||
| 663 | |||
| 664 | /* ULPD_DPLL_CTRL */ | ||
| 665 | #define DPLL_IOB (1 << 13) | ||
| 666 | #define DPLL_PLL_ENABLE (1 << 4) | ||
| 667 | #define DPLL_LOCK (1 << 0) | ||
| 668 | |||
| 669 | /* ULPD_APLL_CTRL */ | ||
| 670 | #define APLL_NDPLL_SWITCH (1 << 0) | ||
| 671 | |||
| 672 | |||
| 673 | static void __init omap_1510_usb_init(struct omap_usb_config *config) | ||
| 674 | { | ||
| 675 | unsigned int val; | ||
| 676 | u16 w; | ||
| 677 | |||
| 678 | omap_usb0_init(config->pins[0], is_usb0_device(config)); | ||
| 679 | omap_usb1_init(config->pins[1]); | ||
| 680 | omap_usb2_init(config->pins[2], 0); | ||
| 681 | |||
| 682 | val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1); | ||
| 683 | val |= (config->hmc_mode << 1); | ||
| 684 | omap_writel(val, MOD_CONF_CTRL_0); | ||
| 685 | |||
| 686 | printk("USB: hmc %d", config->hmc_mode); | ||
| 687 | if (config->pins[0]) | ||
| 688 | printk(", usb0 %d wires%s", config->pins[0], | ||
| 689 | is_usb0_device(config) ? " (dev)" : ""); | ||
| 690 | if (config->pins[1]) | ||
| 691 | printk(", usb1 %d wires", config->pins[1]); | ||
| 692 | if (config->pins[2]) | ||
| 693 | printk(", usb2 %d wires", config->pins[2]); | ||
| 694 | printk("\n"); | ||
| 695 | |||
| 696 | /* use DPLL for 48 MHz function clock */ | ||
| 697 | pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL), | ||
| 698 | omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ)); | ||
| 699 | |||
| 700 | w = omap_readw(ULPD_APLL_CTRL); | ||
| 701 | w &= ~APLL_NDPLL_SWITCH; | ||
| 702 | omap_writew(w, ULPD_APLL_CTRL); | ||
| 703 | |||
| 704 | w = omap_readw(ULPD_DPLL_CTRL); | ||
| 705 | w |= DPLL_IOB | DPLL_PLL_ENABLE; | ||
| 706 | omap_writew(w, ULPD_DPLL_CTRL); | ||
| 707 | |||
| 708 | w = omap_readw(ULPD_SOFT_REQ); | ||
| 709 | w |= SOFT_UDC_REQ | SOFT_DPLL_REQ; | ||
| 710 | omap_writew(w, ULPD_SOFT_REQ); | ||
| 711 | |||
| 712 | while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK)) | ||
| 713 | cpu_relax(); | ||
| 714 | |||
| 715 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 716 | if (config->register_dev) { | ||
| 717 | int status; | ||
| 718 | |||
| 719 | udc_device.dev.platform_data = config; | ||
| 720 | status = platform_device_register(&udc_device); | ||
| 721 | if (status) | ||
| 722 | pr_debug("can't register UDC device, %d\n", status); | ||
| 723 | /* udc driver gates 48MHz by D+ pullup */ | ||
| 724 | } | ||
| 725 | #endif | ||
| 726 | |||
| 727 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 728 | if (config->register_host) { | ||
| 729 | int status; | ||
| 730 | |||
| 731 | ohci_device.dev.platform_data = config; | ||
| 732 | status = platform_device_register(&ohci_device); | ||
| 733 | if (status) | ||
| 734 | pr_debug("can't register OHCI device, %d\n", status); | ||
| 735 | /* hcd explicitly gates 48MHz */ | ||
| 736 | } | ||
| 737 | #endif | ||
| 738 | } | ||
| 739 | |||
| 740 | #else | ||
| 741 | static inline void omap_1510_usb_init(struct omap_usb_config *config) {} | ||
| 742 | #endif | 143 | #endif |
| 743 | |||
| 744 | /*-------------------------------------------------------------------------*/ | ||
| 745 | |||
| 746 | void __init omap_usb_init(struct omap_usb_config *pdata) | ||
| 747 | { | ||
| 748 | if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) | ||
| 749 | omap_otg_init(pdata); | ||
| 750 | else if (cpu_is_omap15xx()) | ||
| 751 | omap_1510_usb_init(pdata); | ||
| 752 | else | ||
| 753 | printk(KERN_ERR "USB: No init for your chip yet\n"); | ||
| 754 | } | ||
| 755 | |||
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index ee87325c7712..133d51528f8d 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c | |||
| @@ -7,6 +7,7 @@ | |||
| 7 | * it under the terms of the GNU General Public License version 2 as | 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
| 9 | */ | 9 | */ |
| 10 | #define CONFIG_MTD_NAND_OMAP_HWECC | ||
| 10 | 11 | ||
| 11 | #include <linux/platform_device.h> | 12 | #include <linux/platform_device.h> |
| 12 | #include <linux/dma-mapping.h> | 13 | #include <linux/dma-mapping.h> |
| @@ -23,20 +24,8 @@ | |||
| 23 | #include <plat/gpmc.h> | 24 | #include <plat/gpmc.h> |
| 24 | #include <plat/nand.h> | 25 | #include <plat/nand.h> |
| 25 | 26 | ||
| 26 | #define GPMC_IRQ_STATUS 0x18 | ||
| 27 | #define GPMC_ECC_CONFIG 0x1F4 | ||
| 28 | #define GPMC_ECC_CONTROL 0x1F8 | ||
| 29 | #define GPMC_ECC_SIZE_CONFIG 0x1FC | ||
| 30 | #define GPMC_ECC1_RESULT 0x200 | ||
| 31 | |||
| 32 | #define DRIVER_NAME "omap2-nand" | 27 | #define DRIVER_NAME "omap2-nand" |
| 33 | 28 | ||
| 34 | #define NAND_WP_OFF 0 | ||
| 35 | #define NAND_WP_BIT 0x00000010 | ||
| 36 | |||
| 37 | #define GPMC_BUF_FULL 0x00000001 | ||
| 38 | #define GPMC_BUF_EMPTY 0x00000000 | ||
| 39 | |||
| 40 | #define NAND_Ecc_P1e (1 << 0) | 29 | #define NAND_Ecc_P1e (1 << 0) |
| 41 | #define NAND_Ecc_P2e (1 << 1) | 30 | #define NAND_Ecc_P2e (1 << 1) |
| 42 | #define NAND_Ecc_P4e (1 << 2) | 31 | #define NAND_Ecc_P4e (1 << 2) |
| @@ -139,34 +128,11 @@ struct omap_nand_info { | |||
| 139 | 128 | ||
| 140 | int gpmc_cs; | 129 | int gpmc_cs; |
| 141 | unsigned long phys_base; | 130 | unsigned long phys_base; |
| 142 | void __iomem *gpmc_cs_baseaddr; | ||
| 143 | void __iomem *gpmc_baseaddr; | ||
| 144 | void __iomem *nand_pref_fifo_add; | ||
| 145 | struct completion comp; | 131 | struct completion comp; |
| 146 | int dma_ch; | 132 | int dma_ch; |
| 147 | }; | 133 | }; |
| 148 | 134 | ||
| 149 | /** | 135 | /** |
| 150 | * omap_nand_wp - This function enable or disable the Write Protect feature | ||
| 151 | * @mtd: MTD device structure | ||
| 152 | * @mode: WP ON/OFF | ||
| 153 | */ | ||
| 154 | static void omap_nand_wp(struct mtd_info *mtd, int mode) | ||
| 155 | { | ||
| 156 | struct omap_nand_info *info = container_of(mtd, | ||
| 157 | struct omap_nand_info, mtd); | ||
| 158 | |||
| 159 | unsigned long config = __raw_readl(info->gpmc_baseaddr + GPMC_CONFIG); | ||
| 160 | |||
| 161 | if (mode) | ||
| 162 | config &= ~(NAND_WP_BIT); /* WP is ON */ | ||
| 163 | else | ||
| 164 | config |= (NAND_WP_BIT); /* WP is OFF */ | ||
| 165 | |||
| 166 | __raw_writel(config, (info->gpmc_baseaddr + GPMC_CONFIG)); | ||
| 167 | } | ||
| 168 | |||
| 169 | /** | ||
| 170 | * omap_hwcontrol - hardware specific access to control-lines | 136 | * omap_hwcontrol - hardware specific access to control-lines |
| 171 | * @mtd: MTD device structure | 137 | * @mtd: MTD device structure |
| 172 | * @cmd: command to device | 138 | * @cmd: command to device |
| @@ -181,31 +147,17 @@ static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |||
| 181 | { | 147 | { |
| 182 | struct omap_nand_info *info = container_of(mtd, | 148 | struct omap_nand_info *info = container_of(mtd, |
| 183 | struct omap_nand_info, mtd); | 149 | struct omap_nand_info, mtd); |
| 184 | switch (ctrl) { | ||
| 185 | case NAND_CTRL_CHANGE | NAND_CTRL_CLE: | ||
| 186 | info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr + | ||
| 187 | GPMC_CS_NAND_COMMAND; | ||
| 188 | info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr + | ||
| 189 | GPMC_CS_NAND_DATA; | ||
| 190 | break; | ||
| 191 | |||
| 192 | case NAND_CTRL_CHANGE | NAND_CTRL_ALE: | ||
| 193 | info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr + | ||
| 194 | GPMC_CS_NAND_ADDRESS; | ||
| 195 | info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr + | ||
| 196 | GPMC_CS_NAND_DATA; | ||
| 197 | break; | ||
| 198 | |||
| 199 | case NAND_CTRL_CHANGE | NAND_NCE: | ||
| 200 | info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr + | ||
| 201 | GPMC_CS_NAND_DATA; | ||
| 202 | info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr + | ||
| 203 | GPMC_CS_NAND_DATA; | ||
| 204 | break; | ||
| 205 | } | ||
| 206 | 150 | ||
| 207 | if (cmd != NAND_CMD_NONE) | 151 | if (cmd != NAND_CMD_NONE) { |
| 208 | __raw_writeb(cmd, info->nand.IO_ADDR_W); | 152 | if (ctrl & NAND_CLE) |
| 153 | gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd); | ||
| 154 | |||
| 155 | else if (ctrl & NAND_ALE) | ||
| 156 | gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd); | ||
| 157 | |||
| 158 | else /* NAND_NCE */ | ||
| 159 | gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd); | ||
| 160 | } | ||
| 209 | } | 161 | } |
| 210 | 162 | ||
| 211 | /** | 163 | /** |
| @@ -232,11 +184,14 @@ static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) | |||
| 232 | struct omap_nand_info *info = container_of(mtd, | 184 | struct omap_nand_info *info = container_of(mtd, |
| 233 | struct omap_nand_info, mtd); | 185 | struct omap_nand_info, mtd); |
| 234 | u_char *p = (u_char *)buf; | 186 | u_char *p = (u_char *)buf; |
| 187 | u32 status = 0; | ||
| 235 | 188 | ||
| 236 | while (len--) { | 189 | while (len--) { |
| 237 | iowrite8(*p++, info->nand.IO_ADDR_W); | 190 | iowrite8(*p++, info->nand.IO_ADDR_W); |
| 238 | while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr + | 191 | /* wait until buffer is available for write */ |
| 239 | GPMC_STATUS) & GPMC_BUF_FULL)); | 192 | do { |
| 193 | status = gpmc_read_status(GPMC_STATUS_BUFFER); | ||
| 194 | } while (!status); | ||
| 240 | } | 195 | } |
| 241 | } | 196 | } |
| 242 | 197 | ||
| @@ -264,16 +219,16 @@ static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) | |||
| 264 | struct omap_nand_info *info = container_of(mtd, | 219 | struct omap_nand_info *info = container_of(mtd, |
| 265 | struct omap_nand_info, mtd); | 220 | struct omap_nand_info, mtd); |
| 266 | u16 *p = (u16 *) buf; | 221 | u16 *p = (u16 *) buf; |
| 267 | 222 | u32 status = 0; | |
| 268 | /* FIXME try bursts of writesw() or DMA ... */ | 223 | /* FIXME try bursts of writesw() or DMA ... */ |
| 269 | len >>= 1; | 224 | len >>= 1; |
| 270 | 225 | ||
| 271 | while (len--) { | 226 | while (len--) { |
| 272 | iowrite16(*p++, info->nand.IO_ADDR_W); | 227 | iowrite16(*p++, info->nand.IO_ADDR_W); |
| 273 | 228 | /* wait until buffer is available for write */ | |
| 274 | while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr + | 229 | do { |
| 275 | GPMC_STATUS) & GPMC_BUF_FULL)) | 230 | status = gpmc_read_status(GPMC_STATUS_BUFFER); |
| 276 | ; | 231 | } while (!status); |
| 277 | } | 232 | } |
| 278 | } | 233 | } |
| 279 | 234 | ||
| @@ -287,7 +242,7 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) | |||
| 287 | { | 242 | { |
| 288 | struct omap_nand_info *info = container_of(mtd, | 243 | struct omap_nand_info *info = container_of(mtd, |
| 289 | struct omap_nand_info, mtd); | 244 | struct omap_nand_info, mtd); |
| 290 | uint32_t pfpw_status = 0, r_count = 0; | 245 | uint32_t r_count = 0; |
| 291 | int ret = 0; | 246 | int ret = 0; |
| 292 | u32 *p = (u32 *)buf; | 247 | u32 *p = (u32 *)buf; |
| 293 | 248 | ||
| @@ -310,16 +265,16 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) | |||
| 310 | else | 265 | else |
| 311 | omap_read_buf8(mtd, buf, len); | 266 | omap_read_buf8(mtd, buf, len); |
| 312 | } else { | 267 | } else { |
| 268 | p = (u32 *) buf; | ||
| 313 | do { | 269 | do { |
| 314 | pfpw_status = gpmc_prefetch_status(); | 270 | r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); |
| 315 | r_count = ((pfpw_status >> 24) & 0x7F) >> 2; | 271 | r_count = r_count >> 2; |
| 316 | ioread32_rep(info->nand_pref_fifo_add, p, r_count); | 272 | ioread32_rep(info->nand.IO_ADDR_R, p, r_count); |
| 317 | p += r_count; | 273 | p += r_count; |
| 318 | len -= r_count << 2; | 274 | len -= r_count << 2; |
| 319 | } while (len); | 275 | } while (len); |
| 320 | |||
| 321 | /* disable and stop the PFPW engine */ | 276 | /* disable and stop the PFPW engine */ |
| 322 | gpmc_prefetch_reset(); | 277 | gpmc_prefetch_reset(info->gpmc_cs); |
| 323 | } | 278 | } |
| 324 | } | 279 | } |
| 325 | 280 | ||
| @@ -334,13 +289,13 @@ static void omap_write_buf_pref(struct mtd_info *mtd, | |||
| 334 | { | 289 | { |
| 335 | struct omap_nand_info *info = container_of(mtd, | 290 | struct omap_nand_info *info = container_of(mtd, |
| 336 | struct omap_nand_info, mtd); | 291 | struct omap_nand_info, mtd); |
| 337 | uint32_t pfpw_status = 0, w_count = 0; | 292 | uint32_t pref_count = 0, w_count = 0; |
| 338 | int i = 0, ret = 0; | 293 | int i = 0, ret = 0; |
| 339 | u16 *p = (u16 *) buf; | 294 | u16 *p; |
| 340 | 295 | ||
| 341 | /* take care of subpage writes */ | 296 | /* take care of subpage writes */ |
| 342 | if (len % 2 != 0) { | 297 | if (len % 2 != 0) { |
| 343 | writeb(*buf, info->nand.IO_ADDR_R); | 298 | writeb(*buf, info->nand.IO_ADDR_W); |
| 344 | p = (u16 *)(buf + 1); | 299 | p = (u16 *)(buf + 1); |
| 345 | len--; | 300 | len--; |
| 346 | } | 301 | } |
| @@ -354,16 +309,19 @@ static void omap_write_buf_pref(struct mtd_info *mtd, | |||
| 354 | else | 309 | else |
| 355 | omap_write_buf8(mtd, buf, len); | 310 | omap_write_buf8(mtd, buf, len); |
| 356 | } else { | 311 | } else { |
| 357 | pfpw_status = gpmc_prefetch_status(); | 312 | p = (u16 *) buf; |
| 358 | while (pfpw_status & 0x3FFF) { | 313 | while (len) { |
| 359 | w_count = ((pfpw_status >> 24) & 0x7F) >> 1; | 314 | w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); |
| 315 | w_count = w_count >> 1; | ||
| 360 | for (i = 0; (i < w_count) && len; i++, len -= 2) | 316 | for (i = 0; (i < w_count) && len; i++, len -= 2) |
| 361 | iowrite16(*p++, info->nand_pref_fifo_add); | 317 | iowrite16(*p++, info->nand.IO_ADDR_W); |
| 362 | pfpw_status = gpmc_prefetch_status(); | ||
| 363 | } | 318 | } |
| 364 | 319 | /* wait for data to flushed-out before reset the prefetch */ | |
| 320 | do { | ||
| 321 | pref_count = gpmc_read_status(GPMC_PREFETCH_COUNT); | ||
| 322 | } while (pref_count); | ||
| 365 | /* disable and stop the PFPW engine */ | 323 | /* disable and stop the PFPW engine */ |
| 366 | gpmc_prefetch_reset(); | 324 | gpmc_prefetch_reset(info->gpmc_cs); |
| 367 | } | 325 | } |
| 368 | } | 326 | } |
| 369 | 327 | ||
| @@ -451,8 +409,9 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, | |||
| 451 | /* setup and start DMA using dma_addr */ | 409 | /* setup and start DMA using dma_addr */ |
| 452 | wait_for_completion(&info->comp); | 410 | wait_for_completion(&info->comp); |
| 453 | 411 | ||
| 454 | while (0x3fff & (prefetch_status = gpmc_prefetch_status())) | 412 | do { |
| 455 | ; | 413 | prefetch_status = gpmc_read_status(GPMC_PREFETCH_COUNT); |
| 414 | } while (prefetch_status); | ||
| 456 | /* disable and stop the PFPW engine */ | 415 | /* disable and stop the PFPW engine */ |
| 457 | gpmc_prefetch_reset(); | 416 | gpmc_prefetch_reset(); |
| 458 | 417 | ||
| @@ -530,29 +489,6 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len) | |||
| 530 | } | 489 | } |
| 531 | 490 | ||
| 532 | #ifdef CONFIG_MTD_NAND_OMAP_HWECC | 491 | #ifdef CONFIG_MTD_NAND_OMAP_HWECC |
| 533 | /** | ||
| 534 | * omap_hwecc_init - Initialize the HW ECC for NAND flash in GPMC controller | ||
| 535 | * @mtd: MTD device structure | ||
| 536 | */ | ||
| 537 | static void omap_hwecc_init(struct mtd_info *mtd) | ||
| 538 | { | ||
| 539 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | ||
| 540 | mtd); | ||
| 541 | struct nand_chip *chip = mtd->priv; | ||
| 542 | unsigned long val = 0x0; | ||
| 543 | |||
| 544 | /* Read from ECC Control Register */ | ||
| 545 | val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONTROL); | ||
| 546 | /* Clear all ECC | Enable Reg1 */ | ||
| 547 | val = ((0x00000001<<8) | 0x00000001); | ||
| 548 | __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONTROL); | ||
| 549 | |||
| 550 | /* Read from ECC Size Config Register */ | ||
| 551 | val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG); | ||
| 552 | /* ECCSIZE1=512 | Select eccResultsize[0-3] */ | ||
| 553 | val = ((((chip->ecc.size >> 1) - 1) << 22) | (0x0000000F)); | ||
| 554 | __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG); | ||
| 555 | } | ||
| 556 | 492 | ||
| 557 | /** | 493 | /** |
| 558 | * gen_true_ecc - This function will generate true ECC value | 494 | * gen_true_ecc - This function will generate true ECC value |
| @@ -755,19 +691,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, | |||
| 755 | { | 691 | { |
| 756 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | 692 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
| 757 | mtd); | 693 | mtd); |
| 758 | unsigned long val = 0x0; | 694 | return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code); |
| 759 | unsigned long reg; | ||
| 760 | |||
| 761 | /* Start Reading from HW ECC1_Result = 0x200 */ | ||
| 762 | reg = (unsigned long)(info->gpmc_baseaddr + GPMC_ECC1_RESULT); | ||
| 763 | val = __raw_readl(reg); | ||
| 764 | *ecc_code++ = val; /* P128e, ..., P1e */ | ||
| 765 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | ||
| 766 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | ||
| 767 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | ||
| 768 | reg += 4; | ||
| 769 | |||
| 770 | return 0; | ||
| 771 | } | 695 | } |
| 772 | 696 | ||
| 773 | /** | 697 | /** |
| @@ -781,32 +705,10 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode) | |||
| 781 | mtd); | 705 | mtd); |
| 782 | struct nand_chip *chip = mtd->priv; | 706 | struct nand_chip *chip = mtd->priv; |
| 783 | unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; | 707 | unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; |
| 784 | unsigned long val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONFIG); | ||
| 785 | |||
| 786 | switch (mode) { | ||
| 787 | case NAND_ECC_READ: | ||
| 788 | __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL); | ||
| 789 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ | ||
| 790 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | ||
| 791 | break; | ||
| 792 | case NAND_ECC_READSYN: | ||
| 793 | __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL); | ||
| 794 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ | ||
| 795 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | ||
| 796 | break; | ||
| 797 | case NAND_ECC_WRITE: | ||
| 798 | __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL); | ||
| 799 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ | ||
| 800 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | ||
| 801 | break; | ||
| 802 | default: | ||
| 803 | DEBUG(MTD_DEBUG_LEVEL0, "Error: Unrecognized Mode[%d]!\n", | ||
| 804 | mode); | ||
| 805 | break; | ||
| 806 | } | ||
| 807 | 708 | ||
| 808 | __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONFIG); | 709 | gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size); |
| 809 | } | 710 | } |
| 711 | |||
| 810 | #endif | 712 | #endif |
| 811 | 713 | ||
| 812 | /** | 714 | /** |
| @@ -834,14 +736,10 @@ static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) | |||
| 834 | else | 736 | else |
| 835 | timeo += (HZ * 20) / 1000; | 737 | timeo += (HZ * 20) / 1000; |
| 836 | 738 | ||
| 837 | this->IO_ADDR_W = (void *) info->gpmc_cs_baseaddr + | 739 | gpmc_nand_write(info->gpmc_cs, |
| 838 | GPMC_CS_NAND_COMMAND; | 740 | GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF)); |
| 839 | this->IO_ADDR_R = (void *) info->gpmc_cs_baseaddr + GPMC_CS_NAND_DATA; | ||
| 840 | |||
| 841 | __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W); | ||
| 842 | |||
| 843 | while (time_before(jiffies, timeo)) { | 741 | while (time_before(jiffies, timeo)) { |
| 844 | status = __raw_readb(this->IO_ADDR_R); | 742 | status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA); |
| 845 | if (status & NAND_STATUS_READY) | 743 | if (status & NAND_STATUS_READY) |
| 846 | break; | 744 | break; |
| 847 | cond_resched(); | 745 | cond_resched(); |
| @@ -855,22 +753,22 @@ static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) | |||
| 855 | */ | 753 | */ |
| 856 | static int omap_dev_ready(struct mtd_info *mtd) | 754 | static int omap_dev_ready(struct mtd_info *mtd) |
| 857 | { | 755 | { |
| 756 | unsigned int val = 0; | ||
| 858 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | 757 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
| 859 | mtd); | 758 | mtd); |
| 860 | unsigned int val = __raw_readl(info->gpmc_baseaddr + GPMC_IRQ_STATUS); | ||
| 861 | 759 | ||
| 760 | val = gpmc_read_status(GPMC_GET_IRQ_STATUS); | ||
| 862 | if ((val & 0x100) == 0x100) { | 761 | if ((val & 0x100) == 0x100) { |
| 863 | /* Clear IRQ Interrupt */ | 762 | /* Clear IRQ Interrupt */ |
| 864 | val |= 0x100; | 763 | val |= 0x100; |
| 865 | val &= ~(0x0); | 764 | val &= ~(0x0); |
| 866 | __raw_writel(val, info->gpmc_baseaddr + GPMC_IRQ_STATUS); | 765 | gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val); |
| 867 | } else { | 766 | } else { |
| 868 | unsigned int cnt = 0; | 767 | unsigned int cnt = 0; |
| 869 | while (cnt++ < 0x1FF) { | 768 | while (cnt++ < 0x1FF) { |
| 870 | if ((val & 0x100) == 0x100) | 769 | if ((val & 0x100) == 0x100) |
| 871 | return 0; | 770 | return 0; |
| 872 | val = __raw_readl(info->gpmc_baseaddr + | 771 | val = gpmc_read_status(GPMC_GET_IRQ_STATUS); |
| 873 | GPMC_IRQ_STATUS); | ||
| 874 | } | 772 | } |
| 875 | } | 773 | } |
| 876 | 774 | ||
| @@ -901,8 +799,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) | |||
| 901 | info->pdev = pdev; | 799 | info->pdev = pdev; |
| 902 | 800 | ||
| 903 | info->gpmc_cs = pdata->cs; | 801 | info->gpmc_cs = pdata->cs; |
| 904 | info->gpmc_baseaddr = pdata->gpmc_baseaddr; | ||
| 905 | info->gpmc_cs_baseaddr = pdata->gpmc_cs_baseaddr; | ||
| 906 | info->phys_base = pdata->phys_base; | 802 | info->phys_base = pdata->phys_base; |
| 907 | 803 | ||
| 908 | info->mtd.priv = &info->nand; | 804 | info->mtd.priv = &info->nand; |
| @@ -913,7 +809,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) | |||
| 913 | info->nand.options |= NAND_SKIP_BBTSCAN; | 809 | info->nand.options |= NAND_SKIP_BBTSCAN; |
| 914 | 810 | ||
| 915 | /* NAND write protect off */ | 811 | /* NAND write protect off */ |
| 916 | omap_nand_wp(&info->mtd, NAND_WP_OFF); | 812 | gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0); |
| 917 | 813 | ||
| 918 | if (!request_mem_region(info->phys_base, NAND_IO_SIZE, | 814 | if (!request_mem_region(info->phys_base, NAND_IO_SIZE, |
| 919 | pdev->dev.driver->name)) { | 815 | pdev->dev.driver->name)) { |
| @@ -948,8 +844,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) | |||
| 948 | } | 844 | } |
| 949 | 845 | ||
| 950 | if (use_prefetch) { | 846 | if (use_prefetch) { |
| 951 | /* copy the virtual address of nand base for fifo access */ | ||
| 952 | info->nand_pref_fifo_add = info->nand.IO_ADDR_R; | ||
| 953 | 847 | ||
| 954 | info->nand.read_buf = omap_read_buf_pref; | 848 | info->nand.read_buf = omap_read_buf_pref; |
| 955 | info->nand.write_buf = omap_write_buf_pref; | 849 | info->nand.write_buf = omap_write_buf_pref; |
| @@ -989,8 +883,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) | |||
| 989 | info->nand.ecc.correct = omap_correct_data; | 883 | info->nand.ecc.correct = omap_correct_data; |
| 990 | info->nand.ecc.mode = NAND_ECC_HW; | 884 | info->nand.ecc.mode = NAND_ECC_HW; |
| 991 | 885 | ||
| 992 | /* init HW ECC */ | ||
| 993 | omap_hwecc_init(&info->mtd); | ||
| 994 | #else | 886 | #else |
| 995 | info->nand.ecc.mode = NAND_ECC_SOFT; | 887 | info->nand.ecc.mode = NAND_ECC_SOFT; |
| 996 | #endif | 888 | #endif |
| @@ -1040,7 +932,7 @@ static int omap_nand_remove(struct platform_device *pdev) | |||
| 1040 | 932 | ||
| 1041 | /* Release NAND device, its internal structures and partitions */ | 933 | /* Release NAND device, its internal structures and partitions */ |
| 1042 | nand_release(&info->mtd); | 934 | nand_release(&info->mtd); |
| 1043 | iounmap(info->nand_pref_fifo_add); | 935 | iounmap(info->nand.IO_ADDR_R); |
| 1044 | kfree(&info->mtd); | 936 | kfree(&info->mtd); |
| 1045 | return 0; | 937 | return 0; |
| 1046 | } | 938 | } |
diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig index 8e8f18d29d7a..5a35f22372b9 100644 --- a/drivers/video/console/Kconfig +++ b/drivers/video/console/Kconfig | |||
| @@ -6,7 +6,7 @@ menu "Console display driver support" | |||
| 6 | 6 | ||
| 7 | config VGA_CONSOLE | 7 | config VGA_CONSOLE |
| 8 | bool "VGA text console" if EMBEDDED || !X86 | 8 | bool "VGA text console" if EMBEDDED || !X86 |
| 9 | depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 | 9 | depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) |
| 10 | default y | 10 | default y |
| 11 | help | 11 | help |
| 12 | Saying Y here will allow you to use Linux in text mode through a | 12 | Saying Y here will allow you to use Linux in text mode through a |
diff --git a/drivers/video/omap/lcd_apollon.c b/drivers/video/omap/lcd_apollon.c index 2be94eb3bbf5..10459d8bd9a0 100644 --- a/drivers/video/omap/lcd_apollon.c +++ b/drivers/video/omap/lcd_apollon.c | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | #include <linux/platform_device.h> | 25 | #include <linux/platform_device.h> |
| 26 | 26 | ||
| 27 | #include <mach/gpio.h> | 27 | #include <mach/gpio.h> |
| 28 | #include <plat/mux.h> | ||
| 29 | 28 | ||
| 30 | #include "omapfb.h" | 29 | #include "omapfb.h" |
| 31 | 30 | ||
| @@ -34,8 +33,6 @@ | |||
| 34 | static int apollon_panel_init(struct lcd_panel *panel, | 33 | static int apollon_panel_init(struct lcd_panel *panel, |
| 35 | struct omapfb_device *fbdev) | 34 | struct omapfb_device *fbdev) |
| 36 | { | 35 | { |
| 37 | /* configure LCD PWR_EN */ | ||
| 38 | omap_cfg_reg(M21_242X_GPIO11); | ||
| 39 | return 0; | 36 | return 0; |
| 40 | } | 37 | } |
| 41 | 38 | ||