[MIPS] VR41xx: Set VR41_CONF_BP only for PrId 0x0c80.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2 files changed, 4 insertions, 1 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index ed35ee57b388..256b6611e718 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -868,7 +868,9 @@ static void __init probe_pcache(void)
                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
                     c->processor_id == 0x0c82U) {
                         config &= ~0x00000030U;
-                        config |= 0x00410000U;
+                        config |= 0x00400000U;
+                        if (c->processor_id == 0x0c80U)
+                                config |= VR41_CONF_BP;
                         write_c0_config(config);
                 }
                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 9192d76c133d..b4169f0fb13b 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -470,6 +470,7 @@
 
 /* Bits specific to the VR41xx.  */
 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
+#define VR41_CONF_BP            (_ULCAST_(1) << 16)
 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 #define VR41_CONF_AD            (_ULCAST_(1) << 23)