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authorPete Popov <ppopov@embeddedalley.com>2005-03-01 01:33:16 -0500
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:30:47 -0400
commite3ad1c23ba72214669b364c6fa304531dc768c3e (patch)
treebc1e0004d3df66b4c37a2deb8d89431657039719
parent784f7b9d895893c6aa3ca471c1344a62fc29c285 (diff)
Base Au1200 2.6 support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/Kconfig18
-rw-r--r--arch/mips/Makefile14
-rw-r--r--arch/mips/au1000/common/au1xxx_irqmap.c32
-rw-r--r--arch/mips/au1000/common/cputable.c3
-rw-r--r--arch/mips/au1000/common/dbdma.c298
-rw-r--r--arch/mips/au1000/common/irq.c4
-rw-r--r--arch/mips/au1000/common/usbdev.c12
-rw-r--r--arch/mips/au1000/pb1200/Makefile5
-rw-r--r--arch/mips/au1000/pb1200/board_setup.c187
-rw-r--r--arch/mips/au1000/pb1200/init.c69
-rw-r--r--arch/mips/au1000/pb1200/irqmap.c180
-rw-r--r--arch/mips/kernel/cpu-probe.c5
-rw-r--r--arch/mips/kernel/proc.c3
-rw-r--r--arch/mips/mm/c-r4k.c4
-rw-r--r--arch/mips/mm/tlbex.c1
-rw-r--r--include/asm-mips/bootinfo.h2
-rw-r--r--include/asm-mips/cpu.h3
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h556
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_dbdma.h124
-rw-r--r--include/asm-mips/mach-db1x00/db1200.h214
-rw-r--r--include/asm-mips/mach-pb1x00/pb1200.h244
21 files changed, 1796 insertions, 182 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2edbef5f3551..455de42db7c9 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -642,6 +642,10 @@ config SGI_IP32
642 help 642 help
643 If you want this kernel to run on SGI O2 workstation, say Y here. 643 If you want this kernel to run on SGI O2 workstation, say Y here.
644 644
645config SOC_AU1200
646 bool
647 select SOC_AU1X00
648
645config SOC_AU1X00 649config SOC_AU1X00
646 bool "Support for AMD/Alchemy Au1X00 SOCs" 650 bool "Support for AMD/Alchemy Au1X00 SOCs"
647 select SYS_SUPPORTS_32BIT_KERNEL 651 select SYS_SUPPORTS_32BIT_KERNEL
@@ -702,6 +706,13 @@ config MIPS_PB1550
702 select HW_HAS_PCI 706 select HW_HAS_PCI
703 select MIPS_DISABLE_OBSOLETE_IDE 707 select MIPS_DISABLE_OBSOLETE_IDE
704 708
709config MIPS_PB1200
710 bool "AMD Alchemy PB1200 board"
711 select SOC_AU1200
712 select DMA_NONCOHERENT
713 select MIPS_DISABLE_OBSOLETE_IDE
714 select SYS_SUPPORTS_LITTLE_ENDIAN
715
705config MIPS_DB1000 716config MIPS_DB1000
706 bool "DB1000 board" 717 bool "DB1000 board"
707 depends on SOC_AU1000 718 depends on SOC_AU1000
@@ -732,6 +743,13 @@ config MIPS_BOSPORUS
732 depends on SOC_AU1500 743 depends on SOC_AU1500
733 select DMA_NONCOHERENT 744 select DMA_NONCOHERENT
734 745
746config MIPS_DB1200
747 bool "AMD Alchemy DB1200 board"
748 select SOC_AU1200
749 select DMA_NONCOHERENT
750 select MIPS_DISABLE_OBSOLETE_IDE
751 select SYS_SUPPORTS_LITTLE_ENDIAN
752
735config MIPS_MIRAGE 753config MIPS_MIRAGE
736 bool "Mirage board" 754 bool "Mirage board"
737 depends on SOC_AU1500 755 depends on SOC_AU1500
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 5f2dfcddb9f2..99da8a2850c7 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -266,6 +266,13 @@ cflags-$(CONFIG_MIPS_PB1550) += -Iinclude/asm-mips/mach-pb1x00
266load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 266load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000
267 267
268# 268#
269# AMD Alchemy Pb1200 eval board
270#
271libs-$(CONFIG_MIPS_PB1200) += arch/mips/au1000/pb1200/
272cflags-$(CONFIG_MIPS_PB1200) += -Iinclude/asm-mips/mach-pb1x00
273load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000
274
275#
269# AMD Alchemy Db1000 eval board 276# AMD Alchemy Db1000 eval board
270# 277#
271libs-$(CONFIG_MIPS_DB1000) += arch/mips/au1000/db1x00/ 278libs-$(CONFIG_MIPS_DB1000) += arch/mips/au1000/db1x00/
@@ -294,6 +301,13 @@ cflags-$(CONFIG_MIPS_DB1550) += -Iinclude/asm-mips/mach-db1x00
294load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 301load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000
295 302
296# 303#
304# AMD Alchemy Db1200 eval board
305#
306libs-$(CONFIG_MIPS_DB1200) += arch/mips/au1000/pb1200/
307cflags-$(CONFIG_MIPS_DB1200) += -Iinclude/asm-mips/mach-db1x00
308load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000
309
310#
297# AMD Alchemy Bosporus eval board 311# AMD Alchemy Bosporus eval board
298# 312#
299libs-$(CONFIG_MIPS_BOSPORUS) += arch/mips/au1000/db1x00/ 313libs-$(CONFIG_MIPS_BOSPORUS) += arch/mips/au1000/db1x00/
diff --git a/arch/mips/au1000/common/au1xxx_irqmap.c b/arch/mips/au1000/common/au1xxx_irqmap.c
index 8a0f39f67c59..0b2c03c52319 100644
--- a/arch/mips/au1000/common/au1xxx_irqmap.c
+++ b/arch/mips/au1000/common/au1xxx_irqmap.c
@@ -173,14 +173,14 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = {
173 { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, 173 { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
174 { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0}, 174 { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0},
175 { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0}, 175 { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0},
176 { AU1550_TOY_INT, INTC_INT_RISE_EDGE, 0 }, 176 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
177 { AU1550_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 177 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
178 { AU1550_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 178 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
179 { AU1550_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, 179 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
180 { AU1550_RTC_INT, INTC_INT_RISE_EDGE, 0 }, 180 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
181 { AU1550_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 181 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
182 { AU1550_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 182 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
183 { AU1550_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, 183 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
184 { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0}, 184 { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0},
185 { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, 185 { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
186 { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, 186 { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
@@ -201,14 +201,14 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = {
201 { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, 201 { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
202 { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0}, 202 { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0},
203 { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0}, 203 { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0},
204 { AU1200_TOY_INT, INTC_INT_RISE_EDGE, 0 }, 204 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
205 { AU1200_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 205 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
206 { AU1200_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 206 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
207 { AU1200_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, 207 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
208 { AU1200_RTC_INT, INTC_INT_RISE_EDGE, 0 }, 208 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
209 { AU1200_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 209 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
210 { AU1200_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 210 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
211 { AU1200_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, 211 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
212 { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0}, 212 { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0},
213 { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 }, 213 { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 },
214 { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0}, 214 { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0},
diff --git a/arch/mips/au1000/common/cputable.c b/arch/mips/au1000/common/cputable.c
index f5521dfccfd6..4dbde82c8215 100644
--- a/arch/mips/au1000/common/cputable.c
+++ b/arch/mips/au1000/common/cputable.c
@@ -37,7 +37,8 @@ struct cpu_spec cpu_specs[] = {
37 { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 }, 37 { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 },
38 { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 }, 38 { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 },
39 { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 }, 39 { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 },
40 { 0xffffffff, 0x04030200, "Au1200 AA", 0, 1 }, 40 { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 },
41 { 0xffffffff, 0x04030201, "Au1200 AC", 0, 1 },
41 { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 }, 42 { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 },
42}; 43};
43 44
diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c
index adfc3172aace..cf10dc246f82 100644
--- a/arch/mips/au1000/common/dbdma.c
+++ b/arch/mips/au1000/common/dbdma.c
@@ -29,6 +29,7 @@
29 * 675 Mass Ave, Cambridge, MA 02139, USA. 29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 * 30 *
31 */ 31 */
32
32#include <linux/config.h> 33#include <linux/config.h>
33#include <linux/kernel.h> 34#include <linux/kernel.h>
34#include <linux/errno.h> 35#include <linux/errno.h>
@@ -42,6 +43,8 @@
42#include <asm/mach-au1x00/au1xxx_dbdma.h> 43#include <asm/mach-au1x00/au1xxx_dbdma.h>
43#include <asm/system.h> 44#include <asm/system.h>
44 45
46/* #include <linux/module.h> */
47
45#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 48#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
46 49
47/* 50/*
@@ -55,43 +58,16 @@
55 * functions. The drivers allocate the data buffers and assign them 58 * functions. The drivers allocate the data buffers and assign them
56 * to the descriptors. 59 * to the descriptors.
57 */ 60 */
58static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock); 61static spinlock_t au1xxx_dbdma_spin_lock = SPIN_LOCK_UNLOCKED;
59 62
60/* I couldn't find a macro that did this...... 63/* I couldn't find a macro that did this......
61*/ 64*/
62#define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1)) 65#define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
63 66
64static volatile dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; 67static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
65static int dbdma_initialized; 68static int dbdma_initialized=0;
66static void au1xxx_dbdma_init(void); 69static void au1xxx_dbdma_init(void);
67 70
68typedef struct dbdma_device_table {
69 u32 dev_id;
70 u32 dev_flags;
71 u32 dev_tsize;
72 u32 dev_devwidth;
73 u32 dev_physaddr; /* If FIFO */
74 u32 dev_intlevel;
75 u32 dev_intpolarity;
76} dbdev_tab_t;
77
78typedef struct dbdma_chan_config {
79 u32 chan_flags;
80 u32 chan_index;
81 dbdev_tab_t *chan_src;
82 dbdev_tab_t *chan_dest;
83 au1x_dma_chan_t *chan_ptr;
84 au1x_ddma_desc_t *chan_desc_base;
85 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
86 void *chan_callparam;
87 void (*chan_callback)(int, void *, struct pt_regs *);
88} chan_tab_t;
89
90#define DEV_FLAGS_INUSE (1 << 0)
91#define DEV_FLAGS_ANYUSE (1 << 1)
92#define DEV_FLAGS_OUT (1 << 2)
93#define DEV_FLAGS_IN (1 << 3)
94
95static dbdev_tab_t dbdev_tab[] = { 71static dbdev_tab_t dbdev_tab[] = {
96#ifdef CONFIG_SOC_AU1550 72#ifdef CONFIG_SOC_AU1550
97 /* UARTS */ 73 /* UARTS */
@@ -157,13 +133,13 @@ static dbdev_tab_t dbdev_tab[] = {
157 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 133 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
158 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 134 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
159 135
160 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, 136 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
161 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 137 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
162 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, 138 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
163 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 139 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
164 140
165 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, 141 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
166 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 142 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
167 143
168 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, 144 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
169 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, 145 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
@@ -173,9 +149,9 @@ static dbdev_tab_t dbdev_tab[] = {
173 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, 149 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
174 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 150 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
175 151
176 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 152 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
177 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 153 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
178 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 154 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
179 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 155 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
180 156
181 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 157 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
@@ -184,6 +160,24 @@ static dbdev_tab_t dbdev_tab[] = {
184 160
185 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 161 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
186 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 162 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
163
164 /* Provide 16 user definable device types */
165 { 0, 0, 0, 0, 0, 0, 0 },
166 { 0, 0, 0, 0, 0, 0, 0 },
167 { 0, 0, 0, 0, 0, 0, 0 },
168 { 0, 0, 0, 0, 0, 0, 0 },
169 { 0, 0, 0, 0, 0, 0, 0 },
170 { 0, 0, 0, 0, 0, 0, 0 },
171 { 0, 0, 0, 0, 0, 0, 0 },
172 { 0, 0, 0, 0, 0, 0, 0 },
173 { 0, 0, 0, 0, 0, 0, 0 },
174 { 0, 0, 0, 0, 0, 0, 0 },
175 { 0, 0, 0, 0, 0, 0, 0 },
176 { 0, 0, 0, 0, 0, 0, 0 },
177 { 0, 0, 0, 0, 0, 0, 0 },
178 { 0, 0, 0, 0, 0, 0, 0 },
179 { 0, 0, 0, 0, 0, 0, 0 },
180 { 0, 0, 0, 0, 0, 0, 0 },
187}; 181};
188 182
189#define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t)) 183#define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
@@ -203,6 +197,30 @@ find_dbdev_id (u32 id)
203 return NULL; 197 return NULL;
204} 198}
205 199
200u32
201au1xxx_ddma_add_device(dbdev_tab_t *dev)
202{
203 u32 ret = 0;
204 dbdev_tab_t *p=NULL;
205 static u16 new_id=0x1000;
206
207 p = find_dbdev_id(0);
208 if ( NULL != p )
209 {
210 memcpy(p, dev, sizeof(dbdev_tab_t));
211 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
212 ret = p->dev_id;
213 new_id++;
214#if 0
215 printk("add_device: id:%x flags:%x padd:%x\n",
216 p->dev_id, p->dev_flags, p->dev_physaddr );
217#endif
218 }
219
220 return ret;
221}
222EXPORT_SYMBOL(au1xxx_ddma_add_device);
223
206/* Allocate a channel and return a non-zero descriptor if successful. 224/* Allocate a channel and return a non-zero descriptor if successful.
207*/ 225*/
208u32 226u32
@@ -215,7 +233,7 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
215 int i; 233 int i;
216 dbdev_tab_t *stp, *dtp; 234 dbdev_tab_t *stp, *dtp;
217 chan_tab_t *ctp; 235 chan_tab_t *ctp;
218 volatile au1x_dma_chan_t *cp; 236 au1x_dma_chan_t *cp;
219 237
220 /* We do the intialization on the first channel allocation. 238 /* We do the intialization on the first channel allocation.
221 * We have to wait because of the interrupt handler initialization 239 * We have to wait because of the interrupt handler initialization
@@ -225,9 +243,6 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
225 au1xxx_dbdma_init(); 243 au1xxx_dbdma_init();
226 dbdma_initialized = 1; 244 dbdma_initialized = 1;
227 245
228 if ((srcid > DSCR_NDEV_IDS) || (destid > DSCR_NDEV_IDS))
229 return 0;
230
231 if ((stp = find_dbdev_id(srcid)) == NULL) return 0; 246 if ((stp = find_dbdev_id(srcid)) == NULL) return 0;
232 if ((dtp = find_dbdev_id(destid)) == NULL) return 0; 247 if ((dtp = find_dbdev_id(destid)) == NULL) return 0;
233 248
@@ -269,9 +284,9 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
269 /* If kmalloc fails, it is caught below same 284 /* If kmalloc fails, it is caught below same
270 * as a channel not available. 285 * as a channel not available.
271 */ 286 */
272 ctp = kmalloc(sizeof(chan_tab_t), GFP_KERNEL); 287 ctp = (chan_tab_t *)
288 kmalloc(sizeof(chan_tab_t), GFP_KERNEL);
273 chan_tab_ptr[i] = ctp; 289 chan_tab_ptr[i] = ctp;
274 ctp->chan_index = chan = i;
275 break; 290 break;
276 } 291 }
277 } 292 }
@@ -279,10 +294,11 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
279 294
280 if (ctp != NULL) { 295 if (ctp != NULL) {
281 memset(ctp, 0, sizeof(chan_tab_t)); 296 memset(ctp, 0, sizeof(chan_tab_t));
297 ctp->chan_index = chan = i;
282 dcp = DDMA_CHANNEL_BASE; 298 dcp = DDMA_CHANNEL_BASE;
283 dcp += (0x0100 * chan); 299 dcp += (0x0100 * chan);
284 ctp->chan_ptr = (au1x_dma_chan_t *)dcp; 300 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
285 cp = (volatile au1x_dma_chan_t *)dcp; 301 cp = (au1x_dma_chan_t *)dcp;
286 ctp->chan_src = stp; 302 ctp->chan_src = stp;
287 ctp->chan_dest = dtp; 303 ctp->chan_dest = dtp;
288 ctp->chan_callback = callback; 304 ctp->chan_callback = callback;
@@ -299,6 +315,9 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
299 i |= DDMA_CFG_DED; 315 i |= DDMA_CFG_DED;
300 if (dtp->dev_intpolarity) 316 if (dtp->dev_intpolarity)
301 i |= DDMA_CFG_DP; 317 i |= DDMA_CFG_DP;
318 if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
319 (dtp->dev_flags & DEV_FLAGS_SYNC))
320 i |= DDMA_CFG_SYNC;
302 cp->ddma_cfg = i; 321 cp->ddma_cfg = i;
303 au_sync(); 322 au_sync();
304 323
@@ -309,14 +328,14 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
309 rv = (u32)(&chan_tab_ptr[chan]); 328 rv = (u32)(&chan_tab_ptr[chan]);
310 } 329 }
311 else { 330 else {
312 /* Release devices. 331 /* Release devices */
313 */
314 stp->dev_flags &= ~DEV_FLAGS_INUSE; 332 stp->dev_flags &= ~DEV_FLAGS_INUSE;
315 dtp->dev_flags &= ~DEV_FLAGS_INUSE; 333 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
316 } 334 }
317 } 335 }
318 return rv; 336 return rv;
319} 337}
338EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
320 339
321/* Set the device width if source or destination is a FIFO. 340/* Set the device width if source or destination is a FIFO.
322 * Should be 8, 16, or 32 bits. 341 * Should be 8, 16, or 32 bits.
@@ -344,6 +363,7 @@ au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
344 363
345 return rv; 364 return rv;
346} 365}
366EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
347 367
348/* Allocate a descriptor ring, initializing as much as possible. 368/* Allocate a descriptor ring, initializing as much as possible.
349*/ 369*/
@@ -370,7 +390,8 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
370 * and if we try that first we are likely to not waste larger 390 * and if we try that first we are likely to not waste larger
371 * slabs of memory. 391 * slabs of memory.
372 */ 392 */
373 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), GFP_KERNEL); 393 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
394 GFP_KERNEL|GFP_DMA);
374 if (desc_base == 0) 395 if (desc_base == 0)
375 return 0; 396 return 0;
376 397
@@ -381,7 +402,7 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
381 kfree((const void *)desc_base); 402 kfree((const void *)desc_base);
382 i = entries * sizeof(au1x_ddma_desc_t); 403 i = entries * sizeof(au1x_ddma_desc_t);
383 i += (sizeof(au1x_ddma_desc_t) - 1); 404 i += (sizeof(au1x_ddma_desc_t) - 1);
384 if ((desc_base = (u32)kmalloc(i, GFP_KERNEL)) == 0) 405 if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0)
385 return 0; 406 return 0;
386 407
387 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t)); 408 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
@@ -461,9 +482,14 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
461 /* If source input is fifo, set static address. 482 /* If source input is fifo, set static address.
462 */ 483 */
463 if (stp->dev_flags & DEV_FLAGS_IN) { 484 if (stp->dev_flags & DEV_FLAGS_IN) {
464 src0 = stp->dev_physaddr; 485 if ( stp->dev_flags & DEV_FLAGS_BURSTABLE )
486 src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
487 else
465 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC); 488 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
489
466 } 490 }
491 if (stp->dev_physaddr)
492 src0 = stp->dev_physaddr;
467 493
468 /* Set up dest1. For now, assume no stride and increment. 494 /* Set up dest1. For now, assume no stride and increment.
469 * A channel attribute update can change this later. 495 * A channel attribute update can change this later.
@@ -487,10 +513,18 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
487 /* If destination output is fifo, set static address. 513 /* If destination output is fifo, set static address.
488 */ 514 */
489 if (dtp->dev_flags & DEV_FLAGS_OUT) { 515 if (dtp->dev_flags & DEV_FLAGS_OUT) {
490 dest0 = dtp->dev_physaddr; 516 if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE )
517 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
518 else
491 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC); 519 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
492 } 520 }
521 if (dtp->dev_physaddr)
522 dest0 = dtp->dev_physaddr;
493 523
524#if 0
525 printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
526 dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 );
527#endif
494 for (i=0; i<entries; i++) { 528 for (i=0; i<entries; i++) {
495 dp->dscr_cmd0 = cmd0; 529 dp->dscr_cmd0 = cmd0;
496 dp->dscr_cmd1 = cmd1; 530 dp->dscr_cmd1 = cmd1;
@@ -499,6 +533,7 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
499 dp->dscr_dest0 = dest0; 533 dp->dscr_dest0 = dest0;
500 dp->dscr_dest1 = dest1; 534 dp->dscr_dest1 = dest1;
501 dp->dscr_stat = 0; 535 dp->dscr_stat = 0;
536 dp->sw_context = dp->sw_status = 0;
502 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1)); 537 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
503 dp++; 538 dp++;
504 } 539 }
@@ -511,13 +546,14 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
511 546
512 return (u32)(ctp->chan_desc_base); 547 return (u32)(ctp->chan_desc_base);
513} 548}
549EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
514 550
515/* Put a source buffer into the DMA ring. 551/* Put a source buffer into the DMA ring.
516 * This updates the source pointer and byte count. Normally used 552 * This updates the source pointer and byte count. Normally used
517 * for memory to fifo transfers. 553 * for memory to fifo transfers.
518 */ 554 */
519u32 555u32
520au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes) 556_au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
521{ 557{
522 chan_tab_t *ctp; 558 chan_tab_t *ctp;
523 au1x_ddma_desc_t *dp; 559 au1x_ddma_desc_t *dp;
@@ -544,24 +580,40 @@ au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes)
544 */ 580 */
545 dp->dscr_source0 = virt_to_phys(buf); 581 dp->dscr_source0 = virt_to_phys(buf);
546 dp->dscr_cmd1 = nbytes; 582 dp->dscr_cmd1 = nbytes;
547 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ 583 /* Check flags */
548 ctp->chan_ptr->ddma_dbell = 0xffffffff; /* Make it go */ 584 if (flags & DDMA_FLAGS_IE)
549 585 dp->dscr_cmd0 |= DSCR_CMD0_IE;
586 if (flags & DDMA_FLAGS_NOIE)
587 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
550 /* Get next descriptor pointer. 588 /* Get next descriptor pointer.
551 */ 589 */
552 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 590 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
553 591
592 /*
593 * There is an errata on the Au1200/Au1550 parts that could result
594 * in "stale" data being DMA'd. It has to do with the snoop logic on
595 * the dache eviction buffer. NONCOHERENT_IO is on by default for
596 * these parts. If it is fixedin the future, these dma_cache_inv will
597 * just be nothing more than empty macros. See io.h.
598 * */
599 dma_cache_wback_inv(buf,nbytes);
600 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
601 au_sync();
602 dma_cache_wback_inv(dp, sizeof(dp));
603 ctp->chan_ptr->ddma_dbell = 0;
604
554 /* return something not zero. 605 /* return something not zero.
555 */ 606 */
556 return nbytes; 607 return nbytes;
557} 608}
609EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
558 610
559/* Put a destination buffer into the DMA ring. 611/* Put a destination buffer into the DMA ring.
560 * This updates the destination pointer and byte count. Normally used 612 * This updates the destination pointer and byte count. Normally used
561 * to place an empty buffer into the ring for fifo to memory transfers. 613 * to place an empty buffer into the ring for fifo to memory transfers.
562 */ 614 */
563u32 615u32
564au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes) 616_au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
565{ 617{
566 chan_tab_t *ctp; 618 chan_tab_t *ctp;
567 au1x_ddma_desc_t *dp; 619 au1x_ddma_desc_t *dp;
@@ -583,11 +635,33 @@ au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes)
583 if (dp->dscr_cmd0 & DSCR_CMD0_V) 635 if (dp->dscr_cmd0 & DSCR_CMD0_V)
584 return 0; 636 return 0;
585 637
586 /* Load up buffer address and byte count. 638 /* Load up buffer address and byte count */
587 */ 639
640 /* Check flags */
641 if (flags & DDMA_FLAGS_IE)
642 dp->dscr_cmd0 |= DSCR_CMD0_IE;
643 if (flags & DDMA_FLAGS_NOIE)
644 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
645
588 dp->dscr_dest0 = virt_to_phys(buf); 646 dp->dscr_dest0 = virt_to_phys(buf);
589 dp->dscr_cmd1 = nbytes; 647 dp->dscr_cmd1 = nbytes;
648#if 0
649 printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
650 dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
651 dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 );
652#endif
653 /*
654 * There is an errata on the Au1200/Au1550 parts that could result in
655 * "stale" data being DMA'd. It has to do with the snoop logic on the
656 * dache eviction buffer. NONCOHERENT_IO is on by default for these
657 * parts. If it is fixedin the future, these dma_cache_inv will just
658 * be nothing more than empty macros. See io.h.
659 * */
660 dma_cache_inv(buf,nbytes);
590 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ 661 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
662 au_sync();
663 dma_cache_wback_inv(dp, sizeof(dp));
664 ctp->chan_ptr->ddma_dbell = 0;
591 665
592 /* Get next descriptor pointer. 666 /* Get next descriptor pointer.
593 */ 667 */
@@ -597,6 +671,7 @@ au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes)
597 */ 671 */
598 return nbytes; 672 return nbytes;
599} 673}
674EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
600 675
601/* Get a destination buffer into the DMA ring. 676/* Get a destination buffer into the DMA ring.
602 * Normally used to get a full buffer from the ring during fifo 677 * Normally used to get a full buffer from the ring during fifo
@@ -646,7 +721,7 @@ void
646au1xxx_dbdma_stop(u32 chanid) 721au1xxx_dbdma_stop(u32 chanid)
647{ 722{
648 chan_tab_t *ctp; 723 chan_tab_t *ctp;
649 volatile au1x_dma_chan_t *cp; 724 au1x_dma_chan_t *cp;
650 int halt_timeout = 0; 725 int halt_timeout = 0;
651 726
652 ctp = *((chan_tab_t **)chanid); 727 ctp = *((chan_tab_t **)chanid);
@@ -666,6 +741,7 @@ au1xxx_dbdma_stop(u32 chanid)
666 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V); 741 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
667 au_sync(); 742 au_sync();
668} 743}
744EXPORT_SYMBOL(au1xxx_dbdma_stop);
669 745
670/* Start using the current descriptor pointer. If the dbdma encounters 746/* Start using the current descriptor pointer. If the dbdma encounters
671 * a not valid descriptor, it will stop. In this case, we can just 747 * a not valid descriptor, it will stop. In this case, we can just
@@ -675,17 +751,17 @@ void
675au1xxx_dbdma_start(u32 chanid) 751au1xxx_dbdma_start(u32 chanid)
676{ 752{
677 chan_tab_t *ctp; 753 chan_tab_t *ctp;
678 volatile au1x_dma_chan_t *cp; 754 au1x_dma_chan_t *cp;
679 755
680 ctp = *((chan_tab_t **)chanid); 756 ctp = *((chan_tab_t **)chanid);
681
682 cp = ctp->chan_ptr; 757 cp = ctp->chan_ptr;
683 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr); 758 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
684 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */ 759 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
685 au_sync(); 760 au_sync();
686 cp->ddma_dbell = 0xffffffff; /* Make it go */ 761 cp->ddma_dbell = 0;
687 au_sync(); 762 au_sync();
688} 763}
764EXPORT_SYMBOL(au1xxx_dbdma_start);
689 765
690void 766void
691au1xxx_dbdma_reset(u32 chanid) 767au1xxx_dbdma_reset(u32 chanid)
@@ -704,15 +780,21 @@ au1xxx_dbdma_reset(u32 chanid)
704 780
705 do { 781 do {
706 dp->dscr_cmd0 &= ~DSCR_CMD0_V; 782 dp->dscr_cmd0 &= ~DSCR_CMD0_V;
783 /* reset our SW status -- this is used to determine
784 * if a descriptor is in use by upper level SW. Since
785 * posting can reset 'V' bit.
786 */
787 dp->sw_status = 0;
707 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 788 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
708 } while (dp != ctp->chan_desc_base); 789 } while (dp != ctp->chan_desc_base);
709} 790}
791EXPORT_SYMBOL(au1xxx_dbdma_reset);
710 792
711u32 793u32
712au1xxx_get_dma_residue(u32 chanid) 794au1xxx_get_dma_residue(u32 chanid)
713{ 795{
714 chan_tab_t *ctp; 796 chan_tab_t *ctp;
715 volatile au1x_dma_chan_t *cp; 797 au1x_dma_chan_t *cp;
716 u32 rv; 798 u32 rv;
717 799
718 ctp = *((chan_tab_t **)chanid); 800 ctp = *((chan_tab_t **)chanid);
@@ -747,15 +829,16 @@ au1xxx_dbdma_chan_free(u32 chanid)
747 829
748 kfree(ctp); 830 kfree(ctp);
749} 831}
832EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
750 833
751static irqreturn_t 834static void
752dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs) 835dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
753{ 836{
754 u32 intstat; 837 u32 intstat, flags;
755 u32 chan_index; 838 u32 chan_index;
756 chan_tab_t *ctp; 839 chan_tab_t *ctp;
757 au1x_ddma_desc_t *dp; 840 au1x_ddma_desc_t *dp;
758 volatile au1x_dma_chan_t *cp; 841 au1x_dma_chan_t *cp;
759 842
760 intstat = dbdma_gptr->ddma_intstat; 843 intstat = dbdma_gptr->ddma_intstat;
761 au_sync(); 844 au_sync();
@@ -774,19 +857,26 @@ dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
774 (ctp->chan_callback)(irq, ctp->chan_callparam, regs); 857 (ctp->chan_callback)(irq, ctp->chan_callparam, regs);
775 858
776 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 859 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
777
778 return IRQ_HANDLED;
779} 860}
780 861
781static void 862static void au1xxx_dbdma_init(void)
782au1xxx_dbdma_init(void)
783{ 863{
864 int irq_nr;
865
784 dbdma_gptr->ddma_config = 0; 866 dbdma_gptr->ddma_config = 0;
785 dbdma_gptr->ddma_throttle = 0; 867 dbdma_gptr->ddma_throttle = 0;
786 dbdma_gptr->ddma_inten = 0xffff; 868 dbdma_gptr->ddma_inten = 0xffff;
787 au_sync(); 869 au_sync();
788 870
789 if (request_irq(AU1550_DDMA_INT, dbdma_interrupt, SA_INTERRUPT, 871#if defined(CONFIG_SOC_AU1550)
872 irq_nr = AU1550_DDMA_INT;
873#elif defined(CONFIG_SOC_AU1200)
874 irq_nr = AU1200_DDMA_INT;
875#else
876 #error Unknown Au1x00 SOC
877#endif
878
879 if (request_irq(irq_nr, dbdma_interrupt, SA_INTERRUPT,
790 "Au1xxx dbdma", (void *)dbdma_gptr)) 880 "Au1xxx dbdma", (void *)dbdma_gptr))
791 printk("Can't get 1550 dbdma irq"); 881 printk("Can't get 1550 dbdma irq");
792} 882}
@@ -797,7 +887,8 @@ au1xxx_dbdma_dump(u32 chanid)
797 chan_tab_t *ctp; 887 chan_tab_t *ctp;
798 au1x_ddma_desc_t *dp; 888 au1x_ddma_desc_t *dp;
799 dbdev_tab_t *stp, *dtp; 889 dbdev_tab_t *stp, *dtp;
800 volatile au1x_dma_chan_t *cp; 890 au1x_dma_chan_t *cp;
891 u32 i = 0;
801 892
802 ctp = *((chan_tab_t **)chanid); 893 ctp = *((chan_tab_t **)chanid);
803 stp = ctp->chan_src; 894 stp = ctp->chan_src;
@@ -822,15 +913,64 @@ au1xxx_dbdma_dump(u32 chanid)
822 dp = ctp->chan_desc_base; 913 dp = ctp->chan_desc_base;
823 914
824 do { 915 do {
825 printk("dp %08x, cmd0 %08x, cmd1 %08x\n", 916 printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
826 (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1); 917 i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
827 printk("src0 %08x, src1 %08x, dest0 %08x\n", 918 printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
828 dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0); 919 dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
829 printk("dest1 %08x, stat %08x, nxtptr %08x\n", 920 printk("stat %08x, nxtptr %08x\n",
830 dp->dscr_dest1, dp->dscr_stat, dp->dscr_nxtptr); 921 dp->dscr_stat, dp->dscr_nxtptr);
831 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 922 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
832 } while (dp != ctp->chan_desc_base); 923 } while (dp != ctp->chan_desc_base);
833} 924}
834 925
926/* Put a descriptor into the DMA ring.
927 * This updates the source/destination pointers and byte count.
928 */
929u32
930au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr )
931{
932 chan_tab_t *ctp;
933 au1x_ddma_desc_t *dp;
934 u32 nbytes=0;
935
936 /* I guess we could check this to be within the
937 * range of the table......
938 */
939 ctp = *((chan_tab_t **)chanid);
940
941 /* We should have multiple callers for a particular channel,
942 * an interrupt doesn't affect this pointer nor the descriptor,
943 * so no locking should be needed.
944 */
945 dp = ctp->put_ptr;
946
947 /* If the descriptor is valid, we are way ahead of the DMA
948 * engine, so just return an error condition.
949 */
950 if (dp->dscr_cmd0 & DSCR_CMD0_V)
951 return 0;
952
953 /* Load up buffer addresses and byte count.
954 */
955 dp->dscr_dest0 = dscr->dscr_dest0;
956 dp->dscr_source0 = dscr->dscr_source0;
957 dp->dscr_dest1 = dscr->dscr_dest1;
958 dp->dscr_source1 = dscr->dscr_source1;
959 dp->dscr_cmd1 = dscr->dscr_cmd1;
960 nbytes = dscr->dscr_cmd1;
961 /* Allow the caller to specifiy if an interrupt is generated */
962 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
963 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
964 ctp->chan_ptr->ddma_dbell = 0;
965
966 /* Get next descriptor pointer.
967 */
968 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
969
970 /* return something not zero.
971 */
972 return nbytes;
973}
974
835#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ 975#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
836 976
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index 0b912f739feb..ebf93bdbad14 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -488,7 +488,7 @@ void intc0_req0_irqdispatch(struct pt_regs *regs)
488 intc0_req0 |= au_readl(IC0_REQ0INT); 488 intc0_req0 |= au_readl(IC0_REQ0INT);
489 489
490 if (!intc0_req0) return; 490 if (!intc0_req0) return;
491 491#ifdef AU1000_USB_DEV_REQ_INT
492 /* 492 /*
493 * Because of the tight timing of SETUP token to reply 493 * Because of the tight timing of SETUP token to reply
494 * transactions, the USB devices-side packet complete 494 * transactions, the USB devices-side packet complete
@@ -499,7 +499,7 @@ void intc0_req0_irqdispatch(struct pt_regs *regs)
499 do_IRQ(AU1000_USB_DEV_REQ_INT, regs); 499 do_IRQ(AU1000_USB_DEV_REQ_INT, regs);
500 return; 500 return;
501 } 501 }
502 502#endif
503 irq = au_ffs(intc0_req0) - 1; 503 irq = au_ffs(intc0_req0) - 1;
504 intc0_req0 &= ~(1<<irq); 504 intc0_req0 &= ~(1<<irq);
505 do_IRQ(irq, regs); 505 do_IRQ(irq, regs);
diff --git a/arch/mips/au1000/common/usbdev.c b/arch/mips/au1000/common/usbdev.c
index 447a9a4612a8..0b21bed7ee55 100644
--- a/arch/mips/au1000/common/usbdev.c
+++ b/arch/mips/au1000/common/usbdev.c
@@ -1005,11 +1005,11 @@ process_ep0_receive (struct usb_dev* dev)
1005#endif 1005#endif
1006 dev->ep0_stage = SETUP_STAGE; 1006 dev->ep0_stage = SETUP_STAGE;
1007 break; 1007 break;
1008 } 1008 }
1009 1009
1010 spin_unlock(&ep0->lock); 1010 spin_unlock(&ep0->lock);
1011 // we're done processing the packet, free it 1011 // we're done processing the packet, free it
1012 kfree(pkt); 1012 kfree(pkt);
1013} 1013}
1014 1014
1015 1015
@@ -1072,8 +1072,7 @@ dma_done_ep0_intr(int irq, void *dev_id, struct pt_regs *regs)
1072 clear_dma_done1(ep0->indma); 1072 clear_dma_done1(ep0->indma);
1073 1073
1074 pkt = send_packet_complete(ep0); 1074 pkt = send_packet_complete(ep0);
1075 if (pkt) 1075 kfree(pkt);
1076 kfree(pkt);
1077 } 1076 }
1078 1077
1079 /* 1078 /*
@@ -1302,8 +1301,7 @@ usbdev_exit(void)
1302 endpoint_flush(ep); 1301 endpoint_flush(ep);
1303 } 1302 }
1304 1303
1305 if (usbdev.full_conf_desc) 1304 kfree(usbdev.full_conf_desc);
1306 kfree(usbdev.full_conf_desc);
1307} 1305}
1308 1306
1309int 1307int
diff --git a/arch/mips/au1000/pb1200/Makefile b/arch/mips/au1000/pb1200/Makefile
new file mode 100644
index 000000000000..22b673cf55af
--- /dev/null
+++ b/arch/mips/au1000/pb1200/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the Alchemy Semiconductor PB1200 board.
3#
4
5lib-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c
new file mode 100644
index 000000000000..209a07cb7321
--- /dev/null
+++ b/arch/mips/au1000/pb1200/board_setup.c
@@ -0,0 +1,187 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Pb1200/Db1200 board setup.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#include <linux/config.h>
27#include <linux/init.h>
28#include <linux/sched.h>
29#include <linux/ioport.h>
30#include <linux/mm.h>
31#include <linux/console.h>
32#include <linux/mc146818rtc.h>
33#include <linux/delay.h>
34
35#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
36#include <linux/ide.h>
37#endif
38
39#include <asm/cpu.h>
40#include <asm/bootinfo.h>
41#include <asm/irq.h>
42#include <asm/mipsregs.h>
43#include <asm/reboot.h>
44#include <asm/pgtable.h>
45#include <asm/mach-au1x00/au1000.h>
46#include <asm/mach-au1x00/au1xxx_dbdma.h>
47
48#ifdef CONFIG_MIPS_PB1200
49#include <asm/mach-pb1x00/pb1200.h>
50#endif
51
52#ifdef CONFIG_MIPS_DB1200
53#include <asm/mach-db1x00/db1200.h>
54#define PB1200_ETH_INT DB1200_ETH_INT
55#define PB1200_IDE_INT DB1200_IDE_INT
56#endif
57
58extern void _board_init_irq(void);
59extern void (*board_init_irq)(void);
60
61#ifdef CONFIG_BLK_DEV_IDE_AU1XXX
62extern struct ide_ops *ide_ops;
63extern struct ide_ops au1xxx_ide_ops;
64extern u32 au1xxx_ide_virtbase;
65extern u64 au1xxx_ide_physbase;
66extern int au1xxx_ide_irq;
67
68u32 led_base_addr;
69/* Ddma */
70chan_tab_t *ide_read_ch, *ide_write_ch;
71u32 au1xxx_ide_ddma_enable = 0, switch4ddma = 1; // PIO+ddma
72
73dbdev_tab_t new_dbdev_tab_element = { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 };
74#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX */
75
76void board_reset (void)
77{
78 bcsr->resets = 0;
79}
80
81void __init board_setup(void)
82{
83 char *argptr = NULL;
84 u32 pin_func;
85
86#if 0
87 /* Enable PSC1 SYNC for AC97. Normaly done in audio driver,
88 * but it is board specific code, so put it here.
89 */
90 pin_func = au_readl(SYS_PINFUNC);
91 au_sync();
92 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
93 au_writel(pin_func, SYS_PINFUNC);
94
95 au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */
96 au_sync();
97#endif
98
99#if defined( CONFIG_I2C_ALGO_AU1550 )
100 {
101 u32 freq0, clksrc;
102
103 /* Select SMBUS in CPLD */
104 bcsr->resets &= ~(BCSR_RESETS_PCS0MUX);
105
106 pin_func = au_readl(SYS_PINFUNC);
107 au_sync();
108 pin_func &= ~(3<<17 | 1<<4);
109 /* Set GPIOs correctly */
110 pin_func |= 2<<17;
111 au_writel(pin_func, SYS_PINFUNC);
112 au_sync();
113
114 /* The i2c driver depends on 50Mhz clock */
115 freq0 = au_readl(SYS_FREQCTRL0);
116 au_sync();
117 freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
118 freq0 |= (3<<SYS_FC_FRDIV1_BIT);
119 /* 396Mhz / (3+1)*2 == 49.5Mhz */
120 au_writel(freq0, SYS_FREQCTRL0);
121 au_sync();
122 freq0 |= SYS_FC_FE1;
123 au_writel(freq0, SYS_FREQCTRL0);
124 au_sync();
125
126 clksrc = au_readl(SYS_CLKSRC);
127 au_sync();
128 clksrc &= ~0x01f00000;
129 /* bit 22 is EXTCLK0 for PSC0 */
130 clksrc |= (0x3 << 22);
131 au_writel(clksrc, SYS_CLKSRC);
132 au_sync();
133 }
134#endif
135
136#ifdef CONFIG_FB_AU1200
137 argptr = prom_getcmdline();
138#ifdef CONFIG_MIPS_PB1200
139 strcat(argptr, " video=au1200fb:panel:s11");
140#endif
141#ifdef CONFIG_MIPS_DB1200
142 strcat(argptr, " video=au1200fb:panel:s7");
143#endif
144#endif
145
146#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
147 /*
148 * Iniz IDE parameters
149 */
150 ide_ops = &au1xxx_ide_ops;
151 au1xxx_ide_irq = PB1200_IDE_INT;
152 au1xxx_ide_physbase = AU1XXX_ATA_PHYS_ADDR;
153 au1xxx_ide_virtbase = KSEG1ADDR(AU1XXX_ATA_PHYS_ADDR);
154 /*
155 * change PIO or PIO+Ddma
156 * check the GPIO-5 pin condition. pb1200:s18_dot */
157 switch4ddma = (au_readl(SYS_PINSTATERD) & (1 << 5)) ? 1 : 0;
158#endif
159
160 /* The Pb1200 development board uses external MUX for PSC0 to
161 support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
162 */
163#if defined(CONFIG_AU1550_PSC_SPI) && defined(CONFIG_I2C_ALGO_AU1550)
164 #error I2C and SPI are mutually exclusive. Both are physically connected to PSC0.\
165 Refer to Pb1200/Db1200 documentation.
166#elif defined( CONFIG_AU1550_PSC_SPI )
167 bcsr->resets |= BCSR_RESETS_PCS0MUX;
168#elif defined( CONFIG_I2C_ALGO_AU1550 )
169 bcsr->resets &= (~BCSR_RESETS_PCS0MUX);
170#endif
171 au_sync();
172
173#ifdef CONFIG_MIPS_PB1200
174 printk("AMD Alchemy Pb1200 Board\n");
175#endif
176#ifdef CONFIG_MIPS_DB1200
177 printk("AMD Alchemy Db1200 Board\n");
178#endif
179#if 0
180 /* Setup Pb1200 External Interrupt Controller */
181 {
182 extern void (*board_init_irq)(void);
183 extern void _board_init_irq(void);
184 board_init_irq = _board_init_irq;
185 }
186#endif
187}
diff --git a/arch/mips/au1000/pb1200/init.c b/arch/mips/au1000/pb1200/init.c
new file mode 100644
index 000000000000..27f09e374e15
--- /dev/null
+++ b/arch/mips/au1000/pb1200/init.c
@@ -0,0 +1,69 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PB1200 board setup
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30#include <linux/init.h>
31#include <linux/mm.h>
32#include <linux/sched.h>
33#include <linux/bootmem.h>
34#include <asm/addrspace.h>
35#include <asm/bootinfo.h>
36#include <linux/string.h>
37#include <linux/kernel.h>
38
39int prom_argc;
40char **prom_argv, **prom_envp;
41extern void __init prom_init_cmdline(void);
42extern char *prom_getenv(char *envname);
43
44const char *get_system_type(void)
45{
46 return "Alchemy Pb1200";
47}
48
49void __init prom_init(void)
50{
51 unsigned char *memsize_str;
52 unsigned long memsize;
53
54 prom_argc = (int) fw_arg0;
55 prom_argv = (char **) fw_arg1;
56 prom_envp = (char **) fw_arg2;
57
58 mips_machgroup = MACH_GROUP_ALCHEMY;
59 mips_machtype = MACH_PB1200;
60
61 prom_init_cmdline();
62 memsize_str = prom_getenv("memsize");
63 if (!memsize_str) {
64 memsize = 0x08000000;
65 } else {
66 memsize = simple_strtol(memsize_str, NULL, 0);
67 }
68 add_memory_region(0, memsize, BOOT_MEM_RAM);
69}
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c
new file mode 100644
index 000000000000..2ec64e78aa01
--- /dev/null
+++ b/arch/mips/au1000/pb1200/irqmap.c
@@ -0,0 +1,180 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx irq map table
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25#include <linux/errno.h>
26#include <linux/init.h>
27#include <linux/irq.h>
28#include <linux/kernel_stat.h>
29#include <linux/module.h>
30#include <linux/signal.h>
31#include <linux/sched.h>
32#include <linux/types.h>
33#include <linux/interrupt.h>
34#include <linux/ioport.h>
35#include <linux/timex.h>
36#include <linux/slab.h>
37#include <linux/random.h>
38#include <linux/delay.h>
39
40#include <asm/bitops.h>
41#include <asm/bootinfo.h>
42#include <asm/io.h>
43#include <asm/mipsregs.h>
44#include <asm/system.h>
45#include <asm/mach-au1x00/au1000.h>
46
47#ifdef CONFIG_MIPS_PB1200
48#include <asm/mach-pb1x00/pb1200.h>
49#endif
50
51#ifdef CONFIG_MIPS_DB1200
52#include <asm/mach-db1x00/db1200.h>
53#define PB1200_INT_BEGIN DB1200_INT_BEGIN
54#define PB1200_INT_END DB1200_INT_END
55#endif
56
57au1xxx_irq_map_t au1xxx_irq_map[] = {
58 { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade
59};
60
61int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
62
63/*
64 * Support for External interrupts on the PbAu1200 Development platform.
65 */
66static volatile int pb1200_cascade_en=0;
67
68void pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs)
69{
70 unsigned short bisr = bcsr->int_status;
71 int extirq_nr = 0;
72
73 /* Clear all the edge interrupts. This has no effect on level */
74 bcsr->int_status = bisr;
75 for( ; bisr; bisr &= (bisr-1) )
76 {
77 extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr);
78 /* Ack and dispatch IRQ */
79 do_IRQ(extirq_nr,regs);
80 }
81}
82
83inline void pb1200_enable_irq(unsigned int irq_nr)
84{
85 bcsr->intset_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
86 bcsr->intset = 1<<(irq_nr - PB1200_INT_BEGIN);
87}
88
89inline void pb1200_disable_irq(unsigned int irq_nr)
90{
91 bcsr->intclr_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
92 bcsr->intclr = 1<<(irq_nr - PB1200_INT_BEGIN);
93}
94
95static unsigned int pb1200_startup_irq( unsigned int irq_nr )
96{
97 if (++pb1200_cascade_en == 1)
98 {
99 request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
100 0, "Pb1200 Cascade", &pb1200_cascade_handler );
101#ifdef CONFIG_MIPS_PB1200
102 /* We have a problem with CPLD rev3. Enable a workaround */
103 if( ((bcsr->whoami & BCSR_WHOAMI_CPLD)>>4) <= 3)
104 {
105 printk("\nWARNING!!!\n");
106 printk("\nWARNING!!!\n");
107 printk("\nWARNING!!!\n");
108 printk("\nWARNING!!!\n");
109 printk("\nWARNING!!!\n");
110 printk("\nWARNING!!!\n");
111 printk("Pb1200 must be at CPLD rev4. Please have Pb1200\n");
112 printk("updated to latest revision. This software will not\n");
113 printk("work on anything less than CPLD rev4\n");
114 printk("\nWARNING!!!\n");
115 printk("\nWARNING!!!\n");
116 printk("\nWARNING!!!\n");
117 printk("\nWARNING!!!\n");
118 printk("\nWARNING!!!\n");
119 printk("\nWARNING!!!\n");
120 while(1);
121 }
122#endif
123 }
124 pb1200_enable_irq(irq_nr);
125 return 0;
126}
127
128static void pb1200_shutdown_irq( unsigned int irq_nr )
129{
130 pb1200_disable_irq(irq_nr);
131 if (--pb1200_cascade_en == 0)
132 {
133 free_irq(AU1000_GPIO_7,&pb1200_cascade_handler );
134 }
135 return;
136}
137
138static inline void pb1200_mask_and_ack_irq(unsigned int irq_nr)
139{
140 pb1200_disable_irq( irq_nr );
141}
142
143static void pb1200_end_irq(unsigned int irq_nr)
144{
145 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
146 pb1200_enable_irq(irq_nr);
147 }
148}
149
150static struct hw_interrupt_type external_irq_type =
151{
152#ifdef CONFIG_MIPS_PB1200
153 "Pb1200 Ext",
154#endif
155#ifdef CONFIG_MIPS_DB1200
156 "Db1200 Ext",
157#endif
158 pb1200_startup_irq,
159 pb1200_shutdown_irq,
160 pb1200_enable_irq,
161 pb1200_disable_irq,
162 pb1200_mask_and_ack_irq,
163 pb1200_end_irq,
164 NULL
165};
166
167void _board_init_irq(void)
168{
169 int irq_nr;
170
171 for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++)
172 {
173 irq_desc[irq_nr].handler = &external_irq_type;
174 pb1200_disable_irq(irq_nr);
175 }
176
177 /* GPIO_7 can not be hooked here, so it is hooked upon first
178 request of any source attached to the cascade */
179}
180
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 7685f8baf3f0..66c2a2788ffe 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -116,6 +116,8 @@ static inline void check_wait(void)
116 case CPU_AU1000: 116 case CPU_AU1000:
117 case CPU_AU1100: 117 case CPU_AU1100:
118 case CPU_AU1500: 118 case CPU_AU1500:
119 case CPU_AU1550:
120 case CPU_AU1200:
119 if (au1k_wait_ptr != NULL) { 121 if (au1k_wait_ptr != NULL) {
120 cpu_wait = au1k_wait_ptr; 122 cpu_wait = au1k_wait_ptr;
121 printk(" available.\n"); 123 printk(" available.\n");
@@ -505,6 +507,9 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
505 case 3: 507 case 3:
506 c->cputype = CPU_AU1550; 508 c->cputype = CPU_AU1550;
507 break; 509 break;
510 case 4:
511 c->cputype = CPU_AU1200;
512 break;
508 default: 513 default:
509 panic("Unknown Au Core!"); 514 panic("Unknown Au Core!");
510 break; 515 break;
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 760fcdfea18e..13888520d41c 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -60,6 +60,9 @@ static const char *cpu_name[] = {
60 [CPU_TX3927] "TX3927", 60 [CPU_TX3927] "TX3927",
61 [CPU_AU1000] "Au1000", 61 [CPU_AU1000] "Au1000",
62 [CPU_AU1500] "Au1500", 62 [CPU_AU1500] "Au1500",
63 [CPU_AU1100] "Au1100",
64 [CPU_AU1550] "Au1550",
65 [CPU_AU1200] "Au1200",
63 [CPU_4KEC] "MIPS 4KEc", 66 [CPU_4KEC] "MIPS 4KEc",
64 [CPU_4KSC] "MIPS 4KSc", 67 [CPU_4KSC] "MIPS 4KSc",
65 [CPU_VR41XX] "NEC Vr41xx", 68 [CPU_VR41XX] "NEC Vr41xx",
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 03100b8a45d9..e26dd829bf20 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1036,7 +1036,11 @@ static void __init probe_pcache(void)
1036 c->icache.flags |= MIPS_CACHE_VTAG; 1036 c->icache.flags |= MIPS_CACHE_VTAG;
1037 break; 1037 break;
1038 1038
1039 case CPU_AU1000:
1039 case CPU_AU1500: 1040 case CPU_AU1500:
1041 case CPU_AU1100:
1042 case CPU_AU1550:
1043 case CPU_AU1200:
1040 c->icache.flags |= MIPS_CACHE_IC_F_DC; 1044 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1041 break; 1045 break;
1042 } 1046 }
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 6569be3983c7..248537cebc89 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -840,6 +840,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
840 case CPU_AU1100: 840 case CPU_AU1100:
841 case CPU_AU1500: 841 case CPU_AU1500:
842 case CPU_AU1550: 842 case CPU_AU1550:
843 case CPU_AU1200:
843 i_nop(p); 844 i_nop(p);
844 tlbw(p); 845 tlbw(p);
845 break; 846 break;
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index b1e57d783604..404856e6b82d 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -177,6 +177,8 @@
177#define MACH_MTX1 7 /* 4G MTX-1 Au1500-based board */ 177#define MACH_MTX1 7 /* 4G MTX-1 Au1500-based board */
178#define MACH_PB1550 8 /* Au1550-based eval board */ 178#define MACH_PB1550 8 /* Au1550-based eval board */
179#define MACH_DB1550 9 /* Au1550-based eval board */ 179#define MACH_DB1550 9 /* Au1550-based eval board */
180#define MACH_PB1200 10 /* Au1200-based eval board */
181#define MACH_DB1200 11 /* Au1200-based eval board */
180 182
181/* 183/*
182 * Valid machtype for group NEC_VR41XX 184 * Valid machtype for group NEC_VR41XX
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index c60281799801..8e167bfd40b1 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -182,7 +182,8 @@
182#define CPU_VR4133 56 182#define CPU_VR4133 56
183#define CPU_AU1550 57 183#define CPU_AU1550 57
184#define CPU_24K 58 184#define CPU_24K 58
185#define CPU_LAST 58 185#define CPU_AU1200 59
186#define CPU_LAST 59
186 187
187/* 188/*
188 * ISA Level encodings 189 * ISA Level encodings
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 148bae2fa7d3..28b04a5f67cf 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -162,27 +162,355 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
162#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) 162#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
163#endif 163#endif
164 164
165/* SDRAM Controller */ 165/*
166 * SDRAM Register Offsets
167 */
166#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100) 168#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
167#define MEM_SDMODE0 0xB4000000 169#define MEM_SDMODE0 (0x0000)
168#define MEM_SDMODE1 0xB4000004 170#define MEM_SDMODE1 (0x0004)
169#define MEM_SDMODE2 0xB4000008 171#define MEM_SDMODE2 (0x0008)
172#define MEM_SDADDR0 (0x000C)
173#define MEM_SDADDR1 (0x0010)
174#define MEM_SDADDR2 (0x0014)
175#define MEM_SDREFCFG (0x0018)
176#define MEM_SDPRECMD (0x001C)
177#define MEM_SDAUTOREF (0x0020)
178#define MEM_SDWRMD0 (0x0024)
179#define MEM_SDWRMD1 (0x0028)
180#define MEM_SDWRMD2 (0x002C)
181#define MEM_SDSLEEP (0x0030)
182#define MEM_SDSMCKE (0x0034)
183
184#ifndef ASSEMBLER
185/*typedef volatile struct
186{
187 uint32 sdmode0;
188 uint32 sdmode1;
189 uint32 sdmode2;
190 uint32 sdaddr0;
191 uint32 sdaddr1;
192 uint32 sdaddr2;
193 uint32 sdrefcfg;
194 uint32 sdautoref;
195 uint32 sdwrmd0;
196 uint32 sdwrmd1;
197 uint32 sdwrmd2;
198 uint32 sdsleep;
199 uint32 sdsmcke;
200
201} AU1X00_SDRAM;*/
202#endif
203
204/*
205 * MEM_SDMODE register content definitions
206 */
207#define MEM_SDMODE_F (1<<22)
208#define MEM_SDMODE_SR (1<<21)
209#define MEM_SDMODE_BS (1<<20)
210#define MEM_SDMODE_RS (3<<18)
211#define MEM_SDMODE_CS (7<<15)
212#define MEM_SDMODE_TRAS (15<<11)
213#define MEM_SDMODE_TMRD (3<<9)
214#define MEM_SDMODE_TWR (3<<7)
215#define MEM_SDMODE_TRP (3<<5)
216#define MEM_SDMODE_TRCD (3<<3)
217#define MEM_SDMODE_TCL (7<<0)
218
219#define MEM_SDMODE_BS_2Bank (0<<20)
220#define MEM_SDMODE_BS_4Bank (1<<20)
221#define MEM_SDMODE_RS_11Row (0<<18)
222#define MEM_SDMODE_RS_12Row (1<<18)
223#define MEM_SDMODE_RS_13Row (2<<18)
224#define MEM_SDMODE_RS_N(N) ((N)<<18)
225#define MEM_SDMODE_CS_7Col (0<<15)
226#define MEM_SDMODE_CS_8Col (1<<15)
227#define MEM_SDMODE_CS_9Col (2<<15)
228#define MEM_SDMODE_CS_10Col (3<<15)
229#define MEM_SDMODE_CS_11Col (4<<15)
230#define MEM_SDMODE_CS_N(N) ((N)<<15)
231#define MEM_SDMODE_TRAS_N(N) ((N)<<11)
232#define MEM_SDMODE_TMRD_N(N) ((N)<<9)
233#define MEM_SDMODE_TWR_N(N) ((N)<<7)
234#define MEM_SDMODE_TRP_N(N) ((N)<<5)
235#define MEM_SDMODE_TRCD_N(N) ((N)<<3)
236#define MEM_SDMODE_TCL_N(N) ((N)<<0)
237
238/*
239 * MEM_SDADDR register contents definitions
240 */
241#define MEM_SDADDR_E (1<<20)
242#define MEM_SDADDR_CSBA (0x03FF<<10)
243#define MEM_SDADDR_CSMASK (0x03FF<<0)
244#define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12)
245#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22)
246
247/*
248 * MEM_SDREFCFG register content definitions
249 */
250#define MEM_SDREFCFG_TRC (15<<28)
251#define MEM_SDREFCFG_TRPM (3<<26)
252#define MEM_SDREFCFG_E (1<<25)
253#define MEM_SDREFCFG_RE (0x1ffffff<<0)
254#define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC)
255#define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM)
256#define MEM_SDREFCFG_REF_N(N) (N)
257#endif
170 258
171#define MEM_SDADDR0 0xB400000C 259/***********************************************************************/
172#define MEM_SDADDR1 0xB4000010
173#define MEM_SDADDR2 0xB4000014
174 260
175#define MEM_SDREFCFG 0xB4000018 261/*
176#define MEM_SDPRECMD 0xB400001C 262 * Au1550 SDRAM Register Offsets
177#define MEM_SDAUTOREF 0xB4000020 263 */
178 264
179#define MEM_SDWRMD0 0xB4000024 265/***********************************************************************/
180#define MEM_SDWRMD1 0xB4000028
181#define MEM_SDWRMD2 0xB400002C
182 266
183#define MEM_SDSLEEP 0xB4000030 267#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
184#define MEM_SDSMCKE 0xB4000034 268#define MEM_SDMODE0 (0x0800)
269#define MEM_SDMODE1 (0x0808)
270#define MEM_SDMODE2 (0x0810)
271#define MEM_SDADDR0 (0x0820)
272#define MEM_SDADDR1 (0x0828)
273#define MEM_SDADDR2 (0x0830)
274#define MEM_SDCONFIGA (0x0840)
275#define MEM_SDCONFIGB (0x0848)
276#define MEM_SDSTAT (0x0850)
277#define MEM_SDERRADDR (0x0858)
278#define MEM_SDSTRIDE0 (0x0860)
279#define MEM_SDSTRIDE1 (0x0868)
280#define MEM_SDSTRIDE2 (0x0870)
281#define MEM_SDWRMD0 (0x0880)
282#define MEM_SDWRMD1 (0x0888)
283#define MEM_SDWRMD2 (0x0890)
284#define MEM_SDPRECMD (0x08C0)
285#define MEM_SDAUTOREF (0x08C8)
286#define MEM_SDSREF (0x08D0)
287#define MEM_SDSLEEP MEM_SDSREF
288
289#ifndef ASSEMBLER
290/*typedef volatile struct
291{
292 uint32 sdmode0;
293 uint32 reserved0;
294 uint32 sdmode1;
295 uint32 reserved1;
296 uint32 sdmode2;
297 uint32 reserved2[3];
298 uint32 sdaddr0;
299 uint32 reserved3;
300 uint32 sdaddr1;
301 uint32 reserved4;
302 uint32 sdaddr2;
303 uint32 reserved5[3];
304 uint32 sdconfiga;
305 uint32 reserved6;
306 uint32 sdconfigb;
307 uint32 reserved7;
308 uint32 sdstat;
309 uint32 reserved8;
310 uint32 sderraddr;
311 uint32 reserved9;
312 uint32 sdstride0;
313 uint32 reserved10;
314 uint32 sdstride1;
315 uint32 reserved11;
316 uint32 sdstride2;
317 uint32 reserved12[3];
318 uint32 sdwrmd0;
319 uint32 reserved13;
320 uint32 sdwrmd1;
321 uint32 reserved14;
322 uint32 sdwrmd2;
323 uint32 reserved15[11];
324 uint32 sdprecmd;
325 uint32 reserved16;
326 uint32 sdautoref;
327 uint32 reserved17;
328 uint32 sdsref;
329
330} AU1550_SDRAM;*/
185#endif 331#endif
332#endif
333
334/*
335 * Physical base addresses for integrated peripherals
336 */
337
338#ifdef CONFIG_SOC_AU1000
339#define MEM_PHYS_ADDR 0x14000000
340#define STATIC_MEM_PHYS_ADDR 0x14001000
341#define DMA0_PHYS_ADDR 0x14002000
342#define DMA1_PHYS_ADDR 0x14002100
343#define DMA2_PHYS_ADDR 0x14002200
344#define DMA3_PHYS_ADDR 0x14002300
345#define DMA4_PHYS_ADDR 0x14002400
346#define DMA5_PHYS_ADDR 0x14002500
347#define DMA6_PHYS_ADDR 0x14002600
348#define DMA7_PHYS_ADDR 0x14002700
349#define IC0_PHYS_ADDR 0x10400000
350#define IC1_PHYS_ADDR 0x11800000
351#define AC97_PHYS_ADDR 0x10000000
352#define USBH_PHYS_ADDR 0x10100000
353#define USBD_PHYS_ADDR 0x10200000
354#define IRDA_PHYS_ADDR 0x10300000
355#define MAC0_PHYS_ADDR 0x10500000
356#define MAC1_PHYS_ADDR 0x10510000
357#define MACEN_PHYS_ADDR 0x10520000
358#define MACDMA0_PHYS_ADDR 0x14004000
359#define MACDMA1_PHYS_ADDR 0x14004200
360#define I2S_PHYS_ADDR 0x11000000
361#define UART0_PHYS_ADDR 0x11100000
362#define UART1_PHYS_ADDR 0x11200000
363#define UART2_PHYS_ADDR 0x11300000
364#define UART3_PHYS_ADDR 0x11400000
365#define SSI0_PHYS_ADDR 0x11600000
366#define SSI1_PHYS_ADDR 0x11680000
367#define SYS_PHYS_ADDR 0x11900000
368#define PCMCIA_IO_PHYS_ADDR 0xF00000000
369#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
370#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
371#endif
372
373/********************************************************************/
374
375#ifdef CONFIG_SOC_AU1500
376#define MEM_PHYS_ADDR 0x14000000
377#define STATIC_MEM_PHYS_ADDR 0x14001000
378#define DMA0_PHYS_ADDR 0x14002000
379#define DMA1_PHYS_ADDR 0x14002100
380#define DMA2_PHYS_ADDR 0x14002200
381#define DMA3_PHYS_ADDR 0x14002300
382#define DMA4_PHYS_ADDR 0x14002400
383#define DMA5_PHYS_ADDR 0x14002500
384#define DMA6_PHYS_ADDR 0x14002600
385#define DMA7_PHYS_ADDR 0x14002700
386#define IC0_PHYS_ADDR 0x10400000
387#define IC1_PHYS_ADDR 0x11800000
388#define AC97_PHYS_ADDR 0x10000000
389#define USBH_PHYS_ADDR 0x10100000
390#define USBD_PHYS_ADDR 0x10200000
391#define PCI_PHYS_ADDR 0x14005000
392#define MAC0_PHYS_ADDR 0x11500000
393#define MAC1_PHYS_ADDR 0x11510000
394#define MACEN_PHYS_ADDR 0x11520000
395#define MACDMA0_PHYS_ADDR 0x14004000
396#define MACDMA1_PHYS_ADDR 0x14004200
397#define I2S_PHYS_ADDR 0x11000000
398#define UART0_PHYS_ADDR 0x11100000
399#define UART3_PHYS_ADDR 0x11400000
400#define GPIO2_PHYS_ADDR 0x11700000
401#define SYS_PHYS_ADDR 0x11900000
402#define PCI_MEM_PHYS_ADDR 0x400000000
403#define PCI_IO_PHYS_ADDR 0x500000000
404#define PCI_CONFIG0_PHYS_ADDR 0x600000000
405#define PCI_CONFIG1_PHYS_ADDR 0x680000000
406#define PCMCIA_IO_PHYS_ADDR 0xF00000000
407#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
408#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
409#endif
410
411/********************************************************************/
412
413#ifdef CONFIG_SOC_AU1100
414#define MEM_PHYS_ADDR 0x14000000
415#define STATIC_MEM_PHYS_ADDR 0x14001000
416#define DMA0_PHYS_ADDR 0x14002000
417#define DMA1_PHYS_ADDR 0x14002100
418#define DMA2_PHYS_ADDR 0x14002200
419#define DMA3_PHYS_ADDR 0x14002300
420#define DMA4_PHYS_ADDR 0x14002400
421#define DMA5_PHYS_ADDR 0x14002500
422#define DMA6_PHYS_ADDR 0x14002600
423#define DMA7_PHYS_ADDR 0x14002700
424#define IC0_PHYS_ADDR 0x10400000
425#define SD0_PHYS_ADDR 0x10600000
426#define SD1_PHYS_ADDR 0x10680000
427#define IC1_PHYS_ADDR 0x11800000
428#define AC97_PHYS_ADDR 0x10000000
429#define USBH_PHYS_ADDR 0x10100000
430#define USBD_PHYS_ADDR 0x10200000
431#define IRDA_PHYS_ADDR 0x10300000
432#define MAC0_PHYS_ADDR 0x10500000
433#define MACEN_PHYS_ADDR 0x10520000
434#define MACDMA0_PHYS_ADDR 0x14004000
435#define MACDMA1_PHYS_ADDR 0x14004200
436#define I2S_PHYS_ADDR 0x11000000
437#define UART0_PHYS_ADDR 0x11100000
438#define UART1_PHYS_ADDR 0x11200000
439#define UART3_PHYS_ADDR 0x11400000
440#define SSI0_PHYS_ADDR 0x11600000
441#define SSI1_PHYS_ADDR 0x11680000
442#define GPIO2_PHYS_ADDR 0x11700000
443#define SYS_PHYS_ADDR 0x11900000
444#define LCD_PHYS_ADDR 0x15000000
445#define PCMCIA_IO_PHYS_ADDR 0xF00000000
446#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
447#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
448#endif
449
450/***********************************************************************/
451
452#ifdef CONFIG_SOC_AU1550
453#define MEM_PHYS_ADDR 0x14000000
454#define STATIC_MEM_PHYS_ADDR 0x14001000
455#define IC0_PHYS_ADDR 0x10400000
456#define IC1_PHYS_ADDR 0x11800000
457#define USBH_PHYS_ADDR 0x14020000
458#define USBD_PHYS_ADDR 0x10200000
459#define PCI_PHYS_ADDR 0x14005000
460#define MAC0_PHYS_ADDR 0x10500000
461#define MAC1_PHYS_ADDR 0x10510000
462#define MACEN_PHYS_ADDR 0x10520000
463#define MACDMA0_PHYS_ADDR 0x14004000
464#define MACDMA1_PHYS_ADDR 0x14004200
465#define UART0_PHYS_ADDR 0x11100000
466#define UART1_PHYS_ADDR 0x11200000
467#define UART3_PHYS_ADDR 0x11400000
468#define GPIO2_PHYS_ADDR 0x11700000
469#define SYS_PHYS_ADDR 0x11900000
470#define DDMA_PHYS_ADDR 0x14002000
471#define PE_PHYS_ADDR 0x14008000
472#define PSC0_PHYS_ADDR 0x11A00000
473#define PSC1_PHYS_ADDR 0x11B00000
474#define PSC2_PHYS_ADDR 0x10A00000
475#define PSC3_PHYS_ADDR 0x10B00000
476#define PCI_MEM_PHYS_ADDR 0x400000000
477#define PCI_IO_PHYS_ADDR 0x500000000
478#define PCI_CONFIG0_PHYS_ADDR 0x600000000
479#define PCI_CONFIG1_PHYS_ADDR 0x680000000
480#define PCMCIA_IO_PHYS_ADDR 0xF00000000
481#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
482#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
483#endif
484
485/***********************************************************************/
486
487#ifdef CONFIG_SOC_AU1200
488#define MEM_PHYS_ADDR 0x14000000
489#define STATIC_MEM_PHYS_ADDR 0x14001000
490#define AES_PHYS_ADDR 0x10300000
491#define CIM_PHYS_ADDR 0x14004000
492#define IC0_PHYS_ADDR 0x10400000
493#define IC1_PHYS_ADDR 0x11800000
494#define USBM_PHYS_ADDR 0x14020000
495#define USBH_PHYS_ADDR 0x14020100
496#define UART0_PHYS_ADDR 0x11100000
497#define UART1_PHYS_ADDR 0x11200000
498#define GPIO2_PHYS_ADDR 0x11700000
499#define SYS_PHYS_ADDR 0x11900000
500#define DDMA_PHYS_ADDR 0x14002000
501#define PSC0_PHYS_ADDR 0x11A00000
502#define PSC1_PHYS_ADDR 0x11B00000
503#define PCMCIA_IO_PHYS_ADDR 0xF00000000
504#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
505#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
506#define SD0_PHYS_ADDR 0x10600000
507#define SD1_PHYS_ADDR 0x10680000
508#define LCD_PHYS_ADDR 0x15000000
509#define SWCNT_PHYS_ADDR 0x1110010C
510#define MAEFE_PHYS_ADDR 0x14012000
511#define MAEBE_PHYS_ADDR 0x14010000
512#endif
513
186 514
187/* Static Bus Controller */ 515/* Static Bus Controller */
188#define MEM_STCFG0 0xB4001000 516#define MEM_STCFG0 0xB4001000
@@ -369,7 +697,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
369#define AU1000_MAC0_ENABLE 0xB0520000 697#define AU1000_MAC0_ENABLE 0xB0520000
370#define AU1000_MAC1_ENABLE 0xB0520004 698#define AU1000_MAC1_ENABLE 0xB0520004
371#define NUM_ETH_INTERFACES 2 699#define NUM_ETH_INTERFACES 2
372#endif // CONFIG_SOC_AU1000 700#endif /* CONFIG_SOC_AU1000 */
373 701
374/* Au1500 */ 702/* Au1500 */
375#ifdef CONFIG_SOC_AU1500 703#ifdef CONFIG_SOC_AU1500
@@ -440,7 +768,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
440#define AU1500_MAC0_ENABLE 0xB1520000 768#define AU1500_MAC0_ENABLE 0xB1520000
441#define AU1500_MAC1_ENABLE 0xB1520004 769#define AU1500_MAC1_ENABLE 0xB1520004
442#define NUM_ETH_INTERFACES 2 770#define NUM_ETH_INTERFACES 2
443#endif // CONFIG_SOC_AU1500 771#endif /* CONFIG_SOC_AU1500 */
444 772
445/* Au1100 */ 773/* Au1100 */
446#ifdef CONFIG_SOC_AU1100 774#ifdef CONFIG_SOC_AU1100
@@ -485,6 +813,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
485#define AU1000_GPIO_13 45 813#define AU1000_GPIO_13 45
486#define AU1000_GPIO_14 46 814#define AU1000_GPIO_14 46
487#define AU1000_GPIO_15 47 815#define AU1000_GPIO_15 47
816#define AU1000_GPIO_16 48
817#define AU1000_GPIO_17 49
818#define AU1000_GPIO_18 50
819#define AU1000_GPIO_19 51
820#define AU1000_GPIO_20 52
821#define AU1000_GPIO_21 53
822#define AU1000_GPIO_22 54
823#define AU1000_GPIO_23 55
824#define AU1000_GPIO_24 56
825#define AU1000_GPIO_25 57
826#define AU1000_GPIO_26 58
827#define AU1000_GPIO_27 59
828#define AU1000_GPIO_28 60
829#define AU1000_GPIO_29 61
830#define AU1000_GPIO_30 62
831#define AU1000_GPIO_31 63
488 832
489#define UART0_ADDR 0xB1100000 833#define UART0_ADDR 0xB1100000
490#define UART1_ADDR 0xB1200000 834#define UART1_ADDR 0xB1200000
@@ -496,7 +840,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
496#define AU1100_ETH0_BASE 0xB0500000 840#define AU1100_ETH0_BASE 0xB0500000
497#define AU1100_MAC0_ENABLE 0xB0520000 841#define AU1100_MAC0_ENABLE 0xB0520000
498#define NUM_ETH_INTERFACES 1 842#define NUM_ETH_INTERFACES 1
499#endif // CONFIG_SOC_AU1100 843#endif /* CONFIG_SOC_AU1100 */
500 844
501#ifdef CONFIG_SOC_AU1550 845#ifdef CONFIG_SOC_AU1550
502#define AU1550_UART0_INT 0 846#define AU1550_UART0_INT 0
@@ -513,14 +857,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
513#define AU1550_PSC1_INT 11 857#define AU1550_PSC1_INT 11
514#define AU1550_PSC2_INT 12 858#define AU1550_PSC2_INT 12
515#define AU1550_PSC3_INT 13 859#define AU1550_PSC3_INT 13
516#define AU1550_TOY_INT 14 860#define AU1000_TOY_INT 14
517#define AU1550_TOY_MATCH0_INT 15 861#define AU1000_TOY_MATCH0_INT 15
518#define AU1550_TOY_MATCH1_INT 16 862#define AU1000_TOY_MATCH1_INT 16
519#define AU1550_TOY_MATCH2_INT 17 863#define AU1000_TOY_MATCH2_INT 17
520#define AU1550_RTC_INT 18 864#define AU1000_RTC_INT 18
521#define AU1550_RTC_MATCH0_INT 19 865#define AU1000_RTC_MATCH0_INT 19
522#define AU1550_RTC_MATCH1_INT 20 866#define AU1000_RTC_MATCH1_INT 20
523#define AU1550_RTC_MATCH2_INT 21 867#define AU1000_RTC_MATCH2_INT 21
524#define AU1550_NAND_INT 23 868#define AU1550_NAND_INT 23
525#define AU1550_USB_DEV_REQ_INT 24 869#define AU1550_USB_DEV_REQ_INT 24
526#define AU1550_USB_DEV_SUS_INT 25 870#define AU1550_USB_DEV_SUS_INT 25
@@ -575,7 +919,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
575#define AU1550_MAC0_ENABLE 0xB0520000 919#define AU1550_MAC0_ENABLE 0xB0520000
576#define AU1550_MAC1_ENABLE 0xB0520004 920#define AU1550_MAC1_ENABLE 0xB0520004
577#define NUM_ETH_INTERFACES 2 921#define NUM_ETH_INTERFACES 2
578#endif // CONFIG_SOC_AU1550 922#endif /* CONFIG_SOC_AU1550 */
579 923
580#ifdef CONFIG_SOC_AU1200 924#ifdef CONFIG_SOC_AU1200
581#define AU1200_UART0_INT 0 925#define AU1200_UART0_INT 0
@@ -592,14 +936,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
592#define AU1200_PSC1_INT 11 936#define AU1200_PSC1_INT 11
593#define AU1200_AES_INT 12 937#define AU1200_AES_INT 12
594#define AU1200_CAMERA_INT 13 938#define AU1200_CAMERA_INT 13
595#define AU1200_TOY_INT 14 939#define AU1000_TOY_INT 14
596#define AU1200_TOY_MATCH0_INT 15 940#define AU1000_TOY_MATCH0_INT 15
597#define AU1200_TOY_MATCH1_INT 16 941#define AU1000_TOY_MATCH1_INT 16
598#define AU1200_TOY_MATCH2_INT 17 942#define AU1000_TOY_MATCH2_INT 17
599#define AU1200_RTC_INT 18 943#define AU1000_RTC_INT 18
600#define AU1200_RTC_MATCH0_INT 19 944#define AU1000_RTC_MATCH0_INT 19
601#define AU1200_RTC_MATCH1_INT 20 945#define AU1000_RTC_MATCH1_INT 20
602#define AU1200_RTC_MATCH2_INT 21 946#define AU1000_RTC_MATCH2_INT 21
603#define AU1200_NAND_INT 23 947#define AU1200_NAND_INT 23
604#define AU1200_GPIO_204 24 948#define AU1200_GPIO_204 24
605#define AU1200_GPIO_205 25 949#define AU1200_GPIO_205 25
@@ -607,6 +951,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
607#define AU1200_GPIO_207 27 951#define AU1200_GPIO_207 27
608#define AU1200_GPIO_208_215 28 // Logical OR of 208:215 952#define AU1200_GPIO_208_215 28 // Logical OR of 208:215
609#define AU1200_USB_INT 29 953#define AU1200_USB_INT 29
954#define AU1000_USB_HOST_INT AU1200_USB_INT
610#define AU1200_LCD_INT 30 955#define AU1200_LCD_INT 30
611#define AU1200_MAE_BOTH_INT 31 956#define AU1200_MAE_BOTH_INT 31
612#define AU1000_GPIO_0 32 957#define AU1000_GPIO_0 32
@@ -645,21 +990,36 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
645#define UART0_ADDR 0xB1100000 990#define UART0_ADDR 0xB1100000
646#define UART1_ADDR 0xB1200000 991#define UART1_ADDR 0xB1200000
647 992
648#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap 993#define USB_UOC_BASE 0x14020020
649#define USB_HOST_CONFIG 0xB4027ffc 994#define USB_UOC_LEN 0x20
650 995#define USB_OHCI_BASE 0x14020100
651// these are here for prototyping on au1550 (do not exist on au1200) 996#define USB_OHCI_LEN 0x100
652#define AU1200_ETH0_BASE 0xB0500000 997#define USB_EHCI_BASE 0x14020200
653#define AU1200_ETH1_BASE 0xB0510000 998#define USB_EHCI_LEN 0x100
654#define AU1200_MAC0_ENABLE 0xB0520000 999#define USB_UDC_BASE 0x14022000
655#define AU1200_MAC1_ENABLE 0xB0520004 1000#define USB_UDC_LEN 0x2000
656#define NUM_ETH_INTERFACES 2 1001#define USB_MSR_BASE 0xB4020000
657#endif // CONFIG_SOC_AU1200 1002#define USB_MSR_MCFG 4
1003#define USBMSRMCFG_OMEMEN 0
1004#define USBMSRMCFG_OBMEN 1
1005#define USBMSRMCFG_EMEMEN 2
1006#define USBMSRMCFG_EBMEN 3
1007#define USBMSRMCFG_DMEMEN 4
1008#define USBMSRMCFG_DBMEN 5
1009#define USBMSRMCFG_GMEMEN 6
1010#define USBMSRMCFG_OHCCLKEN 16
1011#define USBMSRMCFG_EHCCLKEN 17
1012#define USBMSRMCFG_UDCCLKEN 18
1013#define USBMSRMCFG_PHYPLLEN 19
1014#define USBMSRMCFG_RDCOMB 30
1015#define USBMSRMCFG_PFEN 31
1016
1017#endif /* CONFIG_SOC_AU1200 */
658 1018
659#define AU1000_LAST_INTC0_INT 31 1019#define AU1000_LAST_INTC0_INT 31
1020#define AU1000_LAST_INTC1_INT 63
660#define AU1000_MAX_INTR 63 1021#define AU1000_MAX_INTR 63
661 1022
662
663/* Programmable Counters 0 and 1 */ 1023/* Programmable Counters 0 and 1 */
664#define SYS_BASE 0xB1900000 1024#define SYS_BASE 0xB1900000
665#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) 1025#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
@@ -730,6 +1090,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
730 #define I2S_CONTROL_D (1<<1) 1090 #define I2S_CONTROL_D (1<<1)
731 #define I2S_CONTROL_CE (1<<0) 1091 #define I2S_CONTROL_CE (1<<0)
732 1092
1093#ifndef CONFIG_SOC_AU1200
1094
733/* USB Host Controller */ 1095/* USB Host Controller */
734#define USB_OHCI_LEN 0x00100000 1096#define USB_OHCI_LEN 0x00100000
735 1097
@@ -775,6 +1137,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
775 #define USBDEV_ENABLE (1<<1) 1137 #define USBDEV_ENABLE (1<<1)
776 #define USBDEV_CE (1<<0) 1138 #define USBDEV_CE (1<<0)
777 1139
1140#endif /* !CONFIG_SOC_AU1200 */
1141
778/* Ethernet Controllers */ 1142/* Ethernet Controllers */
779 1143
780/* 4 byte offsets from AU1000_ETH_BASE */ 1144/* 4 byte offsets from AU1000_ETH_BASE */
@@ -1173,6 +1537,37 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1173 #define SYS_PF_PSC1_S1 (1 << 1) 1537 #define SYS_PF_PSC1_S1 (1 << 1)
1174 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 1538 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1175 1539
1540/* Au1200 Only */
1541#ifdef CONFIG_SOC_AU1200
1542#define SYS_PINFUNC_DMA (1<<31)
1543#define SYS_PINFUNC_S0A (1<<30)
1544#define SYS_PINFUNC_S1A (1<<29)
1545#define SYS_PINFUNC_LP0 (1<<28)
1546#define SYS_PINFUNC_LP1 (1<<27)
1547#define SYS_PINFUNC_LD16 (1<<26)
1548#define SYS_PINFUNC_LD8 (1<<25)
1549#define SYS_PINFUNC_LD1 (1<<24)
1550#define SYS_PINFUNC_LD0 (1<<23)
1551#define SYS_PINFUNC_P1A (3<<21)
1552#define SYS_PINFUNC_P1B (1<<20)
1553#define SYS_PINFUNC_FS3 (1<<19)
1554#define SYS_PINFUNC_P0A (3<<17)
1555#define SYS_PINFUNC_CS (1<<16)
1556#define SYS_PINFUNC_CIM (1<<15)
1557#define SYS_PINFUNC_P1C (1<<14)
1558#define SYS_PINFUNC_U1T (1<<12)
1559#define SYS_PINFUNC_U1R (1<<11)
1560#define SYS_PINFUNC_EX1 (1<<10)
1561#define SYS_PINFUNC_EX0 (1<<9)
1562#define SYS_PINFUNC_U0R (1<<8)
1563#define SYS_PINFUNC_MC (1<<7)
1564#define SYS_PINFUNC_S0B (1<<6)
1565#define SYS_PINFUNC_S0C (1<<5)
1566#define SYS_PINFUNC_P0B (1<<4)
1567#define SYS_PINFUNC_U0T (1<<3)
1568#define SYS_PINFUNC_S1B (1<<2)
1569#endif
1570
1176#define SYS_TRIOUTRD 0xB1900100 1571#define SYS_TRIOUTRD 0xB1900100
1177#define SYS_TRIOUTCLR 0xB1900100 1572#define SYS_TRIOUTCLR 0xB1900100
1178#define SYS_OUTPUTRD 0xB1900108 1573#define SYS_OUTPUTRD 0xB1900108
@@ -1300,7 +1695,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1300#define SD1_XMIT_FIFO 0xB0680000 1695#define SD1_XMIT_FIFO 0xB0680000
1301#define SD1_RECV_FIFO 0xB0680004 1696#define SD1_RECV_FIFO 0xB0680004
1302 1697
1303
1304#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) 1698#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1305/* Au1500 PCI Controller */ 1699/* Au1500 PCI Controller */
1306#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr 1700#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
@@ -1363,36 +1757,77 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1363 _ctl_; }) 1757 _ctl_; })
1364 1758
1365 1759
1366#else /* Au1000 and Au1100 */ 1760#else /* Au1000 and Au1100 and Au1200 */
1367 1761
1368/* don't allow any legacy ports probing */ 1762/* don't allow any legacy ports probing */
1369#define IOPORT_RESOURCE_START 0x10000000; 1763#define IOPORT_RESOURCE_START 0x10000000
1370#define IOPORT_RESOURCE_END 0xffffffff 1764#define IOPORT_RESOURCE_END 0xffffffff
1371#define IOMEM_RESOURCE_START 0x10000000 1765#define IOMEM_RESOURCE_START 0x10000000
1372#define IOMEM_RESOURCE_END 0xffffffff 1766#define IOMEM_RESOURCE_END 0xffffffff
1373 1767
1374#ifdef CONFIG_MIPS_PB1000
1375#define PCI_IO_START 0x10000000
1376#define PCI_IO_END 0x1000ffff
1377#define PCI_MEM_START 0x18000000
1378#define PCI_MEM_END 0x18ffffff
1379#define PCI_FIRST_DEVFN 0
1380#define PCI_LAST_DEVFN 1
1381#else
1382/* no PCI bus controller */
1383#define PCI_IO_START 0 1768#define PCI_IO_START 0
1384#define PCI_IO_END 0 1769#define PCI_IO_END 0
1385#define PCI_MEM_START 0 1770#define PCI_MEM_START 0
1386#define PCI_MEM_END 0 1771#define PCI_MEM_END 0
1387#define PCI_FIRST_DEVFN 0 1772#define PCI_FIRST_DEVFN 0
1388#define PCI_LAST_DEVFN 0 1773#define PCI_LAST_DEVFN 0
1389#endif
1390 1774
1391#endif 1775#endif
1392 1776
1777#ifndef _LANGUAGE_ASSEMBLY
1778typedef volatile struct
1779{
1780 /* 0x0000 */ u32 toytrim;
1781 /* 0x0004 */ u32 toywrite;
1782 /* 0x0008 */ u32 toymatch0;
1783 /* 0x000C */ u32 toymatch1;
1784 /* 0x0010 */ u32 toymatch2;
1785 /* 0x0014 */ u32 cntrctrl;
1786 /* 0x0018 */ u32 scratch0;
1787 /* 0x001C */ u32 scratch1;
1788 /* 0x0020 */ u32 freqctrl0;
1789 /* 0x0024 */ u32 freqctrl1;
1790 /* 0x0028 */ u32 clksrc;
1791 /* 0x002C */ u32 pinfunc;
1792 /* 0x0030 */ u32 reserved0;
1793 /* 0x0034 */ u32 wakemsk;
1794 /* 0x0038 */ u32 endian;
1795 /* 0x003C */ u32 powerctrl;
1796 /* 0x0040 */ u32 toyread;
1797 /* 0x0044 */ u32 rtctrim;
1798 /* 0x0048 */ u32 rtcwrite;
1799 /* 0x004C */ u32 rtcmatch0;
1800 /* 0x0050 */ u32 rtcmatch1;
1801 /* 0x0054 */ u32 rtcmatch2;
1802 /* 0x0058 */ u32 rtcread;
1803 /* 0x005C */ u32 wakesrc;
1804 /* 0x0060 */ u32 cpupll;
1805 /* 0x0064 */ u32 auxpll;
1806 /* 0x0068 */ u32 reserved1;
1807 /* 0x006C */ u32 reserved2;
1808 /* 0x0070 */ u32 reserved3;
1809 /* 0x0074 */ u32 reserved4;
1810 /* 0x0078 */ u32 slppwr;
1811 /* 0x007C */ u32 sleep;
1812 /* 0x0080 */ u32 reserved5[32];
1813 /* 0x0100 */ u32 trioutrd;
1814#define trioutclr trioutrd
1815 /* 0x0104 */ u32 reserved6;
1816 /* 0x0108 */ u32 outputrd;
1817#define outputset outputrd
1818 /* 0x010C */ u32 outputclr;
1819 /* 0x0110 */ u32 pinstaterd;
1820#define pininputen pinstaterd
1821
1822} AU1X00_SYS;
1823
1824static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE;
1825
1826#endif
1393/* Processor information base on prid. 1827/* Processor information base on prid.
1394 * Copied from PowerPC. 1828 * Copied from PowerPC.
1395 */ 1829 */
1830#ifndef _LANGUAGE_ASSEMBLY
1396struct cpu_spec { 1831struct cpu_spec {
1397 /* CPU is matched via (PRID & prid_mask) == prid_value */ 1832 /* CPU is matched via (PRID & prid_mask) == prid_value */
1398 unsigned int prid_mask; 1833 unsigned int prid_mask;
@@ -1406,3 +1841,6 @@ struct cpu_spec {
1406extern struct cpu_spec cpu_specs[]; 1841extern struct cpu_spec cpu_specs[];
1407extern struct cpu_spec *cur_cpu_spec[]; 1842extern struct cpu_spec *cur_cpu_spec[];
1408#endif 1843#endif
1844
1845#endif
1846
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
index d5eb88cd7d51..ddbd9f5a2489 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
@@ -45,7 +45,7 @@
45#define DDMA_GLOBAL_BASE 0xb4003000 45#define DDMA_GLOBAL_BASE 0xb4003000
46#define DDMA_CHANNEL_BASE 0xb4002000 46#define DDMA_CHANNEL_BASE 0xb4002000
47 47
48typedef struct dbdma_global { 48typedef volatile struct dbdma_global {
49 u32 ddma_config; 49 u32 ddma_config;
50 u32 ddma_intstat; 50 u32 ddma_intstat;
51 u32 ddma_throttle; 51 u32 ddma_throttle;
@@ -62,7 +62,7 @@ typedef struct dbdma_global {
62 62
63/* The structure of a DMA Channel. 63/* The structure of a DMA Channel.
64*/ 64*/
65typedef struct au1xxx_dma_channel { 65typedef volatile struct au1xxx_dma_channel {
66 u32 ddma_cfg; /* See below */ 66 u32 ddma_cfg; /* See below */
67 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */ 67 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
68 u32 ddma_statptr; /* word aligned pointer to status word */ 68 u32 ddma_statptr; /* word aligned pointer to status word */
@@ -98,7 +98,7 @@ typedef struct au1xxx_dma_channel {
98/* "Standard" DDMA Descriptor. 98/* "Standard" DDMA Descriptor.
99 * Must be 32-byte aligned. 99 * Must be 32-byte aligned.
100 */ 100 */
101typedef struct au1xxx_ddma_desc { 101typedef volatile struct au1xxx_ddma_desc {
102 u32 dscr_cmd0; /* See below */ 102 u32 dscr_cmd0; /* See below */
103 u32 dscr_cmd1; /* See below */ 103 u32 dscr_cmd1; /* See below */
104 u32 dscr_source0; /* source phys address */ 104 u32 dscr_source0; /* source phys address */
@@ -107,6 +107,12 @@ typedef struct au1xxx_ddma_desc {
107 u32 dscr_dest1; /* See below */ 107 u32 dscr_dest1; /* See below */
108 u32 dscr_stat; /* completion status */ 108 u32 dscr_stat; /* completion status */
109 u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */ 109 u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
110 /* First 32bytes are HW specific!!!
111 Lets have some SW data following.. make sure its 32bytes
112 */
113 u32 sw_status;
114 u32 sw_context;
115 u32 sw_reserved[6];
110} au1x_ddma_desc_t; 116} au1x_ddma_desc_t;
111 117
112#define DSCR_CMD0_V (1 << 31) /* Descriptor valid */ 118#define DSCR_CMD0_V (1 << 31) /* Descriptor valid */
@@ -125,8 +131,11 @@ typedef struct au1xxx_ddma_desc {
125#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */ 131#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
126#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */ 132#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
127 133
134#define SW_STATUS_INUSE (1<<0)
135
128/* Command 0 device IDs. 136/* Command 0 device IDs.
129*/ 137*/
138#ifdef CONFIG_SOC_AU1550
130#define DSCR_CMD0_UART0_TX 0 139#define DSCR_CMD0_UART0_TX 0
131#define DSCR_CMD0_UART0_RX 1 140#define DSCR_CMD0_UART0_RX 1
132#define DSCR_CMD0_UART3_TX 2 141#define DSCR_CMD0_UART3_TX 2
@@ -155,9 +164,45 @@ typedef struct au1xxx_ddma_desc {
155#define DSCR_CMD0_MAC0_TX 25 164#define DSCR_CMD0_MAC0_TX 25
156#define DSCR_CMD0_MAC1_RX 26 165#define DSCR_CMD0_MAC1_RX 26
157#define DSCR_CMD0_MAC1_TX 27 166#define DSCR_CMD0_MAC1_TX 27
167#endif /* CONFIG_SOC_AU1550 */
168
169#ifdef CONFIG_SOC_AU1200
170#define DSCR_CMD0_UART0_TX 0
171#define DSCR_CMD0_UART0_RX 1
172#define DSCR_CMD0_UART1_TX 2
173#define DSCR_CMD0_UART1_RX 3
174#define DSCR_CMD0_DMA_REQ0 4
175#define DSCR_CMD0_DMA_REQ1 5
176#define DSCR_CMD0_MAE_BE 6
177#define DSCR_CMD0_MAE_FE 7
178#define DSCR_CMD0_SDMS_TX0 8
179#define DSCR_CMD0_SDMS_RX0 9
180#define DSCR_CMD0_SDMS_TX1 10
181#define DSCR_CMD0_SDMS_RX1 11
182#define DSCR_CMD0_AES_TX 13
183#define DSCR_CMD0_AES_RX 12
184#define DSCR_CMD0_PSC0_TX 14
185#define DSCR_CMD0_PSC0_RX 15
186#define DSCR_CMD0_PSC1_TX 16
187#define DSCR_CMD0_PSC1_RX 17
188#define DSCR_CMD0_CIM_RXA 18
189#define DSCR_CMD0_CIM_RXB 19
190#define DSCR_CMD0_CIM_RXC 20
191#define DSCR_CMD0_MAE_BOTH 21
192#define DSCR_CMD0_LCD 22
193#define DSCR_CMD0_NAND_FLASH 23
194#define DSCR_CMD0_PSC0_SYNC 24
195#define DSCR_CMD0_PSC1_SYNC 25
196#define DSCR_CMD0_CIM_SYNC 26
197#endif /* CONFIG_SOC_AU1200 */
198
158#define DSCR_CMD0_THROTTLE 30 199#define DSCR_CMD0_THROTTLE 30
159#define DSCR_CMD0_ALWAYS 31 200#define DSCR_CMD0_ALWAYS 31
160#define DSCR_NDEV_IDS 32 201#define DSCR_NDEV_IDS 32
202/* THis macro is used to find/create custom device types */
203#define DSCR_DEV2CUSTOM_ID(x,d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
204#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF)
205
161 206
162#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25) 207#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
163#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20) 208#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
@@ -246,6 +291,43 @@ typedef struct au1xxx_ddma_desc {
246*/ 291*/
247#define NUM_DBDMA_CHANS 16 292#define NUM_DBDMA_CHANS 16
248 293
294/*
295 * Ddma API definitions
296 * FIXME: may not fit to this header file
297 */
298typedef struct dbdma_device_table {
299 u32 dev_id;
300 u32 dev_flags;
301 u32 dev_tsize;
302 u32 dev_devwidth;
303 u32 dev_physaddr; /* If FIFO */
304 u32 dev_intlevel;
305 u32 dev_intpolarity;
306} dbdev_tab_t;
307
308
309typedef struct dbdma_chan_config {
310 spinlock_t lock;
311
312 u32 chan_flags;
313 u32 chan_index;
314 dbdev_tab_t *chan_src;
315 dbdev_tab_t *chan_dest;
316 au1x_dma_chan_t *chan_ptr;
317 au1x_ddma_desc_t *chan_desc_base;
318 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
319 void *chan_callparam;
320 void (*chan_callback)(int, void *, struct pt_regs *);
321} chan_tab_t;
322
323#define DEV_FLAGS_INUSE (1 << 0)
324#define DEV_FLAGS_ANYUSE (1 << 1)
325#define DEV_FLAGS_OUT (1 << 2)
326#define DEV_FLAGS_IN (1 << 3)
327#define DEV_FLAGS_BURSTABLE (1 << 4)
328#define DEV_FLAGS_SYNC (1 << 5)
329/* end Ddma API definitions */
330
249/* External functions for drivers to use. 331/* External functions for drivers to use.
250*/ 332*/
251/* Use this to allocate a dbdma channel. The device ids are one of the 333/* Use this to allocate a dbdma channel. The device ids are one of the
@@ -258,18 +340,6 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
258 340
259#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS 341#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
260 342
261/* ACK! These should be in a board specific description file.
262*/
263#ifdef CONFIG_MIPS_PB1550
264#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
265#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
266#endif
267#ifdef CONFIG_MIPS_DB1550
268#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
269#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
270#endif
271
272
273/* Set the device width of a in/out fifo. 343/* Set the device width of a in/out fifo.
274*/ 344*/
275u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits); 345u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
@@ -280,8 +350,8 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
280 350
281/* Put buffers on source/destination descriptors. 351/* Put buffers on source/destination descriptors.
282*/ 352*/
283u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes); 353u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
284u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes); 354u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
285 355
286/* Get a buffer from the destination descriptor. 356/* Get a buffer from the destination descriptor.
287*/ 357*/
@@ -295,5 +365,25 @@ u32 au1xxx_get_dma_residue(u32 chanid);
295void au1xxx_dbdma_chan_free(u32 chanid); 365void au1xxx_dbdma_chan_free(u32 chanid);
296void au1xxx_dbdma_dump(u32 chanid); 366void au1xxx_dbdma_dump(u32 chanid);
297 367
368u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr );
369
370u32 au1xxx_ddma_add_device( dbdev_tab_t *dev );
371
372/*
373 Some compatibilty macros --
374 Needed to make changes to API without breaking existing drivers
375*/
376#define au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
377#define au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
378
379#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
380#define au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
381
382/*
383 * Flags for the put_source/put_dest functions.
384 */
385#define DDMA_FLAGS_IE (1<<0)
386#define DDMA_FLAGS_NOIE (1<<1)
387
298#endif /* _LANGUAGE_ASSEMBLY */ 388#endif /* _LANGUAGE_ASSEMBLY */
299#endif /* _AU1000_DBDMA_H_ */ 389#endif /* _AU1000_DBDMA_H_ */
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h
new file mode 100644
index 000000000000..6d1ddf43d290
--- /dev/null
+++ b/include/asm-mips/mach-db1x00/db1200.h
@@ -0,0 +1,214 @@
1/*
2 * AMD Alchemy DB1200 Referrence Board
3 * Board Registers defines.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 *
23 */
24#ifndef __ASM_DB1200_H
25#define __ASM_DB1200_H
26
27#include <linux/types.h>
28
29// This is defined in au1000.h with bogus value
30#undef AU1X00_EXTERNAL_INT
31
32#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
34#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
35#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
36
37/* SPI and SMB are muxed on the Pb1200 board.
38 Refer to board documentation.
39 */
40#define SPI_PSC_BASE PSC0_BASE_ADDR
41#define SMBUS_PSC_BASE PSC0_BASE_ADDR
42/* AC97 and I2S are muxed on the Pb1200 board.
43 Refer to board documentation.
44 */
45#define AC97_PSC_BASE PSC1_BASE_ADDR
46#define I2S_PSC_BASE PSC1_BASE_ADDR
47
48#define BCSR_KSEG1_ADDR 0xB9800000
49
50typedef volatile struct
51{
52 /*00*/ u16 whoami;
53 u16 reserved0;
54 /*04*/ u16 status;
55 u16 reserved1;
56 /*08*/ u16 switches;
57 u16 reserved2;
58 /*0C*/ u16 resets;
59 u16 reserved3;
60
61 /*10*/ u16 pcmcia;
62 u16 reserved4;
63 /*14*/ u16 board;
64 u16 reserved5;
65 /*18*/ u16 disk_leds;
66 u16 reserved6;
67 /*1C*/ u16 system;
68 u16 reserved7;
69
70 /*20*/ u16 intclr;
71 u16 reserved8;
72 /*24*/ u16 intset;
73 u16 reserved9;
74 /*28*/ u16 intclr_mask;
75 u16 reserved10;
76 /*2C*/ u16 intset_mask;
77 u16 reserved11;
78
79 /*30*/ u16 sig_status;
80 u16 reserved12;
81 /*34*/ u16 int_status;
82 u16 reserved13;
83 /*38*/ u16 reserved14;
84 u16 reserved15;
85 /*3C*/ u16 reserved16;
86 u16 reserved17;
87
88} BCSR;
89
90static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
91
92/*
93 * Register bit definitions for the BCSRs
94 */
95#define BCSR_WHOAMI_DCID 0x000F
96#define BCSR_WHOAMI_CPLD 0x00F0
97#define BCSR_WHOAMI_BOARD 0x0F00
98
99#define BCSR_STATUS_PCMCIA0VS 0x0003
100#define BCSR_STATUS_PCMCIA1VS 0x000C
101#define BCSR_STATUS_SWAPBOOT 0x0040
102#define BCSR_STATUS_FLASHBUSY 0x0100
103#define BCSR_STATUS_IDECBLID 0x0200
104#define BCSR_STATUS_SD0WP 0x0400
105#define BCSR_STATUS_U0RXD 0x1000
106#define BCSR_STATUS_U1RXD 0x2000
107
108#define BCSR_SWITCHES_OCTAL 0x00FF
109#define BCSR_SWITCHES_DIP_1 0x0080
110#define BCSR_SWITCHES_DIP_2 0x0040
111#define BCSR_SWITCHES_DIP_3 0x0020
112#define BCSR_SWITCHES_DIP_4 0x0010
113#define BCSR_SWITCHES_DIP_5 0x0008
114#define BCSR_SWITCHES_DIP_6 0x0004
115#define BCSR_SWITCHES_DIP_7 0x0002
116#define BCSR_SWITCHES_DIP_8 0x0001
117#define BCSR_SWITCHES_ROTARY 0x0F00
118
119#define BCSR_RESETS_ETH 0x0001
120#define BCSR_RESETS_CAMERA 0x0002
121#define BCSR_RESETS_DC 0x0004
122#define BCSR_RESETS_IDE 0x0008
123#define BCSR_RESETS_TV 0x0010
124/* not resets but in the same register */
125#define BCSR_RESETS_PWMR1mUX 0x0800
126#define BCSR_RESETS_PCS0MUX 0x1000
127#define BCSR_RESETS_PCS1MUX 0x2000
128#define BCSR_RESETS_SPISEL 0x4000
129
130#define BCSR_PCMCIA_PC0VPP 0x0003
131#define BCSR_PCMCIA_PC0VCC 0x000C
132#define BCSR_PCMCIA_PC0DRVEN 0x0010
133#define BCSR_PCMCIA_PC0RST 0x0080
134#define BCSR_PCMCIA_PC1VPP 0x0300
135#define BCSR_PCMCIA_PC1VCC 0x0C00
136#define BCSR_PCMCIA_PC1DRVEN 0x1000
137#define BCSR_PCMCIA_PC1RST 0x8000
138
139#define BCSR_BOARD_LCDVEE 0x0001
140#define BCSR_BOARD_LCDVDD 0x0002
141#define BCSR_BOARD_LCDBL 0x0004
142#define BCSR_BOARD_CAMSNAP 0x0010
143#define BCSR_BOARD_CAMPWR 0x0020
144#define BCSR_BOARD_SD0PWR 0x0040
145
146#define BCSR_LEDS_DECIMALS 0x0003
147#define BCSR_LEDS_LED0 0x0100
148#define BCSR_LEDS_LED1 0x0200
149#define BCSR_LEDS_LED2 0x0400
150#define BCSR_LEDS_LED3 0x0800
151
152#define BCSR_SYSTEM_POWEROFF 0x4000
153#define BCSR_SYSTEM_RESET 0x8000
154
155/* Bit positions for the different interrupt sources */
156#define BCSR_INT_IDE 0x0001
157#define BCSR_INT_ETH 0x0002
158#define BCSR_INT_PC0 0x0004
159#define BCSR_INT_PC0STSCHG 0x0008
160#define BCSR_INT_PC1 0x0010
161#define BCSR_INT_PC1STSCHG 0x0020
162#define BCSR_INT_DC 0x0040
163#define BCSR_INT_FLASHBUSY 0x0080
164#define BCSR_INT_PC0INSERT 0x0100
165#define BCSR_INT_PC0EJECT 0x0200
166#define BCSR_INT_PC1INSERT 0x0400
167#define BCSR_INT_PC1EJECT 0x0800
168#define BCSR_INT_SD0INSERT 0x1000
169#define BCSR_INT_SD0EJECT 0x2000
170
171#define AU1XXX_SMC91111_PHYS_ADDR (0x19000300)
172#define AU1XXX_SMC91111_IRQ DB1200_ETH_INT
173
174#define AU1XXX_ATA_PHYS_ADDR (0x18800000)
175#define AU1XXX_ATA_PHYS_LEN (0x100)
176#define AU1XXX_ATA_REG_OFFSET (5)
177#define AU1XXX_ATA_INT DB1200_IDE_INT
178#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1;
179#define AU1XXX_ATA_RQSIZE 128
180
181#define NAND_PHYS_ADDR 0x20000000
182
183/*
184 * External Interrupts for Pb1200 as of 8/6/2004.
185 * Bit positions in the CPLD registers can be calculated by taking
186 * the interrupt define and subtracting the DB1200_INT_BEGIN value.
187 * *example: IDE bis pos is = 64 - 64
188 ETH bit pos is = 65 - 64
189 */
190#define DB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1)
191#define DB1200_IDE_INT (DB1200_INT_BEGIN + 0)
192#define DB1200_ETH_INT (DB1200_INT_BEGIN + 1)
193#define DB1200_PC0_INT (DB1200_INT_BEGIN + 2)
194#define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3)
195#define DB1200_PC1_INT (DB1200_INT_BEGIN + 4)
196#define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5)
197#define DB1200_DC_INT (DB1200_INT_BEGIN + 6)
198#define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7)
199#define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8)
200#define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9)
201#define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10)
202#define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11)
203#define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12)
204#define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13)
205
206#define DB1200_INT_END (DB1200_INT_BEGIN + 15)
207
208/* For drivers/pcmcia/au1000_db1x00.c */
209#define BOARD_PC0_INT DB1200_PC0_INT
210#define BOARD_PC1_INT DB1200_PC1_INT
211#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
212
213#endif /* __ASM_DB1200_H */
214
diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h
new file mode 100644
index 000000000000..0f6646335e90
--- /dev/null
+++ b/include/asm-mips/mach-pb1x00/pb1200.h
@@ -0,0 +1,244 @@
1/*
2 * AMD Alchemy PB1200 Referrence Board
3 * Board Registers defines.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 *
23 */
24#ifndef __ASM_PB1200_H
25#define __ASM_PB1200_H
26
27#include <linux/types.h>
28
29// This is defined in au1000.h with bogus value
30#undef AU1X00_EXTERNAL_INT
31
32#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
34#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
35#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
36
37/* SPI and SMB are muxed on the Pb1200 board.
38 Refer to board documentation.
39 */
40#define SPI_PSC_BASE PSC0_BASE_ADDR
41#define SMBUS_PSC_BASE PSC0_BASE_ADDR
42/* AC97 and I2S are muxed on the Pb1200 board.
43 Refer to board documentation.
44 */
45#define AC97_PSC_BASE PSC1_BASE_ADDR
46#define I2S_PSC_BASE PSC1_BASE_ADDR
47
48#define BCSR_KSEG1_ADDR 0xAD800000
49
50typedef volatile struct
51{
52 /*00*/ u16 whoami;
53 u16 reserved0;
54 /*04*/ u16 status;
55 u16 reserved1;
56 /*08*/ u16 switches;
57 u16 reserved2;
58 /*0C*/ u16 resets;
59 u16 reserved3;
60
61 /*10*/ u16 pcmcia;
62 u16 reserved4;
63 /*14*/ u16 board;
64 u16 reserved5;
65 /*18*/ u16 disk_leds;
66 u16 reserved6;
67 /*1C*/ u16 system;
68 u16 reserved7;
69
70 /*20*/ u16 intclr;
71 u16 reserved8;
72 /*24*/ u16 intset;
73 u16 reserved9;
74 /*28*/ u16 intclr_mask;
75 u16 reserved10;
76 /*2C*/ u16 intset_mask;
77 u16 reserved11;
78
79 /*30*/ u16 sig_status;
80 u16 reserved12;
81 /*34*/ u16 int_status;
82 u16 reserved13;
83 /*38*/ u16 reserved14;
84 u16 reserved15;
85 /*3C*/ u16 reserved16;
86 u16 reserved17;
87
88} BCSR;
89
90static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
91
92/*
93 * Register bit definitions for the BCSRs
94 */
95#define BCSR_WHOAMI_DCID 0x000F
96#define BCSR_WHOAMI_CPLD 0x00F0
97#define BCSR_WHOAMI_BOARD 0x0F00
98
99#define BCSR_STATUS_PCMCIA0VS 0x0003
100#define BCSR_STATUS_PCMCIA1VS 0x000C
101#define BCSR_STATUS_SWAPBOOT 0x0040
102#define BCSR_STATUS_FLASHBUSY 0x0100
103#define BCSR_STATUS_IDECBLID 0x0200
104#define BCSR_STATUS_SD0WP 0x0400
105#define BCSR_STATUS_SD1WP 0x0800
106#define BCSR_STATUS_U0RXD 0x1000
107#define BCSR_STATUS_U1RXD 0x2000
108
109#define BCSR_SWITCHES_OCTAL 0x00FF
110#define BCSR_SWITCHES_DIP_1 0x0080
111#define BCSR_SWITCHES_DIP_2 0x0040
112#define BCSR_SWITCHES_DIP_3 0x0020
113#define BCSR_SWITCHES_DIP_4 0x0010
114#define BCSR_SWITCHES_DIP_5 0x0008
115#define BCSR_SWITCHES_DIP_6 0x0004
116#define BCSR_SWITCHES_DIP_7 0x0002
117#define BCSR_SWITCHES_DIP_8 0x0001
118#define BCSR_SWITCHES_ROTARY 0x0F00
119
120#define BCSR_RESETS_ETH 0x0001
121#define BCSR_RESETS_CAMERA 0x0002
122#define BCSR_RESETS_DC 0x0004
123#define BCSR_RESETS_IDE 0x0008
124/* not resets but in the same register */
125#define BCSR_RESETS_WSCFSM 0x0800
126#define BCSR_RESETS_PCS0MUX 0x1000
127#define BCSR_RESETS_PCS1MUX 0x2000
128#define BCSR_RESETS_SPISEL 0x4000
129#define BCSR_RESETS_SD1MUX 0x8000
130
131#define BCSR_PCMCIA_PC0VPP 0x0003
132#define BCSR_PCMCIA_PC0VCC 0x000C
133#define BCSR_PCMCIA_PC0DRVEN 0x0010
134#define BCSR_PCMCIA_PC0RST 0x0080
135#define BCSR_PCMCIA_PC1VPP 0x0300
136#define BCSR_PCMCIA_PC1VCC 0x0C00
137#define BCSR_PCMCIA_PC1DRVEN 0x1000
138#define BCSR_PCMCIA_PC1RST 0x8000
139
140#define BCSR_BOARD_LCDVEE 0x0001
141#define BCSR_BOARD_LCDVDD 0x0002
142#define BCSR_BOARD_LCDBL 0x0004
143#define BCSR_BOARD_CAMSNAP 0x0010
144#define BCSR_BOARD_CAMPWR 0x0020
145#define BCSR_BOARD_SD0PWR 0x0040
146#define BCSR_BOARD_SD1PWR 0x0080
147
148#define BCSR_LEDS_DECIMALS 0x00FF
149#define BCSR_LEDS_LED0 0x0100
150#define BCSR_LEDS_LED1 0x0200
151#define BCSR_LEDS_LED2 0x0400
152#define BCSR_LEDS_LED3 0x0800
153
154#define BCSR_SYSTEM_VDDI 0x001F
155#define BCSR_SYSTEM_POWEROFF 0x4000
156#define BCSR_SYSTEM_RESET 0x8000
157
158/* Bit positions for the different interrupt sources */
159#define BCSR_INT_IDE 0x0001
160#define BCSR_INT_ETH 0x0002
161#define BCSR_INT_PC0 0x0004
162#define BCSR_INT_PC0STSCHG 0x0008
163#define BCSR_INT_PC1 0x0010
164#define BCSR_INT_PC1STSCHG 0x0020
165#define BCSR_INT_DC 0x0040
166#define BCSR_INT_FLASHBUSY 0x0080
167#define BCSR_INT_PC0INSERT 0x0100
168#define BCSR_INT_PC0EJECT 0x0200
169#define BCSR_INT_PC1INSERT 0x0400
170#define BCSR_INT_PC1EJECT 0x0800
171#define BCSR_INT_SD0INSERT 0x1000
172#define BCSR_INT_SD0EJECT 0x2000
173#define BCSR_INT_SD1INSERT 0x4000
174#define BCSR_INT_SD1EJECT 0x8000
175
176#define AU1XXX_SMC91111_PHYS_ADDR (0x0D000300)
177#define AU1XXX_SMC91111_IRQ PB1200_ETH_INT
178
179#define AU1XXX_ATA_PHYS_ADDR (0x0C800000)
180#define AU1XXX_ATA_PHYS_LEN (0x100)
181#define AU1XXX_ATA_REG_OFFSET (5)
182#define AU1XXX_ATA_INT PB1200_IDE_INT
183#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1;
184#define AU1XXX_ATA_RQSIZE 128
185
186#define NAND_PHYS_ADDR 0x1C000000
187
188/* Timing values as described in databook, * ns value stripped of
189 * lower 2 bits.
190 * These defines are here rather than an SOC1200 generic file because
191 * the parts chosen on another board may be different and may require
192 * different timings.
193 */
194#define NAND_T_H (18 >> 2)
195#define NAND_T_PUL (30 >> 2)
196#define NAND_T_SU (30 >> 2)
197#define NAND_T_WH (30 >> 2)
198
199/* Bitfield shift amounts */
200#define NAND_T_H_SHIFT 0
201#define NAND_T_PUL_SHIFT 4
202#define NAND_T_SU_SHIFT 8
203#define NAND_T_WH_SHIFT 12
204
205#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
206 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
207 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
208 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
209
210
211/*
212 * External Interrupts for Pb1200 as of 8/6/2004.
213 * Bit positions in the CPLD registers can be calculated by taking
214 * the interrupt define and subtracting the PB1200_INT_BEGIN value.
215 * *example: IDE bis pos is = 64 - 64
216 ETH bit pos is = 65 - 64
217 */
218#define PB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1)
219#define PB1200_IDE_INT (PB1200_INT_BEGIN + 0)
220#define PB1200_ETH_INT (PB1200_INT_BEGIN + 1)
221#define PB1200_PC0_INT (PB1200_INT_BEGIN + 2)
222#define PB1200_PC0_STSCHG_INT (PB1200_INT_BEGIN + 3)
223#define PB1200_PC1_INT (PB1200_INT_BEGIN + 4)
224#define PB1200_PC1_STSCHG_INT (PB1200_INT_BEGIN + 5)
225#define PB1200_DC_INT (PB1200_INT_BEGIN + 6)
226#define PB1200_FLASHBUSY_INT (PB1200_INT_BEGIN + 7)
227#define PB1200_PC0_INSERT_INT (PB1200_INT_BEGIN + 8)
228#define PB1200_PC0_EJECT_INT (PB1200_INT_BEGIN + 9)
229#define PB1200_PC1_INSERT_INT (PB1200_INT_BEGIN + 10)
230#define PB1200_PC1_EJECT_INT (PB1200_INT_BEGIN + 11)
231#define PB1200_SD0_INSERT_INT (PB1200_INT_BEGIN + 12)
232#define PB1200_SD0_EJECT_INT (PB1200_INT_BEGIN + 13)
233#define PB1200_SD1_INSERT_INT (PB1200_INT_BEGIN + 14)
234#define PB1200_SD1_EJECT_INT (PB1200_INT_BEGIN + 15)
235
236#define PB1200_INT_END (PB1200_INT_BEGIN + 15)
237
238/* For drivers/pcmcia/au1000_db1x00.c */
239#define BOARD_PC0_INT PB1200_PC0_INT
240#define BOARD_PC1_INT PB1200_PC1_INT
241#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
242
243#endif /* __ASM_PB1200_H */
244
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