aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorStephen Hemminger <shemminger@linux-foundation.org>2008-01-23 22:16:04 -0500
committerDavid S. Miller <davem@davemloft.net>2008-02-03 07:28:44 -0500
commit82637e808478087ce861129745fa60cc37e7929d (patch)
treeb9bf662a5690f4948b376f821f8eb57d9247c2e3
parenta7bffe722c996679b4fb2103ecaf673ec2b9b4a7 (diff)
sky2: fix Wake On Lan interaction with BIOS
This patch disables config mode access after clearing PCI settings. Some BIOS's seem to not do WOL if config bit still set. Fixes: http://bugzilla.kernel.org/show_bug.cgi?id=9721 Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/sky2.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 6675b2256cdb..dc062367a1c8 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -623,6 +623,7 @@ static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
623 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; 623 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
624 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; 624 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
625 625
626 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
626 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 627 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
627 /* Turn on/off phy power saving */ 628 /* Turn on/off phy power saving */
628 if (onoff) 629 if (onoff)
@@ -634,7 +635,8 @@ static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
634 reg1 |= coma_mode[port]; 635 reg1 |= coma_mode[port];
635 636
636 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 637 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
637 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 638 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
639 sky2_pci_read32(hw, PCI_DEV_REG1);
638 640
639 udelay(100); 641 udelay(100);
640} 642}
@@ -2437,6 +2439,7 @@ static void sky2_hw_intr(struct sky2_hw *hw)
2437 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { 2439 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2438 u16 pci_err; 2440 u16 pci_err;
2439 2441
2442 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2440 pci_err = sky2_pci_read16(hw, PCI_STATUS); 2443 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2441 if (net_ratelimit()) 2444 if (net_ratelimit())
2442 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", 2445 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
@@ -2444,12 +2447,14 @@ static void sky2_hw_intr(struct sky2_hw *hw)
2444 2447
2445 sky2_pci_write16(hw, PCI_STATUS, 2448 sky2_pci_write16(hw, PCI_STATUS,
2446 pci_err | PCI_STATUS_ERROR_BITS); 2449 pci_err | PCI_STATUS_ERROR_BITS);
2450 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2447 } 2451 }
2448 2452
2449 if (status & Y2_IS_PCI_EXP) { 2453 if (status & Y2_IS_PCI_EXP) {
2450 /* PCI-Express uncorrectable Error occurred */ 2454 /* PCI-Express uncorrectable Error occurred */
2451 u32 err; 2455 u32 err;
2452 2456
2457 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2453 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2458 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2454 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 2459 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2455 0xfffffffful); 2460 0xfffffffful);
@@ -2457,6 +2462,7 @@ static void sky2_hw_intr(struct sky2_hw *hw)
2457 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); 2462 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2458 2463
2459 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2464 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2465 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2460 } 2466 }
2461 2467
2462 if (status & Y2_HWE_L1_MASK) 2468 if (status & Y2_HWE_L1_MASK)
@@ -2832,6 +2838,7 @@ static void sky2_reset(struct sky2_hw *hw)
2832 } 2838 }
2833 2839
2834 sky2_power_on(hw); 2840 sky2_power_on(hw);
2841 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2835 2842
2836 for (i = 0; i < hw->ports; i++) { 2843 for (i = 0; i < hw->ports; i++) {
2837 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 2844 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);