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authorMatt Carlson <mcarlson@broadcom.com>2010-01-20 11:58:02 -0500
committerDavid S. Miller <davem@davemloft.net>2010-01-20 22:20:57 -0500
commit614b05900ec3516b835cd06f848ef6bc915beeea (patch)
treebe57c5d34fda094682c1ad5ff74378f40ed76113
parent7981d6f6b280d28779343cff4a88029fe53d1b47 (diff)
tg3: Enable PLL PD when CLKREQ disabled for 5717A0
PCIe PLL power down cannot be used if CLKREQ is enabled because data corruption will occur. If CLKREQ is disabled though, enabling PCIE P1 PLL power-down saves some power. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/tg3.c16
-rw-r--r--drivers/net/tg3.h14
2 files changed, 30 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index b0630cd093a3..b80e7eef8af9 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7569,6 +7569,20 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7569 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); 7569 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7570 } 7570 }
7571 7571
7572 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7573 u32 grc_mode = tr32(GRC_MODE);
7574
7575 /* Access the lower 1K of PL PCIE block registers. */
7576 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7577 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7578
7579 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7580 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7581 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7582
7583 tw32(GRC_MODE, grc_mode);
7584 }
7585
7572 /* This works around an issue with Athlon chipsets on 7586 /* This works around an issue with Athlon chipsets on
7573 * B3 tigon3 silicon. This bit has no effect on any 7587 * B3 tigon3 silicon. This bit has no effect on any
7574 * other revision. But do not set this on PCI Express 7588 * other revision. But do not set this on PCI Express
@@ -13096,6 +13110,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13096 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || 13110 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13097 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) 13111 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13098 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG; 13112 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13113 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13114 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13099 } 13115 }
13100 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { 13116 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13101 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; 13117 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index cd30889650f8..44a505d07e20 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1540,6 +1540,8 @@
1540#define GRC_MODE_HOST_SENDBDS 0x00020000 1540#define GRC_MODE_HOST_SENDBDS 0x00020000
1541#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000 1541#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1542#define GRC_MODE_NVRAM_WR_ENABLE 0x00200000 1542#define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
1543#define GRC_MODE_PCIE_TL_SEL 0x00000000
1544#define GRC_MODE_PCIE_PL_SEL 0x00400000
1543#define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000 1545#define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1544#define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000 1546#define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1545#define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000 1547#define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
@@ -1547,7 +1549,13 @@
1547#define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000 1549#define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1548#define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000 1550#define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1549#define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000 1551#define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1552#define GRC_MODE_PCIE_DL_SEL 0x20000000
1550#define GRC_MODE_MCAST_FRM_ENABLE 0x40000000 1553#define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1554#define GRC_MODE_PCIE_HI_1K_EN 0x80000000
1555#define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \
1556 GRC_MODE_PCIE_PL_SEL | \
1557 GRC_MODE_PCIE_DL_SEL | \
1558 GRC_MODE_PCIE_HI_1K_EN)
1551#define GRC_MISC_CFG 0x00006804 1559#define GRC_MISC_CFG 0x00006804
1552#define GRC_MISC_CFG_CORECLK_RESET 0x00000001 1560#define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1553#define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe 1561#define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
@@ -1801,6 +1809,11 @@
1801/* 0x7e74 --> 0x8000 unused */ 1809/* 0x7e74 --> 0x8000 unused */
1802 1810
1803 1811
1812/* Alternate PCIE definitions */
1813#define TG3_PCIE_TLDLPL_PORT 0x00007c00
1814#define TG3_PCIE_PL_LO_PHYCTL1 0x00000004
1815#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000
1816
1804/* OTP bit definitions */ 1817/* OTP bit definitions */
1805#define TG3_OTP_AGCTGT_MASK 0x000000e0 1818#define TG3_OTP_AGCTGT_MASK 0x000000e0
1806#define TG3_OTP_AGCTGT_SHIFT 1 1819#define TG3_OTP_AGCTGT_SHIFT 1
@@ -2809,6 +2822,7 @@ struct tg3 {
2809#define TG3_FLG3_40BIT_DMA_LIMIT_BUG 0x00100000 2822#define TG3_FLG3_40BIT_DMA_LIMIT_BUG 0x00100000
2810#define TG3_FLG3_SHORT_DMA_BUG 0x00200000 2823#define TG3_FLG3_SHORT_DMA_BUG 0x00200000
2811#define TG3_FLG3_USE_JUMBO_BDFLAG 0x00400000 2824#define TG3_FLG3_USE_JUMBO_BDFLAG 0x00400000
2825#define TG3_FLG3_L1PLLPD_EN 0x00800000
2812 2826
2813 struct timer_list timer; 2827 struct timer_list timer;
2814 u16 timer_counter; 2828 u16 timer_counter;