aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorMark Brown <broonie@opensource.wolfsonmicro.com>2008-09-10 13:58:42 -0400
committerLiam Girdwood <lrg@slimlogic.co.uk>2008-10-13 16:51:52 -0400
commit1d9f9f040035da73d6ee5d2b3b3a25483a980da3 (patch)
treede6decdace491997d40fba0908661fa9ffda5b9c
parent8a62ab4c4eaf5bce4d9cc84b77d6402c4742d9ab (diff)
mfd: Core support for the WM8400 AudioPlus HiFi CODEC and PMU
The WM8400 is a highly integrated audio CODEC and power management unit optimised for use in mobile multimedia applications. This patch adds core support for the WM8400 to the MFD subsystem. Both I2C and SPI access are supported by the hardware but currently only I2C access is implemented. The code is structured to allow SPI support to be slotted in later. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Samuel Ortiz <sameo@openedhand.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
Diffstat
-rw-r--r--drivers/mfd/Kconfig8
-rw-r--r--drivers/mfd/Makefile2
-rw-r--r--drivers/mfd/wm8400-core.c455
-rw-r--r--include/linux/mfd/wm8400-audio.h1186
-rw-r--r--include/linux/mfd/wm8400-private.h935
5 files changed, 2586 insertions, 0 deletions
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 0dae245c6259..a3ddf6581ea6 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -87,6 +87,14 @@ config MFD_TC6393XB
87 help 87 help
88 Support for Toshiba Mobile IO Controller TC6393XB 88 Support for Toshiba Mobile IO Controller TC6393XB
89 89
90config MFD_WM8400
91 tristate "Support Wolfson Microelectronics WM8400"
92 help
93 Support for the Wolfson Microelecronics WM8400 PMIC and audio
94 CODEC. This driver adds provides common support for accessing
95 the device, additional drivers must be enabled in order to use
96 the functionality of the device.
97
90endmenu 98endmenu
91 99
92menu "Multimedia Capabilities Port drivers" 100menu "Multimedia Capabilities Port drivers"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 6abebe364419..1624c7d87a49 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -12,6 +12,8 @@ obj-$(CONFIG_MFD_T7L66XB) += t7l66xb.o
12obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o 12obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o
13obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o 13obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o
14 14
15obj-$(CONFIG_MFD_WM8400) += wm8400-core.o
16
15obj-$(CONFIG_MFD_CORE) += mfd-core.o 17obj-$(CONFIG_MFD_CORE) += mfd-core.o
16 18
17obj-$(CONFIG_MCP) += mcp-core.o 19obj-$(CONFIG_MCP) += mcp-core.o
diff --git a/drivers/mfd/wm8400-core.c b/drivers/mfd/wm8400-core.c
new file mode 100644
index 000000000000..6a0cedb5bb8a
--- /dev/null
+++ b/drivers/mfd/wm8400-core.c
@@ -0,0 +1,455 @@
1/*
2 * Core driver for WM8400.
3 *
4 * Copyright 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 */
14
15#include <linux/bug.h>
16#include <linux/i2c.h>
17#include <linux/kernel.h>
18#include <linux/mfd/wm8400-private.h>
19#include <linux/mfd/wm8400-audio.h>
20
21static struct {
22 u16 readable; /* Mask of readable bits */
23 u16 writable; /* Mask of writable bits */
24 u16 vol; /* Mask of volatile bits */
25 int is_codec; /* Register controlled by codec reset */
26 u16 default_val; /* Value on reset */
27} reg_data[] = {
28 { 0xFFFF, 0xFFFF, 0x0000, 0, 0x6172 }, /* R0 */
29 { 0x7000, 0x0000, 0x8000, 0, 0x0000 }, /* R1 */
30 { 0xFF17, 0xFF17, 0x0000, 0, 0x0000 }, /* R2 */
31 { 0xEBF3, 0xEBF3, 0x0000, 1, 0x6000 }, /* R3 */
32 { 0x3CF3, 0x3CF3, 0x0000, 1, 0x0000 }, /* R4 */
33 { 0xF1F8, 0xF1F8, 0x0000, 1, 0x4050 }, /* R5 */
34 { 0xFC1F, 0xFC1F, 0x0000, 1, 0x4000 }, /* R6 */
35 { 0xDFDE, 0xDFDE, 0x0000, 1, 0x01C8 }, /* R7 */
36 { 0xFCFC, 0xFCFC, 0x0000, 1, 0x0000 }, /* R8 */
37 { 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R9 */
38 { 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R10 */
39 { 0x27F7, 0x27F7, 0x0000, 1, 0x0004 }, /* R11 */
40 { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R12 */
41 { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R13 */
42 { 0x1FEF, 0x1FEF, 0x0000, 1, 0x0000 }, /* R14 */
43 { 0x0163, 0x0163, 0x0000, 1, 0x0100 }, /* R15 */
44 { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R16 */
45 { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R17 */
46 { 0x1FFF, 0x0FFF, 0x0000, 1, 0x0000 }, /* R18 */
47 { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1000 }, /* R19 */
48 { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R20 */
49 { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R21 */
50 { 0x0FDD, 0x0FDD, 0x0000, 1, 0x8000 }, /* R22 */
51 { 0x1FFF, 0x1FFF, 0x0000, 1, 0x0800 }, /* R23 */
52 { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R24 */
53 { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R25 */
54 { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R26 */
55 { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R27 */
56 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R28 */
57 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R29 */
58 { 0x0000, 0x0077, 0x0000, 1, 0x0066 }, /* R30 */
59 { 0x0000, 0x0033, 0x0000, 1, 0x0022 }, /* R31 */
60 { 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R32 */
61 { 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R33 */
62 { 0x0000, 0x0003, 0x0000, 1, 0x0003 }, /* R34 */
63 { 0x0000, 0x01FF, 0x0000, 1, 0x0003 }, /* R35 */
64 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R36 */
65 { 0x0000, 0x003F, 0x0000, 1, 0x0100 }, /* R37 */
66 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R38 */
67 { 0x0000, 0x000F, 0x0000, 0, 0x0000 }, /* R39 */
68 { 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R40 */
69 { 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R41 */
70 { 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R42 */
71 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R43 */
72 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R44 */
73 { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R45 */
74 { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R46 */
75 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R47 */
76 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R48 */
77 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R49 */
78 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R50 */
79 { 0x0000, 0x01B3, 0x0000, 1, 0x0180 }, /* R51 */
80 { 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R52 */
81 { 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R53 */
82 { 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R54 */
83 { 0x0000, 0x0001, 0x0000, 1, 0x0000 }, /* R55 */
84 { 0x0000, 0x003F, 0x0000, 1, 0x0000 }, /* R56 */
85 { 0x0000, 0x004F, 0x0000, 1, 0x0000 }, /* R57 */
86 { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R58 */
87 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R59 */
88 { 0x1FFF, 0x1FFF, 0x0000, 1, 0x0000 }, /* R60 */
89 { 0xFFFF, 0xFFFF, 0x0000, 1, 0x0000 }, /* R61 */
90 { 0x03FF, 0x03FF, 0x0000, 1, 0x0000 }, /* R62 */
91 { 0x007F, 0x007F, 0x0000, 1, 0x0000 }, /* R63 */
92 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R64 */
93 { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R65 */
94 { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R66 */
95 { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R67 */
96 { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R68 */
97 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R69 */
98 { 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R70 */
99 { 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R71 */
100 { 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R72 */
101 { 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R73 */
102 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R74 */
103 { 0x000E, 0x000E, 0x0000, 0, 0x0008 }, /* R75 */
104 { 0xE00F, 0xE00F, 0x0000, 0, 0x0000 }, /* R76 */
105 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R77 */
106 { 0x03C0, 0x03C0, 0x0000, 0, 0x02C0 }, /* R78 */
107 { 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R79 */
108 { 0xFFFF, 0xFFFF, 0x0000, 0, 0x0000 }, /* R80 */
109 { 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R81 */
110 { 0x2BFF, 0x0000, 0xffff, 0, 0x0000 }, /* R82 */
111 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R83 */
112 { 0x80FF, 0x80FF, 0x0000, 0, 0x00ff }, /* R84 */
113};
114
115static int wm8400_read(struct wm8400 *wm8400, u8 reg, int num_regs, u16 *dest)
116{
117 int i, ret = 0;
118
119 BUG_ON(reg + num_regs - 1 > ARRAY_SIZE(wm8400->reg_cache));
120
121 /* If there are any volatile reads then read back the entire block */
122 for (i = reg; i < reg + num_regs; i++)
123 if (reg_data[i].vol) {
124 ret = wm8400->read_dev(wm8400->io_data, reg,
125 num_regs, dest);
126 if (ret != 0)
127 return ret;
128 for (i = 0; i < num_regs; i++)
129 dest[i] = be16_to_cpu(dest[i]);
130
131 return 0;
132 }
133
134 /* Otherwise use the cache */
135 memcpy(dest, &wm8400->reg_cache[reg], num_regs * sizeof(u16));
136
137 return 0;
138}
139
140static int wm8400_write(struct wm8400 *wm8400, u8 reg, int num_regs,
141 u16 *src)
142{
143 int ret, i;
144
145 BUG_ON(reg + num_regs - 1 > ARRAY_SIZE(wm8400->reg_cache));
146
147 for (i = 0; i < num_regs; i++) {
148 BUG_ON(!reg_data[reg + i].writable);
149 wm8400->reg_cache[reg + i] = src[i];
150 src[i] = cpu_to_be16(src[i]);
151 }
152
153 /* Do the actual I/O */
154 ret = wm8400->write_dev(wm8400->io_data, reg, num_regs, src);
155 if (ret != 0)
156 return -EIO;
157
158 return 0;
159}
160
161/**
162 * wm8400_reg_read - Single register read
163 *
164 * @wm8400: Pointer to wm8400 control structure
165 * @reg: Register to read
166 *
167 * @return Read value
168 */
169u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg)
170{
171 u16 val;
172
173 mutex_lock(&wm8400->io_lock);
174
175 wm8400_read(wm8400, reg, 1, &val);
176
177 mutex_unlock(&wm8400->io_lock);
178
179 return val;
180}
181EXPORT_SYMBOL_GPL(wm8400_reg_read);
182
183int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data)
184{
185 int ret;
186
187 mutex_lock(&wm8400->io_lock);
188
189 ret = wm8400_read(wm8400, reg, count, data);
190
191 mutex_unlock(&wm8400->io_lock);
192
193 return ret;
194}
195EXPORT_SYMBOL_GPL(wm8400_block_read);
196
197/**
198 * wm8400_set_bits - Bitmask write
199 *
200 * @wm8400: Pointer to wm8400 control structure
201 * @reg: Register to access
202 * @mask: Mask of bits to change
203 * @val: Value to set for masked bits
204 */
205int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val)
206{
207 u16 tmp;
208 int ret;
209
210 mutex_lock(&wm8400->io_lock);
211
212 ret = wm8400_read(wm8400, reg, 1, &tmp);
213 tmp = (tmp & ~mask) | val;
214 if (ret == 0)
215 ret = wm8400_write(wm8400, reg, 1, &tmp);
216
217 mutex_unlock(&wm8400->io_lock);
218
219 return ret;
220}
221EXPORT_SYMBOL_GPL(wm8400_set_bits);
222
223/**
224 * wm8400_reset_codec_reg_cache - Reset cached codec registers to
225 * their default values.
226 */
227void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400)
228{
229 int i;
230
231 mutex_lock(&wm8400->io_lock);
232
233 /* Reset all codec registers to their initial value */
234 for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
235 if (reg_data[i].is_codec)
236 wm8400->reg_cache[i] = reg_data[i].default_val;
237
238 mutex_unlock(&wm8400->io_lock);
239}
240EXPORT_SYMBOL_GPL(wm8400_reset_codec_reg_cache);
241
242/*
243 * wm8400_init - Generic initialisation
244 *
245 * The WM8400 can be configured as either an I2C or SPI device. Probe
246 * functions for each bus set up the accessors then call into this to
247 * set up the device itself.
248 */
249static int wm8400_init(struct wm8400 *wm8400,
250 struct wm8400_platform_data *pdata)
251{
252 u16 reg;
253 int ret, i;
254
255 mutex_init(&wm8400->io_lock);
256
257 wm8400->dev->driver_data = wm8400;
258
259 /* Check that this is actually a WM8400 */
260 ret = wm8400->read_dev(wm8400->io_data, WM8400_RESET_ID, 1, &reg);
261 if (ret != 0) {
262 dev_err(wm8400->dev, "Chip ID register read failed\n");
263 return -EIO;
264 }
265 if (be16_to_cpu(reg) != reg_data[WM8400_RESET_ID].default_val) {
266 dev_err(wm8400->dev, "Device is not a WM8400, ID is %x\n",
267 be16_to_cpu(reg));
268 return -ENODEV;
269 }
270
271 /* We don't know what state the hardware is in and since this
272 * is a PMIC we can't reset it safely so initialise the register
273 * cache from the hardware.
274 */
275 ret = wm8400->read_dev(wm8400->io_data, 0,
276 ARRAY_SIZE(wm8400->reg_cache),
277 wm8400->reg_cache);
278 if (ret != 0) {
279 dev_err(wm8400->dev, "Register cache read failed\n");
280 return -EIO;
281 }
282 for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
283 wm8400->reg_cache[i] = be16_to_cpu(wm8400->reg_cache[i]);
284
285 /* If the codec is in reset use hard coded values */
286 if (!(wm8400->reg_cache[WM8400_POWER_MANAGEMENT_1] & WM8400_CODEC_ENA))
287 for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
288 if (reg_data[i].is_codec)
289 wm8400->reg_cache[i] = reg_data[i].default_val;
290
291 ret = wm8400_read(wm8400, WM8400_ID, 1, &reg);
292 if (ret != 0) {
293 dev_err(wm8400->dev, "ID register read failed: %d\n", ret);
294 return ret;
295 }
296 reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT;
297 dev_info(wm8400->dev, "WM8400 revision %x\n", reg);
298
299 if (pdata && pdata->platform_init) {
300 ret = pdata->platform_init(wm8400->dev);
301 if (ret != 0)
302 dev_err(wm8400->dev, "Platform init failed: %d\n",
303 ret);
304 } else
305 dev_warn(wm8400->dev, "No platform initialisation supplied\n");
306
307 return ret;
308}
309
310static void wm8400_release(struct wm8400 *wm8400)
311{
312 int i;
313
314 for (i = 0; i < ARRAY_SIZE(wm8400->regulators); i++)
315 if (wm8400->regulators[i].name)
316 platform_device_unregister(&wm8400->regulators[i]);
317}
318
319#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
320static int wm8400_i2c_read(void *io_data, char reg, int count, u16 *dest)
321{
322 struct i2c_client *i2c = io_data;
323 struct i2c_msg xfer[2];
324 int ret;
325
326 /* Write register */
327 xfer[0].addr = i2c->addr;
328 xfer[0].flags = 0;
329 xfer[0].len = 1;
330 xfer[0].buf = &reg;
331
332 /* Read data */
333 xfer[1].addr = i2c->addr;
334 xfer[1].flags = I2C_M_RD;
335 xfer[1].len = count * sizeof(u16);
336 xfer[1].buf = (u8 *)dest;
337
338 ret = i2c_transfer(i2c->adapter, xfer, 2);
339 if (ret == 2)
340 ret = 0;
341 else if (ret >= 0)
342 ret = -EIO;
343
344 return ret;
345}
346
347static int wm8400_i2c_write(void *io_data, char reg, int count, const u16 *src)
348{
349 struct i2c_client *i2c = io_data;
350 u8 *msg;
351 int ret;
352
353 /* We add 1 byte for device register - ideally I2C would gather. */
354 msg = kmalloc((count * sizeof(u16)) + 1, GFP_KERNEL);
355 if (msg == NULL)
356 return -ENOMEM;
357
358 msg[0] = reg;
359 memcpy(&msg[1], src, count * sizeof(u16));
360
361 ret = i2c_master_send(i2c, msg, (count * sizeof(u16)) + 1);
362
363 if (ret == (count * 2) + 1)
364 ret = 0;
365 else if (ret >= 0)
366 ret = -EIO;
367
368 kfree(msg);
369
370 return ret;
371}
372
373static int wm8400_i2c_probe(struct i2c_client *i2c,
374 const struct i2c_device_id *id)
375{
376 struct wm8400 *wm8400;
377 int ret;
378
379 wm8400 = kzalloc(sizeof(struct wm8400), GFP_KERNEL);
380 if (wm8400 == NULL) {
381 ret = -ENOMEM;
382 goto err;
383 }
384
385 wm8400->io_data = i2c;
386 wm8400->read_dev = wm8400_i2c_read;
387 wm8400->write_dev = wm8400_i2c_write;
388 wm8400->dev = &i2c->dev;
389 i2c_set_clientdata(i2c, wm8400);
390
391 ret = wm8400_init(wm8400, i2c->dev.platform_data);
392 if (ret != 0)
393 goto struct_err;
394
395 return 0;
396
397struct_err:
398 i2c_set_clientdata(i2c, NULL);
399 kfree(wm8400);
400err:
401 return ret;
402}
403
404static int wm8400_i2c_remove(struct i2c_client *i2c)
405{
406 struct wm8400 *wm8400 = i2c_get_clientdata(i2c);
407
408 wm8400_release(wm8400);
409 i2c_set_clientdata(i2c, NULL);
410 kfree(wm8400);
411
412 return 0;
413}
414
415static const struct i2c_device_id wm8400_i2c_id[] = {
416 { "wm8400", 0 },
417 { }
418};
419MODULE_DEVICE_TABLE(i2c, wm8400_i2c_id);
420
421static struct i2c_driver wm8400_i2c_driver = {
422 .driver = {
423 .name = "WM8400",
424 .owner = THIS_MODULE,
425 },
426 .probe = wm8400_i2c_probe,
427 .remove = wm8400_i2c_remove,
428 .id_table = wm8400_i2c_id,
429};
430#endif
431
432static int __init wm8400_module_init(void)
433{
434 int ret = -ENODEV;
435
436#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
437 ret = i2c_add_driver(&wm8400_i2c_driver);
438 if (ret != 0)
439 pr_err("Failed to register I2C driver: %d\n", ret);
440#endif
441
442 return ret;
443}
444module_init(wm8400_module_init);
445
446static void __exit wm8400_module_exit(void)
447{
448#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
449 i2c_del_driver(&wm8400_i2c_driver);
450#endif
451}
452module_exit(wm8400_module_exit);
453
454MODULE_LICENSE("GPL");
455MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
diff --git a/include/linux/mfd/wm8400-audio.h b/include/linux/mfd/wm8400-audio.h
new file mode 100644
index 000000000000..b6640e018046
--- /dev/null
+++ b/include/linux/mfd/wm8400-audio.h
@@ -0,0 +1,1186 @@
1/*
2 * wm8400 private definitions for audio
3 *
4 * Copyright 2008 Wolfson Microelectronics plc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#ifndef __LINUX_MFD_WM8400_AUDIO_H
22#define __LINUX_MFD_WM8400_AUDIO_H
23
24#include <linux/mfd/wm8400-audio.h>
25
26/*
27 * R2 (0x02) - Power Management (1)
28 */
29#define WM8400_CODEC_ENA 0x8000 /* CODEC_ENA */
30#define WM8400_CODEC_ENA_MASK 0x8000 /* CODEC_ENA */
31#define WM8400_CODEC_ENA_SHIFT 15 /* CODEC_ENA */
32#define WM8400_CODEC_ENA_WIDTH 1 /* CODEC_ENA */
33#define WM8400_SYSCLK_ENA 0x4000 /* SYSCLK_ENA */
34#define WM8400_SYSCLK_ENA_MASK 0x4000 /* SYSCLK_ENA */
35#define WM8400_SYSCLK_ENA_SHIFT 14 /* SYSCLK_ENA */
36#define WM8400_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */
37#define WM8400_SPK_MIX_ENA 0x2000 /* SPK_MIX_ENA */
38#define WM8400_SPK_MIX_ENA_MASK 0x2000 /* SPK_MIX_ENA */
39#define WM8400_SPK_MIX_ENA_SHIFT 13 /* SPK_MIX_ENA */
40#define WM8400_SPK_MIX_ENA_WIDTH 1 /* SPK_MIX_ENA */
41#define WM8400_SPK_ENA 0x1000 /* SPK_ENA */
42#define WM8400_SPK_ENA_MASK 0x1000 /* SPK_ENA */
43#define WM8400_SPK_ENA_SHIFT 12 /* SPK_ENA */
44#define WM8400_SPK_ENA_WIDTH 1 /* SPK_ENA */
45#define WM8400_OUT3_ENA 0x0800 /* OUT3_ENA */
46#define WM8400_OUT3_ENA_MASK 0x0800 /* OUT3_ENA */
47#define WM8400_OUT3_ENA_SHIFT 11 /* OUT3_ENA */
48#define WM8400_OUT3_ENA_WIDTH 1 /* OUT3_ENA */
49#define WM8400_OUT4_ENA 0x0400 /* OUT4_ENA */
50#define WM8400_OUT4_ENA_MASK 0x0400 /* OUT4_ENA */
51#define WM8400_OUT4_ENA_SHIFT 10 /* OUT4_ENA */
52#define WM8400_OUT4_ENA_WIDTH 1 /* OUT4_ENA */
53#define WM8400_LOUT_ENA 0x0200 /* LOUT_ENA */
54#define WM8400_LOUT_ENA_MASK 0x0200 /* LOUT_ENA */
55#define WM8400_LOUT_ENA_SHIFT 9 /* LOUT_ENA */
56#define WM8400_LOUT_ENA_WIDTH 1 /* LOUT_ENA */
57#define WM8400_ROUT_ENA 0x0100 /* ROUT_ENA */
58#define WM8400_ROUT_ENA_MASK 0x0100 /* ROUT_ENA */
59#define WM8400_ROUT_ENA_SHIFT 8 /* ROUT_ENA */
60#define WM8400_ROUT_ENA_WIDTH 1 /* ROUT_ENA */
61#define WM8400_MIC1BIAS_ENA 0x0010 /* MIC1BIAS_ENA */
62#define WM8400_MIC1BIAS_ENA_MASK 0x0010 /* MIC1BIAS_ENA */
63#define WM8400_MIC1BIAS_ENA_SHIFT 4 /* MIC1BIAS_ENA */
64#define WM8400_MIC1BIAS_ENA_WIDTH 1 /* MIC1BIAS_ENA */
65#define WM8400_VMID_MODE_MASK 0x0006 /* VMID_MODE - [2:1] */
66#define WM8400_VMID_MODE_SHIFT 1 /* VMID_MODE - [2:1] */
67#define WM8400_VMID_MODE_WIDTH 2 /* VMID_MODE - [2:1] */
68#define WM8400_VREF_ENA 0x0001 /* VREF_ENA */
69#define WM8400_VREF_ENA_MASK 0x0001 /* VREF_ENA */
70#define WM8400_VREF_ENA_SHIFT 0 /* VREF_ENA */
71#define WM8400_VREF_ENA_WIDTH 1 /* VREF_ENA */
72
73/*
74 * R3 (0x03) - Power Management (2)
75 */
76#define WM8400_FLL_ENA 0x8000 /* FLL_ENA */
77#define WM8400_FLL_ENA_MASK 0x8000 /* FLL_ENA */
78#define WM8400_FLL_ENA_SHIFT 15 /* FLL_ENA */
79#define WM8400_FLL_ENA_WIDTH 1 /* FLL_ENA */
80#define WM8400_TSHUT_ENA 0x4000 /* TSHUT_ENA */
81#define WM8400_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */
82#define WM8400_TSHUT_ENA_SHIFT 14 /* TSHUT_ENA */
83#define WM8400_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
84#define WM8400_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */
85#define WM8400_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */
86#define WM8400_TSHUT_OPDIS_SHIFT 13 /* TSHUT_OPDIS */
87#define WM8400_TSHUT_OPDIS_WIDTH 1 /* TSHUT_OPDIS */
88#define WM8400_OPCLK_ENA 0x0800 /* OPCLK_ENA */
89#define WM8400_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */
90#define WM8400_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */
91#define WM8400_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
92#define WM8400_AINL_ENA 0x0200 /* AINL_ENA */
93#define WM8400_AINL_ENA_MASK 0x0200 /* AINL_ENA */
94#define WM8400_AINL_ENA_SHIFT 9 /* AINL_ENA */
95#define WM8400_AINL_ENA_WIDTH 1 /* AINL_ENA */
96#define WM8400_AINR_ENA 0x0100 /* AINR_ENA */
97#define WM8400_AINR_ENA_MASK 0x0100 /* AINR_ENA */
98#define WM8400_AINR_ENA_SHIFT 8 /* AINR_ENA */
99#define WM8400_AINR_ENA_WIDTH 1 /* AINR_ENA */
100#define WM8400_LIN34_ENA 0x0080 /* LIN34_ENA */
101#define WM8400_LIN34_ENA_MASK 0x0080 /* LIN34_ENA */
102#define WM8400_LIN34_ENA_SHIFT 7 /* LIN34_ENA */
103#define WM8400_LIN34_ENA_WIDTH 1 /* LIN34_ENA */
104#define WM8400_LIN12_ENA 0x0040 /* LIN12_ENA */
105#define WM8400_LIN12_ENA_MASK 0x0040 /* LIN12_ENA */
106#define WM8400_LIN12_ENA_SHIFT 6 /* LIN12_ENA */
107#define WM8400_LIN12_ENA_WIDTH 1 /* LIN12_ENA */
108#define WM8400_RIN34_ENA 0x0020 /* RIN34_ENA */
109#define WM8400_RIN34_ENA_MASK 0x0020 /* RIN34_ENA */
110#define WM8400_RIN34_ENA_SHIFT 5 /* RIN34_ENA */
111#define WM8400_RIN34_ENA_WIDTH 1 /* RIN34_ENA */
112#define WM8400_RIN12_ENA 0x0010 /* RIN12_ENA */
113#define WM8400_RIN12_ENA_MASK 0x0010 /* RIN12_ENA */
114#define WM8400_RIN12_ENA_SHIFT 4 /* RIN12_ENA */
115#define WM8400_RIN12_ENA_WIDTH 1 /* RIN12_ENA */
116#define WM8400_ADCL_ENA 0x0002 /* ADCL_ENA */
117#define WM8400_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */
118#define WM8400_ADCL_ENA_SHIFT 1 /* ADCL_ENA */
119#define WM8400_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
120#define WM8400_ADCR_ENA 0x0001 /* ADCR_ENA */
121#define WM8400_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
122#define WM8400_ADCR_ENA_SHIFT 0 /* ADCR_ENA */
123#define WM8400_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
124
125/*
126 * R4 (0x04) - Power Management (3)
127 */
128#define WM8400_LON_ENA 0x2000 /* LON_ENA */
129#define WM8400_LON_ENA_MASK 0x2000 /* LON_ENA */
130#define WM8400_LON_ENA_SHIFT 13 /* LON_ENA */
131#define WM8400_LON_ENA_WIDTH 1 /* LON_ENA */
132#define WM8400_LOP_ENA 0x1000 /* LOP_ENA */
133#define WM8400_LOP_ENA_MASK 0x1000 /* LOP_ENA */
134#define WM8400_LOP_ENA_SHIFT 12 /* LOP_ENA */
135#define WM8400_LOP_ENA_WIDTH 1 /* LOP_ENA */
136#define WM8400_RON_ENA 0x0800 /* RON_ENA */
137#define WM8400_RON_ENA_MASK 0x0800 /* RON_ENA */
138#define WM8400_RON_ENA_SHIFT 11 /* RON_ENA */
139#define WM8400_RON_ENA_WIDTH 1 /* RON_ENA */
140#define WM8400_ROP_ENA 0x0400 /* ROP_ENA */
141#define WM8400_ROP_ENA_MASK 0x0400 /* ROP_ENA */
142#define WM8400_ROP_ENA_SHIFT 10 /* ROP_ENA */
143#define WM8400_ROP_ENA_WIDTH 1 /* ROP_ENA */
144#define WM8400_LOPGA_ENA 0x0080 /* LOPGA_ENA */
145#define WM8400_LOPGA_ENA_MASK 0x0080 /* LOPGA_ENA */
146#define WM8400_LOPGA_ENA_SHIFT 7 /* LOPGA_ENA */
147#define WM8400_LOPGA_ENA_WIDTH 1 /* LOPGA_ENA */
148#define WM8400_ROPGA_ENA 0x0040 /* ROPGA_ENA */
149#define WM8400_ROPGA_ENA_MASK 0x0040 /* ROPGA_ENA */
150#define WM8400_ROPGA_ENA_SHIFT 6 /* ROPGA_ENA */
151#define WM8400_ROPGA_ENA_WIDTH 1 /* ROPGA_ENA */
152#define WM8400_LOMIX_ENA 0x0020 /* LOMIX_ENA */
153#define WM8400_LOMIX_ENA_MASK 0x0020 /* LOMIX_ENA */
154#define WM8400_LOMIX_ENA_SHIFT 5 /* LOMIX_ENA */
155#define WM8400_LOMIX_ENA_WIDTH 1 /* LOMIX_ENA */
156#define WM8400_ROMIX_ENA 0x0010 /* ROMIX_ENA */
157#define WM8400_ROMIX_ENA_MASK 0x0010 /* ROMIX_ENA */
158#define WM8400_ROMIX_ENA_SHIFT 4 /* ROMIX_ENA */
159#define WM8400_ROMIX_ENA_WIDTH 1 /* ROMIX_ENA */
160#define WM8400_DACL_ENA 0x0002 /* DACL_ENA */
161#define WM8400_DACL_ENA_MASK 0x0002 /* DACL_ENA */
162#define WM8400_DACL_ENA_SHIFT 1 /* DACL_ENA */
163#define WM8400_DACL_ENA_WIDTH 1 /* DACL_ENA */
164#define WM8400_DACR_ENA 0x0001 /* DACR_ENA */
165#define WM8400_DACR_ENA_MASK 0x0001 /* DACR_ENA */
166#define WM8400_DACR_ENA_SHIFT 0 /* DACR_ENA */
167#define WM8400_DACR_ENA_WIDTH 1 /* DACR_ENA */
168
169/*
170 * R5 (0x05) - Audio Interface (1)
171 */
172#define WM8400_AIFADCL_SRC 0x8000 /* AIFADCL_SRC */
173#define WM8400_AIFADCL_SRC_MASK 0x8000 /* AIFADCL_SRC */
174#define WM8400_AIFADCL_SRC_SHIFT 15 /* AIFADCL_SRC */
175#define WM8400_AIFADCL_SRC_WIDTH 1 /* AIFADCL_SRC */
176#define WM8400_AIFADCR_SRC 0x4000 /* AIFADCR_SRC */
177#define WM8400_AIFADCR_SRC_MASK 0x4000 /* AIFADCR_SRC */
178#define WM8400_AIFADCR_SRC_SHIFT 14 /* AIFADCR_SRC */
179#define WM8400_AIFADCR_SRC_WIDTH 1 /* AIFADCR_SRC */
180#define WM8400_AIFADC_TDM 0x2000 /* AIFADC_TDM */
181#define WM8400_AIFADC_TDM_MASK 0x2000 /* AIFADC_TDM */
182#define WM8400_AIFADC_TDM_SHIFT 13 /* AIFADC_TDM */
183#define WM8400_AIFADC_TDM_WIDTH 1 /* AIFADC_TDM */
184#define WM8400_AIFADC_TDM_CHAN 0x1000 /* AIFADC_TDM_CHAN */
185#define WM8400_AIFADC_TDM_CHAN_MASK 0x1000 /* AIFADC_TDM_CHAN */
186#define WM8400_AIFADC_TDM_CHAN_SHIFT 12 /* AIFADC_TDM_CHAN */
187#define WM8400_AIFADC_TDM_CHAN_WIDTH 1 /* AIFADC_TDM_CHAN */
188#define WM8400_AIF_BCLK_INV 0x0100 /* AIF_BCLK_INV */
189#define WM8400_AIF_BCLK_INV_MASK 0x0100 /* AIF_BCLK_INV */
190#define WM8400_AIF_BCLK_INV_SHIFT 8 /* AIF_BCLK_INV */
191#define WM8400_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */
192#define WM8400_AIF_LRCLK_INV 0x0080 /* AIF_LRCLK_INV */
193#define WM8400_AIF_LRCLK_INV_MASK 0x0080 /* AIF_LRCLK_INV */
194#define WM8400_AIF_LRCLK_INV_SHIFT 7 /* AIF_LRCLK_INV */
195#define WM8400_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */
196#define WM8400_AIF_WL_MASK 0x0060 /* AIF_WL - [6:5] */
197#define WM8400_AIF_WL_SHIFT 5 /* AIF_WL - [6:5] */
198#define WM8400_AIF_WL_WIDTH 2 /* AIF_WL - [6:5] */
199#define WM8400_AIF_WL_16BITS (0 << 5)
200#define WM8400_AIF_WL_20BITS (1 << 5)
201#define WM8400_AIF_WL_24BITS (2 << 5)
202#define WM8400_AIF_WL_32BITS (3 << 5)
203#define WM8400_AIF_FMT_MASK 0x0018 /* AIF_FMT - [4:3] */
204#define WM8400_AIF_FMT_SHIFT 3 /* AIF_FMT - [4:3] */
205#define WM8400_AIF_FMT_WIDTH 2 /* AIF_FMT - [4:3] */
206#define WM8400_AIF_FMT_RIGHTJ (0 << 3)
207#define WM8400_AIF_FMT_LEFTJ (1 << 3)
208#define WM8400_AIF_FMT_I2S (2 << 3)
209#define WM8400_AIF_FMT_DSP (3 << 3)
210
211/*
212 * R6 (0x06) - Audio Interface (2)
213 */
214#define WM8400_DACL_SRC 0x8000 /* DACL_SRC */
215#define WM8400_DACL_SRC_MASK 0x8000 /* DACL_SRC */
216#define WM8400_DACL_SRC_SHIFT 15 /* DACL_SRC */
217#define WM8400_DACL_SRC_WIDTH 1 /* DACL_SRC */
218#define WM8400_DACR_SRC 0x4000 /* DACR_SRC */
219#define WM8400_DACR_SRC_MASK 0x4000 /* DACR_SRC */
220#define WM8400_DACR_SRC_SHIFT 14 /* DACR_SRC */
221#define WM8400_DACR_SRC_WIDTH 1 /* DACR_SRC */
222#define WM8400_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */
223#define WM8400_AIFDAC_TDM_MASK 0x2000 /* AIFDAC_TDM */
224#define WM8400_AIFDAC_TDM_SHIFT 13 /* AIFDAC_TDM */
225#define WM8400_AIFDAC_TDM_WIDTH 1 /* AIFDAC_TDM */
226#define WM8400_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */
227#define WM8400_AIFDAC_TDM_CHAN_MASK 0x1000 /* AIFDAC_TDM_CHAN */
228#define WM8400_AIFDAC_TDM_CHAN_SHIFT 12 /* AIFDAC_TDM_CHAN */
229#define WM8400_AIFDAC_TDM_CHAN_WIDTH 1 /* AIFDAC_TDM_CHAN */
230#define WM8400_DAC_BOOST_MASK 0x0C00 /* DAC_BOOST - [11:10] */
231#define WM8400_DAC_BOOST_SHIFT 10 /* DAC_BOOST - [11:10] */
232#define WM8400_DAC_BOOST_WIDTH 2 /* DAC_BOOST - [11:10] */
233#define WM8400_DAC_COMP 0x0010 /* DAC_COMP */
234#define WM8400_DAC_COMP_MASK 0x0010 /* DAC_COMP */
235#define WM8400_DAC_COMP_SHIFT 4 /* DAC_COMP */
236#define WM8400_DAC_COMP_WIDTH 1 /* DAC_COMP */
237#define WM8400_DAC_COMPMODE 0x0008 /* DAC_COMPMODE */
238#define WM8400_DAC_COMPMODE_MASK 0x0008 /* DAC_COMPMODE */
239#define WM8400_DAC_COMPMODE_SHIFT 3 /* DAC_COMPMODE */
240#define WM8400_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */
241#define WM8400_ADC_COMP 0x0004 /* ADC_COMP */
242#define WM8400_ADC_COMP_MASK 0x0004 /* ADC_COMP */
243#define WM8400_ADC_COMP_SHIFT 2 /* ADC_COMP */
244#define WM8400_ADC_COMP_WIDTH 1 /* ADC_COMP */
245#define WM8400_ADC_COMPMODE 0x0002 /* ADC_COMPMODE */
246#define WM8400_ADC_COMPMODE_MASK 0x0002 /* ADC_COMPMODE */
247#define WM8400_ADC_COMPMODE_SHIFT 1 /* ADC_COMPMODE */
248#define WM8400_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */
249#define WM8400_LOOPBACK 0x0001 /* LOOPBACK */
250#define WM8400_LOOPBACK_MASK 0x0001 /* LOOPBACK */
251#define WM8400_LOOPBACK_SHIFT 0 /* LOOPBACK */
252#define WM8400_LOOPBACK_WIDTH 1 /* LOOPBACK */
253
254/*
255 * R7 (0x07) - Clocking (1)
256 */
257#define WM8400_TOCLK_RATE 0x8000 /* TOCLK_RATE */
258#define WM8400_TOCLK_RATE_MASK 0x8000 /* TOCLK_RATE */
259#define WM8400_TOCLK_RATE_SHIFT 15 /* TOCLK_RATE */
260#define WM8400_TOCLK_RATE_WIDTH 1 /* TOCLK_RATE */
261#define WM8400_TOCLK_ENA 0x4000 /* TOCLK_ENA */
262#define WM8400_TOCLK_ENA_MASK 0x4000 /* TOCLK_ENA */
263#define WM8400_TOCLK_ENA_SHIFT 14 /* TOCLK_ENA */
264#define WM8400_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
265#define WM8400_OPCLKDIV_MASK 0x1E00 /* OPCLKDIV - [12:9] */
266#define WM8400_OPCLKDIV_SHIFT 9 /* OPCLKDIV - [12:9] */
267#define WM8400_OPCLKDIV_WIDTH 4 /* OPCLKDIV - [12:9] */
268#define WM8400_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */
269#define WM8400_DCLKDIV_SHIFT 6 /* DCLKDIV - [8:6] */
270#define WM8400_DCLKDIV_WIDTH 3 /* DCLKDIV - [8:6] */
271#define WM8400_BCLK_DIV_MASK 0x001E /* BCLK_DIV - [4:1] */
272#define WM8400_BCLK_DIV_SHIFT 1 /* BCLK_DIV - [4:1] */
273#define WM8400_BCLK_DIV_WIDTH 4 /* BCLK_DIV - [4:1] */
274
275/*
276 * R8 (0x08) - Clocking (2)
277 */
278#define WM8400_MCLK_SRC 0x8000 /* MCLK_SRC */
279#define WM8400_MCLK_SRC_MASK 0x8000 /* MCLK_SRC */
280#define WM8400_MCLK_SRC_SHIFT 15 /* MCLK_SRC */
281#define WM8400_MCLK_SRC_WIDTH 1 /* MCLK_SRC */
282#define WM8400_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */
283#define WM8400_SYSCLK_SRC_MASK 0x4000 /* SYSCLK_SRC */
284#define WM8400_SYSCLK_SRC_SHIFT 14 /* SYSCLK_SRC */
285#define WM8400_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */
286#define WM8400_CLK_FORCE 0x2000 /* CLK_FORCE */
287#define WM8400_CLK_FORCE_MASK 0x2000 /* CLK_FORCE */
288#define WM8400_CLK_FORCE_SHIFT 13 /* CLK_FORCE */
289#define WM8400_CLK_FORCE_WIDTH 1 /* CLK_FORCE */
290#define WM8400_MCLK_DIV_MASK 0x1800 /* MCLK_DIV - [12:11] */
291#define WM8400_MCLK_DIV_SHIFT 11 /* MCLK_DIV - [12:11] */
292#define WM8400_MCLK_DIV_WIDTH 2 /* MCLK_DIV - [12:11] */
293#define WM8400_MCLK_INV 0x0400 /* MCLK_INV */
294#define WM8400_MCLK_INV_MASK 0x0400 /* MCLK_INV */
295#define WM8400_MCLK_INV_SHIFT 10 /* MCLK_INV */
296#define WM8400_MCLK_INV_WIDTH 1 /* MCLK_INV */
297#define WM8400_ADC_CLKDIV_MASK 0x00E0 /* ADC_CLKDIV - [7:5] */
298#define WM8400_ADC_CLKDIV_SHIFT 5 /* ADC_CLKDIV - [7:5] */
299#define WM8400_ADC_CLKDIV_WIDTH 3 /* ADC_CLKDIV - [7:5] */
300#define WM8400_DAC_CLKDIV_MASK 0x001C /* DAC_CLKDIV - [4:2] */
301#define WM8400_DAC_CLKDIV_SHIFT 2 /* DAC_CLKDIV - [4:2] */
302#define WM8400_DAC_CLKDIV_WIDTH 3 /* DAC_CLKDIV - [4:2] */
303
304/*
305 * R9 (0x09) - Audio Interface (3)
306 */
307#define WM8400_AIF_MSTR1 0x8000 /* AIF_MSTR1 */
308#define WM8400_AIF_MSTR1_MASK 0x8000 /* AIF_MSTR1 */
309#define WM8400_AIF_MSTR1_SHIFT 15 /* AIF_MSTR1 */
310#define WM8400_AIF_MSTR1_WIDTH 1 /* AIF_MSTR1 */
311#define WM8400_AIF_MSTR2 0x4000 /* AIF_MSTR2 */
312#define WM8400_AIF_MSTR2_MASK 0x4000 /* AIF_MSTR2 */
313#define WM8400_AIF_MSTR2_SHIFT 14 /* AIF_MSTR2 */
314#define WM8400_AIF_MSTR2_WIDTH 1 /* AIF_MSTR2 */
315#define WM8400_AIF_SEL 0x2000 /* AIF_SEL */
316#define WM8400_AIF_SEL_MASK 0x2000 /* AIF_SEL */
317#define WM8400_AIF_SEL_SHIFT 13 /* AIF_SEL */
318#define WM8400_AIF_SEL_WIDTH 1 /* AIF_SEL */
319#define WM8400_ADCLRC_DIR 0x0800 /* ADCLRC_DIR */
320#define WM8400_ADCLRC_DIR_MASK 0x0800 /* ADCLRC_DIR */
321#define WM8400_ADCLRC_DIR_SHIFT 11 /* ADCLRC_DIR */
322#define WM8400_ADCLRC_DIR_WIDTH 1 /* ADCLRC_DIR */
323#define WM8400_ADCLRC_RATE_MASK 0x07FF /* ADCLRC_RATE - [10:0] */
324#define WM8400_ADCLRC_RATE_SHIFT 0 /* ADCLRC_RATE - [10:0] */
325#define WM8400_ADCLRC_RATE_WIDTH 11 /* ADCLRC_RATE - [10:0] */
326
327/*
328 * R10 (0x0A) - Audio Interface (4)
329 */
330#define WM8400_ALRCGPIO1 0x8000 /* ALRCGPIO1 */
331#define WM8400_ALRCGPIO1_MASK 0x8000 /* ALRCGPIO1 */
332#define WM8400_ALRCGPIO1_SHIFT 15 /* ALRCGPIO1 */
333#define WM8400_ALRCGPIO1_WIDTH 1 /* ALRCGPIO1 */
334#define WM8400_ALRCBGPIO6 0x4000 /* ALRCBGPIO6 */
335#define WM8400_ALRCBGPIO6_MASK 0x4000 /* ALRCBGPIO6 */
336#define WM8400_ALRCBGPIO6_SHIFT 14 /* ALRCBGPIO6 */
337#define WM8400_ALRCBGPIO6_WIDTH 1 /* ALRCBGPIO6 */
338#define WM8400_AIF_TRIS 0x2000 /* AIF_TRIS */
339#define WM8400_AIF_TRIS_MASK 0x2000 /* AIF_TRIS */
340#define WM8400_AIF_TRIS_SHIFT 13 /* AIF_TRIS */
341#define WM8400_AIF_TRIS_WIDTH 1 /* AIF_TRIS */
342#define WM8400_DACLRC_DIR 0x0800 /* DACLRC_DIR */
343#define WM8400_DACLRC_DIR_MASK 0x0800 /* DACLRC_DIR */
344#define WM8400_DACLRC_DIR_SHIFT 11 /* DACLRC_DIR */
345#define WM8400_DACLRC_DIR_WIDTH 1 /* DACLRC_DIR */
346#define WM8400_DACLRC_RATE_MASK 0x07FF /* DACLRC_RATE - [10:0] */
347#define WM8400_DACLRC_RATE_SHIFT 0 /* DACLRC_RATE - [10:0] */
348#define WM8400_DACLRC_RATE_WIDTH 11 /* DACLRC_RATE - [10:0] */
349
350/*
351 * R11 (0x0B) - DAC CTRL
352 */
353#define WM8400_DAC_SDMCLK_RATE 0x2000 /* DAC_SDMCLK_RATE */
354#define WM8400_DAC_SDMCLK_RATE_MASK 0x2000 /* DAC_SDMCLK_RATE */
355#define WM8400_DAC_SDMCLK_RATE_SHIFT 13 /* DAC_SDMCLK_RATE */
356#define WM8400_DAC_SDMCLK_RATE_WIDTH 1 /* DAC_SDMCLK_RATE */
357#define WM8400_AIF_LRCLKRATE 0x0400 /* AIF_LRCLKRATE */
358#define WM8400_AIF_LRCLKRATE_MASK 0x0400 /* AIF_LRCLKRATE */
359#define WM8400_AIF_LRCLKRATE_SHIFT 10 /* AIF_LRCLKRATE */
360#define WM8400_AIF_LRCLKRATE_WIDTH 1 /* AIF_LRCLKRATE */
361#define WM8400_DAC_MONO 0x0200 /* DAC_MONO */
362#define WM8400_DAC_MONO_MASK 0x0200 /* DAC_MONO */
363#define WM8400_DAC_MONO_SHIFT 9 /* DAC_MONO */
364#define WM8400_DAC_MONO_WIDTH 1 /* DAC_MONO */
365#define WM8400_DAC_SB_FILT 0x0100 /* DAC_SB_FILT */
366#define WM8400_DAC_SB_FILT_MASK 0x0100 /* DAC_SB_FILT */
367#define WM8400_DAC_SB_FILT_SHIFT 8 /* DAC_SB_FILT */
368#define WM8400_DAC_SB_FILT_WIDTH 1 /* DAC_SB_FILT */
369#define WM8400_DAC_MUTERATE 0x0080 /* DAC_MUTERATE */
370#define WM8400_DAC_MUTERATE_MASK 0x0080 /* DAC_MUTERATE */
371#define WM8400_DAC_MUTERATE_SHIFT 7 /* DAC_MUTERATE */
372#define WM8400_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
373#define WM8400_DAC_MUTEMODE 0x0040 /* DAC_MUTEMODE */
374#define WM8400_DAC_MUTEMODE_MASK 0x0040 /* DAC_MUTEMODE */
375#define WM8400_DAC_MUTEMODE_SHIFT 6 /* DAC_MUTEMODE */
376#define WM8400_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */
377#define WM8400_DEEMP_MASK 0x0030 /* DEEMP - [5:4] */
378#define WM8400_DEEMP_SHIFT 4 /* DEEMP - [5:4] */
379#define WM8400_DEEMP_WIDTH 2 /* DEEMP - [5:4] */
380#define WM8400_DAC_MUTE 0x0004 /* DAC_MUTE */
381#define WM8400_DAC_MUTE_MASK 0x0004 /* DAC_MUTE */
382#define WM8400_DAC_MUTE_SHIFT 2 /* DAC_MUTE */
383#define WM8400_DAC_MUTE_WIDTH 1 /* DAC_MUTE */
384#define WM8400_DACL_DATINV 0x0002 /* DACL_DATINV */
385#define WM8400_DACL_DATINV_MASK 0x0002 /* DACL_DATINV */
386#define WM8400_DACL_DATINV_SHIFT 1 /* DACL_DATINV */
387#define WM8400_DACL_DATINV_WIDTH 1 /* DACL_DATINV */
388#define WM8400_DACR_DATINV 0x0001 /* DACR_DATINV */
389#define WM8400_DACR_DATINV_MASK 0x0001 /* DACR_DATINV */
390#define WM8400_DACR_DATINV_SHIFT 0 /* DACR_DATINV */
391#define WM8400_DACR_DATINV_WIDTH 1 /* DACR_DATINV */
392
393/*
394 * R12 (0x0C) - Left DAC Digital Volume
395 */
396#define WM8400_DAC_VU 0x0100 /* DAC_VU */
397#define WM8400_DAC_VU_MASK 0x0100 /* DAC_VU */
398#define WM8400_DAC_VU_SHIFT 8 /* DAC_VU */
399#define WM8400_DAC_VU_WIDTH 1 /* DAC_VU */
400#define WM8400_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */
401#define WM8400_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */
402#define WM8400_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */
403
404/*
405 * R13 (0x0D) - Right DAC Digital Volume
406 */
407#define WM8400_DAC_VU 0x0100 /* DAC_VU */
408#define WM8400_DAC_VU_MASK 0x0100 /* DAC_VU */
409#define WM8400_DAC_VU_SHIFT 8 /* DAC_VU */
410#define WM8400_DAC_VU_WIDTH 1 /* DAC_VU */
411#define WM8400_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */
412#define WM8400_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */
413#define WM8400_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */
414
415/*
416 * R14 (0x0E) - Digital Side Tone
417 */
418#define WM8400_ADCL_DAC_SVOL_MASK 0x1E00 /* ADCL_DAC_SVOL - [12:9] */
419#define WM8400_ADCL_DAC_SVOL_SHIFT 9 /* ADCL_DAC_SVOL - [12:9] */
420#define WM8400_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [12:9] */
421#define WM8400_ADCR_DAC_SVOL_MASK 0x01E0 /* ADCR_DAC_SVOL - [8:5] */
422#define WM8400_ADCR_DAC_SVOL_SHIFT 5 /* ADCR_DAC_SVOL - [8:5] */
423#define WM8400_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [8:5] */
424#define WM8400_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */
425#define WM8400_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */
426#define WM8400_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */
427#define WM8400_ADC_TO_DACR_MASK 0x0003 /* ADC_TO_DACR - [1:0] */
428#define WM8400_ADC_TO_DACR_SHIFT 0 /* ADC_TO_DACR - [1:0] */
429#define WM8400_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [1:0] */
430
431/*
432 * R15 (0x0F) - ADC CTRL
433 */
434#define WM8400_ADC_HPF_ENA 0x0100 /* ADC_HPF_ENA */
435#define WM8400_ADC_HPF_ENA_MASK 0x0100 /* ADC_HPF_ENA */
436#define WM8400_ADC_HPF_ENA_SHIFT 8 /* ADC_HPF_ENA */
437#define WM8400_ADC_HPF_ENA_WIDTH 1 /* ADC_HPF_ENA */
438#define WM8400_ADC_HPF_CUT_MASK 0x0060 /* ADC_HPF_CUT - [6:5] */
439#define WM8400_ADC_HPF_CUT_SHIFT 5 /* ADC_HPF_CUT - [6:5] */
440#define WM8400_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [6:5] */
441#define WM8400_ADCL_DATINV 0x0002 /* ADCL_DATINV */
442#define WM8400_ADCL_DATINV_MASK 0x0002 /* ADCL_DATINV */
443#define WM8400_ADCL_DATINV_SHIFT 1 /* ADCL_DATINV */
444#define WM8400_ADCL_DATINV_WIDTH 1 /* ADCL_DATINV */
445#define WM8400_ADCR_DATINV 0x0001 /* ADCR_DATINV */
446#define WM8400_ADCR_DATINV_MASK 0x0001 /* ADCR_DATINV */
447#define WM8400_ADCR_DATINV_SHIFT 0 /* ADCR_DATINV */
448#define WM8400_ADCR_DATINV_WIDTH 1 /* ADCR_DATINV */
449
450/*
451 * R16 (0x10) - Left ADC Digital Volume
452 */
453#define WM8400_ADC_VU 0x0100 /* ADC_VU */
454#define WM8400_ADC_VU_MASK 0x0100 /* ADC_VU */
455#define WM8400_ADC_VU_SHIFT 8 /* ADC_VU */
456#define WM8400_ADC_VU_WIDTH 1 /* ADC_VU */
457#define WM8400_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */
458#define WM8400_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */
459#define WM8400_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */
460
461/*
462 * R17 (0x11) - Right ADC Digital Volume
463 */
464#define WM8400_ADC_VU 0x0100 /* ADC_VU */
465#define WM8400_ADC_VU_MASK 0x0100 /* ADC_VU */
466#define WM8400_ADC_VU_SHIFT 8 /* ADC_VU */
467#define WM8400_ADC_VU_WIDTH 1 /* ADC_VU */
468#define WM8400_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */
469#define WM8400_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */
470#define WM8400_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */
471
472/*
473 * R24 (0x18) - Left Line Input 1&2 Volume
474 */
475#define WM8400_IPVU 0x0100 /* IPVU */
476#define WM8400_IPVU_MASK 0x0100 /* IPVU */
477#define WM8400_IPVU_SHIFT 8 /* IPVU */
478#define WM8400_IPVU_WIDTH 1 /* IPVU */
479#define WM8400_LI12MUTE 0x0080 /* LI12MUTE */
480#define WM8400_LI12MUTE_MASK 0x0080 /* LI12MUTE */
481#define WM8400_LI12MUTE_SHIFT 7 /* LI12MUTE */
482#define WM8400_LI12MUTE_WIDTH 1 /* LI12MUTE */
483#define WM8400_LI12ZC 0x0040 /* LI12ZC */
484#define WM8400_LI12ZC_MASK 0x0040 /* LI12ZC */
485#define WM8400_LI12ZC_SHIFT 6 /* LI12ZC */
486#define WM8400_LI12ZC_WIDTH 1 /* LI12ZC */
487#define WM8400_LIN12VOL_MASK 0x001F /* LIN12VOL - [4:0] */
488#define WM8400_LIN12VOL_SHIFT 0 /* LIN12VOL - [4:0] */
489#define WM8400_LIN12VOL_WIDTH 5 /* LIN12VOL - [4:0] */
490
491/*
492 * R25 (0x19) - Left Line Input 3&4 Volume
493 */
494#define WM8400_IPVU 0x0100 /* IPVU */
495#define WM8400_IPVU_MASK 0x0100 /* IPVU */
496#define WM8400_IPVU_SHIFT 8 /* IPVU */
497#define WM8400_IPVU_WIDTH 1 /* IPVU */
498#define WM8400_LI34MUTE 0x0080 /* LI34MUTE */
499#define WM8400_LI34MUTE_MASK 0x0080 /* LI34MUTE */
500#define WM8400_LI34MUTE_SHIFT 7 /* LI34MUTE */
501#define WM8400_LI34MUTE_WIDTH 1 /* LI34MUTE */
502#define WM8400_LI34ZC 0x0040 /* LI34ZC */
503#define WM8400_LI34ZC_MASK 0x0040 /* LI34ZC */
504#define WM8400_LI34ZC_SHIFT 6 /* LI34ZC */
505#define WM8400_LI34ZC_WIDTH 1 /* LI34ZC */
506#define WM8400_LIN34VOL_MASK 0x001F /* LIN34VOL - [4:0] */
507#define WM8400_LIN34VOL_SHIFT 0 /* LIN34VOL - [4:0] */
508#define WM8400_LIN34VOL_WIDTH 5 /* LIN34VOL - [4:0] */
509
510/*
511 * R26 (0x1A) - Right Line Input 1&2 Volume
512 */
513#define WM8400_IPVU 0x0100 /* IPVU */
514#define WM8400_IPVU_MASK 0x0100 /* IPVU */
515#define WM8400_IPVU_SHIFT 8 /* IPVU */
516#define WM8400_IPVU_WIDTH 1 /* IPVU */
517#define WM8400_RI12MUTE 0x0080 /* RI12MUTE */
518#define WM8400_RI12MUTE_MASK 0x0080 /* RI12MUTE */
519#define WM8400_RI12MUTE_SHIFT 7 /* RI12MUTE */
520#define WM8400_RI12MUTE_WIDTH 1 /* RI12MUTE */
521#define WM8400_RI12ZC 0x0040 /* RI12ZC */
522#define WM8400_RI12ZC_MASK 0x0040 /* RI12ZC */
523#define WM8400_RI12ZC_SHIFT 6 /* RI12ZC */
524#define WM8400_RI12ZC_WIDTH 1 /* RI12ZC */
525#define WM8400_RIN12VOL_MASK 0x001F /* RIN12VOL - [4:0] */
526#define WM8400_RIN12VOL_SHIFT 0 /* RIN12VOL - [4:0] */
527#define WM8400_RIN12VOL_WIDTH 5 /* RIN12VOL - [4:0] */
528
529/*
530 * R27 (0x1B) - Right Line Input 3&4 Volume
531 */
532#define WM8400_IPVU 0x0100 /* IPVU */
533#define WM8400_IPVU_MASK 0x0100 /* IPVU */
534#define WM8400_IPVU_SHIFT 8 /* IPVU */
535#define WM8400_IPVU_WIDTH 1 /* IPVU */
536#define WM8400_RI34MUTE 0x0080 /* RI34MUTE */
537#define WM8400_RI34MUTE_MASK 0x0080 /* RI34MUTE */
538#define WM8400_RI34MUTE_SHIFT 7 /* RI34MUTE */
539#define WM8400_RI34MUTE_WIDTH 1 /* RI34MUTE */
540#define WM8400_RI34ZC 0x0040 /* RI34ZC */
541#define WM8400_RI34ZC_MASK 0x0040 /* RI34ZC */
542#define WM8400_RI34ZC_SHIFT 6 /* RI34ZC */
543#define WM8400_RI34ZC_WIDTH 1 /* RI34ZC */
544#define WM8400_RIN34VOL_MASK 0x001F /* RIN34VOL - [4:0] */
545#define WM8400_RIN34VOL_SHIFT 0 /* RIN34VOL - [4:0] */
546#define WM8400_RIN34VOL_WIDTH 5 /* RIN34VOL - [4:0] */
547
548/*
549 * R28 (0x1C) - Left Output Volume
550 */
551#define WM8400_OPVU 0x0100 /* OPVU */
552#define WM8400_OPVU_MASK 0x0100 /* OPVU */
553#define WM8400_OPVU_SHIFT 8 /* OPVU */
554#define WM8400_OPVU_WIDTH 1 /* OPVU */
555#define WM8400_LOZC 0x0080 /* LOZC */
556#define WM8400_LOZC_MASK 0x0080 /* LOZC */
557#define WM8400_LOZC_SHIFT 7 /* LOZC */
558#define WM8400_LOZC_WIDTH 1 /* LOZC */
559#define WM8400_LOUTVOL_MASK 0x007F /* LOUTVOL - [6:0] */
560#define WM8400_LOUTVOL_SHIFT 0 /* LOUTVOL - [6:0] */
561#define WM8400_LOUTVOL_WIDTH 7 /* LOUTVOL - [6:0] */
562
563/*
564 * R29 (0x1D) - Right Output Volume
565 */
566#define WM8400_OPVU 0x0100 /* OPVU */
567#define WM8400_OPVU_MASK 0x0100 /* OPVU */
568#define WM8400_OPVU_SHIFT 8 /* OPVU */
569#define WM8400_OPVU_WIDTH 1 /* OPVU */
570#define WM8400_ROZC 0x0080 /* ROZC */
571#define WM8400_ROZC_MASK 0x0080 /* ROZC */
572#define WM8400_ROZC_SHIFT 7 /* ROZC */
573#define WM8400_ROZC_WIDTH 1 /* ROZC */
574#define WM8400_ROUTVOL_MASK 0x007F /* ROUTVOL - [6:0] */
575#define WM8400_ROUTVOL_SHIFT 0 /* ROUTVOL - [6:0] */
576#define WM8400_ROUTVOL_WIDTH 7 /* ROUTVOL - [6:0] */
577
578/*
579 * R30 (0x1E) - Line Outputs Volume
580 */
581#define WM8400_LONMUTE 0x0040 /* LONMUTE */
582#define WM8400_LONMUTE_MASK 0x0040 /* LONMUTE */
583#define WM8400_LONMUTE_SHIFT 6 /* LONMUTE */
584#define WM8400_LONMUTE_WIDTH 1 /* LONMUTE */
585#define WM8400_LOPMUTE 0x0020 /* LOPMUTE */
586#define WM8400_LOPMUTE_MASK 0x0020 /* LOPMUTE */
587#define WM8400_LOPMUTE_SHIFT 5 /* LOPMUTE */
588#define WM8400_LOPMUTE_WIDTH 1 /* LOPMUTE */
589#define WM8400_LOATTN 0x0010 /* LOATTN */
590#define WM8400_LOATTN_MASK 0x0010 /* LOATTN */
591#define WM8400_LOATTN_SHIFT 4 /* LOATTN */
592#define WM8400_LOATTN_WIDTH 1 /* LOATTN */
593#define WM8400_RONMUTE 0x0004 /* RONMUTE */
594#define WM8400_RONMUTE_MASK 0x0004 /* RONMUTE */
595#define WM8400_RONMUTE_SHIFT 2 /* RONMUTE */
596#define WM8400_RONMUTE_WIDTH 1 /* RONMUTE */
597#define WM8400_ROPMUTE 0x0002 /* ROPMUTE */
598#define WM8400_ROPMUTE_MASK 0x0002 /* ROPMUTE */
599#define WM8400_ROPMUTE_SHIFT 1 /* ROPMUTE */
600#define WM8400_ROPMUTE_WIDTH 1 /* ROPMUTE */
601#define WM8400_ROATTN 0x0001 /* ROATTN */
602#define WM8400_ROATTN_MASK 0x0001 /* ROATTN */
603#define WM8400_ROATTN_SHIFT 0 /* ROATTN */
604#define WM8400_ROATTN_WIDTH 1 /* ROATTN */
605
606/*
607 * R31 (0x1F) - Out3/4 Volume
608 */
609#define WM8400_OUT3MUTE 0x0020 /* OUT3MUTE */
610#define WM8400_OUT3MUTE_MASK 0x0020 /* OUT3MUTE */
611#define WM8400_OUT3MUTE_SHIFT 5 /* OUT3MUTE */
612#define WM8400_OUT3MUTE_WIDTH 1 /* OUT3MUTE */
613#define WM8400_OUT3ATTN 0x0010 /* OUT3ATTN */
614#define WM8400_OUT3ATTN_MASK 0x0010 /* OUT3ATTN */
615#define WM8400_OUT3ATTN_SHIFT 4 /* OUT3ATTN */
616#define WM8400_OUT3ATTN_WIDTH 1 /* OUT3ATTN */
617#define WM8400_OUT4MUTE 0x0002 /* OUT4MUTE */
618#define WM8400_OUT4MUTE_MASK 0x0002 /* OUT4MUTE */
619#define WM8400_OUT4MUTE_SHIFT 1 /* OUT4MUTE */
620#define WM8400_OUT4MUTE_WIDTH 1 /* OUT4MUTE */
621#define WM8400_OUT4ATTN 0x0001 /* OUT4ATTN */
622#define WM8400_OUT4ATTN_MASK 0x0001 /* OUT4ATTN */
623#define WM8400_OUT4ATTN_SHIFT 0 /* OUT4ATTN */
624#define WM8400_OUT4ATTN_WIDTH 1 /* OUT4ATTN */
625
626/*
627 * R32 (0x20) - Left OPGA Volume
628 */
629#define WM8400_OPVU 0x0100 /* OPVU */
630#define WM8400_OPVU_MASK 0x0100 /* OPVU */
631#define WM8400_OPVU_SHIFT 8 /* OPVU */
632#define WM8400_OPVU_WIDTH 1 /* OPVU */
633#define WM8400_LOPGAZC 0x0080 /* LOPGAZC */
634#define WM8400_LOPGAZC_MASK 0x0080 /* LOPGAZC */
635#define WM8400_LOPGAZC_SHIFT 7 /* LOPGAZC */
636#define WM8400_LOPGAZC_WIDTH 1 /* LOPGAZC */
637#define WM8400_LOPGAVOL_MASK 0x007F /* LOPGAVOL - [6:0] */
638#define WM8400_LOPGAVOL_SHIFT 0 /* LOPGAVOL - [6:0] */
639#define WM8400_LOPGAVOL_WIDTH 7 /* LOPGAVOL - [6:0] */
640
641/*
642 * R33 (0x21) - Right OPGA Volume
643 */
644#define WM8400_OPVU 0x0100 /* OPVU */
645#define WM8400_OPVU_MASK 0x0100 /* OPVU */
646#define WM8400_OPVU_SHIFT 8 /* OPVU */
647#define WM8400_OPVU_WIDTH 1 /* OPVU */
648#define WM8400_ROPGAZC 0x0080 /* ROPGAZC */
649#define WM8400_ROPGAZC_MASK 0x0080 /* ROPGAZC */
650#define WM8400_ROPGAZC_SHIFT 7 /* ROPGAZC */
651#define WM8400_ROPGAZC_WIDTH 1 /* ROPGAZC */
652#define WM8400_ROPGAVOL_MASK 0x007F /* ROPGAVOL - [6:0] */
653#define WM8400_ROPGAVOL_SHIFT 0 /* ROPGAVOL - [6:0] */
654#define WM8400_ROPGAVOL_WIDTH 7 /* ROPGAVOL - [6:0] */
655
656/*
657 * R34 (0x22) - Speaker Volume
658 */
659#define WM8400_SPKATTN_MASK 0x0003 /* SPKATTN - [1:0] */
660#define WM8400_SPKATTN_SHIFT 0 /* SPKATTN - [1:0] */
661#define WM8400_SPKATTN_WIDTH 2 /* SPKATTN - [1:0] */
662
663/*
664 * R35 (0x23) - ClassD1
665 */
666#define WM8400_CDMODE 0x0100 /* CDMODE */
667#define WM8400_CDMODE_MASK 0x0100 /* CDMODE */
668#define WM8400_CDMODE_SHIFT 8 /* CDMODE */
669#define WM8400_CDMODE_WIDTH 1 /* CDMODE */
670#define WM8400_CLASSD_CLK_SEL 0x0080 /* CLASSD_CLK_SEL */
671#define WM8400_CLASSD_CLK_SEL_MASK 0x0080 /* CLASSD_CLK_SEL */
672#define WM8400_CLASSD_CLK_SEL_SHIFT 7 /* CLASSD_CLK_SEL */
673#define WM8400_CLASSD_CLK_SEL_WIDTH 1 /* CLASSD_CLK_SEL */
674#define WM8400_CD_SRCTRL 0x0040 /* CD_SRCTRL */
675#define WM8400_CD_SRCTRL_MASK 0x0040 /* CD_SRCTRL */
676#define WM8400_CD_SRCTRL_SHIFT 6 /* CD_SRCTRL */
677#define WM8400_CD_SRCTRL_WIDTH 1 /* CD_SRCTRL */
678#define WM8400_SPKNOPOP 0x0020 /* SPKNOPOP */
679#define WM8400_SPKNOPOP_MASK 0x0020 /* SPKNOPOP */
680#define WM8400_SPKNOPOP_SHIFT 5 /* SPKNOPOP */
681#define WM8400_SPKNOPOP_WIDTH 1 /* SPKNOPOP */
682#define WM8400_DBLERATE 0x0010 /* DBLERATE */
683#define WM8400_DBLERATE_MASK 0x0010 /* DBLERATE */
684#define WM8400_DBLERATE_SHIFT 4 /* DBLERATE */
685#define WM8400_DBLERATE_WIDTH 1 /* DBLERATE */
686#define WM8400_LOOPTEST 0x0008 /* LOOPTEST */
687#define WM8400_LOOPTEST_MASK 0x0008 /* LOOPTEST */
688#define WM8400_LOOPTEST_SHIFT 3 /* LOOPTEST */
689#define WM8400_LOOPTEST_WIDTH 1 /* LOOPTEST */
690#define WM8400_HALFABBIAS 0x0004 /* HALFABBIAS */
691#define WM8400_HALFABBIAS_MASK 0x0004 /* HALFABBIAS */
692#define WM8400_HALFABBIAS_SHIFT 2 /* HALFABBIAS */
693#define WM8400_HALFABBIAS_WIDTH 1 /* HALFABBIAS */
694#define WM8400_TRIDEL_MASK 0x0003 /* TRIDEL - [1:0] */
695#define WM8400_TRIDEL_SHIFT 0 /* TRIDEL - [1:0] */
696#define WM8400_TRIDEL_WIDTH 2 /* TRIDEL - [1:0] */
697
698/*
699 * R37 (0x25) - ClassD3
700 */
701#define WM8400_DCGAIN_MASK 0x0038 /* DCGAIN - [5:3] */
702#define WM8400_DCGAIN_SHIFT 3 /* DCGAIN - [5:3] */
703#define WM8400_DCGAIN_WIDTH 3 /* DCGAIN - [5:3] */
704#define WM8400_ACGAIN_MASK 0x0007 /* ACGAIN - [2:0] */
705#define WM8400_ACGAIN_SHIFT 0 /* ACGAIN - [2:0] */
706#define WM8400_ACGAIN_WIDTH 3 /* ACGAIN - [2:0] */
707
708/*
709 * R39 (0x27) - Input Mixer1
710 */
711#define WM8400_AINLMODE_MASK 0x000C /* AINLMODE - [3:2] */
712#define WM8400_AINLMODE_SHIFT 2 /* AINLMODE - [3:2] */
713#define WM8400_AINLMODE_WIDTH 2 /* AINLMODE - [3:2] */
714#define WM8400_AINRMODE_MASK 0x0003 /* AINRMODE - [1:0] */
715#define WM8400_AINRMODE_SHIFT 0 /* AINRMODE - [1:0] */
716#define WM8400_AINRMODE_WIDTH 2 /* AINRMODE - [1:0] */
717
718/*
719 * R40 (0x28) - Input Mixer2
720 */
721#define WM8400_LMP4 0x0080 /* LMP4 */
722#define WM8400_LMP4_MASK 0x0080 /* LMP4 */
723#define WM8400_LMP4_SHIFT 7 /* LMP4 */
724#define WM8400_LMP4_WIDTH 1 /* LMP4 */
725#define WM8400_LMN3 0x0040 /* LMN3 */
726#define WM8400_LMN3_MASK 0x0040 /* LMN3 */
727#define WM8400_LMN3_SHIFT 6 /* LMN3 */
728#define WM8400_LMN3_WIDTH 1 /* LMN3 */
729#define WM8400_LMP2 0x0020 /* LMP2 */
730#define WM8400_LMP2_MASK 0x0020 /* LMP2 */
731#define WM8400_LMP2_SHIFT 5 /* LMP2 */
732#define WM8400_LMP2_WIDTH 1 /* LMP2 */
733#define WM8400_LMN1 0x0010 /* LMN1 */
734#define WM8400_LMN1_MASK 0x0010 /* LMN1 */
735#define WM8400_LMN1_SHIFT 4 /* LMN1 */
736#define WM8400_LMN1_WIDTH 1 /* LMN1 */
737#define WM8400_RMP4 0x0008 /* RMP4 */
738#define WM8400_RMP4_MASK 0x0008 /* RMP4 */
739#define WM8400_RMP4_SHIFT 3 /* RMP4 */
740#define WM8400_RMP4_WIDTH 1 /* RMP4 */
741#define WM8400_RMN3 0x0004 /* RMN3 */
742#define WM8400_RMN3_MASK 0x0004 /* RMN3 */
743#define WM8400_RMN3_SHIFT 2 /* RMN3 */
744#define WM8400_RMN3_WIDTH 1 /* RMN3 */
745#define WM8400_RMP2 0x0002 /* RMP2 */
746#define WM8400_RMP2_MASK 0x0002 /* RMP2 */
747#define WM8400_RMP2_SHIFT 1 /* RMP2 */
748#define WM8400_RMP2_WIDTH 1 /* RMP2 */
749#define WM8400_RMN1 0x0001 /* RMN1 */
750#define WM8400_RMN1_MASK 0x0001 /* RMN1 */
751#define WM8400_RMN1_SHIFT 0 /* RMN1 */
752#define WM8400_RMN1_WIDTH 1 /* RMN1 */
753
754/*
755 * R41 (0x29) - Input Mixer3
756 */
757#define WM8400_L34MNB 0x0100 /* L34MNB */
758#define WM8400_L34MNB_MASK 0x0100 /* L34MNB */
759#define WM8400_L34MNB_SHIFT 8 /* L34MNB */
760#define WM8400_L34MNB_WIDTH 1 /* L34MNB */
761#define WM8400_L34MNBST 0x0080 /* L34MNBST */
762#define WM8400_L34MNBST_MASK 0x0080 /* L34MNBST */
763#define WM8400_L34MNBST_SHIFT 7 /* L34MNBST */
764#define WM8400_L34MNBST_WIDTH 1 /* L34MNBST */
765#define WM8400_L12MNB 0x0020 /* L12MNB */
766#define WM8400_L12MNB_MASK 0x0020 /* L12MNB */
767#define WM8400_L12MNB_SHIFT 5 /* L12MNB */
768#define WM8400_L12MNB_WIDTH 1 /* L12MNB */
769#define WM8400_L12MNBST 0x0010 /* L12MNBST */
770#define WM8400_L12MNBST_MASK 0x0010 /* L12MNBST */
771#define WM8400_L12MNBST_SHIFT 4 /* L12MNBST */
772#define WM8400_L12MNBST_WIDTH 1 /* L12MNBST */
773#define WM8400_LDBVOL_MASK 0x0007 /* LDBVOL - [2:0] */
774#define WM8400_LDBVOL_SHIFT 0 /* LDBVOL - [2:0] */
775#define WM8400_LDBVOL_WIDTH 3 /* LDBVOL - [2:0] */
776
777/*
778 * R42 (0x2A) - Input Mixer4
779 */
780#define WM8400_R34MNB 0x0100 /* R34MNB */
781#define WM8400_R34MNB_MASK 0x0100 /* R34MNB */
782#define WM8400_R34MNB_SHIFT 8 /* R34MNB */
783#define WM8400_R34MNB_WIDTH 1 /* R34MNB */
784#define WM8400_R34MNBST 0x0080 /* R34MNBST */
785#define WM8400_R34MNBST_MASK 0x0080 /* R34MNBST */
786#define WM8400_R34MNBST_SHIFT 7 /* R34MNBST */
787#define WM8400_R34MNBST_WIDTH 1 /* R34MNBST */
788#define WM8400_R12MNB 0x0020 /* R12MNB */
789#define WM8400_R12MNB_MASK 0x0020 /* R12MNB */
790#define WM8400_R12MNB_SHIFT 5 /* R12MNB */
791#define WM8400_R12MNB_WIDTH 1 /* R12MNB */
792#define WM8400_R12MNBST 0x0010 /* R12MNBST */
793#define WM8400_R12MNBST_MASK 0x0010 /* R12MNBST */
794#define WM8400_R12MNBST_SHIFT 4 /* R12MNBST */
795#define WM8400_R12MNBST_WIDTH 1 /* R12MNBST */
796#define WM8400_RDBVOL_MASK 0x0007 /* RDBVOL - [2:0] */
797#define WM8400_RDBVOL_SHIFT 0 /* RDBVOL - [2:0] */
798#define WM8400_RDBVOL_WIDTH 3 /* RDBVOL - [2:0] */
799
800/*
801 * R43 (0x2B) - Input Mixer5
802 */
803#define WM8400_LI2BVOL_MASK 0x01C0 /* LI2BVOL - [8:6] */
804#define WM8400_LI2BVOL_SHIFT 6 /* LI2BVOL - [8:6] */
805#define WM8400_LI2BVOL_WIDTH 3 /* LI2BVOL - [8:6] */
806#define WM8400_LR4BVOL_MASK 0x0038 /* LR4BVOL - [5:3] */
807#define WM8400_LR4BVOL_SHIFT 3 /* LR4BVOL - [5:3] */
808#define WM8400_LR4BVOL_WIDTH 3 /* LR4BVOL - [5:3] */
809#define WM8400_LL4BVOL_MASK 0x0007 /* LL4BVOL - [2:0] */
810#define WM8400_LL4BVOL_SHIFT 0 /* LL4BVOL - [2:0] */
811#define WM8400_LL4BVOL_WIDTH 3 /* LL4BVOL - [2:0] */
812
813/*
814 * R44 (0x2C) - Input Mixer6
815 */
816#define WM8400_RI2BVOL_MASK 0x01C0 /* RI2BVOL - [8:6] */
817#define WM8400_RI2BVOL_SHIFT 6 /* RI2BVOL - [8:6] */
818#define WM8400_RI2BVOL_WIDTH 3 /* RI2BVOL - [8:6] */
819#define WM8400_RL4BVOL_MASK 0x0038 /* RL4BVOL - [5:3] */
820#define WM8400_RL4BVOL_SHIFT 3 /* RL4BVOL - [5:3] */
821#define WM8400_RL4BVOL_WIDTH 3 /* RL4BVOL - [5:3] */
822#define WM8400_RR4BVOL_MASK 0x0007 /* RR4BVOL - [2:0] */
823#define WM8400_RR4BVOL_SHIFT 0 /* RR4BVOL - [2:0] */
824#define WM8400_RR4BVOL_WIDTH 3 /* RR4BVOL - [2:0] */
825
826/*
827 * R45 (0x2D) - Output Mixer1
828 */
829#define WM8400_LRBLO 0x0080 /* LRBLO */
830#define WM8400_LRBLO_MASK 0x0080 /* LRBLO */
831#define WM8400_LRBLO_SHIFT 7 /* LRBLO */
832#define WM8400_LRBLO_WIDTH 1 /* LRBLO */
833#define WM8400_LLBLO 0x0040 /* LLBLO */
834#define WM8400_LLBLO_MASK 0x0040 /* LLBLO */
835#define WM8400_LLBLO_SHIFT 6 /* LLBLO */
836#define WM8400_LLBLO_WIDTH 1 /* LLBLO */
837#define WM8400_LRI3LO 0x0020 /* LRI3LO */
838#define WM8400_LRI3LO_MASK 0x0020 /* LRI3LO */
839#define WM8400_LRI3LO_SHIFT 5 /* LRI3LO */
840#define WM8400_LRI3LO_WIDTH 1 /* LRI3LO */
841#define WM8400_LLI3LO 0x0010 /* LLI3LO */
842#define WM8400_LLI3LO_MASK 0x0010 /* LLI3LO */
843#define WM8400_LLI3LO_SHIFT 4 /* LLI3LO */
844#define WM8400_LLI3LO_WIDTH 1 /* LLI3LO */
845#define WM8400_LR12LO 0x0008 /* LR12LO */
846#define WM8400_LR12LO_MASK 0x0008 /* LR12LO */
847#define WM8400_LR12LO_SHIFT 3 /* LR12LO */
848#define WM8400_LR12LO_WIDTH 1 /* LR12LO */
849#define WM8400_LL12LO 0x0004 /* LL12LO */
850#define WM8400_LL12LO_MASK 0x0004 /* LL12LO */
851#define WM8400_LL12LO_SHIFT 2 /* LL12LO */
852#define WM8400_LL12LO_WIDTH 1 /* LL12LO */
853#define WM8400_LDLO 0x0001 /* LDLO */
854#define WM8400_LDLO_MASK 0x0001 /* LDLO */
855#define WM8400_LDLO_SHIFT 0 /* LDLO */
856#define WM8400_LDLO_WIDTH 1 /* LDLO */
857
858/*
859 * R46 (0x2E) - Output Mixer2
860 */
861#define WM8400_RLBRO 0x0080 /* RLBRO */
862#define WM8400_RLBRO_MASK 0x0080 /* RLBRO */
863#define WM8400_RLBRO_SHIFT 7 /* RLBRO */
864#define WM8400_RLBRO_WIDTH 1 /* RLBRO */
865#define WM8400_RRBRO 0x0040 /* RRBRO */
866#define WM8400_RRBRO_MASK 0x0040 /* RRBRO */
867#define WM8400_RRBRO_SHIFT 6 /* RRBRO */
868#define WM8400_RRBRO_WIDTH 1 /* RRBRO */
869#define WM8400_RLI3RO 0x0020 /* RLI3RO */
870#define WM8400_RLI3RO_MASK 0x0020 /* RLI3RO */
871#define WM8400_RLI3RO_SHIFT 5 /* RLI3RO */
872#define WM8400_RLI3RO_WIDTH 1 /* RLI3RO */
873#define WM8400_RRI3RO 0x0010 /* RRI3RO */
874#define WM8400_RRI3RO_MASK 0x0010 /* RRI3RO */
875#define WM8400_RRI3RO_SHIFT 4 /* RRI3RO */
876#define WM8400_RRI3RO_WIDTH 1 /* RRI3RO */
877#define WM8400_RL12RO 0x0008 /* RL12RO */
878#define WM8400_RL12RO_MASK 0x0008 /* RL12RO */
879#define WM8400_RL12RO_SHIFT 3 /* RL12RO */
880#define WM8400_RL12RO_WIDTH 1 /* RL12RO */
881#define WM8400_RR12RO 0x0004 /* RR12RO */
882#define WM8400_RR12RO_MASK 0x0004 /* RR12RO */
883#define WM8400_RR12RO_SHIFT 2 /* RR12RO */
884#define WM8400_RR12RO_WIDTH 1 /* RR12RO */
885#define WM8400_RDRO 0x0001 /* RDRO */
886#define WM8400_RDRO_MASK 0x0001 /* RDRO */
887#define WM8400_RDRO_SHIFT 0 /* RDRO */
888#define WM8400_RDRO_WIDTH 1 /* RDRO */
889
890/*
891 * R47 (0x2F) - Output Mixer3
892 */
893#define WM8400_LLI3LOVOL_MASK 0x01C0 /* LLI3LOVOL - [8:6] */
894#define WM8400_LLI3LOVOL_SHIFT 6 /* LLI3LOVOL - [8:6] */
895#define WM8400_LLI3LOVOL_WIDTH 3 /* LLI3LOVOL - [8:6] */
896#define WM8400_LR12LOVOL_MASK 0x0038 /* LR12LOVOL - [5:3] */
897#define WM8400_LR12LOVOL_SHIFT 3 /* LR12LOVOL - [5:3] */
898#define WM8400_LR12LOVOL_WIDTH 3 /* LR12LOVOL - [5:3] */
899#define WM8400_LL12LOVOL_MASK 0x0007 /* LL12LOVOL - [2:0] */
900#define WM8400_LL12LOVOL_SHIFT 0 /* LL12LOVOL - [2:0] */
901#define WM8400_LL12LOVOL_WIDTH 3 /* LL12LOVOL - [2:0] */
902
903/*
904 * R48 (0x30) - Output Mixer4
905 */
906#define WM8400_RRI3ROVOL_MASK 0x01C0 /* RRI3ROVOL - [8:6] */
907#define WM8400_RRI3ROVOL_SHIFT 6 /* RRI3ROVOL - [8:6] */
908#define WM8400_RRI3ROVOL_WIDTH 3 /* RRI3ROVOL - [8:6] */
909#define WM8400_RL12ROVOL_MASK 0x0038 /* RL12ROVOL - [5:3] */
910#define WM8400_RL12ROVOL_SHIFT 3 /* RL12ROVOL - [5:3] */
911#define WM8400_RL12ROVOL_WIDTH 3 /* RL12ROVOL - [5:3] */
912#define WM8400_RR12ROVOL_MASK 0x0007 /* RR12ROVOL - [2:0] */
913#define WM8400_RR12ROVOL_SHIFT 0 /* RR12ROVOL - [2:0] */
914#define WM8400_RR12ROVOL_WIDTH 3 /* RR12ROVOL - [2:0] */
915
916/*
917 * R49 (0x31) - Output Mixer5
918 */
919#define WM8400_LRI3LOVOL_MASK 0x01C0 /* LRI3LOVOL - [8:6] */
920#define WM8400_LRI3LOVOL_SHIFT 6 /* LRI3LOVOL - [8:6] */
921#define WM8400_LRI3LOVOL_WIDTH 3 /* LRI3LOVOL - [8:6] */
922#define WM8400_LRBLOVOL_MASK 0x0038 /* LRBLOVOL - [5:3] */
923#define WM8400_LRBLOVOL_SHIFT 3 /* LRBLOVOL - [5:3] */
924#define WM8400_LRBLOVOL_WIDTH 3 /* LRBLOVOL - [5:3] */
925#define WM8400_LLBLOVOL_MASK 0x0007 /* LLBLOVOL - [2:0] */
926#define WM8400_LLBLOVOL_SHIFT 0 /* LLBLOVOL - [2:0] */
927#define WM8400_LLBLOVOL_WIDTH 3 /* LLBLOVOL - [2:0] */
928
929/*
930 * R50 (0x32) - Output Mixer6
931 */
932#define WM8400_RLI3ROVOL_MASK 0x01C0 /* RLI3ROVOL - [8:6] */
933#define WM8400_RLI3ROVOL_SHIFT 6 /* RLI3ROVOL - [8:6] */
934#define WM8400_RLI3ROVOL_WIDTH 3 /* RLI3ROVOL - [8:6] */
935#define WM8400_RLBROVOL_MASK 0x0038 /* RLBROVOL - [5:3] */
936#define WM8400_RLBROVOL_SHIFT 3 /* RLBROVOL - [5:3] */
937#define WM8400_RLBROVOL_WIDTH 3 /* RLBROVOL - [5:3] */
938#define WM8400_RRBROVOL_MASK 0x0007 /* RRBROVOL - [2:0] */
939#define WM8400_RRBROVOL_SHIFT 0 /* RRBROVOL - [2:0] */
940#define WM8400_RRBROVOL_WIDTH 3 /* RRBROVOL - [2:0] */
941
942/*
943 * R51 (0x33) - Out3/4 Mixer
944 */
945#define WM8400_VSEL_MASK 0x0180 /* VSEL - [8:7] */
946#define WM8400_VSEL_SHIFT 7 /* VSEL - [8:7] */
947#define WM8400_VSEL_WIDTH 2 /* VSEL - [8:7] */
948#define WM8400_LI4O3 0x0020 /* LI4O3 */
949#define WM8400_LI4O3_MASK 0x0020 /* LI4O3 */
950#define WM8400_LI4O3_SHIFT 5 /* LI4O3 */
951#define WM8400_LI4O3_WIDTH 1 /* LI4O3 */
952#define WM8400_LPGAO3 0x0010 /* LPGAO3 */
953#define WM8400_LPGAO3_MASK 0x0010 /* LPGAO3 */
954#define WM8400_LPGAO3_SHIFT 4 /* LPGAO3 */
955#define WM8400_LPGAO3_WIDTH 1 /* LPGAO3 */
956#define WM8400_RI4O4 0x0002 /* RI4O4 */
957#define WM8400_RI4O4_MASK 0x0002 /* RI4O4 */
958#define WM8400_RI4O4_SHIFT 1 /* RI4O4 */
959#define WM8400_RI4O4_WIDTH 1 /* RI4O4 */
960#define WM8400_RPGAO4 0x0001 /* RPGAO4 */
961#define WM8400_RPGAO4_MASK 0x0001 /* RPGAO4 */
962#define WM8400_RPGAO4_SHIFT 0 /* RPGAO4 */
963#define WM8400_RPGAO4_WIDTH 1 /* RPGAO4 */
964
965/*
966 * R52 (0x34) - Line Mixer1
967 */
968#define WM8400_LLOPGALON 0x0040 /* LLOPGALON */
969#define WM8400_LLOPGALON_MASK 0x0040 /* LLOPGALON */
970#define WM8400_LLOPGALON_SHIFT 6 /* LLOPGALON */
971#define WM8400_LLOPGALON_WIDTH 1 /* LLOPGALON */
972#define WM8400_LROPGALON 0x0020 /* LROPGALON */
973#define WM8400_LROPGALON_MASK 0x0020 /* LROPGALON */
974#define WM8400_LROPGALON_SHIFT 5 /* LROPGALON */
975#define WM8400_LROPGALON_WIDTH 1 /* LROPGALON */
976#define WM8400_LOPLON 0x0010 /* LOPLON */
977#define WM8400_LOPLON_MASK 0x0010 /* LOPLON */
978#define WM8400_LOPLON_SHIFT 4 /* LOPLON */
979#define WM8400_LOPLON_WIDTH 1 /* LOPLON */
980#define WM8400_LR12LOP 0x0004 /* LR12LOP */
981#define WM8400_LR12LOP_MASK 0x0004 /* LR12LOP */
982#define WM8400_LR12LOP_SHIFT 2 /* LR12LOP */
983#define WM8400_LR12LOP_WIDTH 1 /* LR12LOP */
984#define WM8400_LL12LOP 0x0002 /* LL12LOP */
985#define WM8400_LL12LOP_MASK 0x0002 /* LL12LOP */
986#define WM8400_LL12LOP_SHIFT 1 /* LL12LOP */
987#define WM8400_LL12LOP_WIDTH 1 /* LL12LOP */
988#define WM8400_LLOPGALOP 0x0001 /* LLOPGALOP */
989#define WM8400_LLOPGALOP_MASK 0x0001 /* LLOPGALOP */
990#define WM8400_LLOPGALOP_SHIFT 0 /* LLOPGALOP */
991#define WM8400_LLOPGALOP_WIDTH 1 /* LLOPGALOP */
992
993/*
994 * R53 (0x35) - Line Mixer2
995 */
996#define WM8400_RROPGARON 0x0040 /* RROPGARON */
997#define WM8400_RROPGARON_MASK 0x0040 /* RROPGARON */
998#define WM8400_RROPGARON_SHIFT 6 /* RROPGARON */
999#define WM8400_RROPGARON_WIDTH 1 /* RROPGARON */
1000#define WM8400_RLOPGARON 0x0020 /* RLOPGARON */
1001#define WM8400_RLOPGARON_MASK 0x0020 /* RLOPGARON */
1002#define WM8400_RLOPGARON_SHIFT 5 /* RLOPGARON */
1003#define WM8400_RLOPGARON_WIDTH 1 /* RLOPGARON */
1004#define WM8400_ROPRON 0x0010 /* ROPRON */
1005#define WM8400_ROPRON_MASK 0x0010 /* ROPRON */
1006#define WM8400_ROPRON_SHIFT 4 /* ROPRON */
1007#define WM8400_ROPRON_WIDTH 1 /* ROPRON */
1008#define WM8400_RL12ROP 0x0004 /* RL12ROP */
1009#define WM8400_RL12ROP_MASK 0x0004 /* RL12ROP */
1010#define WM8400_RL12ROP_SHIFT 2 /* RL12ROP */
1011#define WM8400_RL12ROP_WIDTH 1 /* RL12ROP */
1012#define WM8400_RR12ROP 0x0002 /* RR12ROP */
1013#define WM8400_RR12ROP_MASK 0x0002 /* RR12ROP */
1014#define WM8400_RR12ROP_SHIFT 1 /* RR12ROP */
1015#define WM8400_RR12ROP_WIDTH 1 /* RR12ROP */
1016#define WM8400_RROPGAROP 0x0001 /* RROPGAROP */
1017#define WM8400_RROPGAROP_MASK 0x0001 /* RROPGAROP */
1018#define WM8400_RROPGAROP_SHIFT 0 /* RROPGAROP */
1019#define WM8400_RROPGAROP_WIDTH 1 /* RROPGAROP */
1020
1021/*
1022 * R54 (0x36) - Speaker Mixer
1023 */
1024#define WM8400_LB2SPK 0x0080 /* LB2SPK */
1025#define WM8400_LB2SPK_MASK 0x0080 /* LB2SPK */
1026#define WM8400_LB2SPK_SHIFT 7 /* LB2SPK */
1027#define WM8400_LB2SPK_WIDTH 1 /* LB2SPK */
1028#define WM8400_RB2SPK 0x0040 /* RB2SPK */
1029#define WM8400_RB2SPK_MASK 0x0040 /* RB2SPK */
1030#define WM8400_RB2SPK_SHIFT 6 /* RB2SPK */
1031#define WM8400_RB2SPK_WIDTH 1 /* RB2SPK */
1032#define WM8400_LI2SPK 0x0020 /* LI2SPK */
1033#define WM8400_LI2SPK_MASK 0x0020 /* LI2SPK */
1034#define WM8400_LI2SPK_SHIFT 5 /* LI2SPK */
1035#define WM8400_LI2SPK_WIDTH 1 /* LI2SPK */
1036#define WM8400_RI2SPK 0x0010 /* RI2SPK */
1037#define WM8400_RI2SPK_MASK 0x0010 /* RI2SPK */
1038#define WM8400_RI2SPK_SHIFT 4 /* RI2SPK */
1039#define WM8400_RI2SPK_WIDTH 1 /* RI2SPK */
1040#define WM8400_LOPGASPK 0x0008 /* LOPGASPK */
1041#define WM8400_LOPGASPK_MASK 0x0008 /* LOPGASPK */
1042#define WM8400_LOPGASPK_SHIFT 3 /* LOPGASPK */
1043#define WM8400_LOPGASPK_WIDTH 1 /* LOPGASPK */
1044#define WM8400_ROPGASPK 0x0004 /* ROPGASPK */
1045#define WM8400_ROPGASPK_MASK 0x0004 /* ROPGASPK */
1046#define WM8400_ROPGASPK_SHIFT 2 /* ROPGASPK */
1047#define WM8400_ROPGASPK_WIDTH 1 /* ROPGASPK */
1048#define WM8400_LDSPK 0x0002 /* LDSPK */
1049#define WM8400_LDSPK_MASK 0x0002 /* LDSPK */
1050#define WM8400_LDSPK_SHIFT 1 /* LDSPK */
1051#define WM8400_LDSPK_WIDTH 1 /* LDSPK */
1052#define WM8400_RDSPK 0x0001 /* RDSPK */
1053#define WM8400_RDSPK_MASK 0x0001 /* RDSPK */
1054#define WM8400_RDSPK_SHIFT 0 /* RDSPK */
1055#define WM8400_RDSPK_WIDTH 1 /* RDSPK */
1056
1057/*
1058 * R55 (0x37) - Additional Control
1059 */
1060#define WM8400_VROI 0x0001 /* VROI */
1061#define WM8400_VROI_MASK 0x0001 /* VROI */
1062#define WM8400_VROI_SHIFT 0 /* VROI */
1063#define WM8400_VROI_WIDTH 1 /* VROI */
1064
1065/*
1066 * R56 (0x38) - AntiPOP1
1067 */
1068#define WM8400_DIS_LLINE 0x0020 /* DIS_LLINE */
1069#define WM8400_DIS_LLINE_MASK 0x0020 /* DIS_LLINE */
1070#define WM8400_DIS_LLINE_SHIFT 5 /* DIS_LLINE */
1071#define WM8400_DIS_LLINE_WIDTH 1 /* DIS_LLINE */
1072#define WM8400_DIS_RLINE 0x0010 /* DIS_RLINE */
1073#define WM8400_DIS_RLINE_MASK 0x0010 /* DIS_RLINE */
1074#define WM8400_DIS_RLINE_SHIFT 4 /* DIS_RLINE */
1075#define WM8400_DIS_RLINE_WIDTH 1 /* DIS_RLINE */
1076#define WM8400_DIS_OUT3 0x0008 /* DIS_OUT3 */
1077#define WM8400_DIS_OUT3_MASK 0x0008 /* DIS_OUT3 */
1078#define WM8400_DIS_OUT3_SHIFT 3 /* DIS_OUT3 */
1079#define WM8400_DIS_OUT3_WIDTH 1 /* DIS_OUT3 */
1080#define WM8400_DIS_OUT4 0x0004 /* DIS_OUT4 */
1081#define WM8400_DIS_OUT4_MASK 0x0004 /* DIS_OUT4 */
1082#define WM8400_DIS_OUT4_SHIFT 2 /* DIS_OUT4 */
1083#define WM8400_DIS_OUT4_WIDTH 1 /* DIS_OUT4 */
1084#define WM8400_DIS_LOUT 0x0002 /* DIS_LOUT */
1085#define WM8400_DIS_LOUT_MASK 0x0002 /* DIS_LOUT */
1086#define WM8400_DIS_LOUT_SHIFT 1 /* DIS_LOUT */
1087#define WM8400_DIS_LOUT_WIDTH 1 /* DIS_LOUT */
1088#define WM8400_DIS_ROUT 0x0001 /* DIS_ROUT */
1089#define WM8400_DIS_ROUT_MASK 0x0001 /* DIS_ROUT */
1090#define WM8400_DIS_ROUT_SHIFT 0 /* DIS_ROUT */
1091#define WM8400_DIS_ROUT_WIDTH 1 /* DIS_ROUT */
1092
1093/*
1094 * R57 (0x39) - AntiPOP2
1095 */
1096#define WM8400_SOFTST 0x0040 /* SOFTST */
1097#define WM8400_SOFTST_MASK 0x0040 /* SOFTST */
1098#define WM8400_SOFTST_SHIFT 6 /* SOFTST */
1099#define WM8400_SOFTST_WIDTH 1 /* SOFTST */
1100#define WM8400_BUFIOEN 0x0008 /* BUFIOEN */
1101#define WM8400_BUFIOEN_MASK 0x0008 /* BUFIOEN */
1102#define WM8400_BUFIOEN_SHIFT 3 /* BUFIOEN */
1103#define WM8400_BUFIOEN_WIDTH 1 /* BUFIOEN */
1104#define WM8400_BUFDCOPEN 0x0004 /* BUFDCOPEN */
1105#define WM8400_BUFDCOPEN_MASK 0x0004 /* BUFDCOPEN */
1106#define WM8400_BUFDCOPEN_SHIFT 2 /* BUFDCOPEN */
1107#define WM8400_BUFDCOPEN_WIDTH 1 /* BUFDCOPEN */
1108#define WM8400_POBCTRL 0x0002 /* POBCTRL */
1109#define WM8400_POBCTRL_MASK 0x0002 /* POBCTRL */
1110#define WM8400_POBCTRL_SHIFT 1 /* POBCTRL */
1111#define WM8400_POBCTRL_WIDTH 1 /* POBCTRL */
1112#define WM8400_VMIDTOG 0x0001 /* VMIDTOG */
1113#define WM8400_VMIDTOG_MASK 0x0001 /* VMIDTOG */
1114#define WM8400_VMIDTOG_SHIFT 0 /* VMIDTOG */
1115#define WM8400_VMIDTOG_WIDTH 1 /* VMIDTOG */
1116
1117/*
1118 * R58 (0x3A) - MICBIAS
1119 */
1120#define WM8400_MCDSCTH_MASK 0x00C0 /* MCDSCTH - [7:6] */
1121#define WM8400_MCDSCTH_SHIFT 6 /* MCDSCTH - [7:6] */
1122#define WM8400_MCDSCTH_WIDTH 2 /* MCDSCTH - [7:6] */
1123#define WM8400_MCDTHR_MASK 0x0038 /* MCDTHR - [5:3] */
1124#define WM8400_MCDTHR_SHIFT 3 /* MCDTHR - [5:3] */
1125#define WM8400_MCDTHR_WIDTH 3 /* MCDTHR - [5:3] */
1126#define WM8400_MCD 0x0004 /* MCD */
1127#define WM8400_MCD_MASK 0x0004 /* MCD */
1128#define WM8400_MCD_SHIFT 2 /* MCD */
1129#define WM8400_MCD_WIDTH 1 /* MCD */
1130#define WM8400_MBSEL 0x0001 /* MBSEL */
1131#define WM8400_MBSEL_MASK 0x0001 /* MBSEL */
1132#define WM8400_MBSEL_SHIFT 0 /* MBSEL */
1133#define WM8400_MBSEL_WIDTH 1 /* MBSEL */
1134
1135/*
1136 * R60 (0x3C) - FLL Control 1
1137 */
1138#define WM8400_FLL_REF_FREQ 0x1000 /* FLL_REF_FREQ */
1139#define WM8400_FLL_REF_FREQ_MASK 0x1000 /* FLL_REF_FREQ */
1140#define WM8400_FLL_REF_FREQ_SHIFT 12 /* FLL_REF_FREQ */
1141#define WM8400_FLL_REF_FREQ_WIDTH 1 /* FLL_REF_FREQ */
1142#define WM8400_FLL_CLK_SRC_MASK 0x0C00 /* FLL_CLK_SRC - [11:10] */
1143#define WM8400_FLL_CLK_SRC_SHIFT 10 /* FLL_CLK_SRC - [11:10] */
1144#define WM8400_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [11:10] */
1145#define WM8400_FLL_FRAC 0x0200 /* FLL_FRAC */
1146#define WM8400_FLL_FRAC_MASK 0x0200 /* FLL_FRAC */
1147#define WM8400_FLL_FRAC_SHIFT 9 /* FLL_FRAC */
1148#define WM8400_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
1149#define WM8400_FLL_OSC_ENA 0x0100 /* FLL_OSC_ENA */
1150#define WM8400_FLL_OSC_ENA_MASK 0x0100 /* FLL_OSC_ENA */
1151#define WM8400_FLL_OSC_ENA_SHIFT 8 /* FLL_OSC_ENA */
1152#define WM8400_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */
1153#define WM8400_FLL_CTRL_RATE_MASK 0x00E0 /* FLL_CTRL_RATE - [7:5] */
1154#define WM8400_FLL_CTRL_RATE_SHIFT 5 /* FLL_CTRL_RATE - [7:5] */
1155#define WM8400_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [7:5] */
1156#define WM8400_FLL_FRATIO_MASK 0x001F /* FLL_FRATIO - [4:0] */
1157#define WM8400_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [4:0] */
1158#define WM8400_FLL_FRATIO_WIDTH 5 /* FLL_FRATIO - [4:0] */
1159
1160/*
1161 * R61 (0x3D) - FLL Control 2
1162 */
1163#define WM8400_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
1164#define WM8400_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
1165#define WM8400_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
1166
1167/*
1168 * R62 (0x3E) - FLL Control 3
1169 */
1170#define WM8400_FLL_N_MASK 0x03FF /* FLL_N - [9:0] */
1171#define WM8400_FLL_N_SHIFT 0 /* FLL_N - [9:0] */
1172#define WM8400_FLL_N_WIDTH 10 /* FLL_N - [9:0] */
1173
1174/*
1175 * R63 (0x3F) - FLL Control 4
1176 */
1177#define WM8400_FLL_TRK_GAIN_MASK 0x0078 /* FLL_TRK_GAIN - [6:3] */
1178#define WM8400_FLL_TRK_GAIN_SHIFT 3 /* FLL_TRK_GAIN - [6:3] */
1179#define WM8400_FLL_TRK_GAIN_WIDTH 4 /* FLL_TRK_GAIN - [6:3] */
1180#define WM8400_FLL_OUTDIV_MASK 0x0007 /* FLL_OUTDIV - [2:0] */
1181#define WM8400_FLL_OUTDIV_SHIFT 0 /* FLL_OUTDIV - [2:0] */
1182#define WM8400_FLL_OUTDIV_WIDTH 3 /* FLL_OUTDIV - [2:0] */
1183
1184void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400);
1185
1186#endif
diff --git a/include/linux/mfd/wm8400-private.h b/include/linux/mfd/wm8400-private.h
new file mode 100644
index 000000000000..49042e990f05
--- /dev/null
+++ b/include/linux/mfd/wm8400-private.h
@@ -0,0 +1,935 @@
1/*
2 * wm8400 private definitions.
3 *
4 * Copyright 2008 Wolfson Microelectronics plc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#ifndef __LINUX_MFD_WM8400_PRIV_H
22#define __LINUX_MFD_WM8400_PRIV_H
23
24#include <linux/mutex.h>
25#include <linux/platform_device.h>
26
27#define WM8400_REGISTER_COUNT 0x55
28
29struct wm8400 {
30 struct device *dev;
31
32 int (*read_dev)(void *data, char reg, int count, u16 *dst);
33 int (*write_dev)(void *data, char reg, int count, const u16 *src);
34
35 struct mutex io_lock;
36 void *io_data;
37
38 u16 reg_cache[WM8400_REGISTER_COUNT];
39
40 struct platform_device regulators[6];
41};
42
43/*
44 * Register values.
45 */
46#define WM8400_RESET_ID 0x00
47#define WM8400_ID 0x01
48#define WM8400_POWER_MANAGEMENT_1 0x02
49#define WM8400_POWER_MANAGEMENT_2 0x03
50#define WM8400_POWER_MANAGEMENT_3 0x04
51#define WM8400_AUDIO_INTERFACE_1 0x05
52#define WM8400_AUDIO_INTERFACE_2 0x06
53#define WM8400_CLOCKING_1 0x07
54#define WM8400_CLOCKING_2 0x08
55#define WM8400_AUDIO_INTERFACE_3 0x09
56#define WM8400_AUDIO_INTERFACE_4 0x0A
57#define WM8400_DAC_CTRL 0x0B
58#define WM8400_LEFT_DAC_DIGITAL_VOLUME 0x0C
59#define WM8400_RIGHT_DAC_DIGITAL_VOLUME 0x0D
60#define WM8400_DIGITAL_SIDE_TONE 0x0E
61#define WM8400_ADC_CTRL 0x0F
62#define WM8400_LEFT_ADC_DIGITAL_VOLUME 0x10
63#define WM8400_RIGHT_ADC_DIGITAL_VOLUME 0x11
64#define WM8400_GPIO_CTRL_1 0x12
65#define WM8400_GPIO1_GPIO2 0x13
66#define WM8400_GPIO3_GPIO4 0x14
67#define WM8400_GPIO5_GPIO6 0x15
68#define WM8400_GPIOCTRL_2 0x16
69#define WM8400_GPIO_POL 0x17
70#define WM8400_LEFT_LINE_INPUT_1_2_VOLUME 0x18
71#define WM8400_LEFT_LINE_INPUT_3_4_VOLUME 0x19
72#define WM8400_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A
73#define WM8400_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B
74#define WM8400_LEFT_OUTPUT_VOLUME 0x1C
75#define WM8400_RIGHT_OUTPUT_VOLUME 0x1D
76#define WM8400_LINE_OUTPUTS_VOLUME 0x1E
77#define WM8400_OUT3_4_VOLUME 0x1F
78#define WM8400_LEFT_OPGA_VOLUME 0x20
79#define WM8400_RIGHT_OPGA_VOLUME 0x21
80#define WM8400_SPEAKER_VOLUME 0x22
81#define WM8400_CLASSD1 0x23
82#define WM8400_CLASSD3 0x25
83#define WM8400_INPUT_MIXER1 0x27
84#define WM8400_INPUT_MIXER2 0x28
85#define WM8400_INPUT_MIXER3 0x29
86#define WM8400_INPUT_MIXER4 0x2A
87#define WM8400_INPUT_MIXER5 0x2B
88#define WM8400_INPUT_MIXER6 0x2C
89#define WM8400_OUTPUT_MIXER1 0x2D
90#define WM8400_OUTPUT_MIXER2 0x2E
91#define WM8400_OUTPUT_MIXER3 0x2F
92#define WM8400_OUTPUT_MIXER4 0x30
93#define WM8400_OUTPUT_MIXER5 0x31
94#define WM8400_OUTPUT_MIXER6 0x32
95#define WM8400_OUT3_4_MIXER 0x33
96#define WM8400_LINE_MIXER1 0x34
97#define WM8400_LINE_MIXER2 0x35
98#define WM8400_SPEAKER_MIXER 0x36
99#define WM8400_ADDITIONAL_CONTROL 0x37
100#define WM8400_ANTIPOP1 0x38
101#define WM8400_ANTIPOP2 0x39
102#define WM8400_MICBIAS 0x3A
103#define WM8400_FLL_CONTROL_1 0x3C
104#define WM8400_FLL_CONTROL_2 0x3D
105#define WM8400_FLL_CONTROL_3 0x3E
106#define WM8400_FLL_CONTROL_4 0x3F
107#define WM8400_LDO1_CONTROL 0x41
108#define WM8400_LDO2_CONTROL 0x42
109#define WM8400_LDO3_CONTROL 0x43
110#define WM8400_LDO4_CONTROL 0x44
111#define WM8400_DCDC1_CONTROL_1 0x46
112#define WM8400_DCDC1_CONTROL_2 0x47
113#define WM8400_DCDC2_CONTROL_1 0x48
114#define WM8400_DCDC2_CONTROL_2 0x49
115#define WM8400_INTERFACE 0x4B
116#define WM8400_PM_GENERAL 0x4C
117#define WM8400_PM_SHUTDOWN_CONTROL 0x4E
118#define WM8400_INTERRUPT_STATUS_1 0x4F
119#define WM8400_INTERRUPT_STATUS_1_MASK 0x50
120#define WM8400_INTERRUPT_LEVELS 0x51
121#define WM8400_SHUTDOWN_REASON 0x52
122#define WM8400_LINE_CIRCUITS 0x54
123
124/*
125 * Field Definitions.
126 */
127
128/*
129 * R0 (0x00) - Reset/ID
130 */
131#define WM8400_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET/CHIP_ID - [15:0] */
132#define WM8400_SW_RESET_CHIP_ID_SHIFT 0 /* SW_RESET/CHIP_ID - [15:0] */
133#define WM8400_SW_RESET_CHIP_ID_WIDTH 16 /* SW_RESET/CHIP_ID - [15:0] */
134
135/*
136 * R1 (0x01) - ID
137 */
138#define WM8400_CHIP_REV_MASK 0x7000 /* CHIP_REV - [14:12] */
139#define WM8400_CHIP_REV_SHIFT 12 /* CHIP_REV - [14:12] */
140#define WM8400_CHIP_REV_WIDTH 3 /* CHIP_REV - [14:12] */
141
142/*
143 * R18 (0x12) - GPIO CTRL 1
144 */
145#define WM8400_IRQ 0x1000 /* IRQ */
146#define WM8400_IRQ_MASK 0x1000 /* IRQ */
147#define WM8400_IRQ_SHIFT 12 /* IRQ */
148#define WM8400_IRQ_WIDTH 1 /* IRQ */
149#define WM8400_TEMPOK 0x0800 /* TEMPOK */
150#define WM8400_TEMPOK_MASK 0x0800 /* TEMPOK */
151#define WM8400_TEMPOK_SHIFT 11 /* TEMPOK */
152#define WM8400_TEMPOK_WIDTH 1 /* TEMPOK */
153#define WM8400_MIC1SHRT 0x0400 /* MIC1SHRT */
154#define WM8400_MIC1SHRT_MASK 0x0400 /* MIC1SHRT */
155#define WM8400_MIC1SHRT_SHIFT 10 /* MIC1SHRT */
156#define WM8400_MIC1SHRT_WIDTH 1 /* MIC1SHRT */
157#define WM8400_MIC1DET 0x0200 /* MIC1DET */
158#define WM8400_MIC1DET_MASK 0x0200 /* MIC1DET */
159#define WM8400_MIC1DET_SHIFT 9 /* MIC1DET */
160#define WM8400_MIC1DET_WIDTH 1 /* MIC1DET */
161#define WM8400_FLL_LCK 0x0100 /* FLL_LCK */
162#define WM8400_FLL_LCK_MASK 0x0100 /* FLL_LCK */
163#define WM8400_FLL_LCK_SHIFT 8 /* FLL_LCK */
164#define WM8400_FLL_LCK_WIDTH 1 /* FLL_LCK */
165#define WM8400_GPIO_STATUS_MASK 0x00FF /* GPIO_STATUS - [7:0] */
166#define WM8400_GPIO_STATUS_SHIFT 0 /* GPIO_STATUS - [7:0] */
167#define WM8400_GPIO_STATUS_WIDTH 8 /* GPIO_STATUS - [7:0] */
168
169/*
170 * R19 (0x13) - GPIO1 & GPIO2
171 */
172#define WM8400_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */
173#define WM8400_GPIO2_DEB_ENA_MASK 0x8000 /* GPIO2_DEB_ENA */
174#define WM8400_GPIO2_DEB_ENA_SHIFT 15 /* GPIO2_DEB_ENA */
175#define WM8400_GPIO2_DEB_ENA_WIDTH 1 /* GPIO2_DEB_ENA */
176#define WM8400_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */
177#define WM8400_GPIO2_IRQ_ENA_MASK 0x4000 /* GPIO2_IRQ_ENA */
178#define WM8400_GPIO2_IRQ_ENA_SHIFT 14 /* GPIO2_IRQ_ENA */
179#define WM8400_GPIO2_IRQ_ENA_WIDTH 1 /* GPIO2_IRQ_ENA */
180#define WM8400_GPIO2_PU 0x2000 /* GPIO2_PU */
181#define WM8400_GPIO2_PU_MASK 0x2000 /* GPIO2_PU */
182#define WM8400_GPIO2_PU_SHIFT 13 /* GPIO2_PU */
183#define WM8400_GPIO2_PU_WIDTH 1 /* GPIO2_PU */
184#define WM8400_GPIO2_PD 0x1000 /* GPIO2_PD */
185#define WM8400_GPIO2_PD_MASK 0x1000 /* GPIO2_PD */
186#define WM8400_GPIO2_PD_SHIFT 12 /* GPIO2_PD */
187#define WM8400_GPIO2_PD_WIDTH 1 /* GPIO2_PD */
188#define WM8400_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */
189#define WM8400_GPIO2_SEL_SHIFT 8 /* GPIO2_SEL - [11:8] */
190#define WM8400_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [11:8] */
191#define WM8400_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */
192#define WM8400_GPIO1_DEB_ENA_MASK 0x0080 /* GPIO1_DEB_ENA */
193#define WM8400_GPIO1_DEB_ENA_SHIFT 7 /* GPIO1_DEB_ENA */
194#define WM8400_GPIO1_DEB_ENA_WIDTH 1 /* GPIO1_DEB_ENA */
195#define WM8400_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */
196#define WM8400_GPIO1_IRQ_ENA_MASK 0x0040 /* GPIO1_IRQ_ENA */
197#define WM8400_GPIO1_IRQ_ENA_SHIFT 6 /* GPIO1_IRQ_ENA */
198#define WM8400_GPIO1_IRQ_ENA_WIDTH 1 /* GPIO1_IRQ_ENA */
199#define WM8400_GPIO1_PU 0x0020 /* GPIO1_PU */
200#define WM8400_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */
201#define WM8400_GPIO1_PU_SHIFT 5 /* GPIO1_PU */
202#define WM8400_GPIO1_PU_WIDTH 1 /* GPIO1_PU */
203#define WM8400_GPIO1_PD 0x0010 /* GPIO1_PD */
204#define WM8400_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */
205#define WM8400_GPIO1_PD_SHIFT 4 /* GPIO1_PD */
206#define WM8400_GPIO1_PD_WIDTH 1 /* GPIO1_PD */
207#define WM8400_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
208#define WM8400_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */
209#define WM8400_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */
210
211/*
212 * R20 (0x14) - GPIO3 & GPIO4
213 */
214#define WM8400_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */
215#define WM8400_GPIO4_DEB_ENA_MASK 0x8000 /* GPIO4_DEB_ENA */
216#define WM8400_GPIO4_DEB_ENA_SHIFT 15 /* GPIO4_DEB_ENA */
217#define WM8400_GPIO4_DEB_ENA_WIDTH 1 /* GPIO4_DEB_ENA */
218#define WM8400_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */
219#define WM8400_GPIO4_IRQ_ENA_MASK 0x4000 /* GPIO4_IRQ_ENA */
220#define WM8400_GPIO4_IRQ_ENA_SHIFT 14 /* GPIO4_IRQ_ENA */
221#define WM8400_GPIO4_IRQ_ENA_WIDTH 1 /* GPIO4_IRQ_ENA */
222#define WM8400_GPIO4_PU 0x2000 /* GPIO4_PU */
223#define WM8400_GPIO4_PU_MASK 0x2000 /* GPIO4_PU */
224#define WM8400_GPIO4_PU_SHIFT 13 /* GPIO4_PU */
225#define WM8400_GPIO4_PU_WIDTH 1 /* GPIO4_PU */
226#define WM8400_GPIO4_PD 0x1000 /* GPIO4_PD */
227#define WM8400_GPIO4_PD_MASK 0x1000 /* GPIO4_PD */
228#define WM8400_GPIO4_PD_SHIFT 12 /* GPIO4_PD */
229#define WM8400_GPIO4_PD_WIDTH 1 /* GPIO4_PD */
230#define WM8400_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */
231#define WM8400_GPIO4_SEL_SHIFT 8 /* GPIO4_SEL - [11:8] */
232#define WM8400_GPIO4_SEL_WIDTH 4 /* GPIO4_SEL - [11:8] */
233#define WM8400_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */
234#define WM8400_GPIO3_DEB_ENA_MASK 0x0080 /* GPIO3_DEB_ENA */
235#define WM8400_GPIO3_DEB_ENA_SHIFT 7 /* GPIO3_DEB_ENA */
236#define WM8400_GPIO3_DEB_ENA_WIDTH 1 /* GPIO3_DEB_ENA */
237#define WM8400_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */
238#define WM8400_GPIO3_IRQ_ENA_MASK 0x0040 /* GPIO3_IRQ_ENA */
239#define WM8400_GPIO3_IRQ_ENA_SHIFT 6 /* GPIO3_IRQ_ENA */
240#define WM8400_GPIO3_IRQ_ENA_WIDTH 1 /* GPIO3_IRQ_ENA */
241#define WM8400_GPIO3_PU 0x0020 /* GPIO3_PU */
242#define WM8400_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */
243#define WM8400_GPIO3_PU_SHIFT 5 /* GPIO3_PU */
244#define WM8400_GPIO3_PU_WIDTH 1 /* GPIO3_PU */
245#define WM8400_GPIO3_PD 0x0010 /* GPIO3_PD */
246#define WM8400_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */
247#define WM8400_GPIO3_PD_SHIFT 4 /* GPIO3_PD */
248#define WM8400_GPIO3_PD_WIDTH 1 /* GPIO3_PD */
249#define WM8400_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
250#define WM8400_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */
251#define WM8400_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */
252
253/*
254 * R21 (0x15) - GPIO5 & GPIO6
255 */
256#define WM8400_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */
257#define WM8400_GPIO6_DEB_ENA_MASK 0x8000 /* GPIO6_DEB_ENA */
258#define WM8400_GPIO6_DEB_ENA_SHIFT 15 /* GPIO6_DEB_ENA */
259#define WM8400_GPIO6_DEB_ENA_WIDTH 1 /* GPIO6_DEB_ENA */
260#define WM8400_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */
261#define WM8400_GPIO6_IRQ_ENA_MASK 0x4000 /* GPIO6_IRQ_ENA */
262#define WM8400_GPIO6_IRQ_ENA_SHIFT 14 /* GPIO6_IRQ_ENA */
263#define WM8400_GPIO6_IRQ_ENA_WIDTH 1 /* GPIO6_IRQ_ENA */
264#define WM8400_GPIO6_PU 0x2000 /* GPIO6_PU */
265#define WM8400_GPIO6_PU_MASK 0x2000 /* GPIO6_PU */
266#define WM8400_GPIO6_PU_SHIFT 13 /* GPIO6_PU */
267#define WM8400_GPIO6_PU_WIDTH 1 /* GPIO6_PU */
268#define WM8400_GPIO6_PD 0x1000 /* GPIO6_PD */
269#define WM8400_GPIO6_PD_MASK 0x1000 /* GPIO6_PD */
270#define WM8400_GPIO6_PD_SHIFT 12 /* GPIO6_PD */
271#define WM8400_GPIO6_PD_WIDTH 1 /* GPIO6_PD */
272#define WM8400_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */
273#define WM8400_GPIO6_SEL_SHIFT 8 /* GPIO6_SEL - [11:8] */
274#define WM8400_GPIO6_SEL_WIDTH 4 /* GPIO6_SEL - [11:8] */
275#define WM8400_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */
276#define WM8400_GPIO5_DEB_ENA_MASK 0x0080 /* GPIO5_DEB_ENA */
277#define WM8400_GPIO5_DEB_ENA_SHIFT 7 /* GPIO5_DEB_ENA */
278#define WM8400_GPIO5_DEB_ENA_WIDTH 1 /* GPIO5_DEB_ENA */
279#define WM8400_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */
280#define WM8400_GPIO5_IRQ_ENA_MASK 0x0040 /* GPIO5_IRQ_ENA */
281#define WM8400_GPIO5_IRQ_ENA_SHIFT 6 /* GPIO5_IRQ_ENA */
282#define WM8400_GPIO5_IRQ_ENA_WIDTH 1 /* GPIO5_IRQ_ENA */
283#define WM8400_GPIO5_PU 0x0020 /* GPIO5_PU */
284#define WM8400_GPIO5_PU_MASK 0x0020 /* GPIO5_PU */
285#define WM8400_GPIO5_PU_SHIFT 5 /* GPIO5_PU */
286#define WM8400_GPIO5_PU_WIDTH 1 /* GPIO5_PU */
287#define WM8400_GPIO5_PD 0x0010 /* GPIO5_PD */
288#define WM8400_GPIO5_PD_MASK 0x0010 /* GPIO5_PD */
289#define WM8400_GPIO5_PD_SHIFT 4 /* GPIO5_PD */
290#define WM8400_GPIO5_PD_WIDTH 1 /* GPIO5_PD */
291#define WM8400_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */
292#define WM8400_GPIO5_SEL_SHIFT 0 /* GPIO5_SEL - [3:0] */
293#define WM8400_GPIO5_SEL_WIDTH 4 /* GPIO5_SEL - [3:0] */
294
295/*
296 * R22 (0x16) - GPIOCTRL 2
297 */
298#define WM8400_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */
299#define WM8400_TEMPOK_IRQ_ENA_MASK 0x0800 /* TEMPOK_IRQ_ENA */
300#define WM8400_TEMPOK_IRQ_ENA_SHIFT 11 /* TEMPOK_IRQ_ENA */
301#define WM8400_TEMPOK_IRQ_ENA_WIDTH 1 /* TEMPOK_IRQ_ENA */
302#define WM8400_MIC1SHRT_IRQ_ENA 0x0400 /* MIC1SHRT_IRQ_ENA */
303#define WM8400_MIC1SHRT_IRQ_ENA_MASK 0x0400 /* MIC1SHRT_IRQ_ENA */
304#define WM8400_MIC1SHRT_IRQ_ENA_SHIFT 10 /* MIC1SHRT_IRQ_ENA */
305#define WM8400_MIC1SHRT_IRQ_ENA_WIDTH 1 /* MIC1SHRT_IRQ_ENA */
306#define WM8400_MIC1DET_IRQ_ENA 0x0200 /* MIC1DET_IRQ_ENA */
307#define WM8400_MIC1DET_IRQ_ENA_MASK 0x0200 /* MIC1DET_IRQ_ENA */
308#define WM8400_MIC1DET_IRQ_ENA_SHIFT 9 /* MIC1DET_IRQ_ENA */
309#define WM8400_MIC1DET_IRQ_ENA_WIDTH 1 /* MIC1DET_IRQ_ENA */
310#define WM8400_FLL_LCK_IRQ_ENA 0x0100 /* FLL_LCK_IRQ_ENA */
311#define WM8400_FLL_LCK_IRQ_ENA_MASK 0x0100 /* FLL_LCK_IRQ_ENA */
312#define WM8400_FLL_LCK_IRQ_ENA_SHIFT 8 /* FLL_LCK_IRQ_ENA */
313#define WM8400_FLL_LCK_IRQ_ENA_WIDTH 1 /* FLL_LCK_IRQ_ENA */
314#define WM8400_GPI8_DEB_ENA 0x0080 /* GPI8_DEB_ENA */
315#define WM8400_GPI8_DEB_ENA_MASK 0x0080 /* GPI8_DEB_ENA */
316#define WM8400_GPI8_DEB_ENA_SHIFT 7 /* GPI8_DEB_ENA */
317#define WM8400_GPI8_DEB_ENA_WIDTH 1 /* GPI8_DEB_ENA */
318#define WM8400_GPI8_IRQ_ENA 0x0040 /* GPI8_IRQ_ENA */
319#define WM8400_GPI8_IRQ_ENA_MASK 0x0040 /* GPI8_IRQ_ENA */
320#define WM8400_GPI8_IRQ_ENA_SHIFT 6 /* GPI8_IRQ_ENA */
321#define WM8400_GPI8_IRQ_ENA_WIDTH 1 /* GPI8_IRQ_ENA */
322#define WM8400_GPI8_ENA 0x0010 /* GPI8_ENA */
323#define WM8400_GPI8_ENA_MASK 0x0010 /* GPI8_ENA */
324#define WM8400_GPI8_ENA_SHIFT 4 /* GPI8_ENA */
325#define WM8400_GPI8_ENA_WIDTH 1 /* GPI8_ENA */
326#define WM8400_GPI7_DEB_ENA 0x0008 /* GPI7_DEB_ENA */
327#define WM8400_GPI7_DEB_ENA_MASK 0x0008 /* GPI7_DEB_ENA */
328#define WM8400_GPI7_DEB_ENA_SHIFT 3 /* GPI7_DEB_ENA */
329#define WM8400_GPI7_DEB_ENA_WIDTH 1 /* GPI7_DEB_ENA */
330#define WM8400_GPI7_IRQ_ENA 0x0004 /* GPI7_IRQ_ENA */
331#define WM8400_GPI7_IRQ_ENA_MASK 0x0004 /* GPI7_IRQ_ENA */
332#define WM8400_GPI7_IRQ_ENA_SHIFT 2 /* GPI7_IRQ_ENA */
333#define WM8400_GPI7_IRQ_ENA_WIDTH 1 /* GPI7_IRQ_ENA */
334#define WM8400_GPI7_ENA 0x0001 /* GPI7_ENA */
335#define WM8400_GPI7_ENA_MASK 0x0001 /* GPI7_ENA */
336#define WM8400_GPI7_ENA_SHIFT 0 /* GPI7_ENA */
337#define WM8400_GPI7_ENA_WIDTH 1 /* GPI7_ENA */
338
339/*
340 * R23 (0x17) - GPIO_POL
341 */
342#define WM8400_IRQ_INV 0x1000 /* IRQ_INV */
343#define WM8400_IRQ_INV_MASK 0x1000 /* IRQ_INV */
344#define WM8400_IRQ_INV_SHIFT 12 /* IRQ_INV */
345#define WM8400_IRQ_INV_WIDTH 1 /* IRQ_INV */
346#define WM8400_TEMPOK_POL 0x0800 /* TEMPOK_POL */
347#define WM8400_TEMPOK_POL_MASK 0x0800 /* TEMPOK_POL */
348#define WM8400_TEMPOK_POL_SHIFT 11 /* TEMPOK_POL */
349#define WM8400_TEMPOK_POL_WIDTH 1 /* TEMPOK_POL */
350#define WM8400_MIC1SHRT_POL 0x0400 /* MIC1SHRT_POL */
351#define WM8400_MIC1SHRT_POL_MASK 0x0400 /* MIC1SHRT_POL */
352#define WM8400_MIC1SHRT_POL_SHIFT 10 /* MIC1SHRT_POL */
353#define WM8400_MIC1SHRT_POL_WIDTH 1 /* MIC1SHRT_POL */
354#define WM8400_MIC1DET_POL 0x0200 /* MIC1DET_POL */
355#define WM8400_MIC1DET_POL_MASK 0x0200 /* MIC1DET_POL */
356#define WM8400_MIC1DET_POL_SHIFT 9 /* MIC1DET_POL */
357#define WM8400_MIC1DET_POL_WIDTH 1 /* MIC1DET_POL */
358#define WM8400_FLL_LCK_POL 0x0100 /* FLL_LCK_POL */
359#define WM8400_FLL_LCK_POL_MASK 0x0100 /* FLL_LCK_POL */
360#define WM8400_FLL_LCK_POL_SHIFT 8 /* FLL_LCK_POL */
361#define WM8400_FLL_LCK_POL_WIDTH 1 /* FLL_LCK_POL */
362#define WM8400_GPIO_POL_MASK 0x00FF /* GPIO_POL - [7:0] */
363#define WM8400_GPIO_POL_SHIFT 0 /* GPIO_POL - [7:0] */
364#define WM8400_GPIO_POL_WIDTH 8 /* GPIO_POL - [7:0] */
365
366/*
367 * R65 (0x41) - LDO 1 Control
368 */
369#define WM8400_LDO1_ENA 0x8000 /* LDO1_ENA */
370#define WM8400_LDO1_ENA_MASK 0x8000 /* LDO1_ENA */
371#define WM8400_LDO1_ENA_SHIFT 15 /* LDO1_ENA */
372#define WM8400_LDO1_ENA_WIDTH 1 /* LDO1_ENA */
373#define WM8400_LDO1_SWI 0x4000 /* LDO1_SWI */
374#define WM8400_LDO1_SWI_MASK 0x4000 /* LDO1_SWI */
375#define WM8400_LDO1_SWI_SHIFT 14 /* LDO1_SWI */
376#define WM8400_LDO1_SWI_WIDTH 1 /* LDO1_SWI */
377#define WM8400_LDO1_OPFLT 0x1000 /* LDO1_OPFLT */
378#define WM8400_LDO1_OPFLT_MASK 0x1000 /* LDO1_OPFLT */
379#define WM8400_LDO1_OPFLT_SHIFT 12 /* LDO1_OPFLT */
380#define WM8400_LDO1_OPFLT_WIDTH 1 /* LDO1_OPFLT */
381#define WM8400_LDO1_ERRACT 0x0800 /* LDO1_ERRACT */
382#define WM8400_LDO1_ERRACT_MASK 0x0800 /* LDO1_ERRACT */
383#define WM8400_LDO1_ERRACT_SHIFT 11 /* LDO1_ERRACT */
384#define WM8400_LDO1_ERRACT_WIDTH 1 /* LDO1_ERRACT */
385#define WM8400_LDO1_HIB_MODE 0x0400 /* LDO1_HIB_MODE */
386#define WM8400_LDO1_HIB_MODE_MASK 0x0400 /* LDO1_HIB_MODE */
387#define WM8400_LDO1_HIB_MODE_SHIFT 10 /* LDO1_HIB_MODE */
388#define WM8400_LDO1_HIB_MODE_WIDTH 1 /* LDO1_HIB_MODE */
389#define WM8400_LDO1_VIMG_MASK 0x03E0 /* LDO1_VIMG - [9:5] */
390#define WM8400_LDO1_VIMG_SHIFT 5 /* LDO1_VIMG - [9:5] */
391#define WM8400_LDO1_VIMG_WIDTH 5 /* LDO1_VIMG - [9:5] */
392#define WM8400_LDO1_VSEL_MASK 0x001F /* LDO1_VSEL - [4:0] */
393#define WM8400_LDO1_VSEL_SHIFT 0 /* LDO1_VSEL - [4:0] */
394#define WM8400_LDO1_VSEL_WIDTH 5 /* LDO1_VSEL - [4:0] */
395
396/*
397 * R66 (0x42) - LDO 2 Control
398 */
399#define WM8400_LDO2_ENA 0x8000 /* LDO2_ENA */
400#define WM8400_LDO2_ENA_MASK 0x8000 /* LDO2_ENA */
401#define WM8400_LDO2_ENA_SHIFT 15 /* LDO2_ENA */
402#define WM8400_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
403#define WM8400_LDO2_SWI 0x4000 /* LDO2_SWI */
404#define WM8400_LDO2_SWI_MASK 0x4000 /* LDO2_SWI */
405#define WM8400_LDO2_SWI_SHIFT 14 /* LDO2_SWI */
406#define WM8400_LDO2_SWI_WIDTH 1 /* LDO2_SWI */
407#define WM8400_LDO2_OPFLT 0x1000 /* LDO2_OPFLT */
408#define WM8400_LDO2_OPFLT_MASK 0x1000 /* LDO2_OPFLT */
409#define WM8400_LDO2_OPFLT_SHIFT 12 /* LDO2_OPFLT */
410#define WM8400_LDO2_OPFLT_WIDTH 1 /* LDO2_OPFLT */
411#define WM8400_LDO2_ERRACT 0x0800 /* LDO2_ERRACT */
412#define WM8400_LDO2_ERRACT_MASK 0x0800 /* LDO2_ERRACT */
413#define WM8400_LDO2_ERRACT_SHIFT 11 /* LDO2_ERRACT */
414#define WM8400_LDO2_ERRACT_WIDTH 1 /* LDO2_ERRACT */
415#define WM8400_LDO2_HIB_MODE 0x0400 /* LDO2_HIB_MODE */
416#define WM8400_LDO2_HIB_MODE_MASK 0x0400 /* LDO2_HIB_MODE */
417#define WM8400_LDO2_HIB_MODE_SHIFT 10 /* LDO2_HIB_MODE */
418#define WM8400_LDO2_HIB_MODE_WIDTH 1 /* LDO2_HIB_MODE */
419#define WM8400_LDO2_VIMG_MASK 0x03E0 /* LDO2_VIMG - [9:5] */
420#define WM8400_LDO2_VIMG_SHIFT 5 /* LDO2_VIMG - [9:5] */
421#define WM8400_LDO2_VIMG_WIDTH 5 /* LDO2_VIMG - [9:5] */
422#define WM8400_LDO2_VSEL_MASK 0x001F /* LDO2_VSEL - [4:0] */
423#define WM8400_LDO2_VSEL_SHIFT 0 /* LDO2_VSEL - [4:0] */
424#define WM8400_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [4:0] */
425
426/*
427 * R67 (0x43) - LDO 3 Control
428 */
429#define WM8400_LDO3_ENA 0x8000 /* LDO3_ENA */
430#define WM8400_LDO3_ENA_MASK 0x8000 /* LDO3_ENA */
431#define WM8400_LDO3_ENA_SHIFT 15 /* LDO3_ENA */
432#define WM8400_LDO3_ENA_WIDTH 1 /* LDO3_ENA */
433#define WM8400_LDO3_SWI 0x4000 /* LDO3_SWI */
434#define WM8400_LDO3_SWI_MASK 0x4000 /* LDO3_SWI */
435#define WM8400_LDO3_SWI_SHIFT 14 /* LDO3_SWI */
436#define WM8400_LDO3_SWI_WIDTH 1 /* LDO3_SWI */
437#define WM8400_LDO3_OPFLT 0x1000 /* LDO3_OPFLT */
438#define WM8400_LDO3_OPFLT_MASK 0x1000 /* LDO3_OPFLT */
439#define WM8400_LDO3_OPFLT_SHIFT 12 /* LDO3_OPFLT */
440#define WM8400_LDO3_OPFLT_WIDTH 1 /* LDO3_OPFLT */
441#define WM8400_LDO3_ERRACT 0x0800 /* LDO3_ERRACT */
442#define WM8400_LDO3_ERRACT_MASK 0x0800 /* LDO3_ERRACT */
443#define WM8400_LDO3_ERRACT_SHIFT 11 /* LDO3_ERRACT */
444#define WM8400_LDO3_ERRACT_WIDTH 1 /* LDO3_ERRACT */
445#define WM8400_LDO3_HIB_MODE 0x0400 /* LDO3_HIB_MODE */
446#define WM8400_LDO3_HIB_MODE_MASK 0x0400 /* LDO3_HIB_MODE */
447#define WM8400_LDO3_HIB_MODE_SHIFT 10 /* LDO3_HIB_MODE */
448#define WM8400_LDO3_HIB_MODE_WIDTH 1 /* LDO3_HIB_MODE */
449#define WM8400_LDO3_VIMG_MASK 0x03E0 /* LDO3_VIMG - [9:5] */
450#define WM8400_LDO3_VIMG_SHIFT 5 /* LDO3_VIMG - [9:5] */
451#define WM8400_LDO3_VIMG_WIDTH 5 /* LDO3_VIMG - [9:5] */
452#define WM8400_LDO3_VSEL_MASK 0x001F /* LDO3_VSEL - [4:0] */
453#define WM8400_LDO3_VSEL_SHIFT 0 /* LDO3_VSEL - [4:0] */
454#define WM8400_LDO3_VSEL_WIDTH 5 /* LDO3_VSEL - [4:0] */
455
456/*
457 * R68 (0x44) - LDO 4 Control
458 */
459#define WM8400_LDO4_ENA 0x8000 /* LDO4_ENA */
460#define WM8400_LDO4_ENA_MASK 0x8000 /* LDO4_ENA */
461#define WM8400_LDO4_ENA_SHIFT 15 /* LDO4_ENA */
462#define WM8400_LDO4_ENA_WIDTH 1 /* LDO4_ENA */
463#define WM8400_LDO4_SWI 0x4000 /* LDO4_SWI */
464#define WM8400_LDO4_SWI_MASK 0x4000 /* LDO4_SWI */
465#define WM8400_LDO4_SWI_SHIFT 14 /* LDO4_SWI */
466#define WM8400_LDO4_SWI_WIDTH 1 /* LDO4_SWI */
467#define WM8400_LDO4_OPFLT 0x1000 /* LDO4_OPFLT */
468#define WM8400_LDO4_OPFLT_MASK 0x1000 /* LDO4_OPFLT */
469#define WM8400_LDO4_OPFLT_SHIFT 12 /* LDO4_OPFLT */
470#define WM8400_LDO4_OPFLT_WIDTH 1 /* LDO4_OPFLT */
471#define WM8400_LDO4_ERRACT 0x0800 /* LDO4_ERRACT */
472#define WM8400_LDO4_ERRACT_MASK 0x0800 /* LDO4_ERRACT */
473#define WM8400_LDO4_ERRACT_SHIFT 11 /* LDO4_ERRACT */
474#define WM8400_LDO4_ERRACT_WIDTH 1 /* LDO4_ERRACT */
475#define WM8400_LDO4_HIB_MODE 0x0400 /* LDO4_HIB_MODE */
476#define WM8400_LDO4_HIB_MODE_MASK 0x0400 /* LDO4_HIB_MODE */
477#define WM8400_LDO4_HIB_MODE_SHIFT 10 /* LDO4_HIB_MODE */
478#define WM8400_LDO4_HIB_MODE_WIDTH 1 /* LDO4_HIB_MODE */
479#define WM8400_LDO4_VIMG_MASK 0x03E0 /* LDO4_VIMG - [9:5] */
480#define WM8400_LDO4_VIMG_SHIFT 5 /* LDO4_VIMG - [9:5] */
481#define WM8400_LDO4_VIMG_WIDTH 5 /* LDO4_VIMG - [9:5] */
482#define WM8400_LDO4_VSEL_MASK 0x001F /* LDO4_VSEL - [4:0] */
483#define WM8400_LDO4_VSEL_SHIFT 0 /* LDO4_VSEL - [4:0] */
484#define WM8400_LDO4_VSEL_WIDTH 5 /* LDO4_VSEL - [4:0] */
485
486/*
487 * R70 (0x46) - DCDC1 Control 1
488 */
489#define WM8400_DC1_ENA 0x8000 /* DC1_ENA */
490#define WM8400_DC1_ENA_MASK 0x8000 /* DC1_ENA */
491#define WM8400_DC1_ENA_SHIFT 15 /* DC1_ENA */
492#define WM8400_DC1_ENA_WIDTH 1 /* DC1_ENA */
493#define WM8400_DC1_ACTIVE 0x4000 /* DC1_ACTIVE */
494#define WM8400_DC1_ACTIVE_MASK 0x4000 /* DC1_ACTIVE */
495#define WM8400_DC1_ACTIVE_SHIFT 14 /* DC1_ACTIVE */
496#define WM8400_DC1_ACTIVE_WIDTH 1 /* DC1_ACTIVE */
497#define WM8400_DC1_SLEEP 0x2000 /* DC1_SLEEP */
498#define WM8400_DC1_SLEEP_MASK 0x2000 /* DC1_SLEEP */
499#define WM8400_DC1_SLEEP_SHIFT 13 /* DC1_SLEEP */
500#define WM8400_DC1_SLEEP_WIDTH 1 /* DC1_SLEEP */
501#define WM8400_DC1_OPFLT 0x1000 /* DC1_OPFLT */
502#define WM8400_DC1_OPFLT_MASK 0x1000 /* DC1_OPFLT */
503#define WM8400_DC1_OPFLT_SHIFT 12 /* DC1_OPFLT */
504#define WM8400_DC1_OPFLT_WIDTH 1 /* DC1_OPFLT */
505#define WM8400_DC1_ERRACT 0x0800 /* DC1_ERRACT */
506#define WM8400_DC1_ERRACT_MASK 0x0800 /* DC1_ERRACT */
507#define WM8400_DC1_ERRACT_SHIFT 11 /* DC1_ERRACT */
508#define WM8400_DC1_ERRACT_WIDTH 1 /* DC1_ERRACT */
509#define WM8400_DC1_HIB_MODE 0x0400 /* DC1_HIB_MODE */
510#define WM8400_DC1_HIB_MODE_MASK 0x0400 /* DC1_HIB_MODE */
511#define WM8400_DC1_HIB_MODE_SHIFT 10 /* DC1_HIB_MODE */
512#define WM8400_DC1_HIB_MODE_WIDTH 1 /* DC1_HIB_MODE */
513#define WM8400_DC1_SOFTST_MASK 0x0300 /* DC1_SOFTST - [9:8] */
514#define WM8400_DC1_SOFTST_SHIFT 8 /* DC1_SOFTST - [9:8] */
515#define WM8400_DC1_SOFTST_WIDTH 2 /* DC1_SOFTST - [9:8] */
516#define WM8400_DC1_OV_PROT 0x0080 /* DC1_OV_PROT */
517#define WM8400_DC1_OV_PROT_MASK 0x0080 /* DC1_OV_PROT */
518#define WM8400_DC1_OV_PROT_SHIFT 7 /* DC1_OV_PROT */
519#define WM8400_DC1_OV_PROT_WIDTH 1 /* DC1_OV_PROT */
520#define WM8400_DC1_VSEL_MASK 0x007F /* DC1_VSEL - [6:0] */
521#define WM8400_DC1_VSEL_SHIFT 0 /* DC1_VSEL - [6:0] */
522#define WM8400_DC1_VSEL_WIDTH 7 /* DC1_VSEL - [6:0] */
523
524/*
525 * R71 (0x47) - DCDC1 Control 2
526 */
527#define WM8400_DC1_FRC_PWM 0x2000 /* DC1_FRC_PWM */
528#define WM8400_DC1_FRC_PWM_MASK 0x2000 /* DC1_FRC_PWM */
529#define WM8400_DC1_FRC_PWM_SHIFT 13 /* DC1_FRC_PWM */
530#define WM8400_DC1_FRC_PWM_WIDTH 1 /* DC1_FRC_PWM */
531#define WM8400_DC1_STBY_LIM_MASK 0x0300 /* DC1_STBY_LIM - [9:8] */
532#define WM8400_DC1_STBY_LIM_SHIFT 8 /* DC1_STBY_LIM - [9:8] */
533#define WM8400_DC1_STBY_LIM_WIDTH 2 /* DC1_STBY_LIM - [9:8] */
534#define WM8400_DC1_ACT_LIM 0x0080 /* DC1_ACT_LIM */
535#define WM8400_DC1_ACT_LIM_MASK 0x0080 /* DC1_ACT_LIM */
536#define WM8400_DC1_ACT_LIM_SHIFT 7 /* DC1_ACT_LIM */
537#define WM8400_DC1_ACT_LIM_WIDTH 1 /* DC1_ACT_LIM */
538#define WM8400_DC1_VIMG_MASK 0x007F /* DC1_VIMG - [6:0] */
539#define WM8400_DC1_VIMG_SHIFT 0 /* DC1_VIMG - [6:0] */
540#define WM8400_DC1_VIMG_WIDTH 7 /* DC1_VIMG - [6:0] */
541
542/*
543 * R72 (0x48) - DCDC2 Control 1
544 */
545#define WM8400_DC2_ENA 0x8000 /* DC2_ENA */
546#define WM8400_DC2_ENA_MASK 0x8000 /* DC2_ENA */
547#define WM8400_DC2_ENA_SHIFT 15 /* DC2_ENA */
548#define WM8400_DC2_ENA_WIDTH 1 /* DC2_ENA */
549#define WM8400_DC2_ACTIVE 0x4000 /* DC2_ACTIVE */
550#define WM8400_DC2_ACTIVE_MASK 0x4000 /* DC2_ACTIVE */
551#define WM8400_DC2_ACTIVE_SHIFT 14 /* DC2_ACTIVE */
552#define WM8400_DC2_ACTIVE_WIDTH 1 /* DC2_ACTIVE */
553#define WM8400_DC2_SLEEP 0x2000 /* DC2_SLEEP */
554#define WM8400_DC2_SLEEP_MASK 0x2000 /* DC2_SLEEP */
555#define WM8400_DC2_SLEEP_SHIFT 13 /* DC2_SLEEP */
556#define WM8400_DC2_SLEEP_WIDTH 1 /* DC2_SLEEP */
557#define WM8400_DC2_OPFLT 0x1000 /* DC2_OPFLT */
558#define WM8400_DC2_OPFLT_MASK 0x1000 /* DC2_OPFLT */
559#define WM8400_DC2_OPFLT_SHIFT 12 /* DC2_OPFLT */
560#define WM8400_DC2_OPFLT_WIDTH 1 /* DC2_OPFLT */
561#define WM8400_DC2_ERRACT 0x0800 /* DC2_ERRACT */
562#define WM8400_DC2_ERRACT_MASK 0x0800 /* DC2_ERRACT */
563#define WM8400_DC2_ERRACT_SHIFT 11 /* DC2_ERRACT */
564#define WM8400_DC2_ERRACT_WIDTH 1 /* DC2_ERRACT */
565#define WM8400_DC2_HIB_MODE 0x0400 /* DC2_HIB_MODE */
566#define WM8400_DC2_HIB_MODE_MASK 0x0400 /* DC2_HIB_MODE */
567#define WM8400_DC2_HIB_MODE_SHIFT 10 /* DC2_HIB_MODE */
568#define WM8400_DC2_HIB_MODE_WIDTH 1 /* DC2_HIB_MODE */
569#define WM8400_DC2_SOFTST_MASK 0x0300 /* DC2_SOFTST - [9:8] */
570#define WM8400_DC2_SOFTST_SHIFT 8 /* DC2_SOFTST - [9:8] */
571#define WM8400_DC2_SOFTST_WIDTH 2 /* DC2_SOFTST - [9:8] */
572#define WM8400_DC2_OV_PROT 0x0080 /* DC2_OV_PROT */
573#define WM8400_DC2_OV_PROT_MASK 0x0080 /* DC2_OV_PROT */
574#define WM8400_DC2_OV_PROT_SHIFT 7 /* DC2_OV_PROT */
575#define WM8400_DC2_OV_PROT_WIDTH 1 /* DC2_OV_PROT */
576#define WM8400_DC2_VSEL_MASK 0x007F /* DC2_VSEL - [6:0] */
577#define WM8400_DC2_VSEL_SHIFT 0 /* DC2_VSEL - [6:0] */
578#define WM8400_DC2_VSEL_WIDTH 7 /* DC2_VSEL - [6:0] */
579
580/*
581 * R73 (0x49) - DCDC2 Control 2
582 */
583#define WM8400_DC2_FRC_PWM 0x2000 /* DC2_FRC_PWM */
584#define WM8400_DC2_FRC_PWM_MASK 0x2000 /* DC2_FRC_PWM */
585#define WM8400_DC2_FRC_PWM_SHIFT 13 /* DC2_FRC_PWM */
586#define WM8400_DC2_FRC_PWM_WIDTH 1 /* DC2_FRC_PWM */
587#define WM8400_DC2_STBY_LIM_MASK 0x0300 /* DC2_STBY_LIM - [9:8] */
588#define WM8400_DC2_STBY_LIM_SHIFT 8 /* DC2_STBY_LIM - [9:8] */
589#define WM8400_DC2_STBY_LIM_WIDTH 2 /* DC2_STBY_LIM - [9:8] */
590#define WM8400_DC2_ACT_LIM 0x0080 /* DC2_ACT_LIM */
591#define WM8400_DC2_ACT_LIM_MASK 0x0080 /* DC2_ACT_LIM */
592#define WM8400_DC2_ACT_LIM_SHIFT 7 /* DC2_ACT_LIM */
593#define WM8400_DC2_ACT_LIM_WIDTH 1 /* DC2_ACT_LIM */
594#define WM8400_DC2_VIMG_MASK 0x007F /* DC2_VIMG - [6:0] */
595#define WM8400_DC2_VIMG_SHIFT 0 /* DC2_VIMG - [6:0] */
596#define WM8400_DC2_VIMG_WIDTH 7 /* DC2_VIMG - [6:0] */
597
598/*
599 * R75 (0x4B) - Interface
600 */
601#define WM8400_AUTOINC 0x0008 /* AUTOINC */
602#define WM8400_AUTOINC_MASK 0x0008 /* AUTOINC */
603#define WM8400_AUTOINC_SHIFT 3 /* AUTOINC */
604#define WM8400_AUTOINC_WIDTH 1 /* AUTOINC */
605#define WM8400_ARA_ENA 0x0004 /* ARA_ENA */
606#define WM8400_ARA_ENA_MASK 0x0004 /* ARA_ENA */
607#define WM8400_ARA_ENA_SHIFT 2 /* ARA_ENA */
608#define WM8400_ARA_ENA_WIDTH 1 /* ARA_ENA */
609#define WM8400_SPI_CFG 0x0002 /* SPI_CFG */
610#define WM8400_SPI_CFG_MASK 0x0002 /* SPI_CFG */
611#define WM8400_SPI_CFG_SHIFT 1 /* SPI_CFG */
612#define WM8400_SPI_CFG_WIDTH 1 /* SPI_CFG */
613
614/*
615 * R76 (0x4C) - PM GENERAL
616 */
617#define WM8400_CODEC_SOFTST 0x8000 /* CODEC_SOFTST */
618#define WM8400_CODEC_SOFTST_MASK 0x8000 /* CODEC_SOFTST */
619#define WM8400_CODEC_SOFTST_SHIFT 15 /* CODEC_SOFTST */
620#define WM8400_CODEC_SOFTST_WIDTH 1 /* CODEC_SOFTST */
621#define WM8400_CODEC_SOFTSD 0x4000 /* CODEC_SOFTSD */
622#define WM8400_CODEC_SOFTSD_MASK 0x4000 /* CODEC_SOFTSD */
623#define WM8400_CODEC_SOFTSD_SHIFT 14 /* CODEC_SOFTSD */
624#define WM8400_CODEC_SOFTSD_WIDTH 1 /* CODEC_SOFTSD */
625#define WM8400_CHIP_SOFTSD 0x2000 /* CHIP_SOFTSD */
626#define WM8400_CHIP_SOFTSD_MASK 0x2000 /* CHIP_SOFTSD */
627#define WM8400_CHIP_SOFTSD_SHIFT 13 /* CHIP_SOFTSD */
628#define WM8400_CHIP_SOFTSD_WIDTH 1 /* CHIP_SOFTSD */
629#define WM8400_DSLEEP1_POL 0x0008 /* DSLEEP1_POL */
630#define WM8400_DSLEEP1_POL_MASK 0x0008 /* DSLEEP1_POL */
631#define WM8400_DSLEEP1_POL_SHIFT 3 /* DSLEEP1_POL */
632#define WM8400_DSLEEP1_POL_WIDTH 1 /* DSLEEP1_POL */
633#define WM8400_DSLEEP2_POL 0x0004 /* DSLEEP2_POL */
634#define WM8400_DSLEEP2_POL_MASK 0x0004 /* DSLEEP2_POL */
635#define WM8400_DSLEEP2_POL_SHIFT 2 /* DSLEEP2_POL */
636#define WM8400_DSLEEP2_POL_WIDTH 1 /* DSLEEP2_POL */
637#define WM8400_PWR_STATE_MASK 0x0003 /* PWR_STATE - [1:0] */
638#define WM8400_PWR_STATE_SHIFT 0 /* PWR_STATE - [1:0] */
639#define WM8400_PWR_STATE_WIDTH 2 /* PWR_STATE - [1:0] */
640
641/*
642 * R78 (0x4E) - PM Shutdown Control
643 */
644#define WM8400_CHIP_GT150_ERRACT 0x0200 /* CHIP_GT150_ERRACT */
645#define WM8400_CHIP_GT150_ERRACT_MASK 0x0200 /* CHIP_GT150_ERRACT */
646#define WM8400_CHIP_GT150_ERRACT_SHIFT 9 /* CHIP_GT150_ERRACT */
647#define WM8400_CHIP_GT150_ERRACT_WIDTH 1 /* CHIP_GT150_ERRACT */
648#define WM8400_CHIP_GT115_ERRACT 0x0100 /* CHIP_GT115_ERRACT */
649#define WM8400_CHIP_GT115_ERRACT_MASK 0x0100 /* CHIP_GT115_ERRACT */
650#define WM8400_CHIP_GT115_ERRACT_SHIFT 8 /* CHIP_GT115_ERRACT */
651#define WM8400_CHIP_GT115_ERRACT_WIDTH 1 /* CHIP_GT115_ERRACT */
652#define WM8400_LINE_CMP_ERRACT 0x0080 /* LINE_CMP_ERRACT */
653#define WM8400_LINE_CMP_ERRACT_MASK 0x0080 /* LINE_CMP_ERRACT */
654#define WM8400_LINE_CMP_ERRACT_SHIFT 7 /* LINE_CMP_ERRACT */
655#define WM8400_LINE_CMP_ERRACT_WIDTH 1 /* LINE_CMP_ERRACT */
656#define WM8400_UVLO_ERRACT 0x0040 /* UVLO_ERRACT */
657#define WM8400_UVLO_ERRACT_MASK 0x0040 /* UVLO_ERRACT */
658#define WM8400_UVLO_ERRACT_SHIFT 6 /* UVLO_ERRACT */
659#define WM8400_UVLO_ERRACT_WIDTH 1 /* UVLO_ERRACT */
660
661/*
662 * R79 (0x4F) - Interrupt Status 1
663 */
664#define WM8400_MICD_CINT 0x8000 /* MICD_CINT */
665#define WM8400_MICD_CINT_MASK 0x8000 /* MICD_CINT */
666#define WM8400_MICD_CINT_SHIFT 15 /* MICD_CINT */
667#define WM8400_MICD_CINT_WIDTH 1 /* MICD_CINT */
668#define WM8400_MICSCD_CINT 0x4000 /* MICSCD_CINT */
669#define WM8400_MICSCD_CINT_MASK 0x4000 /* MICSCD_CINT */
670#define WM8400_MICSCD_CINT_SHIFT 14 /* MICSCD_CINT */
671#define WM8400_MICSCD_CINT_WIDTH 1 /* MICSCD_CINT */
672#define WM8400_JDL_CINT 0x2000 /* JDL_CINT */
673#define WM8400_JDL_CINT_MASK 0x2000 /* JDL_CINT */
674#define WM8400_JDL_CINT_SHIFT 13 /* JDL_CINT */
675#define WM8400_JDL_CINT_WIDTH 1 /* JDL_CINT */
676#define WM8400_JDR_CINT 0x1000 /* JDR_CINT */
677#define WM8400_JDR_CINT_MASK 0x1000 /* JDR_CINT */
678#define WM8400_JDR_CINT_SHIFT 12 /* JDR_CINT */
679#define WM8400_JDR_CINT_WIDTH 1 /* JDR_CINT */
680#define WM8400_CODEC_SEQ_END_EINT 0x0800 /* CODEC_SEQ_END_EINT */
681#define WM8400_CODEC_SEQ_END_EINT_MASK 0x0800 /* CODEC_SEQ_END_EINT */
682#define WM8400_CODEC_SEQ_END_EINT_SHIFT 11 /* CODEC_SEQ_END_EINT */
683#define WM8400_CODEC_SEQ_END_EINT_WIDTH 1 /* CODEC_SEQ_END_EINT */
684#define WM8400_CDEL_TO_EINT 0x0400 /* CDEL_TO_EINT */
685#define WM8400_CDEL_TO_EINT_MASK 0x0400 /* CDEL_TO_EINT */
686#define WM8400_CDEL_TO_EINT_SHIFT 10 /* CDEL_TO_EINT */
687#define WM8400_CDEL_TO_EINT_WIDTH 1 /* CDEL_TO_EINT */
688#define WM8400_CHIP_GT150_EINT 0x0200 /* CHIP_GT150_EINT */
689#define WM8400_CHIP_GT150_EINT_MASK 0x0200 /* CHIP_GT150_EINT */
690#define WM8400_CHIP_GT150_EINT_SHIFT 9 /* CHIP_GT150_EINT */
691#define WM8400_CHIP_GT150_EINT_WIDTH 1 /* CHIP_GT150_EINT */
692#define WM8400_CHIP_GT115_EINT 0x0100 /* CHIP_GT115_EINT */
693#define WM8400_CHIP_GT115_EINT_MASK 0x0100 /* CHIP_GT115_EINT */
694#define WM8400_CHIP_GT115_EINT_SHIFT 8 /* CHIP_GT115_EINT */
695#define WM8400_CHIP_GT115_EINT_WIDTH 1 /* CHIP_GT115_EINT */
696#define WM8400_LINE_CMP_EINT 0x0080 /* LINE_CMP_EINT */
697#define WM8400_LINE_CMP_EINT_MASK 0x0080 /* LINE_CMP_EINT */
698#define WM8400_LINE_CMP_EINT_SHIFT 7 /* LINE_CMP_EINT */
699#define WM8400_LINE_CMP_EINT_WIDTH 1 /* LINE_CMP_EINT */
700#define WM8400_UVLO_EINT 0x0040 /* UVLO_EINT */
701#define WM8400_UVLO_EINT_MASK 0x0040 /* UVLO_EINT */
702#define WM8400_UVLO_EINT_SHIFT 6 /* UVLO_EINT */
703#define WM8400_UVLO_EINT_WIDTH 1 /* UVLO_EINT */
704#define WM8400_DC2_UV_EINT 0x0020 /* DC2_UV_EINT */
705#define WM8400_DC2_UV_EINT_MASK 0x0020 /* DC2_UV_EINT */
706#define WM8400_DC2_UV_EINT_SHIFT 5 /* DC2_UV_EINT */
707#define WM8400_DC2_UV_EINT_WIDTH 1 /* DC2_UV_EINT */
708#define WM8400_DC1_UV_EINT 0x0010 /* DC1_UV_EINT */
709#define WM8400_DC1_UV_EINT_MASK 0x0010 /* DC1_UV_EINT */
710#define WM8400_DC1_UV_EINT_SHIFT 4 /* DC1_UV_EINT */
711#define WM8400_DC1_UV_EINT_WIDTH 1 /* DC1_UV_EINT */
712#define WM8400_LDO4_UV_EINT 0x0008 /* LDO4_UV_EINT */
713#define WM8400_LDO4_UV_EINT_MASK 0x0008 /* LDO4_UV_EINT */
714#define WM8400_LDO4_UV_EINT_SHIFT 3 /* LDO4_UV_EINT */
715#define WM8400_LDO4_UV_EINT_WIDTH 1 /* LDO4_UV_EINT */
716#define WM8400_LDO3_UV_EINT 0x0004 /* LDO3_UV_EINT */
717#define WM8400_LDO3_UV_EINT_MASK 0x0004 /* LDO3_UV_EINT */
718#define WM8400_LDO3_UV_EINT_SHIFT 2 /* LDO3_UV_EINT */
719#define WM8400_LDO3_UV_EINT_WIDTH 1 /* LDO3_UV_EINT */
720#define WM8400_LDO2_UV_EINT 0x0002 /* LDO2_UV_EINT */
721#define WM8400_LDO2_UV_EINT_MASK 0x0002 /* LDO2_UV_EINT */
722#define WM8400_LDO2_UV_EINT_SHIFT 1 /* LDO2_UV_EINT */
723#define WM8400_LDO2_UV_EINT_WIDTH 1 /* LDO2_UV_EINT */
724#define WM8400_LDO1_UV_EINT 0x0001 /* LDO1_UV_EINT */
725#define WM8400_LDO1_UV_EINT_MASK 0x0001 /* LDO1_UV_EINT */
726#define WM8400_LDO1_UV_EINT_SHIFT 0 /* LDO1_UV_EINT */
727#define WM8400_LDO1_UV_EINT_WIDTH 1 /* LDO1_UV_EINT */
728
729/*
730 * R80 (0x50) - Interrupt Status 1 Mask
731 */
732#define WM8400_IM_MICD_CINT 0x8000 /* IM_MICD_CINT */
733#define WM8400_IM_MICD_CINT_MASK 0x8000 /* IM_MICD_CINT */
734#define WM8400_IM_MICD_CINT_SHIFT 15 /* IM_MICD_CINT */
735#define WM8400_IM_MICD_CINT_WIDTH 1 /* IM_MICD_CINT */
736#define WM8400_IM_MICSCD_CINT 0x4000 /* IM_MICSCD_CINT */
737#define WM8400_IM_MICSCD_CINT_MASK 0x4000 /* IM_MICSCD_CINT */
738#define WM8400_IM_MICSCD_CINT_SHIFT 14 /* IM_MICSCD_CINT */
739#define WM8400_IM_MICSCD_CINT_WIDTH 1 /* IM_MICSCD_CINT */
740#define WM8400_IM_JDL_CINT 0x2000 /* IM_JDL_CINT */
741#define WM8400_IM_JDL_CINT_MASK 0x2000 /* IM_JDL_CINT */
742#define WM8400_IM_JDL_CINT_SHIFT 13 /* IM_JDL_CINT */
743#define WM8400_IM_JDL_CINT_WIDTH 1 /* IM_JDL_CINT */
744#define WM8400_IM_JDR_CINT 0x1000 /* IM_JDR_CINT */
745#define WM8400_IM_JDR_CINT_MASK 0x1000 /* IM_JDR_CINT */
746#define WM8400_IM_JDR_CINT_SHIFT 12 /* IM_JDR_CINT */
747#define WM8400_IM_JDR_CINT_WIDTH 1 /* IM_JDR_CINT */
748#define WM8400_IM_CODEC_SEQ_END_EINT 0x0800 /* IM_CODEC_SEQ_END_EINT */
749#define WM8400_IM_CODEC_SEQ_END_EINT_MASK 0x0800 /* IM_CODEC_SEQ_END_EINT */
750#define WM8400_IM_CODEC_SEQ_END_EINT_SHIFT 11 /* IM_CODEC_SEQ_END_EINT */
751#define WM8400_IM_CODEC_SEQ_END_EINT_WIDTH 1 /* IM_CODEC_SEQ_END_EINT */
752#define WM8400_IM_CDEL_TO_EINT 0x0400 /* IM_CDEL_TO_EINT */
753#define WM8400_IM_CDEL_TO_EINT_MASK 0x0400 /* IM_CDEL_TO_EINT */
754#define WM8400_IM_CDEL_TO_EINT_SHIFT 10 /* IM_CDEL_TO_EINT */
755#define WM8400_IM_CDEL_TO_EINT_WIDTH 1 /* IM_CDEL_TO_EINT */
756#define WM8400_IM_CHIP_GT150_EINT 0x0200 /* IM_CHIP_GT150_EINT */
757#define WM8400_IM_CHIP_GT150_EINT_MASK 0x0200 /* IM_CHIP_GT150_EINT */
758#define WM8400_IM_CHIP_GT150_EINT_SHIFT 9 /* IM_CHIP_GT150_EINT */
759#define WM8400_IM_CHIP_GT150_EINT_WIDTH 1 /* IM_CHIP_GT150_EINT */
760#define WM8400_IM_CHIP_GT115_EINT 0x0100 /* IM_CHIP_GT115_EINT */
761#define WM8400_IM_CHIP_GT115_EINT_MASK 0x0100 /* IM_CHIP_GT115_EINT */
762#define WM8400_IM_CHIP_GT115_EINT_SHIFT 8 /* IM_CHIP_GT115_EINT */
763#define WM8400_IM_CHIP_GT115_EINT_WIDTH 1 /* IM_CHIP_GT115_EINT */
764#define WM8400_IM_LINE_CMP_EINT 0x0080 /* IM_LINE_CMP_EINT */
765#define WM8400_IM_LINE_CMP_EINT_MASK 0x0080 /* IM_LINE_CMP_EINT */
766#define WM8400_IM_LINE_CMP_EINT_SHIFT 7 /* IM_LINE_CMP_EINT */
767#define WM8400_IM_LINE_CMP_EINT_WIDTH 1 /* IM_LINE_CMP_EINT */
768#define WM8400_IM_UVLO_EINT 0x0040 /* IM_UVLO_EINT */
769#define WM8400_IM_UVLO_EINT_MASK 0x0040 /* IM_UVLO_EINT */
770#define WM8400_IM_UVLO_EINT_SHIFT 6 /* IM_UVLO_EINT */
771#define WM8400_IM_UVLO_EINT_WIDTH 1 /* IM_UVLO_EINT */
772#define WM8400_IM_DC2_UV_EINT 0x0020 /* IM_DC2_UV_EINT */
773#define WM8400_IM_DC2_UV_EINT_MASK 0x0020 /* IM_DC2_UV_EINT */
774#define WM8400_IM_DC2_UV_EINT_SHIFT 5 /* IM_DC2_UV_EINT */
775#define WM8400_IM_DC2_UV_EINT_WIDTH 1 /* IM_DC2_UV_EINT */
776#define WM8400_IM_DC1_UV_EINT 0x0010 /* IM_DC1_UV_EINT */
777#define WM8400_IM_DC1_UV_EINT_MASK 0x0010 /* IM_DC1_UV_EINT */
778#define WM8400_IM_DC1_UV_EINT_SHIFT 4 /* IM_DC1_UV_EINT */
779#define WM8400_IM_DC1_UV_EINT_WIDTH 1 /* IM_DC1_UV_EINT */
780#define WM8400_IM_LDO4_UV_EINT 0x0008 /* IM_LDO4_UV_EINT */
781#define WM8400_IM_LDO4_UV_EINT_MASK 0x0008 /* IM_LDO4_UV_EINT */
782#define WM8400_IM_LDO4_UV_EINT_SHIFT 3 /* IM_LDO4_UV_EINT */
783#define WM8400_IM_LDO4_UV_EINT_WIDTH 1 /* IM_LDO4_UV_EINT */
784#define WM8400_IM_LDO3_UV_EINT 0x0004 /* IM_LDO3_UV_EINT */
785#define WM8400_IM_LDO3_UV_EINT_MASK 0x0004 /* IM_LDO3_UV_EINT */
786#define WM8400_IM_LDO3_UV_EINT_SHIFT 2 /* IM_LDO3_UV_EINT */
787#define WM8400_IM_LDO3_UV_EINT_WIDTH 1 /* IM_LDO3_UV_EINT */
788#define WM8400_IM_LDO2_UV_EINT 0x0002 /* IM_LDO2_UV_EINT */
789#define WM8400_IM_LDO2_UV_EINT_MASK 0x0002 /* IM_LDO2_UV_EINT */
790#define WM8400_IM_LDO2_UV_EINT_SHIFT 1 /* IM_LDO2_UV_EINT */
791#define WM8400_IM_LDO2_UV_EINT_WIDTH 1 /* IM_LDO2_UV_EINT */
792#define WM8400_IM_LDO1_UV_EINT 0x0001 /* IM_LDO1_UV_EINT */
793#define WM8400_IM_LDO1_UV_EINT_MASK 0x0001 /* IM_LDO1_UV_EINT */
794#define WM8400_IM_LDO1_UV_EINT_SHIFT 0 /* IM_LDO1_UV_EINT */
795#define WM8400_IM_LDO1_UV_EINT_WIDTH 1 /* IM_LDO1_UV_EINT */
796
797/*
798 * R81 (0x51) - Interrupt Levels
799 */
800#define WM8400_MICD_LVL 0x8000 /* MICD_LVL */
801#define WM8400_MICD_LVL_MASK 0x8000 /* MICD_LVL */
802#define WM8400_MICD_LVL_SHIFT 15 /* MICD_LVL */
803#define WM8400_MICD_LVL_WIDTH 1 /* MICD_LVL */
804#define WM8400_MICSCD_LVL 0x4000 /* MICSCD_LVL */
805#define WM8400_MICSCD_LVL_MASK 0x4000 /* MICSCD_LVL */
806#define WM8400_MICSCD_LVL_SHIFT 14 /* MICSCD_LVL */
807#define WM8400_MICSCD_LVL_WIDTH 1 /* MICSCD_LVL */
808#define WM8400_JDL_LVL 0x2000 /* JDL_LVL */
809#define WM8400_JDL_LVL_MASK 0x2000 /* JDL_LVL */
810#define WM8400_JDL_LVL_SHIFT 13 /* JDL_LVL */
811#define WM8400_JDL_LVL_WIDTH 1 /* JDL_LVL */
812#define WM8400_JDR_LVL 0x1000 /* JDR_LVL */
813#define WM8400_JDR_LVL_MASK 0x1000 /* JDR_LVL */
814#define WM8400_JDR_LVL_SHIFT 12 /* JDR_LVL */
815#define WM8400_JDR_LVL_WIDTH 1 /* JDR_LVL */
816#define WM8400_CODEC_SEQ_END_LVL 0x0800 /* CODEC_SEQ_END_LVL */
817#define WM8400_CODEC_SEQ_END_LVL_MASK 0x0800 /* CODEC_SEQ_END_LVL */
818#define WM8400_CODEC_SEQ_END_LVL_SHIFT 11 /* CODEC_SEQ_END_LVL */
819#define WM8400_CODEC_SEQ_END_LVL_WIDTH 1 /* CODEC_SEQ_END_LVL */
820#define WM8400_CDEL_TO_LVL 0x0400 /* CDEL_TO_LVL */
821#define WM8400_CDEL_TO_LVL_MASK 0x0400 /* CDEL_TO_LVL */
822#define WM8400_CDEL_TO_LVL_SHIFT 10 /* CDEL_TO_LVL */
823#define WM8400_CDEL_TO_LVL_WIDTH 1 /* CDEL_TO_LVL */
824#define WM8400_CHIP_GT150_LVL 0x0200 /* CHIP_GT150_LVL */
825#define WM8400_CHIP_GT150_LVL_MASK 0x0200 /* CHIP_GT150_LVL */
826#define WM8400_CHIP_GT150_LVL_SHIFT 9 /* CHIP_GT150_LVL */
827#define WM8400_CHIP_GT150_LVL_WIDTH 1 /* CHIP_GT150_LVL */
828#define WM8400_CHIP_GT115_LVL 0x0100 /* CHIP_GT115_LVL */
829#define WM8400_CHIP_GT115_LVL_MASK 0x0100 /* CHIP_GT115_LVL */
830#define WM8400_CHIP_GT115_LVL_SHIFT 8 /* CHIP_GT115_LVL */
831#define WM8400_CHIP_GT115_LVL_WIDTH 1 /* CHIP_GT115_LVL */
832#define WM8400_LINE_CMP_LVL 0x0080 /* LINE_CMP_LVL */
833#define WM8400_LINE_CMP_LVL_MASK 0x0080 /* LINE_CMP_LVL */
834#define WM8400_LINE_CMP_LVL_SHIFT 7 /* LINE_CMP_LVL */
835#define WM8400_LINE_CMP_LVL_WIDTH 1 /* LINE_CMP_LVL */
836#define WM8400_UVLO_LVL 0x0040 /* UVLO_LVL */
837#define WM8400_UVLO_LVL_MASK 0x0040 /* UVLO_LVL */
838#define WM8400_UVLO_LVL_SHIFT 6 /* UVLO_LVL */
839#define WM8400_UVLO_LVL_WIDTH 1 /* UVLO_LVL */
840#define WM8400_DC2_UV_LVL 0x0020 /* DC2_UV_LVL */
841#define WM8400_DC2_UV_LVL_MASK 0x0020 /* DC2_UV_LVL */
842#define WM8400_DC2_UV_LVL_SHIFT 5 /* DC2_UV_LVL */
843#define WM8400_DC2_UV_LVL_WIDTH 1 /* DC2_UV_LVL */
844#define WM8400_DC1_UV_LVL 0x0010 /* DC1_UV_LVL */
845#define WM8400_DC1_UV_LVL_MASK 0x0010 /* DC1_UV_LVL */
846#define WM8400_DC1_UV_LVL_SHIFT 4 /* DC1_UV_LVL */
847#define WM8400_DC1_UV_LVL_WIDTH 1 /* DC1_UV_LVL */
848#define WM8400_LDO4_UV_LVL 0x0008 /* LDO4_UV_LVL */
849#define WM8400_LDO4_UV_LVL_MASK 0x0008 /* LDO4_UV_LVL */
850#define WM8400_LDO4_UV_LVL_SHIFT 3 /* LDO4_UV_LVL */
851#define WM8400_LDO4_UV_LVL_WIDTH 1 /* LDO4_UV_LVL */
852#define WM8400_LDO3_UV_LVL 0x0004 /* LDO3_UV_LVL */
853#define WM8400_LDO3_UV_LVL_MASK 0x0004 /* LDO3_UV_LVL */
854#define WM8400_LDO3_UV_LVL_SHIFT 2 /* LDO3_UV_LVL */
855#define WM8400_LDO3_UV_LVL_WIDTH 1 /* LDO3_UV_LVL */
856#define WM8400_LDO2_UV_LVL 0x0002 /* LDO2_UV_LVL */
857#define WM8400_LDO2_UV_LVL_MASK 0x0002 /* LDO2_UV_LVL */
858#define WM8400_LDO2_UV_LVL_SHIFT 1 /* LDO2_UV_LVL */
859#define WM8400_LDO2_UV_LVL_WIDTH 1 /* LDO2_UV_LVL */
860#define WM8400_LDO1_UV_LVL 0x0001 /* LDO1_UV_LVL */
861#define WM8400_LDO1_UV_LVL_MASK 0x0001 /* LDO1_UV_LVL */
862#define WM8400_LDO1_UV_LVL_SHIFT 0 /* LDO1_UV_LVL */
863#define WM8400_LDO1_UV_LVL_WIDTH 1 /* LDO1_UV_LVL */
864
865/*
866 * R82 (0x52) - Shutdown Reason
867 */
868#define WM8400_SDR_CHIP_SOFTSD 0x2000 /* SDR_CHIP_SOFTSD */
869#define WM8400_SDR_CHIP_SOFTSD_MASK 0x2000 /* SDR_CHIP_SOFTSD */
870#define WM8400_SDR_CHIP_SOFTSD_SHIFT 13 /* SDR_CHIP_SOFTSD */
871#define WM8400_SDR_CHIP_SOFTSD_WIDTH 1 /* SDR_CHIP_SOFTSD */
872#define WM8400_SDR_NPDN 0x0800 /* SDR_NPDN */
873#define WM8400_SDR_NPDN_MASK 0x0800 /* SDR_NPDN */
874#define WM8400_SDR_NPDN_SHIFT 11 /* SDR_NPDN */
875#define WM8400_SDR_NPDN_WIDTH 1 /* SDR_NPDN */
876#define WM8400_SDR_CHIP_GT150 0x0200 /* SDR_CHIP_GT150 */
877#define WM8400_SDR_CHIP_GT150_MASK 0x0200 /* SDR_CHIP_GT150 */
878#define WM8400_SDR_CHIP_GT150_SHIFT 9 /* SDR_CHIP_GT150 */
879#define WM8400_SDR_CHIP_GT150_WIDTH 1 /* SDR_CHIP_GT150 */
880#define WM8400_SDR_CHIP_GT115 0x0100 /* SDR_CHIP_GT115 */
881#define WM8400_SDR_CHIP_GT115_MASK 0x0100 /* SDR_CHIP_GT115 */
882#define WM8400_SDR_CHIP_GT115_SHIFT 8 /* SDR_CHIP_GT115 */
883#define WM8400_SDR_CHIP_GT115_WIDTH 1 /* SDR_CHIP_GT115 */
884#define WM8400_SDR_LINE_CMP 0x0080 /* SDR_LINE_CMP */
885#define WM8400_SDR_LINE_CMP_MASK 0x0080 /* SDR_LINE_CMP */
886#define WM8400_SDR_LINE_CMP_SHIFT 7 /* SDR_LINE_CMP */
887#define WM8400_SDR_LINE_CMP_WIDTH 1 /* SDR_LINE_CMP */
888#define WM8400_SDR_UVLO 0x0040 /* SDR_UVLO */
889#define WM8400_SDR_UVLO_MASK 0x0040 /* SDR_UVLO */
890#define WM8400_SDR_UVLO_SHIFT 6 /* SDR_UVLO */
891#define WM8400_SDR_UVLO_WIDTH 1 /* SDR_UVLO */
892#define WM8400_SDR_DC2_UV 0x0020 /* SDR_DC2_UV */
893#define WM8400_SDR_DC2_UV_MASK 0x0020 /* SDR_DC2_UV */
894#define WM8400_SDR_DC2_UV_SHIFT 5 /* SDR_DC2_UV */
895#define WM8400_SDR_DC2_UV_WIDTH 1 /* SDR_DC2_UV */
896#define WM8400_SDR_DC1_UV 0x0010 /* SDR_DC1_UV */
897#define WM8400_SDR_DC1_UV_MASK 0x0010 /* SDR_DC1_UV */
898#define WM8400_SDR_DC1_UV_SHIFT 4 /* SDR_DC1_UV */
899#define WM8400_SDR_DC1_UV_WIDTH 1 /* SDR_DC1_UV */
900#define WM8400_SDR_LDO4_UV 0x0008 /* SDR_LDO4_UV */
901#define WM8400_SDR_LDO4_UV_MASK 0x0008 /* SDR_LDO4_UV */
902#define WM8400_SDR_LDO4_UV_SHIFT 3 /* SDR_LDO4_UV */
903#define WM8400_SDR_LDO4_UV_WIDTH 1 /* SDR_LDO4_UV */
904#define WM8400_SDR_LDO3_UV 0x0004 /* SDR_LDO3_UV */
905#define WM8400_SDR_LDO3_UV_MASK 0x0004 /* SDR_LDO3_UV */
906#define WM8400_SDR_LDO3_UV_SHIFT 2 /* SDR_LDO3_UV */
907#define WM8400_SDR_LDO3_UV_WIDTH 1 /* SDR_LDO3_UV */
908#define WM8400_SDR_LDO2_UV 0x0002 /* SDR_LDO2_UV */
909#define WM8400_SDR_LDO2_UV_MASK 0x0002 /* SDR_LDO2_UV */
910#define WM8400_SDR_LDO2_UV_SHIFT 1 /* SDR_LDO2_UV */
911#define WM8400_SDR_LDO2_UV_WIDTH 1 /* SDR_LDO2_UV */
912#define WM8400_SDR_LDO1_UV 0x0001 /* SDR_LDO1_UV */
913#define WM8400_SDR_LDO1_UV_MASK 0x0001 /* SDR_LDO1_UV */
914#define WM8400_SDR_LDO1_UV_SHIFT 0 /* SDR_LDO1_UV */
915#define WM8400_SDR_LDO1_UV_WIDTH 1 /* SDR_LDO1_UV */
916
917/*
918 * R84 (0x54) - Line Circuits
919 */
920#define WM8400_BG_LINE_COMP 0x8000 /* BG_LINE_COMP */
921#define WM8400_BG_LINE_COMP_MASK 0x8000 /* BG_LINE_COMP */
922#define WM8400_BG_LINE_COMP_SHIFT 15 /* BG_LINE_COMP */
923#define WM8400_BG_LINE_COMP_WIDTH 1 /* BG_LINE_COMP */
924#define WM8400_LINE_CMP_VTHI_MASK 0x00F0 /* LINE_CMP_VTHI - [7:4] */
925#define WM8400_LINE_CMP_VTHI_SHIFT 4 /* LINE_CMP_VTHI - [7:4] */
926#define WM8400_LINE_CMP_VTHI_WIDTH 4 /* LINE_CMP_VTHI - [7:4] */
927#define WM8400_LINE_CMP_VTHD_MASK 0x000F /* LINE_CMP_VTHD - [3:0] */
928#define WM8400_LINE_CMP_VTHD_SHIFT 0 /* LINE_CMP_VTHD - [3:0] */
929#define WM8400_LINE_CMP_VTHD_WIDTH 4 /* LINE_CMP_VTHD - [3:0] */
930
931u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg);
932int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data);
933int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val);
934
935#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 11:49:55 -0500