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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2008-10-13 19:11:27 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2008-10-13 19:11:27 -0400
commit5006d1aae813727cc77cc56cca9e90ef748650ce (patch)
treec24a6c2adff1cb311f5f94b3e6357313006fd14d
parent22d660ffd0db8d136b122751287d186e869ca474 (diff)
parent4c3ed7d61bd474380e0d3e1eb0da164942f7c84e (diff)
Merge commit 'gcl/gcl-next'
-rw-r--r--arch/powerpc/platforms/52xx/mpc52xx_common.c5
-rw-r--r--arch/powerpc/platforms/52xx/mpc52xx_pci.c13
-rw-r--r--drivers/i2c/busses/i2c-mpc.c1
-rw-r--r--drivers/of/base.c2
-rw-r--r--drivers/spi/mpc52xx_psc_spi.c6
5 files changed, 16 insertions, 11 deletions
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c
index 4d5fd1dbd400..044b4e6e8743 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -90,7 +90,7 @@ mpc5200_setup_xlb_arbiter(void)
90 of_node_put(np); 90 of_node_put(np);
91 if (!xlb) { 91 if (!xlb) {
92 printk(KERN_ERR __FILE__ ": " 92 printk(KERN_ERR __FILE__ ": "
93 "Error mapping XLB in mpc52xx_setup_cpu(). " 93 "Error mapping XLB in mpc52xx_setup_cpu(). "
94 "Expect some abnormal behavior\n"); 94 "Expect some abnormal behavior\n");
95 return; 95 return;
96 } 96 }
@@ -216,7 +216,8 @@ mpc52xx_restart(char *cmd)
216 out_be32(&mpc52xx_wdt->count, 0x000000ff); 216 out_be32(&mpc52xx_wdt->count, 0x000000ff);
217 out_be32(&mpc52xx_wdt->mode, 0x00009004); 217 out_be32(&mpc52xx_wdt->mode, 0x00009004);
218 } else 218 } else
219 printk("mpc52xx_restart: Can't access wdt. " 219 printk(KERN_ERR __FILE__ ": "
220 "mpc52xx_restart: Can't access wdt. "
220 "Restart impossible, system halted.\n"); 221 "Restart impossible, system halted.\n");
221 222
222 while (1); 223 while (1);
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pci.c b/arch/powerpc/platforms/52xx/mpc52xx_pci.c
index 5a382bb15f62..b49a18527661 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_pci.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pci.c
@@ -265,8 +265,11 @@ mpc52xx_pci_setup(struct pci_controller *hose,
265 /* Memory windows */ 265 /* Memory windows */
266 res = &hose->mem_resources[0]; 266 res = &hose->mem_resources[0];
267 if (res->flags) { 267 if (res->flags) {
268 pr_debug("mem_resource[0] = {.start=%x, .end=%x, .flags=%lx}\n", 268 pr_debug("mem_resource[0] = "
269 res->start, res->end, res->flags); 269 "{.start=%llx, .end=%llx, .flags=%llx}\n",
270 (unsigned long long)res->start,
271 (unsigned long long)res->end,
272 (unsigned long long)res->flags);
270 out_be32(&pci_regs->iw0btar, 273 out_be32(&pci_regs->iw0btar,
271 MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start, 274 MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start,
272 res->end - res->start + 1)); 275 res->end - res->start + 1));
@@ -297,9 +300,11 @@ mpc52xx_pci_setup(struct pci_controller *hose,
297 printk(KERN_ERR "%s: Didn't find IO resources\n", __FILE__); 300 printk(KERN_ERR "%s: Didn't find IO resources\n", __FILE__);
298 return; 301 return;
299 } 302 }
300 pr_debug(".io_resource={.start=%x,.end=%x,.flags=%lx} " 303 pr_debug(".io_resource={.start=%llx,.end=%llx,.flags=%llx} "
301 ".io_base_phys=0x%p\n", 304 ".io_base_phys=0x%p\n",
302 res->start, res->end, res->flags, (void*)hose->io_base_phys); 305 (unsigned long long)res->start,
306 (unsigned long long)res->end,
307 (unsigned long long)res->flags, (void*)hose->io_base_phys);
303 out_be32(&pci_regs->iw2btar, 308 out_be32(&pci_regs->iw2btar,
304 MPC52xx_PCI_IWBTAR_TRANSLATION(hose->io_base_phys, 309 MPC52xx_PCI_IWBTAR_TRANSLATION(hose->io_base_phys,
305 res->start, 310 res->start,
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index 27443f073bc9..a9a45fcc8544 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -312,7 +312,6 @@ static struct i2c_adapter mpc_ops = {
312 .name = "MPC adapter", 312 .name = "MPC adapter",
313 .id = I2C_HW_MPC107, 313 .id = I2C_HW_MPC107,
314 .algo = &mpc_algo, 314 .algo = &mpc_algo,
315 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
316 .timeout = 1, 315 .timeout = 1,
317}; 316};
318 317
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 4270eb4a26a1..7c79e94a35ea 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -410,7 +410,7 @@ struct of_modalias_table {
410 char *modalias; 410 char *modalias;
411}; 411};
412static struct of_modalias_table of_modalias_table[] = { 412static struct of_modalias_table of_modalias_table[] = {
413 /* Empty for now; add entries as needed */ 413 { "fsl,mcu-mpc8349emitx", "mcu-mpc8349emitx" },
414}; 414};
415 415
416/** 416/**
diff --git a/drivers/spi/mpc52xx_psc_spi.c b/drivers/spi/mpc52xx_psc_spi.c
index 25eda71f4bf4..cdb3d3191719 100644
--- a/drivers/spi/mpc52xx_psc_spi.c
+++ b/drivers/spi/mpc52xx_psc_spi.c
@@ -108,13 +108,13 @@ static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
108 * Because psc->ccr is defined as 16bit register instead of 32bit 108 * Because psc->ccr is defined as 16bit register instead of 32bit
109 * just set the lower byte of BitClkDiv 109 * just set the lower byte of BitClkDiv
110 */ 110 */
111 ccr = in_be16(&psc->ccr); 111 ccr = in_be16((u16 __iomem *)&psc->ccr);
112 ccr &= 0xFF00; 112 ccr &= 0xFF00;
113 if (cs->speed_hz) 113 if (cs->speed_hz)
114 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; 114 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
115 else /* by default SPI Clk 1MHz */ 115 else /* by default SPI Clk 1MHz */
116 ccr |= (MCLK / 1000000 - 1) & 0xFF; 116 ccr |= (MCLK / 1000000 - 1) & 0xFF;
117 out_be16(&psc->ccr, ccr); 117 out_be16((u16 __iomem *)&psc->ccr, ccr);
118 mps->bits_per_word = cs->bits_per_word; 118 mps->bits_per_word = cs->bits_per_word;
119 119
120 if (mps->activate_cs) 120 if (mps->activate_cs)
@@ -347,7 +347,7 @@ static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
347 /* Configure 8bit codec mode as a SPI master and use EOF flags */ 347 /* Configure 8bit codec mode as a SPI master and use EOF flags */
348 /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */ 348 /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
349 out_be32(&psc->sicr, 0x0180C800); 349 out_be32(&psc->sicr, 0x0180C800);
350 out_be16(&psc->ccr, 0x070F); /* by default SPI Clk 1MHz */ 350 out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
351 351
352 /* Set 2ms DTL delay */ 352 /* Set 2ms DTL delay */
353 out_8(&psc->ctur, 0x00); 353 out_8(&psc->ctur, 0x00);