mmc: dw_mmc: correct the calculation for CLKDIV

In case of "host->bus_hz < slot->clock", divider value is
miscalculated. And clock divider register value is multiple of 2. If
calculated divider value is odd number, result can be over-clocking.

Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Acked-by: Will Newton <will.newton@gmail.com>
Signed-off-by: Chris Ball <cjb@laptop.org>

1 files changed, 5 insertions, 4 deletions

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index b070ee542c8e..1ca5e72ceb65 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -617,14 +617,15 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot)
         u32 div;
 
         if (slot->clock != host->current_speed) {
-                if (host->bus_hz % slot->clock)
+                div = host->bus_hz / slot->clock;
+                if (host->bus_hz % slot->clock && host->bus_hz > slot->clock)
                         /*
                          * move the + 1 after the divide to prevent
                          * over-clocking the card.
                          */
-                        div = ((host->bus_hz / slot->clock) >> 1) + 1;
-                else
-                        div = (host->bus_hz  / slot->clock) >> 1;
+                        div += 1;
+
+                div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0;
 
                 dev_info(&slot->mmc->class_dev,
                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"