diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-03-07 23:43:55 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-03-07 23:43:55 -0500 |
commit | b44a53d1dad6ba9ed87c8b3324133ec87fe5e588 (patch) | |
tree | dd35d4c9b25be1fe8fa46ef8613fbbe52a410c41 | |
parent | 214d93b02c4fe93638ad268613c9702a81ed9192 (diff) | |
parent | 062ac622e03a8be5f894555ece540d63a54ae8bd (diff) |
Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
drm: index i shadowed in 2nd loop
drm/nv50-nvc0: prevent multiple vm/bar flushes occuring simultanenously
drm/nouveau: fix regression causing ttm to not be able to evict vram
drm/i915: Rebind the buffer if its alignment constraints changes with tiling
drm/i915: Disable GPU semaphores by default
drm/i915: Do not overflow the MMADDR write FIFO
Revert "drm/i915: fix corruptions on i8xx due to relaxed fencing"
-rw-r--r-- | drivers/gpu/drm/drm_fb_helper.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_debugfs.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.c | 17 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 24 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_tiling.c | 37 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.h | 13 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_mem.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_mm.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_instmem.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_vm.c | 4 |
14 files changed, 89 insertions, 46 deletions
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 6977a1ce9d98..f73ef4390db6 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c | |||
@@ -672,7 +672,7 @@ int drm_fb_helper_setcmap(struct fb_cmap *cmap, struct fb_info *info) | |||
672 | struct drm_crtc_helper_funcs *crtc_funcs; | 672 | struct drm_crtc_helper_funcs *crtc_funcs; |
673 | u16 *red, *green, *blue, *transp; | 673 | u16 *red, *green, *blue, *transp; |
674 | struct drm_crtc *crtc; | 674 | struct drm_crtc *crtc; |
675 | int i, rc = 0; | 675 | int i, j, rc = 0; |
676 | int start; | 676 | int start; |
677 | 677 | ||
678 | for (i = 0; i < fb_helper->crtc_count; i++) { | 678 | for (i = 0; i < fb_helper->crtc_count; i++) { |
@@ -685,7 +685,7 @@ int drm_fb_helper_setcmap(struct fb_cmap *cmap, struct fb_info *info) | |||
685 | transp = cmap->transp; | 685 | transp = cmap->transp; |
686 | start = cmap->start; | 686 | start = cmap->start; |
687 | 687 | ||
688 | for (i = 0; i < cmap->len; i++) { | 688 | for (j = 0; j < cmap->len; j++) { |
689 | u16 hred, hgreen, hblue, htransp = 0xffff; | 689 | u16 hred, hgreen, hblue, htransp = 0xffff; |
690 | 690 | ||
691 | hred = *red++; | 691 | hred = *red++; |
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 3601466c5502..4ff9b6cc973f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c | |||
@@ -865,7 +865,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |||
865 | int max_freq; | 865 | int max_freq; |
866 | 866 | ||
867 | /* RPSTAT1 is in the GT power well */ | 867 | /* RPSTAT1 is in the GT power well */ |
868 | __gen6_force_wake_get(dev_priv); | 868 | __gen6_gt_force_wake_get(dev_priv); |
869 | 869 | ||
870 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); | 870 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
871 | seq_printf(m, "RPSTAT1: 0x%08x\n", I915_READ(GEN6_RPSTAT1)); | 871 | seq_printf(m, "RPSTAT1: 0x%08x\n", I915_READ(GEN6_RPSTAT1)); |
@@ -888,7 +888,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |||
888 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | 888 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
889 | max_freq * 100); | 889 | max_freq * 100); |
890 | 890 | ||
891 | __gen6_force_wake_put(dev_priv); | 891 | __gen6_gt_force_wake_put(dev_priv); |
892 | } else { | 892 | } else { |
893 | seq_printf(m, "no P-state info available\n"); | 893 | seq_printf(m, "no P-state info available\n"); |
894 | } | 894 | } |
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 0ad533f06af9..22ec066adae6 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c | |||
@@ -46,6 +46,9 @@ module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); | |||
46 | unsigned int i915_powersave = 1; | 46 | unsigned int i915_powersave = 1; |
47 | module_param_named(powersave, i915_powersave, int, 0600); | 47 | module_param_named(powersave, i915_powersave, int, 0600); |
48 | 48 | ||
49 | unsigned int i915_semaphores = 0; | ||
50 | module_param_named(semaphores, i915_semaphores, int, 0600); | ||
51 | |||
49 | unsigned int i915_enable_rc6 = 0; | 52 | unsigned int i915_enable_rc6 = 0; |
50 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); | 53 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); |
51 | 54 | ||
@@ -254,7 +257,7 @@ void intel_detect_pch (struct drm_device *dev) | |||
254 | } | 257 | } |
255 | } | 258 | } |
256 | 259 | ||
257 | void __gen6_force_wake_get(struct drm_i915_private *dev_priv) | 260 | void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
258 | { | 261 | { |
259 | int count; | 262 | int count; |
260 | 263 | ||
@@ -270,12 +273,22 @@ void __gen6_force_wake_get(struct drm_i915_private *dev_priv) | |||
270 | udelay(10); | 273 | udelay(10); |
271 | } | 274 | } |
272 | 275 | ||
273 | void __gen6_force_wake_put(struct drm_i915_private *dev_priv) | 276 | void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
274 | { | 277 | { |
275 | I915_WRITE_NOTRACE(FORCEWAKE, 0); | 278 | I915_WRITE_NOTRACE(FORCEWAKE, 0); |
276 | POSTING_READ(FORCEWAKE); | 279 | POSTING_READ(FORCEWAKE); |
277 | } | 280 | } |
278 | 281 | ||
282 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) | ||
283 | { | ||
284 | int loop = 500; | ||
285 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | ||
286 | while (fifo < 20 && loop--) { | ||
287 | udelay(10); | ||
288 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | ||
289 | } | ||
290 | } | ||
291 | |||
279 | static int i915_drm_freeze(struct drm_device *dev) | 292 | static int i915_drm_freeze(struct drm_device *dev) |
280 | { | 293 | { |
281 | struct drm_i915_private *dev_priv = dev->dev_private; | 294 | struct drm_i915_private *dev_priv = dev->dev_private; |
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 65dfe81d0035..456f40484838 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -956,6 +956,7 @@ extern struct drm_ioctl_desc i915_ioctls[]; | |||
956 | extern int i915_max_ioctl; | 956 | extern int i915_max_ioctl; |
957 | extern unsigned int i915_fbpercrtc; | 957 | extern unsigned int i915_fbpercrtc; |
958 | extern unsigned int i915_powersave; | 958 | extern unsigned int i915_powersave; |
959 | extern unsigned int i915_semaphores; | ||
959 | extern unsigned int i915_lvds_downclock; | 960 | extern unsigned int i915_lvds_downclock; |
960 | extern unsigned int i915_panel_use_ssc; | 961 | extern unsigned int i915_panel_use_ssc; |
961 | extern unsigned int i915_enable_rc6; | 962 | extern unsigned int i915_enable_rc6; |
@@ -1177,6 +1178,9 @@ void i915_gem_detach_phys_object(struct drm_device *dev, | |||
1177 | void i915_gem_free_all_phys_object(struct drm_device *dev); | 1178 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
1178 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); | 1179 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
1179 | 1180 | ||
1181 | uint32_t | ||
1182 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj); | ||
1183 | |||
1180 | /* i915_gem_gtt.c */ | 1184 | /* i915_gem_gtt.c */ |
1181 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); | 1185 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
1182 | int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); | 1186 | int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); |
@@ -1353,22 +1357,32 @@ __i915_write(64, q) | |||
1353 | * must be set to prevent GT core from power down and stale values being | 1357 | * must be set to prevent GT core from power down and stale values being |
1354 | * returned. | 1358 | * returned. |
1355 | */ | 1359 | */ |
1356 | void __gen6_force_wake_get(struct drm_i915_private *dev_priv); | 1360 | void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1357 | void __gen6_force_wake_put (struct drm_i915_private *dev_priv); | 1361 | void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); |
1358 | static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg) | 1362 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
1363 | |||
1364 | static inline u32 i915_gt_read(struct drm_i915_private *dev_priv, u32 reg) | ||
1359 | { | 1365 | { |
1360 | u32 val; | 1366 | u32 val; |
1361 | 1367 | ||
1362 | if (dev_priv->info->gen >= 6) { | 1368 | if (dev_priv->info->gen >= 6) { |
1363 | __gen6_force_wake_get(dev_priv); | 1369 | __gen6_gt_force_wake_get(dev_priv); |
1364 | val = I915_READ(reg); | 1370 | val = I915_READ(reg); |
1365 | __gen6_force_wake_put(dev_priv); | 1371 | __gen6_gt_force_wake_put(dev_priv); |
1366 | } else | 1372 | } else |
1367 | val = I915_READ(reg); | 1373 | val = I915_READ(reg); |
1368 | 1374 | ||
1369 | return val; | 1375 | return val; |
1370 | } | 1376 | } |
1371 | 1377 | ||
1378 | static inline void i915_gt_write(struct drm_i915_private *dev_priv, | ||
1379 | u32 reg, u32 val) | ||
1380 | { | ||
1381 | if (dev_priv->info->gen >= 6) | ||
1382 | __gen6_gt_wait_for_fifo(dev_priv); | ||
1383 | I915_WRITE(reg, val); | ||
1384 | } | ||
1385 | |||
1372 | static inline void | 1386 | static inline void |
1373 | i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len) | 1387 | i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len) |
1374 | { | 1388 | { |
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index cf4f74c7c6fb..36e66cc5225e 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c | |||
@@ -1398,7 +1398,7 @@ i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj) | |||
1398 | * Return the required GTT alignment for an object, only taking into account | 1398 | * Return the required GTT alignment for an object, only taking into account |
1399 | * unfenced tiled surface requirements. | 1399 | * unfenced tiled surface requirements. |
1400 | */ | 1400 | */ |
1401 | static uint32_t | 1401 | uint32_t |
1402 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) | 1402 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) |
1403 | { | 1403 | { |
1404 | struct drm_device *dev = obj->base.dev; | 1404 | struct drm_device *dev = obj->base.dev; |
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index d2f445e825f2..50ab1614571c 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c | |||
@@ -772,8 +772,8 @@ i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj, | |||
772 | if (from == NULL || to == from) | 772 | if (from == NULL || to == from) |
773 | return 0; | 773 | return 0; |
774 | 774 | ||
775 | /* XXX gpu semaphores are currently causing hard hangs on SNB mobile */ | 775 | /* XXX gpu semaphores are implicated in various hard hangs on SNB */ |
776 | if (INTEL_INFO(obj->base.dev)->gen < 6 || IS_MOBILE(obj->base.dev)) | 776 | if (INTEL_INFO(obj->base.dev)->gen < 6 || !i915_semaphores) |
777 | return i915_gem_object_wait_rendering(obj, true); | 777 | return i915_gem_object_wait_rendering(obj, true); |
778 | 778 | ||
779 | idx = intel_ring_sync_index(from, to); | 779 | idx = intel_ring_sync_index(from, to); |
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index 79a04fde69b5..d64843e18df2 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c | |||
@@ -184,7 +184,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) | |||
184 | static bool | 184 | static bool |
185 | i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) | 185 | i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) |
186 | { | 186 | { |
187 | int tile_width, tile_height; | 187 | int tile_width; |
188 | 188 | ||
189 | /* Linear is always fine */ | 189 | /* Linear is always fine */ |
190 | if (tiling_mode == I915_TILING_NONE) | 190 | if (tiling_mode == I915_TILING_NONE) |
@@ -215,20 +215,6 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) | |||
215 | } | 215 | } |
216 | } | 216 | } |
217 | 217 | ||
218 | if (IS_GEN2(dev) || | ||
219 | (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) | ||
220 | tile_height = 32; | ||
221 | else | ||
222 | tile_height = 8; | ||
223 | /* i8xx is strange: It has 2 interleaved rows of tiles, so needs an even | ||
224 | * number of tile rows. */ | ||
225 | if (IS_GEN2(dev)) | ||
226 | tile_height *= 2; | ||
227 | |||
228 | /* Size needs to be aligned to a full tile row */ | ||
229 | if (size & (tile_height * stride - 1)) | ||
230 | return false; | ||
231 | |||
232 | /* 965+ just needs multiples of tile width */ | 218 | /* 965+ just needs multiples of tile width */ |
233 | if (INTEL_INFO(dev)->gen >= 4) { | 219 | if (INTEL_INFO(dev)->gen >= 4) { |
234 | if (stride & (tile_width - 1)) | 220 | if (stride & (tile_width - 1)) |
@@ -363,14 +349,27 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, | |||
363 | (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end && | 349 | (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end && |
364 | i915_gem_object_fence_ok(obj, args->tiling_mode)); | 350 | i915_gem_object_fence_ok(obj, args->tiling_mode)); |
365 | 351 | ||
366 | obj->tiling_changed = true; | 352 | /* Rebind if we need a change of alignment */ |
367 | obj->tiling_mode = args->tiling_mode; | 353 | if (!obj->map_and_fenceable) { |
368 | obj->stride = args->stride; | 354 | u32 unfenced_alignment = |
355 | i915_gem_get_unfenced_gtt_alignment(obj); | ||
356 | if (obj->gtt_offset & (unfenced_alignment - 1)) | ||
357 | ret = i915_gem_object_unbind(obj); | ||
358 | } | ||
359 | |||
360 | if (ret == 0) { | ||
361 | obj->tiling_changed = true; | ||
362 | obj->tiling_mode = args->tiling_mode; | ||
363 | obj->stride = args->stride; | ||
364 | } | ||
369 | } | 365 | } |
366 | /* we have to maintain this existing ABI... */ | ||
367 | args->stride = obj->stride; | ||
368 | args->tiling_mode = obj->tiling_mode; | ||
370 | drm_gem_object_unreference(&obj->base); | 369 | drm_gem_object_unreference(&obj->base); |
371 | mutex_unlock(&dev->struct_mutex); | 370 | mutex_unlock(&dev->struct_mutex); |
372 | 371 | ||
373 | return 0; | 372 | return ret; |
374 | } | 373 | } |
375 | 374 | ||
376 | /** | 375 | /** |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 729d4233b763..3e6f486f4605 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -3261,6 +3261,8 @@ | |||
3261 | #define FORCEWAKE 0xA18C | 3261 | #define FORCEWAKE 0xA18C |
3262 | #define FORCEWAKE_ACK 0x130090 | 3262 | #define FORCEWAKE_ACK 0x130090 |
3263 | 3263 | ||
3264 | #define GT_FIFO_FREE_ENTRIES 0x120008 | ||
3265 | |||
3264 | #define GEN6_RPNSWREQ 0xA008 | 3266 | #define GEN6_RPNSWREQ 0xA008 |
3265 | #define GEN6_TURBO_DISABLE (1<<31) | 3267 | #define GEN6_TURBO_DISABLE (1<<31) |
3266 | #define GEN6_FREQUENCY(x) ((x)<<25) | 3268 | #define GEN6_FREQUENCY(x) ((x)<<25) |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e79b25bbee6c..49fb54fd9a18 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -1219,7 +1219,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev) | |||
1219 | u32 blt_ecoskpd; | 1219 | u32 blt_ecoskpd; |
1220 | 1220 | ||
1221 | /* Make sure blitter notifies FBC of writes */ | 1221 | /* Make sure blitter notifies FBC of writes */ |
1222 | __gen6_force_wake_get(dev_priv); | 1222 | __gen6_gt_force_wake_get(dev_priv); |
1223 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); | 1223 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
1224 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | 1224 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << |
1225 | GEN6_BLITTER_LOCK_SHIFT; | 1225 | GEN6_BLITTER_LOCK_SHIFT; |
@@ -1230,7 +1230,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev) | |||
1230 | GEN6_BLITTER_LOCK_SHIFT); | 1230 | GEN6_BLITTER_LOCK_SHIFT); |
1231 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | 1231 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
1232 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | 1232 | POSTING_READ(GEN6_BLITTER_ECOSKPD); |
1233 | __gen6_force_wake_put(dev_priv); | 1233 | __gen6_gt_force_wake_put(dev_priv); |
1234 | } | 1234 | } |
1235 | 1235 | ||
1236 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | 1236 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
@@ -6282,7 +6282,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) | |||
6282 | * userspace... | 6282 | * userspace... |
6283 | */ | 6283 | */ |
6284 | I915_WRITE(GEN6_RC_STATE, 0); | 6284 | I915_WRITE(GEN6_RC_STATE, 0); |
6285 | __gen6_force_wake_get(dev_priv); | 6285 | __gen6_gt_force_wake_get(dev_priv); |
6286 | 6286 | ||
6287 | /* disable the counters and set deterministic thresholds */ | 6287 | /* disable the counters and set deterministic thresholds */ |
6288 | I915_WRITE(GEN6_RC_CONTROL, 0); | 6288 | I915_WRITE(GEN6_RC_CONTROL, 0); |
@@ -6380,7 +6380,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) | |||
6380 | /* enable all PM interrupts */ | 6380 | /* enable all PM interrupts */ |
6381 | I915_WRITE(GEN6_PMINTRMSK, 0); | 6381 | I915_WRITE(GEN6_PMINTRMSK, 0); |
6382 | 6382 | ||
6383 | __gen6_force_wake_put(dev_priv); | 6383 | __gen6_gt_force_wake_put(dev_priv); |
6384 | } | 6384 | } |
6385 | 6385 | ||
6386 | void intel_enable_clock_gating(struct drm_device *dev) | 6386 | void intel_enable_clock_gating(struct drm_device *dev) |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 6d6fde85a636..34306865a5df 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h | |||
@@ -14,22 +14,23 @@ struct intel_hw_status_page { | |||
14 | struct drm_i915_gem_object *obj; | 14 | struct drm_i915_gem_object *obj; |
15 | }; | 15 | }; |
16 | 16 | ||
17 | #define I915_RING_READ(reg) i915_safe_read(dev_priv, reg) | 17 | #define I915_RING_READ(reg) i915_gt_read(dev_priv, reg) |
18 | #define I915_RING_WRITE(reg, val) i915_gt_write(dev_priv, reg, val) | ||
18 | 19 | ||
19 | #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base)) | 20 | #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base)) |
20 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) | 21 | #define I915_WRITE_TAIL(ring, val) I915_RING_WRITE(RING_TAIL((ring)->mmio_base), val) |
21 | 22 | ||
22 | #define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base)) | 23 | #define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base)) |
23 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) | 24 | #define I915_WRITE_START(ring, val) I915_RING_WRITE(RING_START((ring)->mmio_base), val) |
24 | 25 | ||
25 | #define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD((ring)->mmio_base)) | 26 | #define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD((ring)->mmio_base)) |
26 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) | 27 | #define I915_WRITE_HEAD(ring, val) I915_RING_WRITE(RING_HEAD((ring)->mmio_base), val) |
27 | 28 | ||
28 | #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base)) | 29 | #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base)) |
29 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) | 30 | #define I915_WRITE_CTL(ring, val) I915_RING_WRITE(RING_CTL((ring)->mmio_base), val) |
30 | 31 | ||
31 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) | ||
32 | #define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base)) | 32 | #define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base)) |
33 | #define I915_WRITE_IMR(ring, val) I915_RING_WRITE(RING_IMR((ring)->mmio_base), val) | ||
33 | 34 | ||
34 | #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base)) | 35 | #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base)) |
35 | #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base)) | 36 | #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base)) |
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c index 26347b7cd872..b0fb9bdcddb7 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c | |||
@@ -725,8 +725,10 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man, | |||
725 | ret = vram->get(dev, mem->num_pages << PAGE_SHIFT, | 725 | ret = vram->get(dev, mem->num_pages << PAGE_SHIFT, |
726 | mem->page_alignment << PAGE_SHIFT, size_nc, | 726 | mem->page_alignment << PAGE_SHIFT, size_nc, |
727 | (nvbo->tile_flags >> 8) & 0xff, &node); | 727 | (nvbo->tile_flags >> 8) & 0xff, &node); |
728 | if (ret) | 728 | if (ret) { |
729 | return ret; | 729 | mem->mm_node = NULL; |
730 | return (ret == -ENOSPC) ? 0 : ret; | ||
731 | } | ||
730 | 732 | ||
731 | node->page_shift = 12; | 733 | node->page_shift = 12; |
732 | if (nvbo->vma.node) | 734 | if (nvbo->vma.node) |
diff --git a/drivers/gpu/drm/nouveau/nouveau_mm.c b/drivers/gpu/drm/nouveau/nouveau_mm.c index 8844b50c3e54..7609756b6faf 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mm.c +++ b/drivers/gpu/drm/nouveau/nouveau_mm.c | |||
@@ -123,7 +123,7 @@ nouveau_mm_get(struct nouveau_mm *rmm, int type, u32 size, u32 size_nc, | |||
123 | return 0; | 123 | return 0; |
124 | } | 124 | } |
125 | 125 | ||
126 | return -ENOMEM; | 126 | return -ENOSPC; |
127 | } | 127 | } |
128 | 128 | ||
129 | int | 129 | int |
diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c index ea0041810ae3..e57caa2a00e3 100644 --- a/drivers/gpu/drm/nouveau/nv50_instmem.c +++ b/drivers/gpu/drm/nouveau/nv50_instmem.c | |||
@@ -403,16 +403,24 @@ nv50_instmem_unmap(struct nouveau_gpuobj *gpuobj) | |||
403 | void | 403 | void |
404 | nv50_instmem_flush(struct drm_device *dev) | 404 | nv50_instmem_flush(struct drm_device *dev) |
405 | { | 405 | { |
406 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
407 | |||
408 | spin_lock(&dev_priv->ramin_lock); | ||
406 | nv_wr32(dev, 0x00330c, 0x00000001); | 409 | nv_wr32(dev, 0x00330c, 0x00000001); |
407 | if (!nv_wait(dev, 0x00330c, 0x00000002, 0x00000000)) | 410 | if (!nv_wait(dev, 0x00330c, 0x00000002, 0x00000000)) |
408 | NV_ERROR(dev, "PRAMIN flush timeout\n"); | 411 | NV_ERROR(dev, "PRAMIN flush timeout\n"); |
412 | spin_unlock(&dev_priv->ramin_lock); | ||
409 | } | 413 | } |
410 | 414 | ||
411 | void | 415 | void |
412 | nv84_instmem_flush(struct drm_device *dev) | 416 | nv84_instmem_flush(struct drm_device *dev) |
413 | { | 417 | { |
418 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
419 | |||
420 | spin_lock(&dev_priv->ramin_lock); | ||
414 | nv_wr32(dev, 0x070000, 0x00000001); | 421 | nv_wr32(dev, 0x070000, 0x00000001); |
415 | if (!nv_wait(dev, 0x070000, 0x00000002, 0x00000000)) | 422 | if (!nv_wait(dev, 0x070000, 0x00000002, 0x00000000)) |
416 | NV_ERROR(dev, "PRAMIN flush timeout\n"); | 423 | NV_ERROR(dev, "PRAMIN flush timeout\n"); |
424 | spin_unlock(&dev_priv->ramin_lock); | ||
417 | } | 425 | } |
418 | 426 | ||
diff --git a/drivers/gpu/drm/nouveau/nv50_vm.c b/drivers/gpu/drm/nouveau/nv50_vm.c index 459ff08241e5..6144156f255a 100644 --- a/drivers/gpu/drm/nouveau/nv50_vm.c +++ b/drivers/gpu/drm/nouveau/nv50_vm.c | |||
@@ -169,7 +169,11 @@ nv50_vm_flush(struct nouveau_vm *vm) | |||
169 | void | 169 | void |
170 | nv50_vm_flush_engine(struct drm_device *dev, int engine) | 170 | nv50_vm_flush_engine(struct drm_device *dev, int engine) |
171 | { | 171 | { |
172 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
173 | |||
174 | spin_lock(&dev_priv->ramin_lock); | ||
172 | nv_wr32(dev, 0x100c80, (engine << 16) | 1); | 175 | nv_wr32(dev, 0x100c80, (engine << 16) | 1); |
173 | if (!nv_wait(dev, 0x100c80, 0x00000001, 0x00000000)) | 176 | if (!nv_wait(dev, 0x100c80, 0x00000001, 0x00000000)) |
174 | NV_ERROR(dev, "vm flush timeout: engine %d\n", engine); | 177 | NV_ERROR(dev, "vm flush timeout: engine %d\n", engine); |
178 | spin_unlock(&dev_priv->ramin_lock); | ||
175 | } | 179 | } |