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authorMike Frysinger <vapier@gentoo.org>2009-09-27 23:16:01 -0400
committerMike Frysinger <vapier@gentoo.org>2011-01-10 07:18:02 -0500
commitb1524e29e318e79b2d04bcbd651a7af8dff32bb3 (patch)
tree7e138995fa0f8727b61fdada567cbda3f95e1670
parent709465d6ea0466454ef547e7d1065db2b23033a9 (diff)
Blackfin: bfin_serial.h: unify heavily duplicated serial code
Each Blackfin port has been duplicating UART structures and defines when there really is no need for it. So start a new bfin_serial.h header to unify all these pieces and give ourselves a fresh start. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat
-rw-r--r--arch/blackfin/include/asm/bfin_serial.h263
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h73
-rw-r--r--arch/blackfin/mach-bf518/include/mach/blackfin.h15
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF51x_base.h45
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h73
-rw-r--r--arch/blackfin/mach-bf527/include/mach/blackfin.h15
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF52x_base.h45
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h74
-rw-r--r--arch/blackfin/mach-bf533/include/mach/blackfin.h15
-rw-r--r--arch/blackfin/mach-bf533/include/mach/defBF532.h77
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h72
-rw-r--r--arch/blackfin/mach-bf537/include/mach/blackfin.h15
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h42
-rw-r--r--arch/blackfin/mach-bf538/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h73
-rw-r--r--arch/blackfin/mach-bf538/include/mach/blackfin.h15
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h77
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bfin_serial.h16
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h60
-rw-r--r--arch/blackfin/mach-bf548/include/mach/blackfin.h15
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h71
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h74
-rw-r--r--arch/blackfin/mach-bf561/include/mach/blackfin.h15
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h77
29 files changed, 377 insertions, 1024 deletions
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
new file mode 100644
index 000000000000..e9510eab5e22
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -0,0 +1,263 @@
1/*
2 * bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_ASM_SERIAL_H__
10#define __BFIN_ASM_SERIAL_H__
11
12#include <linux/serial_core.h>
13#include <mach/anomaly.h>
14#include <mach/bfin_serial.h>
15
16struct circ_buf;
17struct timer_list;
18struct work_struct;
19
20struct bfin_serial_port {
21 struct uart_port port;
22 unsigned int old_status;
23 int status_irq;
24#ifndef BFIN_UART_BF54X_STYLE
25 unsigned int lsr;
26#endif
27#ifdef CONFIG_SERIAL_BFIN_DMA
28 int tx_done;
29 int tx_count;
30 struct circ_buf rx_dma_buf;
31 struct timer_list rx_dma_timer;
32 int rx_dma_nrows;
33 unsigned int tx_dma_channel;
34 unsigned int rx_dma_channel;
35 struct work_struct tx_dma_workqueue;
36#elif ANOMALY_05000363
37 unsigned int anomaly_threshold;
38#endif
39#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
40 int scts;
41#endif
42#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
43 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
44 int cts_pin;
45 int rts_pin;
46#endif
47};
48
49/* UART_LCR Masks */
50#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
51#define STB 0x04 /* Stop Bits */
52#define PEN 0x08 /* Parity Enable */
53#define EPS 0x10 /* Even Parity Select */
54#define STP 0x20 /* Stick Parity */
55#define SB 0x40 /* Set Break */
56#define DLAB 0x80 /* Divisor Latch Access */
57
58/* UART_LSR Masks */
59#define DR 0x01 /* Data Ready */
60#define OE 0x02 /* Overrun Error */
61#define PE 0x04 /* Parity Error */
62#define FE 0x08 /* Framing Error */
63#define BI 0x10 /* Break Interrupt */
64#define THRE 0x20 /* THR Empty */
65#define TEMT 0x40 /* TSR and UART_THR Empty */
66#define TFI 0x80 /* Transmission Finished Indicator */
67
68/* UART_IER Masks */
69#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
70#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
71#define ELSI 0x04 /* Enable RX Status Interrupt */
72#define EDSSI 0x08 /* Enable Modem Status Interrupt */
73#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
74#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
75#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
76
77/* UART_MCR Masks */
78#define XOFF 0x01 /* Transmitter Off */
79#define MRTS 0x02 /* Manual Request To Send */
80#define RFIT 0x04 /* Receive FIFO IRQ Threshold */
81#define RFRT 0x08 /* Receive FIFO RTS Threshold */
82#define LOOP_ENA 0x10 /* Loopback Mode Enable */
83#define FCPOL 0x20 /* Flow Control Pin Polarity */
84#define ARTS 0x40 /* Automatic Request To Send */
85#define ACTS 0x80 /* Automatic Clear To Send */
86
87/* UART_MSR Masks */
88#define SCTS 0x01 /* Sticky CTS */
89#define CTS 0x10 /* Clear To Send */
90#define RFCS 0x20 /* Receive FIFO Count Status */
91
92/* UART_GCTL Masks */
93#define UCEN 0x01 /* Enable UARTx Clocks */
94#define IREN 0x02 /* Enable IrDA Mode */
95#define TPOLC 0x04 /* IrDA TX Polarity Change */
96#define RPOLC 0x08 /* IrDA RX Polarity Change */
97#define FPE 0x10 /* Force Parity Error On Transmit */
98#define FFE 0x20 /* Force Framing Error On Transmit */
99
100#ifdef BFIN_UART_BF54X_STYLE
101# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
102# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
103# define OFFSET_GCTL 0x08 /* Global Control Register */
104# define OFFSET_LCR 0x0C /* Line Control Register */
105# define OFFSET_MCR 0x10 /* Modem Control Register */
106# define OFFSET_LSR 0x14 /* Line Status Register */
107# define OFFSET_MSR 0x18 /* Modem Status Register */
108# define OFFSET_SCR 0x1C /* SCR Scratch Register */
109# define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
110# define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
111# define OFFSET_THR 0x28 /* Transmit Holding register */
112# define OFFSET_RBR 0x2C /* Receive Buffer register */
113#else /* BF533 style */
114# define OFFSET_THR 0x00 /* Transmit Holding register */
115# define OFFSET_RBR 0x00 /* Receive Buffer register */
116# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
117# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
118# define OFFSET_IER 0x04 /* Interrupt Enable Register */
119# define OFFSET_IIR 0x08 /* Interrupt Identification Register */
120# define OFFSET_LCR 0x0C /* Line Control Register */
121# define OFFSET_MCR 0x10 /* Modem Control Register */
122# define OFFSET_LSR 0x14 /* Line Status Register */
123# define OFFSET_MSR 0x18 /* Modem Status Register */
124# define OFFSET_SCR 0x1C /* SCR Scratch Register */
125# define OFFSET_GCTL 0x24 /* Global Control Register */
126/* code should not need IIR, so force build error if they use it */
127# undef OFFSET_IIR
128#endif
129
130/*
131 * All Blackfin system MMRs are padded to 32bits even if the register
132 * itself is only 16bits. So use a helper macro to streamline this.
133 */
134#define __BFP(m) u16 m; u16 __pad_##m
135struct bfin_uart_regs {
136#ifdef BFIN_UART_BF54X_STYLE
137 __BFP(dll);
138 __BFP(dlh);
139 __BFP(gctl);
140 __BFP(lcr);
141 __BFP(mcr);
142 __BFP(lsr);
143 __BFP(msr);
144 __BFP(scr);
145 __BFP(ier_set);
146 __BFP(ier_clear);
147 __BFP(thr);
148 __BFP(rbr);
149#else
150 union {
151 u16 dll;
152 u16 thr;
153 const u16 rbr;
154 };
155 const u16 __pad0;
156 union {
157 u16 dlh;
158 u16 ier;
159 };
160 const u16 __pad1;
161 const __BFP(iir);
162 __BFP(lcr);
163 __BFP(mcr);
164 __BFP(lsr);
165 __BFP(msr);
166 __BFP(scr);
167 const u32 __pad2;
168 __BFP(gctl);
169#endif
170};
171#undef __BFP
172
173#ifndef port_membase
174# define port_membase(p) (((struct bfin_serial_port *)(p))->port.membase)
175#endif
176
177#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
178#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
179#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
180#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
181#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
182#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
183#define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR)
184
185#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
186#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
187#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
188#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
189#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
190#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
191
192#ifdef BFIN_UART_BF54X_STYLE
193
194#define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
195#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET)
196#define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
197
198#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */
199#define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */
200
201#define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1)
202#define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR)
203#define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v)
204
205/* This handles hard CTS/RTS */
206#define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
207#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
208#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
209#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
210#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
211#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
212
213#else /* BF533 style */
214
215#define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
216#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER)
217#define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v)
218#define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v))
219
220#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
221#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
222
223#ifndef put_lsr_cache
224# define put_lsr_cache(p, v) (((struct bfin_serial_port *)(p))->lsr = (v))
225#endif
226#ifndef get_lsr_cache
227# define get_lsr_cache(p) (((struct bfin_serial_port *)(p))->lsr)
228#endif
229
230/* The hardware clears the LSR bits upon read, so we need to cache
231 * some of the more fun bits in software so they don't get lost
232 * when checking the LSR in other code paths (TX).
233 */
234static inline void UART_CLEAR_LSR(void *p)
235{
236 put_lsr_cache(p, 0);
237 bfin_write16(port_membase(p) + OFFSET_LSR, -1);
238}
239static inline unsigned int UART_GET_LSR(void *p)
240{
241 unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
242 put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
243 return lsr | get_lsr_cache(p);
244}
245static inline void UART_PUT_LSR(void *p, uint16_t val)
246{
247 put_lsr_cache(p, get_lsr_cache(p) & ~val);
248}
249
250/* This handles soft CTS/RTS */
251#define UART_GET_CTS(x) gpio_get_value((x)->cts_pin)
252#define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1)
253#define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0)
254#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
255#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
256
257#endif
258
259#ifndef BFIN_UART_TX_FIFO_SIZE
260# define BFIN_UART_TX_FIFO_SIZE 2
261#endif
262
263#endif /* __BFIN_ASM_SERIAL_H__ */
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 2
13
14#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
index 970d310021e7..f6d924ac0c44 100644
--- a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
20#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
21#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
22#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
25#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
26#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39 12
@@ -54,50 +27,6 @@
54# endif 27# endif
55#endif 28#endif
56 29
57#define BFIN_UART_TX_FIFO_SIZE 2
58
59/*
60 * The pin configuration is different from schematic
61 */
62struct bfin_serial_port {
63 struct uart_port port;
64 unsigned int old_status;
65 int status_irq;
66 unsigned int lsr;
67#ifdef CONFIG_SERIAL_BFIN_DMA
68 int tx_done;
69 int tx_count;
70 struct circ_buf rx_dma_buf;
71 struct timer_list rx_dma_timer;
72 int rx_dma_nrows;
73 unsigned int tx_dma_channel;
74 unsigned int rx_dma_channel;
75 struct work_struct tx_dma_workqueue;
76#endif
77#ifdef CONFIG_SERIAL_BFIN_CTSRTS
78 struct timer_list cts_timer;
79 int cts_pin;
80 int rts_pin;
81#endif
82};
83
84/* The hardware clears the LSR bits upon read, so we need to cache
85 * some of the more fun bits in software so they don't get lost
86 * when checking the LSR in other code paths (TX).
87 */
88static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
89{
90 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
91 uart->lsr |= (lsr & (BI|FE|PE|OE));
92 return lsr | uart->lsr;
93}
94
95static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
96{
97 uart->lsr = 0;
98 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
99}
100
101struct bfin_serial_res { 30struct bfin_serial_res {
102 unsigned long uart_base_addr; 31 unsigned long uart_base_addr;
103 int uart_irq; 32 int uart_irq;
@@ -146,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
146}; 75};
147 76
148#define DRIVER_NAME "bfin-uart" 77#define DRIVER_NAME "bfin-uart"
78
79#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h
index 9053462be4b1..3ddc978bada2 100644
--- a/arch/blackfin/mach-bf518/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h
@@ -43,19 +43,4 @@
43#endif 43#endif
44#endif 44#endif
45 45
46#define BFIN_UART_NR_PORTS 2
47
48#define OFFSET_THR 0x00 /* Transmit Holding register */
49#define OFFSET_RBR 0x00 /* Receive Buffer register */
50#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
51#define OFFSET_IER 0x04 /* Interrupt Enable Register */
52#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
53#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
54#define OFFSET_LCR 0x0C /* Line Control Register */
55#define OFFSET_MCR 0x10 /* Modem Control Register */
56#define OFFSET_LSR 0x14 /* Line Status Register */
57#define OFFSET_MSR 0x18 /* Modem Status Register */
58#define OFFSET_SCR 0x1C /* SCR Scratch Register */
59#define OFFSET_GCTL 0x24 /* Global Control Register */
60
61#endif 46#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
index 5f84913dcd91..e816c63a5a5f 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -703,51 +703,6 @@
703#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ 703#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
704#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 704#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
705 705
706
707/* ************** UART CONTROLLER MASKS *************************/
708/* UARTx_LCR Masks */
709#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
710#define STB 0x04 /* Stop Bits */
711#define PEN 0x08 /* Parity Enable */
712#define EPS 0x10 /* Even Parity Select */
713#define STP 0x20 /* Stick Parity */
714#define SB 0x40 /* Set Break */
715#define DLAB 0x80 /* Divisor Latch Access */
716
717/* UARTx_MCR Mask */
718#define LOOP_ENA 0x10 /* Loopback Mode Enable */
719#define LOOP_ENA_P 0x04
720
721/* UARTx_LSR Masks */
722#define DR 0x01 /* Data Ready */
723#define OE 0x02 /* Overrun Error */
724#define PE 0x04 /* Parity Error */
725#define FE 0x08 /* Framing Error */
726#define BI 0x10 /* Break Interrupt */
727#define THRE 0x20 /* THR Empty */
728#define TEMT 0x40 /* TSR and UART_THR Empty */
729
730/* UARTx_IER Masks */
731#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
732#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
733#define ELSI 0x04 /* Enable RX Status Interrupt */
734
735/* UARTx_IIR Masks */
736#define NINT 0x01 /* Pending Interrupt */
737#define IIR_TX_READY 0x02 /* UART_THR empty */
738#define IIR_RX_READY 0x04 /* Receive data ready */
739#define IIR_LINE_CHANGE 0x06 /* Receive line status */
740#define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */
741
742/* UARTx_GCTL Masks */
743#define UCEN 0x01 /* Enable UARTx Clocks */
744#define IREN 0x02 /* Enable IrDA Mode */
745#define TPOLC 0x04 /* IrDA TX Polarity Change */
746#define RPOLC 0x08 /* IrDA RX Polarity Change */
747#define FPE 0x10 /* Force Parity Error On Transmit */
748#define FFE 0x20 /* Force Framing Error On Transmit */
749
750
751/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 706/* **************** GENERAL PURPOSE TIMER MASKS **********************/
752/* TIMER_ENABLE Masks */ 707/* TIMER_ENABLE Masks */
753#define TIMEN0 0x0001 /* Enable Timer 0 */ 708#define TIMEN0 0x0001 /* Enable Timer 0 */
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 2
13
14#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
index c1d55b878b45..960e08919def 100644
--- a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
20#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
21#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
22#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
25#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
26#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39 12
@@ -54,50 +27,6 @@
54# endif 27# endif
55#endif 28#endif
56 29
57#define BFIN_UART_TX_FIFO_SIZE 2
58
59/*
60 * The pin configuration is different from schematic
61 */
62struct bfin_serial_port {
63 struct uart_port port;
64 unsigned int old_status;
65 int status_irq;
66 unsigned int lsr;
67#ifdef CONFIG_SERIAL_BFIN_DMA
68 int tx_done;
69 int tx_count;
70 struct circ_buf rx_dma_buf;
71 struct timer_list rx_dma_timer;
72 int rx_dma_nrows;
73 unsigned int tx_dma_channel;
74 unsigned int rx_dma_channel;
75 struct work_struct tx_dma_workqueue;
76#endif
77#ifdef CONFIG_SERIAL_BFIN_CTSRTS
78 struct timer_list cts_timer;
79 int cts_pin;
80 int rts_pin;
81#endif
82};
83
84/* The hardware clears the LSR bits upon read, so we need to cache
85 * some of the more fun bits in software so they don't get lost
86 * when checking the LSR in other code paths (TX).
87 */
88static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
89{
90 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
91 uart->lsr |= (lsr & (BI|FE|PE|OE));
92 return lsr | uart->lsr;
93}
94
95static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
96{
97 uart->lsr = 0;
98 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
99}
100
101struct bfin_serial_res { 30struct bfin_serial_res {
102 unsigned long uart_base_addr; 31 unsigned long uart_base_addr;
103 int uart_irq; 32 int uart_irq;
@@ -146,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
146}; 75};
147 76
148#define DRIVER_NAME "bfin-uart" 77#define DRIVER_NAME "bfin-uart"
78
79#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h
index f714c5de3073..1ede5e127449 100644
--- a/arch/blackfin/mach-bf527/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h
@@ -31,19 +31,4 @@
31#endif 31#endif
32#endif 32#endif
33 33
34#define BFIN_UART_NR_PORTS 2
35
36#define OFFSET_THR 0x00 /* Transmit Holding register */
37#define OFFSET_RBR 0x00 /* Receive Buffer register */
38#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
39#define OFFSET_IER 0x04 /* Interrupt Enable Register */
40#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
41#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
42#define OFFSET_LCR 0x0C /* Line Control Register */
43#define OFFSET_MCR 0x10 /* Modem Control Register */
44#define OFFSET_LSR 0x14 /* Line Status Register */
45#define OFFSET_MSR 0x18 /* Modem Status Register */
46#define OFFSET_SCR 0x1C /* SCR Scratch Register */
47#define OFFSET_GCTL 0x24 /* Global Control Register */
48
49#endif 34#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index 09475034c6a1..d2594f3b14bc 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -704,51 +704,6 @@
704#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ 704#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
705#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 705#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
706 706
707
708/* ************** UART CONTROLLER MASKS *************************/
709/* UARTx_LCR Masks */
710#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
711#define STB 0x04 /* Stop Bits */
712#define PEN 0x08 /* Parity Enable */
713#define EPS 0x10 /* Even Parity Select */
714#define STP 0x20 /* Stick Parity */
715#define SB 0x40 /* Set Break */
716#define DLAB 0x80 /* Divisor Latch Access */
717
718/* UARTx_MCR Mask */
719#define LOOP_ENA 0x10 /* Loopback Mode Enable */
720#define LOOP_ENA_P 0x04
721
722/* UARTx_LSR Masks */
723#define DR 0x01 /* Data Ready */
724#define OE 0x02 /* Overrun Error */
725#define PE 0x04 /* Parity Error */
726#define FE 0x08 /* Framing Error */
727#define BI 0x10 /* Break Interrupt */
728#define THRE 0x20 /* THR Empty */
729#define TEMT 0x40 /* TSR and UART_THR Empty */
730
731/* UARTx_IER Masks */
732#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
733#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
734#define ELSI 0x04 /* Enable RX Status Interrupt */
735
736/* UARTx_IIR Masks */
737#define NINT 0x01 /* Pending Interrupt */
738#define IIR_TX_READY 0x02 /* UART_THR empty */
739#define IIR_RX_READY 0x04 /* Receive data ready */
740#define IIR_LINE_CHANGE 0x06 /* Receive line status */
741#define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */
742
743/* UARTx_GCTL Masks */
744#define UCEN 0x01 /* Enable UARTx Clocks */
745#define IREN 0x02 /* Enable IrDA Mode */
746#define TPOLC 0x04 /* IrDA TX Polarity Change */
747#define RPOLC 0x08 /* IrDA RX Polarity Change */
748#define FPE 0x10 /* Force Parity Error On Transmit */
749#define FFE 0x20 /* Force Framing Error On Transmit */
750
751
752/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 707/* **************** GENERAL PURPOSE TIMER MASKS **********************/
753/* TIMER_ENABLE Masks */ 708/* TIMER_ENABLE Masks */
754#define TIMEN0 0x0001 /* Enable Timer 0 */ 709#define TIMEN0 0x0001 /* Enable Timer 0 */
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..08072c86d5dc
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 1
13
14#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
index 9e1f3defb6bc..45dcaa4f3e41 100644
--- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
20#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
21#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
22#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
25#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
26#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#ifdef CONFIG_BFIN_UART0_CTSRTS 10#ifdef CONFIG_BFIN_UART0_CTSRTS
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39# ifndef CONFIG_UART0_CTS_PIN 12# ifndef CONFIG_UART0_CTS_PIN
@@ -44,51 +17,6 @@
44# endif 17# endif
45#endif 18#endif
46 19
47#define BFIN_UART_TX_FIFO_SIZE 2
48
49struct bfin_serial_port {
50 struct uart_port port;
51 unsigned int old_status;
52 int status_irq;
53 unsigned int lsr;
54#ifdef CONFIG_SERIAL_BFIN_DMA
55 int tx_done;
56 int tx_count;
57 struct circ_buf rx_dma_buf;
58 struct timer_list rx_dma_timer;
59 int rx_dma_nrows;
60 unsigned int tx_dma_channel;
61 unsigned int rx_dma_channel;
62 struct work_struct tx_dma_workqueue;
63#else
64# if ANOMALY_05000363
65 unsigned int anomaly_threshold;
66# endif
67#endif
68#ifdef CONFIG_SERIAL_BFIN_CTSRTS
69 struct timer_list cts_timer;
70 int cts_pin;
71 int rts_pin;
72#endif
73};
74
75/* The hardware clears the LSR bits upon read, so we need to cache
76 * some of the more fun bits in software so they don't get lost
77 * when checking the LSR in other code paths (TX).
78 */
79static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
80{
81 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
82 uart->lsr |= (lsr & (BI|FE|PE|OE));
83 return lsr | uart->lsr;
84}
85
86static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
87{
88 uart->lsr = 0;
89 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
90}
91
92struct bfin_serial_res { 20struct bfin_serial_res {
93 unsigned long uart_base_addr; 21 unsigned long uart_base_addr;
94 int uart_irq; 22 int uart_irq;
@@ -120,3 +48,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
120}; 48};
121 49
122#define DRIVER_NAME "bfin-uart" 50#define DRIVER_NAME "bfin-uart"
51
52#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h
index f4bd6df5d968..d1dd917ec319 100644
--- a/arch/blackfin/mach-bf533/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h
@@ -17,19 +17,4 @@
17#include "cdefBF532.h" 17#include "cdefBF532.h"
18#endif 18#endif
19 19
20#define BFIN_UART_NR_PORTS 1
21
22#define OFFSET_THR 0x00 /* Transmit Holding register */
23#define OFFSET_RBR 0x00 /* Receive Buffer register */
24#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
25#define OFFSET_IER 0x04 /* Interrupt Enable Register */
26#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
27#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
28#define OFFSET_LCR 0x0C /* Line Control Register */
29#define OFFSET_MCR 0x10 /* Modem Control Register */
30#define OFFSET_LSR 0x14 /* Line Status Register */
31#define OFFSET_MSR 0x18 /* Modem Status Register */
32#define OFFSET_SCR 0x1C /* SCR Scratch Register */
33#define OFFSET_GCTL 0x24 /* Global Control Register */
34
35#endif /* _MACH_BLACKFIN_H_ */ 20#endif /* _MACH_BLACKFIN_H_ */
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
index 3adb0b44e597..8e8099b567f7 100644
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@@ -432,83 +432,6 @@
432#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ 432#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
433#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ 433#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
434 434
435/* ***************************** UART CONTROLLER MASKS ********************** */
436
437/* UART_LCR Register */
438
439#define DLAB 0x80
440#define SB 0x40
441#define STP 0x20
442#define EPS 0x10
443#define PEN 0x08
444#define STB 0x04
445#define WLS(x) ((x-5) & 0x03)
446
447#define DLAB_P 0x07
448#define SB_P 0x06
449#define STP_P 0x05
450#define EPS_P 0x04
451#define PEN_P 0x03
452#define STB_P 0x02
453#define WLS_P1 0x01
454#define WLS_P0 0x00
455
456/* UART_MCR Register */
457#define LOOP_ENA 0x10
458#define LOOP_ENA_P 0x04
459
460/* UART_LSR Register */
461#define TEMT 0x40
462#define THRE 0x20
463#define BI 0x10
464#define FE 0x08
465#define PE 0x04
466#define OE 0x02
467#define DR 0x01
468
469#define TEMP_P 0x06
470#define THRE_P 0x05
471#define BI_P 0x04
472#define FE_P 0x03
473#define PE_P 0x02
474#define OE_P 0x01
475#define DR_P 0x00
476
477/* UART_IER Register */
478#define ELSI 0x04
479#define ETBEI 0x02
480#define ERBFI 0x01
481
482#define ELSI_P 0x02
483#define ETBEI_P 0x01
484#define ERBFI_P 0x00
485
486/* UART_IIR Register */
487#define STATUS(x) ((x << 1) & 0x06)
488#define NINT 0x01
489#define STATUS_P1 0x02
490#define STATUS_P0 0x01
491#define NINT_P 0x00
492#define IIR_TX_READY 0x02 /* UART_THR empty */
493#define IIR_RX_READY 0x04 /* Receive data ready */
494#define IIR_LINE_CHANGE 0x06 /* Receive line status */
495#define IIR_STATUS 0x06
496
497/* UART_GCTL Register */
498#define FFE 0x20
499#define FPE 0x10
500#define RPOLC 0x08
501#define TPOLC 0x04
502#define IREN 0x02
503#define UCEN 0x01
504
505#define FFE_P 0x05
506#define FPE_P 0x04
507#define RPOLC_P 0x03
508#define TPOLC_P 0x02
509#define IREN_P 0x01
510#define UCEN_P 0x00
511
512/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ 435/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
513 436
514/* PPI_CONTROL Masks */ 437/* PPI_CONTROL Masks */
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 2
13
14#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
index 635c91c526a3..3e955dba8951 100644
--- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later 4 * Licensed under the GPL-2 or later
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
20#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
21#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
22#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
25#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
26#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39 12
@@ -54,49 +27,6 @@
54# endif 27# endif
55#endif 28#endif
56 29
57#define BFIN_UART_TX_FIFO_SIZE 2
58
59/*
60 * The pin configuration is different from schematic
61 */
62struct bfin_serial_port {
63 struct uart_port port;
64 unsigned int old_status;
65 int status_irq;
66 unsigned int lsr;
67#ifdef CONFIG_SERIAL_BFIN_DMA
68 int tx_done;
69 int tx_count;
70 struct circ_buf rx_dma_buf;
71 struct timer_list rx_dma_timer;
72 int rx_dma_nrows;
73 unsigned int tx_dma_channel;
74 unsigned int rx_dma_channel;
75 struct work_struct tx_dma_workqueue;
76#endif
77#ifdef CONFIG_SERIAL_BFIN_CTSRTS
78 int cts_pin;
79 int rts_pin;
80#endif
81};
82
83/* The hardware clears the LSR bits upon read, so we need to cache
84 * some of the more fun bits in software so they don't get lost
85 * when checking the LSR in other code paths (TX).
86 */
87static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
88{
89 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
90 uart->lsr |= (lsr & (BI|FE|PE|OE));
91 return lsr | uart->lsr;
92}
93
94static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
95{
96 uart->lsr = 0;
97 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
98}
99
100struct bfin_serial_res { 30struct bfin_serial_res {
101 unsigned long uart_base_addr; 31 unsigned long uart_base_addr;
102 int uart_irq; 32 int uart_irq;
@@ -145,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
145}; 75};
146 76
147#define DRIVER_NAME "bfin-uart" 77#define DRIVER_NAME "bfin-uart"
78
79#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
index a12d4b6a221d..1f8a41bc0741 100644
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h
@@ -25,19 +25,4 @@
25#endif 25#endif
26#endif 26#endif
27 27
28#define BFIN_UART_NR_PORTS 2
29
30#define OFFSET_THR 0x00 /* Transmit Holding register */
31#define OFFSET_RBR 0x00 /* Receive Buffer register */
32#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
33#define OFFSET_IER 0x04 /* Interrupt Enable Register */
34#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
35#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
36#define OFFSET_LCR 0x0C /* Line Control Register */
37#define OFFSET_MCR 0x10 /* Modem Control Register */
38#define OFFSET_LSR 0x14 /* Line Status Register */
39#define OFFSET_MSR 0x18 /* Modem Status Register */
40#define OFFSET_SCR 0x1C /* SCR Scratch Register */
41#define OFFSET_GCTL 0x24 /* Global Control Register */
42
43#endif 28#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 0323e6bacdae..8ca84edf3c38 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1029,48 +1029,6 @@
1029#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ 1029#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1030#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 1030#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1031 1031
1032/* ************** UART CONTROLLER MASKS *************************/
1033/* UARTx_LCR Masks */
1034#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
1035#define STB 0x04 /* Stop Bits */
1036#define PEN 0x08 /* Parity Enable */
1037#define EPS 0x10 /* Even Parity Select */
1038#define STP 0x20 /* Stick Parity */
1039#define SB 0x40 /* Set Break */
1040#define DLAB 0x80 /* Divisor Latch Access */
1041
1042/* UARTx_MCR Mask */
1043#define LOOP_ENA 0x10 /* Loopback Mode Enable */
1044#define LOOP_ENA_P 0x04
1045/* UARTx_LSR Masks */
1046#define DR 0x01 /* Data Ready */
1047#define OE 0x02 /* Overrun Error */
1048#define PE 0x04 /* Parity Error */
1049#define FE 0x08 /* Framing Error */
1050#define BI 0x10 /* Break Interrupt */
1051#define THRE 0x20 /* THR Empty */
1052#define TEMT 0x40 /* TSR and UART_THR Empty */
1053
1054/* UARTx_IER Masks */
1055#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1056#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1057#define ELSI 0x04 /* Enable RX Status Interrupt */
1058
1059/* UARTx_IIR Masks */
1060#define NINT 0x01 /* Pending Interrupt */
1061#define IIR_TX_READY 0x02 /* UART_THR empty */
1062#define IIR_RX_READY 0x04 /* Receive data ready */
1063#define IIR_LINE_CHANGE 0x06 /* Receive line status */
1064#define IIR_STATUS 0x06
1065
1066/* UARTx_GCTL Masks */
1067#define UCEN 0x01 /* Enable UARTx Clocks */
1068#define IREN 0x02 /* Enable IrDA Mode */
1069#define TPOLC 0x04 /* IrDA TX Polarity Change */
1070#define RPOLC 0x08 /* IrDA RX Polarity Change */
1071#define FPE 0x10 /* Force Parity Error On Transmit */
1072#define FFE 0x20 /* Force Framing Error On Transmit */
1073
1074/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 1032/* **************** GENERAL PURPOSE TIMER MASKS **********************/
1075/* TIMER_ENABLE Masks */ 1033/* TIMER_ENABLE Masks */
1076#define TIMEN0 0x0001 /* Enable Timer 0 */ 1034#define TIMEN0 0x0001 /* Enable Timer 0 */
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..c66e2760aad3
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 3
13
14#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
index 5c148142f041..beb502e9cb33 100644
--- a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
20#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
21#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
22#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
25#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
26#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39 12
@@ -54,50 +27,6 @@
54# endif 27# endif
55#endif 28#endif
56 29
57#define BFIN_UART_TX_FIFO_SIZE 2
58
59/*
60 * The pin configuration is different from schematic
61 */
62struct bfin_serial_port {
63 struct uart_port port;
64 unsigned int old_status;
65 int status_irq;
66 unsigned int lsr;
67#ifdef CONFIG_SERIAL_BFIN_DMA
68 int tx_done;
69 int tx_count;
70 struct circ_buf rx_dma_buf;
71 struct timer_list rx_dma_timer;
72 int rx_dma_nrows;
73 unsigned int tx_dma_channel;
74 unsigned int rx_dma_channel;
75 struct work_struct tx_dma_workqueue;
76#endif
77#ifdef CONFIG_SERIAL_BFIN_CTSRTS
78 struct timer_list cts_timer;
79 int cts_pin;
80 int rts_pin;
81#endif
82};
83
84/* The hardware clears the LSR bits upon read, so we need to cache
85 * some of the more fun bits in software so they don't get lost
86 * when checking the LSR in other code paths (TX).
87 */
88static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
89{
90 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
91 uart->lsr |= (lsr & (BI|FE|PE|OE));
92 return lsr | uart->lsr;
93}
94
95static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
96{
97 uart->lsr = 0;
98 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
99}
100
101struct bfin_serial_res { 30struct bfin_serial_res {
102 unsigned long uart_base_addr; 31 unsigned long uart_base_addr;
103 int uart_irq; 32 int uart_irq;
@@ -160,3 +89,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
160}; 89};
161 90
162#define DRIVER_NAME "bfin-uart" 91#define DRIVER_NAME "bfin-uart"
92
93#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
index 08b5eabb1ed5..b82cb0248ab6 100644
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h
@@ -22,19 +22,4 @@
22#endif 22#endif
23#endif 23#endif
24 24
25#define BFIN_UART_NR_PORTS 3
26
27#define OFFSET_THR 0x00 /* Transmit Holding register */
28#define OFFSET_RBR 0x00 /* Receive Buffer register */
29#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
30#define OFFSET_IER 0x04 /* Interrupt Enable Register */
31#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
32#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
33#define OFFSET_LCR 0x0C /* Line Control Register */
34#define OFFSET_MCR 0x10 /* Modem Control Register */
35#define OFFSET_LSR 0x14 /* Line Status Register */
36#define OFFSET_MSR 0x18 /* Modem Status Register */
37#define OFFSET_SCR 0x1C /* SCR Scratch Register */
38#define OFFSET_GCTL 0x24 /* Global Control Register */
39
40#endif 25#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 7a8ac5f44204..0ef05c9845b8 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -1534,83 +1534,6 @@
1534#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 1534#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1535#endif /* _MISRA_RULES */ 1535#endif /* _MISRA_RULES */
1536 1536
1537
1538/* ***************************** UART CONTROLLER MASKS ********************** */
1539/* UARTx_LCR Register */
1540#ifdef _MISRA_RULES
1541#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
1542#else
1543#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
1544#endif /* _MISRA_RULES */
1545#define STB 0x04 /* Stop Bits */
1546#define PEN 0x08 /* Parity Enable */
1547#define EPS 0x10 /* Even Parity Select */
1548#define STP 0x20 /* Stick Parity */
1549#define SB 0x40 /* Set Break */
1550#define DLAB 0x80 /* Divisor Latch Access */
1551
1552#define DLAB_P 0x07
1553#define SB_P 0x06
1554#define STP_P 0x05
1555#define EPS_P 0x04
1556#define PEN_P 0x03
1557#define STB_P 0x02
1558#define WLS_P1 0x01
1559#define WLS_P0 0x00
1560
1561/* UARTx_MCR Register */
1562#define LOOP_ENA 0x10 /* Loopback Mode Enable */
1563#define LOOP_ENA_P 0x04
1564/* Deprecated UARTx_MCR Mask */
1565
1566/* UARTx_LSR Register */
1567#define DR 0x01 /* Data Ready */
1568#define OE 0x02 /* Overrun Error */
1569#define PE 0x04 /* Parity Error */
1570#define FE 0x08 /* Framing Error */
1571#define BI 0x10 /* Break Interrupt */
1572#define THRE 0x20 /* THR Empty */
1573#define TEMT 0x40 /* TSR and UART_THR Empty */
1574
1575#define TEMP_P 0x06
1576#define THRE_P 0x05
1577#define BI_P 0x04
1578#define FE_P 0x03
1579#define PE_P 0x02
1580#define OE_P 0x01
1581#define DR_P 0x00
1582
1583/* UARTx_IER Register */
1584#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1585#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1586#define ELSI 0x04 /* Enable RX Status Interrupt */
1587
1588#define ELSI_P 0x02
1589#define ETBEI_P 0x01
1590#define ERBFI_P 0x00
1591
1592/* UARTx_IIR Register */
1593#define NINT 0x01
1594#define STATUS_P1 0x02
1595#define STATUS_P0 0x01
1596#define NINT_P 0x00
1597
1598/* UARTx_GCTL Register */
1599#define UCEN 0x01 /* Enable UARTx Clocks */
1600#define IREN 0x02 /* Enable IrDA Mode */
1601#define TPOLC 0x04 /* IrDA TX Polarity Change */
1602#define RPOLC 0x08 /* IrDA RX Polarity Change */
1603#define FPE 0x10 /* Force Parity Error On Transmit */
1604#define FFE 0x20 /* Force Framing Error On Transmit */
1605
1606#define FFE_P 0x05
1607#define FPE_P 0x04
1608#define RPOLC_P 0x03
1609#define TPOLC_P 0x02
1610#define IREN_P 0x01
1611#define UCEN_P 0x00
1612
1613
1614/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ 1537/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
1615/* PPI_CONTROL Masks */ 1538/* PPI_CONTROL Masks */
1616#define PORT_EN 0x0001 /* PPI Port Enable */ 1539#define PORT_EN 0x0001 /* PPI Port Enable */
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..a77109f99720
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
@@ -0,0 +1,16 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 4
13
14#define BFIN_UART_BF54X_STYLE
15
16#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
index dd44aa75fe72..0d94edaaaa2e 100644
--- a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
@@ -4,72 +4,14 @@
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
14#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
15#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
16#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18#define UART_GET_MSR(uart) bfin_read16(((uart)->port.membase + OFFSET_MSR))
19#define UART_GET_MCR(uart) bfin_read16(((uart)->port.membase + OFFSET_MCR))
20
21#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
22#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
23#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
24#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
25#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
26#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
27#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
28#define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
29#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
30#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
31#define UART_CLEAR_SCTS(uart) bfin_write16(((uart)->port.membase + OFFSET_MSR),SCTS)
32
33#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */
34#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */
35
36#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
37#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS|MRTS))
38#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
39#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
40#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
41
42#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \ 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
43 defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS) 11 defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
44# define CONFIG_SERIAL_BFIN_HARD_CTSRTS 12# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
45#endif 13#endif
46 14
47#define BFIN_UART_TX_FIFO_SIZE 2
48
49/*
50 * The pin configuration is different from schematic
51 */
52struct bfin_serial_port {
53 struct uart_port port;
54 unsigned int old_status;
55 int status_irq;
56#ifdef CONFIG_SERIAL_BFIN_DMA
57 int tx_done;
58 int tx_count;
59 struct circ_buf rx_dma_buf;
60 struct timer_list rx_dma_timer;
61 int rx_dma_nrows;
62 unsigned int tx_dma_channel;
63 unsigned int rx_dma_channel;
64 struct work_struct tx_dma_workqueue;
65#endif
66#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
67 int scts;
68 int cts_pin;
69 int rts_pin;
70#endif
71};
72
73struct bfin_serial_res { 15struct bfin_serial_res {
74 unsigned long uart_base_addr; 16 unsigned long uart_base_addr;
75 int uart_irq; 17 int uart_irq;
@@ -148,3 +90,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
148}; 90};
149 91
150#define DRIVER_NAME "bfin-uart" 92#define DRIVER_NAME "bfin-uart"
93
94#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
index 5684030ccc21..bbdcde48d050 100644
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -49,19 +49,4 @@
49 49
50#endif 50#endif
51 51
52#define BFIN_UART_NR_PORTS 4
53
54#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
55#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
56#define OFFSET_GCTL 0x08 /* Global Control Register */
57#define OFFSET_LCR 0x0C /* Line Control Register */
58#define OFFSET_MCR 0x10 /* Modem Control Register */
59#define OFFSET_LSR 0x14 /* Line Status Register */
60#define OFFSET_MSR 0x18 /* Modem Status Register */
61#define OFFSET_SCR 0x1C /* SCR Scratch Register */
62#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
63#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
64#define OFFSET_THR 0x28 /* Transmit Holding register */
65#define OFFSET_RBR 0x2C /* Receive Buffer register */
66
67#endif 52#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 78f91103f175..3d751f134b7e 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -2172,68 +2172,6 @@
2172 2172
2173#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */ 2173#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
2174 2174
2175/* Bit masks for UARTx_LCR */
2176
2177#if 0
2178/* conflicts with legacy one in last section */
2179#define WLS 0x3 /* Word Length Select */
2180#endif
2181#define STB 0x4 /* Stop Bits */
2182#define PEN 0x8 /* Parity Enable */
2183#define EPS 0x10 /* Even Parity Select */
2184#define STP 0x20 /* Sticky Parity */
2185#define SB 0x40 /* Set Break */
2186
2187/* Bit masks for UARTx_MCR */
2188
2189#define XOFF 0x1 /* Transmitter Off */
2190#define MRTS 0x2 /* Manual Request To Send */
2191#define RFIT 0x4 /* Receive FIFO IRQ Threshold */
2192#define RFRT 0x8 /* Receive FIFO RTS Threshold */
2193#define LOOP_ENA 0x10 /* Loopback Mode Enable */
2194#define FCPOL 0x20 /* Flow Control Pin Polarity */
2195#define ARTS 0x40 /* Automatic Request To Send */
2196#define ACTS 0x80 /* Automatic Clear To Send */
2197
2198/* Bit masks for UARTx_LSR */
2199
2200#define DR 0x1 /* Data Ready */
2201#define OE 0x2 /* Overrun Error */
2202#define PE 0x4 /* Parity Error */
2203#define FE 0x8 /* Framing Error */
2204#define BI 0x10 /* Break Interrupt */
2205#define THRE 0x20 /* THR Empty */
2206#define TEMT 0x40 /* Transmitter Empty */
2207#define TFI 0x80 /* Transmission Finished Indicator */
2208
2209/* Bit masks for UARTx_MSR */
2210
2211#define SCTS 0x1 /* Sticky CTS */
2212#define CTS 0x10 /* Clear To Send */
2213#define RFCS 0x20 /* Receive FIFO Count Status */
2214
2215/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */
2216
2217#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */
2218#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */
2219#define ELSI 0x4 /* Enable Receive Status Interrupt */
2220#define EDSSI 0x8 /* Enable Modem Status Interrupt */
2221#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
2222#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
2223#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
2224
2225/* Bit masks for UARTx_GCTL */
2226
2227#define UCEN 0x1 /* UART Enable */
2228#define IREN 0x2 /* IrDA Mode Enable */
2229#define TPOLC 0x4 /* IrDA TX Polarity Change */
2230#define RPOLC 0x8 /* IrDA RX Polarity Change */
2231#define FPE 0x10 /* Force Parity Error */
2232#define FFE 0x20 /* Force Framing Error */
2233#define EDBO 0x40 /* Enable Divide-by-One */
2234#define EGLSI 0x80 /* Enable Global LS Interrupt */
2235
2236
2237/* ******************************************* */ 2175/* ******************************************* */
2238/* MULTI BIT MACRO ENUMERATIONS */ 2176/* MULTI BIT MACRO ENUMERATIONS */
2239/* ******************************************* */ 2177/* ******************************************* */
@@ -2251,13 +2189,6 @@
2251#define WDTH_CAP 0x0002 2189#define WDTH_CAP 0x0002
2252#define EXT_CLK 0x0003 2190#define EXT_CLK 0x0003
2253 2191
2254/* UARTx_LCR bit field options */
2255
2256#define WLS_5 0x0000 /* 5 data bits */
2257#define WLS_6 0x0001 /* 6 data bits */
2258#define WLS_7 0x0002 /* 7 data bits */
2259#define WLS_8 0x0003 /* 8 data bits */
2260
2261/* PINTx Register Bit Definitions */ 2192/* PINTx Register Bit Definitions */
2262 2193
2263#define PIQ0 0x00000001 2194#define PIQ0 0x00000001
@@ -2706,8 +2637,6 @@ PORTJ_FER registers
2706 2637
2707/* for legacy compatibility */ 2638/* for legacy compatibility */
2708 2639
2709#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
2710#define W1LMAX_MAX W1LMAX_MIN
2711#define EBIU_AMCBCTL0 EBIU_AMBCTL0 2640#define EBIU_AMCBCTL0 EBIU_AMBCTL0
2712#define EBIU_AMCBCTL1 EBIU_AMBCTL1 2641#define EBIU_AMCBCTL1 EBIU_AMBCTL1
2713#define PINT0_IRQ PINT0_REQUEST 2642#define PINT0_IRQ PINT0_REQUEST
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..08072c86d5dc
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 1
13
14#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
index e33e158bc16d..3a6947456cf1 100644
--- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
20#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
21#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
22#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
25#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
26#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#ifdef CONFIG_BFIN_UART0_CTSRTS 10#ifdef CONFIG_BFIN_UART0_CTSRTS
38# define CONFIG_SERIAL_BFIN_CTSRTS 11# define CONFIG_SERIAL_BFIN_CTSRTS
39# ifndef CONFIG_UART0_CTS_PIN 12# ifndef CONFIG_UART0_CTS_PIN
@@ -44,51 +17,6 @@
44# endif 17# endif
45#endif 18#endif
46 19
47#define BFIN_UART_TX_FIFO_SIZE 2
48
49struct bfin_serial_port {
50 struct uart_port port;
51 unsigned int old_status;
52 int status_irq;
53 unsigned int lsr;
54#ifdef CONFIG_SERIAL_BFIN_DMA
55 int tx_done;
56 int tx_count;
57 struct circ_buf rx_dma_buf;
58 struct timer_list rx_dma_timer;
59 int rx_dma_nrows;
60 unsigned int tx_dma_channel;
61 unsigned int rx_dma_channel;
62 struct work_struct tx_dma_workqueue;
63#else
64# if ANOMALY_05000363
65 unsigned int anomaly_threshold;
66# endif
67#endif
68#ifdef CONFIG_SERIAL_BFIN_CTSRTS
69 struct timer_list cts_timer;
70 int cts_pin;
71 int rts_pin;
72#endif
73};
74
75/* The hardware clears the LSR bits upon read, so we need to cache
76 * some of the more fun bits in software so they don't get lost
77 * when checking the LSR in other code paths (TX).
78 */
79static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
80{
81 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
82 uart->lsr |= (lsr & (BI|FE|PE|OE));
83 return lsr | uart->lsr;
84}
85
86static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
87{
88 uart->lsr = 0;
89 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
90}
91
92struct bfin_serial_res { 20struct bfin_serial_res {
93 unsigned long uart_base_addr; 21 unsigned long uart_base_addr;
94 int uart_irq; 22 int uart_irq;
@@ -120,3 +48,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
120}; 48};
121 49
122#define DRIVER_NAME "bfin-uart" 50#define DRIVER_NAME "bfin-uart"
51
52#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
index 6c7dc58c018c..891cb599aa63 100644
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -35,19 +35,4 @@
35#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x)) 35#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
36#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val) 36#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
37 37
38#define BFIN_UART_NR_PORTS 1
39
40#define OFFSET_THR 0x00 /* Transmit Holding register */
41#define OFFSET_RBR 0x00 /* Receive Buffer register */
42#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
43#define OFFSET_IER 0x04 /* Interrupt Enable Register */
44#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
45#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
46#define OFFSET_LCR 0x0C /* Line Control Register */
47#define OFFSET_MCR 0x10 /* Modem Control Register */
48#define OFFSET_LSR 0x14 /* Line Status Register */
49#define OFFSET_MSR 0x18 /* Modem Status Register */
50#define OFFSET_SCR 0x1C /* SCR Scratch Register */
51#define OFFSET_GCTL 0x24 /* Global Control Register */
52
53#endif /* _MACH_BLACKFIN_H_ */ 38#endif /* _MACH_BLACKFIN_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 79e048d452e0..bfc9180695fe 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -927,83 +927,6 @@
927#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ 927#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
928#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ 928#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
929 929
930/* ***************************** UART CONTROLLER MASKS ********************** */
931
932/* UART_LCR Register */
933
934#define DLAB 0x80
935#define SB 0x40
936#define STP 0x20
937#define EPS 0x10
938#define PEN 0x08
939#define STB 0x04
940#define WLS(x) ((x-5) & 0x03)
941
942#define DLAB_P 0x07
943#define SB_P 0x06
944#define STP_P 0x05
945#define EPS_P 0x04
946#define PEN_P 0x03
947#define STB_P 0x02
948#define WLS_P1 0x01
949#define WLS_P0 0x00
950
951/* UART_MCR Register */
952#define LOOP_ENA 0x10
953#define LOOP_ENA_P 0x04
954
955/* UART_LSR Register */
956#define TEMT 0x40
957#define THRE 0x20
958#define BI 0x10
959#define FE 0x08
960#define PE 0x04
961#define OE 0x02
962#define DR 0x01
963
964#define TEMP_P 0x06
965#define THRE_P 0x05
966#define BI_P 0x04
967#define FE_P 0x03
968#define PE_P 0x02
969#define OE_P 0x01
970#define DR_P 0x00
971
972/* UART_IER Register */
973#define ELSI 0x04
974#define ETBEI 0x02
975#define ERBFI 0x01
976
977#define ELSI_P 0x02
978#define ETBEI_P 0x01
979#define ERBFI_P 0x00
980
981/* UART_IIR Register */
982#define STATUS(x) ((x << 1) & 0x06)
983#define NINT 0x01
984#define STATUS_P1 0x02
985#define STATUS_P0 0x01
986#define NINT_P 0x00
987#define IIR_TX_READY 0x02 /* UART_THR empty */
988#define IIR_RX_READY 0x04 /* Receive data ready */
989#define IIR_LINE_CHANGE 0x06 /* Receive line status */
990#define IIR_STATUS 0x06
991
992/* UART_GCTL Register */
993#define FFE 0x20
994#define FPE 0x10
995#define RPOLC 0x08
996#define TPOLC 0x04
997#define IREN 0x02
998#define UCEN 0x01
999
1000#define FFE_P 0x05
1001#define FPE_P 0x04
1002#define RPOLC_P 0x03
1003#define TPOLC_P 0x02
1004#define IREN_P 0x01
1005#define UCEN_P 0x00
1006
1007/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ 930/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
1008 931
1009/* PPI_CONTROL Masks */ 932/* PPI_CONTROL Masks */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 02:19:11 -0500