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authorMark Lord <liml@rtr.ca>2008-05-27 17:58:56 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-05-30 12:37:23 -0400
commit5cf73bfb061552aa18d816d2859409be9ace5306 (patch)
treecb3afa056f6aabb69a4cd1e6c22448c5d91733ab
parent8c30a8b9b574cf6c51e207464b852a6f559da153 (diff)
sata_mv: nuke unreleased GenIIe revisions
The only public release of the 6042/7042 chips was/is revision "B0". Remove code that attempted to deal with earlier, non-released revs. This matches the logic of the current Marvell "proprietary" driver. Also, bump up the sata_mv version number, to reflect this batch of erratas. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
-rw-r--r--drivers/ata/sata_mv.c23
1 files changed, 4 insertions, 19 deletions
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index a39779aed8f5..969a76987781 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -72,7 +72,7 @@
72#include <linux/libata.h> 72#include <linux/libata.h>
73 73
74#define DRV_NAME "sata_mv" 74#define DRV_NAME "sata_mv"
75#define DRV_VERSION "1.21" 75#define DRV_VERSION "1.22"
76 76
77enum { 77enum {
78 /* BAR's are enumerated in terms of pci_resource_start() terms */ 78 /* BAR's are enumerated in terms of pci_resource_start() terms */
@@ -354,7 +354,6 @@ enum {
354 MV_HP_ERRATA_50XXB2 = (1 << 2), 354 MV_HP_ERRATA_50XXB2 = (1 << 2),
355 MV_HP_ERRATA_60X1B2 = (1 << 3), 355 MV_HP_ERRATA_60X1B2 = (1 << 3),
356 MV_HP_ERRATA_60X1C0 = (1 << 4), 356 MV_HP_ERRATA_60X1C0 = (1 << 4),
357 MV_HP_ERRATA_XX42A0 = (1 << 5),
358 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 357 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
359 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 358 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
360 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 359 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
@@ -811,12 +810,7 @@ static void mv_set_edma_ptrs(void __iomem *port_mmio,
811 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 810 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
812 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 811 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
813 port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 812 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
814 813 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
815 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
816 writelfl((pp->crqb_dma & 0xffffffff) | index,
817 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
818 else
819 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
820 814
821 /* 815 /*
822 * initialize response queue 816 * initialize response queue
@@ -826,13 +820,7 @@ static void mv_set_edma_ptrs(void __iomem *port_mmio,
826 820
827 WARN_ON(pp->crpb_dma & 0xff); 821 WARN_ON(pp->crpb_dma & 0xff);
828 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 822 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
829 823 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
830 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
831 writelfl((pp->crpb_dma & 0xffffffff) | index,
832 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
833 else
834 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
835
836 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 824 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
837 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 825 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
838} 826}
@@ -3002,10 +2990,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3002 hp_flags |= MV_HP_CUT_THROUGH; 2990 hp_flags |= MV_HP_CUT_THROUGH;
3003 2991
3004 switch (pdev->revision) { 2992 switch (pdev->revision) {
3005 case 0x0: 2993 case 0x2: /* Rev.B0: the first/only public release */
3006 hp_flags |= MV_HP_ERRATA_XX42A0;
3007 break;
3008 case 0x1:
3009 hp_flags |= MV_HP_ERRATA_60X1C0; 2994 hp_flags |= MV_HP_ERRATA_60X1C0;
3010 break; 2995 break;
3011 default: 2996 default: