diff options
| author | Scott Wood <scottwood@freescale.com> | 2012-09-12 09:00:09 -0400 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2012-09-17 02:31:47 -0400 |
| commit | f3d3444572dbf01d36884f9b3fe69a611420ad37 (patch) | |
| tree | 98dd108e3803425ec612af65347d26b0cec2fb78 | |
| parent | b92a66a65cb4480774066d9a3080c77eb34b7232 (diff) | |
powerpc/mm: Fix typo in PTRS_PER_PUD
PTRS_PER_PUD should be based on PUD_INDEX_SIZE, not PMD_INDEX_SIZE. We
got away with it because PUD and PMD had the same index size, but this is
no longer true with Aneesh's patchset to support a 46-bit user effective
address space.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| -rw-r--r-- | arch/powerpc/include/asm/pgtable-ppc64-4k.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-4k.h b/arch/powerpc/include/asm/pgtable-ppc64-4k.h index 6eefdcffa359..d6489a2c64c8 100644 --- a/arch/powerpc/include/asm/pgtable-ppc64-4k.h +++ b/arch/powerpc/include/asm/pgtable-ppc64-4k.h | |||
| @@ -19,7 +19,7 @@ | |||
| 19 | 19 | ||
| 20 | #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) | 20 | #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) |
| 21 | #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) | 21 | #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) |
| 22 | #define PTRS_PER_PUD (1 << PMD_INDEX_SIZE) | 22 | #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) |
| 23 | #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) | 23 | #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) |
| 24 | 24 | ||
| 25 | /* PMD_SHIFT determines what a second-level page table entry can map */ | 25 | /* PMD_SHIFT determines what a second-level page table entry can map */ |