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authorDavid Gibson <david@gibson.dropbear.id.au>2006-01-12 22:56:25 -0500
committerPaul Mackerras <paulus@samba.org>2006-01-13 05:16:23 -0500
commite58c3495e6007af59382540bb21ee941e470d88d (patch)
tree24b559cb768bfa5cf4bdef69f2943b081a1f5afa
parent7e78e5e502d4f220d24c6f738f2fdb078ad33607 (diff)
[PATCH] powerpc: Cleanup LOADADDR etc. asm macros
This patch consolidates the variety of macros used for loading 32 or 64-bit constants in assembler (LOADADDR, LOADBASE, SET_REG_TO_*). The idea is to make the set of macros consistent across 32 and 64 bit and to make it more obvious which is the appropriate one to use in a given situation. The new macros and their semantics are described in the comments in ppc_asm.h. In the process, we change several places that were unnecessarily using immediate loads on ppc64 to use the GOT/TOC. Likewise we cleanup a couple of places where we were clumsily subtracting PAGE_OFFSET with asm instructions to use assemble-time arithmetic or the toreal() macro instead. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
-rw-r--r--arch/powerpc/kernel/cpu_setup_power4.S4
-rw-r--r--arch/powerpc/kernel/entry_32.S2
-rw-r--r--arch/powerpc/kernel/entry_64.S12
-rw-r--r--arch/powerpc/kernel/fpu.S10
-rw-r--r--arch/powerpc/kernel/head_64.S87
-rw-r--r--arch/powerpc/kernel/idle_power4.S8
-rw-r--r--arch/powerpc/kernel/misc_32.S4
-rw-r--r--arch/powerpc/kernel/misc_64.S10
-rw-r--r--include/asm-powerpc/ppc_asm.h76
9 files changed, 108 insertions, 105 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_power4.S b/arch/powerpc/kernel/cpu_setup_power4.S
index cca942fe6115..b61d86e7ceb6 100644
--- a/arch/powerpc/kernel/cpu_setup_power4.S
+++ b/arch/powerpc/kernel/cpu_setup_power4.S
@@ -130,7 +130,7 @@ _GLOBAL(__save_cpu_setup)
130 mfcr r7 130 mfcr r7
131 131
132 /* Get storage ptr */ 132 /* Get storage ptr */
133 LOADADDR(r5,cpu_state_storage) 133 LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
134 134
135 /* We only deal with 970 for now */ 135 /* We only deal with 970 for now */
136 mfspr r0,SPRN_PVR 136 mfspr r0,SPRN_PVR
@@ -164,7 +164,7 @@ _GLOBAL(__restore_cpu_setup)
164 /* Get storage ptr (FIXME when using anton reloc as we 164 /* Get storage ptr (FIXME when using anton reloc as we
165 * are running with translation disabled here 165 * are running with translation disabled here
166 */ 166 */
167 LOADADDR(r5,cpu_state_storage) 167 LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
168 168
169 /* We only deal with 970 for now */ 169 /* We only deal with 970 for now */
170 mfspr r0,SPRN_PVR 170 mfspr r0,SPRN_PVR
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 036b71d2adfc..d8da2a35c0a4 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -988,7 +988,7 @@ _GLOBAL(enter_rtas)
988 stwu r1,-INT_FRAME_SIZE(r1) 988 stwu r1,-INT_FRAME_SIZE(r1)
989 mflr r0 989 mflr r0
990 stw r0,INT_FRAME_SIZE+4(r1) 990 stw r0,INT_FRAME_SIZE+4(r1)
991 LOADADDR(r4, rtas) 991 LOAD_REG_ADDR(r4, rtas)
992 lis r6,1f@ha /* physical return address for rtas */ 992 lis r6,1f@ha /* physical return address for rtas */
993 addi r6,r6,1f@l 993 addi r6,r6,1f@l
994 tophys(r6,r6) 994 tophys(r6,r6)
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index aacebb33e98a..4ba81e1b6bf1 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -689,9 +689,8 @@ _GLOBAL(enter_rtas)
689 std r6,PACASAVEDMSR(r13) 689 std r6,PACASAVEDMSR(r13)
690 690
691 /* Setup our real return addr */ 691 /* Setup our real return addr */
692 SET_REG_TO_LABEL(r4,.rtas_return_loc) 692 LOAD_REG_ADDR(r4,.rtas_return_loc)
693 SET_REG_TO_CONST(r9,PAGE_OFFSET) 693 clrldi r4,r4,2 /* convert to realmode address */
694 sub r4,r4,r9
695 mtlr r4 694 mtlr r4
696 695
697 li r0,0 696 li r0,0
@@ -706,7 +705,7 @@ _GLOBAL(enter_rtas)
706 sync /* disable interrupts so SRR0/1 */ 705 sync /* disable interrupts so SRR0/1 */
707 mtmsrd r0 /* don't get trashed */ 706 mtmsrd r0 /* don't get trashed */
708 707
709 SET_REG_TO_LABEL(r4,rtas) 708 LOAD_REG_ADDR(r4, rtas)
710 ld r5,RTASENTRY(r4) /* get the rtas->entry value */ 709 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
711 ld r4,RTASBASE(r4) /* get the rtas->base value */ 710 ld r4,RTASBASE(r4) /* get the rtas->base value */
712 711
@@ -718,8 +717,7 @@ _GLOBAL(enter_rtas)
718_STATIC(rtas_return_loc) 717_STATIC(rtas_return_loc)
719 /* relocation is off at this point */ 718 /* relocation is off at this point */
720 mfspr r4,SPRN_SPRG3 /* Get PACA */ 719 mfspr r4,SPRN_SPRG3 /* Get PACA */
721 SET_REG_TO_CONST(r5, PAGE_OFFSET) 720 clrldi r4,r4,2 /* convert to realmode address */
722 sub r4,r4,r5 /* RELOC the PACA base pointer */
723 721
724 mfmsr r6 722 mfmsr r6
725 li r0,MSR_RI 723 li r0,MSR_RI
@@ -728,7 +726,7 @@ _STATIC(rtas_return_loc)
728 mtmsrd r6 726 mtmsrd r6
729 727
730 ld r1,PACAR1(r4) /* Restore our SP */ 728 ld r1,PACAR1(r4) /* Restore our SP */
731 LOADADDR(r3,.rtas_restore_regs) 729 LOAD_REG_IMMEDIATE(r3,.rtas_restore_regs)
732 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */ 730 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
733 731
734 mtspr SPRN_SRR0,r3 732 mtspr SPRN_SRR0,r3
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index b780b42c95fc..e4362dfa37fb 100644
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -39,9 +39,9 @@ _GLOBAL(load_up_fpu)
39 * to another. Instead we call giveup_fpu in switch_to. 39 * to another. Instead we call giveup_fpu in switch_to.
40 */ 40 */
41#ifndef CONFIG_SMP 41#ifndef CONFIG_SMP
42 LOADBASE(r3, last_task_used_math) 42 LOAD_REG_ADDRBASE(r3, last_task_used_math)
43 toreal(r3) 43 toreal(r3)
44 PPC_LL r4,OFF(last_task_used_math)(r3) 44 PPC_LL r4,ADDROFF(last_task_used_math)(r3)
45 PPC_LCMPI 0,r4,0 45 PPC_LCMPI 0,r4,0
46 beq 1f 46 beq 1f
47 toreal(r4) 47 toreal(r4)
@@ -77,7 +77,7 @@ _GLOBAL(load_up_fpu)
77#ifndef CONFIG_SMP 77#ifndef CONFIG_SMP
78 subi r4,r5,THREAD 78 subi r4,r5,THREAD
79 fromreal(r4) 79 fromreal(r4)
80 PPC_STL r4,OFF(last_task_used_math)(r3) 80 PPC_STL r4,ADDROFF(last_task_used_math)(r3)
81#endif /* CONFIG_SMP */ 81#endif /* CONFIG_SMP */
82 /* restore registers and return */ 82 /* restore registers and return */
83 /* we haven't used ctr or xer or lr */ 83 /* we haven't used ctr or xer or lr */
@@ -113,8 +113,8 @@ _GLOBAL(giveup_fpu)
1131: 1131:
114#ifndef CONFIG_SMP 114#ifndef CONFIG_SMP
115 li r5,0 115 li r5,0
116 LOADBASE(r4,last_task_used_math) 116 LOAD_REG_ADDRBASE(r4,last_task_used_math)
117 PPC_STL r5,OFF(last_task_used_math)(r4) 117 PPC_STL r5,ADDROFF(last_task_used_math)(r4)
118#endif /* CONFIG_SMP */ 118#endif /* CONFIG_SMP */
119 blr 119 blr
120 120
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 1c066d125375..b3718f3eb7b5 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -154,12 +154,12 @@ _GLOBAL(__secondary_hold)
154 bne 100b 154 bne 100b
155 155
156#ifdef CONFIG_HMT 156#ifdef CONFIG_HMT
157 LOADADDR(r4, .hmt_init) 157 SET_REG_IMMEDIATE(r4, .hmt_init)
158 mtctr r4 158 mtctr r4
159 bctr 159 bctr
160#else 160#else
161#ifdef CONFIG_SMP 161#ifdef CONFIG_SMP
162 LOADADDR(r4, .pSeries_secondary_smp_init) 162 LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init)
163 mtctr r4 163 mtctr r4
164 mr r3,r24 164 mr r3,r24
165 bctr 165 bctr
@@ -205,9 +205,10 @@ exception_marker:
205#define EX_LR 72 205#define EX_LR 72
206 206
207/* 207/*
208 * We're short on space and time in the exception prolog, so we can't use 208 * We're short on space and time in the exception prolog, so we can't
209 * the normal LOADADDR macro. Normally we just need the low halfword of the 209 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
210 * address, but for Kdump we need the whole low word. 210 * low halfword of the address, but for Kdump we need the whole low
211 * word.
211 */ 212 */
212#ifdef CONFIG_CRASH_DUMP 213#ifdef CONFIG_CRASH_DUMP
213#define LOAD_HANDLER(reg, label) \ 214#define LOAD_HANDLER(reg, label) \
@@ -713,7 +714,7 @@ system_reset_iSeries:
713 lbz r23,PACAPROCSTART(r13) /* Test if this processor 714 lbz r23,PACAPROCSTART(r13) /* Test if this processor
714 * should start */ 715 * should start */
715 sync 716 sync
716 LOADADDR(r3,current_set) 717 LOAD_REG_IMMEDIATE(r3,current_set)
717 sldi r28,r24,3 /* get current_set[cpu#] */ 718 sldi r28,r24,3 /* get current_set[cpu#] */
718 ldx r3,r3,r28 719 ldx r3,r3,r28
719 addi r1,r3,THREAD_SIZE 720 addi r1,r3,THREAD_SIZE
@@ -746,8 +747,8 @@ iSeries_secondary_smp_loop:
746decrementer_iSeries_masked: 747decrementer_iSeries_masked:
747 li r11,1 748 li r11,1
748 stb r11,PACALPPACA+LPPACADECRINT(r13) 749 stb r11,PACALPPACA+LPPACADECRINT(r13)
749 LOADBASE(r12,tb_ticks_per_jiffy) 750 LOAD_REG_ADDRBASE(r12,tb_ticks_per_jiffy)
750 lwz r12,OFF(tb_ticks_per_jiffy)(r12) 751 lwz r12,ADDROFF(tb_ticks_per_jiffy)(r12)
751 mtspr SPRN_DEC,r12 752 mtspr SPRN_DEC,r12
752 /* fall through */ 753 /* fall through */
753 754
@@ -1412,7 +1413,7 @@ _GLOBAL(pSeries_secondary_smp_init)
1412 * physical cpu id in r24, we need to search the pacas to find 1413 * physical cpu id in r24, we need to search the pacas to find
1413 * which logical id maps to our physical one. 1414 * which logical id maps to our physical one.
1414 */ 1415 */
1415 LOADADDR(r13, paca) /* Get base vaddr of paca array */ 1416 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */
1416 li r5,0 /* logical cpu id */ 1417 li r5,0 /* logical cpu id */
14171: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 14181: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1418 cmpw r6,r24 /* Compare to our id */ 1419 cmpw r6,r24 /* Compare to our id */
@@ -1446,8 +1447,8 @@ _GLOBAL(pSeries_secondary_smp_init)
1446#ifdef CONFIG_PPC_ISERIES 1447#ifdef CONFIG_PPC_ISERIES
1447_STATIC(__start_initialization_iSeries) 1448_STATIC(__start_initialization_iSeries)
1448 /* Clear out the BSS */ 1449 /* Clear out the BSS */
1449 LOADADDR(r11,__bss_stop) 1450 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1450 LOADADDR(r8,__bss_start) 1451 LOAD_REG_IMMEDIATE(r8,__bss_start)
1451 sub r11,r11,r8 /* bss size */ 1452 sub r11,r11,r8 /* bss size */
1452 addi r11,r11,7 /* round up to an even double word */ 1453 addi r11,r11,7 /* round up to an even double word */
1453 rldicl. r11,r11,61,3 /* shift right by 3 */ 1454 rldicl. r11,r11,61,3 /* shift right by 3 */
@@ -1458,17 +1459,17 @@ _STATIC(__start_initialization_iSeries)
14583: stdu r0,8(r8) 14593: stdu r0,8(r8)
1459 bdnz 3b 1460 bdnz 3b
14604: 14614:
1461 LOADADDR(r1,init_thread_union) 1462 LOAD_REG_IMMEDIATE(r1,init_thread_union)
1462 addi r1,r1,THREAD_SIZE 1463 addi r1,r1,THREAD_SIZE
1463 li r0,0 1464 li r0,0
1464 stdu r0,-STACK_FRAME_OVERHEAD(r1) 1465 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1465 1466
1466 LOADADDR(r3,cpu_specs) 1467 LOAD_REG_IMMEDIATE(r3,cpu_specs)
1467 LOADADDR(r4,cur_cpu_spec) 1468 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
1468 li r5,0 1469 li r5,0
1469 bl .identify_cpu 1470 bl .identify_cpu
1470 1471
1471 LOADADDR(r2,__toc_start) 1472 LOAD_REG_IMMEDIATE(r2,__toc_start)
1472 addi r2,r2,0x4000 1473 addi r2,r2,0x4000
1473 addi r2,r2,0x4000 1474 addi r2,r2,0x4000
1474 1475
@@ -1528,7 +1529,7 @@ _GLOBAL(__start_initialization_multiplatform)
1528 li r24,0 1529 li r24,0
1529 1530
1530 /* Switch off MMU if not already */ 1531 /* Switch off MMU if not already */
1531 LOADADDR(r4, .__after_prom_start - KERNELBASE) 1532 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1532 add r4,r4,r30 1533 add r4,r4,r30
1533 bl .__mmu_off 1534 bl .__mmu_off
1534 b .__after_prom_start 1535 b .__after_prom_start
@@ -1548,7 +1549,7 @@ _STATIC(__boot_from_prom)
1548 /* put a relocation offset into r3 */ 1549 /* put a relocation offset into r3 */
1549 bl .reloc_offset 1550 bl .reloc_offset
1550 1551
1551 LOADADDR(r2,__toc_start) 1552 LOAD_REG_IMMEDIATE(r2,__toc_start)
1552 addi r2,r2,0x4000 1553 addi r2,r2,0x4000
1553 addi r2,r2,0x4000 1554 addi r2,r2,0x4000
1554 1555
@@ -1588,9 +1589,9 @@ _STATIC(__after_prom_start)
1588 */ 1589 */
1589 bl .reloc_offset 1590 bl .reloc_offset
1590 mr r26,r3 1591 mr r26,r3
1591 SET_REG_TO_CONST(r27,KERNELBASE) 1592 LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1592 1593
1593 LOADADDR(r3, PHYSICAL_START) /* target addr */ 1594 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */
1594 1595
1595 // XXX FIXME: Use phys returned by OF (r30) 1596 // XXX FIXME: Use phys returned by OF (r30)
1596 add r4,r27,r26 /* source addr */ 1597 add r4,r27,r26 /* source addr */
@@ -1598,7 +1599,7 @@ _STATIC(__after_prom_start)
1598 /* i.e. where we are running */ 1599 /* i.e. where we are running */
1599 /* the source addr */ 1600 /* the source addr */
1600 1601
1601 LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */ 1602 LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1602 sub r5,r5,r27 1603 sub r5,r5,r27
1603 1604
1604 li r6,0x100 /* Start offset, the first 0x100 */ 1605 li r6,0x100 /* Start offset, the first 0x100 */
@@ -1608,11 +1609,11 @@ _STATIC(__after_prom_start)
1608 /* this includes the code being */ 1609 /* this includes the code being */
1609 /* executed here. */ 1610 /* executed here. */
1610 1611
1611 LOADADDR(r0, 4f) /* Jump to the copy of this code */ 1612 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */
1612 mtctr r0 /* that we just made/relocated */ 1613 mtctr r0 /* that we just made/relocated */
1613 bctr 1614 bctr
1614 1615
16154: LOADADDR(r5,klimit) 16164: LOAD_REG_IMMEDIATE(r5,klimit)
1616 add r5,r5,r26 1617 add r5,r5,r26
1617 ld r5,0(r5) /* get the value of klimit */ 1618 ld r5,0(r5) /* get the value of klimit */
1618 sub r5,r5,r27 1619 sub r5,r5,r27
@@ -1694,7 +1695,7 @@ _GLOBAL(pmac_secondary_start)
1694 mtmsrd r3 /* RI on */ 1695 mtmsrd r3 /* RI on */
1695 1696
1696 /* Set up a paca value for this processor. */ 1697 /* Set up a paca value for this processor. */
1697 LOADADDR(r4, paca) /* Get base vaddr of paca array */ 1698 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */
1698 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ 1699 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1699 add r13,r13,r4 /* for this processor. */ 1700 add r13,r13,r4 /* for this processor. */
1700 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 1701 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
@@ -1731,7 +1732,7 @@ _GLOBAL(__secondary_start)
1731 bl .early_setup_secondary 1732 bl .early_setup_secondary
1732 1733
1733 /* Initialize the kernel stack. Just a repeat for iSeries. */ 1734 /* Initialize the kernel stack. Just a repeat for iSeries. */
1734 LOADADDR(r3,current_set) 1735 LOAD_REG_ADDR(r3, current_set)
1735 sldi r28,r24,3 /* get current_set[cpu#] */ 1736 sldi r28,r24,3 /* get current_set[cpu#] */
1736 ldx r1,r3,r28 1737 ldx r1,r3,r28
1737 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 1738 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
@@ -1742,8 +1743,8 @@ _GLOBAL(__secondary_start)
1742 mtlr r7 1743 mtlr r7
1743 1744
1744 /* enable MMU and jump to start_secondary */ 1745 /* enable MMU and jump to start_secondary */
1745 LOADADDR(r3,.start_secondary_prolog) 1746 LOAD_REG_ADDR(r3, .start_secondary_prolog)
1746 SET_REG_TO_CONST(r4, MSR_KERNEL) 1747 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1747#ifdef DO_SOFT_DISABLE 1748#ifdef DO_SOFT_DISABLE
1748 ori r4,r4,MSR_EE 1749 ori r4,r4,MSR_EE
1749#endif 1750#endif
@@ -1792,8 +1793,8 @@ _STATIC(start_here_multiplatform)
1792 * be detached from the kernel completely. Besides, we need 1793 * be detached from the kernel completely. Besides, we need
1793 * to clear it now for kexec-style entry. 1794 * to clear it now for kexec-style entry.
1794 */ 1795 */
1795 LOADADDR(r11,__bss_stop) 1796 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1796 LOADADDR(r8,__bss_start) 1797 LOAD_REG_IMMEDIATE(r8,__bss_start)
1797 sub r11,r11,r8 /* bss size */ 1798 sub r11,r11,r8 /* bss size */
1798 addi r11,r11,7 /* round up to an even double word */ 1799 addi r11,r11,7 /* round up to an even double word */
1799 rldicl. r11,r11,61,3 /* shift right by 3 */ 1800 rldicl. r11,r11,61,3 /* shift right by 3 */
@@ -1831,7 +1832,7 @@ _STATIC(start_here_multiplatform)
1831 /* up the htab. This is done because we have relocated the */ 1832 /* up the htab. This is done because we have relocated the */
1832 /* kernel but are still running in real mode. */ 1833 /* kernel but are still running in real mode. */
1833 1834
1834 LOADADDR(r3,init_thread_union) 1835 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1835 add r3,r3,r26 1836 add r3,r3,r26
1836 1837
1837 /* set up a stack pointer (physical address) */ 1838 /* set up a stack pointer (physical address) */
@@ -1840,14 +1841,14 @@ _STATIC(start_here_multiplatform)
1840 stdu r0,-STACK_FRAME_OVERHEAD(r1) 1841 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1841 1842
1842 /* set up the TOC (physical address) */ 1843 /* set up the TOC (physical address) */
1843 LOADADDR(r2,__toc_start) 1844 LOAD_REG_IMMEDIATE(r2,__toc_start)
1844 addi r2,r2,0x4000 1845 addi r2,r2,0x4000
1845 addi r2,r2,0x4000 1846 addi r2,r2,0x4000
1846 add r2,r2,r26 1847 add r2,r2,r26
1847 1848
1848 LOADADDR(r3,cpu_specs) 1849 LOAD_REG_IMMEDIATE(r3, cpu_specs)
1849 add r3,r3,r26 1850 add r3,r3,r26
1850 LOADADDR(r4,cur_cpu_spec) 1851 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
1851 add r4,r4,r26 1852 add r4,r4,r26
1852 mr r5,r26 1853 mr r5,r26
1853 bl .identify_cpu 1854 bl .identify_cpu
@@ -1863,11 +1864,11 @@ _STATIC(start_here_multiplatform)
1863 * nowhere it can be initialized differently before we reach this 1864 * nowhere it can be initialized differently before we reach this
1864 * code 1865 * code
1865 */ 1866 */
1866 LOADADDR(r27, boot_cpuid) 1867 LOAD_REG_IMMEDIATE(r27, boot_cpuid)
1867 add r27,r27,r26 1868 add r27,r27,r26
1868 lwz r27,0(r27) 1869 lwz r27,0(r27)
1869 1870
1870 LOADADDR(r24, paca) /* Get base vaddr of paca array */ 1871 LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */
1871 mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */ 1872 mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
1872 add r13,r13,r24 /* for this processor. */ 1873 add r13,r13,r24 /* for this processor. */
1873 add r13,r13,r26 /* convert to physical addr */ 1874 add r13,r13,r26 /* convert to physical addr */
@@ -1880,8 +1881,8 @@ _STATIC(start_here_multiplatform)
1880 mr r3,r31 1881 mr r3,r31
1881 bl .early_setup 1882 bl .early_setup
1882 1883
1883 LOADADDR(r3,.start_here_common) 1884 LOAD_REG_IMMEDIATE(r3, .start_here_common)
1884 SET_REG_TO_CONST(r4, MSR_KERNEL) 1885 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1885 mtspr SPRN_SRR0,r3 1886 mtspr SPRN_SRR0,r3
1886 mtspr SPRN_SRR1,r4 1887 mtspr SPRN_SRR1,r4
1887 rfid 1888 rfid
@@ -1895,7 +1896,7 @@ _STATIC(start_here_common)
1895 /* The following code sets up the SP and TOC now that we are */ 1896 /* The following code sets up the SP and TOC now that we are */
1896 /* running with translation enabled. */ 1897 /* running with translation enabled. */
1897 1898
1898 LOADADDR(r3,init_thread_union) 1899 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1899 1900
1900 /* set up the stack */ 1901 /* set up the stack */
1901 addi r1,r3,THREAD_SIZE 1902 addi r1,r3,THREAD_SIZE
@@ -1908,16 +1909,16 @@ _STATIC(start_here_common)
1908 li r3,0 1909 li r3,0
1909 bl .do_cpu_ftr_fixups 1910 bl .do_cpu_ftr_fixups
1910 1911
1911 LOADADDR(r26, boot_cpuid) 1912 LOAD_REG_IMMEDIATE(r26, boot_cpuid)
1912 lwz r26,0(r26) 1913 lwz r26,0(r26)
1913 1914
1914 LOADADDR(r24, paca) /* Get base vaddr of paca array */ 1915 LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */
1915 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */ 1916 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
1916 add r13,r13,r24 /* for this processor. */ 1917 add r13,r13,r24 /* for this processor. */
1917 mtspr SPRN_SPRG3,r13 1918 mtspr SPRN_SPRG3,r13
1918 1919
1919 /* ptr to current */ 1920 /* ptr to current */
1920 LOADADDR(r4,init_task) 1921 LOAD_REG_IMMEDIATE(r4, init_task)
1921 std r4,PACACURRENT(r13) 1922 std r4,PACACURRENT(r13)
1922 1923
1923 /* Load the TOC */ 1924 /* Load the TOC */
@@ -1940,7 +1941,7 @@ _STATIC(start_here_common)
1940 1941
1941_GLOBAL(hmt_init) 1942_GLOBAL(hmt_init)
1942#ifdef CONFIG_HMT 1943#ifdef CONFIG_HMT
1943 LOADADDR(r5, hmt_thread_data) 1944 LOAD_REG_IMMEDIATE(r5, hmt_thread_data)
1944 mfspr r7,SPRN_PVR 1945 mfspr r7,SPRN_PVR
1945 srwi r7,r7,16 1946 srwi r7,r7,16
1946 cmpwi r7,0x34 /* Pulsar */ 1947 cmpwi r7,0x34 /* Pulsar */
@@ -1961,7 +1962,7 @@ _GLOBAL(hmt_init)
1961 b 101f 1962 b 101f
1962 1963
1963__hmt_secondary_hold: 1964__hmt_secondary_hold:
1964 LOADADDR(r5, hmt_thread_data) 1965 LOAD_REG_IMMEDIATE(r5, hmt_thread_data)
1965 clrldi r5,r5,4 1966 clrldi r5,r5,4
1966 li r7,0 1967 li r7,0
1967 mfspr r6,SPRN_PIR 1968 mfspr r6,SPRN_PIR
@@ -1989,7 +1990,7 @@ __hmt_secondary_hold:
1989 1990
1990#ifdef CONFIG_HMT 1991#ifdef CONFIG_HMT
1991_GLOBAL(hmt_start_secondary) 1992_GLOBAL(hmt_start_secondary)
1992 LOADADDR(r4,__hmt_secondary_hold) 1993 LOAD_REG_IMMEDIATE(r4,__hmt_secondary_hold)
1993 clrldi r4,r4,4 1994 clrldi r4,r4,4
1994 mtspr SPRN_NIADORM, r4 1995 mtspr SPRN_NIADORM, r4
1995 mfspr r4, SPRN_MSRDORM 1996 mfspr r4, SPRN_MSRDORM
diff --git a/arch/powerpc/kernel/idle_power4.S b/arch/powerpc/kernel/idle_power4.S
index 1494e2f177f7..c16b4afab582 100644
--- a/arch/powerpc/kernel/idle_power4.S
+++ b/arch/powerpc/kernel/idle_power4.S
@@ -38,14 +38,14 @@ END_FTR_SECTION_IFCLR(CPU_FTR_CAN_NAP)
38 /* We must dynamically check for the NAP feature as it 38 /* We must dynamically check for the NAP feature as it
39 * can be cleared by CPU init after the fixups are done 39 * can be cleared by CPU init after the fixups are done
40 */ 40 */
41 LOADBASE(r3,cur_cpu_spec) 41 LOAD_REG_ADDRBASE(r3,cur_cpu_spec)
42 ld r4,OFF(cur_cpu_spec)(r3) 42 ld r4,ADDROFF(cur_cpu_spec)(r3)
43 ld r4,CPU_SPEC_FEATURES(r4) 43 ld r4,CPU_SPEC_FEATURES(r4)
44 andi. r0,r4,CPU_FTR_CAN_NAP 44 andi. r0,r4,CPU_FTR_CAN_NAP
45 beqlr 45 beqlr
46 /* Now check if user or arch enabled NAP mode */ 46 /* Now check if user or arch enabled NAP mode */
47 LOADBASE(r3,powersave_nap) 47 LOAD_REG_ADDRBASE(r3,powersave_nap)
48 lwz r4,OFF(powersave_nap)(r3) 48 lwz r4,ADDROFF(powersave_nap)(r3)
49 cmpwi 0,r4,0 49 cmpwi 0,r4,0
50 beqlr 50 beqlr
51 51
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 01d0d97a16e1..be982023409e 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -68,7 +68,7 @@ _GLOBAL(reloc_offset)
68 mflr r0 68 mflr r0
69 bl 1f 69 bl 1f
701: mflr r3 701: mflr r3
71 LOADADDR(r4,1b) 71 LOAD_REG_IMMEDIATE(r4,1b)
72 subf r3,r4,r3 72 subf r3,r4,r3
73 mtlr r0 73 mtlr r0
74 blr 74 blr
@@ -80,7 +80,7 @@ _GLOBAL(add_reloc_offset)
80 mflr r0 80 mflr r0
81 bl 1f 81 bl 1f
821: mflr r5 821: mflr r5
83 LOADADDR(r4,1b) 83 LOAD_REG_IMMEDIATE(r4,1b)
84 subf r5,r4,r5 84 subf r5,r4,r5
85 add r3,r3,r5 85 add r3,r3,r5
86 mtlr r0 86 mtlr r0
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index ae48a002f81a..2778cce058e2 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -39,7 +39,7 @@ _GLOBAL(reloc_offset)
39 mflr r0 39 mflr r0
40 bl 1f 40 bl 1f
411: mflr r3 411: mflr r3
42 LOADADDR(r4,1b) 42 LOAD_REG_IMMEDIATE(r4,1b)
43 subf r3,r4,r3 43 subf r3,r4,r3
44 mtlr r0 44 mtlr r0
45 blr 45 blr
@@ -51,7 +51,7 @@ _GLOBAL(add_reloc_offset)
51 mflr r0 51 mflr r0
52 bl 1f 52 bl 1f
531: mflr r5 531: mflr r5
54 LOADADDR(r4,1b) 54 LOAD_REG_IMMEDIATE(r4,1b)
55 subf r5,r4,r5 55 subf r5,r4,r5
56 add r3,r3,r5 56 add r3,r3,r5
57 mtlr r0 57 mtlr r0
@@ -498,15 +498,15 @@ _GLOBAL(identify_cpu)
498 */ 498 */
499_GLOBAL(do_cpu_ftr_fixups) 499_GLOBAL(do_cpu_ftr_fixups)
500 /* Get CPU 0 features */ 500 /* Get CPU 0 features */
501 LOADADDR(r6,cur_cpu_spec) 501 LOAD_REG_IMMEDIATE(r6,cur_cpu_spec)
502 sub r6,r6,r3 502 sub r6,r6,r3
503 ld r4,0(r6) 503 ld r4,0(r6)
504 sub r4,r4,r3 504 sub r4,r4,r3
505 ld r4,CPU_SPEC_FEATURES(r4) 505 ld r4,CPU_SPEC_FEATURES(r4)
506 /* Get the fixup table */ 506 /* Get the fixup table */
507 LOADADDR(r6,__start___ftr_fixup) 507 LOAD_REG_IMMEDIATE(r6,__start___ftr_fixup)
508 sub r6,r6,r3 508 sub r6,r6,r3
509 LOADADDR(r7,__stop___ftr_fixup) 509 LOAD_REG_IMMEDIATE(r7,__stop___ftr_fixup)
510 sub r7,r7,r3 510 sub r7,r7,r3
511 /* Do the fixup */ 511 /* Do the fixup */
5121: cmpld r6,r7 5121: cmpld r6,r7
diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h
index 0dc798d46ea4..ab8688d39024 100644
--- a/include/asm-powerpc/ppc_asm.h
+++ b/include/asm-powerpc/ppc_asm.h
@@ -156,52 +156,56 @@ n:
156#endif 156#endif
157 157
158/* 158/*
159 * LOADADDR( rn, name ) 159 * LOAD_REG_IMMEDIATE(rn, expr)
160 * loads the address of 'name' into 'rn' 160 * Loads the value of the constant expression 'expr' into register 'rn'
161 * using immediate instructions only. Use this when it's important not
162 * to reference other data (i.e. on ppc64 when the TOC pointer is not
163 * valid).
161 * 164 *
162 * LOADBASE( rn, name ) 165 * LOAD_REG_ADDR(rn, name)
163 * loads the address (possibly without the low 16 bits) of 'name' into 'rn' 166 * Loads the address of label 'name' into register 'rn'. Use this when
164 * suitable for base+disp addressing 167 * you don't particularly need immediate instructions only, but you need
168 * the whole address in one register (e.g. it's a structure address and
169 * you want to access various offsets within it). On ppc32 this is
170 * identical to LOAD_REG_IMMEDIATE.
171 *
172 * LOAD_REG_ADDRBASE(rn, name)
173 * ADDROFF(name)
174 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
175 * register 'rn'. ADDROFF(name) returns the remainder of the address as
176 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
177 * in size, so is suitable for use directly as an offset in load and store
178 * instructions. Use this when loading/storing a single word or less as:
179 * LOAD_REG_ADDRBASE(rX, name)
180 * ld rY,ADDROFF(name)(rX)
165 */ 181 */
166#ifdef __powerpc64__ 182#ifdef __powerpc64__
167#define LOADADDR(rn,name) \ 183#define LOAD_REG_IMMEDIATE(reg,expr) \
168 lis rn,name##@highest; \ 184 lis (reg),(expr)@highest; \
169 ori rn,rn,name##@higher; \ 185 ori (reg),(reg),(expr)@higher; \
170 rldicr rn,rn,32,31; \ 186 rldicr (reg),(reg),32,31; \
171 oris rn,rn,name##@h; \ 187 oris (reg),(reg),(expr)@h; \
172 ori rn,rn,name##@l 188 ori (reg),(reg),(expr)@l;
173 189
174#define LOADBASE(rn,name) \ 190#define LOAD_REG_ADDR(reg,name) \
175 ld rn,name@got(r2) 191 ld (reg),name@got(r2)
176 192
177#define OFF(name) 0 193#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
178 194#define ADDROFF(name) 0
179#define SET_REG_TO_CONST(reg, value) \
180 lis reg,(((value)>>48)&0xFFFF); \
181 ori reg,reg,(((value)>>32)&0xFFFF); \
182 rldicr reg,reg,32,31; \
183 oris reg,reg,(((value)>>16)&0xFFFF); \
184 ori reg,reg,((value)&0xFFFF);
185
186#define SET_REG_TO_LABEL(reg, label) \
187 lis reg,(label)@highest; \
188 ori reg,reg,(label)@higher; \
189 rldicr reg,reg,32,31; \
190 oris reg,reg,(label)@h; \
191 ori reg,reg,(label)@l;
192 195
193/* offsets for stack frame layout */ 196/* offsets for stack frame layout */
194#define LRSAVE 16 197#define LRSAVE 16
195 198
196#else /* 32-bit */ 199#else /* 32-bit */
197#define LOADADDR(rn,name) \
198 lis rn,name@ha; \
199 addi rn,rn,name@l
200 200
201#define LOADBASE(rn,name) \ 201#define LOAD_REG_IMMEDIATE(reg,expr) \
202 lis rn,name@ha 202 lis (reg),(expr)@ha; \
203 addi (reg),(reg),(expr)@l;
204
205#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
203 206
204#define OFF(name) name@l 207#define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha
208#define ADDROFF(name) name@l
205 209
206/* offsets for stack frame layout */ 210/* offsets for stack frame layout */
207#define LRSAVE 4 211#define LRSAVE 4