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authorDouglas Leung <douglas@mips.com>2012-07-19 03:11:13 -0400
committerRalf Baechle <ralf@linux-mips.org>2012-07-19 05:23:43 -0400
commitdc34b05fea0cc9a869863b929f37f1e8ce30edf4 (patch)
treead064e7dcf5235d8c51060ed0c8db167c5490bd3
parentc022630633624a75b3b58f43dd3c6cc896a56cff (diff)
MIPS: Fix decoding of c0_config1 for MIPSxx caches with 32 ways per set.
This affects certain 4Kc cores. Signed-off-by: Douglas Leung <douglas@mips.com> Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3855/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/mm/c-r4k.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index e56efd059189..f092c265dc63 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void)
977 c->icache.linesz = 2 << lsize; 977 c->icache.linesz = 2 << lsize;
978 else 978 else
979 c->icache.linesz = lsize; 979 c->icache.linesz = lsize;
980 c->icache.sets = 64 << ((config1 >> 22) & 7); 980 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
981 c->icache.ways = 1 + ((config1 >> 16) & 7); 981 c->icache.ways = 1 + ((config1 >> 16) & 7);
982 982
983 icache_size = c->icache.sets * 983 icache_size = c->icache.sets *
@@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void)
997 c->dcache.linesz = 2 << lsize; 997 c->dcache.linesz = 2 << lsize;
998 else 998 else
999 c->dcache.linesz= lsize; 999 c->dcache.linesz= lsize;
1000 c->dcache.sets = 64 << ((config1 >> 13) & 7); 1000 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1001 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1001 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1002 1002
1003 dcache_size = c->dcache.sets * 1003 dcache_size = c->dcache.sets *