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authorMauro Carvalho Chehab <mchehab@redhat.com>2011-07-09 08:50:21 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2011-07-27 16:55:48 -0400
commit5e66b87840dd275eafa6b4135b174212dd7c0d75 (patch)
tree795296039bc6419bed9cb6bd9e7b1a44f58e1f78
parent2da6750117c8fc4772a9c980e14a8d5d67f504a4 (diff)
[media] drxk: remove _0 from read/write routines
The normal 16-bits read routine is called as "Read16_0". This is due to a flags that could optionally be passed. Yet, on no places at the code, a flag is passed there. The same happens with 16-bits write and 32-read/write routines, and with WriteBlock. Also, using flags, is an exception: there's no place currently using flags, except for an #ifdef at WriteBlock. Rename the function as just "read16", and the one that requires flags, as "read16_flags". This helps to see where the flags are used, and also avoid using CamelCase on Kernel. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat
-rw-r--r--drivers/media/dvb/frontends/drxk_hard.c1313
1 files changed, 662 insertions, 651 deletions
diff --git a/drivers/media/dvb/frontends/drxk_hard.c b/drivers/media/dvb/frontends/drxk_hard.c
index fe9445922942..8b2e06ea5c08 100644
--- a/drivers/media/dvb/frontends/drxk_hard.c
+++ b/drivers/media/dvb/frontends/drxk_hard.c
@@ -372,7 +372,7 @@ static int i2c_read(struct i2c_adapter *adap,
372 return 0; 372 return 0;
373} 373}
374 374
375static int Read16(struct drxk_state *state, u32 reg, u16 *data, u8 flags) 375static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
376{ 376{
377 u8 adr = state->demod_address, mm1[4], mm2[2], len; 377 u8 adr = state->demod_address, mm1[4], mm2[2], len;
378#ifdef I2C_LONG_ADR 378#ifdef I2C_LONG_ADR
@@ -398,12 +398,12 @@ static int Read16(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
398 return 0; 398 return 0;
399} 399}
400 400
401static int Read16_0(struct drxk_state *state, u32 reg, u16 *data) 401static int read16(struct drxk_state *state, u32 reg, u16 *data)
402{ 402{
403 return Read16(state, reg, data, 0); 403 return read16_flags(state, reg, data, 0);
404} 404}
405 405
406static int Read32(struct drxk_state *state, u32 reg, u32 *data, u8 flags) 406static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
407{ 407{
408 u8 adr = state->demod_address, mm1[4], mm2[4], len; 408 u8 adr = state->demod_address, mm1[4], mm2[4], len;
409#ifdef I2C_LONG_ADR 409#ifdef I2C_LONG_ADR
@@ -430,7 +430,12 @@ static int Read32(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
430 return 0; 430 return 0;
431} 431}
432 432
433static int Write16(struct drxk_state *state, u32 reg, u16 data, u8 flags) 433static int read32(struct drxk_state *state, u32 reg, u32 *data)
434{
435 return read32_flags(state, reg, data, 0);
436}
437
438static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
434{ 439{
435 u8 adr = state->demod_address, mm[6], len; 440 u8 adr = state->demod_address, mm[6], len;
436#ifdef I2C_LONG_ADR 441#ifdef I2C_LONG_ADR
@@ -456,12 +461,12 @@ static int Write16(struct drxk_state *state, u32 reg, u16 data, u8 flags)
456 return 0; 461 return 0;
457} 462}
458 463
459static int Write16_0(struct drxk_state *state, u32 reg, u16 data) 464static int write16(struct drxk_state *state, u32 reg, u16 data)
460{ 465{
461 return Write16(state, reg, data, 0); 466 return write16_flags(state, reg, data, 0);
462} 467}
463 468
464static int Write32(struct drxk_state *state, u32 reg, u32 data, u8 flags) 469static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
465{ 470{
466 u8 adr = state->demod_address, mm[8], len; 471 u8 adr = state->demod_address, mm[8], len;
467#ifdef I2C_LONG_ADR 472#ifdef I2C_LONG_ADR
@@ -488,10 +493,16 @@ static int Write32(struct drxk_state *state, u32 reg, u32 data, u8 flags)
488 return 0; 493 return 0;
489} 494}
490 495
491static int WriteBlock(struct drxk_state *state, u32 Address, 496static int write32(struct drxk_state *state, u32 reg, u32 data)
492 const int BlockSize, const u8 pBlock[], u8 Flags) 497{
498 return write32_flags(state, reg, data, 0);
499}
500
501static int write_block(struct drxk_state *state, u32 Address,
502 const int BlockSize, const u8 pBlock[])
493{ 503{
494 int status = 0, BlkSize = BlockSize; 504 int status = 0, BlkSize = BlockSize;
505 u8 Flags = 0;
495#ifdef I2C_LONG_ADR 506#ifdef I2C_LONG_ADR
496 Flags |= 0xC0; 507 Flags |= 0xC0;
497#endif 508#endif
@@ -567,14 +578,14 @@ int PowerUpDevice(struct drxk_state *state)
567 return -1; 578 return -1;
568 do { 579 do {
569 /* Make sure all clk domains are active */ 580 /* Make sure all clk domains are active */
570 status = Write16_0(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE); 581 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
571 if (status < 0) 582 if (status < 0)
572 break; 583 break;
573 status = Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 584 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
574 if (status < 0) 585 if (status < 0)
575 break; 586 break;
576 /* Enable pll lock tests */ 587 /* Enable pll lock tests */
577 status = Write16_0(state, SIO_CC_PLL_LOCK__A, 1); 588 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
578 if (status < 0) 589 if (status < 0)
579 break; 590 break;
580 state->m_currentPowerMode = DRX_POWER_UP; 591 state->m_currentPowerMode = DRX_POWER_UP;
@@ -850,23 +861,23 @@ static int DRXX_Open(struct drxk_state *state)
850 dprintk(1, "\n"); 861 dprintk(1, "\n");
851 do { 862 do {
852 /* stop lock indicator process */ 863 /* stop lock indicator process */
853 status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 864 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
854 if (status < 0) 865 if (status < 0)
855 break; 866 break;
856 /* Check device id */ 867 /* Check device id */
857 status = Read16(state, SIO_TOP_COMM_KEY__A, &key, 0); 868 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
858 if (status < 0) 869 if (status < 0)
859 break; 870 break;
860 status = Write16_0(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 871 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
861 if (status < 0) 872 if (status < 0)
862 break; 873 break;
863 status = Read32(state, SIO_TOP_JTAGID_LO__A, &jtag, 0); 874 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
864 if (status < 0) 875 if (status < 0)
865 break; 876 break;
866 status = Read16(state, SIO_PDR_UIO_IN_HI__A, &bid, 0); 877 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
867 if (status < 0) 878 if (status < 0)
868 break; 879 break;
869 status = Write16_0(state, SIO_TOP_COMM_KEY__A, key); 880 status = write16(state, SIO_TOP_COMM_KEY__A, key);
870 if (status < 0) 881 if (status < 0)
871 break; 882 break;
872 } while (0); 883 } while (0);
@@ -883,17 +894,17 @@ static int GetDeviceCapabilities(struct drxk_state *state)
883 do { 894 do {
884 /* driver 0.9.0 */ 895 /* driver 0.9.0 */
885 /* stop lock indicator process */ 896 /* stop lock indicator process */
886 status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 897 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
887 if (status < 0) 898 if (status < 0)
888 break; 899 break;
889 900
890 status = Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA); 901 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
891 if (status < 0) 902 if (status < 0)
892 break; 903 break;
893 status = Read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg, 0); 904 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
894 if (status < 0) 905 if (status < 0)
895 break; 906 break;
896 status = Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000); 907 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
897 if (status < 0) 908 if (status < 0)
898 break; 909 break;
899 910
@@ -920,7 +931,7 @@ static int GetDeviceCapabilities(struct drxk_state *state)
920 Determine device capabilities 931 Determine device capabilities
921 Based on pinning v14 932 Based on pinning v14
922 */ 933 */
923 status = Read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo, 0); 934 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
924 if (status < 0) 935 if (status < 0)
925 break; 936 break;
926 /* driver 0.9.0 */ 937 /* driver 0.9.0 */
@@ -1062,7 +1073,7 @@ static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1062 dprintk(1, "\n"); 1073 dprintk(1, "\n");
1063 1074
1064 /* Write command */ 1075 /* Write command */
1065 status = Write16_0(state, SIO_HI_RA_RAM_CMD__A, cmd); 1076 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1066 if (status < 0) 1077 if (status < 0)
1067 return status; 1078 return status;
1068 if (cmd == SIO_HI_RA_RAM_CMD_RESET) 1079 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
@@ -1081,14 +1092,14 @@ static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1081 do { 1092 do {
1082 msleep(1); 1093 msleep(1);
1083 retryCount += 1; 1094 retryCount += 1;
1084 status = Read16(state, SIO_HI_RA_RAM_CMD__A, 1095 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1085 &waitCmd, 0); 1096 &waitCmd);
1086 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES) 1097 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1087 && (waitCmd != 0)); 1098 && (waitCmd != 0));
1088 1099
1089 if (status == 0) 1100 if (status == 0)
1090 status = Read16(state, SIO_HI_RA_RAM_RES__A, 1101 status = read16(state, SIO_HI_RA_RAM_RES__A,
1091 pResult, 0); 1102 pResult);
1092 } 1103 }
1093 return status; 1104 return status;
1094} 1105}
@@ -1101,22 +1112,22 @@ static int HI_CfgCommand(struct drxk_state *state)
1101 1112
1102 mutex_lock(&state->mutex); 1113 mutex_lock(&state->mutex);
1103 do { 1114 do {
1104 status = Write16_0(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout); 1115 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1105 if (status < 0) 1116 if (status < 0)
1106 break; 1117 break;
1107 status = Write16_0(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl); 1118 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1108 if (status < 0) 1119 if (status < 0)
1109 break; 1120 break;
1110 status = Write16_0(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey); 1121 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1111 if (status < 0) 1122 if (status < 0)
1112 break; 1123 break;
1113 status = Write16_0(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay); 1124 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1114 if (status < 0) 1125 if (status < 0)
1115 break; 1126 break;
1116 status = Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv); 1127 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1117 if (status < 0) 1128 if (status < 0)
1118 break; 1129 break;
1119 status = Write16_0(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); 1130 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1120 if (status < 0) 1131 if (status < 0)
1121 break; 1132 break;
1122 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0); 1133 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
@@ -1149,51 +1160,51 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1149 dprintk(1, "\n"); 1160 dprintk(1, "\n");
1150 do { 1161 do {
1151 /* stop lock indicator process */ 1162 /* stop lock indicator process */
1152 status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 1163 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1153 if (status < 0) 1164 if (status < 0)
1154 break; 1165 break;
1155 1166
1156 /* MPEG TS pad configuration */ 1167 /* MPEG TS pad configuration */
1157 status = Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA); 1168 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
1158 if (status < 0) 1169 if (status < 0)
1159 break; 1170 break;
1160 1171
1161 if (mpegEnable == false) { 1172 if (mpegEnable == false) {
1162 /* Set MPEG TS pads to inputmode */ 1173 /* Set MPEG TS pads to inputmode */
1163 status = Write16_0(state, SIO_PDR_MSTRT_CFG__A, 0x0000); 1174 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1164 if (status < 0) 1175 if (status < 0)
1165 break; 1176 break;
1166 status = Write16_0(state, SIO_PDR_MERR_CFG__A, 0x0000); 1177 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1167 if (status < 0) 1178 if (status < 0)
1168 break; 1179 break;
1169 status = Write16_0(state, SIO_PDR_MCLK_CFG__A, 0x0000); 1180 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1170 if (status < 0) 1181 if (status < 0)
1171 break; 1182 break;
1172 status = Write16_0(state, SIO_PDR_MVAL_CFG__A, 0x0000); 1183 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1173 if (status < 0) 1184 if (status < 0)
1174 break; 1185 break;
1175 status = Write16_0(state, SIO_PDR_MD0_CFG__A, 0x0000); 1186 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1176 if (status < 0) 1187 if (status < 0)
1177 break; 1188 break;
1178 status = Write16_0(state, SIO_PDR_MD1_CFG__A, 0x0000); 1189 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1179 if (status < 0) 1190 if (status < 0)
1180 break; 1191 break;
1181 status = Write16_0(state, SIO_PDR_MD2_CFG__A, 0x0000); 1192 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1182 if (status < 0) 1193 if (status < 0)
1183 break; 1194 break;
1184 status = Write16_0(state, SIO_PDR_MD3_CFG__A, 0x0000); 1195 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1185 if (status < 0) 1196 if (status < 0)
1186 break; 1197 break;
1187 status = Write16_0(state, SIO_PDR_MD4_CFG__A, 0x0000); 1198 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1188 if (status < 0) 1199 if (status < 0)
1189 break; 1200 break;
1190 status = Write16_0(state, SIO_PDR_MD5_CFG__A, 0x0000); 1201 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1191 if (status < 0) 1202 if (status < 0)
1192 break; 1203 break;
1193 status = Write16_0(state, SIO_PDR_MD6_CFG__A, 0x0000); 1204 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1194 if (status < 0) 1205 if (status < 0)
1195 break; 1206 break;
1196 status = Write16_0(state, SIO_PDR_MD7_CFG__A, 0x0000); 1207 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1197 if (status < 0) 1208 if (status < 0)
1198 break; 1209 break;
1199 } else { 1210 } else {
@@ -1205,36 +1216,36 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1205 SIO_PDR_MCLK_CFG_DRIVE__B) | 1216 SIO_PDR_MCLK_CFG_DRIVE__B) |
1206 0x0003); 1217 0x0003);
1207 1218
1208 status = Write16_0(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg); 1219 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1209 if (status < 0) 1220 if (status < 0)
1210 break; 1221 break;
1211 status = Write16_0(state, SIO_PDR_MERR_CFG__A, 0x0000); /* Disable */ 1222 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); /* Disable */
1212 if (status < 0) 1223 if (status < 0)
1213 break; 1224 break;
1214 status = Write16_0(state, SIO_PDR_MVAL_CFG__A, 0x0000); /* Disable */ 1225 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); /* Disable */
1215 if (status < 0) 1226 if (status < 0)
1216 break; 1227 break;
1217 if (state->m_enableParallel == true) { 1228 if (state->m_enableParallel == true) {
1218 /* paralel -> enable MD1 to MD7 */ 1229 /* paralel -> enable MD1 to MD7 */
1219 status = Write16_0(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg); 1230 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1220 if (status < 0) 1231 if (status < 0)
1221 break; 1232 break;
1222 status = Write16_0(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg); 1233 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1223 if (status < 0) 1234 if (status < 0)
1224 break; 1235 break;
1225 status = Write16_0(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg); 1236 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1226 if (status < 0) 1237 if (status < 0)
1227 break; 1238 break;
1228 status = Write16_0(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg); 1239 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1229 if (status < 0) 1240 if (status < 0)
1230 break; 1241 break;
1231 status = Write16_0(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg); 1242 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1232 if (status < 0) 1243 if (status < 0)
1233 break; 1244 break;
1234 status = Write16_0(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg); 1245 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1235 if (status < 0) 1246 if (status < 0)
1236 break; 1247 break;
1237 status = Write16_0(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg); 1248 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1238 if (status < 0) 1249 if (status < 0)
1239 break; 1250 break;
1240 } else { 1251 } else {
@@ -1242,41 +1253,41 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1242 SIO_PDR_MD0_CFG_DRIVE__B) 1253 SIO_PDR_MD0_CFG_DRIVE__B)
1243 | 0x0003); 1254 | 0x0003);
1244 /* serial -> disable MD1 to MD7 */ 1255 /* serial -> disable MD1 to MD7 */
1245 status = Write16_0(state, SIO_PDR_MD1_CFG__A, 0x0000); 1256 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1246 if (status < 0) 1257 if (status < 0)
1247 break; 1258 break;
1248 status = Write16_0(state, SIO_PDR_MD2_CFG__A, 0x0000); 1259 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1249 if (status < 0) 1260 if (status < 0)
1250 break; 1261 break;
1251 status = Write16_0(state, SIO_PDR_MD3_CFG__A, 0x0000); 1262 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1252 if (status < 0) 1263 if (status < 0)
1253 break; 1264 break;
1254 status = Write16_0(state, SIO_PDR_MD4_CFG__A, 0x0000); 1265 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1255 if (status < 0) 1266 if (status < 0)
1256 break; 1267 break;
1257 status = Write16_0(state, SIO_PDR_MD5_CFG__A, 0x0000); 1268 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1258 if (status < 0) 1269 if (status < 0)
1259 break; 1270 break;
1260 status = Write16_0(state, SIO_PDR_MD6_CFG__A, 0x0000); 1271 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1261 if (status < 0) 1272 if (status < 0)
1262 break; 1273 break;
1263 status = Write16_0(state, SIO_PDR_MD7_CFG__A, 0x0000); 1274 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1264 if (status < 0) 1275 if (status < 0)
1265 break; 1276 break;
1266 } 1277 }
1267 status = Write16_0(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg); 1278 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1268 if (status < 0) 1279 if (status < 0)
1269 break; 1280 break;
1270 status = Write16_0(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg); 1281 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1271 if (status < 0) 1282 if (status < 0)
1272 break; 1283 break;
1273 } 1284 }
1274 /* Enable MB output over MPEG pads and ctl input */ 1285 /* Enable MB output over MPEG pads and ctl input */
1275 status = Write16_0(state, SIO_PDR_MON_CFG__A, 0x0000); 1286 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1276 if (status < 0) 1287 if (status < 0)
1277 break; 1288 break;
1278 /* Write nomagic word to enable pdr reg write */ 1289 /* Write nomagic word to enable pdr reg write */
1279 status = Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000); 1290 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1280 if (status < 0) 1291 if (status < 0)
1281 break; 1292 break;
1282 } while (0); 1293 } while (0);
@@ -1301,23 +1312,23 @@ static int BLChainCmd(struct drxk_state *state,
1301 1312
1302 mutex_lock(&state->mutex); 1313 mutex_lock(&state->mutex);
1303 do { 1314 do {
1304 status = Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); 1315 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1305 if (status < 0) 1316 if (status < 0)
1306 break; 1317 break;
1307 status = Write16_0(state, SIO_BL_CHAIN_ADDR__A, romOffset); 1318 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1308 if (status < 0) 1319 if (status < 0)
1309 break; 1320 break;
1310 status = Write16_0(state, SIO_BL_CHAIN_LEN__A, nrOfElements); 1321 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1311 if (status < 0) 1322 if (status < 0)
1312 break; 1323 break;
1313 status = Write16_0(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); 1324 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1314 if (status < 0) 1325 if (status < 0)
1315 break; 1326 break;
1316 end = jiffies + msecs_to_jiffies(timeOut); 1327 end = jiffies + msecs_to_jiffies(timeOut);
1317 1328
1318 do { 1329 do {
1319 msleep(1); 1330 msleep(1);
1320 status = Read16(state, SIO_BL_STATUS__A, &blStatus, 0); 1331 status = read16(state, SIO_BL_STATUS__A, &blStatus);
1321 if (status < 0) 1332 if (status < 0)
1322 break; 1333 break;
1323 } while ((blStatus == 0x1) && 1334 } while ((blStatus == 0x1) &&
@@ -1374,7 +1385,7 @@ static int DownloadMicrocode(struct drxk_state *state,
1374 BlockCRC = (pSrc[0] << 8) | pSrc[1]; 1385 BlockCRC = (pSrc[0] << 8) | pSrc[1];
1375 pSrc += sizeof(u16); 1386 pSrc += sizeof(u16);
1376 offset += sizeof(u16); 1387 offset += sizeof(u16);
1377 status = WriteBlock(state, Address, BlockSize, pSrc, 0); 1388 status = write_block(state, Address, BlockSize, pSrc);
1378 if (status < 0) 1389 if (status < 0)
1379 break; 1390 break;
1380 pSrc += BlockSize; 1391 pSrc += BlockSize;
@@ -1398,7 +1409,7 @@ static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1398 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; 1409 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1399 } 1410 }
1400 1411
1401 status = (Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); 1412 status = (read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data));
1402 1413
1403 if (data == desiredStatus) { 1414 if (data == desiredStatus) {
1404 /* tokenring already has correct status */ 1415 /* tokenring already has correct status */
@@ -1406,11 +1417,11 @@ static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1406 } 1417 }
1407 /* Disable/enable dvbt tokenring bridge */ 1418 /* Disable/enable dvbt tokenring bridge */
1408 status = 1419 status =
1409 Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl); 1420 write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1410 1421
1411 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); 1422 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1412 do { 1423 do {
1413 status = Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); 1424 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1414 if (status < 0) 1425 if (status < 0)
1415 break; 1426 break;
1416 } while ((data != desiredStatus) && ((time_is_after_jiffies(end)))); 1427 } while ((data != desiredStatus) && ((time_is_after_jiffies(end))));
@@ -1431,20 +1442,20 @@ static int MPEGTSStop(struct drxk_state *state)
1431 1442
1432 do { 1443 do {
1433 /* Gracefull shutdown (byte boundaries) */ 1444 /* Gracefull shutdown (byte boundaries) */
1434 status = Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); 1445 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1435 if (status < 0) 1446 if (status < 0)
1436 break; 1447 break;
1437 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M; 1448 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1438 status = Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode); 1449 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1439 if (status < 0) 1450 if (status < 0)
1440 break; 1451 break;
1441 1452
1442 /* Suppress MCLK during absence of data */ 1453 /* Suppress MCLK during absence of data */
1443 status = Read16_0(state, FEC_OC_IPR_MODE__A, &fecOcIprMode); 1454 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1444 if (status < 0) 1455 if (status < 0)
1445 break; 1456 break;
1446 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; 1457 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1447 status = Write16_0(state, FEC_OC_IPR_MODE__A, fecOcIprMode); 1458 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1448 if (status < 0) 1459 if (status < 0)
1449 break; 1460 break;
1450 } while (0); 1461 } while (0);
@@ -1482,13 +1493,13 @@ static int scu_command(struct drxk_state *state,
1482 buffer[cnt++] = (cmd & 0xFF); 1493 buffer[cnt++] = (cmd & 0xFF);
1483 buffer[cnt++] = ((cmd >> 8) & 0xFF); 1494 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1484 1495
1485 WriteBlock(state, SCU_RAM_PARAM_0__A - 1496 write_block(state, SCU_RAM_PARAM_0__A -
1486 (parameterLen - 1), cnt, buffer, 0x00); 1497 (parameterLen - 1), cnt, buffer);
1487 /* Wait until SCU has processed command */ 1498 /* Wait until SCU has processed command */
1488 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME); 1499 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1489 do { 1500 do {
1490 msleep(1); 1501 msleep(1);
1491 status = Read16_0(state, SCU_RAM_COMMAND__A, &curCmd); 1502 status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1492 if (status < 0) 1503 if (status < 0)
1493 break; 1504 break;
1494 } while (!(curCmd == DRX_SCU_READY) 1505 } while (!(curCmd == DRX_SCU_READY)
@@ -1504,7 +1515,7 @@ static int scu_command(struct drxk_state *state,
1504 int ii; 1515 int ii;
1505 1516
1506 for (ii = resultLen - 1; ii >= 0; ii -= 1) { 1517 for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1507 status = Read16_0(state, SCU_RAM_PARAM_0__A - ii, &result[ii]); 1518 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1508 if (status < 0) 1519 if (status < 0)
1509 break; 1520 break;
1510 } 1521 }
@@ -1547,7 +1558,7 @@ static int SetIqmAf(struct drxk_state *state, bool active)
1547 1558
1548 do { 1559 do {
1549 /* Configure IQM */ 1560 /* Configure IQM */
1550 status = Read16_0(state, IQM_AF_STDBY__A, &data); 1561 status = read16(state, IQM_AF_STDBY__A, &data);
1551 if (status < 0) 1562 if (status < 0)
1552 break; 1563 break;
1553 if (!active) { 1564 if (!active) {
@@ -1565,7 +1576,7 @@ static int SetIqmAf(struct drxk_state *state, bool active)
1565 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) 1576 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1566 ); 1577 );
1567 } 1578 }
1568 status = Write16_0(state, IQM_AF_STDBY__A, data); 1579 status = write16(state, IQM_AF_STDBY__A, data);
1569 if (status < 0) 1580 if (status < 0)
1570 break; 1581 break;
1571 } while (0); 1582 } while (0);
@@ -1658,10 +1669,10 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1658 status = DVBTEnableOFDMTokenRing(state, false); 1669 status = DVBTEnableOFDMTokenRing(state, false);
1659 if (status < 0) 1670 if (status < 0)
1660 break; 1671 break;
1661 status = Write16_0(state, SIO_CC_PWD_MODE__A, sioCcPwdMode); 1672 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1662 if (status < 0) 1673 if (status < 0)
1663 break; 1674 break;
1664 status = Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 1675 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1665 if (status < 0) 1676 if (status < 0)
1666 break; 1677 break;
1667 1678
@@ -1688,7 +1699,7 @@ static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1688 dprintk(1, "\n"); 1699 dprintk(1, "\n");
1689 1700
1690 do { 1701 do {
1691 status = Read16_0(state, SCU_COMM_EXEC__A, &data); 1702 status = read16(state, SCU_COMM_EXEC__A, &data);
1692 if (status < 0) 1703 if (status < 0)
1693 break; 1704 break;
1694 if (data == SCU_COMM_EXEC_ACTIVE) { 1705 if (data == SCU_COMM_EXEC_ACTIVE) {
@@ -1703,13 +1714,13 @@ static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1703 } 1714 }
1704 1715
1705 /* Reset datapath for OFDM, processors first */ 1716 /* Reset datapath for OFDM, processors first */
1706 status = Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); 1717 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1707 if (status < 0) 1718 if (status < 0)
1708 break; 1719 break;
1709 status = Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); 1720 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1710 if (status < 0) 1721 if (status < 0)
1711 break; 1722 break;
1712 status = Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); 1723 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1713 if (status < 0) 1724 if (status < 0)
1714 break; 1725 break;
1715 1726
@@ -1741,7 +1752,7 @@ static int SetOperationMode(struct drxk_state *state,
1741 */ 1752 */
1742 do { 1753 do {
1743 /* disable HW lock indicator */ 1754 /* disable HW lock indicator */
1744 status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 1755 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1745 if (status < 0) 1756 if (status < 0)
1746 break; 1757 break;
1747 1758
@@ -1907,14 +1918,14 @@ static int MPEGTSStart(struct drxk_state *state)
1907 1918
1908 do { 1919 do {
1909 /* Allow OC to sync again */ 1920 /* Allow OC to sync again */
1910 status = Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); 1921 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1911 if (status < 0) 1922 if (status < 0)
1912 break; 1923 break;
1913 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; 1924 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1914 status = Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode); 1925 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1915 if (status < 0) 1926 if (status < 0)
1916 break; 1927 break;
1917 status = Write16_0(state, FEC_OC_SNC_UNLOCK__A, 1); 1928 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1918 if (status < 0) 1929 if (status < 0)
1919 break; 1930 break;
1920 } while (0); 1931 } while (0);
@@ -1929,39 +1940,39 @@ static int MPEGTSDtoInit(struct drxk_state *state)
1929 1940
1930 do { 1941 do {
1931 /* Rate integration settings */ 1942 /* Rate integration settings */
1932 status = Write16_0(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000); 1943 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1933 if (status < 0) 1944 if (status < 0)
1934 break; 1945 break;
1935 status = Write16_0(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C); 1946 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1936 if (status < 0) 1947 if (status < 0)
1937 break; 1948 break;
1938 status = Write16_0(state, FEC_OC_RCN_GAIN__A, 0x000A); 1949 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1939 if (status < 0) 1950 if (status < 0)
1940 break; 1951 break;
1941 status = Write16_0(state, FEC_OC_AVR_PARM_A__A, 0x0008); 1952 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1942 if (status < 0) 1953 if (status < 0)
1943 break; 1954 break;
1944 status = Write16_0(state, FEC_OC_AVR_PARM_B__A, 0x0006); 1955 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1945 if (status < 0) 1956 if (status < 0)
1946 break; 1957 break;
1947 status = Write16_0(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680); 1958 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1948 if (status < 0) 1959 if (status < 0)
1949 break; 1960 break;
1950 status = Write16_0(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080); 1961 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1951 if (status < 0) 1962 if (status < 0)
1952 break; 1963 break;
1953 status = Write16_0(state, FEC_OC_TMD_COUNT__A, 0x03F4); 1964 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1954 if (status < 0) 1965 if (status < 0)
1955 break; 1966 break;
1956 1967
1957 /* Additional configuration */ 1968 /* Additional configuration */
1958 status = Write16_0(state, FEC_OC_OCR_INVERT__A, 0); 1969 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1959 if (status < 0) 1970 if (status < 0)
1960 break; 1971 break;
1961 status = Write16_0(state, FEC_OC_SNC_LWM__A, 2); 1972 status = write16(state, FEC_OC_SNC_LWM__A, 2);
1962 if (status < 0) 1973 if (status < 0)
1963 break; 1974 break;
1964 status = Write16_0(state, FEC_OC_SNC_HWM__A, 12); 1975 status = write16(state, FEC_OC_SNC_HWM__A, 12);
1965 if (status < 0) 1976 if (status < 0)
1966 break; 1977 break;
1967 } while (0); 1978 } while (0);
@@ -1989,10 +2000,10 @@ static int MPEGTSDtoSetup(struct drxk_state *state,
1989 2000
1990 do { 2001 do {
1991 /* Check insertion of the Reed-Solomon parity bytes */ 2002 /* Check insertion of the Reed-Solomon parity bytes */
1992 status = Read16_0(state, FEC_OC_MODE__A, &fecOcRegMode); 2003 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
1993 if (status < 0) 2004 if (status < 0)
1994 break; 2005 break;
1995 status = Read16_0(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode); 2006 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
1996 if (status < 0) 2007 if (status < 0)
1997 break; 2008 break;
1998 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); 2009 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
@@ -2073,33 +2084,33 @@ static int MPEGTSDtoSetup(struct drxk_state *state,
2073 } 2084 }
2074 2085
2075 /* Write appropriate registers with requested configuration */ 2086 /* Write appropriate registers with requested configuration */
2076 status = Write16_0(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen); 2087 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2077 if (status < 0) 2088 if (status < 0)
2078 break; 2089 break;
2079 status = Write16_0(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod); 2090 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2080 if (status < 0) 2091 if (status < 0)
2081 break; 2092 break;
2082 status = Write16_0(state, FEC_OC_DTO_MODE__A, fecOcDtoMode); 2093 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2083 if (status < 0) 2094 if (status < 0)
2084 break; 2095 break;
2085 status = Write16_0(state, FEC_OC_FCT_MODE__A, fecOcFctMode); 2096 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2086 if (status < 0) 2097 if (status < 0)
2087 break; 2098 break;
2088 status = Write16_0(state, FEC_OC_MODE__A, fecOcRegMode); 2099 status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2089 if (status < 0) 2100 if (status < 0)
2090 break; 2101 break;
2091 status = Write16_0(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode); 2102 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2092 if (status < 0) 2103 if (status < 0)
2093 break; 2104 break;
2094 2105
2095 /* Rate integration settings */ 2106 /* Rate integration settings */
2096 status = Write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate, 0); 2107 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2097 if (status < 0) 2108 if (status < 0)
2098 break; 2109 break;
2099 status = Write16_0(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate); 2110 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2100 if (status < 0) 2111 if (status < 0)
2101 break; 2112 break;
2102 status = Write16_0(state, FEC_OC_TMD_MODE__A, fecOcTmdMode); 2113 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2103 if (status < 0) 2114 if (status < 0)
2104 break; 2115 break;
2105 } while (0); 2116 } while (0);
@@ -2136,7 +2147,7 @@ static int MPEGTSConfigurePolarity(struct drxk_state *state)
2136 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); 2147 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2137 if (state->m_invertCLK == true) 2148 if (state->m_invertCLK == true)
2138 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; 2149 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
2139 status = Write16_0(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); 2150 status = write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
2140 return status; 2151 return status;
2141} 2152}
2142 2153
@@ -2160,15 +2171,15 @@ static int SetAgcRf(struct drxk_state *state,
2160 case DRXK_AGC_CTRL_AUTO: 2171 case DRXK_AGC_CTRL_AUTO:
2161 2172
2162 /* Enable RF AGC DAC */ 2173 /* Enable RF AGC DAC */
2163 status = Read16_0(state, IQM_AF_STDBY__A, &data); 2174 status = read16(state, IQM_AF_STDBY__A, &data);
2164 if (status < 0) 2175 if (status < 0)
2165 break; 2176 break;
2166 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2177 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2167 status = Write16_0(state, IQM_AF_STDBY__A, data); 2178 status = write16(state, IQM_AF_STDBY__A, data);
2168 if (status < 0) 2179 if (status < 0)
2169 break; 2180 break;
2170 2181
2171 status = Read16(state, SCU_RAM_AGC_CONFIG__A, &data, 0); 2182 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2172 if (status < 0) 2183 if (status < 0)
2173 break; 2184 break;
2174 2185
@@ -2180,12 +2191,12 @@ static int SetAgcRf(struct drxk_state *state,
2180 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2191 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2181 else 2192 else
2182 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2193 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2183 status = Write16_0(state, SCU_RAM_AGC_CONFIG__A, data); 2194 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2184 if (status < 0) 2195 if (status < 0)
2185 break; 2196 break;
2186 2197
2187 /* Set speed (using complementary reduction value) */ 2198 /* Set speed (using complementary reduction value) */
2188 status = Read16(state, SCU_RAM_AGC_KI_RED__A, &data, 0); 2199 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2189 if (status < 0) 2200 if (status < 0)
2190 break; 2201 break;
2191 2202
@@ -2194,7 +2205,7 @@ static int SetAgcRf(struct drxk_state *state,
2194 SCU_RAM_AGC_KI_RED_RAGC_RED__B) 2205 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2195 & SCU_RAM_AGC_KI_RED_RAGC_RED__M); 2206 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2196 2207
2197 status = Write16_0(state, SCU_RAM_AGC_KI_RED__A, data); 2208 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2198 if (status < 0) 2209 if (status < 0)
2199 break; 2210 break;
2200 2211
@@ -2209,17 +2220,17 @@ static int SetAgcRf(struct drxk_state *state,
2209 2220
2210 /* Set TOP, only if IF-AGC is in AUTO mode */ 2221 /* Set TOP, only if IF-AGC is in AUTO mode */
2211 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO) 2222 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2212 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top); 2223 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2213 if (status < 0) 2224 if (status < 0)
2214 break; 2225 break;
2215 2226
2216 /* Cut-Off current */ 2227 /* Cut-Off current */
2217 status = Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent); 2228 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2218 if (status < 0) 2229 if (status < 0)
2219 break; 2230 break;
2220 2231
2221 /* Max. output level */ 2232 /* Max. output level */
2222 status = Write16_0(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel); 2233 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2223 if (status < 0) 2234 if (status < 0)
2224 break; 2235 break;
2225 2236
@@ -2227,16 +2238,16 @@ static int SetAgcRf(struct drxk_state *state,
2227 2238
2228 case DRXK_AGC_CTRL_USER: 2239 case DRXK_AGC_CTRL_USER:
2229 /* Enable RF AGC DAC */ 2240 /* Enable RF AGC DAC */
2230 status = Read16_0(state, IQM_AF_STDBY__A, &data); 2241 status = read16(state, IQM_AF_STDBY__A, &data);
2231 if (status < 0) 2242 if (status < 0)
2232 break; 2243 break;
2233 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2244 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2234 status = Write16_0(state, IQM_AF_STDBY__A, data); 2245 status = write16(state, IQM_AF_STDBY__A, data);
2235 if (status < 0) 2246 if (status < 0)
2236 break; 2247 break;
2237 2248
2238 /* Disable SCU RF AGC loop */ 2249 /* Disable SCU RF AGC loop */
2239 status = Read16_0(state, SCU_RAM_AGC_CONFIG__A, &data); 2250 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2240 if (status < 0) 2251 if (status < 0)
2241 break; 2252 break;
2242 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2253 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
@@ -2244,37 +2255,37 @@ static int SetAgcRf(struct drxk_state *state,
2244 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2255 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2245 else 2256 else
2246 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2257 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2247 status = Write16_0(state, SCU_RAM_AGC_CONFIG__A, data); 2258 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2248 if (status < 0) 2259 if (status < 0)
2249 break; 2260 break;
2250 2261
2251 /* SCU c.o.c. to 0, enabling full control range */ 2262 /* SCU c.o.c. to 0, enabling full control range */
2252 status = Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0); 2263 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2253 if (status < 0) 2264 if (status < 0)
2254 break; 2265 break;
2255 2266
2256 /* Write value to output pin */ 2267 /* Write value to output pin */
2257 status = Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel); 2268 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2258 if (status < 0) 2269 if (status < 0)
2259 break; 2270 break;
2260 break; 2271 break;
2261 2272
2262 case DRXK_AGC_CTRL_OFF: 2273 case DRXK_AGC_CTRL_OFF:
2263 /* Disable RF AGC DAC */ 2274 /* Disable RF AGC DAC */
2264 status = Read16_0(state, IQM_AF_STDBY__A, &data); 2275 status = read16(state, IQM_AF_STDBY__A, &data);
2265 if (status < 0) 2276 if (status < 0)
2266 break; 2277 break;
2267 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2278 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2268 status = Write16_0(state, IQM_AF_STDBY__A, data); 2279 status = write16(state, IQM_AF_STDBY__A, data);
2269 if (status < 0) 2280 if (status < 0)
2270 break; 2281 break;
2271 2282
2272 /* Disable SCU RF AGC loop */ 2283 /* Disable SCU RF AGC loop */
2273 status = Read16_0(state, SCU_RAM_AGC_CONFIG__A, &data); 2284 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2274 if (status < 0) 2285 if (status < 0)
2275 break; 2286 break;
2276 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2287 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2277 status = Write16_0(state, SCU_RAM_AGC_CONFIG__A, data); 2288 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2278 if (status < 0) 2289 if (status < 0)
2279 break; 2290 break;
2280 break; 2291 break;
@@ -2303,15 +2314,15 @@ static int SetAgcIf(struct drxk_state *state,
2303 case DRXK_AGC_CTRL_AUTO: 2314 case DRXK_AGC_CTRL_AUTO:
2304 2315
2305 /* Enable IF AGC DAC */ 2316 /* Enable IF AGC DAC */
2306 status = Read16_0(state, IQM_AF_STDBY__A, &data); 2317 status = read16(state, IQM_AF_STDBY__A, &data);
2307 if (status < 0) 2318 if (status < 0)
2308 break; 2319 break;
2309 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2320 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2310 status = Write16_0(state, IQM_AF_STDBY__A, data); 2321 status = write16(state, IQM_AF_STDBY__A, data);
2311 if (status < 0) 2322 if (status < 0)
2312 break; 2323 break;
2313 2324
2314 status = Read16_0(state, SCU_RAM_AGC_CONFIG__A, &data); 2325 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2315 if (status < 0) 2326 if (status < 0)
2316 break; 2327 break;
2317 2328
@@ -2323,12 +2334,12 @@ static int SetAgcIf(struct drxk_state *state,
2323 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2334 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2324 else 2335 else
2325 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2336 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2326 status = Write16_0(state, SCU_RAM_AGC_CONFIG__A, data); 2337 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2327 if (status < 0) 2338 if (status < 0)
2328 break; 2339 break;
2329 2340
2330 /* Set speed (using complementary reduction value) */ 2341 /* Set speed (using complementary reduction value) */
2331 status = Read16_0(state, SCU_RAM_AGC_KI_RED__A, &data); 2342 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2332 if (status < 0) 2343 if (status < 0)
2333 break; 2344 break;
2334 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; 2345 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
@@ -2336,7 +2347,7 @@ static int SetAgcIf(struct drxk_state *state,
2336 SCU_RAM_AGC_KI_RED_IAGC_RED__B) 2347 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2337 & SCU_RAM_AGC_KI_RED_IAGC_RED__M); 2348 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2338 2349
2339 status = Write16_0(state, SCU_RAM_AGC_KI_RED__A, data); 2350 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2340 if (status < 0) 2351 if (status < 0)
2341 break; 2352 break;
2342 2353
@@ -2347,7 +2358,7 @@ static int SetAgcIf(struct drxk_state *state,
2347 if (pRfAgcSettings == NULL) 2358 if (pRfAgcSettings == NULL)
2348 return -1; 2359 return -1;
2349 /* Restore TOP */ 2360 /* Restore TOP */
2350 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top); 2361 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2351 if (status < 0) 2362 if (status < 0)
2352 break; 2363 break;
2353 break; 2364 break;
@@ -2355,15 +2366,15 @@ static int SetAgcIf(struct drxk_state *state,
2355 case DRXK_AGC_CTRL_USER: 2366 case DRXK_AGC_CTRL_USER:
2356 2367
2357 /* Enable IF AGC DAC */ 2368 /* Enable IF AGC DAC */
2358 status = Read16_0(state, IQM_AF_STDBY__A, &data); 2369 status = read16(state, IQM_AF_STDBY__A, &data);
2359 if (status < 0) 2370 if (status < 0)
2360 break; 2371 break;
2361 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2372 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2362 status = Write16_0(state, IQM_AF_STDBY__A, data); 2373 status = write16(state, IQM_AF_STDBY__A, data);
2363 if (status < 0) 2374 if (status < 0)
2364 break; 2375 break;
2365 2376
2366 status = Read16_0(state, SCU_RAM_AGC_CONFIG__A, &data); 2377 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2367 if (status < 0) 2378 if (status < 0)
2368 break; 2379 break;
2369 2380
@@ -2375,12 +2386,12 @@ static int SetAgcIf(struct drxk_state *state,
2375 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2386 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2376 else 2387 else
2377 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2388 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2378 status = Write16_0(state, SCU_RAM_AGC_CONFIG__A, data); 2389 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2379 if (status < 0) 2390 if (status < 0)
2380 break; 2391 break;
2381 2392
2382 /* Write value to output pin */ 2393 /* Write value to output pin */
2383 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel); 2394 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2384 if (status < 0) 2395 if (status < 0)
2385 break; 2396 break;
2386 break; 2397 break;
@@ -2388,20 +2399,20 @@ static int SetAgcIf(struct drxk_state *state,
2388 case DRXK_AGC_CTRL_OFF: 2399 case DRXK_AGC_CTRL_OFF:
2389 2400
2390 /* Disable If AGC DAC */ 2401 /* Disable If AGC DAC */
2391 status = Read16_0(state, IQM_AF_STDBY__A, &data); 2402 status = read16(state, IQM_AF_STDBY__A, &data);
2392 if (status < 0) 2403 if (status < 0)
2393 break; 2404 break;
2394 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2405 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2395 status = Write16_0(state, IQM_AF_STDBY__A, data); 2406 status = write16(state, IQM_AF_STDBY__A, data);
2396 if (status < 0) 2407 if (status < 0)
2397 break; 2408 break;
2398 2409
2399 /* Disable SCU IF AGC loop */ 2410 /* Disable SCU IF AGC loop */
2400 status = Read16_0(state, SCU_RAM_AGC_CONFIG__A, &data); 2411 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2401 if (status < 0) 2412 if (status < 0)
2402 break; 2413 break;
2403 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2414 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2404 status = Write16_0(state, SCU_RAM_AGC_CONFIG__A, data); 2415 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2405 if (status < 0) 2416 if (status < 0)
2406 break; 2417 break;
2407 break; 2418 break;
@@ -2409,7 +2420,7 @@ static int SetAgcIf(struct drxk_state *state,
2409 2420
2410 /* always set the top to support 2421 /* always set the top to support
2411 configurations without if-loop */ 2422 configurations without if-loop */
2412 status = Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top); 2423 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2413 if (status < 0) 2424 if (status < 0)
2414 break; 2425 break;
2415 2426
@@ -2421,7 +2432,7 @@ static int SetAgcIf(struct drxk_state *state,
2421static int ReadIFAgc(struct drxk_state *state, u32 *pValue) 2432static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
2422{ 2433{
2423 u16 agcDacLvl; 2434 u16 agcDacLvl;
2424 int status = Read16_0(state, IQM_AF_AGC_IF__A, &agcDacLvl); 2435 int status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
2425 2436
2426 dprintk(1, "\n"); 2437 dprintk(1, "\n");
2427 2438
@@ -2455,7 +2466,7 @@ static int GetQAMSignalToNoise(struct drxk_state *state,
2455 u32 qamSlMer = 0; /* QAM MER */ 2466 u32 qamSlMer = 0; /* QAM MER */
2456 2467
2457 /* get the register value needed for MER */ 2468 /* get the register value needed for MER */
2458 status = Read16_0(state, QAM_SL_ERR_POWER__A, &qamSlErrPower); 2469 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2459 if (status < 0) 2470 if (status < 0)
2460 break; 2471 break;
2461 2472
@@ -2508,16 +2519,16 @@ static int GetDVBTSignalToNoise(struct drxk_state *state,
2508 2519
2509 dprintk(1, "\n"); 2520 dprintk(1, "\n");
2510 do { 2521 do {
2511 status = Read16_0(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs); 2522 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2512 if (status < 0) 2523 if (status < 0)
2513 break; 2524 break;
2514 status = Read16_0(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt); 2525 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2515 if (status < 0) 2526 if (status < 0)
2516 break; 2527 break;
2517 status = Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp); 2528 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2518 if (status < 0) 2529 if (status < 0)
2519 break; 2530 break;
2520 status = Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &regData); 2531 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &regData);
2521 if (status < 0) 2532 if (status < 0)
2522 break; 2533 break;
2523 /* Extend SQR_ERR_I operational range */ 2534 /* Extend SQR_ERR_I operational range */
@@ -2526,7 +2537,7 @@ static int GetDVBTSignalToNoise(struct drxk_state *state,
2526 (EqRegTdSqrErrI < 0x00000FFFUL)) { 2537 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2527 EqRegTdSqrErrI += 0x00010000UL; 2538 EqRegTdSqrErrI += 0x00010000UL;
2528 } 2539 }
2529 status = Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &regData); 2540 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &regData);
2530 if (status < 0) 2541 if (status < 0)
2531 break; 2542 break;
2532 /* Extend SQR_ERR_Q operational range */ 2543 /* Extend SQR_ERR_Q operational range */
@@ -2535,7 +2546,7 @@ static int GetDVBTSignalToNoise(struct drxk_state *state,
2535 (EqRegTdSqrErrQ < 0x00000FFFUL)) 2546 (EqRegTdSqrErrQ < 0x00000FFFUL))
2536 EqRegTdSqrErrQ += 0x00010000UL; 2547 EqRegTdSqrErrQ += 0x00010000UL;
2537 2548
2538 status = Read16_0(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams); 2549 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2539 if (status < 0) 2550 if (status < 0)
2540 break; 2551 break;
2541 2552
@@ -2645,12 +2656,12 @@ static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2645 status = GetDVBTSignalToNoise(state, &SignalToNoise); 2656 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2646 if (status < 0) 2657 if (status < 0)
2647 break; 2658 break;
2648 status = Read16_0(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation); 2659 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2649 if (status < 0) 2660 if (status < 0)
2650 break; 2661 break;
2651 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; 2662 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2652 2663
2653 status = Read16_0(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate); 2664 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2654 if (status < 0) 2665 if (status < 0)
2655 break; 2666 break;
2656 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; 2667 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
@@ -2762,15 +2773,15 @@ static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2762 return -1; 2773 return -1;
2763 2774
2764 do { 2775 do {
2765 status = Write16_0(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); 2776 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2766 if (status < 0) 2777 if (status < 0)
2767 break; 2778 break;
2768 if (bEnableBridge) { 2779 if (bEnableBridge) {
2769 status = Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED); 2780 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2770 if (status < 0) 2781 if (status < 0)
2771 break; 2782 break;
2772 } else { 2783 } else {
2773 status = Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN); 2784 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2774 if (status < 0) 2785 if (status < 0)
2775 break; 2786 break;
2776 } 2787 }
@@ -2793,7 +2804,7 @@ static int SetPreSaw(struct drxk_state *state,
2793 || (pPreSawCfg->reference > IQM_AF_PDREF__M)) 2804 || (pPreSawCfg->reference > IQM_AF_PDREF__M))
2794 return -1; 2805 return -1;
2795 2806
2796 status = Write16_0(state, IQM_AF_PDREF__A, pPreSawCfg->reference); 2807 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
2797 return status; 2808 return status;
2798} 2809}
2799 2810
@@ -2810,28 +2821,28 @@ static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2810 2821
2811 mutex_lock(&state->mutex); 2822 mutex_lock(&state->mutex);
2812 do { 2823 do {
2813 status = Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); 2824 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2814 if (status < 0) 2825 if (status < 0)
2815 break; 2826 break;
2816 status = Write16_0(state, SIO_BL_TGT_HDR__A, blockbank); 2827 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2817 if (status < 0) 2828 if (status < 0)
2818 break; 2829 break;
2819 status = Write16_0(state, SIO_BL_TGT_ADDR__A, offset); 2830 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2820 if (status < 0) 2831 if (status < 0)
2821 break; 2832 break;
2822 status = Write16_0(state, SIO_BL_SRC_ADDR__A, romOffset); 2833 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2823 if (status < 0) 2834 if (status < 0)
2824 break; 2835 break;
2825 status = Write16_0(state, SIO_BL_SRC_LEN__A, nrOfElements); 2836 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2826 if (status < 0) 2837 if (status < 0)
2827 break; 2838 break;
2828 status = Write16_0(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); 2839 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2829 if (status < 0) 2840 if (status < 0)
2830 break; 2841 break;
2831 2842
2832 end = jiffies + msecs_to_jiffies(timeOut); 2843 end = jiffies + msecs_to_jiffies(timeOut);
2833 do { 2844 do {
2834 status = Read16_0(state, SIO_BL_STATUS__A, &blStatus); 2845 status = read16(state, SIO_BL_STATUS__A, &blStatus);
2835 if (status < 0) 2846 if (status < 0)
2836 break; 2847 break;
2837 } while ((blStatus == 0x1) && time_is_after_jiffies(end)); 2848 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
@@ -2855,25 +2866,25 @@ static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2855 2866
2856 do { 2867 do {
2857 /* Start measurement */ 2868 /* Start measurement */
2858 status = Write16_0(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); 2869 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2859 if (status < 0) 2870 if (status < 0)
2860 break; 2871 break;
2861 status = Write16_0(state, IQM_AF_START_LOCK__A, 1); 2872 status = write16(state, IQM_AF_START_LOCK__A, 1);
2862 if (status < 0) 2873 if (status < 0)
2863 break; 2874 break;
2864 2875
2865 *count = 0; 2876 *count = 0;
2866 status = Read16_0(state, IQM_AF_PHASE0__A, &data); 2877 status = read16(state, IQM_AF_PHASE0__A, &data);
2867 if (status < 0) 2878 if (status < 0)
2868 break; 2879 break;
2869 if (data == 127) 2880 if (data == 127)
2870 *count = *count + 1; 2881 *count = *count + 1;
2871 status = Read16_0(state, IQM_AF_PHASE1__A, &data); 2882 status = read16(state, IQM_AF_PHASE1__A, &data);
2872 if (status < 0) 2883 if (status < 0)
2873 break; 2884 break;
2874 if (data == 127) 2885 if (data == 127)
2875 *count = *count + 1; 2886 *count = *count + 1;
2876 status = Read16_0(state, IQM_AF_PHASE2__A, &data); 2887 status = read16(state, IQM_AF_PHASE2__A, &data);
2877 if (status < 0) 2888 if (status < 0)
2878 break; 2889 break;
2879 if (data == 127) 2890 if (data == 127)
@@ -2898,7 +2909,7 @@ static int ADCSynchronization(struct drxk_state *state)
2898 /* Try sampling on a diffrent edge */ 2909 /* Try sampling on a diffrent edge */
2899 u16 clkNeg = 0; 2910 u16 clkNeg = 0;
2900 2911
2901 status = Read16_0(state, IQM_AF_CLKNEG__A, &clkNeg); 2912 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
2902 if (status < 0) 2913 if (status < 0)
2903 break; 2914 break;
2904 if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) == 2915 if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
@@ -2911,7 +2922,7 @@ static int ADCSynchronization(struct drxk_state *state)
2911 clkNeg |= 2922 clkNeg |=
2912 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; 2923 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2913 } 2924 }
2914 status = Write16_0(state, IQM_AF_CLKNEG__A, clkNeg); 2925 status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
2915 if (status < 0) 2926 if (status < 0)
2916 break; 2927 break;
2917 status = ADCSyncMeasurement(state, &count); 2928 status = ADCSyncMeasurement(state, &count);
@@ -2984,8 +2995,8 @@ static int SetFrequencyShifter(struct drxk_state *state,
2984 2995
2985 /* Program frequency shifter with tuner offset compensation */ 2996 /* Program frequency shifter with tuner offset compensation */
2986 /* frequencyShift += tunerFreqOffset; TODO */ 2997 /* frequencyShift += tunerFreqOffset; TODO */
2987 status = Write32(state, IQM_FS_RATE_OFS_LO__A, 2998 status = write32(state, IQM_FS_RATE_OFS_LO__A,
2988 state->m_IqmFsRateOfs, 0); 2999 state->m_IqmFsRateOfs);
2989 return status; 3000 return status;
2990} 3001}
2991 3002
@@ -3049,127 +3060,127 @@ static int InitAGC(struct drxk_state *state, bool isDTV)
3049 fastClpCtrlDelay = 3060 fastClpCtrlDelay =
3050 state->m_dvbtIfAgcCfg.FastClipCtrlDelay; 3061 state->m_dvbtIfAgcCfg.FastClipCtrlDelay;
3051 } 3062 }
3052 status = Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay); 3063 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3053 if (status < 0) 3064 if (status < 0)
3054 break; 3065 break;
3055 3066
3056 status = Write16_0(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode); 3067 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3057 if (status < 0) 3068 if (status < 0)
3058 break; 3069 break;
3059 status = Write16_0(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt); 3070 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3060 if (status < 0) 3071 if (status < 0)
3061 break; 3072 break;
3062 status = Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin); 3073 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3063 if (status < 0) 3074 if (status < 0)
3064 break; 3075 break;
3065 status = Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax); 3076 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3066 if (status < 0) 3077 if (status < 0)
3067 break; 3078 break;
3068 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin); 3079 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3069 if (status < 0) 3080 if (status < 0)
3070 break; 3081 break;
3071 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax); 3082 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3072 if (status < 0) 3083 if (status < 0)
3073 break; 3084 break;
3074 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); 3085 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3075 if (status < 0) 3086 if (status < 0)
3076 break; 3087 break;
3077 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0); 3088 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3078 if (status < 0) 3089 if (status < 0)
3079 break; 3090 break;
3080 status = Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0); 3091 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3081 if (status < 0) 3092 if (status < 0)
3082 break; 3093 break;
3083 status = Write16_0(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); 3094 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3084 if (status < 0) 3095 if (status < 0)
3085 break; 3096 break;
3086 status = Write16_0(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax); 3097 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3087 if (status < 0) 3098 if (status < 0)
3088 break; 3099 break;
3089 status = Write16_0(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax); 3100 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3090 if (status < 0) 3101 if (status < 0)
3091 break; 3102 break;
3092 3103
3093 status = Write16_0(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin); 3104 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3094 if (status < 0) 3105 if (status < 0)
3095 break; 3106 break;
3096 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt); 3107 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3097 if (status < 0) 3108 if (status < 0)
3098 break; 3109 break;
3099 status = Write16_0(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen); 3110 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3100 if (status < 0) 3111 if (status < 0)
3101 break; 3112 break;
3102 3113
3103 status = Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023); 3114 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3104 if (status < 0) 3115 if (status < 0)
3105 break; 3116 break;
3106 status = Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023); 3117 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3107 if (status < 0) 3118 if (status < 0)
3108 break; 3119 break;
3109 status = Write16_0(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); 3120 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3110 if (status < 0) 3121 if (status < 0)
3111 break; 3122 break;
3112 3123
3113 status = Write16_0(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); 3124 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3114 if (status < 0) 3125 if (status < 0)
3115 break; 3126 break;
3116 status = Write16_0(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin); 3127 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3117 if (status < 0) 3128 if (status < 0)
3118 break; 3129 break;
3119 status = Write16_0(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin); 3130 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3120 if (status < 0) 3131 if (status < 0)
3121 break; 3132 break;
3122 status = Write16_0(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo); 3133 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3123 if (status < 0) 3134 if (status < 0)
3124 break; 3135 break;
3125 status = Write16_0(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo); 3136 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3126 if (status < 0) 3137 if (status < 0)
3127 break; 3138 break;
3128 status = Write16_0(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); 3139 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3129 if (status < 0) 3140 if (status < 0)
3130 break; 3141 break;
3131 status = Write16_0(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); 3142 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3132 if (status < 0) 3143 if (status < 0)
3133 break; 3144 break;
3134 status = Write16_0(state, SCU_RAM_AGC_KI_MIN__A, 0x0117); 3145 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3135 if (status < 0) 3146 if (status < 0)
3136 break; 3147 break;
3137 status = Write16_0(state, SCU_RAM_AGC_KI_MAX__A, 0x0657); 3148 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3138 if (status < 0) 3149 if (status < 0)
3139 break; 3150 break;
3140 status = Write16_0(state, SCU_RAM_AGC_CLP_SUM__A, 0); 3151 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3141 if (status < 0) 3152 if (status < 0)
3142 break; 3153 break;
3143 status = Write16_0(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0); 3154 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3144 if (status < 0) 3155 if (status < 0)
3145 break; 3156 break;
3146 status = Write16_0(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0); 3157 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3147 if (status < 0) 3158 if (status < 0)
3148 break; 3159 break;
3149 status = Write16_0(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1); 3160 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3150 if (status < 0) 3161 if (status < 0)
3151 break; 3162 break;
3152 status = Write16_0(state, SCU_RAM_AGC_SNS_SUM__A, 0); 3163 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3153 if (status < 0) 3164 if (status < 0)
3154 break; 3165 break;
3155 status = Write16_0(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0); 3166 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3156 if (status < 0) 3167 if (status < 0)
3157 break; 3168 break;
3158 status = Write16_0(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0); 3169 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3159 if (status < 0) 3170 if (status < 0)
3160 break; 3171 break;
3161 status = Write16_0(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1); 3172 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3162 if (status < 0) 3173 if (status < 0)
3163 break; 3174 break;
3164 status = Write16_0(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500); 3175 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3165 if (status < 0) 3176 if (status < 0)
3166 break; 3177 break;
3167 status = Write16_0(state, SCU_RAM_AGC_KI_CYCLEN__A, 500); 3178 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3168 if (status < 0) 3179 if (status < 0)
3169 break; 3180 break;
3170 3181
3171 /* Initialize inner-loop KI gain factors */ 3182 /* Initialize inner-loop KI gain factors */
3172 status = Read16_0(state, SCU_RAM_AGC_KI__A, &data); 3183 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3173 if (status < 0) 3184 if (status < 0)
3174 break; 3185 break;
3175 if (IsQAM(state)) { 3186 if (IsQAM(state)) {
@@ -3179,7 +3190,7 @@ static int InitAGC(struct drxk_state *state, bool isDTV)
3179 data &= ~SCU_RAM_AGC_KI_IF__M; 3190 data &= ~SCU_RAM_AGC_KI_IF__M;
3180 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); 3191 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3181 } 3192 }
3182 status = Write16_0(state, SCU_RAM_AGC_KI__A, data); 3193 status = write16(state, SCU_RAM_AGC_KI__A, data);
3183 if (status < 0) 3194 if (status < 0)
3184 break; 3195 break;
3185 } while (0); 3196 } while (0);
@@ -3193,11 +3204,11 @@ static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
3193 dprintk(1, "\n"); 3204 dprintk(1, "\n");
3194 do { 3205 do {
3195 if (packetErr == NULL) { 3206 if (packetErr == NULL) {
3196 status = Write16_0(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); 3207 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3197 if (status < 0) 3208 if (status < 0)
3198 break; 3209 break;
3199 } else { 3210 } else {
3200 status = Read16_0(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr); 3211 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3201 if (status < 0) 3212 if (status < 0)
3202 break; 3213 break;
3203 } 3214 }
@@ -3217,7 +3228,7 @@ static int DVBTScCommand(struct drxk_state *state,
3217 int status; 3228 int status;
3218 3229
3219 dprintk(1, "\n"); 3230 dprintk(1, "\n");
3220 status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &scExec); 3231 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
3221 if (scExec != 1) { 3232 if (scExec != 1) {
3222 /* SC is not running */ 3233 /* SC is not running */
3223 return -1; 3234 return -1;
@@ -3227,7 +3238,7 @@ static int DVBTScCommand(struct drxk_state *state,
3227 retryCnt = 0; 3238 retryCnt = 0;
3228 do { 3239 do {
3229 msleep(1); 3240 msleep(1);
3230 status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); 3241 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3231 retryCnt++; 3242 retryCnt++;
3232 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); 3243 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3233 if (retryCnt >= DRXK_MAX_RETRIES) 3244 if (retryCnt >= DRXK_MAX_RETRIES)
@@ -3239,7 +3250,7 @@ static int DVBTScCommand(struct drxk_state *state,
3239 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: 3250 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3240 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: 3251 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3241 status = 3252 status =
3242 Write16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); 3253 write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3243 break; 3254 break;
3244 default: 3255 default:
3245 /* Do nothing */ 3256 /* Do nothing */
@@ -3256,17 +3267,17 @@ static int DVBTScCommand(struct drxk_state *state,
3256 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: 3267 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3257 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: 3268 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3258 status = 3269 status =
3259 Write16_0(state, OFDM_SC_RA_RAM_PARAM1__A, param1); 3270 write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3260 /* All commands using 1 parameters */ 3271 /* All commands using 1 parameters */
3261 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: 3272 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3262 case OFDM_SC_RA_RAM_CMD_USER_IO: 3273 case OFDM_SC_RA_RAM_CMD_USER_IO:
3263 status = 3274 status =
3264 Write16_0(state, OFDM_SC_RA_RAM_PARAM0__A, param0); 3275 write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3265 /* All commands using 0 parameters */ 3276 /* All commands using 0 parameters */
3266 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: 3277 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3267 case OFDM_SC_RA_RAM_CMD_NULL: 3278 case OFDM_SC_RA_RAM_CMD_NULL:
3268 /* Write command */ 3279 /* Write command */
3269 status = Write16_0(state, OFDM_SC_RA_RAM_CMD__A, cmd); 3280 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3270 break; 3281 break;
3271 default: 3282 default:
3272 /* Unknown command */ 3283 /* Unknown command */
@@ -3277,14 +3288,14 @@ static int DVBTScCommand(struct drxk_state *state,
3277 retryCnt = 0; 3288 retryCnt = 0;
3278 do { 3289 do {
3279 msleep(1); 3290 msleep(1);
3280 status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); 3291 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3281 retryCnt++; 3292 retryCnt++;
3282 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); 3293 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3283 if (retryCnt >= DRXK_MAX_RETRIES) 3294 if (retryCnt >= DRXK_MAX_RETRIES)
3284 return -1; 3295 return -1;
3285 3296
3286 /* Check for illegal cmd */ 3297 /* Check for illegal cmd */
3287 status = Read16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode); 3298 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
3288 if (errCode == 0xFFFF) { 3299 if (errCode == 0xFFFF) {
3289 /* illegal command */ 3300 /* illegal command */
3290 return -EINVAL; 3301 return -EINVAL;
@@ -3300,7 +3311,7 @@ static int DVBTScCommand(struct drxk_state *state,
3300 case OFDM_SC_RA_RAM_CMD_USER_IO: 3311 case OFDM_SC_RA_RAM_CMD_USER_IO:
3301 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: 3312 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3302 status = 3313 status =
3303 Read16_0(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); 3314 read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3304 /* All commands yielding 0 results */ 3315 /* All commands yielding 0 results */
3305 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: 3316 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3306 case OFDM_SC_RA_RAM_CMD_SET_TIMER: 3317 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
@@ -3337,9 +3348,9 @@ static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
3337 3348
3338 dprintk(1, "\n"); 3349 dprintk(1, "\n");
3339 if (*enabled == true) 3350 if (*enabled == true)
3340 status = Write16_0(state, IQM_CF_BYPASSDET__A, 0); 3351 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3341 else 3352 else
3342 status = Write16_0(state, IQM_CF_BYPASSDET__A, 1); 3353 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3343 3354
3344 return status; 3355 return status;
3345} 3356}
@@ -3353,11 +3364,11 @@ static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
3353 dprintk(1, "\n"); 3364 dprintk(1, "\n");
3354 if (*enabled == true) { 3365 if (*enabled == true) {
3355 /* write mask to 1 */ 3366 /* write mask to 1 */
3356 status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 3367 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3357 DEFAULT_FR_THRES_8K); 3368 DEFAULT_FR_THRES_8K);
3358 } else { 3369 } else {
3359 /* write mask to 0 */ 3370 /* write mask to 0 */
3360 status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); 3371 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3361 } 3372 }
3362 3373
3363 return status; 3374 return status;
@@ -3371,7 +3382,7 @@ static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3371 3382
3372 dprintk(1, "\n"); 3383 dprintk(1, "\n");
3373 do { 3384 do {
3374 status = Read16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); 3385 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3375 if (status < 0) 3386 if (status < 0)
3376 break; 3387 break;
3377 3388
@@ -3395,7 +3406,7 @@ static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3395 break; 3406 break;
3396 } 3407 }
3397 3408
3398 status = Write16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data); 3409 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3399 if (status < 0) 3410 if (status < 0)
3400 break; 3411 break;
3401 } while (0); 3412 } while (0);
@@ -3418,7 +3429,7 @@ static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3418 default: 3429 default:
3419 return -EINVAL; 3430 return -EINVAL;
3420 } 3431 }
3421 status = Write16_0(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, 3432 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3422 (u16) *speed); 3433 (u16) *speed);
3423 return status; 3434 return status;
3424} 3435}
@@ -3456,7 +3467,7 @@ static int DVBTActivatePresets(struct drxk_state *state)
3456 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k); 3467 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3457 if (status < 0) 3468 if (status < 0)
3458 break; 3469 break;
3459 status = Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax); 3470 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3460 if (status < 0) 3471 if (status < 0)
3461 break; 3472 break;
3462 } while (0); 3473 } while (0);
@@ -3498,73 +3509,73 @@ static int SetDVBTStandard(struct drxk_state *state,
3498 break; 3509 break;
3499 3510
3500 /* reset datapath for OFDM, processors first */ 3511 /* reset datapath for OFDM, processors first */
3501 status = Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); 3512 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3502 if (status < 0) 3513 if (status < 0)
3503 break; 3514 break;
3504 status = Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); 3515 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3505 if (status < 0) 3516 if (status < 0)
3506 break; 3517 break;
3507 status = Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); 3518 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3508 if (status < 0) 3519 if (status < 0)
3509 break; 3520 break;
3510 3521
3511 /* IQM setup */ 3522 /* IQM setup */
3512 /* synchronize on ofdstate->m_festart */ 3523 /* synchronize on ofdstate->m_festart */
3513 status = Write16_0(state, IQM_AF_UPD_SEL__A, 1); 3524 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3514 if (status < 0) 3525 if (status < 0)
3515 break; 3526 break;
3516 /* window size for clipping ADC detection */ 3527 /* window size for clipping ADC detection */
3517 status = Write16_0(state, IQM_AF_CLP_LEN__A, 0); 3528 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3518 if (status < 0) 3529 if (status < 0)
3519 break; 3530 break;
3520 /* window size for for sense pre-SAW detection */ 3531 /* window size for for sense pre-SAW detection */
3521 status = Write16_0(state, IQM_AF_SNS_LEN__A, 0); 3532 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3522 if (status < 0) 3533 if (status < 0)
3523 break; 3534 break;
3524 /* sense threshold for sense pre-SAW detection */ 3535 /* sense threshold for sense pre-SAW detection */
3525 status = Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); 3536 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3526 if (status < 0) 3537 if (status < 0)
3527 break; 3538 break;
3528 status = SetIqmAf(state, true); 3539 status = SetIqmAf(state, true);
3529 if (status < 0) 3540 if (status < 0)
3530 break; 3541 break;
3531 3542
3532 status = Write16_0(state, IQM_AF_AGC_RF__A, 0); 3543 status = write16(state, IQM_AF_AGC_RF__A, 0);
3533 if (status < 0) 3544 if (status < 0)
3534 break; 3545 break;
3535 3546
3536 /* Impulse noise cruncher setup */ 3547 /* Impulse noise cruncher setup */
3537 status = Write16_0(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */ 3548 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3538 if (status < 0) 3549 if (status < 0)
3539 break; 3550 break;
3540 status = Write16_0(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */ 3551 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3541 if (status < 0) 3552 if (status < 0)
3542 break; 3553 break;
3543 status = Write16_0(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */ 3554 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3544 if (status < 0) 3555 if (status < 0)
3545 break; 3556 break;
3546 3557
3547 status = Write16_0(state, IQM_RC_STRETCH__A, 16); 3558 status = write16(state, IQM_RC_STRETCH__A, 16);
3548 if (status < 0) 3559 if (status < 0)
3549 break; 3560 break;
3550 status = Write16_0(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ 3561 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3551 if (status < 0) 3562 if (status < 0)
3552 break; 3563 break;
3553 status = Write16_0(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ 3564 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3554 if (status < 0) 3565 if (status < 0)
3555 break; 3566 break;
3556 status = Write16_0(state, IQM_CF_SCALE__A, 1600); 3567 status = write16(state, IQM_CF_SCALE__A, 1600);
3557 if (status < 0) 3568 if (status < 0)
3558 break; 3569 break;
3559 status = Write16_0(state, IQM_CF_SCALE_SH__A, 0); 3570 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3560 if (status < 0) 3571 if (status < 0)
3561 break; 3572 break;
3562 3573
3563 /* virtual clipping threshold for clipping ADC detection */ 3574 /* virtual clipping threshold for clipping ADC detection */
3564 status = Write16_0(state, IQM_AF_CLP_TH__A, 448); 3575 status = write16(state, IQM_AF_CLP_TH__A, 448);
3565 if (status < 0) 3576 if (status < 0)
3566 break; 3577 break;
3567 status = Write16_0(state, IQM_CF_DATATH__A, 495); /* crunching threshold */ 3578 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3568 if (status < 0) 3579 if (status < 0)
3569 break; 3580 break;
3570 3581
@@ -3572,17 +3583,17 @@ static int SetDVBTStandard(struct drxk_state *state,
3572 if (status < 0) 3583 if (status < 0)
3573 break; 3584 break;
3574 3585
3575 status = Write16_0(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */ 3586 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3576 if (status < 0) 3587 if (status < 0)
3577 break; 3588 break;
3578 status = Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 2); 3589 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3579 if (status < 0) 3590 if (status < 0)
3580 break; 3591 break;
3581 /* enable power measurement interrupt */ 3592 /* enable power measurement interrupt */
3582 status = Write16_0(state, IQM_CF_COMM_INT_MSK__A, 1); 3593 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3583 if (status < 0) 3594 if (status < 0)
3584 break; 3595 break;
3585 status = Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); 3596 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3586 if (status < 0) 3597 if (status < 0)
3587 break; 3598 break;
3588 3599
@@ -3595,7 +3606,7 @@ static int SetDVBTStandard(struct drxk_state *state,
3595 break; 3606 break;
3596 3607
3597 /* Halt SCU to enable safe non-atomic accesses */ 3608 /* Halt SCU to enable safe non-atomic accesses */
3598 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 3609 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3599 if (status < 0) 3610 if (status < 0)
3600 break; 3611 break;
3601 3612
@@ -3607,52 +3618,52 @@ static int SetDVBTStandard(struct drxk_state *state,
3607 break; 3618 break;
3608 3619
3609 /* Set Noise Estimation notch width and enable DC fix */ 3620 /* Set Noise Estimation notch width and enable DC fix */
3610 status = Read16_0(state, OFDM_SC_RA_RAM_CONFIG__A, &data); 3621 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3611 if (status < 0) 3622 if (status < 0)
3612 break; 3623 break;
3613 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; 3624 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3614 status = Write16_0(state, OFDM_SC_RA_RAM_CONFIG__A, data); 3625 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3615 if (status < 0) 3626 if (status < 0)
3616 break; 3627 break;
3617 3628
3618 /* Activate SCU to enable SCU commands */ 3629 /* Activate SCU to enable SCU commands */
3619 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 3630 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3620 if (status < 0) 3631 if (status < 0)
3621 break; 3632 break;
3622 3633
3623 if (!state->m_DRXK_A3_ROM_CODE) { 3634 if (!state->m_DRXK_A3_ROM_CODE) {
3624 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */ 3635 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3625 status = Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay); 3636 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3626 if (status < 0) 3637 if (status < 0)
3627 break; 3638 break;
3628 } 3639 }
3629 3640
3630 /* OFDM_SC setup */ 3641 /* OFDM_SC setup */
3631#ifdef COMPILE_FOR_NONRT 3642#ifdef COMPILE_FOR_NONRT
3632 status = Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1); 3643 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3633 if (status < 0) 3644 if (status < 0)
3634 break; 3645 break;
3635 status = Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2); 3646 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3636 if (status < 0) 3647 if (status < 0)
3637 break; 3648 break;
3638#endif 3649#endif
3639 3650
3640 /* FEC setup */ 3651 /* FEC setup */
3641 status = Write16_0(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */ 3652 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3642 if (status < 0) 3653 if (status < 0)
3643 break; 3654 break;
3644 3655
3645 3656
3646#ifdef COMPILE_FOR_NONRT 3657#ifdef COMPILE_FOR_NONRT
3647 status = Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400); 3658 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3648 if (status < 0) 3659 if (status < 0)
3649 break; 3660 break;
3650#else 3661#else
3651 status = Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000); 3662 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3652 if (status < 0) 3663 if (status < 0)
3653 break; 3664 break;
3654#endif 3665#endif
3655 status = Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001); 3666 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3656 if (status < 0) 3667 if (status < 0)
3657 break; 3668 break;
3658 3669
@@ -3697,7 +3708,7 @@ static int DVBTStart(struct drxk_state *state)
3697 status = MPEGTSStart(state); 3708 status = MPEGTSStart(state);
3698 if (status < 0) 3709 if (status < 0)
3699 break; 3710 break;
3700 status = Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); 3711 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3701 if (status < 0) 3712 if (status < 0)
3702 break; 3713 break;
3703 } while (0); 3714 } while (0);
@@ -3732,21 +3743,21 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3732 break; 3743 break;
3733 3744
3734 /* Halt SCU to enable safe non-atomic accesses */ 3745 /* Halt SCU to enable safe non-atomic accesses */
3735 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 3746 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3736 if (status < 0) 3747 if (status < 0)
3737 break; 3748 break;
3738 3749
3739 /* Stop processors */ 3750 /* Stop processors */
3740 status = Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); 3751 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3741 if (status < 0) 3752 if (status < 0)
3742 break; 3753 break;
3743 status = Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); 3754 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3744 if (status < 0) 3755 if (status < 0)
3745 break; 3756 break;
3746 3757
3747 /* Mandatory fix, always stop CP, required to set spl offset back to 3758 /* Mandatory fix, always stop CP, required to set spl offset back to
3748 hardware default (is set to 0 by ucode during pilot detection */ 3759 hardware default (is set to 0 by ucode during pilot detection */
3749 status = Write16_0(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP); 3760 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3750 if (status < 0) 3761 if (status < 0)
3751 break; 3762 break;
3752 3763
@@ -3859,7 +3870,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3859#else 3870#else
3860 /* Set Priorty high */ 3871 /* Set Priorty high */
3861 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; 3872 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3862 status = Write16_0(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); 3873 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3863 if (status < 0) 3874 if (status < 0)
3864 break; 3875 break;
3865#endif 3876#endif
@@ -3903,58 +3914,58 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3903 case BANDWIDTH_AUTO: 3914 case BANDWIDTH_AUTO:
3904 case BANDWIDTH_8_MHZ: 3915 case BANDWIDTH_8_MHZ:
3905 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; 3916 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3906 status = Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052); 3917 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3907 if (status < 0) 3918 if (status < 0)
3908 break; 3919 break;
3909 /* cochannel protection for PAL 8 MHz */ 3920 /* cochannel protection for PAL 8 MHz */
3910 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7); 3921 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3911 if (status < 0) 3922 if (status < 0)
3912 break; 3923 break;
3913 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7); 3924 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3914 if (status < 0) 3925 if (status < 0)
3915 break; 3926 break;
3916 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7); 3927 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3917 if (status < 0) 3928 if (status < 0)
3918 break; 3929 break;
3919 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); 3930 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3920 if (status < 0) 3931 if (status < 0)
3921 break; 3932 break;
3922 break; 3933 break;
3923 case BANDWIDTH_7_MHZ: 3934 case BANDWIDTH_7_MHZ:
3924 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; 3935 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3925 status = Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491); 3936 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3926 if (status < 0) 3937 if (status < 0)
3927 break; 3938 break;
3928 /* cochannel protection for PAL 7 MHz */ 3939 /* cochannel protection for PAL 7 MHz */
3929 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8); 3940 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3930 if (status < 0) 3941 if (status < 0)
3931 break; 3942 break;
3932 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8); 3943 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3933 if (status < 0) 3944 if (status < 0)
3934 break; 3945 break;
3935 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4); 3946 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3936 if (status < 0) 3947 if (status < 0)
3937 break; 3948 break;
3938 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); 3949 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3939 if (status < 0) 3950 if (status < 0)
3940 break; 3951 break;
3941 break; 3952 break;
3942 case BANDWIDTH_6_MHZ: 3953 case BANDWIDTH_6_MHZ:
3943 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; 3954 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3944 status = Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073); 3955 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3945 if (status < 0) 3956 if (status < 0)
3946 break; 3957 break;
3947 /* cochannel protection for NTSC 6 MHz */ 3958 /* cochannel protection for NTSC 6 MHz */
3948 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19); 3959 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
3949 if (status < 0) 3960 if (status < 0)
3950 break; 3961 break;
3951 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19); 3962 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
3952 if (status < 0) 3963 if (status < 0)
3953 break; 3964 break;
3954 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14); 3965 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
3955 if (status < 0) 3966 if (status < 0)
3956 break; 3967 break;
3957 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); 3968 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3958 if (status < 0) 3969 if (status < 0)
3959 break; 3970 break;
3960 break; 3971 break;
@@ -3986,7 +3997,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3986 iqmRcRateOfs &= 3997 iqmRcRateOfs &=
3987 ((((u32) IQM_RC_RATE_OFS_HI__M) << 3998 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
3988 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M); 3999 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
3989 status = Write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs, 0); 4000 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
3990 if (status < 0) 4001 if (status < 0)
3991 break; 4002 break;
3992 4003
@@ -4004,15 +4015,15 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
4004 /*== Start SC, write channel settings to SC ===============================*/ 4015 /*== Start SC, write channel settings to SC ===============================*/
4005 4016
4006 /* Activate SCU to enable SCU commands */ 4017 /* Activate SCU to enable SCU commands */
4007 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 4018 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4008 if (status < 0) 4019 if (status < 0)
4009 break; 4020 break;
4010 4021
4011 /* Enable SC after setting all other parameters */ 4022 /* Enable SC after setting all other parameters */
4012 status = Write16_0(state, OFDM_SC_COMM_STATE__A, 0); 4023 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4013 if (status < 0) 4024 if (status < 0)
4014 break; 4025 break;
4015 status = Write16_0(state, OFDM_SC_COMM_EXEC__A, 1); 4026 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4016 if (status < 0) 4027 if (status < 0)
4017 break; 4028 break;
4018 4029
@@ -4065,14 +4076,14 @@ static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4065 4076
4066 /* driver 0.9.0 */ 4077 /* driver 0.9.0 */
4067 /* Check if SC is running */ 4078 /* Check if SC is running */
4068 status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &ScCommExec); 4079 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
4069 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) { 4080 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) {
4070 /* SC not active; return DRX_NOT_LOCKED */ 4081 /* SC not active; return DRX_NOT_LOCKED */
4071 *pLockStatus = NOT_LOCKED; 4082 *pLockStatus = NOT_LOCKED;
4072 return status; 4083 return status;
4073 } 4084 }
4074 4085
4075 status = Read16_0(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock); 4086 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
4076 4087
4077 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) 4088 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4078 *pLockStatus = MPEG_LOCK; 4089 *pLockStatus = MPEG_LOCK;
@@ -4114,7 +4125,7 @@ static int PowerDownQAM(struct drxk_state *state)
4114 4125
4115 dprintk(1, "\n"); 4126 dprintk(1, "\n");
4116 do { 4127 do {
4117 status = Read16_0(state, SCU_COMM_EXEC__A, &data); 4128 status = read16(state, SCU_COMM_EXEC__A, &data);
4118 if (status < 0) 4129 if (status < 0)
4119 break; 4130 break;
4120 if (data == SCU_COMM_EXEC_ACTIVE) { 4131 if (data == SCU_COMM_EXEC_ACTIVE) {
@@ -4123,7 +4134,7 @@ static int PowerDownQAM(struct drxk_state *state)
4123 QAM and HW blocks 4134 QAM and HW blocks
4124 */ 4135 */
4125 /* stop all comstate->m_exec */ 4136 /* stop all comstate->m_exec */
4126 status = Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); 4137 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4127 if (status < 0) 4138 if (status < 0)
4128 break; 4139 break;
4129 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult); 4140 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
@@ -4217,13 +4228,13 @@ static int SetQAMMeasurement(struct drxk_state *state,
4217 (fecRsPrescale >> 1)) / fecRsPrescale; 4228 (fecRsPrescale >> 1)) / fecRsPrescale;
4218 4229
4219 /* write corresponding registers */ 4230 /* write corresponding registers */
4220 status = Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod); 4231 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
4221 if (status < 0) 4232 if (status < 0)
4222 break; 4233 break;
4223 status = Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale); 4234 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4224 if (status < 0) 4235 if (status < 0)
4225 break; 4236 break;
4226 status = Write16_0(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod); 4237 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4227 if (status < 0) 4238 if (status < 0)
4228 break; 4239 break;
4229 4240
@@ -4243,176 +4254,176 @@ static int SetQAM16(struct drxk_state *state)
4243 do { 4254 do {
4244 /* QAM Equalizer Setup */ 4255 /* QAM Equalizer Setup */
4245 /* Equalizer */ 4256 /* Equalizer */
4246 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517); 4257 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4247 if (status < 0) 4258 if (status < 0)
4248 break; 4259 break;
4249 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517); 4260 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4250 if (status < 0) 4261 if (status < 0)
4251 break; 4262 break;
4252 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517); 4263 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4253 if (status < 0) 4264 if (status < 0)
4254 break; 4265 break;
4255 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517); 4266 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4256 if (status < 0) 4267 if (status < 0)
4257 break; 4268 break;
4258 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517); 4269 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4259 if (status < 0) 4270 if (status < 0)
4260 break; 4271 break;
4261 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517); 4272 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4262 if (status < 0) 4273 if (status < 0)
4263 break; 4274 break;
4264 /* Decision Feedback Equalizer */ 4275 /* Decision Feedback Equalizer */
4265 status = Write16_0(state, QAM_DQ_QUAL_FUN0__A, 2); 4276 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4266 if (status < 0) 4277 if (status < 0)
4267 break; 4278 break;
4268 status = Write16_0(state, QAM_DQ_QUAL_FUN1__A, 2); 4279 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4269 if (status < 0) 4280 if (status < 0)
4270 break; 4281 break;
4271 status = Write16_0(state, QAM_DQ_QUAL_FUN2__A, 2); 4282 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4272 if (status < 0) 4283 if (status < 0)
4273 break; 4284 break;
4274 status = Write16_0(state, QAM_DQ_QUAL_FUN3__A, 2); 4285 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4275 if (status < 0) 4286 if (status < 0)
4276 break; 4287 break;
4277 status = Write16_0(state, QAM_DQ_QUAL_FUN4__A, 2); 4288 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4278 if (status < 0) 4289 if (status < 0)
4279 break; 4290 break;
4280 status = Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0); 4291 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4281 if (status < 0) 4292 if (status < 0)
4282 break; 4293 break;
4283 4294
4284 status = Write16_0(state, QAM_SY_SYNC_HWM__A, 5); 4295 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4285 if (status < 0) 4296 if (status < 0)
4286 break; 4297 break;
4287 status = Write16_0(state, QAM_SY_SYNC_AWM__A, 4); 4298 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4288 if (status < 0) 4299 if (status < 0)
4289 break; 4300 break;
4290 status = Write16_0(state, QAM_SY_SYNC_LWM__A, 3); 4301 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4291 if (status < 0) 4302 if (status < 0)
4292 break; 4303 break;
4293 4304
4294 /* QAM Slicer Settings */ 4305 /* QAM Slicer Settings */
4295 status = Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16); 4306 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4296 if (status < 0) 4307 if (status < 0)
4297 break; 4308 break;
4298 4309
4299 /* QAM Loop Controller Coeficients */ 4310 /* QAM Loop Controller Coeficients */
4300 status = Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4311 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4301 if (status < 0) 4312 if (status < 0)
4302 break; 4313 break;
4303 status = Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4314 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4304 if (status < 0) 4315 if (status < 0)
4305 break; 4316 break;
4306 status = Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4317 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4307 if (status < 0) 4318 if (status < 0)
4308 break; 4319 break;
4309 status = Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4320 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4310 if (status < 0) 4321 if (status < 0)
4311 break; 4322 break;
4312 status = Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4323 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4313 if (status < 0) 4324 if (status < 0)
4314 break; 4325 break;
4315 status = Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4326 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4316 if (status < 0) 4327 if (status < 0)
4317 break; 4328 break;
4318 status = Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4329 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4319 if (status < 0) 4330 if (status < 0)
4320 break; 4331 break;
4321 status = Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4332 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4322 if (status < 0) 4333 if (status < 0)
4323 break; 4334 break;
4324 4335
4325 status = Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4336 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4326 if (status < 0) 4337 if (status < 0)
4327 break; 4338 break;
4328 status = Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); 4339 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4329 if (status < 0) 4340 if (status < 0)
4330 break; 4341 break;
4331 status = Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); 4342 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4332 if (status < 0) 4343 if (status < 0)
4333 break; 4344 break;
4334 status = Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4345 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4335 if (status < 0) 4346 if (status < 0)
4336 break; 4347 break;
4337 status = Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); 4348 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4338 if (status < 0) 4349 if (status < 0)
4339 break; 4350 break;
4340 status = Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); 4351 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4341 if (status < 0) 4352 if (status < 0)
4342 break; 4353 break;
4343 status = Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4354 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4344 if (status < 0) 4355 if (status < 0)
4345 break; 4356 break;
4346 status = Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); 4357 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4347 if (status < 0) 4358 if (status < 0)
4348 break; 4359 break;
4349 status = Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32); 4360 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4350 if (status < 0) 4361 if (status < 0)
4351 break; 4362 break;
4352 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4363 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4353 if (status < 0) 4364 if (status < 0)
4354 break; 4365 break;
4355 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4366 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4356 if (status < 0) 4367 if (status < 0)
4357 break; 4368 break;
4358 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); 4369 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4359 if (status < 0) 4370 if (status < 0)
4360 break; 4371 break;
4361 4372
4362 4373
4363 /* QAM State Machine (FSM) Thresholds */ 4374 /* QAM State Machine (FSM) Thresholds */
4364 4375
4365 status = Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 140); 4376 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4366 if (status < 0) 4377 if (status < 0)
4367 break; 4378 break;
4368 status = Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50); 4379 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4369 if (status < 0) 4380 if (status < 0)
4370 break; 4381 break;
4371 status = Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 95); 4382 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4372 if (status < 0) 4383 if (status < 0)
4373 break; 4384 break;
4374 status = Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 120); 4385 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4375 if (status < 0) 4386 if (status < 0)
4376 break; 4387 break;
4377 status = Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 230); 4388 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4378 if (status < 0) 4389 if (status < 0)
4379 break; 4390 break;
4380 status = Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 105); 4391 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4381 if (status < 0) 4392 if (status < 0)
4382 break; 4393 break;
4383 4394
4384 status = Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4395 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4385 if (status < 0) 4396 if (status < 0)
4386 break; 4397 break;
4387 status = Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 4398 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4388 if (status < 0) 4399 if (status < 0)
4389 break; 4400 break;
4390 status = Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24); 4401 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4391 if (status < 0) 4402 if (status < 0)
4392 break; 4403 break;
4393 4404
4394 4405
4395 /* QAM FSM Tracking Parameters */ 4406 /* QAM FSM Tracking Parameters */
4396 4407
4397 status = Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16); 4408 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4398 if (status < 0) 4409 if (status < 0)
4399 break; 4410 break;
4400 status = Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220); 4411 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4401 if (status < 0) 4412 if (status < 0)
4402 break; 4413 break;
4403 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25); 4414 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4404 if (status < 0) 4415 if (status < 0)
4405 break; 4416 break;
4406 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6); 4417 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4407 if (status < 0) 4418 if (status < 0)
4408 break; 4419 break;
4409 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24); 4420 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4410 if (status < 0) 4421 if (status < 0)
4411 break; 4422 break;
4412 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65); 4423 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4413 if (status < 0) 4424 if (status < 0)
4414 break; 4425 break;
4415 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127); 4426 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4416 if (status < 0) 4427 if (status < 0)
4417 break; 4428 break;
4418 } while (0); 4429 } while (0);
@@ -4435,180 +4446,180 @@ static int SetQAM32(struct drxk_state *state)
4435 do { 4446 do {
4436 /* QAM Equalizer Setup */ 4447 /* QAM Equalizer Setup */
4437 /* Equalizer */ 4448 /* Equalizer */
4438 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707); 4449 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4439 if (status < 0) 4450 if (status < 0)
4440 break; 4451 break;
4441 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707); 4452 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4442 if (status < 0) 4453 if (status < 0)
4443 break; 4454 break;
4444 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707); 4455 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4445 if (status < 0) 4456 if (status < 0)
4446 break; 4457 break;
4447 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707); 4458 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4448 if (status < 0) 4459 if (status < 0)
4449 break; 4460 break;
4450 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707); 4461 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4451 if (status < 0) 4462 if (status < 0)
4452 break; 4463 break;
4453 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707); 4464 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4454 if (status < 0) 4465 if (status < 0)
4455 break; 4466 break;
4456 4467
4457 /* Decision Feedback Equalizer */ 4468 /* Decision Feedback Equalizer */
4458 status = Write16_0(state, QAM_DQ_QUAL_FUN0__A, 3); 4469 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4459 if (status < 0) 4470 if (status < 0)
4460 break; 4471 break;
4461 status = Write16_0(state, QAM_DQ_QUAL_FUN1__A, 3); 4472 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4462 if (status < 0) 4473 if (status < 0)
4463 break; 4474 break;
4464 status = Write16_0(state, QAM_DQ_QUAL_FUN2__A, 3); 4475 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4465 if (status < 0) 4476 if (status < 0)
4466 break; 4477 break;
4467 status = Write16_0(state, QAM_DQ_QUAL_FUN3__A, 3); 4478 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4468 if (status < 0) 4479 if (status < 0)
4469 break; 4480 break;
4470 status = Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3); 4481 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4471 if (status < 0) 4482 if (status < 0)
4472 break; 4483 break;
4473 status = Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0); 4484 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4474 if (status < 0) 4485 if (status < 0)
4475 break; 4486 break;
4476 4487
4477 status = Write16_0(state, QAM_SY_SYNC_HWM__A, 6); 4488 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4478 if (status < 0) 4489 if (status < 0)
4479 break; 4490 break;
4480 status = Write16_0(state, QAM_SY_SYNC_AWM__A, 5); 4491 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4481 if (status < 0) 4492 if (status < 0)
4482 break; 4493 break;
4483 status = Write16_0(state, QAM_SY_SYNC_LWM__A, 3); 4494 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4484 if (status < 0) 4495 if (status < 0)
4485 break; 4496 break;
4486 4497
4487 /* QAM Slicer Settings */ 4498 /* QAM Slicer Settings */
4488 4499
4489 status = Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32); 4500 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4490 if (status < 0) 4501 if (status < 0)
4491 break; 4502 break;
4492 4503
4493 4504
4494 /* QAM Loop Controller Coeficients */ 4505 /* QAM Loop Controller Coeficients */
4495 4506
4496 status = Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4507 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4497 if (status < 0) 4508 if (status < 0)
4498 break; 4509 break;
4499 status = Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4510 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4500 if (status < 0) 4511 if (status < 0)
4501 break; 4512 break;
4502 status = Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4513 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4503 if (status < 0) 4514 if (status < 0)
4504 break; 4515 break;
4505 status = Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4516 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4506 if (status < 0) 4517 if (status < 0)
4507 break; 4518 break;
4508 status = Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4519 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4509 if (status < 0) 4520 if (status < 0)
4510 break; 4521 break;
4511 status = Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4522 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4512 if (status < 0) 4523 if (status < 0)
4513 break; 4524 break;
4514 status = Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4525 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4515 if (status < 0) 4526 if (status < 0)
4516 break; 4527 break;
4517 status = Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4528 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4518 if (status < 0) 4529 if (status < 0)
4519 break; 4530 break;
4520 4531
4521 status = Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4532 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4522 if (status < 0) 4533 if (status < 0)
4523 break; 4534 break;
4524 status = Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); 4535 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4525 if (status < 0) 4536 if (status < 0)
4526 break; 4537 break;
4527 status = Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); 4538 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4528 if (status < 0) 4539 if (status < 0)
4529 break; 4540 break;
4530 status = Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4541 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4531 if (status < 0) 4542 if (status < 0)
4532 break; 4543 break;
4533 status = Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); 4544 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4534 if (status < 0) 4545 if (status < 0)
4535 break; 4546 break;
4536 status = Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); 4547 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4537 if (status < 0) 4548 if (status < 0)
4538 break; 4549 break;
4539 status = Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4550 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4540 if (status < 0) 4551 if (status < 0)
4541 break; 4552 break;
4542 status = Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); 4553 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4543 if (status < 0) 4554 if (status < 0)
4544 break; 4555 break;
4545 status = Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16); 4556 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4546 if (status < 0) 4557 if (status < 0)
4547 break; 4558 break;
4548 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4559 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4549 if (status < 0) 4560 if (status < 0)
4550 break; 4561 break;
4551 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4562 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4552 if (status < 0) 4563 if (status < 0)
4553 break; 4564 break;
4554 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); 4565 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4555 if (status < 0) 4566 if (status < 0)
4556 break; 4567 break;
4557 4568
4558 4569
4559 /* QAM State Machine (FSM) Thresholds */ 4570 /* QAM State Machine (FSM) Thresholds */
4560 4571
4561 status = Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 90); 4572 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4562 if (status < 0) 4573 if (status < 0)
4563 break; 4574 break;
4564 status = Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50); 4575 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4565 if (status < 0) 4576 if (status < 0)
4566 break; 4577 break;
4567 status = Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80); 4578 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4568 if (status < 0) 4579 if (status < 0)
4569 break; 4580 break;
4570 status = Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100); 4581 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4571 if (status < 0) 4582 if (status < 0)
4572 break; 4583 break;
4573 status = Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 170); 4584 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4574 if (status < 0) 4585 if (status < 0)
4575 break; 4586 break;
4576 status = Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100); 4587 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4577 if (status < 0) 4588 if (status < 0)
4578 break; 4589 break;
4579 4590
4580 status = Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4591 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4581 if (status < 0) 4592 if (status < 0)
4582 break; 4593 break;
4583 status = Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 4594 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4584 if (status < 0) 4595 if (status < 0)
4585 break; 4596 break;
4586 status = Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10); 4597 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4587 if (status < 0) 4598 if (status < 0)
4588 break; 4599 break;
4589 4600
4590 4601
4591 /* QAM FSM Tracking Parameters */ 4602 /* QAM FSM Tracking Parameters */
4592 4603
4593 status = Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); 4604 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4594 if (status < 0) 4605 if (status < 0)
4595 break; 4606 break;
4596 status = Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140); 4607 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4597 if (status < 0) 4608 if (status < 0)
4598 break; 4609 break;
4599 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8); 4610 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4600 if (status < 0) 4611 if (status < 0)
4601 break; 4612 break;
4602 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16); 4613 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4603 if (status < 0) 4614 if (status < 0)
4604 break; 4615 break;
4605 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26); 4616 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4606 if (status < 0) 4617 if (status < 0)
4607 break; 4618 break;
4608 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56); 4619 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4609 if (status < 0) 4620 if (status < 0)
4610 break; 4621 break;
4611 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); 4622 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4612 if (status < 0) 4623 if (status < 0)
4613 break; 4624 break;
4614 } while (0); 4625 } while (0);
@@ -4631,179 +4642,179 @@ static int SetQAM64(struct drxk_state *state)
4631 do { 4642 do {
4632 /* QAM Equalizer Setup */ 4643 /* QAM Equalizer Setup */
4633 /* Equalizer */ 4644 /* Equalizer */
4634 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336); 4645 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4635 if (status < 0) 4646 if (status < 0)
4636 break; 4647 break;
4637 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618); 4648 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4638 if (status < 0) 4649 if (status < 0)
4639 break; 4650 break;
4640 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988); 4651 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4641 if (status < 0) 4652 if (status < 0)
4642 break; 4653 break;
4643 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809); 4654 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4644 if (status < 0) 4655 if (status < 0)
4645 break; 4656 break;
4646 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809); 4657 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4647 if (status < 0) 4658 if (status < 0)
4648 break; 4659 break;
4649 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609); 4660 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4650 if (status < 0) 4661 if (status < 0)
4651 break; 4662 break;
4652 4663
4653 /* Decision Feedback Equalizer */ 4664 /* Decision Feedback Equalizer */
4654 status = Write16_0(state, QAM_DQ_QUAL_FUN0__A, 4); 4665 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4655 if (status < 0) 4666 if (status < 0)
4656 break; 4667 break;
4657 status = Write16_0(state, QAM_DQ_QUAL_FUN1__A, 4); 4668 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4658 if (status < 0) 4669 if (status < 0)
4659 break; 4670 break;
4660 status = Write16_0(state, QAM_DQ_QUAL_FUN2__A, 4); 4671 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4661 if (status < 0) 4672 if (status < 0)
4662 break; 4673 break;
4663 status = Write16_0(state, QAM_DQ_QUAL_FUN3__A, 4); 4674 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4664 if (status < 0) 4675 if (status < 0)
4665 break; 4676 break;
4666 status = Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3); 4677 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4667 if (status < 0) 4678 if (status < 0)
4668 break; 4679 break;
4669 status = Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0); 4680 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4670 if (status < 0) 4681 if (status < 0)
4671 break; 4682 break;
4672 4683
4673 status = Write16_0(state, QAM_SY_SYNC_HWM__A, 5); 4684 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4674 if (status < 0) 4685 if (status < 0)
4675 break; 4686 break;
4676 status = Write16_0(state, QAM_SY_SYNC_AWM__A, 4); 4687 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4677 if (status < 0) 4688 if (status < 0)
4678 break; 4689 break;
4679 status = Write16_0(state, QAM_SY_SYNC_LWM__A, 3); 4690 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4680 if (status < 0) 4691 if (status < 0)
4681 break; 4692 break;
4682 4693
4683 /* QAM Slicer Settings */ 4694 /* QAM Slicer Settings */
4684 status = Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64); 4695 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4685 if (status < 0) 4696 if (status < 0)
4686 break; 4697 break;
4687 4698
4688 4699
4689 /* QAM Loop Controller Coeficients */ 4700 /* QAM Loop Controller Coeficients */
4690 4701
4691 status = Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4702 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4692 if (status < 0) 4703 if (status < 0)
4693 break; 4704 break;
4694 status = Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4705 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4695 if (status < 0) 4706 if (status < 0)
4696 break; 4707 break;
4697 status = Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4708 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4698 if (status < 0) 4709 if (status < 0)
4699 break; 4710 break;
4700 status = Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4711 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4701 if (status < 0) 4712 if (status < 0)
4702 break; 4713 break;
4703 status = Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4714 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4704 if (status < 0) 4715 if (status < 0)
4705 break; 4716 break;
4706 status = Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4717 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4707 if (status < 0) 4718 if (status < 0)
4708 break; 4719 break;
4709 status = Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4720 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4710 if (status < 0) 4721 if (status < 0)
4711 break; 4722 break;
4712 status = Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4723 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4713 if (status < 0) 4724 if (status < 0)
4714 break; 4725 break;
4715 4726
4716 status = Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4727 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4717 if (status < 0) 4728 if (status < 0)
4718 break; 4729 break;
4719 status = Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); 4730 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4720 if (status < 0) 4731 if (status < 0)
4721 break; 4732 break;
4722 status = Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100); 4733 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4723 if (status < 0) 4734 if (status < 0)
4724 break; 4735 break;
4725 status = Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4736 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4726 if (status < 0) 4737 if (status < 0)
4727 break; 4738 break;
4728 status = Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30); 4739 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4729 if (status < 0) 4740 if (status < 0)
4730 break; 4741 break;
4731 status = Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); 4742 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4732 if (status < 0) 4743 if (status < 0)
4733 break; 4744 break;
4734 status = Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4745 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4735 if (status < 0) 4746 if (status < 0)
4736 break; 4747 break;
4737 status = Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); 4748 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4738 if (status < 0) 4749 if (status < 0)
4739 break; 4750 break;
4740 status = Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); 4751 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4741 if (status < 0) 4752 if (status < 0)
4742 break; 4753 break;
4743 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4754 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4744 if (status < 0) 4755 if (status < 0)
4745 break; 4756 break;
4746 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4757 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4747 if (status < 0) 4758 if (status < 0)
4748 break; 4759 break;
4749 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); 4760 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4750 if (status < 0) 4761 if (status < 0)
4751 break; 4762 break;
4752 4763
4753 4764
4754 /* QAM State Machine (FSM) Thresholds */ 4765 /* QAM State Machine (FSM) Thresholds */
4755 4766
4756 status = Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 100); 4767 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4757 if (status < 0) 4768 if (status < 0)
4758 break; 4769 break;
4759 status = Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60); 4770 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4760 if (status < 0) 4771 if (status < 0)
4761 break; 4772 break;
4762 status = Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80); 4773 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4763 if (status < 0) 4774 if (status < 0)
4764 break; 4775 break;
4765 status = Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 110); 4776 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4766 if (status < 0) 4777 if (status < 0)
4767 break; 4778 break;
4768 status = Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 200); 4779 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4769 if (status < 0) 4780 if (status < 0)
4770 break; 4781 break;
4771 status = Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 95); 4782 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4772 if (status < 0) 4783 if (status < 0)
4773 break; 4784 break;
4774 4785
4775 status = Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4786 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4776 if (status < 0) 4787 if (status < 0)
4777 break; 4788 break;
4778 status = Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 4789 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4779 if (status < 0) 4790 if (status < 0)
4780 break; 4791 break;
4781 status = Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15); 4792 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4782 if (status < 0) 4793 if (status < 0)
4783 break; 4794 break;
4784 4795
4785 4796
4786 /* QAM FSM Tracking Parameters */ 4797 /* QAM FSM Tracking Parameters */
4787 4798
4788 status = Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); 4799 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4789 if (status < 0) 4800 if (status < 0)
4790 break; 4801 break;
4791 status = Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141); 4802 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4792 if (status < 0) 4803 if (status < 0)
4793 break; 4804 break;
4794 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7); 4805 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4795 if (status < 0) 4806 if (status < 0)
4796 break; 4807 break;
4797 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0); 4808 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4798 if (status < 0) 4809 if (status < 0)
4799 break; 4810 break;
4800 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15); 4811 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4801 if (status < 0) 4812 if (status < 0)
4802 break; 4813 break;
4803 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45); 4814 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4804 if (status < 0) 4815 if (status < 0)
4805 break; 4816 break;
4806 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); 4817 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4807 if (status < 0) 4818 if (status < 0)
4808 break; 4819 break;
4809 } while (0); 4820 } while (0);
@@ -4826,181 +4837,181 @@ static int SetQAM128(struct drxk_state *state)
4826 do { 4837 do {
4827 /* QAM Equalizer Setup */ 4838 /* QAM Equalizer Setup */
4828 /* Equalizer */ 4839 /* Equalizer */
4829 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564); 4840 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4830 if (status < 0) 4841 if (status < 0)
4831 break; 4842 break;
4832 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598); 4843 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4833 if (status < 0) 4844 if (status < 0)
4834 break; 4845 break;
4835 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394); 4846 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4836 if (status < 0) 4847 if (status < 0)
4837 break; 4848 break;
4838 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409); 4849 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4839 if (status < 0) 4850 if (status < 0)
4840 break; 4851 break;
4841 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656); 4852 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4842 if (status < 0) 4853 if (status < 0)
4843 break; 4854 break;
4844 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238); 4855 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4845 if (status < 0) 4856 if (status < 0)
4846 break; 4857 break;
4847 4858
4848 /* Decision Feedback Equalizer */ 4859 /* Decision Feedback Equalizer */
4849 status = Write16_0(state, QAM_DQ_QUAL_FUN0__A, 6); 4860 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4850 if (status < 0) 4861 if (status < 0)
4851 break; 4862 break;
4852 status = Write16_0(state, QAM_DQ_QUAL_FUN1__A, 6); 4863 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4853 if (status < 0) 4864 if (status < 0)
4854 break; 4865 break;
4855 status = Write16_0(state, QAM_DQ_QUAL_FUN2__A, 6); 4866 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4856 if (status < 0) 4867 if (status < 0)
4857 break; 4868 break;
4858 status = Write16_0(state, QAM_DQ_QUAL_FUN3__A, 6); 4869 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4859 if (status < 0) 4870 if (status < 0)
4860 break; 4871 break;
4861 status = Write16_0(state, QAM_DQ_QUAL_FUN4__A, 5); 4872 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4862 if (status < 0) 4873 if (status < 0)
4863 break; 4874 break;
4864 status = Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0); 4875 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4865 if (status < 0) 4876 if (status < 0)
4866 break; 4877 break;
4867 4878
4868 status = Write16_0(state, QAM_SY_SYNC_HWM__A, 6); 4879 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4869 if (status < 0) 4880 if (status < 0)
4870 break; 4881 break;
4871 status = Write16_0(state, QAM_SY_SYNC_AWM__A, 5); 4882 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4872 if (status < 0) 4883 if (status < 0)
4873 break; 4884 break;
4874 status = Write16_0(state, QAM_SY_SYNC_LWM__A, 3); 4885 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4875 if (status < 0) 4886 if (status < 0)
4876 break; 4887 break;
4877 4888
4878 4889
4879 /* QAM Slicer Settings */ 4890 /* QAM Slicer Settings */
4880 4891
4881 status = Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128); 4892 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4882 if (status < 0) 4893 if (status < 0)
4883 break; 4894 break;
4884 4895
4885 4896
4886 /* QAM Loop Controller Coeficients */ 4897 /* QAM Loop Controller Coeficients */
4887 4898
4888 status = Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4899 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4889 if (status < 0) 4900 if (status < 0)
4890 break; 4901 break;
4891 status = Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4902 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4892 if (status < 0) 4903 if (status < 0)
4893 break; 4904 break;
4894 status = Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4905 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4895 if (status < 0) 4906 if (status < 0)
4896 break; 4907 break;
4897 status = Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4908 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4898 if (status < 0) 4909 if (status < 0)
4899 break; 4910 break;
4900 status = Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4911 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4901 if (status < 0) 4912 if (status < 0)
4902 break; 4913 break;
4903 status = Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4914 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4904 if (status < 0) 4915 if (status < 0)
4905 break; 4916 break;
4906 status = Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4917 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4907 if (status < 0) 4918 if (status < 0)
4908 break; 4919 break;
4909 status = Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4920 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4910 if (status < 0) 4921 if (status < 0)
4911 break; 4922 break;
4912 4923
4913 status = Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4924 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4914 if (status < 0) 4925 if (status < 0)
4915 break; 4926 break;
4916 status = Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); 4927 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4917 if (status < 0) 4928 if (status < 0)
4918 break; 4929 break;
4919 status = Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120); 4930 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4920 if (status < 0) 4931 if (status < 0)
4921 break; 4932 break;
4922 status = Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4933 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4923 if (status < 0) 4934 if (status < 0)
4924 break; 4935 break;
4925 status = Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40); 4936 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4926 if (status < 0) 4937 if (status < 0)
4927 break; 4938 break;
4928 status = Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60); 4939 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4929 if (status < 0) 4940 if (status < 0)
4930 break; 4941 break;
4931 status = Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4942 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4932 if (status < 0) 4943 if (status < 0)
4933 break; 4944 break;
4934 status = Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); 4945 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4935 if (status < 0) 4946 if (status < 0)
4936 break; 4947 break;
4937 status = Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64); 4948 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4938 if (status < 0) 4949 if (status < 0)
4939 break; 4950 break;
4940 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4951 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4941 if (status < 0) 4952 if (status < 0)
4942 break; 4953 break;
4943 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4954 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4944 if (status < 0) 4955 if (status < 0)
4945 break; 4956 break;
4946 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); 4957 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4947 if (status < 0) 4958 if (status < 0)
4948 break; 4959 break;
4949 4960
4950 4961
4951 /* QAM State Machine (FSM) Thresholds */ 4962 /* QAM State Machine (FSM) Thresholds */
4952 4963
4953 status = Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50); 4964 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4954 if (status < 0) 4965 if (status < 0)
4955 break; 4966 break;
4956 status = Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60); 4967 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4957 if (status < 0) 4968 if (status < 0)
4958 break; 4969 break;
4959 status = Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80); 4970 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4960 if (status < 0) 4971 if (status < 0)
4961 break; 4972 break;
4962 status = Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100); 4973 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4963 if (status < 0) 4974 if (status < 0)
4964 break; 4975 break;
4965 status = Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 140); 4976 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4966 if (status < 0) 4977 if (status < 0)
4967 break; 4978 break;
4968 status = Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100); 4979 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4969 if (status < 0) 4980 if (status < 0)
4970 break; 4981 break;
4971 4982
4972 status = Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4983 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4973 if (status < 0) 4984 if (status < 0)
4974 break; 4985 break;
4975 status = Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5); 4986 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
4976 if (status < 0) 4987 if (status < 0)
4977 break; 4988 break;
4978 4989
4979 status = Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); 4990 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
4980 if (status < 0) 4991 if (status < 0)
4981 break; 4992 break;
4982 4993
4983 /* QAM FSM Tracking Parameters */ 4994 /* QAM FSM Tracking Parameters */
4984 4995
4985 status = Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); 4996 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
4986 if (status < 0) 4997 if (status < 0)
4987 break; 4998 break;
4988 status = Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65); 4999 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
4989 if (status < 0) 5000 if (status < 0)
4990 break; 5001 break;
4991 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5); 5002 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
4992 if (status < 0) 5003 if (status < 0)
4993 break; 5004 break;
4994 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3); 5005 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
4995 if (status < 0) 5006 if (status < 0)
4996 break; 5007 break;
4997 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1); 5008 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
4998 if (status < 0) 5009 if (status < 0)
4999 break; 5010 break;
5000 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12); 5011 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5001 if (status < 0) 5012 if (status < 0)
5002 break; 5013 break;
5003 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); 5014 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5004 if (status < 0) 5015 if (status < 0)
5005 break; 5016 break;
5006 } while (0); 5017 } while (0);
@@ -5023,180 +5034,180 @@ static int SetQAM256(struct drxk_state *state)
5023 do { 5034 do {
5024 /* QAM Equalizer Setup */ 5035 /* QAM Equalizer Setup */
5025 /* Equalizer */ 5036 /* Equalizer */
5026 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502); 5037 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5027 if (status < 0) 5038 if (status < 0)
5028 break; 5039 break;
5029 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084); 5040 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5030 if (status < 0) 5041 if (status < 0)
5031 break; 5042 break;
5032 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543); 5043 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5033 if (status < 0) 5044 if (status < 0)
5034 break; 5045 break;
5035 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931); 5046 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5036 if (status < 0) 5047 if (status < 0)
5037 break; 5048 break;
5038 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629); 5049 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5039 if (status < 0) 5050 if (status < 0)
5040 break; 5051 break;
5041 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385); 5052 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5042 if (status < 0) 5053 if (status < 0)
5043 break; 5054 break;
5044 5055
5045 /* Decision Feedback Equalizer */ 5056 /* Decision Feedback Equalizer */
5046 status = Write16_0(state, QAM_DQ_QUAL_FUN0__A, 8); 5057 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5047 if (status < 0) 5058 if (status < 0)
5048 break; 5059 break;
5049 status = Write16_0(state, QAM_DQ_QUAL_FUN1__A, 8); 5060 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5050 if (status < 0) 5061 if (status < 0)
5051 break; 5062 break;
5052 status = Write16_0(state, QAM_DQ_QUAL_FUN2__A, 8); 5063 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5053 if (status < 0) 5064 if (status < 0)
5054 break; 5065 break;
5055 status = Write16_0(state, QAM_DQ_QUAL_FUN3__A, 8); 5066 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5056 if (status < 0) 5067 if (status < 0)
5057 break; 5068 break;
5058 status = Write16_0(state, QAM_DQ_QUAL_FUN4__A, 6); 5069 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5059 if (status < 0) 5070 if (status < 0)
5060 break; 5071 break;
5061 status = Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0); 5072 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5062 if (status < 0) 5073 if (status < 0)
5063 break; 5074 break;
5064 5075
5065 status = Write16_0(state, QAM_SY_SYNC_HWM__A, 5); 5076 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5066 if (status < 0) 5077 if (status < 0)
5067 break; 5078 break;
5068 status = Write16_0(state, QAM_SY_SYNC_AWM__A, 4); 5079 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5069 if (status < 0) 5080 if (status < 0)
5070 break; 5081 break;
5071 status = Write16_0(state, QAM_SY_SYNC_LWM__A, 3); 5082 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5072 if (status < 0) 5083 if (status < 0)
5073 break; 5084 break;
5074 5085
5075 /* QAM Slicer Settings */ 5086 /* QAM Slicer Settings */
5076 5087
5077 status = Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256); 5088 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5078 if (status < 0) 5089 if (status < 0)
5079 break; 5090 break;
5080 5091
5081 5092
5082 /* QAM Loop Controller Coeficients */ 5093 /* QAM Loop Controller Coeficients */
5083 5094
5084 status = Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 5095 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5085 if (status < 0) 5096 if (status < 0)
5086 break; 5097 break;
5087 status = Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 5098 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5088 if (status < 0) 5099 if (status < 0)
5089 break; 5100 break;
5090 status = Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 5101 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5091 if (status < 0) 5102 if (status < 0)
5092 break; 5103 break;
5093 status = Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 5104 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5094 if (status < 0) 5105 if (status < 0)
5095 break; 5106 break;
5096 status = Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 5107 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5097 if (status < 0) 5108 if (status < 0)
5098 break; 5109 break;
5099 status = Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 5110 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5100 if (status < 0) 5111 if (status < 0)
5101 break; 5112 break;
5102 status = Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 5113 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5103 if (status < 0) 5114 if (status < 0)
5104 break; 5115 break;
5105 status = Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 5116 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5106 if (status < 0) 5117 if (status < 0)
5107 break; 5118 break;
5108 5119
5109 status = Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 5120 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5110 if (status < 0) 5121 if (status < 0)
5111 break; 5122 break;
5112 status = Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); 5123 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5113 if (status < 0) 5124 if (status < 0)
5114 break; 5125 break;
5115 status = Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250); 5126 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5116 if (status < 0) 5127 if (status < 0)
5117 break; 5128 break;
5118 status = Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 5129 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5119 if (status < 0) 5130 if (status < 0)
5120 break; 5131 break;
5121 status = Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50); 5132 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5122 if (status < 0) 5133 if (status < 0)
5123 break; 5134 break;
5124 status = Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125); 5135 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5125 if (status < 0) 5136 if (status < 0)
5126 break; 5137 break;
5127 status = Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 5138 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5128 if (status < 0) 5139 if (status < 0)
5129 break; 5140 break;
5130 status = Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); 5141 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5131 if (status < 0) 5142 if (status < 0)
5132 break; 5143 break;
5133 status = Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); 5144 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5134 if (status < 0) 5145 if (status < 0)
5135 break; 5146 break;
5136 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 5147 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5137 if (status < 0) 5148 if (status < 0)
5138 break; 5149 break;
5139 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 5150 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5140 if (status < 0) 5151 if (status < 0)
5141 break; 5152 break;
5142 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); 5153 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5143 if (status < 0) 5154 if (status < 0)
5144 break; 5155 break;
5145 5156
5146 5157
5147 /* QAM State Machine (FSM) Thresholds */ 5158 /* QAM State Machine (FSM) Thresholds */
5148 5159
5149 status = Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50); 5160 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5150 if (status < 0) 5161 if (status < 0)
5151 break; 5162 break;
5152 status = Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60); 5163 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5153 if (status < 0) 5164 if (status < 0)
5154 break; 5165 break;
5155 status = Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80); 5166 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5156 if (status < 0) 5167 if (status < 0)
5157 break; 5168 break;
5158 status = Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100); 5169 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5159 if (status < 0) 5170 if (status < 0)
5160 break; 5171 break;
5161 status = Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 150); 5172 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5162 if (status < 0) 5173 if (status < 0)
5163 break; 5174 break;
5164 status = Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 110); 5175 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5165 if (status < 0) 5176 if (status < 0)
5166 break; 5177 break;
5167 5178
5168 status = Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 5179 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5169 if (status < 0) 5180 if (status < 0)
5170 break; 5181 break;
5171 status = Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 5182 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5172 if (status < 0) 5183 if (status < 0)
5173 break; 5184 break;
5174 status = Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); 5185 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5175 if (status < 0) 5186 if (status < 0)
5176 break; 5187 break;
5177 5188
5178 5189
5179 /* QAM FSM Tracking Parameters */ 5190 /* QAM FSM Tracking Parameters */
5180 5191
5181 status = Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); 5192 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5182 if (status < 0) 5193 if (status < 0)
5183 break; 5194 break;
5184 status = Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74); 5195 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5185 if (status < 0) 5196 if (status < 0)
5186 break; 5197 break;
5187 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18); 5198 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5188 if (status < 0) 5199 if (status < 0)
5189 break; 5200 break;
5190 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13); 5201 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5191 if (status < 0) 5202 if (status < 0)
5192 break; 5203 break;
5193 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7); 5204 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5194 if (status < 0) 5205 if (status < 0)
5195 break; 5206 break;
5196 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0); 5207 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5197 if (status < 0) 5208 if (status < 0)
5198 break; 5209 break;
5199 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); 5210 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5200 if (status < 0) 5211 if (status < 0)
5201 break; 5212 break;
5202 } while (0); 5213 } while (0);
@@ -5220,7 +5231,7 @@ static int QAMResetQAM(struct drxk_state *state)
5220 dprintk(1, "\n"); 5231 dprintk(1, "\n");
5221 do { 5232 do {
5222 /* Stop QAM comstate->m_exec */ 5233 /* Stop QAM comstate->m_exec */
5223 status = Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); 5234 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5224 if (status < 0) 5235 if (status < 0)
5225 break; 5236 break;
5226 5237
@@ -5262,7 +5273,7 @@ static int QAMSetSymbolrate(struct drxk_state *state)
5262 ratesel = 2; 5273 ratesel = 2;
5263 else if (state->param.u.qam.symbol_rate <= 4755000) 5274 else if (state->param.u.qam.symbol_rate <= 4755000)
5264 ratesel = 1; 5275 ratesel = 1;
5265 status = Write16_0(state, IQM_FD_RATESEL__A, ratesel); 5276 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5266 if (status < 0) 5277 if (status < 0)
5267 break; 5278 break;
5268 5279
@@ -5277,7 +5288,7 @@ static int QAMSetSymbolrate(struct drxk_state *state)
5277 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) + 5288 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5278 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) - 5289 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5279 (1 << 23); 5290 (1 << 23);
5280 status = Write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate, 0); 5291 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5281 if (status < 0) 5292 if (status < 0)
5282 break; 5293 break;
5283 state->m_iqmRcRate = iqmRcRate; 5294 state->m_iqmRcRate = iqmRcRate;
@@ -5294,7 +5305,7 @@ static int QAMSetSymbolrate(struct drxk_state *state)
5294 16); 5305 16);
5295 if (lcSymbRate > 511) 5306 if (lcSymbRate > 511)
5296 lcSymbRate = 511; 5307 lcSymbRate = 511;
5297 status = Write16_0(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate); 5308 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5298 if (status < 0) 5309 if (status < 0)
5299 break; 5310 break;
5300 } while (0); 5311 } while (0);
@@ -5368,10 +5379,10 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5368 resets QAM block 5379 resets QAM block
5369 resets SCU variables 5380 resets SCU variables
5370 */ 5381 */
5371 status = Write16_0(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP); 5382 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5372 if (status < 0) 5383 if (status < 0)
5373 break; 5384 break;
5374 status = Write16_0(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP); 5385 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5375 if (status < 0) 5386 if (status < 0)
5376 break; 5387 break;
5377 status = QAMResetQAM(state); 5388 status = QAMResetQAM(state);
@@ -5446,80 +5457,80 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5446 break; 5457 break;
5447 5458
5448 /* Reset default values */ 5459 /* Reset default values */
5449 status = Write16_0(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); 5460 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5450 if (status < 0) 5461 if (status < 0)
5451 break; 5462 break;
5452 status = Write16_0(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); 5463 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5453 if (status < 0) 5464 if (status < 0)
5454 break; 5465 break;
5455 5466
5456 /* Reset default LC values */ 5467 /* Reset default LC values */
5457 status = Write16_0(state, QAM_LC_RATE_LIMIT__A, 3); 5468 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5458 if (status < 0) 5469 if (status < 0)
5459 break; 5470 break;
5460 status = Write16_0(state, QAM_LC_LPF_FACTORP__A, 4); 5471 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5461 if (status < 0) 5472 if (status < 0)
5462 break; 5473 break;
5463 status = Write16_0(state, QAM_LC_LPF_FACTORI__A, 4); 5474 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5464 if (status < 0) 5475 if (status < 0)
5465 break; 5476 break;
5466 status = Write16_0(state, QAM_LC_MODE__A, 7); 5477 status = write16(state, QAM_LC_MODE__A, 7);
5467 if (status < 0) 5478 if (status < 0)
5468 break; 5479 break;
5469 5480
5470 status = Write16_0(state, QAM_LC_QUAL_TAB0__A, 1); 5481 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5471 if (status < 0) 5482 if (status < 0)
5472 break; 5483 break;
5473 status = Write16_0(state, QAM_LC_QUAL_TAB1__A, 1); 5484 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5474 if (status < 0) 5485 if (status < 0)
5475 break; 5486 break;
5476 status = Write16_0(state, QAM_LC_QUAL_TAB2__A, 1); 5487 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5477 if (status < 0) 5488 if (status < 0)
5478 break; 5489 break;
5479 status = Write16_0(state, QAM_LC_QUAL_TAB3__A, 1); 5490 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5480 if (status < 0) 5491 if (status < 0)
5481 break; 5492 break;
5482 status = Write16_0(state, QAM_LC_QUAL_TAB4__A, 2); 5493 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5483 if (status < 0) 5494 if (status < 0)
5484 break; 5495 break;
5485 status = Write16_0(state, QAM_LC_QUAL_TAB5__A, 2); 5496 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5486 if (status < 0) 5497 if (status < 0)
5487 break; 5498 break;
5488 status = Write16_0(state, QAM_LC_QUAL_TAB6__A, 2); 5499 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5489 if (status < 0) 5500 if (status < 0)
5490 break; 5501 break;
5491 status = Write16_0(state, QAM_LC_QUAL_TAB8__A, 2); 5502 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5492 if (status < 0) 5503 if (status < 0)
5493 break; 5504 break;
5494 status = Write16_0(state, QAM_LC_QUAL_TAB9__A, 2); 5505 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5495 if (status < 0) 5506 if (status < 0)
5496 break; 5507 break;
5497 status = Write16_0(state, QAM_LC_QUAL_TAB10__A, 2); 5508 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5498 if (status < 0) 5509 if (status < 0)
5499 break; 5510 break;
5500 status = Write16_0(state, QAM_LC_QUAL_TAB12__A, 2); 5511 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5501 if (status < 0) 5512 if (status < 0)
5502 break; 5513 break;
5503 status = Write16_0(state, QAM_LC_QUAL_TAB15__A, 3); 5514 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5504 if (status < 0) 5515 if (status < 0)
5505 break; 5516 break;
5506 status = Write16_0(state, QAM_LC_QUAL_TAB16__A, 3); 5517 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5507 if (status < 0) 5518 if (status < 0)
5508 break; 5519 break;
5509 status = Write16_0(state, QAM_LC_QUAL_TAB20__A, 4); 5520 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5510 if (status < 0) 5521 if (status < 0)
5511 break; 5522 break;
5512 status = Write16_0(state, QAM_LC_QUAL_TAB25__A, 4); 5523 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5513 if (status < 0) 5524 if (status < 0)
5514 break; 5525 break;
5515 5526
5516 /* Mirroring, QAM-block starting point not inverted */ 5527 /* Mirroring, QAM-block starting point not inverted */
5517 status = Write16_0(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS); 5528 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5518 if (status < 0) 5529 if (status < 0)
5519 break; 5530 break;
5520 5531
5521 /* Halt SCU to enable safe non-atomic accesses */ 5532 /* Halt SCU to enable safe non-atomic accesses */
5522 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 5533 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5523 if (status < 0) 5534 if (status < 0)
5524 break; 5535 break;
5525 5536
@@ -5556,7 +5567,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5556 break; 5567 break;
5557 } /* switch */ 5568 } /* switch */
5558 /* Activate SCU to enable SCU commands */ 5569 /* Activate SCU to enable SCU commands */
5559 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 5570 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5560 if (status < 0) 5571 if (status < 0)
5561 break; 5572 break;
5562 5573
@@ -5572,13 +5583,13 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5572 status = MPEGTSStart(state); 5583 status = MPEGTSStart(state);
5573 if (status < 0) 5584 if (status < 0)
5574 break; 5585 break;
5575 status = Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); 5586 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5576 if (status < 0) 5587 if (status < 0)
5577 break; 5588 break;
5578 status = Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); 5589 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5579 if (status < 0) 5590 if (status < 0)
5580 break; 5591 break;
5581 status = Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); 5592 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5582 if (status < 0) 5593 if (status < 0)
5583 break; 5594 break;
5584 5595
@@ -5626,10 +5637,10 @@ static int SetQAMStandard(struct drxk_state *state,
5626 5637
5627 /* Setup IQM */ 5638 /* Setup IQM */
5628 5639
5629 status = Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); 5640 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5630 if (status < 0) 5641 if (status < 0)
5631 break; 5642 break;
5632 status = Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); 5643 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5633 if (status < 0) 5644 if (status < 0)
5634 break; 5645 break;
5635 5646
@@ -5656,65 +5667,65 @@ static int SetQAMStandard(struct drxk_state *state,
5656 if (status < 0) 5667 if (status < 0)
5657 break; 5668 break;
5658 5669
5659 status = Write16_0(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B)); 5670 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5660 if (status < 0) 5671 if (status < 0)
5661 break; 5672 break;
5662 status = Write16_0(state, IQM_CF_SYMMETRIC__A, 0); 5673 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5663 if (status < 0) 5674 if (status < 0)
5664 break; 5675 break;
5665 status = Write16_0(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B))); 5676 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5666 if (status < 0) 5677 if (status < 0)
5667 break; 5678 break;
5668 5679
5669 status = Write16_0(state, IQM_RC_STRETCH__A, 21); 5680 status = write16(state, IQM_RC_STRETCH__A, 21);
5670 if (status < 0) 5681 if (status < 0)
5671 break; 5682 break;
5672 status = Write16_0(state, IQM_AF_CLP_LEN__A, 0); 5683 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5673 if (status < 0) 5684 if (status < 0)
5674 break; 5685 break;
5675 status = Write16_0(state, IQM_AF_CLP_TH__A, 448); 5686 status = write16(state, IQM_AF_CLP_TH__A, 448);
5676 if (status < 0) 5687 if (status < 0)
5677 break; 5688 break;
5678 status = Write16_0(state, IQM_AF_SNS_LEN__A, 0); 5689 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5679 if (status < 0) 5690 if (status < 0)
5680 break; 5691 break;
5681 status = Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 0); 5692 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5682 if (status < 0) 5693 if (status < 0)
5683 break; 5694 break;
5684 5695
5685 status = Write16_0(state, IQM_FS_ADJ_SEL__A, 1); 5696 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5686 if (status < 0) 5697 if (status < 0)
5687 break; 5698 break;
5688 status = Write16_0(state, IQM_RC_ADJ_SEL__A, 1); 5699 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5689 if (status < 0) 5700 if (status < 0)
5690 break; 5701 break;
5691 status = Write16_0(state, IQM_CF_ADJ_SEL__A, 1); 5702 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5692 if (status < 0) 5703 if (status < 0)
5693 break; 5704 break;
5694 status = Write16_0(state, IQM_AF_UPD_SEL__A, 0); 5705 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5695 if (status < 0) 5706 if (status < 0)
5696 break; 5707 break;
5697 5708
5698 /* IQM Impulse Noise Processing Unit */ 5709 /* IQM Impulse Noise Processing Unit */
5699 status = Write16_0(state, IQM_CF_CLP_VAL__A, 500); 5710 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5700 if (status < 0) 5711 if (status < 0)
5701 break; 5712 break;
5702 status = Write16_0(state, IQM_CF_DATATH__A, 1000); 5713 status = write16(state, IQM_CF_DATATH__A, 1000);
5703 if (status < 0) 5714 if (status < 0)
5704 break; 5715 break;
5705 status = Write16_0(state, IQM_CF_BYPASSDET__A, 1); 5716 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5706 if (status < 0) 5717 if (status < 0)
5707 break; 5718 break;
5708 status = Write16_0(state, IQM_CF_DET_LCT__A, 0); 5719 status = write16(state, IQM_CF_DET_LCT__A, 0);
5709 if (status < 0) 5720 if (status < 0)
5710 break; 5721 break;
5711 status = Write16_0(state, IQM_CF_WND_LEN__A, 1); 5722 status = write16(state, IQM_CF_WND_LEN__A, 1);
5712 if (status < 0) 5723 if (status < 0)
5713 break; 5724 break;
5714 status = Write16_0(state, IQM_CF_PKDTH__A, 1); 5725 status = write16(state, IQM_CF_PKDTH__A, 1);
5715 if (status < 0) 5726 if (status < 0)
5716 break; 5727 break;
5717 status = Write16_0(state, IQM_AF_INC_BYPASS__A, 1); 5728 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5718 if (status < 0) 5729 if (status < 0)
5719 break; 5730 break;
5720 5731
@@ -5722,7 +5733,7 @@ static int SetQAMStandard(struct drxk_state *state,
5722 status = SetIqmAf(state, true); 5733 status = SetIqmAf(state, true);
5723 if (status < 0) 5734 if (status < 0)
5724 break; 5735 break;
5725 status = Write16_0(state, IQM_AF_START_LOCK__A, 0x01); 5736 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5726 if (status < 0) 5737 if (status < 0)
5727 break; 5738 break;
5728 5739
@@ -5732,12 +5743,12 @@ static int SetQAMStandard(struct drxk_state *state,
5732 break; 5743 break;
5733 5744
5734 /* Set the FSM step period */ 5745 /* Set the FSM step period */
5735 status = Write16_0(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000); 5746 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5736 if (status < 0) 5747 if (status < 0)
5737 break; 5748 break;
5738 5749
5739 /* Halt SCU to enable safe non-atomic accesses */ 5750 /* Halt SCU to enable safe non-atomic accesses */
5740 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 5751 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5741 if (status < 0) 5752 if (status < 0)
5742 break; 5753 break;
5743 5754
@@ -5760,7 +5771,7 @@ static int SetQAMStandard(struct drxk_state *state,
5760 break; 5771 break;
5761 5772
5762 /* Activate SCU to enable SCU commands */ 5773 /* Activate SCU to enable SCU commands */
5763 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 5774 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5764 if (status < 0) 5775 if (status < 0)
5765 break; 5776 break;
5766 } while (0); 5777 } while (0);
@@ -5775,23 +5786,23 @@ static int WriteGPIO(struct drxk_state *state)
5775 dprintk(1, "\n"); 5786 dprintk(1, "\n");
5776 do { 5787 do {
5777 /* stop lock indicator process */ 5788 /* stop lock indicator process */
5778 status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 5789 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5779 if (status < 0) 5790 if (status < 0)
5780 break; 5791 break;
5781 5792
5782 /* Write magic word to enable pdr reg write */ 5793 /* Write magic word to enable pdr reg write */
5783 status = Write16_0(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 5794 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5784 if (status < 0) 5795 if (status < 0)
5785 break; 5796 break;
5786 5797
5787 if (state->m_hasSAWSW) { 5798 if (state->m_hasSAWSW) {
5788 /* write to io pad configuration register - output mode */ 5799 /* write to io pad configuration register - output mode */
5789 status = Write16_0(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg); 5800 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5790 if (status < 0) 5801 if (status < 0)
5791 break; 5802 break;
5792 5803
5793 /* use corresponding bit in io data output registar */ 5804 /* use corresponding bit in io data output registar */
5794 status = Read16_0(state, SIO_PDR_UIO_OUT_LO__A, &value); 5805 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5795 if (status < 0) 5806 if (status < 0)
5796 break; 5807 break;
5797 if (state->m_GPIO == 0) 5808 if (state->m_GPIO == 0)
@@ -5799,13 +5810,13 @@ static int WriteGPIO(struct drxk_state *state)
5799 else 5810 else
5800 value |= 0x8000; /* write one to 15th bit - 1st UIO */ 5811 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5801 /* write back to io data output register */ 5812 /* write back to io data output register */
5802 status = Write16_0(state, SIO_PDR_UIO_OUT_LO__A, value); 5813 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5803 if (status < 0) 5814 if (status < 0)
5804 break; 5815 break;
5805 5816
5806 } 5817 }
5807 /* Write magic word to disable pdr reg write */ 5818 /* Write magic word to disable pdr reg write */
5808 status = Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000); 5819 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5809 if (status < 0) 5820 if (status < 0)
5810 break; 5821 break;
5811 } while (0); 5822 } while (0);
@@ -5864,10 +5875,10 @@ static int PowerDownDevice(struct drxk_state *state)
5864 if (status < 0) 5875 if (status < 0)
5865 break; 5876 break;
5866 5877
5867 status = Write16_0(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK); 5878 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
5868 if (status < 0) 5879 if (status < 0)
5869 break; 5880 break;
5870 status = Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 5881 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5871 if (status < 0) 5882 if (status < 0)
5872 break; 5883 break;
5873 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 5884 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
@@ -5918,10 +5929,10 @@ static int init_drxk(struct drxk_state *state)
5918 if (status < 0) 5929 if (status < 0)
5919 break; 5930 break;
5920 /* Soft reset of OFDM-, sys- and osc-clockdomain */ 5931 /* Soft reset of OFDM-, sys- and osc-clockdomain */
5921 status = Write16_0(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M); 5932 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
5922 if (status < 0) 5933 if (status < 0)
5923 break; 5934 break;
5924 status = Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 5935 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5925 if (status < 0) 5936 if (status < 0)
5926 break; 5937 break;
5927 /* TODO is this needed, if yes how much delay in worst case scenario */ 5938 /* TODO is this needed, if yes how much delay in worst case scenario */
@@ -5957,7 +5968,7 @@ static int init_drxk(struct drxk_state *state)
5957 && !(state->m_DRXK_A2_ROM_CODE)) 5968 && !(state->m_DRXK_A2_ROM_CODE))
5958#endif 5969#endif
5959 { 5970 {
5960 status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 5971 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5961 if (status < 0) 5972 if (status < 0)
5962 break; 5973 break;
5963 } 5974 }
@@ -5968,20 +5979,20 @@ static int init_drxk(struct drxk_state *state)
5968 break; 5979 break;
5969 5980
5970 /* Stop AUD and SCU */ 5981 /* Stop AUD and SCU */
5971 status = Write16_0(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); 5982 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
5972 if (status < 0) 5983 if (status < 0)
5973 break; 5984 break;
5974 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); 5985 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
5975 if (status < 0) 5986 if (status < 0)
5976 break; 5987 break;
5977 5988
5978 /* enable token-ring bus through OFDM block for possible ucode upload */ 5989 /* enable token-ring bus through OFDM block for possible ucode upload */
5979 status = Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON); 5990 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
5980 if (status < 0) 5991 if (status < 0)
5981 break; 5992 break;
5982 5993
5983 /* include boot loader section */ 5994 /* include boot loader section */
5984 status = Write16_0(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE); 5995 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
5985 if (status < 0) 5996 if (status < 0)
5986 break; 5997 break;
5987 status = BLChainCmd(state, 0, 6, 100); 5998 status = BLChainCmd(state, 0, 6, 100);
@@ -6003,12 +6014,12 @@ static int init_drxk(struct drxk_state *state)
6003 break; 6014 break;
6004#endif 6015#endif
6005 /* disable token-ring bus through OFDM block for possible ucode upload */ 6016 /* disable token-ring bus through OFDM block for possible ucode upload */
6006 status = Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF); 6017 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6007 if (status < 0) 6018 if (status < 0)
6008 break; 6019 break;
6009 6020
6010 /* Run SCU for a little while to initialize microcode version numbers */ 6021 /* Run SCU for a little while to initialize microcode version numbers */
6011 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 6022 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6012 if (status < 0) 6023 if (status < 0)
6013 break; 6024 break;
6014 status = DRXX_Open(state); 6025 status = DRXX_Open(state);
@@ -6033,7 +6044,7 @@ static int init_drxk(struct drxk_state *state)
6033 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) + 6044 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6034 ((DRXK_VERSION_MAJOR % 10) << 4) + 6045 ((DRXK_VERSION_MAJOR % 10) << 4) +
6035 (DRXK_VERSION_MINOR % 10); 6046 (DRXK_VERSION_MINOR % 10);
6036 status = Write16_0(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion); 6047 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6037 if (status < 0) 6048 if (status < 0)
6038 break; 6049 break;
6039 driverVersion = 6050 driverVersion =
@@ -6041,7 +6052,7 @@ static int init_drxk(struct drxk_state *state)
6041 (((DRXK_VERSION_PATCH / 100) % 10) << 8) + 6052 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6042 (((DRXK_VERSION_PATCH / 10) % 10) << 4) + 6053 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6043 (DRXK_VERSION_PATCH % 10); 6054 (DRXK_VERSION_PATCH % 10);
6044 status = Write16_0(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion); 6055 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6045 if (status < 0) 6056 if (status < 0)
6046 break; 6057 break;
6047 6058
@@ -6057,13 +6068,13 @@ static int init_drxk(struct drxk_state *state)
6057 /* m_dvbtRfAgcCfg.speed = 3; */ 6068 /* m_dvbtRfAgcCfg.speed = 3; */
6058 6069
6059 /* Reset driver debug flags to 0 */ 6070 /* Reset driver debug flags to 0 */
6060 status = Write16_0(state, SCU_RAM_DRIVER_DEBUG__A, 0); 6071 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6061 if (status < 0) 6072 if (status < 0)
6062 break; 6073 break;
6063 /* driver 0.9.0 */ 6074 /* driver 0.9.0 */
6064 /* Setup FEC OC: 6075 /* Setup FEC OC:
6065 NOTE: No more full FEC resets allowed afterwards!! */ 6076 NOTE: No more full FEC resets allowed afterwards!! */
6066 status = Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); 6077 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6067 if (status < 0) 6078 if (status < 0)
6068 break; 6079 break;
6069 /* MPEGTS functions are still the same */ 6080 /* MPEGTS functions are still the same */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-03 10:53:55 -0500