diff options
author | Jie Yang <jie.yang@atheros.com> | 2009-02-18 20:24:15 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-02-18 20:24:15 -0500 |
commit | 43250ddd75a35d1f7926d989a10fefd30c37eaa7 (patch) | |
tree | ec184c27437fc303d90dbbeb9188f10dc17a09f7 | |
parent | 92a0acce186cde8ead56c6915d9479773673ea1a (diff) |
atl1c: Atheros L1C Gigabit Ethernet driver
Supporting AR8131, and AR8132.
Signed-off-by: Jie Yang <jie.yang@atheros.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/Kconfig | 11 | ||||
-rw-r--r-- | drivers/net/Makefile | 1 | ||||
-rw-r--r-- | drivers/net/atl1c/Makefile | 2 | ||||
-rw-r--r-- | drivers/net/atl1c/atl1c.h | 606 | ||||
-rw-r--r-- | drivers/net/atl1c/atl1c_ethtool.c | 317 | ||||
-rw-r--r-- | drivers/net/atl1c/atl1c_hw.c | 527 | ||||
-rw-r--r-- | drivers/net/atl1c/atl1c_hw.h | 859 | ||||
-rw-r--r-- | drivers/net/atl1c/atl1c_main.c | 2797 |
8 files changed, 5120 insertions, 0 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 6bdfd47d679d..a2f185fd7072 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig | |||
@@ -2342,6 +2342,17 @@ config ATL1E | |||
2342 | To compile this driver as a module, choose M here. The module | 2342 | To compile this driver as a module, choose M here. The module |
2343 | will be called atl1e. | 2343 | will be called atl1e. |
2344 | 2344 | ||
2345 | config ATL1C | ||
2346 | tristate "Atheros L1C Gigabit Ethernet support (EXPERIMENTAL)" | ||
2347 | depends on PCI && EXPERIMENTAL | ||
2348 | select CRC32 | ||
2349 | select MII | ||
2350 | help | ||
2351 | This driver supports the Atheros L1C gigabit ethernet adapter. | ||
2352 | |||
2353 | To compile this driver as a module, choose M here. The module | ||
2354 | will be called atl1c. | ||
2355 | |||
2345 | config JME | 2356 | config JME |
2346 | tristate "JMicron(R) PCI-Express Gigabit Ethernet support" | 2357 | tristate "JMicron(R) PCI-Express Gigabit Ethernet support" |
2347 | depends on PCI | 2358 | depends on PCI |
diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a3c5c002f224..aca8492db654 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile | |||
@@ -17,6 +17,7 @@ obj-$(CONFIG_BONDING) += bonding/ | |||
17 | obj-$(CONFIG_ATL1) += atlx/ | 17 | obj-$(CONFIG_ATL1) += atlx/ |
18 | obj-$(CONFIG_ATL2) += atlx/ | 18 | obj-$(CONFIG_ATL2) += atlx/ |
19 | obj-$(CONFIG_ATL1E) += atl1e/ | 19 | obj-$(CONFIG_ATL1E) += atl1e/ |
20 | obj-$(CONFIG_ATL1C) += atl1c/ | ||
20 | obj-$(CONFIG_GIANFAR) += gianfar_driver.o | 21 | obj-$(CONFIG_GIANFAR) += gianfar_driver.o |
21 | obj-$(CONFIG_TEHUTI) += tehuti.o | 22 | obj-$(CONFIG_TEHUTI) += tehuti.o |
22 | obj-$(CONFIG_ENIC) += enic/ | 23 | obj-$(CONFIG_ENIC) += enic/ |
diff --git a/drivers/net/atl1c/Makefile b/drivers/net/atl1c/Makefile new file mode 100644 index 000000000000..c37d966952ee --- /dev/null +++ b/drivers/net/atl1c/Makefile | |||
@@ -0,0 +1,2 @@ | |||
1 | obj-$(CONFIG_ATL1C) += atl1c.o | ||
2 | atl1c-objs := atl1c_main.o atl1c_hw.o atl1c_ethtool.o | ||
diff --git a/drivers/net/atl1c/atl1c.h b/drivers/net/atl1c/atl1c.h new file mode 100644 index 000000000000..ac11b84b8377 --- /dev/null +++ b/drivers/net/atl1c/atl1c.h | |||
@@ -0,0 +1,606 @@ | |||
1 | /* | ||
2 | * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved. | ||
3 | * | ||
4 | * Derived from Intel e1000 driver | ||
5 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License as published by the Free | ||
9 | * Software Foundation; either version 2 of the License, or (at your option) | ||
10 | * any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
15 | * more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License along with | ||
18 | * this program; if not, write to the Free Software Foundation, Inc., 59 | ||
19 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
20 | */ | ||
21 | |||
22 | #ifndef _ATL1C_H_ | ||
23 | #define _ATL1C_H_ | ||
24 | |||
25 | #include <linux/version.h> | ||
26 | #include <linux/init.h> | ||
27 | #include <linux/types.h> | ||
28 | #include <linux/errno.h> | ||
29 | #include <linux/module.h> | ||
30 | #include <linux/pci.h> | ||
31 | #include <linux/netdevice.h> | ||
32 | #include <linux/etherdevice.h> | ||
33 | #include <linux/skbuff.h> | ||
34 | #include <linux/ioport.h> | ||
35 | #include <linux/slab.h> | ||
36 | #include <linux/list.h> | ||
37 | #include <linux/delay.h> | ||
38 | #include <linux/sched.h> | ||
39 | #include <linux/in.h> | ||
40 | #include <linux/ip.h> | ||
41 | #include <linux/ipv6.h> | ||
42 | #include <linux/udp.h> | ||
43 | #include <linux/mii.h> | ||
44 | #include <linux/io.h> | ||
45 | #include <linux/vmalloc.h> | ||
46 | #include <linux/pagemap.h> | ||
47 | #include <linux/tcp.h> | ||
48 | #include <linux/mii.h> | ||
49 | #include <linux/ethtool.h> | ||
50 | #include <linux/if_vlan.h> | ||
51 | #include <linux/workqueue.h> | ||
52 | #include <net/checksum.h> | ||
53 | #include <net/ip6_checksum.h> | ||
54 | |||
55 | #include "atl1c_hw.h" | ||
56 | |||
57 | /* Wake Up Filter Control */ | ||
58 | #define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ | ||
59 | #define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ | ||
60 | #define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ | ||
61 | #define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */ | ||
62 | #define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ | ||
63 | |||
64 | #define AT_VLAN_TO_TAG(_vlan, _tag) \ | ||
65 | _tag = ((((_vlan) >> 8) & 0xFF) |\ | ||
66 | (((_vlan) & 0xFF) << 8)) | ||
67 | |||
68 | #define AT_TAG_TO_VLAN(_tag, _vlan) \ | ||
69 | _vlan = ((((_tag) >> 8) & 0xFF) |\ | ||
70 | (((_tag) & 0xFF) << 8)) | ||
71 | |||
72 | #define SPEED_0 0xffff | ||
73 | #define HALF_DUPLEX 1 | ||
74 | #define FULL_DUPLEX 2 | ||
75 | |||
76 | #define AT_RX_BUF_SIZE (ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN) | ||
77 | #define MAX_JUMBO_FRAME_SIZE (9*1024) | ||
78 | #define MAX_TX_OFFLOAD_THRESH (9*1024) | ||
79 | |||
80 | #define AT_MAX_RECEIVE_QUEUE 4 | ||
81 | #define AT_DEF_RECEIVE_QUEUE 1 | ||
82 | #define AT_MAX_TRANSMIT_QUEUE 2 | ||
83 | |||
84 | #define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL | ||
85 | #define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL | ||
86 | |||
87 | #define AT_TX_WATCHDOG (5 * HZ) | ||
88 | #define AT_MAX_INT_WORK 5 | ||
89 | #define AT_TWSI_EEPROM_TIMEOUT 100 | ||
90 | #define AT_HW_MAX_IDLE_DELAY 10 | ||
91 | #define AT_SUSPEND_LINK_TIMEOUT 28 | ||
92 | |||
93 | #define AT_ASPM_L0S_TIMER 6 | ||
94 | #define AT_ASPM_L1_TIMER 12 | ||
95 | |||
96 | #define ATL1C_PCIE_L0S_L1_DISABLE 0x01 | ||
97 | #define ATL1C_PCIE_PHY_RESET 0x02 | ||
98 | |||
99 | #define ATL1C_ASPM_L0s_ENABLE 0x0001 | ||
100 | #define ATL1C_ASPM_L1_ENABLE 0x0002 | ||
101 | |||
102 | #define AT_REGS_LEN (75 * sizeof(u32)) | ||
103 | #define AT_EEPROM_LEN 512 | ||
104 | |||
105 | #define ATL1C_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i])) | ||
106 | #define ATL1C_RFD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_rx_free_desc) | ||
107 | #define ATL1C_TPD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_tpd_desc) | ||
108 | #define ATL1C_RRD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_recv_ret_status) | ||
109 | |||
110 | /* tpd word 1 bit 0:7 General Checksum task offload */ | ||
111 | #define TPD_L4HDR_OFFSET_MASK 0x00FF | ||
112 | #define TPD_L4HDR_OFFSET_SHIFT 0 | ||
113 | |||
114 | /* tpd word 1 bit 0:7 Large Send task offload (IPv4/IPV6) */ | ||
115 | #define TPD_TCPHDR_OFFSET_MASK 0x00FF | ||
116 | #define TPD_TCPHDR_OFFSET_SHIFT 0 | ||
117 | |||
118 | /* tpd word 1 bit 0:7 Custom Checksum task offload */ | ||
119 | #define TPD_PLOADOFFSET_MASK 0x00FF | ||
120 | #define TPD_PLOADOFFSET_SHIFT 0 | ||
121 | |||
122 | /* tpd word 1 bit 8:17 */ | ||
123 | #define TPD_CCSUM_EN_MASK 0x0001 | ||
124 | #define TPD_CCSUM_EN_SHIFT 8 | ||
125 | #define TPD_IP_CSUM_MASK 0x0001 | ||
126 | #define TPD_IP_CSUM_SHIFT 9 | ||
127 | #define TPD_TCP_CSUM_MASK 0x0001 | ||
128 | #define TPD_TCP_CSUM_SHIFT 10 | ||
129 | #define TPD_UDP_CSUM_MASK 0x0001 | ||
130 | #define TPD_UDP_CSUM_SHIFT 11 | ||
131 | #define TPD_LSO_EN_MASK 0x0001 /* TCP Large Send Offload */ | ||
132 | #define TPD_LSO_EN_SHIFT 12 | ||
133 | #define TPD_LSO_VER_MASK 0x0001 | ||
134 | #define TPD_LSO_VER_SHIFT 13 /* 0 : ipv4; 1 : ipv4/ipv6 */ | ||
135 | #define TPD_CON_VTAG_MASK 0x0001 | ||
136 | #define TPD_CON_VTAG_SHIFT 14 | ||
137 | #define TPD_INS_VTAG_MASK 0x0001 | ||
138 | #define TPD_INS_VTAG_SHIFT 15 | ||
139 | #define TPD_IPV4_PACKET_MASK 0x0001 /* valid when LSO VER is 1 */ | ||
140 | #define TPD_IPV4_PACKET_SHIFT 16 | ||
141 | #define TPD_ETH_TYPE_MASK 0x0001 | ||
142 | #define TPD_ETH_TYPE_SHIFT 17 /* 0 : 802.3 frame; 1 : Ethernet */ | ||
143 | |||
144 | /* tpd word 18:25 Custom Checksum task offload */ | ||
145 | #define TPD_CCSUM_OFFSET_MASK 0x00FF | ||
146 | #define TPD_CCSUM_OFFSET_SHIFT 18 | ||
147 | #define TPD_CCSUM_EPAD_MASK 0x0001 | ||
148 | #define TPD_CCSUM_EPAD_SHIFT 30 | ||
149 | |||
150 | /* tpd word 18:30 Large Send task offload (IPv4/IPV6) */ | ||
151 | #define TPD_MSS_MASK 0x1FFF | ||
152 | #define TPD_MSS_SHIFT 18 | ||
153 | |||
154 | #define TPD_EOP_MASK 0x0001 | ||
155 | #define TPD_EOP_SHIFT 31 | ||
156 | |||
157 | struct atl1c_tpd_desc { | ||
158 | __le16 buffer_len; /* include 4-byte CRC */ | ||
159 | __le16 vlan_tag; | ||
160 | __le32 word1; | ||
161 | __le64 buffer_addr; | ||
162 | }; | ||
163 | |||
164 | struct atl1c_tpd_ext_desc { | ||
165 | u32 reservd_0; | ||
166 | __le32 word1; | ||
167 | __le32 pkt_len; | ||
168 | u32 reservd_1; | ||
169 | }; | ||
170 | /* rrs word 0 bit 0:31 */ | ||
171 | #define RRS_RX_CSUM_MASK 0xFFFF | ||
172 | #define RRS_RX_CSUM_SHIFT 0 | ||
173 | #define RRS_RX_RFD_CNT_MASK 0x000F | ||
174 | #define RRS_RX_RFD_CNT_SHIFT 16 | ||
175 | #define RRS_RX_RFD_INDEX_MASK 0x0FFF | ||
176 | #define RRS_RX_RFD_INDEX_SHIFT 20 | ||
177 | |||
178 | /* rrs flag bit 0:16 */ | ||
179 | #define RRS_HEAD_LEN_MASK 0x00FF | ||
180 | #define RRS_HEAD_LEN_SHIFT 0 | ||
181 | #define RRS_HDS_TYPE_MASK 0x0003 | ||
182 | #define RRS_HDS_TYPE_SHIFT 8 | ||
183 | #define RRS_CPU_NUM_MASK 0x0003 | ||
184 | #define RRS_CPU_NUM_SHIFT 10 | ||
185 | #define RRS_HASH_FLG_MASK 0x000F | ||
186 | #define RRS_HASH_FLG_SHIFT 12 | ||
187 | |||
188 | #define RRS_HDS_TYPE_HEAD 1 | ||
189 | #define RRS_HDS_TYPE_DATA 2 | ||
190 | |||
191 | #define RRS_IS_NO_HDS_TYPE(flag) \ | ||
192 | (((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK == 0) | ||
193 | |||
194 | #define RRS_IS_HDS_HEAD(flag) \ | ||
195 | (((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK == \ | ||
196 | RRS_HDS_TYPE_HEAD) | ||
197 | |||
198 | #define RRS_IS_HDS_DATA(flag) \ | ||
199 | (((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK == \ | ||
200 | RRS_HDS_TYPE_DATA) | ||
201 | |||
202 | /* rrs word 3 bit 0:31 */ | ||
203 | #define RRS_PKT_SIZE_MASK 0x3FFF | ||
204 | #define RRS_PKT_SIZE_SHIFT 0 | ||
205 | #define RRS_ERR_L4_CSUM_MASK 0x0001 | ||
206 | #define RRS_ERR_L4_CSUM_SHIFT 14 | ||
207 | #define RRS_ERR_IP_CSUM_MASK 0x0001 | ||
208 | #define RRS_ERR_IP_CSUM_SHIFT 15 | ||
209 | #define RRS_VLAN_INS_MASK 0x0001 | ||
210 | #define RRS_VLAN_INS_SHIFT 16 | ||
211 | #define RRS_PROT_ID_MASK 0x0007 | ||
212 | #define RRS_PROT_ID_SHIFT 17 | ||
213 | #define RRS_RX_ERR_SUM_MASK 0x0001 | ||
214 | #define RRS_RX_ERR_SUM_SHIFT 20 | ||
215 | #define RRS_RX_ERR_CRC_MASK 0x0001 | ||
216 | #define RRS_RX_ERR_CRC_SHIFT 21 | ||
217 | #define RRS_RX_ERR_FAE_MASK 0x0001 | ||
218 | #define RRS_RX_ERR_FAE_SHIFT 22 | ||
219 | #define RRS_RX_ERR_TRUNC_MASK 0x0001 | ||
220 | #define RRS_RX_ERR_TRUNC_SHIFT 23 | ||
221 | #define RRS_RX_ERR_RUNC_MASK 0x0001 | ||
222 | #define RRS_RX_ERR_RUNC_SHIFT 24 | ||
223 | #define RRS_RX_ERR_ICMP_MASK 0x0001 | ||
224 | #define RRS_RX_ERR_ICMP_SHIFT 25 | ||
225 | #define RRS_PACKET_BCAST_MASK 0x0001 | ||
226 | #define RRS_PACKET_BCAST_SHIFT 26 | ||
227 | #define RRS_PACKET_MCAST_MASK 0x0001 | ||
228 | #define RRS_PACKET_MCAST_SHIFT 27 | ||
229 | #define RRS_PACKET_TYPE_MASK 0x0001 | ||
230 | #define RRS_PACKET_TYPE_SHIFT 28 | ||
231 | #define RRS_FIFO_FULL_MASK 0x0001 | ||
232 | #define RRS_FIFO_FULL_SHIFT 29 | ||
233 | #define RRS_802_3_LEN_ERR_MASK 0x0001 | ||
234 | #define RRS_802_3_LEN_ERR_SHIFT 30 | ||
235 | #define RRS_RXD_UPDATED_MASK 0x0001 | ||
236 | #define RRS_RXD_UPDATED_SHIFT 31 | ||
237 | |||
238 | #define RRS_ERR_L4_CSUM 0x00004000 | ||
239 | #define RRS_ERR_IP_CSUM 0x00008000 | ||
240 | #define RRS_VLAN_INS 0x00010000 | ||
241 | #define RRS_RX_ERR_SUM 0x00100000 | ||
242 | #define RRS_RX_ERR_CRC 0x00200000 | ||
243 | #define RRS_802_3_LEN_ERR 0x40000000 | ||
244 | #define RRS_RXD_UPDATED 0x80000000 | ||
245 | |||
246 | #define RRS_PACKET_TYPE_802_3 1 | ||
247 | #define RRS_PACKET_TYPE_ETH 0 | ||
248 | #define RRS_PACKET_IS_ETH(word) \ | ||
249 | (((word) >> RRS_PACKET_TYPE_SHIFT) & RRS_PACKET_TYPE_MASK == \ | ||
250 | RRS_PACKET_TYPE_ETH) | ||
251 | #define RRS_RXD_IS_VALID(word) \ | ||
252 | ((((word) >> RRS_RXD_UPDATED_SHIFT) & RRS_RXD_UPDATED_MASK) == 1) | ||
253 | |||
254 | #define RRS_PACKET_PROT_IS_IPV4_ONLY(word) \ | ||
255 | ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 1) | ||
256 | #define RRS_PACKET_PROT_IS_IPV6_ONLY(word) \ | ||
257 | ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 6) | ||
258 | |||
259 | struct atl1c_recv_ret_status { | ||
260 | __le32 word0; | ||
261 | __le32 rss_hash; | ||
262 | __le16 vlan_tag; | ||
263 | __le16 flag; | ||
264 | __le32 word3; | ||
265 | }; | ||
266 | |||
267 | /* RFD desciptor */ | ||
268 | struct atl1c_rx_free_desc { | ||
269 | __le64 buffer_addr; | ||
270 | }; | ||
271 | |||
272 | /* DMA Order Settings */ | ||
273 | enum atl1c_dma_order { | ||
274 | atl1c_dma_ord_in = 1, | ||
275 | atl1c_dma_ord_enh = 2, | ||
276 | atl1c_dma_ord_out = 4 | ||
277 | }; | ||
278 | |||
279 | enum atl1c_dma_rcb { | ||
280 | atl1c_rcb_64 = 0, | ||
281 | atl1c_rcb_128 = 1 | ||
282 | }; | ||
283 | |||
284 | enum atl1c_mac_speed { | ||
285 | atl1c_mac_speed_0 = 0, | ||
286 | atl1c_mac_speed_10_100 = 1, | ||
287 | atl1c_mac_speed_1000 = 2 | ||
288 | }; | ||
289 | |||
290 | enum atl1c_dma_req_block { | ||
291 | atl1c_dma_req_128 = 0, | ||
292 | atl1c_dma_req_256 = 1, | ||
293 | atl1c_dma_req_512 = 2, | ||
294 | atl1c_dma_req_1024 = 3, | ||
295 | atl1c_dma_req_2048 = 4, | ||
296 | atl1c_dma_req_4096 = 5 | ||
297 | }; | ||
298 | |||
299 | enum atl1c_rss_mode { | ||
300 | atl1c_rss_mode_disable = 0, | ||
301 | atl1c_rss_sig_que = 1, | ||
302 | atl1c_rss_mul_que_sig_int = 2, | ||
303 | atl1c_rss_mul_que_mul_int = 4, | ||
304 | }; | ||
305 | |||
306 | enum atl1c_rss_type { | ||
307 | atl1c_rss_disable = 0, | ||
308 | atl1c_rss_ipv4 = 1, | ||
309 | atl1c_rss_ipv4_tcp = 2, | ||
310 | atl1c_rss_ipv6 = 4, | ||
311 | atl1c_rss_ipv6_tcp = 8 | ||
312 | }; | ||
313 | |||
314 | enum atl1c_nic_type { | ||
315 | athr_l1c = 0, | ||
316 | athr_l2c = 1, | ||
317 | }; | ||
318 | |||
319 | enum atl1c_trans_queue { | ||
320 | atl1c_trans_normal = 0, | ||
321 | atl1c_trans_high = 1 | ||
322 | }; | ||
323 | |||
324 | struct atl1c_hw_stats { | ||
325 | /* rx */ | ||
326 | unsigned long rx_ok; /* The number of good packet received. */ | ||
327 | unsigned long rx_bcast; /* The number of good broadcast packet received. */ | ||
328 | unsigned long rx_mcast; /* The number of good multicast packet received. */ | ||
329 | unsigned long rx_pause; /* The number of Pause packet received. */ | ||
330 | unsigned long rx_ctrl; /* The number of Control packet received other than Pause frame. */ | ||
331 | unsigned long rx_fcs_err; /* The number of packets with bad FCS. */ | ||
332 | unsigned long rx_len_err; /* The number of packets with mismatch of length field and actual size. */ | ||
333 | unsigned long rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */ | ||
334 | unsigned long rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */ | ||
335 | unsigned long rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */ | ||
336 | unsigned long rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */ | ||
337 | unsigned long rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */ | ||
338 | unsigned long rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */ | ||
339 | unsigned long rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */ | ||
340 | unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */ | ||
341 | unsigned long rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */ | ||
342 | unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */ | ||
343 | unsigned long rx_sz_ov; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */ | ||
344 | unsigned long rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */ | ||
345 | unsigned long rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */ | ||
346 | unsigned long rx_align_err; /* Alignment Error */ | ||
347 | unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */ | ||
348 | unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */ | ||
349 | unsigned long rx_err_addr; /* The number of packets dropped due to address filtering. */ | ||
350 | |||
351 | /* tx */ | ||
352 | unsigned long tx_ok; /* The number of good packet transmitted. */ | ||
353 | unsigned long tx_bcast; /* The number of good broadcast packet transmitted. */ | ||
354 | unsigned long tx_mcast; /* The number of good multicast packet transmitted. */ | ||
355 | unsigned long tx_pause; /* The number of Pause packet transmitted. */ | ||
356 | unsigned long tx_exc_defer; /* The number of packets transmitted with excessive deferral. */ | ||
357 | unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */ | ||
358 | unsigned long tx_defer; /* The number of packets transmitted that is deferred. */ | ||
359 | unsigned long tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */ | ||
360 | unsigned long tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */ | ||
361 | unsigned long tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */ | ||
362 | unsigned long tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */ | ||
363 | unsigned long tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */ | ||
364 | unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */ | ||
365 | unsigned long tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */ | ||
366 | unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */ | ||
367 | unsigned long tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */ | ||
368 | unsigned long tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */ | ||
369 | unsigned long tx_late_col; /* The number of packets transmitted with late collisions. */ | ||
370 | unsigned long tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */ | ||
371 | unsigned long tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */ | ||
372 | unsigned long tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */ | ||
373 | unsigned long tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */ | ||
374 | unsigned long tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */ | ||
375 | unsigned long tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */ | ||
376 | unsigned long tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */ | ||
377 | }; | ||
378 | |||
379 | struct atl1c_hw { | ||
380 | u8 __iomem *hw_addr; /* inner register address */ | ||
381 | struct atl1c_adapter *adapter; | ||
382 | enum atl1c_nic_type nic_type; | ||
383 | enum atl1c_dma_order dma_order; | ||
384 | enum atl1c_dma_rcb rcb_value; | ||
385 | enum atl1c_dma_req_block dmar_block; | ||
386 | enum atl1c_dma_req_block dmaw_block; | ||
387 | |||
388 | u16 device_id; | ||
389 | u16 vendor_id; | ||
390 | u16 subsystem_id; | ||
391 | u16 subsystem_vendor_id; | ||
392 | u8 revision_id; | ||
393 | |||
394 | u32 intr_mask; | ||
395 | u8 dmaw_dly_cnt; | ||
396 | u8 dmar_dly_cnt; | ||
397 | |||
398 | u8 preamble_len; | ||
399 | u16 max_frame_size; | ||
400 | u16 min_frame_size; | ||
401 | |||
402 | enum atl1c_mac_speed mac_speed; | ||
403 | bool mac_duplex; | ||
404 | bool hibernate; | ||
405 | u16 media_type; | ||
406 | #define MEDIA_TYPE_AUTO_SENSOR 0 | ||
407 | #define MEDIA_TYPE_100M_FULL 1 | ||
408 | #define MEDIA_TYPE_100M_HALF 2 | ||
409 | #define MEDIA_TYPE_10M_FULL 3 | ||
410 | #define MEDIA_TYPE_10M_HALF 4 | ||
411 | |||
412 | u16 autoneg_advertised; | ||
413 | u16 mii_autoneg_adv_reg; | ||
414 | u16 mii_1000t_ctrl_reg; | ||
415 | |||
416 | u16 tx_imt; /* TX Interrupt Moderator timer ( 2us resolution) */ | ||
417 | u16 rx_imt; /* RX Interrupt Moderator timer ( 2us resolution) */ | ||
418 | u16 ict; /* Interrupt Clear timer (2us resolution) */ | ||
419 | u16 ctrl_flags; | ||
420 | #define ATL1C_INTR_CLEAR_ON_READ 0x0001 | ||
421 | #define ATL1C_INTR_MODRT_ENABLE 0x0002 | ||
422 | #define ATL1C_CMB_ENABLE 0x0004 | ||
423 | #define ATL1C_SMB_ENABLE 0x0010 | ||
424 | #define ATL1C_TXQ_MODE_ENHANCE 0x0020 | ||
425 | #define ATL1C_RX_IPV6_CHKSUM 0x0040 | ||
426 | #define ATL1C_ASPM_L0S_SUPPORT 0x0080 | ||
427 | #define ATL1C_ASPM_L1_SUPPORT 0x0100 | ||
428 | #define ATL1C_ASPM_CTRL_MON 0x0200 | ||
429 | #define ATL1C_HIB_DISABLE 0x0400 | ||
430 | #define ATL1C_LINK_CAP_1000M 0x0800 | ||
431 | #define ATL1C_FPGA_VERSION 0x8000 | ||
432 | u16 cmb_tpd; | ||
433 | u16 cmb_rrd; | ||
434 | u16 cmb_rx_timer; /* 2us resolution */ | ||
435 | u16 cmb_tx_timer; | ||
436 | u32 smb_timer; | ||
437 | |||
438 | u16 rrd_thresh; /* Threshold of number of RRD produced to trigger | ||
439 | interrupt request */ | ||
440 | u16 tpd_thresh; | ||
441 | u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. */ | ||
442 | u8 rfd_burst; | ||
443 | enum atl1c_rss_type rss_type; | ||
444 | enum atl1c_rss_mode rss_mode; | ||
445 | u8 rss_hash_bits; | ||
446 | u32 base_cpu; | ||
447 | u32 indirect_tab; | ||
448 | u8 mac_addr[ETH_ALEN]; | ||
449 | u8 perm_mac_addr[ETH_ALEN]; | ||
450 | |||
451 | bool phy_configured; | ||
452 | bool re_autoneg; | ||
453 | bool emi_ca; | ||
454 | }; | ||
455 | |||
456 | /* | ||
457 | * atl1c_ring_header represents a single, contiguous block of DMA space | ||
458 | * mapped for the three descriptor rings (tpd, rfd, rrd) and the two | ||
459 | * message blocks (cmb, smb) described below | ||
460 | */ | ||
461 | struct atl1c_ring_header { | ||
462 | void *desc; /* virtual address */ | ||
463 | dma_addr_t dma; /* physical address*/ | ||
464 | unsigned int size; /* length in bytes */ | ||
465 | }; | ||
466 | |||
467 | /* | ||
468 | * atl1c_buffer is wrapper around a pointer to a socket buffer | ||
469 | * so a DMA handle can be stored along with the skb | ||
470 | */ | ||
471 | struct atl1c_buffer { | ||
472 | struct sk_buff *skb; /* socket buffer */ | ||
473 | u16 length; /* rx buffer length */ | ||
474 | u16 state; /* state of buffer */ | ||
475 | #define ATL1_BUFFER_FREE 0 | ||
476 | #define ATL1_BUFFER_BUSY 1 | ||
477 | dma_addr_t dma; | ||
478 | }; | ||
479 | |||
480 | /* transimit packet descriptor (tpd) ring */ | ||
481 | struct atl1c_tpd_ring { | ||
482 | void *desc; /* descriptor ring virtual address */ | ||
483 | dma_addr_t dma; /* descriptor ring physical address */ | ||
484 | u16 size; /* descriptor ring length in bytes */ | ||
485 | u16 count; /* number of descriptors in the ring */ | ||
486 | u16 next_to_use; /* this is protectd by adapter->tx_lock */ | ||
487 | atomic_t next_to_clean; | ||
488 | struct atl1c_buffer *buffer_info; | ||
489 | }; | ||
490 | |||
491 | /* receive free descriptor (rfd) ring */ | ||
492 | struct atl1c_rfd_ring { | ||
493 | void *desc; /* descriptor ring virtual address */ | ||
494 | dma_addr_t dma; /* descriptor ring physical address */ | ||
495 | u16 size; /* descriptor ring length in bytes */ | ||
496 | u16 count; /* number of descriptors in the ring */ | ||
497 | u16 next_to_use; | ||
498 | u16 next_to_clean; | ||
499 | struct atl1c_buffer *buffer_info; | ||
500 | }; | ||
501 | |||
502 | /* receive return desciptor (rrd) ring */ | ||
503 | struct atl1c_rrd_ring { | ||
504 | void *desc; /* descriptor ring virtual address */ | ||
505 | dma_addr_t dma; /* descriptor ring physical address */ | ||
506 | u16 size; /* descriptor ring length in bytes */ | ||
507 | u16 count; /* number of descriptors in the ring */ | ||
508 | u16 next_to_use; | ||
509 | u16 next_to_clean; | ||
510 | }; | ||
511 | |||
512 | struct atl1c_cmb { | ||
513 | void *cmb; | ||
514 | dma_addr_t dma; | ||
515 | }; | ||
516 | |||
517 | struct atl1c_smb { | ||
518 | void *smb; | ||
519 | dma_addr_t dma; | ||
520 | }; | ||
521 | |||
522 | /* board specific private data structure */ | ||
523 | struct atl1c_adapter { | ||
524 | struct net_device *netdev; | ||
525 | struct pci_dev *pdev; | ||
526 | struct vlan_group *vlgrp; | ||
527 | struct napi_struct napi; | ||
528 | struct atl1c_hw hw; | ||
529 | struct atl1c_hw_stats hw_stats; | ||
530 | struct net_device_stats net_stats; | ||
531 | struct mii_if_info mii; /* MII interface info */ | ||
532 | u16 rx_buffer_len; | ||
533 | |||
534 | unsigned long flags; | ||
535 | #define __AT_TESTING 0x0001 | ||
536 | #define __AT_RESETTING 0x0002 | ||
537 | #define __AT_DOWN 0x0003 | ||
538 | u32 msg_enable; | ||
539 | |||
540 | bool have_msi; | ||
541 | u32 wol; | ||
542 | u16 link_speed; | ||
543 | u16 link_duplex; | ||
544 | |||
545 | spinlock_t mdio_lock; | ||
546 | spinlock_t tx_lock; | ||
547 | atomic_t irq_sem; | ||
548 | |||
549 | struct work_struct reset_task; | ||
550 | struct work_struct link_chg_task; | ||
551 | struct timer_list watchdog_timer; | ||
552 | struct timer_list phy_config_timer; | ||
553 | |||
554 | /* All Descriptor memory */ | ||
555 | struct atl1c_ring_header ring_header; | ||
556 | struct atl1c_tpd_ring tpd_ring[AT_MAX_TRANSMIT_QUEUE]; | ||
557 | struct atl1c_rfd_ring rfd_ring[AT_MAX_RECEIVE_QUEUE]; | ||
558 | struct atl1c_rrd_ring rrd_ring[AT_MAX_RECEIVE_QUEUE]; | ||
559 | struct atl1c_cmb cmb; | ||
560 | struct atl1c_smb smb; | ||
561 | int num_rx_queues; | ||
562 | u32 bd_number; /* board number;*/ | ||
563 | }; | ||
564 | |||
565 | #define AT_WRITE_REG(a, reg, value) ( \ | ||
566 | writel((value), ((a)->hw_addr + reg))) | ||
567 | |||
568 | #define AT_WRITE_FLUSH(a) (\ | ||
569 | readl((a)->hw_addr)) | ||
570 | |||
571 | #define AT_READ_REG(a, reg, pdata) do { \ | ||
572 | if (unlikely((a)->hibernate)) { \ | ||
573 | readl((a)->hw_addr + reg); \ | ||
574 | *(u32 *)pdata = readl((a)->hw_addr + reg); \ | ||
575 | } else { \ | ||
576 | *(u32 *)pdata = readl((a)->hw_addr + reg); \ | ||
577 | } \ | ||
578 | } while (0) | ||
579 | |||
580 | #define AT_WRITE_REGB(a, reg, value) (\ | ||
581 | writeb((value), ((a)->hw_addr + reg))) | ||
582 | |||
583 | #define AT_READ_REGB(a, reg) (\ | ||
584 | readb((a)->hw_addr + reg)) | ||
585 | |||
586 | #define AT_WRITE_REGW(a, reg, value) (\ | ||
587 | writew((value), ((a)->hw_addr + reg))) | ||
588 | |||
589 | #define AT_READ_REGW(a, reg) (\ | ||
590 | readw((a)->hw_addr + reg)) | ||
591 | |||
592 | #define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \ | ||
593 | writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))) | ||
594 | |||
595 | #define AT_READ_REG_ARRAY(a, reg, offset) ( \ | ||
596 | readl(((a)->hw_addr + reg) + ((offset) << 2))) | ||
597 | |||
598 | extern char atl1c_driver_name[]; | ||
599 | extern char atl1c_driver_version[]; | ||
600 | |||
601 | extern int atl1c_up(struct atl1c_adapter *adapter); | ||
602 | extern void atl1c_down(struct atl1c_adapter *adapter); | ||
603 | extern void atl1c_reinit_locked(struct atl1c_adapter *adapter); | ||
604 | extern s32 atl1c_reset_hw(struct atl1c_hw *hw); | ||
605 | extern void atl1c_set_ethtool_ops(struct net_device *netdev); | ||
606 | #endif /* _ATL1C_H_ */ | ||
diff --git a/drivers/net/atl1c/atl1c_ethtool.c b/drivers/net/atl1c/atl1c_ethtool.c new file mode 100644 index 000000000000..45c5b7332cd3 --- /dev/null +++ b/drivers/net/atl1c/atl1c_ethtool.c | |||
@@ -0,0 +1,317 @@ | |||
1 | /* | ||
2 | * Copyright(c) 2009 - 2009 Atheros Corporation. All rights reserved. | ||
3 | * | ||
4 | * Derived from Intel e1000 driver | ||
5 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License as published by the Free | ||
9 | * Software Foundation; either version 2 of the License, or (at your option) | ||
10 | * any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
15 | * more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License along with | ||
18 | * this program; if not, write to the Free Software Foundation, Inc., 59 | ||
19 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
20 | * | ||
21 | */ | ||
22 | |||
23 | #include <linux/netdevice.h> | ||
24 | #include <linux/ethtool.h> | ||
25 | |||
26 | #include "atl1c.h" | ||
27 | |||
28 | static int atl1c_get_settings(struct net_device *netdev, | ||
29 | struct ethtool_cmd *ecmd) | ||
30 | { | ||
31 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
32 | struct atl1c_hw *hw = &adapter->hw; | ||
33 | |||
34 | ecmd->supported = (SUPPORTED_10baseT_Half | | ||
35 | SUPPORTED_10baseT_Full | | ||
36 | SUPPORTED_100baseT_Half | | ||
37 | SUPPORTED_100baseT_Full | | ||
38 | SUPPORTED_Autoneg | | ||
39 | SUPPORTED_TP); | ||
40 | if (hw->ctrl_flags & ATL1C_LINK_CAP_1000M) | ||
41 | ecmd->supported |= SUPPORTED_1000baseT_Full; | ||
42 | |||
43 | ecmd->advertising = ADVERTISED_TP; | ||
44 | |||
45 | ecmd->advertising |= hw->autoneg_advertised; | ||
46 | |||
47 | ecmd->port = PORT_TP; | ||
48 | ecmd->phy_address = 0; | ||
49 | ecmd->transceiver = XCVR_INTERNAL; | ||
50 | |||
51 | if (adapter->link_speed != SPEED_0) { | ||
52 | ecmd->speed = adapter->link_speed; | ||
53 | if (adapter->link_duplex == FULL_DUPLEX) | ||
54 | ecmd->duplex = DUPLEX_FULL; | ||
55 | else | ||
56 | ecmd->duplex = DUPLEX_HALF; | ||
57 | } else { | ||
58 | ecmd->speed = -1; | ||
59 | ecmd->duplex = -1; | ||
60 | } | ||
61 | |||
62 | ecmd->autoneg = AUTONEG_ENABLE; | ||
63 | return 0; | ||
64 | } | ||
65 | |||
66 | static int atl1c_set_settings(struct net_device *netdev, | ||
67 | struct ethtool_cmd *ecmd) | ||
68 | { | ||
69 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
70 | struct atl1c_hw *hw = &adapter->hw; | ||
71 | u16 autoneg_advertised; | ||
72 | |||
73 | while (test_and_set_bit(__AT_RESETTING, &adapter->flags)) | ||
74 | msleep(1); | ||
75 | |||
76 | if (ecmd->autoneg == AUTONEG_ENABLE) { | ||
77 | autoneg_advertised = ADVERTISED_Autoneg; | ||
78 | } else { | ||
79 | if (ecmd->speed == SPEED_1000) { | ||
80 | if (ecmd->duplex != DUPLEX_FULL) { | ||
81 | if (netif_msg_link(adapter)) | ||
82 | dev_warn(&adapter->pdev->dev, | ||
83 | "1000M half is invalid\n"); | ||
84 | clear_bit(__AT_RESETTING, &adapter->flags); | ||
85 | return -EINVAL; | ||
86 | } | ||
87 | autoneg_advertised = ADVERTISED_1000baseT_Full; | ||
88 | } else if (ecmd->speed == SPEED_100) { | ||
89 | if (ecmd->duplex == DUPLEX_FULL) | ||
90 | autoneg_advertised = ADVERTISED_100baseT_Full; | ||
91 | else | ||
92 | autoneg_advertised = ADVERTISED_100baseT_Half; | ||
93 | } else { | ||
94 | if (ecmd->duplex == DUPLEX_FULL) | ||
95 | autoneg_advertised = ADVERTISED_10baseT_Full; | ||
96 | else | ||
97 | autoneg_advertised = ADVERTISED_10baseT_Half; | ||
98 | } | ||
99 | } | ||
100 | |||
101 | if (hw->autoneg_advertised != autoneg_advertised) { | ||
102 | hw->autoneg_advertised = autoneg_advertised; | ||
103 | if (atl1c_restart_autoneg(hw) != 0) { | ||
104 | if (netif_msg_link(adapter)) | ||
105 | dev_warn(&adapter->pdev->dev, | ||
106 | "ethtool speed/duplex setting failed\n"); | ||
107 | clear_bit(__AT_RESETTING, &adapter->flags); | ||
108 | return -EINVAL; | ||
109 | } | ||
110 | } | ||
111 | clear_bit(__AT_RESETTING, &adapter->flags); | ||
112 | return 0; | ||
113 | } | ||
114 | |||
115 | static u32 atl1c_get_tx_csum(struct net_device *netdev) | ||
116 | { | ||
117 | return (netdev->features & NETIF_F_HW_CSUM) != 0; | ||
118 | } | ||
119 | |||
120 | static u32 atl1c_get_msglevel(struct net_device *netdev) | ||
121 | { | ||
122 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
123 | return adapter->msg_enable; | ||
124 | } | ||
125 | |||
126 | static void atl1c_set_msglevel(struct net_device *netdev, u32 data) | ||
127 | { | ||
128 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
129 | adapter->msg_enable = data; | ||
130 | } | ||
131 | |||
132 | static int atl1c_get_regs_len(struct net_device *netdev) | ||
133 | { | ||
134 | return AT_REGS_LEN; | ||
135 | } | ||
136 | |||
137 | static void atl1c_get_regs(struct net_device *netdev, | ||
138 | struct ethtool_regs *regs, void *p) | ||
139 | { | ||
140 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
141 | struct atl1c_hw *hw = &adapter->hw; | ||
142 | u32 *regs_buff = p; | ||
143 | u16 phy_data; | ||
144 | |||
145 | memset(p, 0, AT_REGS_LEN); | ||
146 | |||
147 | regs->version = 0; | ||
148 | AT_READ_REG(hw, REG_VPD_CAP, p++); | ||
149 | AT_READ_REG(hw, REG_PM_CTRL, p++); | ||
150 | AT_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL, p++); | ||
151 | AT_READ_REG(hw, REG_TWSI_CTRL, p++); | ||
152 | AT_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL, p++); | ||
153 | AT_READ_REG(hw, REG_MASTER_CTRL, p++); | ||
154 | AT_READ_REG(hw, REG_MANUAL_TIMER_INIT, p++); | ||
155 | AT_READ_REG(hw, REG_IRQ_MODRT_TIMER_INIT, p++); | ||
156 | AT_READ_REG(hw, REG_GPHY_CTRL, p++); | ||
157 | AT_READ_REG(hw, REG_LINK_CTRL, p++); | ||
158 | AT_READ_REG(hw, REG_IDLE_STATUS, p++); | ||
159 | AT_READ_REG(hw, REG_MDIO_CTRL, p++); | ||
160 | AT_READ_REG(hw, REG_SERDES_LOCK, p++); | ||
161 | AT_READ_REG(hw, REG_MAC_CTRL, p++); | ||
162 | AT_READ_REG(hw, REG_MAC_IPG_IFG, p++); | ||
163 | AT_READ_REG(hw, REG_MAC_STA_ADDR, p++); | ||
164 | AT_READ_REG(hw, REG_MAC_STA_ADDR+4, p++); | ||
165 | AT_READ_REG(hw, REG_RX_HASH_TABLE, p++); | ||
166 | AT_READ_REG(hw, REG_RX_HASH_TABLE+4, p++); | ||
167 | AT_READ_REG(hw, REG_RXQ_CTRL, p++); | ||
168 | AT_READ_REG(hw, REG_TXQ_CTRL, p++); | ||
169 | AT_READ_REG(hw, REG_MTU, p++); | ||
170 | AT_READ_REG(hw, REG_WOL_CTRL, p++); | ||
171 | |||
172 | atl1c_read_phy_reg(hw, MII_BMCR, &phy_data); | ||
173 | regs_buff[73] = (u32) phy_data; | ||
174 | atl1c_read_phy_reg(hw, MII_BMSR, &phy_data); | ||
175 | regs_buff[74] = (u32) phy_data; | ||
176 | } | ||
177 | |||
178 | static int atl1c_get_eeprom_len(struct net_device *netdev) | ||
179 | { | ||
180 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
181 | |||
182 | if (atl1c_check_eeprom_exist(&adapter->hw)) | ||
183 | return AT_EEPROM_LEN; | ||
184 | else | ||
185 | return 0; | ||
186 | } | ||
187 | |||
188 | static int atl1c_get_eeprom(struct net_device *netdev, | ||
189 | struct ethtool_eeprom *eeprom, u8 *bytes) | ||
190 | { | ||
191 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
192 | struct atl1c_hw *hw = &adapter->hw; | ||
193 | u32 *eeprom_buff; | ||
194 | int first_dword, last_dword; | ||
195 | int ret_val = 0; | ||
196 | int i; | ||
197 | |||
198 | if (eeprom->len == 0) | ||
199 | return -EINVAL; | ||
200 | |||
201 | if (!atl1c_check_eeprom_exist(hw)) /* not exist */ | ||
202 | return -EINVAL; | ||
203 | |||
204 | eeprom->magic = adapter->pdev->vendor | | ||
205 | (adapter->pdev->device << 16); | ||
206 | |||
207 | first_dword = eeprom->offset >> 2; | ||
208 | last_dword = (eeprom->offset + eeprom->len - 1) >> 2; | ||
209 | |||
210 | eeprom_buff = kmalloc(sizeof(u32) * | ||
211 | (last_dword - first_dword + 1), GFP_KERNEL); | ||
212 | if (eeprom_buff == NULL) | ||
213 | return -ENOMEM; | ||
214 | |||
215 | for (i = first_dword; i < last_dword; i++) { | ||
216 | if (!atl1c_read_eeprom(hw, i * 4, &(eeprom_buff[i-first_dword]))) { | ||
217 | kfree(eeprom_buff); | ||
218 | return -EIO; | ||
219 | } | ||
220 | } | ||
221 | |||
222 | memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3), | ||
223 | eeprom->len); | ||
224 | kfree(eeprom_buff); | ||
225 | |||
226 | return ret_val; | ||
227 | return 0; | ||
228 | } | ||
229 | |||
230 | static void atl1c_get_drvinfo(struct net_device *netdev, | ||
231 | struct ethtool_drvinfo *drvinfo) | ||
232 | { | ||
233 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
234 | |||
235 | strncpy(drvinfo->driver, atl1c_driver_name, sizeof(drvinfo->driver)); | ||
236 | strncpy(drvinfo->version, atl1c_driver_version, | ||
237 | sizeof(drvinfo->version)); | ||
238 | strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); | ||
239 | strncpy(drvinfo->bus_info, pci_name(adapter->pdev), | ||
240 | sizeof(drvinfo->bus_info)); | ||
241 | drvinfo->n_stats = 0; | ||
242 | drvinfo->testinfo_len = 0; | ||
243 | drvinfo->regdump_len = atl1c_get_regs_len(netdev); | ||
244 | drvinfo->eedump_len = atl1c_get_eeprom_len(netdev); | ||
245 | } | ||
246 | |||
247 | static void atl1c_get_wol(struct net_device *netdev, | ||
248 | struct ethtool_wolinfo *wol) | ||
249 | { | ||
250 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
251 | |||
252 | wol->supported = WAKE_MAGIC | WAKE_PHY; | ||
253 | wol->wolopts = 0; | ||
254 | |||
255 | if (adapter->wol & AT_WUFC_EX) | ||
256 | wol->wolopts |= WAKE_UCAST; | ||
257 | if (adapter->wol & AT_WUFC_MC) | ||
258 | wol->wolopts |= WAKE_MCAST; | ||
259 | if (adapter->wol & AT_WUFC_BC) | ||
260 | wol->wolopts |= WAKE_BCAST; | ||
261 | if (adapter->wol & AT_WUFC_MAG) | ||
262 | wol->wolopts |= WAKE_MAGIC; | ||
263 | if (adapter->wol & AT_WUFC_LNKC) | ||
264 | wol->wolopts |= WAKE_PHY; | ||
265 | |||
266 | return; | ||
267 | } | ||
268 | |||
269 | static int atl1c_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | ||
270 | { | ||
271 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
272 | |||
273 | if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE | | ||
274 | WAKE_MCAST | WAKE_BCAST | WAKE_MCAST)) | ||
275 | return -EOPNOTSUPP; | ||
276 | /* these settings will always override what we currently have */ | ||
277 | adapter->wol = 0; | ||
278 | |||
279 | if (wol->wolopts & WAKE_MAGIC) | ||
280 | adapter->wol |= AT_WUFC_MAG; | ||
281 | if (wol->wolopts & WAKE_PHY) | ||
282 | adapter->wol |= AT_WUFC_LNKC; | ||
283 | |||
284 | return 0; | ||
285 | } | ||
286 | |||
287 | static int atl1c_nway_reset(struct net_device *netdev) | ||
288 | { | ||
289 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
290 | if (netif_running(netdev)) | ||
291 | atl1c_reinit_locked(adapter); | ||
292 | return 0; | ||
293 | } | ||
294 | |||
295 | static struct ethtool_ops atl1c_ethtool_ops = { | ||
296 | .get_settings = atl1c_get_settings, | ||
297 | .set_settings = atl1c_set_settings, | ||
298 | .get_drvinfo = atl1c_get_drvinfo, | ||
299 | .get_regs_len = atl1c_get_regs_len, | ||
300 | .get_regs = atl1c_get_regs, | ||
301 | .get_wol = atl1c_get_wol, | ||
302 | .set_wol = atl1c_set_wol, | ||
303 | .get_msglevel = atl1c_get_msglevel, | ||
304 | .set_msglevel = atl1c_set_msglevel, | ||
305 | .nway_reset = atl1c_nway_reset, | ||
306 | .get_link = ethtool_op_get_link, | ||
307 | .get_eeprom_len = atl1c_get_eeprom_len, | ||
308 | .get_eeprom = atl1c_get_eeprom, | ||
309 | .get_tx_csum = atl1c_get_tx_csum, | ||
310 | .get_sg = ethtool_op_get_sg, | ||
311 | .set_sg = ethtool_op_set_sg, | ||
312 | }; | ||
313 | |||
314 | void atl1c_set_ethtool_ops(struct net_device *netdev) | ||
315 | { | ||
316 | SET_ETHTOOL_OPS(netdev, &atl1c_ethtool_ops); | ||
317 | } | ||
diff --git a/drivers/net/atl1c/atl1c_hw.c b/drivers/net/atl1c/atl1c_hw.c new file mode 100644 index 000000000000..3e69b940b8f7 --- /dev/null +++ b/drivers/net/atl1c/atl1c_hw.c | |||
@@ -0,0 +1,527 @@ | |||
1 | /* | ||
2 | * Copyright(c) 2007 Atheros Corporation. All rights reserved. | ||
3 | * | ||
4 | * Derived from Intel e1000 driver | ||
5 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License as published by the Free | ||
9 | * Software Foundation; either version 2 of the License, or (at your option) | ||
10 | * any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
15 | * more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License along with | ||
18 | * this program; if not, write to the Free Software Foundation, Inc., 59 | ||
19 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
20 | */ | ||
21 | #include <linux/pci.h> | ||
22 | #include <linux/delay.h> | ||
23 | #include <linux/mii.h> | ||
24 | #include <linux/crc32.h> | ||
25 | |||
26 | #include "atl1c.h" | ||
27 | |||
28 | /* | ||
29 | * check_eeprom_exist | ||
30 | * return 1 if eeprom exist | ||
31 | */ | ||
32 | int atl1c_check_eeprom_exist(struct atl1c_hw *hw) | ||
33 | { | ||
34 | u32 data; | ||
35 | |||
36 | AT_READ_REG(hw, REG_TWSI_DEBUG, &data); | ||
37 | if (data & TWSI_DEBUG_DEV_EXIST) | ||
38 | return 1; | ||
39 | |||
40 | return 0; | ||
41 | } | ||
42 | |||
43 | void atl1c_hw_set_mac_addr(struct atl1c_hw *hw) | ||
44 | { | ||
45 | u32 value; | ||
46 | /* | ||
47 | * 00-0B-6A-F6-00-DC | ||
48 | * 0: 6AF600DC 1: 000B | ||
49 | * low dword | ||
50 | */ | ||
51 | value = (((u32)hw->mac_addr[2]) << 24) | | ||
52 | (((u32)hw->mac_addr[3]) << 16) | | ||
53 | (((u32)hw->mac_addr[4]) << 8) | | ||
54 | (((u32)hw->mac_addr[5])) ; | ||
55 | AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); | ||
56 | /* hight dword */ | ||
57 | value = (((u32)hw->mac_addr[0]) << 8) | | ||
58 | (((u32)hw->mac_addr[1])) ; | ||
59 | AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); | ||
60 | } | ||
61 | |||
62 | /* | ||
63 | * atl1c_get_permanent_address | ||
64 | * return 0 if get valid mac address, | ||
65 | */ | ||
66 | static int atl1c_get_permanent_address(struct atl1c_hw *hw) | ||
67 | { | ||
68 | u32 addr[2]; | ||
69 | u32 i; | ||
70 | u32 otp_ctrl_data; | ||
71 | u32 twsi_ctrl_data; | ||
72 | u8 eth_addr[ETH_ALEN]; | ||
73 | |||
74 | /* init */ | ||
75 | addr[0] = addr[1] = 0; | ||
76 | AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data); | ||
77 | if (atl1c_check_eeprom_exist(hw)) { | ||
78 | /* Enable OTP CLK */ | ||
79 | if (!(otp_ctrl_data & OTP_CTRL_CLK_EN)) { | ||
80 | otp_ctrl_data |= OTP_CTRL_CLK_EN; | ||
81 | AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data); | ||
82 | AT_WRITE_FLUSH(hw); | ||
83 | msleep(1); | ||
84 | } | ||
85 | |||
86 | AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data); | ||
87 | twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART; | ||
88 | AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data); | ||
89 | for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) { | ||
90 | msleep(10); | ||
91 | AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data); | ||
92 | if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0) | ||
93 | break; | ||
94 | } | ||
95 | if (i >= AT_TWSI_EEPROM_TIMEOUT) | ||
96 | return -1; | ||
97 | } | ||
98 | /* Disable OTP_CLK */ | ||
99 | if (otp_ctrl_data & OTP_CTRL_CLK_EN) { | ||
100 | otp_ctrl_data &= ~OTP_CTRL_CLK_EN; | ||
101 | AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data); | ||
102 | AT_WRITE_FLUSH(hw); | ||
103 | msleep(1); | ||
104 | } | ||
105 | |||
106 | /* maybe MAC-address is from BIOS */ | ||
107 | AT_READ_REG(hw, REG_MAC_STA_ADDR, &addr[0]); | ||
108 | AT_READ_REG(hw, REG_MAC_STA_ADDR + 4, &addr[1]); | ||
109 | *(u32 *) ð_addr[2] = swab32(addr[0]); | ||
110 | *(u16 *) ð_addr[0] = swab16(*(u16 *)&addr[1]); | ||
111 | |||
112 | if (is_valid_ether_addr(eth_addr)) { | ||
113 | memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); | ||
114 | return 0; | ||
115 | } | ||
116 | |||
117 | return -1; | ||
118 | } | ||
119 | |||
120 | bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value) | ||
121 | { | ||
122 | int i; | ||
123 | int ret = false; | ||
124 | u32 otp_ctrl_data; | ||
125 | u32 control; | ||
126 | u32 data; | ||
127 | |||
128 | if (offset & 3) | ||
129 | return ret; /* address do not align */ | ||
130 | |||
131 | AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data); | ||
132 | if (!(otp_ctrl_data & OTP_CTRL_CLK_EN)) | ||
133 | AT_WRITE_REG(hw, REG_OTP_CTRL, | ||
134 | (otp_ctrl_data | OTP_CTRL_CLK_EN)); | ||
135 | |||
136 | AT_WRITE_REG(hw, REG_EEPROM_DATA_LO, 0); | ||
137 | control = (offset & EEPROM_CTRL_ADDR_MASK) << EEPROM_CTRL_ADDR_SHIFT; | ||
138 | AT_WRITE_REG(hw, REG_EEPROM_CTRL, control); | ||
139 | |||
140 | for (i = 0; i < 10; i++) { | ||
141 | udelay(100); | ||
142 | AT_READ_REG(hw, REG_EEPROM_CTRL, &control); | ||
143 | if (control & EEPROM_CTRL_RW) | ||
144 | break; | ||
145 | } | ||
146 | if (control & EEPROM_CTRL_RW) { | ||
147 | AT_READ_REG(hw, REG_EEPROM_CTRL, &data); | ||
148 | AT_READ_REG(hw, REG_EEPROM_DATA_LO, p_value); | ||
149 | data = data & 0xFFFF; | ||
150 | *p_value = swab32((data << 16) | (*p_value >> 16)); | ||
151 | ret = true; | ||
152 | } | ||
153 | if (!(otp_ctrl_data & OTP_CTRL_CLK_EN)) | ||
154 | AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data); | ||
155 | |||
156 | return ret; | ||
157 | } | ||
158 | /* | ||
159 | * Reads the adapter's MAC address from the EEPROM | ||
160 | * | ||
161 | * hw - Struct containing variables accessed by shared code | ||
162 | */ | ||
163 | int atl1c_read_mac_addr(struct atl1c_hw *hw) | ||
164 | { | ||
165 | int err = 0; | ||
166 | |||
167 | err = atl1c_get_permanent_address(hw); | ||
168 | if (err) | ||
169 | random_ether_addr(hw->perm_mac_addr); | ||
170 | |||
171 | memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr)); | ||
172 | return 0; | ||
173 | } | ||
174 | |||
175 | /* | ||
176 | * atl1c_hash_mc_addr | ||
177 | * purpose | ||
178 | * set hash value for a multicast address | ||
179 | * hash calcu processing : | ||
180 | * 1. calcu 32bit CRC for multicast address | ||
181 | * 2. reverse crc with MSB to LSB | ||
182 | */ | ||
183 | u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr) | ||
184 | { | ||
185 | u32 crc32; | ||
186 | u32 value = 0; | ||
187 | int i; | ||
188 | |||
189 | crc32 = ether_crc_le(6, mc_addr); | ||
190 | for (i = 0; i < 32; i++) | ||
191 | value |= (((crc32 >> i) & 1) << (31 - i)); | ||
192 | |||
193 | return value; | ||
194 | } | ||
195 | |||
196 | /* | ||
197 | * Sets the bit in the multicast table corresponding to the hash value. | ||
198 | * hw - Struct containing variables accessed by shared code | ||
199 | * hash_value - Multicast address hash value | ||
200 | */ | ||
201 | void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value) | ||
202 | { | ||
203 | u32 hash_bit, hash_reg; | ||
204 | u32 mta; | ||
205 | |||
206 | /* | ||
207 | * The HASH Table is a register array of 2 32-bit registers. | ||
208 | * It is treated like an array of 64 bits. We want to set | ||
209 | * bit BitArray[hash_value]. So we figure out what register | ||
210 | * the bit is in, read it, OR in the new bit, then write | ||
211 | * back the new value. The register is determined by the | ||
212 | * upper bit of the hash value and the bit within that | ||
213 | * register are determined by the lower 5 bits of the value. | ||
214 | */ | ||
215 | hash_reg = (hash_value >> 31) & 0x1; | ||
216 | hash_bit = (hash_value >> 26) & 0x1F; | ||
217 | |||
218 | mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); | ||
219 | |||
220 | mta |= (1 << hash_bit); | ||
221 | |||
222 | AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); | ||
223 | } | ||
224 | |||
225 | /* | ||
226 | * Reads the value from a PHY register | ||
227 | * hw - Struct containing variables accessed by shared code | ||
228 | * reg_addr - address of the PHY register to read | ||
229 | */ | ||
230 | int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data) | ||
231 | { | ||
232 | u32 val; | ||
233 | int i; | ||
234 | |||
235 | val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | | ||
236 | MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | | ||
237 | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; | ||
238 | |||
239 | AT_WRITE_REG(hw, REG_MDIO_CTRL, val); | ||
240 | |||
241 | for (i = 0; i < MDIO_WAIT_TIMES; i++) { | ||
242 | udelay(2); | ||
243 | AT_READ_REG(hw, REG_MDIO_CTRL, &val); | ||
244 | if (!(val & (MDIO_START | MDIO_BUSY))) | ||
245 | break; | ||
246 | } | ||
247 | if (!(val & (MDIO_START | MDIO_BUSY))) { | ||
248 | *phy_data = (u16)val; | ||
249 | return 0; | ||
250 | } | ||
251 | |||
252 | return -1; | ||
253 | } | ||
254 | |||
255 | /* | ||
256 | * Writes a value to a PHY register | ||
257 | * hw - Struct containing variables accessed by shared code | ||
258 | * reg_addr - address of the PHY register to write | ||
259 | * data - data to write to the PHY | ||
260 | */ | ||
261 | int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data) | ||
262 | { | ||
263 | int i; | ||
264 | u32 val; | ||
265 | |||
266 | val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | | ||
267 | (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | | ||
268 | MDIO_SUP_PREAMBLE | MDIO_START | | ||
269 | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; | ||
270 | |||
271 | AT_WRITE_REG(hw, REG_MDIO_CTRL, val); | ||
272 | |||
273 | for (i = 0; i < MDIO_WAIT_TIMES; i++) { | ||
274 | udelay(2); | ||
275 | AT_READ_REG(hw, REG_MDIO_CTRL, &val); | ||
276 | if (!(val & (MDIO_START | MDIO_BUSY))) | ||
277 | break; | ||
278 | } | ||
279 | |||
280 | if (!(val & (MDIO_START | MDIO_BUSY))) | ||
281 | return 0; | ||
282 | |||
283 | return -1; | ||
284 | } | ||
285 | |||
286 | /* | ||
287 | * Configures PHY autoneg and flow control advertisement settings | ||
288 | * | ||
289 | * hw - Struct containing variables accessed by shared code | ||
290 | */ | ||
291 | static int atl1c_phy_setup_adv(struct atl1c_hw *hw) | ||
292 | { | ||
293 | u16 mii_adv_data = ADVERTISE_DEFAULT_CAP & ~ADVERTISE_SPEED_MASK; | ||
294 | u16 mii_giga_ctrl_data = GIGA_CR_1000T_DEFAULT_CAP & | ||
295 | ~GIGA_CR_1000T_SPEED_MASK; | ||
296 | |||
297 | if (hw->autoneg_advertised & ADVERTISED_10baseT_Half) | ||
298 | mii_adv_data |= ADVERTISE_10HALF; | ||
299 | if (hw->autoneg_advertised & ADVERTISED_10baseT_Full) | ||
300 | mii_adv_data |= ADVERTISE_10FULL; | ||
301 | if (hw->autoneg_advertised & ADVERTISED_100baseT_Half) | ||
302 | mii_adv_data |= ADVERTISE_100HALF; | ||
303 | if (hw->autoneg_advertised & ADVERTISED_100baseT_Full) | ||
304 | mii_adv_data |= ADVERTISE_100FULL; | ||
305 | |||
306 | if (hw->autoneg_advertised & ADVERTISED_Autoneg) | ||
307 | mii_adv_data |= ADVERTISE_10HALF | ADVERTISE_10FULL | | ||
308 | ADVERTISE_100HALF | ADVERTISE_100FULL; | ||
309 | |||
310 | if (hw->ctrl_flags & ATL1C_LINK_CAP_1000M) { | ||
311 | if (hw->autoneg_advertised & ADVERTISED_1000baseT_Half) | ||
312 | mii_giga_ctrl_data |= ADVERTISE_1000HALF; | ||
313 | if (hw->autoneg_advertised & ADVERTISED_1000baseT_Full) | ||
314 | mii_giga_ctrl_data |= ADVERTISE_1000FULL; | ||
315 | if (hw->autoneg_advertised & ADVERTISED_Autoneg) | ||
316 | mii_giga_ctrl_data |= ADVERTISE_1000HALF | | ||
317 | ADVERTISE_1000FULL; | ||
318 | } | ||
319 | |||
320 | if (atl1c_write_phy_reg(hw, MII_ADVERTISE, mii_adv_data) != 0 || | ||
321 | atl1c_write_phy_reg(hw, MII_GIGA_CR, mii_giga_ctrl_data) != 0) | ||
322 | return -1; | ||
323 | return 0; | ||
324 | } | ||
325 | |||
326 | void atl1c_phy_disable(struct atl1c_hw *hw) | ||
327 | { | ||
328 | AT_WRITE_REGW(hw, REG_GPHY_CTRL, | ||
329 | GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET); | ||
330 | } | ||
331 | |||
332 | static void atl1c_phy_magic_data(struct atl1c_hw *hw) | ||
333 | { | ||
334 | u16 data; | ||
335 | |||
336 | data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | | ||
337 | ((1 & ANA_INTERVAL_SEL_TIMER_MASK) << | ||
338 | ANA_INTERVAL_SEL_TIMER_SHIFT); | ||
339 | |||
340 | atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_18); | ||
341 | atl1c_write_phy_reg(hw, MII_DBG_DATA, data); | ||
342 | |||
343 | data = (2 & ANA_SERDES_CDR_BW_MASK) | ANA_MS_PAD_DBG | | ||
344 | ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | | ||
345 | ANA_SERDES_EN_LCKDT; | ||
346 | |||
347 | atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_5); | ||
348 | atl1c_write_phy_reg(hw, MII_DBG_DATA, data); | ||
349 | |||
350 | data = (44 & ANA_LONG_CABLE_TH_100_MASK) | | ||
351 | ((33 & ANA_SHORT_CABLE_TH_100_MASK) << | ||
352 | ANA_SHORT_CABLE_TH_100_SHIFT) | ANA_BP_BAD_LINK_ACCUM | | ||
353 | ANA_BP_SMALL_BW; | ||
354 | |||
355 | atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_54); | ||
356 | atl1c_write_phy_reg(hw, MII_DBG_DATA, data); | ||
357 | |||
358 | data = (11 & ANA_IECHO_ADJ_MASK) | ((11 & ANA_IECHO_ADJ_MASK) << | ||
359 | ANA_IECHO_ADJ_2_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) << | ||
360 | ANA_IECHO_ADJ_1_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) << | ||
361 | ANA_IECHO_ADJ_0_SHIFT); | ||
362 | |||
363 | atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_4); | ||
364 | atl1c_write_phy_reg(hw, MII_DBG_DATA, data); | ||
365 | |||
366 | data = ANA_RESTART_CAL | ((7 & ANA_MANUL_SWICH_ON_MASK) << | ||
367 | ANA_MANUL_SWICH_ON_SHIFT) | ANA_MAN_ENABLE | | ||
368 | ANA_SEL_HSP | ANA_EN_HB | ANA_OEN_125M; | ||
369 | |||
370 | atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_0); | ||
371 | atl1c_write_phy_reg(hw, MII_DBG_DATA, data); | ||
372 | |||
373 | if (hw->ctrl_flags & ATL1C_HIB_DISABLE) { | ||
374 | atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_41); | ||
375 | if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0) | ||
376 | return; | ||
377 | data &= ~ANA_TOP_PS_EN; | ||
378 | atl1c_write_phy_reg(hw, MII_DBG_DATA, data); | ||
379 | |||
380 | atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_11); | ||
381 | if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0) | ||
382 | return; | ||
383 | data &= ~ANA_PS_HIB_EN; | ||
384 | atl1c_write_phy_reg(hw, MII_DBG_DATA, data); | ||
385 | } | ||
386 | } | ||
387 | |||
388 | int atl1c_phy_reset(struct atl1c_hw *hw) | ||
389 | { | ||
390 | struct atl1c_adapter *adapter = hw->adapter; | ||
391 | struct pci_dev *pdev = adapter->pdev; | ||
392 | u32 phy_ctrl_data = GPHY_CTRL_DEFAULT; | ||
393 | u32 mii_ier_data = IER_LINK_UP | IER_LINK_DOWN; | ||
394 | int err; | ||
395 | |||
396 | if (hw->ctrl_flags & ATL1C_HIB_DISABLE) | ||
397 | phy_ctrl_data &= ~GPHY_CTRL_HIB_EN; | ||
398 | |||
399 | AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data); | ||
400 | AT_WRITE_FLUSH(hw); | ||
401 | msleep(40); | ||
402 | phy_ctrl_data |= GPHY_CTRL_EXT_RESET; | ||
403 | AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data); | ||
404 | AT_WRITE_FLUSH(hw); | ||
405 | msleep(10); | ||
406 | |||
407 | /*Enable PHY LinkChange Interrupt */ | ||
408 | err = atl1c_write_phy_reg(hw, MII_IER, mii_ier_data); | ||
409 | if (err) { | ||
410 | if (netif_msg_hw(adapter)) | ||
411 | dev_err(&pdev->dev, | ||
412 | "Error enable PHY linkChange Interrupt\n"); | ||
413 | return err; | ||
414 | } | ||
415 | if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION)) | ||
416 | atl1c_phy_magic_data(hw); | ||
417 | return 0; | ||
418 | } | ||
419 | |||
420 | int atl1c_phy_init(struct atl1c_hw *hw) | ||
421 | { | ||
422 | struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter; | ||
423 | struct pci_dev *pdev = adapter->pdev; | ||
424 | int ret_val; | ||
425 | u16 mii_bmcr_data = BMCR_RESET; | ||
426 | u16 phy_id1, phy_id2; | ||
427 | |||
428 | if ((atl1c_read_phy_reg(hw, MII_PHYSID1, &phy_id1) != 0) || | ||
429 | (atl1c_read_phy_reg(hw, MII_PHYSID2, &phy_id2) != 0)) { | ||
430 | if (netif_msg_link(adapter)) | ||
431 | dev_err(&pdev->dev, "Error get phy ID\n"); | ||
432 | return -1; | ||
433 | } | ||
434 | switch (hw->media_type) { | ||
435 | case MEDIA_TYPE_AUTO_SENSOR: | ||
436 | ret_val = atl1c_phy_setup_adv(hw); | ||
437 | if (ret_val) { | ||
438 | if (netif_msg_link(adapter)) | ||
439 | dev_err(&pdev->dev, | ||
440 | "Error Setting up Auto-Negotiation\n"); | ||
441 | return ret_val; | ||
442 | } | ||
443 | mii_bmcr_data |= BMCR_AUTO_NEG_EN | BMCR_RESTART_AUTO_NEG; | ||
444 | break; | ||
445 | case MEDIA_TYPE_100M_FULL: | ||
446 | mii_bmcr_data |= BMCR_SPEED_100 | BMCR_FULL_DUPLEX; | ||
447 | break; | ||
448 | case MEDIA_TYPE_100M_HALF: | ||
449 | mii_bmcr_data |= BMCR_SPEED_100; | ||
450 | break; | ||
451 | case MEDIA_TYPE_10M_FULL: | ||
452 | mii_bmcr_data |= BMCR_SPEED_10 | BMCR_FULL_DUPLEX; | ||
453 | break; | ||
454 | case MEDIA_TYPE_10M_HALF: | ||
455 | mii_bmcr_data |= BMCR_SPEED_10; | ||
456 | break; | ||
457 | default: | ||
458 | if (netif_msg_link(adapter)) | ||
459 | dev_err(&pdev->dev, "Wrong Media type %d\n", | ||
460 | hw->media_type); | ||
461 | return -1; | ||
462 | break; | ||
463 | } | ||
464 | |||
465 | ret_val = atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data); | ||
466 | if (ret_val) | ||
467 | return ret_val; | ||
468 | hw->phy_configured = true; | ||
469 | |||
470 | return 0; | ||
471 | } | ||
472 | |||
473 | /* | ||
474 | * Detects the current speed and duplex settings of the hardware. | ||
475 | * | ||
476 | * hw - Struct containing variables accessed by shared code | ||
477 | * speed - Speed of the connection | ||
478 | * duplex - Duplex setting of the connection | ||
479 | */ | ||
480 | int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex) | ||
481 | { | ||
482 | int err; | ||
483 | u16 phy_data; | ||
484 | |||
485 | /* Read PHY Specific Status Register (17) */ | ||
486 | err = atl1c_read_phy_reg(hw, MII_GIGA_PSSR, &phy_data); | ||
487 | if (err) | ||
488 | return err; | ||
489 | |||
490 | if (!(phy_data & GIGA_PSSR_SPD_DPLX_RESOLVED)) | ||
491 | return -1; | ||
492 | |||
493 | switch (phy_data & GIGA_PSSR_SPEED) { | ||
494 | case GIGA_PSSR_1000MBS: | ||
495 | *speed = SPEED_1000; | ||
496 | break; | ||
497 | case GIGA_PSSR_100MBS: | ||
498 | *speed = SPEED_100; | ||
499 | break; | ||
500 | case GIGA_PSSR_10MBS: | ||
501 | *speed = SPEED_10; | ||
502 | break; | ||
503 | default: | ||
504 | return -1; | ||
505 | break; | ||
506 | } | ||
507 | |||
508 | if (phy_data & GIGA_PSSR_DPLX) | ||
509 | *duplex = FULL_DUPLEX; | ||
510 | else | ||
511 | *duplex = HALF_DUPLEX; | ||
512 | |||
513 | return 0; | ||
514 | } | ||
515 | |||
516 | int atl1c_restart_autoneg(struct atl1c_hw *hw) | ||
517 | { | ||
518 | int err = 0; | ||
519 | u16 mii_bmcr_data = BMCR_RESET; | ||
520 | |||
521 | err = atl1c_phy_setup_adv(hw); | ||
522 | if (err) | ||
523 | return err; | ||
524 | mii_bmcr_data |= BMCR_AUTO_NEG_EN | BMCR_RESTART_AUTO_NEG; | ||
525 | |||
526 | return atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data); | ||
527 | } | ||
diff --git a/drivers/net/atl1c/atl1c_hw.h b/drivers/net/atl1c/atl1c_hw.h new file mode 100644 index 000000000000..c2c738df5c63 --- /dev/null +++ b/drivers/net/atl1c/atl1c_hw.h | |||
@@ -0,0 +1,859 @@ | |||
1 | /* | ||
2 | * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved. | ||
3 | * | ||
4 | * Derived from Intel e1000 driver | ||
5 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License as published by the Free | ||
9 | * Software Foundation; either version 2 of the License, or (at your option) | ||
10 | * any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
15 | * more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License along with | ||
18 | * this program; if not, write to the Free Software Foundation, Inc., 59 | ||
19 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
20 | */ | ||
21 | |||
22 | #ifndef _ATL1C_HW_H_ | ||
23 | #define _ATL1C_HW_H_ | ||
24 | |||
25 | #include <linux/types.h> | ||
26 | #include <linux/mii.h> | ||
27 | |||
28 | struct atl1c_adapter; | ||
29 | struct atl1c_hw; | ||
30 | |||
31 | /* function prototype */ | ||
32 | void atl1c_phy_disable(struct atl1c_hw *hw); | ||
33 | void atl1c_hw_set_mac_addr(struct atl1c_hw *hw); | ||
34 | int atl1c_phy_reset(struct atl1c_hw *hw); | ||
35 | int atl1c_read_mac_addr(struct atl1c_hw *hw); | ||
36 | int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex); | ||
37 | u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr); | ||
38 | void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value); | ||
39 | int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data); | ||
40 | int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data); | ||
41 | bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value); | ||
42 | int atl1c_phy_init(struct atl1c_hw *hw); | ||
43 | int atl1c_check_eeprom_exist(struct atl1c_hw *hw); | ||
44 | int atl1c_restart_autoneg(struct atl1c_hw *hw); | ||
45 | |||
46 | /* register definition */ | ||
47 | #define REG_DEVICE_CAP 0x5C | ||
48 | #define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7 | ||
49 | #define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0 | ||
50 | |||
51 | #define REG_DEVICE_CTRL 0x60 | ||
52 | #define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7 | ||
53 | #define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5 | ||
54 | #define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7 | ||
55 | #define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12 | ||
56 | |||
57 | #define REG_LINK_CTRL 0x68 | ||
58 | #define LINK_CTRL_L0S_EN 0x01 | ||
59 | #define LINK_CTRL_L1_EN 0x02 | ||
60 | |||
61 | #define REG_VPD_CAP 0x6C | ||
62 | #define VPD_CAP_ID_MASK 0xff | ||
63 | #define VPD_CAP_ID_SHIFT 0 | ||
64 | #define VPD_CAP_NEXT_PTR_MASK 0xFF | ||
65 | #define VPD_CAP_NEXT_PTR_SHIFT 8 | ||
66 | #define VPD_CAP_VPD_ADDR_MASK 0x7FFF | ||
67 | #define VPD_CAP_VPD_ADDR_SHIFT 16 | ||
68 | #define VPD_CAP_VPD_FLAG 0x80000000 | ||
69 | |||
70 | #define REG_VPD_DATA 0x70 | ||
71 | |||
72 | #define REG_PCIE_UC_SEVERITY 0x10C | ||
73 | #define PCIE_UC_SERVRITY_TRN 0x00000001 | ||
74 | #define PCIE_UC_SERVRITY_DLP 0x00000010 | ||
75 | #define PCIE_UC_SERVRITY_PSN_TLP 0x00001000 | ||
76 | #define PCIE_UC_SERVRITY_FCP 0x00002000 | ||
77 | #define PCIE_UC_SERVRITY_CPL_TO 0x00004000 | ||
78 | #define PCIE_UC_SERVRITY_CA 0x00008000 | ||
79 | #define PCIE_UC_SERVRITY_UC 0x00010000 | ||
80 | #define PCIE_UC_SERVRITY_ROV 0x00020000 | ||
81 | #define PCIE_UC_SERVRITY_MLFP 0x00040000 | ||
82 | #define PCIE_UC_SERVRITY_ECRC 0x00080000 | ||
83 | #define PCIE_UC_SERVRITY_UR 0x00100000 | ||
84 | |||
85 | #define REG_DEV_SERIALNUM_CTRL 0x200 | ||
86 | #define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */ | ||
87 | #define REG_DEV_MAC_SEL_SHIFT 0 | ||
88 | #define REG_DEV_SERIAL_NUM_EN_MASK 0x1 | ||
89 | #define REG_DEV_SERIAL_NUM_EN_SHIFT 1 | ||
90 | |||
91 | #define REG_TWSI_CTRL 0x218 | ||
92 | #define TWSI_CTRL_LD_OFFSET_MASK 0xFF | ||
93 | #define TWSI_CTRL_LD_OFFSET_SHIFT 0 | ||
94 | #define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7 | ||
95 | #define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8 | ||
96 | #define TWSI_CTRL_SW_LDSTART 0x800 | ||
97 | #define TWSI_CTRL_HW_LDSTART 0x1000 | ||
98 | #define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F | ||
99 | #define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15 | ||
100 | #define TWSI_CTRL_LD_EXIST 0x400000 | ||
101 | #define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3 | ||
102 | #define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23 | ||
103 | #define TWSI_CTRL_FREQ_SEL_100K 0 | ||
104 | #define TWSI_CTRL_FREQ_SEL_200K 1 | ||
105 | #define TWSI_CTRL_FREQ_SEL_300K 2 | ||
106 | #define TWSI_CTRL_FREQ_SEL_400K 3 | ||
107 | #define TWSI_CTRL_SMB_SLV_ADDR | ||
108 | #define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3 | ||
109 | #define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24 | ||
110 | |||
111 | |||
112 | #define REG_PCIE_DEV_MISC_CTRL 0x21C | ||
113 | #define PCIE_DEV_MISC_EXT_PIPE 0x2 | ||
114 | #define PCIE_DEV_MISC_RETRY_BUFDIS 0x1 | ||
115 | #define PCIE_DEV_MISC_SPIROM_EXIST 0x4 | ||
116 | #define PCIE_DEV_MISC_SERDES_ENDIAN 0x8 | ||
117 | #define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10 | ||
118 | |||
119 | #define REG_PCIE_PHYMISC 0x1000 | ||
120 | #define PCIE_PHYMISC_FORCE_RCV_DET 0x4 | ||
121 | |||
122 | #define REG_TWSI_DEBUG 0x1108 | ||
123 | #define TWSI_DEBUG_DEV_EXIST 0x20000000 | ||
124 | |||
125 | #define REG_EEPROM_CTRL 0x12C0 | ||
126 | #define EEPROM_CTRL_DATA_HI_MASK 0xFFFF | ||
127 | #define EEPROM_CTRL_DATA_HI_SHIFT 0 | ||
128 | #define EEPROM_CTRL_ADDR_MASK 0x3FF | ||
129 | #define EEPROM_CTRL_ADDR_SHIFT 16 | ||
130 | #define EEPROM_CTRL_ACK 0x40000000 | ||
131 | #define EEPROM_CTRL_RW 0x80000000 | ||
132 | |||
133 | #define REG_EEPROM_DATA_LO 0x12C4 | ||
134 | |||
135 | #define REG_OTP_CTRL 0x12F0 | ||
136 | #define OTP_CTRL_CLK_EN 0x0002 | ||
137 | |||
138 | #define REG_PM_CTRL 0x12F8 | ||
139 | #define PM_CTRL_SDES_EN 0x00000001 | ||
140 | #define PM_CTRL_RBER_EN 0x00000002 | ||
141 | #define PM_CTRL_CLK_REQ_EN 0x00000004 | ||
142 | #define PM_CTRL_ASPM_L1_EN 0x00000008 | ||
143 | #define PM_CTRL_SERDES_L1_EN 0x00000010 | ||
144 | #define PM_CTRL_SERDES_PLL_L1_EN 0x00000020 | ||
145 | #define PM_CTRL_SERDES_PD_EX_L1 0x00000040 | ||
146 | #define PM_CTRL_SERDES_BUDS_RX_L1_EN 0x00000080 | ||
147 | #define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xF | ||
148 | #define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8 | ||
149 | #define PM_CTRL_ASPM_L0S_EN 0x00001000 | ||
150 | #define PM_CTRL_CLK_SWH_L1 0x00002000 | ||
151 | #define PM_CTRL_CLK_PWM_VER1_1 0x00004000 | ||
152 | #define PM_CTRL_PCIE_RECV 0x00008000 | ||
153 | #define PM_CTRL_L1_ENTRY_TIMER_MASK 0xF | ||
154 | #define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16 | ||
155 | #define PM_CTRL_PM_REQ_TIMER_MASK 0xF | ||
156 | #define PM_CTRL_PM_REQ_TIMER_SHIFT 20 | ||
157 | #define PM_CTRL_LCKDET_TIMER_MASK 0x3F | ||
158 | #define PM_CTRL_LCKDET_TIMER_SHIFT 24 | ||
159 | #define PM_CTRL_MAC_ASPM_CHK 0x40000000 | ||
160 | #define PM_CTRL_HOTRST 0x80000000 | ||
161 | |||
162 | /* Selene Master Control Register */ | ||
163 | #define REG_MASTER_CTRL 0x1400 | ||
164 | #define MASTER_CTRL_SOFT_RST 0x1 | ||
165 | #define MASTER_CTRL_TEST_MODE_MASK 0x3 | ||
166 | #define MASTER_CTRL_TEST_MODE_SHIFT 2 | ||
167 | #define MASTER_CTRL_BERT_START 0x10 | ||
168 | #define MASTER_CTRL_MTIMER_EN 0x100 | ||
169 | #define MASTER_CTRL_MANUAL_INT 0x200 | ||
170 | #define MASTER_CTRL_TX_ITIMER_EN 0x400 | ||
171 | #define MASTER_CTRL_RX_ITIMER_EN 0x800 | ||
172 | #define MASTER_CTRL_CLK_SEL_DIS 0x1000 | ||
173 | #define MASTER_CTRL_CLK_SWH_MODE 0x2000 | ||
174 | #define MASTER_CTRL_INT_RDCLR 0x4000 | ||
175 | #define MASTER_CTRL_REV_NUM_SHIFT 16 | ||
176 | #define MASTER_CTRL_REV_NUM_MASK 0xff | ||
177 | #define MASTER_CTRL_DEV_ID_SHIFT 24 | ||
178 | #define MASTER_CTRL_DEV_ID_MASK 0x7f | ||
179 | #define MASTER_CTRL_OTP_SEL 0x80000000 | ||
180 | |||
181 | /* Timer Initial Value Register */ | ||
182 | #define REG_MANUAL_TIMER_INIT 0x1404 | ||
183 | |||
184 | /* IRQ ModeratorTimer Initial Value Register */ | ||
185 | #define REG_IRQ_MODRT_TIMER_INIT 0x1408 | ||
186 | #define IRQ_MODRT_TIMER_MASK 0xffff | ||
187 | #define IRQ_MODRT_TX_TIMER_SHIFT 0 | ||
188 | #define IRQ_MODRT_RX_TIMER_SHIFT 16 | ||
189 | |||
190 | #define REG_GPHY_CTRL 0x140C | ||
191 | #define GPHY_CTRL_EXT_RESET 0x1 | ||
192 | #define GPHY_CTRL_RTL_MODE 0x2 | ||
193 | #define GPHY_CTRL_LED_MODE 0x4 | ||
194 | #define GPHY_CTRL_ANEG_NOW 0x8 | ||
195 | #define GPHY_CTRL_REV_ANEG 0x10 | ||
196 | #define GPHY_CTRL_GATE_25M_EN 0x20 | ||
197 | #define GPHY_CTRL_LPW_EXIT 0x40 | ||
198 | #define GPHY_CTRL_PHY_IDDQ 0x80 | ||
199 | #define GPHY_CTRL_PHY_IDDQ_DIS 0x100 | ||
200 | #define GPHY_CTRL_GIGA_DIS 0x200 | ||
201 | #define GPHY_CTRL_HIB_EN 0x400 | ||
202 | #define GPHY_CTRL_HIB_PULSE 0x800 | ||
203 | #define GPHY_CTRL_SEL_ANA_RST 0x1000 | ||
204 | #define GPHY_CTRL_PHY_PLL_ON 0x2000 | ||
205 | #define GPHY_CTRL_PWDOWN_HW 0x4000 | ||
206 | #define GPHY_CTRL_PHY_PLL_BYPASS 0x8000 | ||
207 | |||
208 | #define GPHY_CTRL_DEFAULT ( \ | ||
209 | GPHY_CTRL_SEL_ANA_RST |\ | ||
210 | GPHY_CTRL_HIB_PULSE |\ | ||
211 | GPHY_CTRL_HIB_EN) | ||
212 | |||
213 | #define GPHY_CTRL_PW_WOL_DIS ( \ | ||
214 | GPHY_CTRL_SEL_ANA_RST |\ | ||
215 | GPHY_CTRL_HIB_PULSE |\ | ||
216 | GPHY_CTRL_HIB_EN |\ | ||
217 | GPHY_CTRL_PWDOWN_HW |\ | ||
218 | GPHY_CTRL_PHY_IDDQ) | ||
219 | |||
220 | /* Block IDLE Status Register */ | ||
221 | #define REG_IDLE_STATUS 0x1410 | ||
222 | #define IDLE_STATUS_MASK 0x00FF | ||
223 | #define IDLE_STATUS_RXMAC_NO_IDLE 0x1 | ||
224 | #define IDLE_STATUS_TXMAC_NO_IDLE 0x2 | ||
225 | #define IDLE_STATUS_RXQ_NO_IDLE 0x4 | ||
226 | #define IDLE_STATUS_TXQ_NO_IDLE 0x8 | ||
227 | #define IDLE_STATUS_DMAR_NO_IDLE 0x10 | ||
228 | #define IDLE_STATUS_DMAW_NO_IDLE 0x20 | ||
229 | #define IDLE_STATUS_SMB_NO_IDLE 0x40 | ||
230 | #define IDLE_STATUS_CMB_NO_IDLE 0x80 | ||
231 | |||
232 | /* MDIO Control Register */ | ||
233 | #define REG_MDIO_CTRL 0x1414 | ||
234 | #define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit | ||
235 | * control data to write to PHY | ||
236 | * MII management register */ | ||
237 | #define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit | ||
238 | * status data that was read | ||
239 | * from the PHY MII management register */ | ||
240 | #define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */ | ||
241 | #define MDIO_REG_ADDR_SHIFT 16 | ||
242 | #define MDIO_RW 0x200000 /* 1: read, 0: write */ | ||
243 | #define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */ | ||
244 | #define MDIO_START 0x800000 /* Write 1 to initiate the MDIO | ||
245 | * master. And this bit is self | ||
246 | * cleared after one cycle */ | ||
247 | #define MDIO_CLK_SEL_SHIFT 24 | ||
248 | #define MDIO_CLK_25_4 0 | ||
249 | #define MDIO_CLK_25_6 2 | ||
250 | #define MDIO_CLK_25_8 3 | ||
251 | #define MDIO_CLK_25_10 4 | ||
252 | #define MDIO_CLK_25_14 5 | ||
253 | #define MDIO_CLK_25_20 6 | ||
254 | #define MDIO_CLK_25_28 7 | ||
255 | #define MDIO_BUSY 0x8000000 | ||
256 | #define MDIO_AP_EN 0x10000000 | ||
257 | #define MDIO_WAIT_TIMES 10 | ||
258 | |||
259 | /* MII PHY Status Register */ | ||
260 | #define REG_PHY_STATUS 0x1418 | ||
261 | #define PHY_GENERAL_STATUS_MASK 0xFFFF | ||
262 | #define PHY_STATUS_RECV_ENABLE 0x0001 | ||
263 | #define PHY_OE_PWSP_STATUS_MASK 0x07FF | ||
264 | #define PHY_OE_PWSP_STATUS_SHIFT 16 | ||
265 | #define PHY_STATUS_LPW_STATE 0x80000000 | ||
266 | /* BIST Control and Status Register0 (for the Packet Memory) */ | ||
267 | #define REG_BIST0_CTRL 0x141c | ||
268 | #define BIST0_NOW 0x1 | ||
269 | #define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is | ||
270 | * un-repairable because | ||
271 | * it has address decoder | ||
272 | * failure or more than 1 cell | ||
273 | * stuck-to-x failure */ | ||
274 | #define BIST0_FUSE_FLAG 0x4 | ||
275 | |||
276 | /* BIST Control and Status Register1(for the retry buffer of PCI Express) */ | ||
277 | #define REG_BIST1_CTRL 0x1420 | ||
278 | #define BIST1_NOW 0x1 | ||
279 | #define BIST1_SRAM_FAIL 0x2 | ||
280 | #define BIST1_FUSE_FLAG 0x4 | ||
281 | |||
282 | /* SerDes Lock Detect Control and Status Register */ | ||
283 | #define REG_SERDES_LOCK 0x1424 | ||
284 | #define SERDES_LOCK_DETECT 0x1 /* SerDes lock detected. This signal | ||
285 | * comes from Analog SerDes */ | ||
286 | #define SERDES_LOCK_DETECT_EN 0x2 /* 1: Enable SerDes Lock detect function */ | ||
287 | |||
288 | /* MAC Control Register */ | ||
289 | #define REG_MAC_CTRL 0x1480 | ||
290 | #define MAC_CTRL_TX_EN 0x1 | ||
291 | #define MAC_CTRL_RX_EN 0x2 | ||
292 | #define MAC_CTRL_TX_FLOW 0x4 | ||
293 | #define MAC_CTRL_RX_FLOW 0x8 | ||
294 | #define MAC_CTRL_LOOPBACK 0x10 | ||
295 | #define MAC_CTRL_DUPLX 0x20 | ||
296 | #define MAC_CTRL_ADD_CRC 0x40 | ||
297 | #define MAC_CTRL_PAD 0x80 | ||
298 | #define MAC_CTRL_LENCHK 0x100 | ||
299 | #define MAC_CTRL_HUGE_EN 0x200 | ||
300 | #define MAC_CTRL_PRMLEN_SHIFT 10 | ||
301 | #define MAC_CTRL_PRMLEN_MASK 0xf | ||
302 | #define MAC_CTRL_RMV_VLAN 0x4000 | ||
303 | #define MAC_CTRL_PROMIS_EN 0x8000 | ||
304 | #define MAC_CTRL_TX_PAUSE 0x10000 | ||
305 | #define MAC_CTRL_SCNT 0x20000 | ||
306 | #define MAC_CTRL_SRST_TX 0x40000 | ||
307 | #define MAC_CTRL_TX_SIMURST 0x80000 | ||
308 | #define MAC_CTRL_SPEED_SHIFT 20 | ||
309 | #define MAC_CTRL_SPEED_MASK 0x3 | ||
310 | #define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 | ||
311 | #define MAC_CTRL_TX_HUGE 0x800000 | ||
312 | #define MAC_CTRL_RX_CHKSUM_EN 0x1000000 | ||
313 | #define MAC_CTRL_MC_ALL_EN 0x2000000 | ||
314 | #define MAC_CTRL_BC_EN 0x4000000 | ||
315 | #define MAC_CTRL_DBG 0x8000000 | ||
316 | #define MAC_CTRL_SINGLE_PAUSE_EN 0x10000000 | ||
317 | |||
318 | /* MAC IPG/IFG Control Register */ | ||
319 | #define REG_MAC_IPG_IFG 0x1484 | ||
320 | #define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back | ||
321 | * inter-packet gap. The | ||
322 | * default is 96-bit time */ | ||
323 | #define MAC_IPG_IFG_IPGT_MASK 0x7f | ||
324 | #define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to | ||
325 | * enforce in between RX frames */ | ||
326 | #define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */ | ||
327 | #define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */ | ||
328 | #define MAC_IPG_IFG_IPGR1_MASK 0x7f | ||
329 | #define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */ | ||
330 | #define MAC_IPG_IFG_IPGR2_MASK 0x7f | ||
331 | |||
332 | /* MAC STATION ADDRESS */ | ||
333 | #define REG_MAC_STA_ADDR 0x1488 | ||
334 | |||
335 | /* Hash table for multicast address */ | ||
336 | #define REG_RX_HASH_TABLE 0x1490 | ||
337 | |||
338 | /* MAC Half-Duplex Control Register */ | ||
339 | #define REG_MAC_HALF_DUPLX_CTRL 0x1498 | ||
340 | #define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */ | ||
341 | #define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff | ||
342 | #define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 | ||
343 | #define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf | ||
344 | #define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 | ||
345 | #define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 | ||
346 | #define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* No back-off on backpressure, | ||
347 | * immediately start the | ||
348 | * transmission after back pressure */ | ||
349 | #define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */ | ||
350 | #define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */ | ||
351 | #define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf | ||
352 | #define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */ | ||
353 | #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */ | ||
354 | |||
355 | /* Maximum Frame Length Control Register */ | ||
356 | #define REG_MTU 0x149c | ||
357 | |||
358 | /* Wake-On-Lan control register */ | ||
359 | #define REG_WOL_CTRL 0x14a0 | ||
360 | #define WOL_PATTERN_EN 0x00000001 | ||
361 | #define WOL_PATTERN_PME_EN 0x00000002 | ||
362 | #define WOL_MAGIC_EN 0x00000004 | ||
363 | #define WOL_MAGIC_PME_EN 0x00000008 | ||
364 | #define WOL_LINK_CHG_EN 0x00000010 | ||
365 | #define WOL_LINK_CHG_PME_EN 0x00000020 | ||
366 | #define WOL_PATTERN_ST 0x00000100 | ||
367 | #define WOL_MAGIC_ST 0x00000200 | ||
368 | #define WOL_LINKCHG_ST 0x00000400 | ||
369 | #define WOL_CLK_SWITCH_EN 0x00008000 | ||
370 | #define WOL_PT0_EN 0x00010000 | ||
371 | #define WOL_PT1_EN 0x00020000 | ||
372 | #define WOL_PT2_EN 0x00040000 | ||
373 | #define WOL_PT3_EN 0x00080000 | ||
374 | #define WOL_PT4_EN 0x00100000 | ||
375 | #define WOL_PT5_EN 0x00200000 | ||
376 | #define WOL_PT6_EN 0x00400000 | ||
377 | |||
378 | /* WOL Length ( 2 DWORD ) */ | ||
379 | #define REG_WOL_PATTERN_LEN 0x14a4 | ||
380 | #define WOL_PT_LEN_MASK 0x7f | ||
381 | #define WOL_PT0_LEN_SHIFT 0 | ||
382 | #define WOL_PT1_LEN_SHIFT 8 | ||
383 | #define WOL_PT2_LEN_SHIFT 16 | ||
384 | #define WOL_PT3_LEN_SHIFT 24 | ||
385 | #define WOL_PT4_LEN_SHIFT 0 | ||
386 | #define WOL_PT5_LEN_SHIFT 8 | ||
387 | #define WOL_PT6_LEN_SHIFT 16 | ||
388 | |||
389 | /* Internal SRAM Partition Register */ | ||
390 | #define RFDX_HEAD_ADDR_MASK 0x03FF | ||
391 | #define RFDX_HARD_ADDR_SHIFT 0 | ||
392 | #define RFDX_TAIL_ADDR_MASK 0x03FF | ||
393 | #define RFDX_TAIL_ADDR_SHIFT 16 | ||
394 | |||
395 | #define REG_SRAM_RFD0_INFO 0x1500 | ||
396 | #define REG_SRAM_RFD1_INFO 0x1504 | ||
397 | #define REG_SRAM_RFD2_INFO 0x1508 | ||
398 | #define REG_SRAM_RFD3_INFO 0x150C | ||
399 | |||
400 | #define REG_RFD_NIC_LEN 0x1510 /* In 8-bytes */ | ||
401 | #define RFD_NIC_LEN_MASK 0x03FF | ||
402 | |||
403 | #define REG_SRAM_TRD_ADDR 0x1518 | ||
404 | #define TPD_HEAD_ADDR_MASK 0x03FF | ||
405 | #define TPD_HEAD_ADDR_SHIFT 0 | ||
406 | #define TPD_TAIL_ADDR_MASK 0x03FF | ||
407 | #define TPD_TAIL_ADDR_SHIFT 16 | ||
408 | |||
409 | #define REG_SRAM_TRD_LEN 0x151C /* In 8-bytes */ | ||
410 | #define TPD_NIC_LEN_MASK 0x03FF | ||
411 | |||
412 | #define REG_SRAM_RXF_ADDR 0x1520 | ||
413 | #define REG_SRAM_RXF_LEN 0x1524 | ||
414 | #define REG_SRAM_TXF_ADDR 0x1528 | ||
415 | #define REG_SRAM_TXF_LEN 0x152C | ||
416 | #define REG_SRAM_TCPH_ADDR 0x1530 | ||
417 | #define REG_SRAM_PKTH_ADDR 0x1532 | ||
418 | |||
419 | /* | ||
420 | * Load Ptr Register | ||
421 | * Software sets this bit after the initialization of the head and tail */ | ||
422 | #define REG_LOAD_PTR 0x1534 | ||
423 | |||
424 | /* | ||
425 | * addresses of all descriptors, as well as the following descriptor | ||
426 | * control register, which triggers each function block to load the head | ||
427 | * pointer to prepare for the operation. This bit is then self-cleared | ||
428 | * after one cycle. | ||
429 | */ | ||
430 | #define REG_RX_BASE_ADDR_HI 0x1540 | ||
431 | #define REG_TX_BASE_ADDR_HI 0x1544 | ||
432 | #define REG_SMB_BASE_ADDR_HI 0x1548 | ||
433 | #define REG_SMB_BASE_ADDR_LO 0x154C | ||
434 | #define REG_RFD0_HEAD_ADDR_LO 0x1550 | ||
435 | #define REG_RFD1_HEAD_ADDR_LO 0x1554 | ||
436 | #define REG_RFD2_HEAD_ADDR_LO 0x1558 | ||
437 | #define REG_RFD3_HEAD_ADDR_LO 0x155C | ||
438 | #define REG_RFD_RING_SIZE 0x1560 | ||
439 | #define RFD_RING_SIZE_MASK 0x0FFF | ||
440 | #define REG_RX_BUF_SIZE 0x1564 | ||
441 | #define RX_BUF_SIZE_MASK 0xFFFF | ||
442 | #define REG_RRD0_HEAD_ADDR_LO 0x1568 | ||
443 | #define REG_RRD1_HEAD_ADDR_LO 0x156C | ||
444 | #define REG_RRD2_HEAD_ADDR_LO 0x1570 | ||
445 | #define REG_RRD3_HEAD_ADDR_LO 0x1574 | ||
446 | #define REG_RRD_RING_SIZE 0x1578 | ||
447 | #define RRD_RING_SIZE_MASK 0x0FFF | ||
448 | #define REG_HTPD_HEAD_ADDR_LO 0x157C | ||
449 | #define REG_NTPD_HEAD_ADDR_LO 0x1580 | ||
450 | #define REG_TPD_RING_SIZE 0x1584 | ||
451 | #define TPD_RING_SIZE_MASK 0xFFFF | ||
452 | #define REG_CMB_BASE_ADDR_LO 0x1588 | ||
453 | |||
454 | /* RSS about */ | ||
455 | #define REG_RSS_KEY0 0x14B0 | ||
456 | #define REG_RSS_KEY1 0x14B4 | ||
457 | #define REG_RSS_KEY2 0x14B8 | ||
458 | #define REG_RSS_KEY3 0x14BC | ||
459 | #define REG_RSS_KEY4 0x14C0 | ||
460 | #define REG_RSS_KEY5 0x14C4 | ||
461 | #define REG_RSS_KEY6 0x14C8 | ||
462 | #define REG_RSS_KEY7 0x14CC | ||
463 | #define REG_RSS_KEY8 0x14D0 | ||
464 | #define REG_RSS_KEY9 0x14D4 | ||
465 | #define REG_IDT_TABLE0 0x14E0 | ||
466 | #define REG_IDT_TABLE1 0x14E4 | ||
467 | #define REG_IDT_TABLE2 0x14E8 | ||
468 | #define REG_IDT_TABLE3 0x14EC | ||
469 | #define REG_IDT_TABLE4 0x14F0 | ||
470 | #define REG_IDT_TABLE5 0x14F4 | ||
471 | #define REG_IDT_TABLE6 0x14F8 | ||
472 | #define REG_IDT_TABLE7 0x14FC | ||
473 | #define REG_IDT_TABLE REG_IDT_TABLE0 | ||
474 | #define REG_RSS_HASH_VALUE 0x15B0 | ||
475 | #define REG_RSS_HASH_FLAG 0x15B4 | ||
476 | #define REG_BASE_CPU_NUMBER 0x15B8 | ||
477 | |||
478 | /* TXQ Control Register */ | ||
479 | #define REG_TXQ_CTRL 0x1590 | ||
480 | #define TXQ_NUM_TPD_BURST_MASK 0xF | ||
481 | #define TXQ_NUM_TPD_BURST_SHIFT 0 | ||
482 | #define TXQ_CTRL_IP_OPTION_EN 0x10 | ||
483 | #define TXQ_CTRL_EN 0x20 | ||
484 | #define TXQ_CTRL_ENH_MODE 0x40 | ||
485 | #define TXQ_CTRL_LS_8023_EN 0x80 | ||
486 | #define TXQ_TXF_BURST_NUM_SHIFT 16 | ||
487 | #define TXQ_TXF_BURST_NUM_MASK 0xFFFF | ||
488 | |||
489 | /* Jumbo packet Threshold for task offload */ | ||
490 | #define REG_TX_TSO_OFFLOAD_THRESH 0x1594 /* In 8-bytes */ | ||
491 | #define TX_TSO_OFFLOAD_THRESH_MASK 0x07FF | ||
492 | |||
493 | #define REG_TXF_WATER_MARK 0x1598 /* In 8-bytes */ | ||
494 | #define TXF_WATER_MARK_MASK 0x0FFF | ||
495 | #define TXF_LOW_WATER_MARK_SHIFT 0 | ||
496 | #define TXF_HIGH_WATER_MARK_SHIFT 16 | ||
497 | #define TXQ_CTRL_BURST_MODE_EN 0x80000000 | ||
498 | |||
499 | #define REG_THRUPUT_MON_CTRL 0x159C | ||
500 | #define THRUPUT_MON_RATE_MASK 0x3 | ||
501 | #define THRUPUT_MON_RATE_SHIFT 0 | ||
502 | #define THRUPUT_MON_EN 0x80 | ||
503 | |||
504 | /* RXQ Control Register */ | ||
505 | #define REG_RXQ_CTRL 0x15A0 | ||
506 | #define ASPM_THRUPUT_LIMIT_MASK 0x3 | ||
507 | #define ASPM_THRUPUT_LIMIT_SHIFT 0 | ||
508 | #define ASPM_THRUPUT_LIMIT_NO 0x00 | ||
509 | #define ASPM_THRUPUT_LIMIT_1M 0x01 | ||
510 | #define ASPM_THRUPUT_LIMIT_10M 0x02 | ||
511 | #define ASPM_THRUPUT_LIMIT_100M 0x04 | ||
512 | #define RXQ1_CTRL_EN 0x10 | ||
513 | #define RXQ2_CTRL_EN 0x20 | ||
514 | #define RXQ3_CTRL_EN 0x40 | ||
515 | #define IPV6_CHKSUM_CTRL_EN 0x80 | ||
516 | #define RSS_HASH_BITS_MASK 0x00FF | ||
517 | #define RSS_HASH_BITS_SHIFT 8 | ||
518 | #define RSS_HASH_IPV4 0x10000 | ||
519 | #define RSS_HASH_IPV4_TCP 0x20000 | ||
520 | #define RSS_HASH_IPV6 0x40000 | ||
521 | #define RSS_HASH_IPV6_TCP 0x80000 | ||
522 | #define RXQ_RFD_BURST_NUM_MASK 0x003F | ||
523 | #define RXQ_RFD_BURST_NUM_SHIFT 20 | ||
524 | #define RSS_MODE_MASK 0x0003 | ||
525 | #define RSS_MODE_SHIFT 26 | ||
526 | #define RSS_NIP_QUEUE_SEL_MASK 0x1 | ||
527 | #define RSS_NIP_QUEUE_SEL_SHIFT 28 | ||
528 | #define RRS_HASH_CTRL_EN 0x20000000 | ||
529 | #define RX_CUT_THRU_EN 0x40000000 | ||
530 | #define RXQ_CTRL_EN 0x80000000 | ||
531 | |||
532 | #define REG_RFD_FREE_THRESH 0x15A4 | ||
533 | #define RFD_FREE_THRESH_MASK 0x003F | ||
534 | #define RFD_FREE_HI_THRESH_SHIFT 0 | ||
535 | #define RFD_FREE_LO_THRESH_SHIFT 6 | ||
536 | |||
537 | /* RXF flow control register */ | ||
538 | #define REG_RXQ_RXF_PAUSE_THRESH 0x15A8 | ||
539 | #define RXQ_RXF_PAUSE_TH_HI_SHIFT 0 | ||
540 | #define RXQ_RXF_PAUSE_TH_HI_MASK 0x0FFF | ||
541 | #define RXQ_RXF_PAUSE_TH_LO_SHIFT 16 | ||
542 | #define RXQ_RXF_PAUSE_TH_LO_MASK 0x0FFF | ||
543 | |||
544 | #define REG_RXD_DMA_CTRL 0x15AC | ||
545 | #define RXD_DMA_THRESH_MASK 0x0FFF /* In 8-bytes */ | ||
546 | #define RXD_DMA_THRESH_SHIFT 0 | ||
547 | #define RXD_DMA_DOWN_TIMER_MASK 0xFFFF | ||
548 | #define RXD_DMA_DOWN_TIMER_SHIFT 16 | ||
549 | |||
550 | /* DMA Engine Control Register */ | ||
551 | #define REG_DMA_CTRL 0x15C0 | ||
552 | #define DMA_CTRL_DMAR_IN_ORDER 0x1 | ||
553 | #define DMA_CTRL_DMAR_ENH_ORDER 0x2 | ||
554 | #define DMA_CTRL_DMAR_OUT_ORDER 0x4 | ||
555 | #define DMA_CTRL_RCB_VALUE 0x8 | ||
556 | #define DMA_CTRL_DMAR_BURST_LEN_MASK 0x0007 | ||
557 | #define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4 | ||
558 | #define DMA_CTRL_DMAW_BURST_LEN_MASK 0x0007 | ||
559 | #define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7 | ||
560 | #define DMA_CTRL_DMAR_REQ_PRI 0x400 | ||
561 | #define DMA_CTRL_DMAR_DLY_CNT_MASK 0x001F | ||
562 | #define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11 | ||
563 | #define DMA_CTRL_DMAW_DLY_CNT_MASK 0x000F | ||
564 | #define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16 | ||
565 | #define DMA_CTRL_CMB_EN 0x100000 | ||
566 | #define DMA_CTRL_SMB_EN 0x200000 | ||
567 | #define DMA_CTRL_CMB_NOW 0x400000 | ||
568 | #define MAC_CTRL_SMB_DIS 0x1000000 | ||
569 | #define DMA_CTRL_SMB_NOW 0x80000000 | ||
570 | |||
571 | /* CMB/SMB Control Register */ | ||
572 | #define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */ | ||
573 | #define SMB_STAT_TIMER_MASK 0xFFFFFF | ||
574 | #define REG_CMB_TPD_THRESH 0x15C8 | ||
575 | #define CMB_TPD_THRESH_MASK 0xFFFF | ||
576 | #define REG_CMB_TX_TIMER 0x15CC /* 2us resolution */ | ||
577 | #define CMB_TX_TIMER_MASK 0xFFFF | ||
578 | |||
579 | /* Mail box */ | ||
580 | #define MB_RFDX_PROD_IDX_MASK 0xFFFF | ||
581 | #define REG_MB_RFD0_PROD_IDX 0x15E0 | ||
582 | #define REG_MB_RFD1_PROD_IDX 0x15E4 | ||
583 | #define REG_MB_RFD2_PROD_IDX 0x15E8 | ||
584 | #define REG_MB_RFD3_PROD_IDX 0x15EC | ||
585 | |||
586 | #define MB_PRIO_PROD_IDX_MASK 0xFFFF | ||
587 | #define REG_MB_PRIO_PROD_IDX 0x15F0 | ||
588 | #define MB_HTPD_PROD_IDX_SHIFT 0 | ||
589 | #define MB_NTPD_PROD_IDX_SHIFT 16 | ||
590 | |||
591 | #define MB_PRIO_CONS_IDX_MASK 0xFFFF | ||
592 | #define REG_MB_PRIO_CONS_IDX 0x15F4 | ||
593 | #define MB_HTPD_CONS_IDX_SHIFT 0 | ||
594 | #define MB_NTPD_CONS_IDX_SHIFT 16 | ||
595 | |||
596 | #define REG_MB_RFD01_CONS_IDX 0x15F8 | ||
597 | #define MB_RFD0_CONS_IDX_MASK 0x0000FFFF | ||
598 | #define MB_RFD1_CONS_IDX_MASK 0xFFFF0000 | ||
599 | #define REG_MB_RFD23_CONS_IDX 0x15FC | ||
600 | #define MB_RFD2_CONS_IDX_MASK 0x0000FFFF | ||
601 | #define MB_RFD3_CONS_IDX_MASK 0xFFFF0000 | ||
602 | |||
603 | /* Interrupt Status Register */ | ||
604 | #define REG_ISR 0x1600 | ||
605 | #define ISR_SMB 0x00000001 | ||
606 | #define ISR_TIMER 0x00000002 | ||
607 | /* | ||
608 | * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set | ||
609 | * in Table 51 Selene Master Control Register (Offset 0x1400). | ||
610 | */ | ||
611 | #define ISR_MANUAL 0x00000004 | ||
612 | #define ISR_HW_RXF_OV 0x00000008 /* RXF overflow interrupt */ | ||
613 | #define ISR_RFD0_UR 0x00000010 /* RFD0 under run */ | ||
614 | #define ISR_RFD1_UR 0x00000020 | ||
615 | #define ISR_RFD2_UR 0x00000040 | ||
616 | #define ISR_RFD3_UR 0x00000080 | ||
617 | #define ISR_TXF_UR 0x00000100 | ||
618 | #define ISR_DMAR_TO_RST 0x00000200 | ||
619 | #define ISR_DMAW_TO_RST 0x00000400 | ||
620 | #define ISR_TX_CREDIT 0x00000800 | ||
621 | #define ISR_GPHY 0x00001000 | ||
622 | /* GPHY low power state interrupt */ | ||
623 | #define ISR_GPHY_LPW 0x00002000 | ||
624 | #define ISR_TXQ_TO_RST 0x00004000 | ||
625 | #define ISR_TX_PKT 0x00008000 | ||
626 | #define ISR_RX_PKT_0 0x00010000 | ||
627 | #define ISR_RX_PKT_1 0x00020000 | ||
628 | #define ISR_RX_PKT_2 0x00040000 | ||
629 | #define ISR_RX_PKT_3 0x00080000 | ||
630 | #define ISR_MAC_RX 0x00100000 | ||
631 | #define ISR_MAC_TX 0x00200000 | ||
632 | #define ISR_UR_DETECTED 0x00400000 | ||
633 | #define ISR_FERR_DETECTED 0x00800000 | ||
634 | #define ISR_NFERR_DETECTED 0x01000000 | ||
635 | #define ISR_CERR_DETECTED 0x02000000 | ||
636 | #define ISR_PHY_LINKDOWN 0x04000000 | ||
637 | #define ISR_DIS_INT 0x80000000 | ||
638 | |||
639 | /* Interrupt Mask Register */ | ||
640 | #define REG_IMR 0x1604 | ||
641 | |||
642 | #define IMR_NORMAL_MASK (\ | ||
643 | ISR_MANUAL |\ | ||
644 | ISR_HW_RXF_OV |\ | ||
645 | ISR_RFD0_UR |\ | ||
646 | ISR_TXF_UR |\ | ||
647 | ISR_DMAR_TO_RST |\ | ||
648 | ISR_TXQ_TO_RST |\ | ||
649 | ISR_DMAW_TO_RST |\ | ||
650 | ISR_GPHY |\ | ||
651 | ISR_TX_PKT |\ | ||
652 | ISR_RX_PKT_0 |\ | ||
653 | ISR_GPHY_LPW |\ | ||
654 | ISR_PHY_LINKDOWN) | ||
655 | |||
656 | #define ISR_RX_PKT (\ | ||
657 | ISR_RX_PKT_0 |\ | ||
658 | ISR_RX_PKT_1 |\ | ||
659 | ISR_RX_PKT_2 |\ | ||
660 | ISR_RX_PKT_3) | ||
661 | |||
662 | #define ISR_OVER (\ | ||
663 | ISR_RFD0_UR |\ | ||
664 | ISR_RFD1_UR |\ | ||
665 | ISR_RFD2_UR |\ | ||
666 | ISR_RFD3_UR |\ | ||
667 | ISR_HW_RXF_OV |\ | ||
668 | ISR_TXF_UR) | ||
669 | |||
670 | #define ISR_ERROR (\ | ||
671 | ISR_DMAR_TO_RST |\ | ||
672 | ISR_TXQ_TO_RST |\ | ||
673 | ISR_DMAW_TO_RST |\ | ||
674 | ISR_PHY_LINKDOWN) | ||
675 | |||
676 | #define REG_INT_RETRIG_TIMER 0x1608 | ||
677 | #define INT_RETRIG_TIMER_MASK 0xFFFF | ||
678 | |||
679 | #define REG_HDS_CTRL 0x160C | ||
680 | #define HDS_CTRL_EN 0x0001 | ||
681 | #define HDS_CTRL_BACKFILLSIZE_SHIFT 8 | ||
682 | #define HDS_CTRL_BACKFILLSIZE_MASK 0x0FFF | ||
683 | #define HDS_CTRL_MAX_HDRSIZE_SHIFT 20 | ||
684 | #define HDS_CTRL_MAC_HDRSIZE_MASK 0x0FFF | ||
685 | |||
686 | #define REG_MAC_RX_STATUS_BIN 0x1700 | ||
687 | #define REG_MAC_RX_STATUS_END 0x175c | ||
688 | #define REG_MAC_TX_STATUS_BIN 0x1760 | ||
689 | #define REG_MAC_TX_STATUS_END 0x17c0 | ||
690 | |||
691 | /* DEBUG ADDR */ | ||
692 | #define REG_DEBUG_DATA0 0x1900 | ||
693 | #define REG_DEBUG_DATA1 0x1904 | ||
694 | |||
695 | /* PHY Control Register */ | ||
696 | #define MII_BMCR 0x00 | ||
697 | #define BMCR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ | ||
698 | #define BMCR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ | ||
699 | #define BMCR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ | ||
700 | #define BMCR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ | ||
701 | #define BMCR_ISOLATE 0x0400 /* Isolate PHY from MII */ | ||
702 | #define BMCR_POWER_DOWN 0x0800 /* Power down */ | ||
703 | #define BMCR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ | ||
704 | #define BMCR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ | ||
705 | #define BMCR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ | ||
706 | #define BMCR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ | ||
707 | #define BMCR_SPEED_MASK 0x2040 | ||
708 | #define BMCR_SPEED_1000 0x0040 | ||
709 | #define BMCR_SPEED_100 0x2000 | ||
710 | #define BMCR_SPEED_10 0x0000 | ||
711 | |||
712 | /* PHY Status Register */ | ||
713 | #define MII_BMSR 0x01 | ||
714 | #define BMMSR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ | ||
715 | #define BMSR_JABBER_DETECT 0x0002 /* Jabber Detected */ | ||
716 | #define BMSR_LINK_STATUS 0x0004 /* Link Status 1 = link */ | ||
717 | #define BMSR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ | ||
718 | #define BMSR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ | ||
719 | #define BMSR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ | ||
720 | #define BMSR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ | ||
721 | #define BMSR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ | ||
722 | #define BMSR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ | ||
723 | #define BMSR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ | ||
724 | #define BMSR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ | ||
725 | #define BMSR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ | ||
726 | #define BMSR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ | ||
727 | #define BMMII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ | ||
728 | #define BMMII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ | ||
729 | |||
730 | #define MII_PHYSID1 0x02 | ||
731 | #define MII_PHYSID2 0x03 | ||
732 | |||
733 | /* Autoneg Advertisement Register */ | ||
734 | #define MII_ADVERTISE 0x04 | ||
735 | #define ADVERTISE_SPEED_MASK 0x01E0 | ||
736 | #define ADVERTISE_DEFAULT_CAP 0x0DE0 | ||
737 | |||
738 | /* 1000BASE-T Control Register */ | ||
739 | #define MII_GIGA_CR 0x09 | ||
740 | #define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */ | ||
741 | |||
742 | #define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */ | ||
743 | #define GIGA_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ | ||
744 | #define GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ | ||
745 | #define GIGA_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ | ||
746 | #define GIGA_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ | ||
747 | #define GIGA_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ | ||
748 | #define GIGA_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ | ||
749 | #define GIGA_CR_1000T_SPEED_MASK 0x0300 | ||
750 | #define GIGA_CR_1000T_DEFAULT_CAP 0x0300 | ||
751 | |||
752 | /* PHY Specific Status Register */ | ||
753 | #define MII_GIGA_PSSR 0x11 | ||
754 | #define GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ | ||
755 | #define GIGA_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ | ||
756 | #define GIGA_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ | ||
757 | #define GIGA_PSSR_10MBS 0x0000 /* 00=10Mbs */ | ||
758 | #define GIGA_PSSR_100MBS 0x4000 /* 01=100Mbs */ | ||
759 | #define GIGA_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ | ||
760 | |||
761 | /* PHY Interrupt Enable Register */ | ||
762 | #define MII_IER 0x12 | ||
763 | #define IER_LINK_UP 0x0400 | ||
764 | #define IER_LINK_DOWN 0x0800 | ||
765 | |||
766 | /* PHY Interrupt Status Register */ | ||
767 | #define MII_ISR 0x13 | ||
768 | #define ISR_LINK_UP 0x0400 | ||
769 | #define ISR_LINK_DOWN 0x0800 | ||
770 | |||
771 | /* Cable-Detect-Test Control Register */ | ||
772 | #define MII_CDTC 0x16 | ||
773 | #define CDTC_EN_OFF 0 /* sc */ | ||
774 | #define CDTC_EN_BITS 1 | ||
775 | #define CDTC_PAIR_OFF 8 | ||
776 | #define CDTC_PAIR_BIT 2 | ||
777 | |||
778 | /* Cable-Detect-Test Status Register */ | ||
779 | #define MII_CDTS 0x1C | ||
780 | #define CDTS_STATUS_OFF 8 | ||
781 | #define CDTS_STATUS_BITS 2 | ||
782 | #define CDTS_STATUS_NORMAL 0 | ||
783 | #define CDTS_STATUS_SHORT 1 | ||
784 | #define CDTS_STATUS_OPEN 2 | ||
785 | #define CDTS_STATUS_INVALID 3 | ||
786 | |||
787 | #define MII_DBG_ADDR 0x1D | ||
788 | #define MII_DBG_DATA 0x1E | ||
789 | |||
790 | #define MII_ANA_CTRL_0 0x0 | ||
791 | #define ANA_RESTART_CAL 0x0001 | ||
792 | #define ANA_MANUL_SWICH_ON_SHIFT 0x1 | ||
793 | #define ANA_MANUL_SWICH_ON_MASK 0xF | ||
794 | #define ANA_MAN_ENABLE 0x0020 | ||
795 | #define ANA_SEL_HSP 0x0040 | ||
796 | #define ANA_EN_HB 0x0080 | ||
797 | #define ANA_EN_HBIAS 0x0100 | ||
798 | #define ANA_OEN_125M 0x0200 | ||
799 | #define ANA_EN_LCKDT 0x0400 | ||
800 | #define ANA_LCKDT_PHY 0x0800 | ||
801 | #define ANA_AFE_MODE 0x1000 | ||
802 | #define ANA_VCO_SLOW 0x2000 | ||
803 | #define ANA_VCO_FAST 0x4000 | ||
804 | #define ANA_SEL_CLK125M_DSP 0x8000 | ||
805 | |||
806 | #define MII_ANA_CTRL_4 0x4 | ||
807 | #define ANA_IECHO_ADJ_MASK 0xF | ||
808 | #define ANA_IECHO_ADJ_3_SHIFT 0 | ||
809 | #define ANA_IECHO_ADJ_2_SHIFT 4 | ||
810 | #define ANA_IECHO_ADJ_1_SHIFT 8 | ||
811 | #define ANA_IECHO_ADJ_0_SHIFT 12 | ||
812 | |||
813 | #define MII_ANA_CTRL_5 0x5 | ||
814 | #define ANA_SERDES_CDR_BW_SHIFT 0 | ||
815 | #define ANA_SERDES_CDR_BW_MASK 0x3 | ||
816 | #define ANA_MS_PAD_DBG 0x0004 | ||
817 | #define ANA_SPEEDUP_DBG 0x0008 | ||
818 | #define ANA_SERDES_TH_LOS_SHIFT 4 | ||
819 | #define ANA_SERDES_TH_LOS_MASK 0x3 | ||
820 | #define ANA_SERDES_EN_DEEM 0x0040 | ||
821 | #define ANA_SERDES_TXELECIDLE 0x0080 | ||
822 | #define ANA_SERDES_BEACON 0x0100 | ||
823 | #define ANA_SERDES_HALFTXDR 0x0200 | ||
824 | #define ANA_SERDES_SEL_HSP 0x0400 | ||
825 | #define ANA_SERDES_EN_PLL 0x0800 | ||
826 | #define ANA_SERDES_EN 0x1000 | ||
827 | #define ANA_SERDES_EN_LCKDT 0x2000 | ||
828 | |||
829 | #define MII_ANA_CTRL_11 0xB | ||
830 | #define ANA_PS_HIB_EN 0x8000 | ||
831 | |||
832 | #define MII_ANA_CTRL_18 0x12 | ||
833 | #define ANA_TEST_MODE_10BT_01SHIFT 0 | ||
834 | #define ANA_TEST_MODE_10BT_01MASK 0x3 | ||
835 | #define ANA_LOOP_SEL_10BT 0x0004 | ||
836 | #define ANA_RGMII_MODE_SW 0x0008 | ||
837 | #define ANA_EN_LONGECABLE 0x0010 | ||
838 | #define ANA_TEST_MODE_10BT_2 0x0020 | ||
839 | #define ANA_EN_10BT_IDLE 0x0400 | ||
840 | #define ANA_EN_MASK_TB 0x0800 | ||
841 | #define ANA_TRIGGER_SEL_TIMER_SHIFT 12 | ||
842 | #define ANA_TRIGGER_SEL_TIMER_MASK 0x3 | ||
843 | #define ANA_INTERVAL_SEL_TIMER_SHIFT 14 | ||
844 | #define ANA_INTERVAL_SEL_TIMER_MASK 0x3 | ||
845 | |||
846 | #define MII_ANA_CTRL_41 0x29 | ||
847 | #define ANA_TOP_PS_EN 0x8000 | ||
848 | |||
849 | #define MII_ANA_CTRL_54 0x36 | ||
850 | #define ANA_LONG_CABLE_TH_100_SHIFT 0 | ||
851 | #define ANA_LONG_CABLE_TH_100_MASK 0x3F | ||
852 | #define ANA_DESERVED 0x0040 | ||
853 | #define ANA_EN_LIT_CH 0x0080 | ||
854 | #define ANA_SHORT_CABLE_TH_100_SHIFT 8 | ||
855 | #define ANA_SHORT_CABLE_TH_100_MASK 0x3F | ||
856 | #define ANA_BP_BAD_LINK_ACCUM 0x4000 | ||
857 | #define ANA_BP_SMALL_BW 0x8000 | ||
858 | |||
859 | #endif /*_ATL1C_HW_H_*/ | ||
diff --git a/drivers/net/atl1c/atl1c_main.c b/drivers/net/atl1c/atl1c_main.c new file mode 100644 index 000000000000..deb7b53167ee --- /dev/null +++ b/drivers/net/atl1c/atl1c_main.c | |||
@@ -0,0 +1,2797 @@ | |||
1 | /* | ||
2 | * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved. | ||
3 | * | ||
4 | * Derived from Intel e1000 driver | ||
5 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License as published by the Free | ||
9 | * Software Foundation; either version 2 of the License, or (at your option) | ||
10 | * any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
15 | * more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License along with | ||
18 | * this program; if not, write to the Free Software Foundation, Inc., 59 | ||
19 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
20 | */ | ||
21 | |||
22 | #include "atl1c.h" | ||
23 | |||
24 | #define ATL1C_DRV_VERSION "1.0.0.1-NAPI" | ||
25 | char atl1c_driver_name[] = "atl1c"; | ||
26 | char atl1c_driver_version[] = ATL1C_DRV_VERSION; | ||
27 | #define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062 | ||
28 | #define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063 | ||
29 | /* | ||
30 | * atl1c_pci_tbl - PCI Device ID Table | ||
31 | * | ||
32 | * Wildcard entries (PCI_ANY_ID) should come last | ||
33 | * Last entry must be all 0s | ||
34 | * | ||
35 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | ||
36 | * Class, Class Mask, private data (not used) } | ||
37 | */ | ||
38 | static struct pci_device_id atl1c_pci_tbl[] = { | ||
39 | {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)}, | ||
40 | {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)}, | ||
41 | /* required last entry */ | ||
42 | { 0 } | ||
43 | }; | ||
44 | MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl); | ||
45 | |||
46 | MODULE_AUTHOR("Jie Yang <jie.yang@atheros.com>"); | ||
47 | MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver"); | ||
48 | MODULE_LICENSE("GPL"); | ||
49 | MODULE_VERSION(ATL1C_DRV_VERSION); | ||
50 | |||
51 | static int atl1c_stop_mac(struct atl1c_hw *hw); | ||
52 | static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw); | ||
53 | static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw); | ||
54 | static void atl1c_disable_l0s_l1(struct atl1c_hw *hw); | ||
55 | static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup); | ||
56 | static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter); | ||
57 | static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que, | ||
58 | int *work_done, int work_to_do); | ||
59 | |||
60 | static const u16 atl1c_pay_load_size[] = { | ||
61 | 128, 256, 512, 1024, 2048, 4096, | ||
62 | }; | ||
63 | |||
64 | static const u16 atl1c_rfd_prod_idx_regs[AT_MAX_RECEIVE_QUEUE] = | ||
65 | { | ||
66 | REG_MB_RFD0_PROD_IDX, | ||
67 | REG_MB_RFD1_PROD_IDX, | ||
68 | REG_MB_RFD2_PROD_IDX, | ||
69 | REG_MB_RFD3_PROD_IDX | ||
70 | }; | ||
71 | |||
72 | static const u16 atl1c_rfd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] = | ||
73 | { | ||
74 | REG_RFD0_HEAD_ADDR_LO, | ||
75 | REG_RFD1_HEAD_ADDR_LO, | ||
76 | REG_RFD2_HEAD_ADDR_LO, | ||
77 | REG_RFD3_HEAD_ADDR_LO | ||
78 | }; | ||
79 | |||
80 | static const u16 atl1c_rrd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] = | ||
81 | { | ||
82 | REG_RRD0_HEAD_ADDR_LO, | ||
83 | REG_RRD1_HEAD_ADDR_LO, | ||
84 | REG_RRD2_HEAD_ADDR_LO, | ||
85 | REG_RRD3_HEAD_ADDR_LO | ||
86 | }; | ||
87 | |||
88 | static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE | | ||
89 | NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP; | ||
90 | |||
91 | /* | ||
92 | * atl1c_init_pcie - init PCIE module | ||
93 | */ | ||
94 | static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag) | ||
95 | { | ||
96 | u32 data; | ||
97 | u32 pci_cmd; | ||
98 | struct pci_dev *pdev = hw->adapter->pdev; | ||
99 | |||
100 | AT_READ_REG(hw, PCI_COMMAND, &pci_cmd); | ||
101 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | ||
102 | pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | | ||
103 | PCI_COMMAND_IO); | ||
104 | AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd); | ||
105 | |||
106 | /* | ||
107 | * Clear any PowerSaveing Settings | ||
108 | */ | ||
109 | pci_enable_wake(pdev, PCI_D3hot, 0); | ||
110 | pci_enable_wake(pdev, PCI_D3cold, 0); | ||
111 | |||
112 | /* | ||
113 | * Mask some pcie error bits | ||
114 | */ | ||
115 | AT_READ_REG(hw, REG_PCIE_UC_SEVERITY, &data); | ||
116 | data &= ~PCIE_UC_SERVRITY_DLP; | ||
117 | data &= ~PCIE_UC_SERVRITY_FCP; | ||
118 | AT_WRITE_REG(hw, REG_PCIE_UC_SEVERITY, data); | ||
119 | |||
120 | if (flag & ATL1C_PCIE_L0S_L1_DISABLE) | ||
121 | atl1c_disable_l0s_l1(hw); | ||
122 | if (flag & ATL1C_PCIE_PHY_RESET) | ||
123 | AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT); | ||
124 | else | ||
125 | AT_WRITE_REG(hw, REG_GPHY_CTRL, | ||
126 | GPHY_CTRL_DEFAULT | GPHY_CTRL_EXT_RESET); | ||
127 | |||
128 | msleep(1); | ||
129 | } | ||
130 | |||
131 | /* | ||
132 | * atl1c_irq_enable - Enable default interrupt generation settings | ||
133 | * @adapter: board private structure | ||
134 | */ | ||
135 | static inline void atl1c_irq_enable(struct atl1c_adapter *adapter) | ||
136 | { | ||
137 | if (likely(atomic_dec_and_test(&adapter->irq_sem))) { | ||
138 | AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF); | ||
139 | AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask); | ||
140 | AT_WRITE_FLUSH(&adapter->hw); | ||
141 | } | ||
142 | } | ||
143 | |||
144 | /* | ||
145 | * atl1c_irq_disable - Mask off interrupt generation on the NIC | ||
146 | * @adapter: board private structure | ||
147 | */ | ||
148 | static inline void atl1c_irq_disable(struct atl1c_adapter *adapter) | ||
149 | { | ||
150 | atomic_inc(&adapter->irq_sem); | ||
151 | AT_WRITE_REG(&adapter->hw, REG_IMR, 0); | ||
152 | AT_WRITE_FLUSH(&adapter->hw); | ||
153 | synchronize_irq(adapter->pdev->irq); | ||
154 | } | ||
155 | |||
156 | /* | ||
157 | * atl1c_irq_reset - reset interrupt confiure on the NIC | ||
158 | * @adapter: board private structure | ||
159 | */ | ||
160 | static inline void atl1c_irq_reset(struct atl1c_adapter *adapter) | ||
161 | { | ||
162 | atomic_set(&adapter->irq_sem, 1); | ||
163 | atl1c_irq_enable(adapter); | ||
164 | } | ||
165 | |||
166 | /* | ||
167 | * atl1c_phy_config - Timer Call-back | ||
168 | * @data: pointer to netdev cast into an unsigned long | ||
169 | */ | ||
170 | static void atl1c_phy_config(unsigned long data) | ||
171 | { | ||
172 | struct atl1c_adapter *adapter = (struct atl1c_adapter *) data; | ||
173 | struct atl1c_hw *hw = &adapter->hw; | ||
174 | unsigned long flags; | ||
175 | |||
176 | spin_lock_irqsave(&adapter->mdio_lock, flags); | ||
177 | atl1c_restart_autoneg(hw); | ||
178 | spin_unlock_irqrestore(&adapter->mdio_lock, flags); | ||
179 | } | ||
180 | |||
181 | void atl1c_reinit_locked(struct atl1c_adapter *adapter) | ||
182 | { | ||
183 | |||
184 | WARN_ON(in_interrupt()); | ||
185 | atl1c_down(adapter); | ||
186 | atl1c_up(adapter); | ||
187 | clear_bit(__AT_RESETTING, &adapter->flags); | ||
188 | } | ||
189 | |||
190 | static void atl1c_reset_task(struct work_struct *work) | ||
191 | { | ||
192 | struct atl1c_adapter *adapter; | ||
193 | struct net_device *netdev; | ||
194 | |||
195 | adapter = container_of(work, struct atl1c_adapter, reset_task); | ||
196 | netdev = adapter->netdev; | ||
197 | |||
198 | netif_device_detach(netdev); | ||
199 | atl1c_down(adapter); | ||
200 | atl1c_up(adapter); | ||
201 | netif_device_attach(netdev); | ||
202 | } | ||
203 | |||
204 | static void atl1c_check_link_status(struct atl1c_adapter *adapter) | ||
205 | { | ||
206 | struct atl1c_hw *hw = &adapter->hw; | ||
207 | struct net_device *netdev = adapter->netdev; | ||
208 | struct pci_dev *pdev = adapter->pdev; | ||
209 | int err; | ||
210 | unsigned long flags; | ||
211 | u16 speed, duplex, phy_data; | ||
212 | |||
213 | spin_lock_irqsave(&adapter->mdio_lock, flags); | ||
214 | /* MII_BMSR must read twise */ | ||
215 | atl1c_read_phy_reg(hw, MII_BMSR, &phy_data); | ||
216 | atl1c_read_phy_reg(hw, MII_BMSR, &phy_data); | ||
217 | spin_unlock_irqrestore(&adapter->mdio_lock, flags); | ||
218 | |||
219 | if ((phy_data & BMSR_LSTATUS) == 0) { | ||
220 | /* link down */ | ||
221 | if (netif_carrier_ok(netdev)) { | ||
222 | hw->hibernate = true; | ||
223 | atl1c_set_aspm(hw, false); | ||
224 | if (atl1c_stop_mac(hw) != 0) | ||
225 | if (netif_msg_hw(adapter)) | ||
226 | dev_warn(&pdev->dev, | ||
227 | "stop mac failed\n"); | ||
228 | } | ||
229 | netif_carrier_off(netdev); | ||
230 | } else { | ||
231 | /* Link Up */ | ||
232 | hw->hibernate = false; | ||
233 | spin_lock_irqsave(&adapter->mdio_lock, flags); | ||
234 | err = atl1c_get_speed_and_duplex(hw, &speed, &duplex); | ||
235 | spin_unlock_irqrestore(&adapter->mdio_lock, flags); | ||
236 | if (unlikely(err)) | ||
237 | return; | ||
238 | /* link result is our setting */ | ||
239 | if (adapter->link_speed != speed || | ||
240 | adapter->link_duplex != duplex) { | ||
241 | adapter->link_speed = speed; | ||
242 | adapter->link_duplex = duplex; | ||
243 | atl1c_enable_tx_ctrl(hw); | ||
244 | atl1c_enable_rx_ctrl(hw); | ||
245 | atl1c_setup_mac_ctrl(adapter); | ||
246 | atl1c_set_aspm(hw, true); | ||
247 | if (netif_msg_link(adapter)) | ||
248 | dev_info(&pdev->dev, | ||
249 | "%s: %s NIC Link is Up<%d Mbps %s>\n", | ||
250 | atl1c_driver_name, netdev->name, | ||
251 | adapter->link_speed, | ||
252 | adapter->link_duplex == FULL_DUPLEX ? | ||
253 | "Full Duplex" : "Half Duplex"); | ||
254 | } | ||
255 | if (!netif_carrier_ok(netdev)) | ||
256 | netif_carrier_on(netdev); | ||
257 | } | ||
258 | } | ||
259 | |||
260 | /* | ||
261 | * atl1c_link_chg_task - deal with link change event Out of interrupt context | ||
262 | * @netdev: network interface device structure | ||
263 | */ | ||
264 | static void atl1c_link_chg_task(struct work_struct *work) | ||
265 | { | ||
266 | struct atl1c_adapter *adapter; | ||
267 | |||
268 | adapter = container_of(work, struct atl1c_adapter, link_chg_task); | ||
269 | atl1c_check_link_status(adapter); | ||
270 | } | ||
271 | |||
272 | static void atl1c_link_chg_event(struct atl1c_adapter *adapter) | ||
273 | { | ||
274 | struct net_device *netdev = adapter->netdev; | ||
275 | struct pci_dev *pdev = adapter->pdev; | ||
276 | u16 phy_data; | ||
277 | u16 link_up; | ||
278 | |||
279 | spin_lock(&adapter->mdio_lock); | ||
280 | atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); | ||
281 | atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); | ||
282 | spin_unlock(&adapter->mdio_lock); | ||
283 | link_up = phy_data & BMSR_LSTATUS; | ||
284 | /* notify upper layer link down ASAP */ | ||
285 | if (!link_up) { | ||
286 | if (netif_carrier_ok(netdev)) { | ||
287 | /* old link state: Up */ | ||
288 | netif_carrier_off(netdev); | ||
289 | if (netif_msg_link(adapter)) | ||
290 | dev_info(&pdev->dev, | ||
291 | "%s: %s NIC Link is Down\n", | ||
292 | atl1c_driver_name, netdev->name); | ||
293 | adapter->link_speed = SPEED_0; | ||
294 | } | ||
295 | } | ||
296 | schedule_work(&adapter->link_chg_task); | ||
297 | } | ||
298 | |||
299 | static void atl1c_del_timer(struct atl1c_adapter *adapter) | ||
300 | { | ||
301 | del_timer_sync(&adapter->phy_config_timer); | ||
302 | } | ||
303 | |||
304 | static void atl1c_cancel_work(struct atl1c_adapter *adapter) | ||
305 | { | ||
306 | cancel_work_sync(&adapter->reset_task); | ||
307 | cancel_work_sync(&adapter->link_chg_task); | ||
308 | } | ||
309 | |||
310 | /* | ||
311 | * atl1c_tx_timeout - Respond to a Tx Hang | ||
312 | * @netdev: network interface device structure | ||
313 | */ | ||
314 | static void atl1c_tx_timeout(struct net_device *netdev) | ||
315 | { | ||
316 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
317 | |||
318 | /* Do the reset outside of interrupt context */ | ||
319 | schedule_work(&adapter->reset_task); | ||
320 | } | ||
321 | |||
322 | /* | ||
323 | * atl1c_set_multi - Multicast and Promiscuous mode set | ||
324 | * @netdev: network interface device structure | ||
325 | * | ||
326 | * The set_multi entry point is called whenever the multicast address | ||
327 | * list or the network interface flags are updated. This routine is | ||
328 | * responsible for configuring the hardware for proper multicast, | ||
329 | * promiscuous mode, and all-multi behavior. | ||
330 | */ | ||
331 | static void atl1c_set_multi(struct net_device *netdev) | ||
332 | { | ||
333 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
334 | struct atl1c_hw *hw = &adapter->hw; | ||
335 | struct dev_mc_list *mc_ptr; | ||
336 | u32 mac_ctrl_data; | ||
337 | u32 hash_value; | ||
338 | |||
339 | /* Check for Promiscuous and All Multicast modes */ | ||
340 | AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data); | ||
341 | |||
342 | if (netdev->flags & IFF_PROMISC) { | ||
343 | mac_ctrl_data |= MAC_CTRL_PROMIS_EN; | ||
344 | } else if (netdev->flags & IFF_ALLMULTI) { | ||
345 | mac_ctrl_data |= MAC_CTRL_MC_ALL_EN; | ||
346 | mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN; | ||
347 | } else { | ||
348 | mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN); | ||
349 | } | ||
350 | |||
351 | AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data); | ||
352 | |||
353 | /* clear the old settings from the multicast hash table */ | ||
354 | AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); | ||
355 | AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); | ||
356 | |||
357 | /* comoute mc addresses' hash value ,and put it into hash table */ | ||
358 | for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) { | ||
359 | hash_value = atl1c_hash_mc_addr(hw, mc_ptr->dmi_addr); | ||
360 | atl1c_hash_set(hw, hash_value); | ||
361 | } | ||
362 | } | ||
363 | |||
364 | static void atl1c_vlan_rx_register(struct net_device *netdev, | ||
365 | struct vlan_group *grp) | ||
366 | { | ||
367 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
368 | struct pci_dev *pdev = adapter->pdev; | ||
369 | u32 mac_ctrl_data = 0; | ||
370 | |||
371 | if (netif_msg_pktdata(adapter)) | ||
372 | dev_dbg(&pdev->dev, "atl1c_vlan_rx_register\n"); | ||
373 | |||
374 | atl1c_irq_disable(adapter); | ||
375 | |||
376 | adapter->vlgrp = grp; | ||
377 | AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data); | ||
378 | |||
379 | if (grp) { | ||
380 | /* enable VLAN tag insert/strip */ | ||
381 | mac_ctrl_data |= MAC_CTRL_RMV_VLAN; | ||
382 | } else { | ||
383 | /* disable VLAN tag insert/strip */ | ||
384 | mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN; | ||
385 | } | ||
386 | |||
387 | AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data); | ||
388 | atl1c_irq_enable(adapter); | ||
389 | } | ||
390 | |||
391 | static void atl1c_restore_vlan(struct atl1c_adapter *adapter) | ||
392 | { | ||
393 | struct pci_dev *pdev = adapter->pdev; | ||
394 | |||
395 | if (netif_msg_pktdata(adapter)) | ||
396 | dev_dbg(&pdev->dev, "atl1c_restore_vlan !"); | ||
397 | atl1c_vlan_rx_register(adapter->netdev, adapter->vlgrp); | ||
398 | } | ||
399 | /* | ||
400 | * atl1c_set_mac - Change the Ethernet Address of the NIC | ||
401 | * @netdev: network interface device structure | ||
402 | * @p: pointer to an address structure | ||
403 | * | ||
404 | * Returns 0 on success, negative on failure | ||
405 | */ | ||
406 | static int atl1c_set_mac_addr(struct net_device *netdev, void *p) | ||
407 | { | ||
408 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
409 | struct sockaddr *addr = p; | ||
410 | |||
411 | if (!is_valid_ether_addr(addr->sa_data)) | ||
412 | return -EADDRNOTAVAIL; | ||
413 | |||
414 | if (netif_running(netdev)) | ||
415 | return -EBUSY; | ||
416 | |||
417 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | ||
418 | memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len); | ||
419 | |||
420 | atl1c_hw_set_mac_addr(&adapter->hw); | ||
421 | |||
422 | return 0; | ||
423 | } | ||
424 | |||
425 | static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter, | ||
426 | struct net_device *dev) | ||
427 | { | ||
428 | int mtu = dev->mtu; | ||
429 | |||
430 | adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ? | ||
431 | roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE; | ||
432 | } | ||
433 | /* | ||
434 | * atl1c_change_mtu - Change the Maximum Transfer Unit | ||
435 | * @netdev: network interface device structure | ||
436 | * @new_mtu: new value for maximum frame size | ||
437 | * | ||
438 | * Returns 0 on success, negative on failure | ||
439 | */ | ||
440 | static int atl1c_change_mtu(struct net_device *netdev, int new_mtu) | ||
441 | { | ||
442 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
443 | int old_mtu = netdev->mtu; | ||
444 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | ||
445 | |||
446 | if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || | ||
447 | (max_frame > MAX_JUMBO_FRAME_SIZE)) { | ||
448 | if (netif_msg_link(adapter)) | ||
449 | dev_warn(&adapter->pdev->dev, "invalid MTU setting\n"); | ||
450 | return -EINVAL; | ||
451 | } | ||
452 | /* set MTU */ | ||
453 | if (old_mtu != new_mtu && netif_running(netdev)) { | ||
454 | while (test_and_set_bit(__AT_RESETTING, &adapter->flags)) | ||
455 | msleep(1); | ||
456 | netdev->mtu = new_mtu; | ||
457 | adapter->hw.max_frame_size = new_mtu; | ||
458 | atl1c_set_rxbufsize(adapter, netdev); | ||
459 | atl1c_down(adapter); | ||
460 | atl1c_up(adapter); | ||
461 | clear_bit(__AT_RESETTING, &adapter->flags); | ||
462 | if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) { | ||
463 | u32 phy_data; | ||
464 | |||
465 | AT_READ_REG(&adapter->hw, 0x1414, &phy_data); | ||
466 | phy_data |= 0x10000000; | ||
467 | AT_WRITE_REG(&adapter->hw, 0x1414, phy_data); | ||
468 | } | ||
469 | |||
470 | } | ||
471 | return 0; | ||
472 | } | ||
473 | |||
474 | /* | ||
475 | * caller should hold mdio_lock | ||
476 | */ | ||
477 | static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num) | ||
478 | { | ||
479 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
480 | u16 result; | ||
481 | |||
482 | atl1c_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result); | ||
483 | return result; | ||
484 | } | ||
485 | |||
486 | static void atl1c_mdio_write(struct net_device *netdev, int phy_id, | ||
487 | int reg_num, int val) | ||
488 | { | ||
489 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
490 | |||
491 | atl1c_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val); | ||
492 | } | ||
493 | |||
494 | /* | ||
495 | * atl1c_mii_ioctl - | ||
496 | * @netdev: | ||
497 | * @ifreq: | ||
498 | * @cmd: | ||
499 | */ | ||
500 | static int atl1c_mii_ioctl(struct net_device *netdev, | ||
501 | struct ifreq *ifr, int cmd) | ||
502 | { | ||
503 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
504 | struct pci_dev *pdev = adapter->pdev; | ||
505 | struct mii_ioctl_data *data = if_mii(ifr); | ||
506 | unsigned long flags; | ||
507 | int retval = 0; | ||
508 | |||
509 | if (!netif_running(netdev)) | ||
510 | return -EINVAL; | ||
511 | |||
512 | spin_lock_irqsave(&adapter->mdio_lock, flags); | ||
513 | switch (cmd) { | ||
514 | case SIOCGMIIPHY: | ||
515 | data->phy_id = 0; | ||
516 | break; | ||
517 | |||
518 | case SIOCGMIIREG: | ||
519 | if (!capable(CAP_NET_ADMIN)) { | ||
520 | retval = -EPERM; | ||
521 | goto out; | ||
522 | } | ||
523 | if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, | ||
524 | &data->val_out)) { | ||
525 | retval = -EIO; | ||
526 | goto out; | ||
527 | } | ||
528 | break; | ||
529 | |||
530 | case SIOCSMIIREG: | ||
531 | if (!capable(CAP_NET_ADMIN)) { | ||
532 | retval = -EPERM; | ||
533 | goto out; | ||
534 | } | ||
535 | if (data->reg_num & ~(0x1F)) { | ||
536 | retval = -EFAULT; | ||
537 | goto out; | ||
538 | } | ||
539 | |||
540 | dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x", | ||
541 | data->reg_num, data->val_in); | ||
542 | if (atl1c_write_phy_reg(&adapter->hw, | ||
543 | data->reg_num, data->val_in)) { | ||
544 | retval = -EIO; | ||
545 | goto out; | ||
546 | } | ||
547 | break; | ||
548 | |||
549 | default: | ||
550 | retval = -EOPNOTSUPP; | ||
551 | break; | ||
552 | } | ||
553 | out: | ||
554 | spin_unlock_irqrestore(&adapter->mdio_lock, flags); | ||
555 | return retval; | ||
556 | } | ||
557 | |||
558 | /* | ||
559 | * atl1c_ioctl - | ||
560 | * @netdev: | ||
561 | * @ifreq: | ||
562 | * @cmd: | ||
563 | */ | ||
564 | static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | ||
565 | { | ||
566 | switch (cmd) { | ||
567 | case SIOCGMIIPHY: | ||
568 | case SIOCGMIIREG: | ||
569 | case SIOCSMIIREG: | ||
570 | return atl1c_mii_ioctl(netdev, ifr, cmd); | ||
571 | default: | ||
572 | return -EOPNOTSUPP; | ||
573 | } | ||
574 | } | ||
575 | |||
576 | /* | ||
577 | * atl1c_alloc_queues - Allocate memory for all rings | ||
578 | * @adapter: board private structure to initialize | ||
579 | * | ||
580 | */ | ||
581 | static int __devinit atl1c_alloc_queues(struct atl1c_adapter *adapter) | ||
582 | { | ||
583 | return 0; | ||
584 | } | ||
585 | |||
586 | static void atl1c_set_mac_type(struct atl1c_hw *hw) | ||
587 | { | ||
588 | switch (hw->device_id) { | ||
589 | case PCI_DEVICE_ID_ATTANSIC_L2C: | ||
590 | hw->nic_type = athr_l2c; | ||
591 | break; | ||
592 | |||
593 | case PCI_DEVICE_ID_ATTANSIC_L1C: | ||
594 | hw->nic_type = athr_l1c; | ||
595 | break; | ||
596 | |||
597 | default: | ||
598 | break; | ||
599 | } | ||
600 | } | ||
601 | |||
602 | static int atl1c_setup_mac_funcs(struct atl1c_hw *hw) | ||
603 | { | ||
604 | u32 phy_status_data; | ||
605 | u32 link_ctrl_data; | ||
606 | |||
607 | atl1c_set_mac_type(hw); | ||
608 | AT_READ_REG(hw, REG_PHY_STATUS, &phy_status_data); | ||
609 | AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data); | ||
610 | |||
611 | hw->ctrl_flags = ATL1C_INTR_CLEAR_ON_READ | | ||
612 | ATL1C_INTR_MODRT_ENABLE | | ||
613 | ATL1C_RX_IPV6_CHKSUM | | ||
614 | ATL1C_TXQ_MODE_ENHANCE; | ||
615 | if (link_ctrl_data & LINK_CTRL_L0S_EN) | ||
616 | hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT; | ||
617 | if (link_ctrl_data & LINK_CTRL_L1_EN) | ||
618 | hw->ctrl_flags |= ATL1C_ASPM_L1_SUPPORT; | ||
619 | |||
620 | if (hw->nic_type == athr_l1c) { | ||
621 | hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON; | ||
622 | hw->ctrl_flags |= ATL1C_LINK_CAP_1000M; | ||
623 | } | ||
624 | return 0; | ||
625 | } | ||
626 | /* | ||
627 | * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter) | ||
628 | * @adapter: board private structure to initialize | ||
629 | * | ||
630 | * atl1c_sw_init initializes the Adapter private data structure. | ||
631 | * Fields are initialized based on PCI device information and | ||
632 | * OS network device settings (MTU size). | ||
633 | */ | ||
634 | static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter) | ||
635 | { | ||
636 | struct atl1c_hw *hw = &adapter->hw; | ||
637 | struct pci_dev *pdev = adapter->pdev; | ||
638 | |||
639 | adapter->wol = 0; | ||
640 | adapter->link_speed = SPEED_0; | ||
641 | adapter->link_duplex = FULL_DUPLEX; | ||
642 | adapter->num_rx_queues = AT_DEF_RECEIVE_QUEUE; | ||
643 | adapter->tpd_ring[0].count = 1024; | ||
644 | adapter->rfd_ring[0].count = 512; | ||
645 | |||
646 | hw->vendor_id = pdev->vendor; | ||
647 | hw->device_id = pdev->device; | ||
648 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | ||
649 | hw->subsystem_id = pdev->subsystem_device; | ||
650 | |||
651 | /* before link up, we assume hibernate is true */ | ||
652 | hw->hibernate = true; | ||
653 | hw->media_type = MEDIA_TYPE_AUTO_SENSOR; | ||
654 | if (atl1c_setup_mac_funcs(hw) != 0) { | ||
655 | dev_err(&pdev->dev, "set mac function pointers failed\n"); | ||
656 | return -1; | ||
657 | } | ||
658 | hw->intr_mask = IMR_NORMAL_MASK; | ||
659 | hw->phy_configured = false; | ||
660 | hw->preamble_len = 7; | ||
661 | hw->max_frame_size = adapter->netdev->mtu; | ||
662 | if (adapter->num_rx_queues < 2) { | ||
663 | hw->rss_type = atl1c_rss_disable; | ||
664 | hw->rss_mode = atl1c_rss_mode_disable; | ||
665 | } else { | ||
666 | hw->rss_type = atl1c_rss_ipv4; | ||
667 | hw->rss_mode = atl1c_rss_mul_que_mul_int; | ||
668 | hw->rss_hash_bits = 16; | ||
669 | } | ||
670 | hw->autoneg_advertised = ADVERTISED_Autoneg; | ||
671 | hw->indirect_tab = 0xE4E4E4E4; | ||
672 | hw->base_cpu = 0; | ||
673 | |||
674 | hw->ict = 50000; /* 100ms */ | ||
675 | hw->smb_timer = 200000; /* 400ms */ | ||
676 | hw->cmb_tpd = 4; | ||
677 | hw->cmb_tx_timer = 1; /* 2 us */ | ||
678 | hw->rx_imt = 200; | ||
679 | hw->tx_imt = 1000; | ||
680 | |||
681 | hw->tpd_burst = 5; | ||
682 | hw->rfd_burst = 8; | ||
683 | hw->dma_order = atl1c_dma_ord_out; | ||
684 | hw->dmar_block = atl1c_dma_req_1024; | ||
685 | hw->dmaw_block = atl1c_dma_req_1024; | ||
686 | hw->dmar_dly_cnt = 15; | ||
687 | hw->dmaw_dly_cnt = 4; | ||
688 | |||
689 | if (atl1c_alloc_queues(adapter)) { | ||
690 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | ||
691 | return -ENOMEM; | ||
692 | } | ||
693 | /* TODO */ | ||
694 | atl1c_set_rxbufsize(adapter, adapter->netdev); | ||
695 | atomic_set(&adapter->irq_sem, 1); | ||
696 | spin_lock_init(&adapter->mdio_lock); | ||
697 | spin_lock_init(&adapter->tx_lock); | ||
698 | set_bit(__AT_DOWN, &adapter->flags); | ||
699 | |||
700 | return 0; | ||
701 | } | ||
702 | |||
703 | /* | ||
704 | * atl1c_clean_tx_ring - Free Tx-skb | ||
705 | * @adapter: board private structure | ||
706 | */ | ||
707 | static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter, | ||
708 | enum atl1c_trans_queue type) | ||
709 | { | ||
710 | struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type]; | ||
711 | struct atl1c_buffer *buffer_info; | ||
712 | struct pci_dev *pdev = adapter->pdev; | ||
713 | u16 index, ring_count; | ||
714 | |||
715 | ring_count = tpd_ring->count; | ||
716 | for (index = 0; index < ring_count; index++) { | ||
717 | buffer_info = &tpd_ring->buffer_info[index]; | ||
718 | if (buffer_info->state == ATL1_BUFFER_FREE) | ||
719 | continue; | ||
720 | if (buffer_info->dma) | ||
721 | pci_unmap_single(pdev, buffer_info->dma, | ||
722 | buffer_info->length, | ||
723 | PCI_DMA_TODEVICE); | ||
724 | if (buffer_info->skb) | ||
725 | dev_kfree_skb(buffer_info->skb); | ||
726 | buffer_info->dma = 0; | ||
727 | buffer_info->skb = NULL; | ||
728 | buffer_info->state = ATL1_BUFFER_FREE; | ||
729 | } | ||
730 | |||
731 | /* Zero out Tx-buffers */ | ||
732 | memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) * | ||
733 | ring_count); | ||
734 | atomic_set(&tpd_ring->next_to_clean, 0); | ||
735 | tpd_ring->next_to_use = 0; | ||
736 | } | ||
737 | |||
738 | /* | ||
739 | * atl1c_clean_rx_ring - Free rx-reservation skbs | ||
740 | * @adapter: board private structure | ||
741 | */ | ||
742 | static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter) | ||
743 | { | ||
744 | struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring; | ||
745 | struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring; | ||
746 | struct atl1c_buffer *buffer_info; | ||
747 | struct pci_dev *pdev = adapter->pdev; | ||
748 | int i, j; | ||
749 | |||
750 | for (i = 0; i < adapter->num_rx_queues; i++) { | ||
751 | for (j = 0; j < rfd_ring[i].count; j++) { | ||
752 | buffer_info = &rfd_ring[i].buffer_info[j]; | ||
753 | if (buffer_info->state == ATL1_BUFFER_FREE) | ||
754 | continue; | ||
755 | if (buffer_info->dma) | ||
756 | pci_unmap_single(pdev, buffer_info->dma, | ||
757 | buffer_info->length, | ||
758 | PCI_DMA_FROMDEVICE); | ||
759 | if (buffer_info->skb) | ||
760 | dev_kfree_skb(buffer_info->skb); | ||
761 | buffer_info->state = ATL1_BUFFER_FREE; | ||
762 | buffer_info->skb = NULL; | ||
763 | } | ||
764 | /* zero out the descriptor ring */ | ||
765 | memset(rfd_ring[i].desc, 0, rfd_ring[i].size); | ||
766 | rfd_ring[i].next_to_clean = 0; | ||
767 | rfd_ring[i].next_to_use = 0; | ||
768 | rrd_ring[i].next_to_use = 0; | ||
769 | rrd_ring[i].next_to_clean = 0; | ||
770 | } | ||
771 | } | ||
772 | |||
773 | /* | ||
774 | * Read / Write Ptr Initialize: | ||
775 | */ | ||
776 | static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter) | ||
777 | { | ||
778 | struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring; | ||
779 | struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring; | ||
780 | struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring; | ||
781 | struct atl1c_buffer *buffer_info; | ||
782 | int i, j; | ||
783 | |||
784 | for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) { | ||
785 | tpd_ring[i].next_to_use = 0; | ||
786 | atomic_set(&tpd_ring[i].next_to_clean, 0); | ||
787 | buffer_info = tpd_ring[i].buffer_info; | ||
788 | for (j = 0; j < tpd_ring->count; j++) | ||
789 | buffer_info[i].state = ATL1_BUFFER_FREE; | ||
790 | } | ||
791 | for (i = 0; i < adapter->num_rx_queues; i++) { | ||
792 | rfd_ring[i].next_to_use = 0; | ||
793 | rfd_ring[i].next_to_clean = 0; | ||
794 | rrd_ring[i].next_to_use = 0; | ||
795 | rrd_ring[i].next_to_clean = 0; | ||
796 | for (j = 0; j < rfd_ring[i].count; j++) { | ||
797 | buffer_info = &rfd_ring[i].buffer_info[j]; | ||
798 | buffer_info->state = ATL1_BUFFER_FREE; | ||
799 | } | ||
800 | } | ||
801 | } | ||
802 | |||
803 | /* | ||
804 | * atl1c_free_ring_resources - Free Tx / RX descriptor Resources | ||
805 | * @adapter: board private structure | ||
806 | * | ||
807 | * Free all transmit software resources | ||
808 | */ | ||
809 | static void atl1c_free_ring_resources(struct atl1c_adapter *adapter) | ||
810 | { | ||
811 | struct pci_dev *pdev = adapter->pdev; | ||
812 | |||
813 | pci_free_consistent(pdev, adapter->ring_header.size, | ||
814 | adapter->ring_header.desc, | ||
815 | adapter->ring_header.dma); | ||
816 | adapter->ring_header.desc = NULL; | ||
817 | |||
818 | /* Note: just free tdp_ring.buffer_info, | ||
819 | * it contain rfd_ring.buffer_info, do not double free */ | ||
820 | if (adapter->tpd_ring[0].buffer_info) { | ||
821 | kfree(adapter->tpd_ring[0].buffer_info); | ||
822 | adapter->tpd_ring[0].buffer_info = NULL; | ||
823 | } | ||
824 | } | ||
825 | |||
826 | /* | ||
827 | * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources | ||
828 | * @adapter: board private structure | ||
829 | * | ||
830 | * Return 0 on success, negative on failure | ||
831 | */ | ||
832 | static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter) | ||
833 | { | ||
834 | struct pci_dev *pdev = adapter->pdev; | ||
835 | struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring; | ||
836 | struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring; | ||
837 | struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring; | ||
838 | struct atl1c_ring_header *ring_header = &adapter->ring_header; | ||
839 | int num_rx_queues = adapter->num_rx_queues; | ||
840 | int size; | ||
841 | int i; | ||
842 | int count = 0; | ||
843 | int rx_desc_count = 0; | ||
844 | u32 offset = 0; | ||
845 | |||
846 | rrd_ring[0].count = rfd_ring[0].count; | ||
847 | for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++) | ||
848 | tpd_ring[i].count = tpd_ring[0].count; | ||
849 | |||
850 | for (i = 1; i < adapter->num_rx_queues; i++) | ||
851 | rfd_ring[i].count = rrd_ring[i].count = rfd_ring[0].count; | ||
852 | |||
853 | /* 2 tpd queue, one high priority queue, | ||
854 | * another normal priority queue */ | ||
855 | size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 + | ||
856 | rfd_ring->count * num_rx_queues); | ||
857 | tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL); | ||
858 | if (unlikely(!tpd_ring->buffer_info)) { | ||
859 | dev_err(&pdev->dev, "kzalloc failed, size = %d\n", | ||
860 | size); | ||
861 | goto err_nomem; | ||
862 | } | ||
863 | for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) { | ||
864 | tpd_ring[i].buffer_info = | ||
865 | (struct atl1c_buffer *) (tpd_ring->buffer_info + count); | ||
866 | count += tpd_ring[i].count; | ||
867 | } | ||
868 | |||
869 | for (i = 0; i < num_rx_queues; i++) { | ||
870 | rfd_ring[i].buffer_info = | ||
871 | (struct atl1c_buffer *) (tpd_ring->buffer_info + count); | ||
872 | count += rfd_ring[i].count; | ||
873 | rx_desc_count += rfd_ring[i].count; | ||
874 | } | ||
875 | /* | ||
876 | * real ring DMA buffer | ||
877 | * each ring/block may need up to 8 bytes for alignment, hence the | ||
878 | * additional bytes tacked onto the end. | ||
879 | */ | ||
880 | ring_header->size = size = | ||
881 | sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 + | ||
882 | sizeof(struct atl1c_rx_free_desc) * rx_desc_count + | ||
883 | sizeof(struct atl1c_recv_ret_status) * rx_desc_count + | ||
884 | sizeof(struct atl1c_hw_stats) + | ||
885 | 8 * 4 + 8 * 2 * num_rx_queues; | ||
886 | |||
887 | ring_header->desc = pci_alloc_consistent(pdev, ring_header->size, | ||
888 | &ring_header->dma); | ||
889 | if (unlikely(!ring_header->desc)) { | ||
890 | dev_err(&pdev->dev, "pci_alloc_consistend failed\n"); | ||
891 | goto err_nomem; | ||
892 | } | ||
893 | memset(ring_header->desc, 0, ring_header->size); | ||
894 | /* init TPD ring */ | ||
895 | |||
896 | tpd_ring[0].dma = roundup(ring_header->dma, 8); | ||
897 | offset = tpd_ring[0].dma - ring_header->dma; | ||
898 | for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) { | ||
899 | tpd_ring[i].dma = ring_header->dma + offset; | ||
900 | tpd_ring[i].desc = (u8 *) ring_header->desc + offset; | ||
901 | tpd_ring[i].size = | ||
902 | sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count; | ||
903 | offset += roundup(tpd_ring[i].size, 8); | ||
904 | } | ||
905 | /* init RFD ring */ | ||
906 | for (i = 0; i < num_rx_queues; i++) { | ||
907 | rfd_ring[i].dma = ring_header->dma + offset; | ||
908 | rfd_ring[i].desc = (u8 *) ring_header->desc + offset; | ||
909 | rfd_ring[i].size = sizeof(struct atl1c_rx_free_desc) * | ||
910 | rfd_ring[i].count; | ||
911 | offset += roundup(rfd_ring[i].size, 8); | ||
912 | } | ||
913 | |||
914 | /* init RRD ring */ | ||
915 | for (i = 0; i < num_rx_queues; i++) { | ||
916 | rrd_ring[i].dma = ring_header->dma + offset; | ||
917 | rrd_ring[i].desc = (u8 *) ring_header->desc + offset; | ||
918 | rrd_ring[i].size = sizeof(struct atl1c_recv_ret_status) * | ||
919 | rrd_ring[i].count; | ||
920 | offset += roundup(rrd_ring[i].size, 8); | ||
921 | } | ||
922 | |||
923 | adapter->smb.dma = ring_header->dma + offset; | ||
924 | adapter->smb.smb = (u8 *)ring_header->desc + offset; | ||
925 | return 0; | ||
926 | |||
927 | err_nomem: | ||
928 | kfree(tpd_ring->buffer_info); | ||
929 | return -ENOMEM; | ||
930 | } | ||
931 | |||
932 | static void atl1c_configure_des_ring(struct atl1c_adapter *adapter) | ||
933 | { | ||
934 | struct atl1c_hw *hw = &adapter->hw; | ||
935 | struct atl1c_rfd_ring *rfd_ring = (struct atl1c_rfd_ring *) | ||
936 | adapter->rfd_ring; | ||
937 | struct atl1c_rrd_ring *rrd_ring = (struct atl1c_rrd_ring *) | ||
938 | adapter->rrd_ring; | ||
939 | struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *) | ||
940 | adapter->tpd_ring; | ||
941 | struct atl1c_cmb *cmb = (struct atl1c_cmb *) &adapter->cmb; | ||
942 | struct atl1c_smb *smb = (struct atl1c_smb *) &adapter->smb; | ||
943 | int i; | ||
944 | |||
945 | /* TPD */ | ||
946 | AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI, | ||
947 | (u32)((tpd_ring[atl1c_trans_normal].dma & | ||
948 | AT_DMA_HI_ADDR_MASK) >> 32)); | ||
949 | /* just enable normal priority TX queue */ | ||
950 | AT_WRITE_REG(hw, REG_NTPD_HEAD_ADDR_LO, | ||
951 | (u32)(tpd_ring[atl1c_trans_normal].dma & | ||
952 | AT_DMA_LO_ADDR_MASK)); | ||
953 | AT_WRITE_REG(hw, REG_HTPD_HEAD_ADDR_LO, | ||
954 | (u32)(tpd_ring[atl1c_trans_high].dma & | ||
955 | AT_DMA_LO_ADDR_MASK)); | ||
956 | AT_WRITE_REG(hw, REG_TPD_RING_SIZE, | ||
957 | (u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK)); | ||
958 | |||
959 | |||
960 | /* RFD */ | ||
961 | AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI, | ||
962 | (u32)((rfd_ring[0].dma & AT_DMA_HI_ADDR_MASK) >> 32)); | ||
963 | for (i = 0; i < adapter->num_rx_queues; i++) | ||
964 | AT_WRITE_REG(hw, atl1c_rfd_addr_lo_regs[i], | ||
965 | (u32)(rfd_ring[i].dma & AT_DMA_LO_ADDR_MASK)); | ||
966 | |||
967 | AT_WRITE_REG(hw, REG_RFD_RING_SIZE, | ||
968 | rfd_ring[0].count & RFD_RING_SIZE_MASK); | ||
969 | AT_WRITE_REG(hw, REG_RX_BUF_SIZE, | ||
970 | adapter->rx_buffer_len & RX_BUF_SIZE_MASK); | ||
971 | |||
972 | /* RRD */ | ||
973 | for (i = 0; i < adapter->num_rx_queues; i++) | ||
974 | AT_WRITE_REG(hw, atl1c_rrd_addr_lo_regs[i], | ||
975 | (u32)(rrd_ring[i].dma & AT_DMA_LO_ADDR_MASK)); | ||
976 | AT_WRITE_REG(hw, REG_RRD_RING_SIZE, | ||
977 | (rrd_ring[0].count & RRD_RING_SIZE_MASK)); | ||
978 | |||
979 | /* CMB */ | ||
980 | AT_WRITE_REG(hw, REG_CMB_BASE_ADDR_LO, cmb->dma & AT_DMA_LO_ADDR_MASK); | ||
981 | |||
982 | /* SMB */ | ||
983 | AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_HI, | ||
984 | (u32)((smb->dma & AT_DMA_HI_ADDR_MASK) >> 32)); | ||
985 | AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_LO, | ||
986 | (u32)(smb->dma & AT_DMA_LO_ADDR_MASK)); | ||
987 | /* Load all of base address above */ | ||
988 | AT_WRITE_REG(hw, REG_LOAD_PTR, 1); | ||
989 | } | ||
990 | |||
991 | static void atl1c_configure_tx(struct atl1c_adapter *adapter) | ||
992 | { | ||
993 | struct atl1c_hw *hw = &adapter->hw; | ||
994 | u32 dev_ctrl_data; | ||
995 | u32 max_pay_load; | ||
996 | u16 tx_offload_thresh; | ||
997 | u32 txq_ctrl_data; | ||
998 | u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */ | ||
999 | |||
1000 | extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN; | ||
1001 | tx_offload_thresh = MAX_TX_OFFLOAD_THRESH; | ||
1002 | AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH, | ||
1003 | (tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK); | ||
1004 | AT_READ_REG(hw, REG_DEVICE_CTRL, &dev_ctrl_data); | ||
1005 | max_pay_load = (dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT) & | ||
1006 | DEVICE_CTRL_MAX_PAYLOAD_MASK; | ||
1007 | hw->dmaw_block = min(max_pay_load, hw->dmaw_block); | ||
1008 | max_pay_load = (dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT) & | ||
1009 | DEVICE_CTRL_MAX_RREQ_SZ_MASK; | ||
1010 | hw->dmar_block = min(max_pay_load, hw->dmar_block); | ||
1011 | |||
1012 | txq_ctrl_data = (hw->tpd_burst & TXQ_NUM_TPD_BURST_MASK) << | ||
1013 | TXQ_NUM_TPD_BURST_SHIFT; | ||
1014 | if (hw->ctrl_flags & ATL1C_TXQ_MODE_ENHANCE) | ||
1015 | txq_ctrl_data |= TXQ_CTRL_ENH_MODE; | ||
1016 | txq_ctrl_data |= (atl1c_pay_load_size[hw->dmar_block] & | ||
1017 | TXQ_TXF_BURST_NUM_MASK) << TXQ_TXF_BURST_NUM_SHIFT; | ||
1018 | |||
1019 | AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data); | ||
1020 | } | ||
1021 | |||
1022 | static void atl1c_configure_rx(struct atl1c_adapter *adapter) | ||
1023 | { | ||
1024 | struct atl1c_hw *hw = &adapter->hw; | ||
1025 | u32 rxq_ctrl_data; | ||
1026 | |||
1027 | rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) << | ||
1028 | RXQ_RFD_BURST_NUM_SHIFT; | ||
1029 | |||
1030 | if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM) | ||
1031 | rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN; | ||
1032 | if (hw->rss_type == atl1c_rss_ipv4) | ||
1033 | rxq_ctrl_data |= RSS_HASH_IPV4; | ||
1034 | if (hw->rss_type == atl1c_rss_ipv4_tcp) | ||
1035 | rxq_ctrl_data |= RSS_HASH_IPV4_TCP; | ||
1036 | if (hw->rss_type == atl1c_rss_ipv6) | ||
1037 | rxq_ctrl_data |= RSS_HASH_IPV6; | ||
1038 | if (hw->rss_type == atl1c_rss_ipv6_tcp) | ||
1039 | rxq_ctrl_data |= RSS_HASH_IPV6_TCP; | ||
1040 | if (hw->rss_type != atl1c_rss_disable) | ||
1041 | rxq_ctrl_data |= RRS_HASH_CTRL_EN; | ||
1042 | |||
1043 | rxq_ctrl_data |= (hw->rss_mode & RSS_MODE_MASK) << | ||
1044 | RSS_MODE_SHIFT; | ||
1045 | rxq_ctrl_data |= (hw->rss_hash_bits & RSS_HASH_BITS_MASK) << | ||
1046 | RSS_HASH_BITS_SHIFT; | ||
1047 | if (hw->ctrl_flags & ATL1C_ASPM_CTRL_MON) | ||
1048 | rxq_ctrl_data |= (ASPM_THRUPUT_LIMIT_100M & | ||
1049 | ASPM_THRUPUT_LIMIT_MASK) << ASPM_THRUPUT_LIMIT_SHIFT; | ||
1050 | |||
1051 | AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data); | ||
1052 | } | ||
1053 | |||
1054 | static void atl1c_configure_rss(struct atl1c_adapter *adapter) | ||
1055 | { | ||
1056 | struct atl1c_hw *hw = &adapter->hw; | ||
1057 | |||
1058 | AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab); | ||
1059 | AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu); | ||
1060 | } | ||
1061 | |||
1062 | static void atl1c_configure_dma(struct atl1c_adapter *adapter) | ||
1063 | { | ||
1064 | struct atl1c_hw *hw = &adapter->hw; | ||
1065 | u32 dma_ctrl_data; | ||
1066 | |||
1067 | dma_ctrl_data = DMA_CTRL_DMAR_REQ_PRI; | ||
1068 | if (hw->ctrl_flags & ATL1C_CMB_ENABLE) | ||
1069 | dma_ctrl_data |= DMA_CTRL_CMB_EN; | ||
1070 | if (hw->ctrl_flags & ATL1C_SMB_ENABLE) | ||
1071 | dma_ctrl_data |= DMA_CTRL_SMB_EN; | ||
1072 | else | ||
1073 | dma_ctrl_data |= MAC_CTRL_SMB_DIS; | ||
1074 | |||
1075 | switch (hw->dma_order) { | ||
1076 | case atl1c_dma_ord_in: | ||
1077 | dma_ctrl_data |= DMA_CTRL_DMAR_IN_ORDER; | ||
1078 | break; | ||
1079 | case atl1c_dma_ord_enh: | ||
1080 | dma_ctrl_data |= DMA_CTRL_DMAR_ENH_ORDER; | ||
1081 | break; | ||
1082 | case atl1c_dma_ord_out: | ||
1083 | dma_ctrl_data |= DMA_CTRL_DMAR_OUT_ORDER; | ||
1084 | break; | ||
1085 | default: | ||
1086 | break; | ||
1087 | } | ||
1088 | |||
1089 | dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK) | ||
1090 | << DMA_CTRL_DMAR_BURST_LEN_SHIFT; | ||
1091 | dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK) | ||
1092 | << DMA_CTRL_DMAW_BURST_LEN_SHIFT; | ||
1093 | dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK) | ||
1094 | << DMA_CTRL_DMAR_DLY_CNT_SHIFT; | ||
1095 | dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK) | ||
1096 | << DMA_CTRL_DMAW_DLY_CNT_SHIFT; | ||
1097 | |||
1098 | AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data); | ||
1099 | } | ||
1100 | |||
1101 | /* | ||
1102 | * Stop the mac, transmit and receive units | ||
1103 | * hw - Struct containing variables accessed by shared code | ||
1104 | * return : 0 or idle status (if error) | ||
1105 | */ | ||
1106 | static int atl1c_stop_mac(struct atl1c_hw *hw) | ||
1107 | { | ||
1108 | u32 data; | ||
1109 | int timeout; | ||
1110 | |||
1111 | AT_READ_REG(hw, REG_RXQ_CTRL, &data); | ||
1112 | data &= ~(RXQ1_CTRL_EN | RXQ2_CTRL_EN | | ||
1113 | RXQ3_CTRL_EN | RXQ_CTRL_EN); | ||
1114 | AT_WRITE_REG(hw, REG_RXQ_CTRL, data); | ||
1115 | |||
1116 | AT_READ_REG(hw, REG_TXQ_CTRL, &data); | ||
1117 | data &= ~TXQ_CTRL_EN; | ||
1118 | AT_WRITE_REG(hw, REG_TWSI_CTRL, data); | ||
1119 | |||
1120 | for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) { | ||
1121 | AT_READ_REG(hw, REG_IDLE_STATUS, &data); | ||
1122 | if ((data & (IDLE_STATUS_RXQ_NO_IDLE | | ||
1123 | IDLE_STATUS_TXQ_NO_IDLE)) == 0) | ||
1124 | break; | ||
1125 | msleep(1); | ||
1126 | } | ||
1127 | |||
1128 | AT_READ_REG(hw, REG_MAC_CTRL, &data); | ||
1129 | data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN); | ||
1130 | AT_WRITE_REG(hw, REG_MAC_CTRL, data); | ||
1131 | |||
1132 | for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) { | ||
1133 | AT_READ_REG(hw, REG_IDLE_STATUS, &data); | ||
1134 | if ((data & IDLE_STATUS_MASK) == 0) | ||
1135 | return 0; | ||
1136 | msleep(1); | ||
1137 | } | ||
1138 | return data; | ||
1139 | } | ||
1140 | |||
1141 | static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw) | ||
1142 | { | ||
1143 | u32 data; | ||
1144 | |||
1145 | AT_READ_REG(hw, REG_RXQ_CTRL, &data); | ||
1146 | switch (hw->adapter->num_rx_queues) { | ||
1147 | case 4: | ||
1148 | data |= (RXQ3_CTRL_EN | RXQ2_CTRL_EN | RXQ1_CTRL_EN); | ||
1149 | break; | ||
1150 | case 3: | ||
1151 | data |= (RXQ2_CTRL_EN | RXQ1_CTRL_EN); | ||
1152 | break; | ||
1153 | case 2: | ||
1154 | data |= RXQ1_CTRL_EN; | ||
1155 | break; | ||
1156 | default: | ||
1157 | break; | ||
1158 | } | ||
1159 | data |= RXQ_CTRL_EN; | ||
1160 | AT_WRITE_REG(hw, REG_RXQ_CTRL, data); | ||
1161 | } | ||
1162 | |||
1163 | static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw) | ||
1164 | { | ||
1165 | u32 data; | ||
1166 | |||
1167 | AT_READ_REG(hw, REG_TXQ_CTRL, &data); | ||
1168 | data |= TXQ_CTRL_EN; | ||
1169 | AT_WRITE_REG(hw, REG_TXQ_CTRL, data); | ||
1170 | } | ||
1171 | |||
1172 | /* | ||
1173 | * Reset the transmit and receive units; mask and clear all interrupts. | ||
1174 | * hw - Struct containing variables accessed by shared code | ||
1175 | * return : 0 or idle status (if error) | ||
1176 | */ | ||
1177 | static int atl1c_reset_mac(struct atl1c_hw *hw) | ||
1178 | { | ||
1179 | struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter; | ||
1180 | struct pci_dev *pdev = adapter->pdev; | ||
1181 | u32 idle_status_data = 0; | ||
1182 | int timeout = 0; | ||
1183 | int ret; | ||
1184 | |||
1185 | AT_WRITE_REG(hw, REG_IMR, 0); | ||
1186 | AT_WRITE_REG(hw, REG_ISR, ISR_DIS_INT); | ||
1187 | |||
1188 | ret = atl1c_stop_mac(hw); | ||
1189 | if (ret) | ||
1190 | return ret; | ||
1191 | /* | ||
1192 | * Issue Soft Reset to the MAC. This will reset the chip's | ||
1193 | * transmit, receive, DMA. It will not effect | ||
1194 | * the current PCI configuration. The global reset bit is self- | ||
1195 | * clearing, and should clear within a microsecond. | ||
1196 | */ | ||
1197 | AT_WRITE_REGW(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); | ||
1198 | AT_WRITE_FLUSH(hw); | ||
1199 | msleep(10); | ||
1200 | /* Wait at least 10ms for All module to be Idle */ | ||
1201 | for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) { | ||
1202 | AT_READ_REG(hw, REG_IDLE_STATUS, &idle_status_data); | ||
1203 | if ((idle_status_data & IDLE_STATUS_MASK) == 0) | ||
1204 | break; | ||
1205 | msleep(1); | ||
1206 | } | ||
1207 | if (timeout >= AT_HW_MAX_IDLE_DELAY) { | ||
1208 | dev_err(&pdev->dev, | ||
1209 | "MAC state machine cann't be idle since" | ||
1210 | " disabled for 10ms second\n"); | ||
1211 | return -1; | ||
1212 | } | ||
1213 | return 0; | ||
1214 | } | ||
1215 | |||
1216 | static void atl1c_disable_l0s_l1(struct atl1c_hw *hw) | ||
1217 | { | ||
1218 | u32 pm_ctrl_data; | ||
1219 | |||
1220 | AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data); | ||
1221 | pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK << | ||
1222 | PM_CTRL_L1_ENTRY_TIMER_SHIFT); | ||
1223 | pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1; | ||
1224 | pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN; | ||
1225 | pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN; | ||
1226 | pm_ctrl_data &= ~PM_CTRL_MAC_ASPM_CHK; | ||
1227 | pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1; | ||
1228 | |||
1229 | pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN; | ||
1230 | pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN; | ||
1231 | pm_ctrl_data |= PM_CTRL_SERDES_L1_EN; | ||
1232 | AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data); | ||
1233 | } | ||
1234 | |||
1235 | /* | ||
1236 | * Set ASPM state. | ||
1237 | * Enable/disable L0s/L1 depend on link state. | ||
1238 | */ | ||
1239 | static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup) | ||
1240 | { | ||
1241 | u32 pm_ctrl_data; | ||
1242 | |||
1243 | AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data); | ||
1244 | |||
1245 | pm_ctrl_data &= PM_CTRL_SERDES_PD_EX_L1; | ||
1246 | pm_ctrl_data |= ~PM_CTRL_SERDES_BUDS_RX_L1_EN; | ||
1247 | pm_ctrl_data |= ~PM_CTRL_SERDES_L1_EN; | ||
1248 | pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK << | ||
1249 | PM_CTRL_L1_ENTRY_TIMER_SHIFT); | ||
1250 | |||
1251 | pm_ctrl_data |= PM_CTRL_MAC_ASPM_CHK; | ||
1252 | |||
1253 | if (linkup) { | ||
1254 | pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN; | ||
1255 | pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1; | ||
1256 | |||
1257 | if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT) { | ||
1258 | pm_ctrl_data |= AT_ASPM_L1_TIMER << | ||
1259 | PM_CTRL_L1_ENTRY_TIMER_SHIFT; | ||
1260 | pm_ctrl_data |= PM_CTRL_ASPM_L1_EN; | ||
1261 | } else | ||
1262 | pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN; | ||
1263 | |||
1264 | if (hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT) | ||
1265 | pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN; | ||
1266 | else | ||
1267 | pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN; | ||
1268 | |||
1269 | } else { | ||
1270 | pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN; | ||
1271 | pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN; | ||
1272 | |||
1273 | pm_ctrl_data |= PM_CTRL_CLK_SWH_L1; | ||
1274 | |||
1275 | if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT) | ||
1276 | pm_ctrl_data |= PM_CTRL_ASPM_L1_EN; | ||
1277 | else | ||
1278 | pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN; | ||
1279 | } | ||
1280 | |||
1281 | AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data); | ||
1282 | } | ||
1283 | |||
1284 | static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter) | ||
1285 | { | ||
1286 | struct atl1c_hw *hw = &adapter->hw; | ||
1287 | struct net_device *netdev = adapter->netdev; | ||
1288 | u32 mac_ctrl_data; | ||
1289 | |||
1290 | mac_ctrl_data = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN; | ||
1291 | mac_ctrl_data |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); | ||
1292 | |||
1293 | if (adapter->link_duplex == FULL_DUPLEX) { | ||
1294 | hw->mac_duplex = true; | ||
1295 | mac_ctrl_data |= MAC_CTRL_DUPLX; | ||
1296 | } | ||
1297 | |||
1298 | if (adapter->link_speed == SPEED_1000) | ||
1299 | hw->mac_speed = atl1c_mac_speed_1000; | ||
1300 | else | ||
1301 | hw->mac_speed = atl1c_mac_speed_10_100; | ||
1302 | |||
1303 | mac_ctrl_data |= (hw->mac_speed & MAC_CTRL_SPEED_MASK) << | ||
1304 | MAC_CTRL_SPEED_SHIFT; | ||
1305 | |||
1306 | mac_ctrl_data |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); | ||
1307 | mac_ctrl_data |= ((hw->preamble_len & MAC_CTRL_PRMLEN_MASK) << | ||
1308 | MAC_CTRL_PRMLEN_SHIFT); | ||
1309 | |||
1310 | if (adapter->vlgrp) | ||
1311 | mac_ctrl_data |= MAC_CTRL_RMV_VLAN; | ||
1312 | |||
1313 | mac_ctrl_data |= MAC_CTRL_BC_EN; | ||
1314 | if (netdev->flags & IFF_PROMISC) | ||
1315 | mac_ctrl_data |= MAC_CTRL_PROMIS_EN; | ||
1316 | if (netdev->flags & IFF_ALLMULTI) | ||
1317 | mac_ctrl_data |= MAC_CTRL_MC_ALL_EN; | ||
1318 | |||
1319 | mac_ctrl_data |= MAC_CTRL_SINGLE_PAUSE_EN; | ||
1320 | AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data); | ||
1321 | } | ||
1322 | |||
1323 | /* | ||
1324 | * atl1c_configure - Configure Transmit&Receive Unit after Reset | ||
1325 | * @adapter: board private structure | ||
1326 | * | ||
1327 | * Configure the Tx /Rx unit of the MAC after a reset. | ||
1328 | */ | ||
1329 | static int atl1c_configure(struct atl1c_adapter *adapter) | ||
1330 | { | ||
1331 | struct atl1c_hw *hw = &adapter->hw; | ||
1332 | u32 master_ctrl_data = 0; | ||
1333 | u32 intr_modrt_data; | ||
1334 | |||
1335 | /* clear interrupt status */ | ||
1336 | AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF); | ||
1337 | /* Clear any WOL status */ | ||
1338 | AT_WRITE_REG(hw, REG_WOL_CTRL, 0); | ||
1339 | /* set Interrupt Clear Timer | ||
1340 | * HW will enable self to assert interrupt event to system after | ||
1341 | * waiting x-time for software to notify it accept interrupt. | ||
1342 | */ | ||
1343 | AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER, | ||
1344 | hw->ict & INT_RETRIG_TIMER_MASK); | ||
1345 | |||
1346 | atl1c_configure_des_ring(adapter); | ||
1347 | |||
1348 | if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) { | ||
1349 | intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) << | ||
1350 | IRQ_MODRT_TX_TIMER_SHIFT; | ||
1351 | intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) << | ||
1352 | IRQ_MODRT_RX_TIMER_SHIFT; | ||
1353 | AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data); | ||
1354 | master_ctrl_data |= | ||
1355 | MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN; | ||
1356 | } | ||
1357 | |||
1358 | if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ) | ||
1359 | master_ctrl_data |= MASTER_CTRL_INT_RDCLR; | ||
1360 | |||
1361 | AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data); | ||
1362 | |||
1363 | if (hw->ctrl_flags & ATL1C_CMB_ENABLE) { | ||
1364 | AT_WRITE_REG(hw, REG_CMB_TPD_THRESH, | ||
1365 | hw->cmb_tpd & CMB_TPD_THRESH_MASK); | ||
1366 | AT_WRITE_REG(hw, REG_CMB_TX_TIMER, | ||
1367 | hw->cmb_tx_timer & CMB_TX_TIMER_MASK); | ||
1368 | } | ||
1369 | |||
1370 | if (hw->ctrl_flags & ATL1C_SMB_ENABLE) | ||
1371 | AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, | ||
1372 | hw->smb_timer & SMB_STAT_TIMER_MASK); | ||
1373 | /* set MTU */ | ||
1374 | AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN + | ||
1375 | VLAN_HLEN + ETH_FCS_LEN); | ||
1376 | /* HDS, disable */ | ||
1377 | AT_WRITE_REG(hw, REG_HDS_CTRL, 0); | ||
1378 | |||
1379 | atl1c_configure_tx(adapter); | ||
1380 | atl1c_configure_rx(adapter); | ||
1381 | atl1c_configure_rss(adapter); | ||
1382 | atl1c_configure_dma(adapter); | ||
1383 | |||
1384 | return 0; | ||
1385 | } | ||
1386 | |||
1387 | static void atl1c_update_hw_stats(struct atl1c_adapter *adapter) | ||
1388 | { | ||
1389 | u16 hw_reg_addr = 0; | ||
1390 | unsigned long *stats_item = NULL; | ||
1391 | u32 data; | ||
1392 | |||
1393 | /* update rx status */ | ||
1394 | hw_reg_addr = REG_MAC_RX_STATUS_BIN; | ||
1395 | stats_item = &adapter->hw_stats.rx_ok; | ||
1396 | while (hw_reg_addr <= REG_MAC_RX_STATUS_END) { | ||
1397 | AT_READ_REG(&adapter->hw, hw_reg_addr, &data); | ||
1398 | *stats_item += data; | ||
1399 | stats_item++; | ||
1400 | hw_reg_addr += 4; | ||
1401 | } | ||
1402 | /* update tx status */ | ||
1403 | hw_reg_addr = REG_MAC_TX_STATUS_BIN; | ||
1404 | stats_item = &adapter->hw_stats.tx_ok; | ||
1405 | while (hw_reg_addr <= REG_MAC_TX_STATUS_END) { | ||
1406 | AT_READ_REG(&adapter->hw, hw_reg_addr, &data); | ||
1407 | *stats_item += data; | ||
1408 | stats_item++; | ||
1409 | hw_reg_addr += 4; | ||
1410 | } | ||
1411 | } | ||
1412 | |||
1413 | /* | ||
1414 | * atl1c_get_stats - Get System Network Statistics | ||
1415 | * @netdev: network interface device structure | ||
1416 | * | ||
1417 | * Returns the address of the device statistics structure. | ||
1418 | * The statistics are actually updated from the timer callback. | ||
1419 | */ | ||
1420 | static struct net_device_stats *atl1c_get_stats(struct net_device *netdev) | ||
1421 | { | ||
1422 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
1423 | struct atl1c_hw_stats *hw_stats = &adapter->hw_stats; | ||
1424 | struct net_device_stats *net_stats = &adapter->net_stats; | ||
1425 | |||
1426 | atl1c_update_hw_stats(adapter); | ||
1427 | net_stats->rx_packets = hw_stats->rx_ok; | ||
1428 | net_stats->tx_packets = hw_stats->tx_ok; | ||
1429 | net_stats->rx_bytes = hw_stats->rx_byte_cnt; | ||
1430 | net_stats->tx_bytes = hw_stats->tx_byte_cnt; | ||
1431 | net_stats->multicast = hw_stats->rx_mcast; | ||
1432 | net_stats->collisions = hw_stats->tx_1_col + | ||
1433 | hw_stats->tx_2_col * 2 + | ||
1434 | hw_stats->tx_late_col + hw_stats->tx_abort_col; | ||
1435 | net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err + | ||
1436 | hw_stats->rx_len_err + hw_stats->rx_sz_ov + | ||
1437 | hw_stats->rx_rrd_ov + hw_stats->rx_align_err; | ||
1438 | net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov; | ||
1439 | net_stats->rx_length_errors = hw_stats->rx_len_err; | ||
1440 | net_stats->rx_crc_errors = hw_stats->rx_fcs_err; | ||
1441 | net_stats->rx_frame_errors = hw_stats->rx_align_err; | ||
1442 | net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov; | ||
1443 | |||
1444 | net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov; | ||
1445 | |||
1446 | net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col + | ||
1447 | hw_stats->tx_underrun + hw_stats->tx_trunc; | ||
1448 | net_stats->tx_fifo_errors = hw_stats->tx_underrun; | ||
1449 | net_stats->tx_aborted_errors = hw_stats->tx_abort_col; | ||
1450 | net_stats->tx_window_errors = hw_stats->tx_late_col; | ||
1451 | |||
1452 | return &adapter->net_stats; | ||
1453 | } | ||
1454 | |||
1455 | static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter) | ||
1456 | { | ||
1457 | u16 phy_data; | ||
1458 | |||
1459 | spin_lock(&adapter->mdio_lock); | ||
1460 | atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data); | ||
1461 | spin_unlock(&adapter->mdio_lock); | ||
1462 | } | ||
1463 | |||
1464 | static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter, | ||
1465 | enum atl1c_trans_queue type) | ||
1466 | { | ||
1467 | struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *) | ||
1468 | &adapter->tpd_ring[type]; | ||
1469 | struct atl1c_buffer *buffer_info; | ||
1470 | u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean); | ||
1471 | u16 hw_next_to_clean; | ||
1472 | u16 shift; | ||
1473 | u32 data; | ||
1474 | |||
1475 | if (type == atl1c_trans_high) | ||
1476 | shift = MB_HTPD_CONS_IDX_SHIFT; | ||
1477 | else | ||
1478 | shift = MB_NTPD_CONS_IDX_SHIFT; | ||
1479 | |||
1480 | AT_READ_REG(&adapter->hw, REG_MB_PRIO_CONS_IDX, &data); | ||
1481 | hw_next_to_clean = (data >> shift) & MB_PRIO_PROD_IDX_MASK; | ||
1482 | |||
1483 | while (next_to_clean != hw_next_to_clean) { | ||
1484 | buffer_info = &tpd_ring->buffer_info[next_to_clean]; | ||
1485 | if (buffer_info->state == ATL1_BUFFER_BUSY) { | ||
1486 | pci_unmap_page(adapter->pdev, buffer_info->dma, | ||
1487 | buffer_info->length, PCI_DMA_TODEVICE); | ||
1488 | buffer_info->dma = 0; | ||
1489 | if (buffer_info->skb) { | ||
1490 | dev_kfree_skb_irq(buffer_info->skb); | ||
1491 | buffer_info->skb = NULL; | ||
1492 | } | ||
1493 | buffer_info->state = ATL1_BUFFER_FREE; | ||
1494 | } | ||
1495 | if (++next_to_clean == tpd_ring->count) | ||
1496 | next_to_clean = 0; | ||
1497 | atomic_set(&tpd_ring->next_to_clean, next_to_clean); | ||
1498 | } | ||
1499 | |||
1500 | if (netif_queue_stopped(adapter->netdev) && | ||
1501 | netif_carrier_ok(adapter->netdev)) { | ||
1502 | netif_wake_queue(adapter->netdev); | ||
1503 | } | ||
1504 | |||
1505 | return true; | ||
1506 | } | ||
1507 | |||
1508 | /* | ||
1509 | * atl1c_intr - Interrupt Handler | ||
1510 | * @irq: interrupt number | ||
1511 | * @data: pointer to a network interface device structure | ||
1512 | * @pt_regs: CPU registers structure | ||
1513 | */ | ||
1514 | static irqreturn_t atl1c_intr(int irq, void *data) | ||
1515 | { | ||
1516 | struct net_device *netdev = data; | ||
1517 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
1518 | struct pci_dev *pdev = adapter->pdev; | ||
1519 | struct atl1c_hw *hw = &adapter->hw; | ||
1520 | int max_ints = AT_MAX_INT_WORK; | ||
1521 | int handled = IRQ_NONE; | ||
1522 | u32 status; | ||
1523 | u32 reg_data; | ||
1524 | |||
1525 | do { | ||
1526 | AT_READ_REG(hw, REG_ISR, ®_data); | ||
1527 | status = reg_data & hw->intr_mask; | ||
1528 | |||
1529 | if (status == 0 || (status & ISR_DIS_INT) != 0) { | ||
1530 | if (max_ints != AT_MAX_INT_WORK) | ||
1531 | handled = IRQ_HANDLED; | ||
1532 | break; | ||
1533 | } | ||
1534 | /* link event */ | ||
1535 | if (status & ISR_GPHY) | ||
1536 | atl1c_clear_phy_int(adapter); | ||
1537 | /* Ack ISR */ | ||
1538 | AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); | ||
1539 | if (status & ISR_RX_PKT) { | ||
1540 | if (likely(napi_schedule_prep(&adapter->napi))) { | ||
1541 | hw->intr_mask &= ~ISR_RX_PKT; | ||
1542 | AT_WRITE_REG(hw, REG_IMR, hw->intr_mask); | ||
1543 | __napi_schedule(&adapter->napi); | ||
1544 | } | ||
1545 | } | ||
1546 | if (status & ISR_TX_PKT) | ||
1547 | atl1c_clean_tx_irq(adapter, atl1c_trans_normal); | ||
1548 | |||
1549 | handled = IRQ_HANDLED; | ||
1550 | /* check if PCIE PHY Link down */ | ||
1551 | if (status & ISR_ERROR) { | ||
1552 | if (netif_msg_hw(adapter)) | ||
1553 | dev_err(&pdev->dev, | ||
1554 | "atl1c hardware error (status = 0x%x)\n", | ||
1555 | status & ISR_ERROR); | ||
1556 | /* reset MAC */ | ||
1557 | hw->intr_mask &= ~ISR_ERROR; | ||
1558 | AT_WRITE_REG(hw, REG_IMR, hw->intr_mask); | ||
1559 | schedule_work(&adapter->reset_task); | ||
1560 | break; | ||
1561 | } | ||
1562 | |||
1563 | if (status & ISR_OVER) | ||
1564 | if (netif_msg_intr(adapter)) | ||
1565 | dev_warn(&pdev->dev, | ||
1566 | "TX/RX over flow (status = 0x%x)\n", | ||
1567 | status & ISR_OVER); | ||
1568 | |||
1569 | /* link event */ | ||
1570 | if (status & (ISR_GPHY | ISR_MANUAL)) { | ||
1571 | adapter->net_stats.tx_carrier_errors++; | ||
1572 | atl1c_link_chg_event(adapter); | ||
1573 | break; | ||
1574 | } | ||
1575 | |||
1576 | } while (--max_ints > 0); | ||
1577 | /* re-enable Interrupt*/ | ||
1578 | AT_WRITE_REG(&adapter->hw, REG_ISR, 0); | ||
1579 | return handled; | ||
1580 | } | ||
1581 | |||
1582 | static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter, | ||
1583 | struct sk_buff *skb, struct atl1c_recv_ret_status *prrs) | ||
1584 | { | ||
1585 | /* | ||
1586 | * The pid field in RRS in not correct sometimes, so we | ||
1587 | * cannot figure out if the packet is fragmented or not, | ||
1588 | * so we tell the KERNEL CHECKSUM_NONE | ||
1589 | */ | ||
1590 | skb->ip_summed = CHECKSUM_NONE; | ||
1591 | } | ||
1592 | |||
1593 | static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter, const int ringid) | ||
1594 | { | ||
1595 | struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring[ringid]; | ||
1596 | struct pci_dev *pdev = adapter->pdev; | ||
1597 | struct atl1c_buffer *buffer_info, *next_info; | ||
1598 | struct sk_buff *skb; | ||
1599 | void *vir_addr = NULL; | ||
1600 | u16 num_alloc = 0; | ||
1601 | u16 rfd_next_to_use, next_next; | ||
1602 | struct atl1c_rx_free_desc *rfd_desc; | ||
1603 | |||
1604 | next_next = rfd_next_to_use = rfd_ring->next_to_use; | ||
1605 | if (++next_next == rfd_ring->count) | ||
1606 | next_next = 0; | ||
1607 | buffer_info = &rfd_ring->buffer_info[rfd_next_to_use]; | ||
1608 | next_info = &rfd_ring->buffer_info[next_next]; | ||
1609 | |||
1610 | while (next_info->state == ATL1_BUFFER_FREE) { | ||
1611 | rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use); | ||
1612 | |||
1613 | skb = dev_alloc_skb(adapter->rx_buffer_len); | ||
1614 | if (unlikely(!skb)) { | ||
1615 | if (netif_msg_rx_err(adapter)) | ||
1616 | dev_warn(&pdev->dev, "alloc rx buffer failed\n"); | ||
1617 | break; | ||
1618 | } | ||
1619 | |||
1620 | /* | ||
1621 | * Make buffer alignment 2 beyond a 16 byte boundary | ||
1622 | * this will result in a 16 byte aligned IP header after | ||
1623 | * the 14 byte MAC header is removed | ||
1624 | */ | ||
1625 | vir_addr = skb->data; | ||
1626 | buffer_info->state = ATL1_BUFFER_BUSY; | ||
1627 | buffer_info->skb = skb; | ||
1628 | buffer_info->length = adapter->rx_buffer_len; | ||
1629 | buffer_info->dma = pci_map_single(pdev, vir_addr, | ||
1630 | buffer_info->length, | ||
1631 | PCI_DMA_FROMDEVICE); | ||
1632 | rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma); | ||
1633 | rfd_next_to_use = next_next; | ||
1634 | if (++next_next == rfd_ring->count) | ||
1635 | next_next = 0; | ||
1636 | buffer_info = &rfd_ring->buffer_info[rfd_next_to_use]; | ||
1637 | next_info = &rfd_ring->buffer_info[next_next]; | ||
1638 | num_alloc++; | ||
1639 | } | ||
1640 | |||
1641 | if (num_alloc) { | ||
1642 | /* TODO: update mailbox here */ | ||
1643 | wmb(); | ||
1644 | rfd_ring->next_to_use = rfd_next_to_use; | ||
1645 | AT_WRITE_REG(&adapter->hw, atl1c_rfd_prod_idx_regs[ringid], | ||
1646 | rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK); | ||
1647 | } | ||
1648 | |||
1649 | return num_alloc; | ||
1650 | } | ||
1651 | |||
1652 | static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_ring, | ||
1653 | struct atl1c_recv_ret_status *rrs, u16 num) | ||
1654 | { | ||
1655 | u16 i; | ||
1656 | /* the relationship between rrd and rfd is one map one */ | ||
1657 | for (i = 0; i < num; i++, rrs = ATL1C_RRD_DESC(rrd_ring, | ||
1658 | rrd_ring->next_to_clean)) { | ||
1659 | rrs->word3 &= ~RRS_RXD_UPDATED; | ||
1660 | if (++rrd_ring->next_to_clean == rrd_ring->count) | ||
1661 | rrd_ring->next_to_clean = 0; | ||
1662 | } | ||
1663 | } | ||
1664 | |||
1665 | static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring, | ||
1666 | struct atl1c_recv_ret_status *rrs, u16 num) | ||
1667 | { | ||
1668 | u16 i; | ||
1669 | u16 rfd_index; | ||
1670 | struct atl1c_buffer *buffer_info = rfd_ring->buffer_info; | ||
1671 | |||
1672 | rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) & | ||
1673 | RRS_RX_RFD_INDEX_MASK; | ||
1674 | for (i = 0; i < num; i++) { | ||
1675 | buffer_info[rfd_index].skb = NULL; | ||
1676 | buffer_info[rfd_index].state = ATL1_BUFFER_FREE; | ||
1677 | if (++rfd_index == rfd_ring->count) | ||
1678 | rfd_index = 0; | ||
1679 | } | ||
1680 | rfd_ring->next_to_clean = rfd_index; | ||
1681 | } | ||
1682 | |||
1683 | static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que, | ||
1684 | int *work_done, int work_to_do) | ||
1685 | { | ||
1686 | u16 rfd_num, rfd_index; | ||
1687 | u16 count = 0; | ||
1688 | u16 length; | ||
1689 | struct pci_dev *pdev = adapter->pdev; | ||
1690 | struct net_device *netdev = adapter->netdev; | ||
1691 | struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring[que]; | ||
1692 | struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring[que]; | ||
1693 | struct sk_buff *skb; | ||
1694 | struct atl1c_recv_ret_status *rrs; | ||
1695 | struct atl1c_buffer *buffer_info; | ||
1696 | |||
1697 | while (1) { | ||
1698 | if (*work_done >= work_to_do) | ||
1699 | break; | ||
1700 | rrs = ATL1C_RRD_DESC(rrd_ring, rrd_ring->next_to_clean); | ||
1701 | if (likely(RRS_RXD_IS_VALID(rrs->word3))) { | ||
1702 | rfd_num = (rrs->word0 >> RRS_RX_RFD_CNT_SHIFT) & | ||
1703 | RRS_RX_RFD_CNT_MASK; | ||
1704 | if (unlikely(rfd_num) != 1) | ||
1705 | /* TODO support mul rfd*/ | ||
1706 | if (netif_msg_rx_err(adapter)) | ||
1707 | dev_warn(&pdev->dev, | ||
1708 | "Multi rfd not support yet!\n"); | ||
1709 | goto rrs_checked; | ||
1710 | } else { | ||
1711 | break; | ||
1712 | } | ||
1713 | rrs_checked: | ||
1714 | atl1c_clean_rrd(rrd_ring, rrs, rfd_num); | ||
1715 | if (rrs->word3 & (RRS_RX_ERR_SUM | RRS_802_3_LEN_ERR)) { | ||
1716 | atl1c_clean_rfd(rfd_ring, rrs, rfd_num); | ||
1717 | if (netif_msg_rx_err(adapter)) | ||
1718 | dev_warn(&pdev->dev, | ||
1719 | "wrong packet! rrs word3 is %x\n", | ||
1720 | rrs->word3); | ||
1721 | continue; | ||
1722 | } | ||
1723 | |||
1724 | length = le16_to_cpu((rrs->word3 >> RRS_PKT_SIZE_SHIFT) & | ||
1725 | RRS_PKT_SIZE_MASK); | ||
1726 | /* Good Receive */ | ||
1727 | if (likely(rfd_num == 1)) { | ||
1728 | rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) & | ||
1729 | RRS_RX_RFD_INDEX_MASK; | ||
1730 | buffer_info = &rfd_ring->buffer_info[rfd_index]; | ||
1731 | pci_unmap_single(pdev, buffer_info->dma, | ||
1732 | buffer_info->length, PCI_DMA_FROMDEVICE); | ||
1733 | skb = buffer_info->skb; | ||
1734 | } else { | ||
1735 | /* TODO */ | ||
1736 | if (netif_msg_rx_err(adapter)) | ||
1737 | dev_warn(&pdev->dev, | ||
1738 | "Multi rfd not support yet!\n"); | ||
1739 | break; | ||
1740 | } | ||
1741 | atl1c_clean_rfd(rfd_ring, rrs, rfd_num); | ||
1742 | skb_put(skb, length - ETH_FCS_LEN); | ||
1743 | skb->protocol = eth_type_trans(skb, netdev); | ||
1744 | skb->dev = netdev; | ||
1745 | atl1c_rx_checksum(adapter, skb, rrs); | ||
1746 | if (unlikely(adapter->vlgrp) && rrs->word3 & RRS_VLAN_INS) { | ||
1747 | u16 vlan; | ||
1748 | |||
1749 | AT_TAG_TO_VLAN(rrs->vlan_tag, vlan); | ||
1750 | vlan = le16_to_cpu(vlan); | ||
1751 | vlan_hwaccel_receive_skb(skb, adapter->vlgrp, vlan); | ||
1752 | } else | ||
1753 | netif_receive_skb(skb); | ||
1754 | |||
1755 | netdev->last_rx = jiffies; | ||
1756 | (*work_done)++; | ||
1757 | count++; | ||
1758 | } | ||
1759 | if (count) | ||
1760 | atl1c_alloc_rx_buffer(adapter, que); | ||
1761 | } | ||
1762 | |||
1763 | /* | ||
1764 | * atl1c_clean - NAPI Rx polling callback | ||
1765 | * @adapter: board private structure | ||
1766 | */ | ||
1767 | static int atl1c_clean(struct napi_struct *napi, int budget) | ||
1768 | { | ||
1769 | struct atl1c_adapter *adapter = | ||
1770 | container_of(napi, struct atl1c_adapter, napi); | ||
1771 | int work_done = 0; | ||
1772 | |||
1773 | /* Keep link state information with original netdev */ | ||
1774 | if (!netif_carrier_ok(adapter->netdev)) | ||
1775 | goto quit_polling; | ||
1776 | /* just enable one RXQ */ | ||
1777 | atl1c_clean_rx_irq(adapter, 0, &work_done, budget); | ||
1778 | |||
1779 | if (work_done < budget) { | ||
1780 | quit_polling: | ||
1781 | napi_complete(napi); | ||
1782 | adapter->hw.intr_mask |= ISR_RX_PKT; | ||
1783 | AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask); | ||
1784 | } | ||
1785 | return work_done; | ||
1786 | } | ||
1787 | |||
1788 | #ifdef CONFIG_NET_POLL_CONTROLLER | ||
1789 | |||
1790 | /* | ||
1791 | * Polling 'interrupt' - used by things like netconsole to send skbs | ||
1792 | * without having to re-enable interrupts. It's not called while | ||
1793 | * the interrupt routine is executing. | ||
1794 | */ | ||
1795 | static void atl1c_netpoll(struct net_device *netdev) | ||
1796 | { | ||
1797 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
1798 | |||
1799 | disable_irq(adapter->pdev->irq); | ||
1800 | atl1c_intr(adapter->pdev->irq, netdev); | ||
1801 | enable_irq(adapter->pdev->irq); | ||
1802 | } | ||
1803 | #endif | ||
1804 | |||
1805 | static inline u16 atl1c_tpd_avail(struct atl1c_adapter *adapter, enum atl1c_trans_queue type) | ||
1806 | { | ||
1807 | struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type]; | ||
1808 | u16 next_to_use = 0; | ||
1809 | u16 next_to_clean = 0; | ||
1810 | |||
1811 | next_to_clean = atomic_read(&tpd_ring->next_to_clean); | ||
1812 | next_to_use = tpd_ring->next_to_use; | ||
1813 | |||
1814 | return (u16)(next_to_clean > next_to_use) ? | ||
1815 | (next_to_clean - next_to_use - 1) : | ||
1816 | (tpd_ring->count + next_to_clean - next_to_use - 1); | ||
1817 | } | ||
1818 | |||
1819 | /* | ||
1820 | * get next usable tpd | ||
1821 | * Note: should call atl1c_tdp_avail to make sure | ||
1822 | * there is enough tpd to use | ||
1823 | */ | ||
1824 | static struct atl1c_tpd_desc *atl1c_get_tpd(struct atl1c_adapter *adapter, | ||
1825 | enum atl1c_trans_queue type) | ||
1826 | { | ||
1827 | struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type]; | ||
1828 | struct atl1c_tpd_desc *tpd_desc; | ||
1829 | u16 next_to_use = 0; | ||
1830 | |||
1831 | next_to_use = tpd_ring->next_to_use; | ||
1832 | if (++tpd_ring->next_to_use == tpd_ring->count) | ||
1833 | tpd_ring->next_to_use = 0; | ||
1834 | tpd_desc = ATL1C_TPD_DESC(tpd_ring, next_to_use); | ||
1835 | memset(tpd_desc, 0, sizeof(struct atl1c_tpd_desc)); | ||
1836 | return tpd_desc; | ||
1837 | } | ||
1838 | |||
1839 | static struct atl1c_buffer * | ||
1840 | atl1c_get_tx_buffer(struct atl1c_adapter *adapter, struct atl1c_tpd_desc *tpd) | ||
1841 | { | ||
1842 | struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring; | ||
1843 | |||
1844 | return &tpd_ring->buffer_info[tpd - | ||
1845 | (struct atl1c_tpd_desc *)tpd_ring->desc]; | ||
1846 | } | ||
1847 | |||
1848 | /* Calculate the transmit packet descript needed*/ | ||
1849 | static u16 atl1c_cal_tpd_req(const struct sk_buff *skb) | ||
1850 | { | ||
1851 | u16 tpd_req; | ||
1852 | u16 proto_hdr_len = 0; | ||
1853 | |||
1854 | tpd_req = skb_shinfo(skb)->nr_frags + 1; | ||
1855 | |||
1856 | if (skb_is_gso(skb)) { | ||
1857 | proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | ||
1858 | if (proto_hdr_len < skb_headlen(skb)) | ||
1859 | tpd_req++; | ||
1860 | if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) | ||
1861 | tpd_req++; | ||
1862 | } | ||
1863 | return tpd_req; | ||
1864 | } | ||
1865 | |||
1866 | static int atl1c_tso_csum(struct atl1c_adapter *adapter, | ||
1867 | struct sk_buff *skb, | ||
1868 | struct atl1c_tpd_desc **tpd, | ||
1869 | enum atl1c_trans_queue type) | ||
1870 | { | ||
1871 | struct pci_dev *pdev = adapter->pdev; | ||
1872 | u8 hdr_len; | ||
1873 | u32 real_len; | ||
1874 | unsigned short offload_type; | ||
1875 | int err; | ||
1876 | |||
1877 | if (skb_is_gso(skb)) { | ||
1878 | if (skb_header_cloned(skb)) { | ||
1879 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | ||
1880 | if (unlikely(err)) | ||
1881 | return -1; | ||
1882 | } | ||
1883 | offload_type = skb_shinfo(skb)->gso_type; | ||
1884 | |||
1885 | if (offload_type & SKB_GSO_TCPV4) { | ||
1886 | real_len = (((unsigned char *)ip_hdr(skb) - skb->data) | ||
1887 | + ntohs(ip_hdr(skb)->tot_len)); | ||
1888 | |||
1889 | if (real_len < skb->len) | ||
1890 | pskb_trim(skb, real_len); | ||
1891 | |||
1892 | hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb)); | ||
1893 | if (unlikely(skb->len == hdr_len)) { | ||
1894 | /* only xsum need */ | ||
1895 | if (netif_msg_tx_queued(adapter)) | ||
1896 | dev_warn(&pdev->dev, | ||
1897 | "IPV4 tso with zero data??\n"); | ||
1898 | goto check_sum; | ||
1899 | } else { | ||
1900 | ip_hdr(skb)->check = 0; | ||
1901 | tcp_hdr(skb)->check = ~csum_tcpudp_magic( | ||
1902 | ip_hdr(skb)->saddr, | ||
1903 | ip_hdr(skb)->daddr, | ||
1904 | 0, IPPROTO_TCP, 0); | ||
1905 | (*tpd)->word1 |= 1 << TPD_IPV4_PACKET_SHIFT; | ||
1906 | } | ||
1907 | } | ||
1908 | |||
1909 | if (offload_type & SKB_GSO_TCPV6) { | ||
1910 | struct atl1c_tpd_ext_desc *etpd = | ||
1911 | *(struct atl1c_tpd_ext_desc **)(tpd); | ||
1912 | |||
1913 | memset(etpd, 0, sizeof(struct atl1c_tpd_ext_desc)); | ||
1914 | *tpd = atl1c_get_tpd(adapter, type); | ||
1915 | ipv6_hdr(skb)->payload_len = 0; | ||
1916 | /* check payload == 0 byte ? */ | ||
1917 | hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb)); | ||
1918 | if (unlikely(skb->len == hdr_len)) { | ||
1919 | /* only xsum need */ | ||
1920 | if (netif_msg_tx_queued(adapter)) | ||
1921 | dev_warn(&pdev->dev, | ||
1922 | "IPV6 tso with zero data??\n"); | ||
1923 | goto check_sum; | ||
1924 | } else | ||
1925 | tcp_hdr(skb)->check = ~csum_ipv6_magic( | ||
1926 | &ipv6_hdr(skb)->saddr, | ||
1927 | &ipv6_hdr(skb)->daddr, | ||
1928 | 0, IPPROTO_TCP, 0); | ||
1929 | etpd->word1 |= 1 << TPD_LSO_EN_SHIFT; | ||
1930 | etpd->word1 |= 1 << TPD_LSO_VER_SHIFT; | ||
1931 | etpd->pkt_len = cpu_to_le32(skb->len); | ||
1932 | (*tpd)->word1 |= 1 << TPD_LSO_VER_SHIFT; | ||
1933 | } | ||
1934 | |||
1935 | (*tpd)->word1 |= 1 << TPD_LSO_EN_SHIFT; | ||
1936 | (*tpd)->word1 |= (skb_transport_offset(skb) & TPD_TCPHDR_OFFSET_MASK) << | ||
1937 | TPD_TCPHDR_OFFSET_SHIFT; | ||
1938 | (*tpd)->word1 |= (skb_shinfo(skb)->gso_size & TPD_MSS_MASK) << | ||
1939 | TPD_MSS_SHIFT; | ||
1940 | return 0; | ||
1941 | } | ||
1942 | |||
1943 | check_sum: | ||
1944 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { | ||
1945 | u8 css, cso; | ||
1946 | cso = skb_transport_offset(skb); | ||
1947 | |||
1948 | if (unlikely(cso & 0x1)) { | ||
1949 | if (netif_msg_tx_err(adapter)) | ||
1950 | dev_err(&adapter->pdev->dev, | ||
1951 | "payload offset should not an event number\n"); | ||
1952 | return -1; | ||
1953 | } else { | ||
1954 | css = cso + skb->csum_offset; | ||
1955 | |||
1956 | (*tpd)->word1 |= ((cso >> 1) & TPD_PLOADOFFSET_MASK) << | ||
1957 | TPD_PLOADOFFSET_SHIFT; | ||
1958 | (*tpd)->word1 |= ((css >> 1) & TPD_CCSUM_OFFSET_MASK) << | ||
1959 | TPD_CCSUM_OFFSET_SHIFT; | ||
1960 | (*tpd)->word1 |= 1 << TPD_CCSUM_EN_SHIFT; | ||
1961 | } | ||
1962 | } | ||
1963 | return 0; | ||
1964 | } | ||
1965 | |||
1966 | static void atl1c_tx_map(struct atl1c_adapter *adapter, | ||
1967 | struct sk_buff *skb, struct atl1c_tpd_desc *tpd, | ||
1968 | enum atl1c_trans_queue type) | ||
1969 | { | ||
1970 | struct atl1c_tpd_desc *use_tpd = NULL; | ||
1971 | struct atl1c_buffer *buffer_info = NULL; | ||
1972 | u16 buf_len = skb_headlen(skb); | ||
1973 | u16 map_len = 0; | ||
1974 | u16 mapped_len = 0; | ||
1975 | u16 hdr_len = 0; | ||
1976 | u16 nr_frags; | ||
1977 | u16 f; | ||
1978 | int tso; | ||
1979 | |||
1980 | nr_frags = skb_shinfo(skb)->nr_frags; | ||
1981 | tso = (tpd->word1 >> TPD_LSO_EN_SHIFT) & TPD_LSO_EN_MASK; | ||
1982 | if (tso) { | ||
1983 | /* TSO */ | ||
1984 | map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | ||
1985 | use_tpd = tpd; | ||
1986 | |||
1987 | buffer_info = atl1c_get_tx_buffer(adapter, use_tpd); | ||
1988 | buffer_info->length = map_len; | ||
1989 | buffer_info->dma = pci_map_single(adapter->pdev, | ||
1990 | skb->data, hdr_len, PCI_DMA_TODEVICE); | ||
1991 | buffer_info->state = ATL1_BUFFER_BUSY; | ||
1992 | mapped_len += map_len; | ||
1993 | use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma); | ||
1994 | use_tpd->buffer_len = cpu_to_le16(buffer_info->length); | ||
1995 | } | ||
1996 | |||
1997 | if (mapped_len < buf_len) { | ||
1998 | /* mapped_len == 0, means we should use the first tpd, | ||
1999 | which is given by caller */ | ||
2000 | if (mapped_len == 0) | ||
2001 | use_tpd = tpd; | ||
2002 | else { | ||
2003 | use_tpd = atl1c_get_tpd(adapter, type); | ||
2004 | memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc)); | ||
2005 | use_tpd = atl1c_get_tpd(adapter, type); | ||
2006 | memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc)); | ||
2007 | } | ||
2008 | buffer_info = atl1c_get_tx_buffer(adapter, use_tpd); | ||
2009 | buffer_info->length = buf_len - mapped_len; | ||
2010 | buffer_info->dma = | ||
2011 | pci_map_single(adapter->pdev, skb->data + mapped_len, | ||
2012 | buffer_info->length, PCI_DMA_TODEVICE); | ||
2013 | buffer_info->state = ATL1_BUFFER_BUSY; | ||
2014 | |||
2015 | use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma); | ||
2016 | use_tpd->buffer_len = cpu_to_le16(buffer_info->length); | ||
2017 | } | ||
2018 | |||
2019 | for (f = 0; f < nr_frags; f++) { | ||
2020 | struct skb_frag_struct *frag; | ||
2021 | |||
2022 | frag = &skb_shinfo(skb)->frags[f]; | ||
2023 | |||
2024 | use_tpd = atl1c_get_tpd(adapter, type); | ||
2025 | memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc)); | ||
2026 | |||
2027 | buffer_info = atl1c_get_tx_buffer(adapter, use_tpd); | ||
2028 | buffer_info->length = frag->size; | ||
2029 | buffer_info->dma = | ||
2030 | pci_map_page(adapter->pdev, frag->page, | ||
2031 | frag->page_offset, | ||
2032 | buffer_info->length, | ||
2033 | PCI_DMA_TODEVICE); | ||
2034 | buffer_info->state = ATL1_BUFFER_BUSY; | ||
2035 | |||
2036 | use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma); | ||
2037 | use_tpd->buffer_len = cpu_to_le16(buffer_info->length); | ||
2038 | } | ||
2039 | |||
2040 | /* The last tpd */ | ||
2041 | use_tpd->word1 |= 1 << TPD_EOP_SHIFT; | ||
2042 | /* The last buffer info contain the skb address, | ||
2043 | so it will be free after unmap */ | ||
2044 | buffer_info->skb = skb; | ||
2045 | } | ||
2046 | |||
2047 | static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb, | ||
2048 | struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type) | ||
2049 | { | ||
2050 | struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type]; | ||
2051 | u32 prod_data; | ||
2052 | |||
2053 | AT_READ_REG(&adapter->hw, REG_MB_PRIO_PROD_IDX, &prod_data); | ||
2054 | switch (type) { | ||
2055 | case atl1c_trans_high: | ||
2056 | prod_data &= 0xFFFF0000; | ||
2057 | prod_data |= tpd_ring->next_to_use & 0xFFFF; | ||
2058 | break; | ||
2059 | case atl1c_trans_normal: | ||
2060 | prod_data &= 0x0000FFFF; | ||
2061 | prod_data |= (tpd_ring->next_to_use & 0xFFFF) << 16; | ||
2062 | break; | ||
2063 | default: | ||
2064 | break; | ||
2065 | } | ||
2066 | wmb(); | ||
2067 | AT_WRITE_REG(&adapter->hw, REG_MB_PRIO_PROD_IDX, prod_data); | ||
2068 | } | ||
2069 | |||
2070 | static int atl1c_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | ||
2071 | { | ||
2072 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
2073 | unsigned long flags; | ||
2074 | u16 tpd_req = 1; | ||
2075 | struct atl1c_tpd_desc *tpd; | ||
2076 | enum atl1c_trans_queue type = atl1c_trans_normal; | ||
2077 | |||
2078 | if (test_bit(__AT_DOWN, &adapter->flags)) { | ||
2079 | dev_kfree_skb_any(skb); | ||
2080 | return NETDEV_TX_OK; | ||
2081 | } | ||
2082 | |||
2083 | tpd_req = atl1c_cal_tpd_req(skb); | ||
2084 | if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) { | ||
2085 | if (netif_msg_pktdata(adapter)) | ||
2086 | dev_info(&adapter->pdev->dev, "tx locked\n"); | ||
2087 | return NETDEV_TX_LOCKED; | ||
2088 | } | ||
2089 | if (skb->mark == 0x01) | ||
2090 | type = atl1c_trans_high; | ||
2091 | else | ||
2092 | type = atl1c_trans_normal; | ||
2093 | |||
2094 | if (atl1c_tpd_avail(adapter, type) < tpd_req) { | ||
2095 | /* no enough descriptor, just stop queue */ | ||
2096 | netif_stop_queue(netdev); | ||
2097 | spin_unlock_irqrestore(&adapter->tx_lock, flags); | ||
2098 | return NETDEV_TX_BUSY; | ||
2099 | } | ||
2100 | |||
2101 | tpd = atl1c_get_tpd(adapter, type); | ||
2102 | |||
2103 | /* do TSO and check sum */ | ||
2104 | if (atl1c_tso_csum(adapter, skb, &tpd, type) != 0) { | ||
2105 | spin_unlock_irqrestore(&adapter->tx_lock, flags); | ||
2106 | dev_kfree_skb_any(skb); | ||
2107 | return NETDEV_TX_OK; | ||
2108 | } | ||
2109 | |||
2110 | if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) { | ||
2111 | u16 vlan = vlan_tx_tag_get(skb); | ||
2112 | __le16 tag; | ||
2113 | |||
2114 | vlan = cpu_to_le16(vlan); | ||
2115 | AT_VLAN_TO_TAG(vlan, tag); | ||
2116 | tpd->word1 |= 1 << TPD_INS_VTAG_SHIFT; | ||
2117 | tpd->vlan_tag = tag; | ||
2118 | } | ||
2119 | |||
2120 | if (skb_network_offset(skb) != ETH_HLEN) | ||
2121 | tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */ | ||
2122 | |||
2123 | atl1c_tx_map(adapter, skb, tpd, type); | ||
2124 | atl1c_tx_queue(adapter, skb, tpd, type); | ||
2125 | |||
2126 | netdev->trans_start = jiffies; | ||
2127 | spin_unlock_irqrestore(&adapter->tx_lock, flags); | ||
2128 | return NETDEV_TX_OK; | ||
2129 | } | ||
2130 | |||
2131 | static void atl1c_free_irq(struct atl1c_adapter *adapter) | ||
2132 | { | ||
2133 | struct net_device *netdev = adapter->netdev; | ||
2134 | |||
2135 | free_irq(adapter->pdev->irq, netdev); | ||
2136 | |||
2137 | if (adapter->have_msi) | ||
2138 | pci_disable_msi(adapter->pdev); | ||
2139 | } | ||
2140 | |||
2141 | static int atl1c_request_irq(struct atl1c_adapter *adapter) | ||
2142 | { | ||
2143 | struct pci_dev *pdev = adapter->pdev; | ||
2144 | struct net_device *netdev = adapter->netdev; | ||
2145 | int flags = 0; | ||
2146 | int err = 0; | ||
2147 | |||
2148 | adapter->have_msi = true; | ||
2149 | err = pci_enable_msi(adapter->pdev); | ||
2150 | if (err) { | ||
2151 | if (netif_msg_ifup(adapter)) | ||
2152 | dev_err(&pdev->dev, | ||
2153 | "Unable to allocate MSI interrupt Error: %d\n", | ||
2154 | err); | ||
2155 | adapter->have_msi = false; | ||
2156 | } else | ||
2157 | netdev->irq = pdev->irq; | ||
2158 | |||
2159 | if (!adapter->have_msi) | ||
2160 | flags |= IRQF_SHARED; | ||
2161 | err = request_irq(adapter->pdev->irq, &atl1c_intr, flags, | ||
2162 | netdev->name, netdev); | ||
2163 | if (err) { | ||
2164 | if (netif_msg_ifup(adapter)) | ||
2165 | dev_err(&pdev->dev, | ||
2166 | "Unable to allocate interrupt Error: %d\n", | ||
2167 | err); | ||
2168 | if (adapter->have_msi) | ||
2169 | pci_disable_msi(adapter->pdev); | ||
2170 | return err; | ||
2171 | } | ||
2172 | if (netif_msg_ifup(adapter)) | ||
2173 | dev_dbg(&pdev->dev, "atl1c_request_irq OK\n"); | ||
2174 | return err; | ||
2175 | } | ||
2176 | |||
2177 | int atl1c_up(struct atl1c_adapter *adapter) | ||
2178 | { | ||
2179 | struct net_device *netdev = adapter->netdev; | ||
2180 | int num; | ||
2181 | int err; | ||
2182 | int i; | ||
2183 | |||
2184 | netif_carrier_off(netdev); | ||
2185 | atl1c_init_ring_ptrs(adapter); | ||
2186 | atl1c_set_multi(netdev); | ||
2187 | atl1c_restore_vlan(adapter); | ||
2188 | |||
2189 | for (i = 0; i < adapter->num_rx_queues; i++) { | ||
2190 | num = atl1c_alloc_rx_buffer(adapter, i); | ||
2191 | if (unlikely(num == 0)) { | ||
2192 | err = -ENOMEM; | ||
2193 | goto err_alloc_rx; | ||
2194 | } | ||
2195 | } | ||
2196 | |||
2197 | if (atl1c_configure(adapter)) { | ||
2198 | err = -EIO; | ||
2199 | goto err_up; | ||
2200 | } | ||
2201 | |||
2202 | err = atl1c_request_irq(adapter); | ||
2203 | if (unlikely(err)) | ||
2204 | goto err_up; | ||
2205 | |||
2206 | clear_bit(__AT_DOWN, &adapter->flags); | ||
2207 | napi_enable(&adapter->napi); | ||
2208 | atl1c_irq_enable(adapter); | ||
2209 | atl1c_check_link_status(adapter); | ||
2210 | netif_start_queue(netdev); | ||
2211 | return err; | ||
2212 | |||
2213 | err_up: | ||
2214 | err_alloc_rx: | ||
2215 | atl1c_clean_rx_ring(adapter); | ||
2216 | return err; | ||
2217 | } | ||
2218 | |||
2219 | void atl1c_down(struct atl1c_adapter *adapter) | ||
2220 | { | ||
2221 | struct net_device *netdev = adapter->netdev; | ||
2222 | |||
2223 | atl1c_del_timer(adapter); | ||
2224 | atl1c_cancel_work(adapter); | ||
2225 | |||
2226 | /* signal that we're down so the interrupt handler does not | ||
2227 | * reschedule our watchdog timer */ | ||
2228 | set_bit(__AT_DOWN, &adapter->flags); | ||
2229 | netif_carrier_off(netdev); | ||
2230 | napi_disable(&adapter->napi); | ||
2231 | atl1c_irq_disable(adapter); | ||
2232 | atl1c_free_irq(adapter); | ||
2233 | AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT); | ||
2234 | /* reset MAC to disable all RX/TX */ | ||
2235 | atl1c_reset_mac(&adapter->hw); | ||
2236 | msleep(1); | ||
2237 | |||
2238 | adapter->link_speed = SPEED_0; | ||
2239 | adapter->link_duplex = -1; | ||
2240 | atl1c_clean_tx_ring(adapter, atl1c_trans_normal); | ||
2241 | atl1c_clean_tx_ring(adapter, atl1c_trans_high); | ||
2242 | atl1c_clean_rx_ring(adapter); | ||
2243 | } | ||
2244 | |||
2245 | /* | ||
2246 | * atl1c_open - Called when a network interface is made active | ||
2247 | * @netdev: network interface device structure | ||
2248 | * | ||
2249 | * Returns 0 on success, negative value on failure | ||
2250 | * | ||
2251 | * The open entry point is called when a network interface is made | ||
2252 | * active by the system (IFF_UP). At this point all resources needed | ||
2253 | * for transmit and receive operations are allocated, the interrupt | ||
2254 | * handler is registered with the OS, the watchdog timer is started, | ||
2255 | * and the stack is notified that the interface is ready. | ||
2256 | */ | ||
2257 | static int atl1c_open(struct net_device *netdev) | ||
2258 | { | ||
2259 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
2260 | int err; | ||
2261 | |||
2262 | /* disallow open during test */ | ||
2263 | if (test_bit(__AT_TESTING, &adapter->flags)) | ||
2264 | return -EBUSY; | ||
2265 | |||
2266 | /* allocate rx/tx dma buffer & descriptors */ | ||
2267 | err = atl1c_setup_ring_resources(adapter); | ||
2268 | if (unlikely(err)) | ||
2269 | return err; | ||
2270 | |||
2271 | err = atl1c_up(adapter); | ||
2272 | if (unlikely(err)) | ||
2273 | goto err_up; | ||
2274 | |||
2275 | if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) { | ||
2276 | u32 phy_data; | ||
2277 | |||
2278 | AT_READ_REG(&adapter->hw, REG_MDIO_CTRL, &phy_data); | ||
2279 | phy_data |= MDIO_AP_EN; | ||
2280 | AT_WRITE_REG(&adapter->hw, REG_MDIO_CTRL, phy_data); | ||
2281 | } | ||
2282 | return 0; | ||
2283 | |||
2284 | err_up: | ||
2285 | atl1c_free_irq(adapter); | ||
2286 | atl1c_free_ring_resources(adapter); | ||
2287 | atl1c_reset_mac(&adapter->hw); | ||
2288 | return err; | ||
2289 | } | ||
2290 | |||
2291 | /* | ||
2292 | * atl1c_close - Disables a network interface | ||
2293 | * @netdev: network interface device structure | ||
2294 | * | ||
2295 | * Returns 0, this is not allowed to fail | ||
2296 | * | ||
2297 | * The close entry point is called when an interface is de-activated | ||
2298 | * by the OS. The hardware is still under the drivers control, but | ||
2299 | * needs to be disabled. A global MAC reset is issued to stop the | ||
2300 | * hardware, and all transmit and receive resources are freed. | ||
2301 | */ | ||
2302 | static int atl1c_close(struct net_device *netdev) | ||
2303 | { | ||
2304 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
2305 | |||
2306 | WARN_ON(test_bit(__AT_RESETTING, &adapter->flags)); | ||
2307 | atl1c_down(adapter); | ||
2308 | atl1c_free_ring_resources(adapter); | ||
2309 | return 0; | ||
2310 | } | ||
2311 | |||
2312 | static int atl1c_suspend(struct pci_dev *pdev, pm_message_t state) | ||
2313 | { | ||
2314 | struct net_device *netdev = pci_get_drvdata(pdev); | ||
2315 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
2316 | struct atl1c_hw *hw = &adapter->hw; | ||
2317 | u32 ctrl; | ||
2318 | u32 mac_ctrl_data; | ||
2319 | u32 master_ctrl_data; | ||
2320 | u32 wol_ctrl_data; | ||
2321 | u16 mii_bmsr_data; | ||
2322 | u16 save_autoneg_advertised; | ||
2323 | u16 mii_intr_status_data; | ||
2324 | u32 wufc = adapter->wol; | ||
2325 | u32 i; | ||
2326 | int retval = 0; | ||
2327 | |||
2328 | if (netif_running(netdev)) { | ||
2329 | WARN_ON(test_bit(__AT_RESETTING, &adapter->flags)); | ||
2330 | atl1c_down(adapter); | ||
2331 | } | ||
2332 | netif_device_detach(netdev); | ||
2333 | atl1c_disable_l0s_l1(hw); | ||
2334 | retval = pci_save_state(pdev); | ||
2335 | if (retval) | ||
2336 | return retval; | ||
2337 | if (wufc) { | ||
2338 | AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data); | ||
2339 | master_ctrl_data &= ~MASTER_CTRL_CLK_SEL_DIS; | ||
2340 | |||
2341 | /* get link status */ | ||
2342 | atl1c_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data); | ||
2343 | atl1c_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data); | ||
2344 | save_autoneg_advertised = hw->autoneg_advertised; | ||
2345 | hw->autoneg_advertised = ADVERTISED_10baseT_Half; | ||
2346 | if (atl1c_restart_autoneg(hw) != 0) | ||
2347 | if (netif_msg_link(adapter)) | ||
2348 | dev_warn(&pdev->dev, "phy autoneg failed\n"); | ||
2349 | hw->phy_configured = false; /* re-init PHY when resume */ | ||
2350 | hw->autoneg_advertised = save_autoneg_advertised; | ||
2351 | /* turn on magic packet wol */ | ||
2352 | if (wufc & AT_WUFC_MAG) | ||
2353 | wol_ctrl_data = WOL_MAGIC_EN | WOL_MAGIC_PME_EN; | ||
2354 | |||
2355 | if (wufc & AT_WUFC_LNKC) { | ||
2356 | for (i = 0; i < AT_SUSPEND_LINK_TIMEOUT; i++) { | ||
2357 | msleep(100); | ||
2358 | atl1c_read_phy_reg(hw, MII_BMSR, | ||
2359 | (u16 *)&mii_bmsr_data); | ||
2360 | if (mii_bmsr_data & BMSR_LSTATUS) | ||
2361 | break; | ||
2362 | } | ||
2363 | if ((mii_bmsr_data & BMSR_LSTATUS) == 0) | ||
2364 | if (netif_msg_link(adapter)) | ||
2365 | dev_warn(&pdev->dev, | ||
2366 | "%s: Link may change" | ||
2367 | "when suspend\n", | ||
2368 | atl1c_driver_name); | ||
2369 | wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN; | ||
2370 | /* only link up can wake up */ | ||
2371 | if (atl1c_write_phy_reg(hw, MII_IER, IER_LINK_UP) != 0) { | ||
2372 | if (netif_msg_link(adapter)) | ||
2373 | dev_err(&pdev->dev, | ||
2374 | "%s: read write phy " | ||
2375 | "register failed.\n", | ||
2376 | atl1c_driver_name); | ||
2377 | goto wol_dis; | ||
2378 | } | ||
2379 | } | ||
2380 | /* clear phy interrupt */ | ||
2381 | atl1c_read_phy_reg(hw, MII_ISR, &mii_intr_status_data); | ||
2382 | /* Config MAC Ctrl register */ | ||
2383 | mac_ctrl_data = MAC_CTRL_RX_EN; | ||
2384 | /* set to 10/100M halt duplex */ | ||
2385 | mac_ctrl_data |= atl1c_mac_speed_10_100 << MAC_CTRL_SPEED_SHIFT; | ||
2386 | mac_ctrl_data |= (((u32)adapter->hw.preamble_len & | ||
2387 | MAC_CTRL_PRMLEN_MASK) << | ||
2388 | MAC_CTRL_PRMLEN_SHIFT); | ||
2389 | |||
2390 | if (adapter->vlgrp) | ||
2391 | mac_ctrl_data |= MAC_CTRL_RMV_VLAN; | ||
2392 | |||
2393 | /* magic packet maybe Broadcast&multicast&Unicast frame */ | ||
2394 | if (wufc & AT_WUFC_MAG) | ||
2395 | mac_ctrl_data |= MAC_CTRL_BC_EN; | ||
2396 | |||
2397 | if (netif_msg_hw(adapter)) | ||
2398 | dev_dbg(&pdev->dev, | ||
2399 | "%s: suspend MAC=0x%x\n", | ||
2400 | atl1c_driver_name, mac_ctrl_data); | ||
2401 | AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data); | ||
2402 | AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data); | ||
2403 | AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data); | ||
2404 | |||
2405 | /* pcie patch */ | ||
2406 | AT_READ_REG(hw, REG_PCIE_PHYMISC, &ctrl); | ||
2407 | ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; | ||
2408 | AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); | ||
2409 | |||
2410 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); | ||
2411 | goto suspend_exit; | ||
2412 | } | ||
2413 | wol_dis: | ||
2414 | |||
2415 | /* WOL disabled */ | ||
2416 | AT_WRITE_REG(hw, REG_WOL_CTRL, 0); | ||
2417 | |||
2418 | /* pcie patch */ | ||
2419 | AT_READ_REG(hw, REG_PCIE_PHYMISC, &ctrl); | ||
2420 | ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; | ||
2421 | AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); | ||
2422 | |||
2423 | atl1c_phy_disable(hw); | ||
2424 | hw->phy_configured = false; /* re-init PHY when resume */ | ||
2425 | |||
2426 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); | ||
2427 | suspend_exit: | ||
2428 | |||
2429 | pci_disable_device(pdev); | ||
2430 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | ||
2431 | |||
2432 | return 0; | ||
2433 | } | ||
2434 | |||
2435 | static int atl1c_resume(struct pci_dev *pdev) | ||
2436 | { | ||
2437 | struct net_device *netdev = pci_get_drvdata(pdev); | ||
2438 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
2439 | |||
2440 | pci_set_power_state(pdev, PCI_D0); | ||
2441 | pci_restore_state(pdev); | ||
2442 | pci_enable_wake(pdev, PCI_D3hot, 0); | ||
2443 | pci_enable_wake(pdev, PCI_D3cold, 0); | ||
2444 | |||
2445 | AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); | ||
2446 | |||
2447 | atl1c_phy_reset(&adapter->hw); | ||
2448 | atl1c_reset_mac(&adapter->hw); | ||
2449 | netif_device_attach(netdev); | ||
2450 | if (netif_running(netdev)) | ||
2451 | atl1c_up(adapter); | ||
2452 | |||
2453 | return 0; | ||
2454 | } | ||
2455 | |||
2456 | static void atl1c_shutdown(struct pci_dev *pdev) | ||
2457 | { | ||
2458 | atl1c_suspend(pdev, PMSG_SUSPEND); | ||
2459 | } | ||
2460 | |||
2461 | static const struct net_device_ops atl1c_netdev_ops = { | ||
2462 | .ndo_open = atl1c_open, | ||
2463 | .ndo_stop = atl1c_close, | ||
2464 | .ndo_validate_addr = eth_validate_addr, | ||
2465 | .ndo_start_xmit = atl1c_xmit_frame, | ||
2466 | .ndo_set_mac_address = atl1c_set_mac_addr, | ||
2467 | .ndo_set_multicast_list = atl1c_set_multi, | ||
2468 | .ndo_change_mtu = atl1c_change_mtu, | ||
2469 | .ndo_do_ioctl = atl1c_ioctl, | ||
2470 | .ndo_tx_timeout = atl1c_tx_timeout, | ||
2471 | .ndo_get_stats = atl1c_get_stats, | ||
2472 | .ndo_vlan_rx_register = atl1c_vlan_rx_register, | ||
2473 | #ifdef CONFIG_NET_POLL_CONTROLLER | ||
2474 | .ndo_poll_controller = atl1c_netpoll, | ||
2475 | #endif | ||
2476 | }; | ||
2477 | |||
2478 | static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev) | ||
2479 | { | ||
2480 | SET_NETDEV_DEV(netdev, &pdev->dev); | ||
2481 | pci_set_drvdata(pdev, netdev); | ||
2482 | |||
2483 | netdev->irq = pdev->irq; | ||
2484 | netdev->netdev_ops = &atl1c_netdev_ops; | ||
2485 | netdev->watchdog_timeo = AT_TX_WATCHDOG; | ||
2486 | atl1c_set_ethtool_ops(netdev); | ||
2487 | |||
2488 | /* TODO: add when ready */ | ||
2489 | netdev->features = NETIF_F_SG | | ||
2490 | NETIF_F_HW_CSUM | | ||
2491 | NETIF_F_HW_VLAN_TX | | ||
2492 | NETIF_F_HW_VLAN_RX | | ||
2493 | NETIF_F_TSO | | ||
2494 | NETIF_F_TSO6; | ||
2495 | return 0; | ||
2496 | } | ||
2497 | |||
2498 | /* | ||
2499 | * atl1c_probe - Device Initialization Routine | ||
2500 | * @pdev: PCI device information struct | ||
2501 | * @ent: entry in atl1c_pci_tbl | ||
2502 | * | ||
2503 | * Returns 0 on success, negative on failure | ||
2504 | * | ||
2505 | * atl1c_probe initializes an adapter identified by a pci_dev structure. | ||
2506 | * The OS initialization, configuring of the adapter private structure, | ||
2507 | * and a hardware reset occur. | ||
2508 | */ | ||
2509 | static int __devinit atl1c_probe(struct pci_dev *pdev, | ||
2510 | const struct pci_device_id *ent) | ||
2511 | { | ||
2512 | struct net_device *netdev; | ||
2513 | struct atl1c_adapter *adapter; | ||
2514 | static int cards_found; | ||
2515 | |||
2516 | int err = 0; | ||
2517 | |||
2518 | /* enable device (incl. PCI PM wakeup and hotplug setup) */ | ||
2519 | err = pci_enable_device_mem(pdev); | ||
2520 | if (err) { | ||
2521 | dev_err(&pdev->dev, "cannot enable PCI device\n"); | ||
2522 | return err; | ||
2523 | } | ||
2524 | |||
2525 | /* | ||
2526 | * The atl1c chip can DMA to 64-bit addresses, but it uses a single | ||
2527 | * shared register for the high 32 bits, so only a single, aligned, | ||
2528 | * 4 GB physical address range can be used at a time. | ||
2529 | * | ||
2530 | * Supporting 64-bit DMA on this hardware is more trouble than it's | ||
2531 | * worth. It is far easier to limit to 32-bit DMA than update | ||
2532 | * various kernel subsystems to support the mechanics required by a | ||
2533 | * fixed-high-32-bit system. | ||
2534 | */ | ||
2535 | if ((pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) || | ||
2536 | (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK) != 0)) { | ||
2537 | dev_err(&pdev->dev, "No usable DMA configuration,aborting\n"); | ||
2538 | goto err_dma; | ||
2539 | } | ||
2540 | |||
2541 | err = pci_request_regions(pdev, atl1c_driver_name); | ||
2542 | if (err) { | ||
2543 | dev_err(&pdev->dev, "cannot obtain PCI resources\n"); | ||
2544 | goto err_pci_reg; | ||
2545 | } | ||
2546 | |||
2547 | pci_set_master(pdev); | ||
2548 | |||
2549 | netdev = alloc_etherdev(sizeof(struct atl1c_adapter)); | ||
2550 | if (netdev == NULL) { | ||
2551 | err = -ENOMEM; | ||
2552 | dev_err(&pdev->dev, "etherdev alloc failed\n"); | ||
2553 | goto err_alloc_etherdev; | ||
2554 | } | ||
2555 | |||
2556 | err = atl1c_init_netdev(netdev, pdev); | ||
2557 | if (err) { | ||
2558 | dev_err(&pdev->dev, "init netdevice failed\n"); | ||
2559 | goto err_init_netdev; | ||
2560 | } | ||
2561 | adapter = netdev_priv(netdev); | ||
2562 | adapter->bd_number = cards_found; | ||
2563 | adapter->netdev = netdev; | ||
2564 | adapter->pdev = pdev; | ||
2565 | adapter->hw.adapter = adapter; | ||
2566 | adapter->msg_enable = netif_msg_init(-1, atl1c_default_msg); | ||
2567 | adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0)); | ||
2568 | if (!adapter->hw.hw_addr) { | ||
2569 | err = -EIO; | ||
2570 | dev_err(&pdev->dev, "cannot map device registers\n"); | ||
2571 | goto err_ioremap; | ||
2572 | } | ||
2573 | netdev->base_addr = (unsigned long)adapter->hw.hw_addr; | ||
2574 | |||
2575 | /* init mii data */ | ||
2576 | adapter->mii.dev = netdev; | ||
2577 | adapter->mii.mdio_read = atl1c_mdio_read; | ||
2578 | adapter->mii.mdio_write = atl1c_mdio_write; | ||
2579 | adapter->mii.phy_id_mask = 0x1f; | ||
2580 | adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK; | ||
2581 | netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64); | ||
2582 | setup_timer(&adapter->phy_config_timer, atl1c_phy_config, | ||
2583 | (unsigned long)adapter); | ||
2584 | /* setup the private structure */ | ||
2585 | err = atl1c_sw_init(adapter); | ||
2586 | if (err) { | ||
2587 | dev_err(&pdev->dev, "net device private data init failed\n"); | ||
2588 | goto err_sw_init; | ||
2589 | } | ||
2590 | atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE | | ||
2591 | ATL1C_PCIE_PHY_RESET); | ||
2592 | |||
2593 | /* Init GPHY as early as possible due to power saving issue */ | ||
2594 | atl1c_phy_reset(&adapter->hw); | ||
2595 | |||
2596 | err = atl1c_reset_mac(&adapter->hw); | ||
2597 | if (err) { | ||
2598 | err = -EIO; | ||
2599 | goto err_reset; | ||
2600 | } | ||
2601 | |||
2602 | device_init_wakeup(&pdev->dev, 1); | ||
2603 | /* reset the controller to | ||
2604 | * put the device in a known good starting state */ | ||
2605 | err = atl1c_phy_init(&adapter->hw); | ||
2606 | if (err) { | ||
2607 | err = -EIO; | ||
2608 | goto err_reset; | ||
2609 | } | ||
2610 | if (atl1c_read_mac_addr(&adapter->hw) != 0) { | ||
2611 | err = -EIO; | ||
2612 | dev_err(&pdev->dev, "get mac address failed\n"); | ||
2613 | goto err_eeprom; | ||
2614 | } | ||
2615 | memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); | ||
2616 | memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len); | ||
2617 | if (netif_msg_probe(adapter)) | ||
2618 | dev_dbg(&pdev->dev, | ||
2619 | "mac address : %02x-%02x-%02x-%02x-%02x-%02x\n", | ||
2620 | adapter->hw.mac_addr[0], adapter->hw.mac_addr[1], | ||
2621 | adapter->hw.mac_addr[2], adapter->hw.mac_addr[3], | ||
2622 | adapter->hw.mac_addr[4], adapter->hw.mac_addr[5]); | ||
2623 | |||
2624 | atl1c_hw_set_mac_addr(&adapter->hw); | ||
2625 | INIT_WORK(&adapter->reset_task, atl1c_reset_task); | ||
2626 | INIT_WORK(&adapter->link_chg_task, atl1c_link_chg_task); | ||
2627 | err = register_netdev(netdev); | ||
2628 | if (err) { | ||
2629 | dev_err(&pdev->dev, "register netdevice failed\n"); | ||
2630 | goto err_register; | ||
2631 | } | ||
2632 | |||
2633 | if (netif_msg_probe(adapter)) | ||
2634 | dev_info(&pdev->dev, "version %s\n", ATL1C_DRV_VERSION); | ||
2635 | cards_found++; | ||
2636 | return 0; | ||
2637 | |||
2638 | err_reset: | ||
2639 | err_register: | ||
2640 | err_sw_init: | ||
2641 | err_eeprom: | ||
2642 | iounmap(adapter->hw.hw_addr); | ||
2643 | err_init_netdev: | ||
2644 | err_ioremap: | ||
2645 | free_netdev(netdev); | ||
2646 | err_alloc_etherdev: | ||
2647 | pci_release_regions(pdev); | ||
2648 | err_pci_reg: | ||
2649 | err_dma: | ||
2650 | pci_disable_device(pdev); | ||
2651 | return err; | ||
2652 | } | ||
2653 | |||
2654 | /* | ||
2655 | * atl1c_remove - Device Removal Routine | ||
2656 | * @pdev: PCI device information struct | ||
2657 | * | ||
2658 | * atl1c_remove is called by the PCI subsystem to alert the driver | ||
2659 | * that it should release a PCI device. The could be caused by a | ||
2660 | * Hot-Plug event, or because the driver is going to be removed from | ||
2661 | * memory. | ||
2662 | */ | ||
2663 | static void __devexit atl1c_remove(struct pci_dev *pdev) | ||
2664 | { | ||
2665 | struct net_device *netdev = pci_get_drvdata(pdev); | ||
2666 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
2667 | |||
2668 | unregister_netdev(netdev); | ||
2669 | atl1c_phy_disable(&adapter->hw); | ||
2670 | |||
2671 | iounmap(adapter->hw.hw_addr); | ||
2672 | |||
2673 | pci_release_regions(pdev); | ||
2674 | pci_disable_device(pdev); | ||
2675 | free_netdev(netdev); | ||
2676 | } | ||
2677 | |||
2678 | /* | ||
2679 | * atl1c_io_error_detected - called when PCI error is detected | ||
2680 | * @pdev: Pointer to PCI device | ||
2681 | * @state: The current pci connection state | ||
2682 | * | ||
2683 | * This function is called after a PCI bus error affecting | ||
2684 | * this device has been detected. | ||
2685 | */ | ||
2686 | static pci_ers_result_t atl1c_io_error_detected(struct pci_dev *pdev, | ||
2687 | pci_channel_state_t state) | ||
2688 | { | ||
2689 | struct net_device *netdev = pci_get_drvdata(pdev); | ||
2690 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
2691 | |||
2692 | netif_device_detach(netdev); | ||
2693 | |||
2694 | if (netif_running(netdev)) | ||
2695 | atl1c_down(adapter); | ||
2696 | |||
2697 | pci_disable_device(pdev); | ||
2698 | |||
2699 | /* Request a slot slot reset. */ | ||
2700 | return PCI_ERS_RESULT_NEED_RESET; | ||
2701 | } | ||
2702 | |||
2703 | /* | ||
2704 | * atl1c_io_slot_reset - called after the pci bus has been reset. | ||
2705 | * @pdev: Pointer to PCI device | ||
2706 | * | ||
2707 | * Restart the card from scratch, as if from a cold-boot. Implementation | ||
2708 | * resembles the first-half of the e1000_resume routine. | ||
2709 | */ | ||
2710 | static pci_ers_result_t atl1c_io_slot_reset(struct pci_dev *pdev) | ||
2711 | { | ||
2712 | struct net_device *netdev = pci_get_drvdata(pdev); | ||
2713 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
2714 | |||
2715 | if (pci_enable_device(pdev)) { | ||
2716 | if (netif_msg_hw(adapter)) | ||
2717 | dev_err(&pdev->dev, | ||
2718 | "Cannot re-enable PCI device after reset\n"); | ||
2719 | return PCI_ERS_RESULT_DISCONNECT; | ||
2720 | } | ||
2721 | pci_set_master(pdev); | ||
2722 | |||
2723 | pci_enable_wake(pdev, PCI_D3hot, 0); | ||
2724 | pci_enable_wake(pdev, PCI_D3cold, 0); | ||
2725 | |||
2726 | atl1c_reset_mac(&adapter->hw); | ||
2727 | |||
2728 | return PCI_ERS_RESULT_RECOVERED; | ||
2729 | } | ||
2730 | |||
2731 | /* | ||
2732 | * atl1c_io_resume - called when traffic can start flowing again. | ||
2733 | * @pdev: Pointer to PCI device | ||
2734 | * | ||
2735 | * This callback is called when the error recovery driver tells us that | ||
2736 | * its OK to resume normal operation. Implementation resembles the | ||
2737 | * second-half of the atl1c_resume routine. | ||
2738 | */ | ||
2739 | static void atl1c_io_resume(struct pci_dev *pdev) | ||
2740 | { | ||
2741 | struct net_device *netdev = pci_get_drvdata(pdev); | ||
2742 | struct atl1c_adapter *adapter = netdev_priv(netdev); | ||
2743 | |||
2744 | if (netif_running(netdev)) { | ||
2745 | if (atl1c_up(adapter)) { | ||
2746 | if (netif_msg_hw(adapter)) | ||
2747 | dev_err(&pdev->dev, | ||
2748 | "Cannot bring device back up after reset\n"); | ||
2749 | return; | ||
2750 | } | ||
2751 | } | ||
2752 | |||
2753 | netif_device_attach(netdev); | ||
2754 | } | ||
2755 | |||
2756 | static struct pci_error_handlers atl1c_err_handler = { | ||
2757 | .error_detected = atl1c_io_error_detected, | ||
2758 | .slot_reset = atl1c_io_slot_reset, | ||
2759 | .resume = atl1c_io_resume, | ||
2760 | }; | ||
2761 | |||
2762 | static struct pci_driver atl1c_driver = { | ||
2763 | .name = atl1c_driver_name, | ||
2764 | .id_table = atl1c_pci_tbl, | ||
2765 | .probe = atl1c_probe, | ||
2766 | .remove = __devexit_p(atl1c_remove), | ||
2767 | /* Power Managment Hooks */ | ||
2768 | .suspend = atl1c_suspend, | ||
2769 | .resume = atl1c_resume, | ||
2770 | .shutdown = atl1c_shutdown, | ||
2771 | .err_handler = &atl1c_err_handler | ||
2772 | }; | ||
2773 | |||
2774 | /* | ||
2775 | * atl1c_init_module - Driver Registration Routine | ||
2776 | * | ||
2777 | * atl1c_init_module is the first routine called when the driver is | ||
2778 | * loaded. All it does is register with the PCI subsystem. | ||
2779 | */ | ||
2780 | static int __init atl1c_init_module(void) | ||
2781 | { | ||
2782 | return pci_register_driver(&atl1c_driver); | ||
2783 | } | ||
2784 | |||
2785 | /* | ||
2786 | * atl1c_exit_module - Driver Exit Cleanup Routine | ||
2787 | * | ||
2788 | * atl1c_exit_module is called just before the driver is removed | ||
2789 | * from memory. | ||
2790 | */ | ||
2791 | static void __exit atl1c_exit_module(void) | ||
2792 | { | ||
2793 | pci_unregister_driver(&atl1c_driver); | ||
2794 | } | ||
2795 | |||
2796 | module_init(atl1c_init_module); | ||
2797 | module_exit(atl1c_exit_module); | ||