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authorTony Lindgren <tony@atomide.com>2011-02-28 20:58:09 -0500
committerTony Lindgren <tony@atomide.com>2011-02-28 20:58:09 -0500
commit1d90da9545b30015c0a9056909fc4b7991fa54e3 (patch)
treef3a1de0bf9d8f4484c0cf08edc4eac2ffa7055f7
parentd6b5d01b3f7c10edb50b9092d8dcac9cab680ea3 (diff)
parent38698bef545403a334cf92153874bd06dc22cc66 (diff)
Merge branch 'hwmod_clockevent_2.6.39' of git://git.pwsan.com/linux-2.6 into omap-for-linus
Diffstat
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c154
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c636
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c635
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c651
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/serial.c2
-rw-r--r--arch/arm/mach-omap2/timer-gp.c7
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h11
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h9
9 files changed, 2045 insertions, 62 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 9e89a58711b7..f76f133780c8 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * omap_hwmod implementation for OMAP2/3/4 2 * omap_hwmod implementation for OMAP2/3/4
3 * 3 *
4 * Copyright (C) 2009-2010 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * 5 *
6 * Paul Walmsley, Benoît Cousson, Kevin Hilman 6 * Paul Walmsley, Benoît Cousson, Kevin Hilman
7 * 7 *
@@ -162,9 +162,6 @@ static LIST_HEAD(omap_hwmod_list);
162/* mpu_oh: used to add/remove MPU initiator from sleepdep list */ 162/* mpu_oh: used to add/remove MPU initiator from sleepdep list */
163static struct omap_hwmod *mpu_oh; 163static struct omap_hwmod *mpu_oh;
164 164
165/* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */
166static u8 inited;
167
168 165
169/* Private functions */ 166/* Private functions */
170 167
@@ -904,18 +901,16 @@ static struct omap_hwmod *_lookup(const char *name)
904 * @oh: struct omap_hwmod * 901 * @oh: struct omap_hwmod *
905 * @data: not used; pass NULL 902 * @data: not used; pass NULL
906 * 903 *
907 * Called by omap_hwmod_late_init() (after omap2_clk_init()). 904 * Called by omap_hwmod_setup_*() (after omap2_clk_init()).
908 * Resolves all clock names embedded in the hwmod. Returns -EINVAL if 905 * Resolves all clock names embedded in the hwmod. Returns 0 on
909 * the omap_hwmod has not yet been registered or if the clocks have 906 * success, or a negative error code on failure.
910 * already been initialized, 0 on success, or a non-zero error on
911 * failure.
912 */ 907 */
913static int _init_clocks(struct omap_hwmod *oh, void *data) 908static int _init_clocks(struct omap_hwmod *oh, void *data)
914{ 909{
915 int ret = 0; 910 int ret = 0;
916 911
917 if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED)) 912 if (oh->_state != _HWMOD_STATE_REGISTERED)
918 return -EINVAL; 913 return 0;
919 914
920 pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); 915 pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
921 916
@@ -1354,14 +1349,16 @@ static int _shutdown(struct omap_hwmod *oh)
1354 * @oh: struct omap_hwmod * 1349 * @oh: struct omap_hwmod *
1355 * 1350 *
1356 * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh 1351 * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
1357 * OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the 1352 * OCP_SYSCONFIG register. Returns 0.
1358 * wrong state or returns 0.
1359 */ 1353 */
1360static int _setup(struct omap_hwmod *oh, void *data) 1354static int _setup(struct omap_hwmod *oh, void *data)
1361{ 1355{
1362 int i, r; 1356 int i, r;
1363 u8 postsetup_state; 1357 u8 postsetup_state;
1364 1358
1359 if (oh->_state != _HWMOD_STATE_CLKS_INITED)
1360 return 0;
1361
1365 /* Set iclk autoidle mode */ 1362 /* Set iclk autoidle mode */
1366 if (oh->slaves_cnt > 0) { 1363 if (oh->slaves_cnt > 0) {
1367 for (i = 0; i < oh->slaves_cnt; i++) { 1364 for (i = 0; i < oh->slaves_cnt; i++) {
@@ -1455,7 +1452,7 @@ static int _setup(struct omap_hwmod *oh, void *data)
1455 */ 1452 */
1456static int __init _register(struct omap_hwmod *oh) 1453static int __init _register(struct omap_hwmod *oh)
1457{ 1454{
1458 int ret, ms_id; 1455 int ms_id;
1459 1456
1460 if (!oh || !oh->name || !oh->class || !oh->class->name || 1457 if (!oh || !oh->name || !oh->class || !oh->class->name ||
1461 (oh->_state != _HWMOD_STATE_UNKNOWN)) 1458 (oh->_state != _HWMOD_STATE_UNKNOWN))
@@ -1478,9 +1475,14 @@ static int __init _register(struct omap_hwmod *oh)
1478 1475
1479 oh->_state = _HWMOD_STATE_REGISTERED; 1476 oh->_state = _HWMOD_STATE_REGISTERED;
1480 1477
1481 ret = 0; 1478 /*
1479 * XXX Rather than doing a strcmp(), this should test a flag
1480 * set in the hwmod data, inserted by the autogenerator code.
1481 */
1482 if (!strcmp(oh->name, MPU_INITIATOR_NAME))
1483 mpu_oh = oh;
1482 1484
1483 return ret; 1485 return 0;
1484} 1486}
1485 1487
1486 1488
@@ -1583,38 +1585,30 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
1583 return ret; 1585 return ret;
1584} 1586}
1585 1587
1586
1587/** 1588/**
1588 * omap_hwmod_init - init omap_hwmod code and register hwmods 1589 * omap_hwmod_register - register an array of hwmods
1589 * @ohs: pointer to an array of omap_hwmods to register 1590 * @ohs: pointer to an array of omap_hwmods to register
1590 * 1591 *
1591 * Intended to be called early in boot before the clock framework is 1592 * Intended to be called early in boot before the clock framework is
1592 * initialized. If @ohs is not null, will register all omap_hwmods 1593 * initialized. If @ohs is not null, will register all omap_hwmods
1593 * listed in @ohs that are valid for this chip. Returns -EINVAL if 1594 * listed in @ohs that are valid for this chip. Returns 0.
1594 * omap_hwmod_init() has already been called or 0 otherwise.
1595 */ 1595 */
1596int __init omap_hwmod_init(struct omap_hwmod **ohs) 1596int __init omap_hwmod_register(struct omap_hwmod **ohs)
1597{ 1597{
1598 struct omap_hwmod *oh; 1598 int r, i;
1599 int r;
1600
1601 if (inited)
1602 return -EINVAL;
1603
1604 inited = 1;
1605 1599
1606 if (!ohs) 1600 if (!ohs)
1607 return 0; 1601 return 0;
1608 1602
1609 oh = *ohs; 1603 i = 0;
1610 while (oh) { 1604 do {
1611 if (omap_chip_is(oh->omap_chip)) { 1605 if (!omap_chip_is(ohs[i]->omap_chip))
1612 r = _register(oh); 1606 continue;
1613 WARN(r, "omap_hwmod: %s: _register returned " 1607
1614 "%d\n", oh->name, r); 1608 r = _register(ohs[i]);
1615 } 1609 WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
1616 oh = *++ohs; 1610 r);
1617 } 1611 } while (ohs[++i]);
1618 1612
1619 return 0; 1613 return 0;
1620} 1614}
@@ -1622,12 +1616,14 @@ int __init omap_hwmod_init(struct omap_hwmod **ohs)
1622/* 1616/*
1623 * _populate_mpu_rt_base - populate the virtual address for a hwmod 1617 * _populate_mpu_rt_base - populate the virtual address for a hwmod
1624 * 1618 *
1625 * Must be called only from omap_hwmod_late_init so ioremap works properly. 1619 * Must be called only from omap_hwmod_setup_*() so ioremap works properly.
1626 * Assumes the caller takes care of locking if needed. 1620 * Assumes the caller takes care of locking if needed.
1627 *
1628 */ 1621 */
1629static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) 1622static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
1630{ 1623{
1624 if (oh->_state != _HWMOD_STATE_REGISTERED)
1625 return 0;
1626
1631 if (oh->_int_flags & _HWMOD_NO_MPU_PORT) 1627 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
1632 return 0; 1628 return 0;
1633 1629
@@ -1640,31 +1636,81 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
1640} 1636}
1641 1637
1642/** 1638/**
1643 * omap_hwmod_late_init - do some post-clock framework initialization 1639 * omap_hwmod_setup_one - set up a single hwmod
1640 * @oh_name: const char * name of the already-registered hwmod to set up
1641 *
1642 * Must be called after omap2_clk_init(). Resolves the struct clk
1643 * names to struct clk pointers for each registered omap_hwmod. Also
1644 * calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon
1645 * success.
1646 */
1647int __init omap_hwmod_setup_one(const char *oh_name)
1648{
1649 struct omap_hwmod *oh;
1650 int r;
1651
1652 pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
1653
1654 if (!mpu_oh) {
1655 pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n",
1656 oh_name, MPU_INITIATOR_NAME);
1657 return -EINVAL;
1658 }
1659
1660 oh = _lookup(oh_name);
1661 if (!oh) {
1662 WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
1663 return -EINVAL;
1664 }
1665
1666 if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
1667 omap_hwmod_setup_one(MPU_INITIATOR_NAME);
1668
1669 r = _populate_mpu_rt_base(oh, NULL);
1670 if (IS_ERR_VALUE(r)) {
1671 WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name);
1672 return -EINVAL;
1673 }
1674
1675 r = _init_clocks(oh, NULL);
1676 if (IS_ERR_VALUE(r)) {
1677 WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name);
1678 return -EINVAL;
1679 }
1680
1681 _setup(oh, NULL);
1682
1683 return 0;
1684}
1685
1686/**
1687 * omap_hwmod_setup - do some post-clock framework initialization
1644 * 1688 *
1645 * Must be called after omap2_clk_init(). Resolves the struct clk names 1689 * Must be called after omap2_clk_init(). Resolves the struct clk names
1646 * to struct clk pointers for each registered omap_hwmod. Also calls 1690 * to struct clk pointers for each registered omap_hwmod. Also calls
1647 * _setup() on each hwmod. Returns 0. 1691 * _setup() on each hwmod. Returns 0 upon success.
1648 */ 1692 */
1649static int __init omap_hwmod_late_init(void) 1693static int __init omap_hwmod_setup_all(void)
1650{ 1694{
1651 int r; 1695 int r;
1652 1696
1697 if (!mpu_oh) {
1698 pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
1699 __func__, MPU_INITIATOR_NAME);
1700 return -EINVAL;
1701 }
1702
1653 r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL); 1703 r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
1654 1704
1655 /* XXX check return value */
1656 r = omap_hwmod_for_each(_init_clocks, NULL); 1705 r = omap_hwmod_for_each(_init_clocks, NULL);
1657 WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n"); 1706 WARN(IS_ERR_VALUE(r),
1658 1707 "omap_hwmod: %s: _init_clocks failed\n", __func__);
1659 mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME);
1660 WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n",
1661 MPU_INITIATOR_NAME);
1662 1708
1663 omap_hwmod_for_each(_setup, NULL); 1709 omap_hwmod_for_each(_setup, NULL);
1664 1710
1665 return 0; 1711 return 0;
1666} 1712}
1667core_initcall(omap_hwmod_late_init); 1713core_initcall(omap_hwmod_setup_all);
1668 1714
1669/** 1715/**
1670 * omap_hwmod_enable - enable an omap_hwmod 1716 * omap_hwmod_enable - enable an omap_hwmod
@@ -2183,11 +2229,11 @@ int omap_hwmod_for_each_by_class(const char *classname,
2183 * @oh: struct omap_hwmod * 2229 * @oh: struct omap_hwmod *
2184 * @state: state that _setup() should leave the hwmod in 2230 * @state: state that _setup() should leave the hwmod in
2185 * 2231 *
2186 * Sets the hwmod state that @oh will enter at the end of _setup() (called by 2232 * Sets the hwmod state that @oh will enter at the end of _setup()
2187 * omap_hwmod_late_init()). Only valid to call between calls to 2233 * (called by omap_hwmod_setup_*()). Only valid to call between
2188 * omap_hwmod_init() and omap_hwmod_late_init(). Returns 0 upon success or 2234 * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns
2189 * -EINVAL if there is a problem with the arguments or if the hwmod is 2235 * 0 upon success or -EINVAL if there is a problem with the arguments
2190 * in the wrong state. 2236 * or if the hwmod is in the wrong state.
2191 */ 2237 */
2192int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) 2238int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
2193{ 2239{
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index f323c6bb22de..e58621aa9b34 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -19,6 +19,7 @@
19#include <plat/i2c.h> 19#include <plat/i2c.h>
20#include <plat/gpio.h> 20#include <plat/gpio.h>
21#include <plat/mcspi.h> 21#include <plat/mcspi.h>
22#include <plat/dmtimer.h>
22#include <plat/l3_2xxx.h> 23#include <plat/l3_2xxx.h>
23#include <plat/l4_2xxx.h> 24#include <plat/l4_2xxx.h>
24 25
@@ -337,6 +338,625 @@ static struct omap_hwmod omap2420_iva_hwmod = {
337 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 338 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
338}; 339};
339 340
341/* Timer Common */
342static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
343 .rev_offs = 0x0000,
344 .sysc_offs = 0x0010,
345 .syss_offs = 0x0014,
346 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
347 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
348 SYSC_HAS_AUTOIDLE),
349 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
350 .sysc_fields = &omap_hwmod_sysc_type1,
351};
352
353static struct omap_hwmod_class omap2420_timer_hwmod_class = {
354 .name = "timer",
355 .sysc = &omap2420_timer_sysc,
356 .rev = OMAP_TIMER_IP_VERSION_1,
357};
358
359/* timer1 */
360static struct omap_hwmod omap2420_timer1_hwmod;
361static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
362 { .irq = 37, },
363};
364
365static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
366 {
367 .pa_start = 0x48028000,
368 .pa_end = 0x48028000 + SZ_1K - 1,
369 .flags = ADDR_TYPE_RT
370 },
371};
372
373/* l4_wkup -> timer1 */
374static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
375 .master = &omap2420_l4_wkup_hwmod,
376 .slave = &omap2420_timer1_hwmod,
377 .clk = "gpt1_ick",
378 .addr = omap2420_timer1_addrs,
379 .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs),
380 .user = OCP_USER_MPU | OCP_USER_SDMA,
381};
382
383/* timer1 slave port */
384static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
385 &omap2420_l4_wkup__timer1,
386};
387
388/* timer1 hwmod */
389static struct omap_hwmod omap2420_timer1_hwmod = {
390 .name = "timer1",
391 .mpu_irqs = omap2420_timer1_mpu_irqs,
392 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
393 .main_clk = "gpt1_fck",
394 .prcm = {
395 .omap2 = {
396 .prcm_reg_id = 1,
397 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
398 .module_offs = WKUP_MOD,
399 .idlest_reg_id = 1,
400 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
401 },
402 },
403 .slaves = omap2420_timer1_slaves,
404 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
405 .class = &omap2420_timer_hwmod_class,
406 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
407};
408
409/* timer2 */
410static struct omap_hwmod omap2420_timer2_hwmod;
411static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
412 { .irq = 38, },
413};
414
415static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
416 {
417 .pa_start = 0x4802a000,
418 .pa_end = 0x4802a000 + SZ_1K - 1,
419 .flags = ADDR_TYPE_RT
420 },
421};
422
423/* l4_core -> timer2 */
424static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
425 .master = &omap2420_l4_core_hwmod,
426 .slave = &omap2420_timer2_hwmod,
427 .clk = "gpt2_ick",
428 .addr = omap2420_timer2_addrs,
429 .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs),
430 .user = OCP_USER_MPU | OCP_USER_SDMA,
431};
432
433/* timer2 slave port */
434static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
435 &omap2420_l4_core__timer2,
436};
437
438/* timer2 hwmod */
439static struct omap_hwmod omap2420_timer2_hwmod = {
440 .name = "timer2",
441 .mpu_irqs = omap2420_timer2_mpu_irqs,
442 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
443 .main_clk = "gpt2_fck",
444 .prcm = {
445 .omap2 = {
446 .prcm_reg_id = 1,
447 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
448 .module_offs = CORE_MOD,
449 .idlest_reg_id = 1,
450 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
451 },
452 },
453 .slaves = omap2420_timer2_slaves,
454 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
455 .class = &omap2420_timer_hwmod_class,
456 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
457};
458
459/* timer3 */
460static struct omap_hwmod omap2420_timer3_hwmod;
461static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
462 { .irq = 39, },
463};
464
465static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
466 {
467 .pa_start = 0x48078000,
468 .pa_end = 0x48078000 + SZ_1K - 1,
469 .flags = ADDR_TYPE_RT
470 },
471};
472
473/* l4_core -> timer3 */
474static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
475 .master = &omap2420_l4_core_hwmod,
476 .slave = &omap2420_timer3_hwmod,
477 .clk = "gpt3_ick",
478 .addr = omap2420_timer3_addrs,
479 .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs),
480 .user = OCP_USER_MPU | OCP_USER_SDMA,
481};
482
483/* timer3 slave port */
484static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
485 &omap2420_l4_core__timer3,
486};
487
488/* timer3 hwmod */
489static struct omap_hwmod omap2420_timer3_hwmod = {
490 .name = "timer3",
491 .mpu_irqs = omap2420_timer3_mpu_irqs,
492 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
493 .main_clk = "gpt3_fck",
494 .prcm = {
495 .omap2 = {
496 .prcm_reg_id = 1,
497 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
498 .module_offs = CORE_MOD,
499 .idlest_reg_id = 1,
500 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
501 },
502 },
503 .slaves = omap2420_timer3_slaves,
504 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
505 .class = &omap2420_timer_hwmod_class,
506 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
507};
508
509/* timer4 */
510static struct omap_hwmod omap2420_timer4_hwmod;
511static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
512 { .irq = 40, },
513};
514
515static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
516 {
517 .pa_start = 0x4807a000,
518 .pa_end = 0x4807a000 + SZ_1K - 1,
519 .flags = ADDR_TYPE_RT
520 },
521};
522
523/* l4_core -> timer4 */
524static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
525 .master = &omap2420_l4_core_hwmod,
526 .slave = &omap2420_timer4_hwmod,
527 .clk = "gpt4_ick",
528 .addr = omap2420_timer4_addrs,
529 .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs),
530 .user = OCP_USER_MPU | OCP_USER_SDMA,
531};
532
533/* timer4 slave port */
534static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
535 &omap2420_l4_core__timer4,
536};
537
538/* timer4 hwmod */
539static struct omap_hwmod omap2420_timer4_hwmod = {
540 .name = "timer4",
541 .mpu_irqs = omap2420_timer4_mpu_irqs,
542 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
543 .main_clk = "gpt4_fck",
544 .prcm = {
545 .omap2 = {
546 .prcm_reg_id = 1,
547 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
548 .module_offs = CORE_MOD,
549 .idlest_reg_id = 1,
550 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
551 },
552 },
553 .slaves = omap2420_timer4_slaves,
554 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
555 .class = &omap2420_timer_hwmod_class,
556 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
557};
558
559/* timer5 */
560static struct omap_hwmod omap2420_timer5_hwmod;
561static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
562 { .irq = 41, },
563};
564
565static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
566 {
567 .pa_start = 0x4807c000,
568 .pa_end = 0x4807c000 + SZ_1K - 1,
569 .flags = ADDR_TYPE_RT
570 },
571};
572
573/* l4_core -> timer5 */
574static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
575 .master = &omap2420_l4_core_hwmod,
576 .slave = &omap2420_timer5_hwmod,
577 .clk = "gpt5_ick",
578 .addr = omap2420_timer5_addrs,
579 .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs),
580 .user = OCP_USER_MPU | OCP_USER_SDMA,
581};
582
583/* timer5 slave port */
584static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
585 &omap2420_l4_core__timer5,
586};
587
588/* timer5 hwmod */
589static struct omap_hwmod omap2420_timer5_hwmod = {
590 .name = "timer5",
591 .mpu_irqs = omap2420_timer5_mpu_irqs,
592 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
593 .main_clk = "gpt5_fck",
594 .prcm = {
595 .omap2 = {
596 .prcm_reg_id = 1,
597 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
598 .module_offs = CORE_MOD,
599 .idlest_reg_id = 1,
600 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
601 },
602 },
603 .slaves = omap2420_timer5_slaves,
604 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
605 .class = &omap2420_timer_hwmod_class,
606 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
607};
608
609
610/* timer6 */
611static struct omap_hwmod omap2420_timer6_hwmod;
612static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
613 { .irq = 42, },
614};
615
616static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
617 {
618 .pa_start = 0x4807e000,
619 .pa_end = 0x4807e000 + SZ_1K - 1,
620 .flags = ADDR_TYPE_RT
621 },
622};
623
624/* l4_core -> timer6 */
625static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
626 .master = &omap2420_l4_core_hwmod,
627 .slave = &omap2420_timer6_hwmod,
628 .clk = "gpt6_ick",
629 .addr = omap2420_timer6_addrs,
630 .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs),
631 .user = OCP_USER_MPU | OCP_USER_SDMA,
632};
633
634/* timer6 slave port */
635static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
636 &omap2420_l4_core__timer6,
637};
638
639/* timer6 hwmod */
640static struct omap_hwmod omap2420_timer6_hwmod = {
641 .name = "timer6",
642 .mpu_irqs = omap2420_timer6_mpu_irqs,
643 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
644 .main_clk = "gpt6_fck",
645 .prcm = {
646 .omap2 = {
647 .prcm_reg_id = 1,
648 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
649 .module_offs = CORE_MOD,
650 .idlest_reg_id = 1,
651 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
652 },
653 },
654 .slaves = omap2420_timer6_slaves,
655 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
656 .class = &omap2420_timer_hwmod_class,
657 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
658};
659
660/* timer7 */
661static struct omap_hwmod omap2420_timer7_hwmod;
662static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
663 { .irq = 43, },
664};
665
666static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
667 {
668 .pa_start = 0x48080000,
669 .pa_end = 0x48080000 + SZ_1K - 1,
670 .flags = ADDR_TYPE_RT
671 },
672};
673
674/* l4_core -> timer7 */
675static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
676 .master = &omap2420_l4_core_hwmod,
677 .slave = &omap2420_timer7_hwmod,
678 .clk = "gpt7_ick",
679 .addr = omap2420_timer7_addrs,
680 .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs),
681 .user = OCP_USER_MPU | OCP_USER_SDMA,
682};
683
684/* timer7 slave port */
685static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
686 &omap2420_l4_core__timer7,
687};
688
689/* timer7 hwmod */
690static struct omap_hwmod omap2420_timer7_hwmod = {
691 .name = "timer7",
692 .mpu_irqs = omap2420_timer7_mpu_irqs,
693 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
694 .main_clk = "gpt7_fck",
695 .prcm = {
696 .omap2 = {
697 .prcm_reg_id = 1,
698 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
699 .module_offs = CORE_MOD,
700 .idlest_reg_id = 1,
701 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
702 },
703 },
704 .slaves = omap2420_timer7_slaves,
705 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
706 .class = &omap2420_timer_hwmod_class,
707 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
708};
709
710/* timer8 */
711static struct omap_hwmod omap2420_timer8_hwmod;
712static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
713 { .irq = 44, },
714};
715
716static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
717 {
718 .pa_start = 0x48082000,
719 .pa_end = 0x48082000 + SZ_1K - 1,
720 .flags = ADDR_TYPE_RT
721 },
722};
723
724/* l4_core -> timer8 */
725static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
726 .master = &omap2420_l4_core_hwmod,
727 .slave = &omap2420_timer8_hwmod,
728 .clk = "gpt8_ick",
729 .addr = omap2420_timer8_addrs,
730 .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs),
731 .user = OCP_USER_MPU | OCP_USER_SDMA,
732};
733
734/* timer8 slave port */
735static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
736 &omap2420_l4_core__timer8,
737};
738
739/* timer8 hwmod */
740static struct omap_hwmod omap2420_timer8_hwmod = {
741 .name = "timer8",
742 .mpu_irqs = omap2420_timer8_mpu_irqs,
743 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
744 .main_clk = "gpt8_fck",
745 .prcm = {
746 .omap2 = {
747 .prcm_reg_id = 1,
748 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
749 .module_offs = CORE_MOD,
750 .idlest_reg_id = 1,
751 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
752 },
753 },
754 .slaves = omap2420_timer8_slaves,
755 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
756 .class = &omap2420_timer_hwmod_class,
757 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
758};
759
760/* timer9 */
761static struct omap_hwmod omap2420_timer9_hwmod;
762static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
763 { .irq = 45, },
764};
765
766static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
767 {
768 .pa_start = 0x48084000,
769 .pa_end = 0x48084000 + SZ_1K - 1,
770 .flags = ADDR_TYPE_RT
771 },
772};
773
774/* l4_core -> timer9 */
775static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
776 .master = &omap2420_l4_core_hwmod,
777 .slave = &omap2420_timer9_hwmod,
778 .clk = "gpt9_ick",
779 .addr = omap2420_timer9_addrs,
780 .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs),
781 .user = OCP_USER_MPU | OCP_USER_SDMA,
782};
783
784/* timer9 slave port */
785static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
786 &omap2420_l4_core__timer9,
787};
788
789/* timer9 hwmod */
790static struct omap_hwmod omap2420_timer9_hwmod = {
791 .name = "timer9",
792 .mpu_irqs = omap2420_timer9_mpu_irqs,
793 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
794 .main_clk = "gpt9_fck",
795 .prcm = {
796 .omap2 = {
797 .prcm_reg_id = 1,
798 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
799 .module_offs = CORE_MOD,
800 .idlest_reg_id = 1,
801 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
802 },
803 },
804 .slaves = omap2420_timer9_slaves,
805 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
806 .class = &omap2420_timer_hwmod_class,
807 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
808};
809
810/* timer10 */
811static struct omap_hwmod omap2420_timer10_hwmod;
812static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
813 { .irq = 46, },
814};
815
816static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
817 {
818 .pa_start = 0x48086000,
819 .pa_end = 0x48086000 + SZ_1K - 1,
820 .flags = ADDR_TYPE_RT
821 },
822};
823
824/* l4_core -> timer10 */
825static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
826 .master = &omap2420_l4_core_hwmod,
827 .slave = &omap2420_timer10_hwmod,
828 .clk = "gpt10_ick",
829 .addr = omap2420_timer10_addrs,
830 .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs),
831 .user = OCP_USER_MPU | OCP_USER_SDMA,
832};
833
834/* timer10 slave port */
835static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
836 &omap2420_l4_core__timer10,
837};
838
839/* timer10 hwmod */
840static struct omap_hwmod omap2420_timer10_hwmod = {
841 .name = "timer10",
842 .mpu_irqs = omap2420_timer10_mpu_irqs,
843 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
844 .main_clk = "gpt10_fck",
845 .prcm = {
846 .omap2 = {
847 .prcm_reg_id = 1,
848 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
849 .module_offs = CORE_MOD,
850 .idlest_reg_id = 1,
851 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
852 },
853 },
854 .slaves = omap2420_timer10_slaves,
855 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
856 .class = &omap2420_timer_hwmod_class,
857 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
858};
859
860/* timer11 */
861static struct omap_hwmod omap2420_timer11_hwmod;
862static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
863 { .irq = 47, },
864};
865
866static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
867 {
868 .pa_start = 0x48088000,
869 .pa_end = 0x48088000 + SZ_1K - 1,
870 .flags = ADDR_TYPE_RT
871 },
872};
873
874/* l4_core -> timer11 */
875static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
876 .master = &omap2420_l4_core_hwmod,
877 .slave = &omap2420_timer11_hwmod,
878 .clk = "gpt11_ick",
879 .addr = omap2420_timer11_addrs,
880 .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs),
881 .user = OCP_USER_MPU | OCP_USER_SDMA,
882};
883
884/* timer11 slave port */
885static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
886 &omap2420_l4_core__timer11,
887};
888
889/* timer11 hwmod */
890static struct omap_hwmod omap2420_timer11_hwmod = {
891 .name = "timer11",
892 .mpu_irqs = omap2420_timer11_mpu_irqs,
893 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
894 .main_clk = "gpt11_fck",
895 .prcm = {
896 .omap2 = {
897 .prcm_reg_id = 1,
898 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
899 .module_offs = CORE_MOD,
900 .idlest_reg_id = 1,
901 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
902 },
903 },
904 .slaves = omap2420_timer11_slaves,
905 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
906 .class = &omap2420_timer_hwmod_class,
907 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
908};
909
910/* timer12 */
911static struct omap_hwmod omap2420_timer12_hwmod;
912static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
913 { .irq = 48, },
914};
915
916static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
917 {
918 .pa_start = 0x4808a000,
919 .pa_end = 0x4808a000 + SZ_1K - 1,
920 .flags = ADDR_TYPE_RT
921 },
922};
923
924/* l4_core -> timer12 */
925static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
926 .master = &omap2420_l4_core_hwmod,
927 .slave = &omap2420_timer12_hwmod,
928 .clk = "gpt12_ick",
929 .addr = omap2420_timer12_addrs,
930 .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs),
931 .user = OCP_USER_MPU | OCP_USER_SDMA,
932};
933
934/* timer12 slave port */
935static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
936 &omap2420_l4_core__timer12,
937};
938
939/* timer12 hwmod */
940static struct omap_hwmod omap2420_timer12_hwmod = {
941 .name = "timer12",
942 .mpu_irqs = omap2420_timer12_mpu_irqs,
943 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
944 .main_clk = "gpt12_fck",
945 .prcm = {
946 .omap2 = {
947 .prcm_reg_id = 1,
948 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
949 .module_offs = CORE_MOD,
950 .idlest_reg_id = 1,
951 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
952 },
953 },
954 .slaves = omap2420_timer12_slaves,
955 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
956 .class = &omap2420_timer_hwmod_class,
957 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
958};
959
340/* l4_wkup -> wd_timer2 */ 960/* l4_wkup -> wd_timer2 */
341static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { 961static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
342 { 962 {
@@ -1326,6 +1946,20 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1326 &omap2420_l4_wkup_hwmod, 1946 &omap2420_l4_wkup_hwmod,
1327 &omap2420_mpu_hwmod, 1947 &omap2420_mpu_hwmod,
1328 &omap2420_iva_hwmod, 1948 &omap2420_iva_hwmod,
1949
1950 &omap2420_timer1_hwmod,
1951 &omap2420_timer2_hwmod,
1952 &omap2420_timer3_hwmod,
1953 &omap2420_timer4_hwmod,
1954 &omap2420_timer5_hwmod,
1955 &omap2420_timer6_hwmod,
1956 &omap2420_timer7_hwmod,
1957 &omap2420_timer8_hwmod,
1958 &omap2420_timer9_hwmod,
1959 &omap2420_timer10_hwmod,
1960 &omap2420_timer11_hwmod,
1961 &omap2420_timer12_hwmod,
1962
1329 &omap2420_wd_timer2_hwmod, 1963 &omap2420_wd_timer2_hwmod,
1330 &omap2420_uart1_hwmod, 1964 &omap2420_uart1_hwmod,
1331 &omap2420_uart2_hwmod, 1965 &omap2420_uart2_hwmod,
@@ -1356,5 +1990,5 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1356 1990
1357int __init omap2420_hwmod_init(void) 1991int __init omap2420_hwmod_init(void)
1358{ 1992{
1359 return omap_hwmod_init(omap2420_hwmods); 1993 return omap_hwmod_register(omap2420_hwmods);
1360} 1994}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index de0015d38433..b46a54ce1a41 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -19,6 +19,7 @@
19#include <plat/i2c.h> 19#include <plat/i2c.h>
20#include <plat/gpio.h> 20#include <plat/gpio.h>
21#include <plat/mcspi.h> 21#include <plat/mcspi.h>
22#include <plat/dmtimer.h>
22#include <plat/l3_2xxx.h> 23#include <plat/l3_2xxx.h>
23 24
24#include "omap_hwmod_common_data.h" 25#include "omap_hwmod_common_data.h"
@@ -393,6 +394,624 @@ static struct omap_hwmod omap2430_iva_hwmod = {
393 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 394 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
394}; 395};
395 396
397/* Timer Common */
398static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
399 .rev_offs = 0x0000,
400 .sysc_offs = 0x0010,
401 .syss_offs = 0x0014,
402 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
403 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
404 SYSC_HAS_AUTOIDLE),
405 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
406 .sysc_fields = &omap_hwmod_sysc_type1,
407};
408
409static struct omap_hwmod_class omap2430_timer_hwmod_class = {
410 .name = "timer",
411 .sysc = &omap2430_timer_sysc,
412 .rev = OMAP_TIMER_IP_VERSION_1,
413};
414
415/* timer1 */
416static struct omap_hwmod omap2430_timer1_hwmod;
417static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
418 { .irq = 37, },
419};
420
421static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
422 {
423 .pa_start = 0x49018000,
424 .pa_end = 0x49018000 + SZ_1K - 1,
425 .flags = ADDR_TYPE_RT
426 },
427};
428
429/* l4_wkup -> timer1 */
430static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
431 .master = &omap2430_l4_wkup_hwmod,
432 .slave = &omap2430_timer1_hwmod,
433 .clk = "gpt1_ick",
434 .addr = omap2430_timer1_addrs,
435 .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs),
436 .user = OCP_USER_MPU | OCP_USER_SDMA,
437};
438
439/* timer1 slave port */
440static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
441 &omap2430_l4_wkup__timer1,
442};
443
444/* timer1 hwmod */
445static struct omap_hwmod omap2430_timer1_hwmod = {
446 .name = "timer1",
447 .mpu_irqs = omap2430_timer1_mpu_irqs,
448 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
449 .main_clk = "gpt1_fck",
450 .prcm = {
451 .omap2 = {
452 .prcm_reg_id = 1,
453 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
454 .module_offs = WKUP_MOD,
455 .idlest_reg_id = 1,
456 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
457 },
458 },
459 .slaves = omap2430_timer1_slaves,
460 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
461 .class = &omap2430_timer_hwmod_class,
462 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
463};
464
465/* timer2 */
466static struct omap_hwmod omap2430_timer2_hwmod;
467static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
468 { .irq = 38, },
469};
470
471static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
472 {
473 .pa_start = 0x4802a000,
474 .pa_end = 0x4802a000 + SZ_1K - 1,
475 .flags = ADDR_TYPE_RT
476 },
477};
478
479/* l4_core -> timer2 */
480static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
481 .master = &omap2430_l4_core_hwmod,
482 .slave = &omap2430_timer2_hwmod,
483 .clk = "gpt2_ick",
484 .addr = omap2430_timer2_addrs,
485 .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs),
486 .user = OCP_USER_MPU | OCP_USER_SDMA,
487};
488
489/* timer2 slave port */
490static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
491 &omap2430_l4_core__timer2,
492};
493
494/* timer2 hwmod */
495static struct omap_hwmod omap2430_timer2_hwmod = {
496 .name = "timer2",
497 .mpu_irqs = omap2430_timer2_mpu_irqs,
498 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
499 .main_clk = "gpt2_fck",
500 .prcm = {
501 .omap2 = {
502 .prcm_reg_id = 1,
503 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
504 .module_offs = CORE_MOD,
505 .idlest_reg_id = 1,
506 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
507 },
508 },
509 .slaves = omap2430_timer2_slaves,
510 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
511 .class = &omap2430_timer_hwmod_class,
512 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
513};
514
515/* timer3 */
516static struct omap_hwmod omap2430_timer3_hwmod;
517static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
518 { .irq = 39, },
519};
520
521static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
522 {
523 .pa_start = 0x48078000,
524 .pa_end = 0x48078000 + SZ_1K - 1,
525 .flags = ADDR_TYPE_RT
526 },
527};
528
529/* l4_core -> timer3 */
530static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
531 .master = &omap2430_l4_core_hwmod,
532 .slave = &omap2430_timer3_hwmod,
533 .clk = "gpt3_ick",
534 .addr = omap2430_timer3_addrs,
535 .addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs),
536 .user = OCP_USER_MPU | OCP_USER_SDMA,
537};
538
539/* timer3 slave port */
540static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
541 &omap2430_l4_core__timer3,
542};
543
544/* timer3 hwmod */
545static struct omap_hwmod omap2430_timer3_hwmod = {
546 .name = "timer3",
547 .mpu_irqs = omap2430_timer3_mpu_irqs,
548 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
549 .main_clk = "gpt3_fck",
550 .prcm = {
551 .omap2 = {
552 .prcm_reg_id = 1,
553 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
554 .module_offs = CORE_MOD,
555 .idlest_reg_id = 1,
556 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
557 },
558 },
559 .slaves = omap2430_timer3_slaves,
560 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
561 .class = &omap2430_timer_hwmod_class,
562 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
563};
564
565/* timer4 */
566static struct omap_hwmod omap2430_timer4_hwmod;
567static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
568 { .irq = 40, },
569};
570
571static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
572 {
573 .pa_start = 0x4807a000,
574 .pa_end = 0x4807a000 + SZ_1K - 1,
575 .flags = ADDR_TYPE_RT
576 },
577};
578
579/* l4_core -> timer4 */
580static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
581 .master = &omap2430_l4_core_hwmod,
582 .slave = &omap2430_timer4_hwmod,
583 .clk = "gpt4_ick",
584 .addr = omap2430_timer4_addrs,
585 .addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs),
586 .user = OCP_USER_MPU | OCP_USER_SDMA,
587};
588
589/* timer4 slave port */
590static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
591 &omap2430_l4_core__timer4,
592};
593
594/* timer4 hwmod */
595static struct omap_hwmod omap2430_timer4_hwmod = {
596 .name = "timer4",
597 .mpu_irqs = omap2430_timer4_mpu_irqs,
598 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
599 .main_clk = "gpt4_fck",
600 .prcm = {
601 .omap2 = {
602 .prcm_reg_id = 1,
603 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
604 .module_offs = CORE_MOD,
605 .idlest_reg_id = 1,
606 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
607 },
608 },
609 .slaves = omap2430_timer4_slaves,
610 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
611 .class = &omap2430_timer_hwmod_class,
612 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
613};
614
615/* timer5 */
616static struct omap_hwmod omap2430_timer5_hwmod;
617static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
618 { .irq = 41, },
619};
620
621static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
622 {
623 .pa_start = 0x4807c000,
624 .pa_end = 0x4807c000 + SZ_1K - 1,
625 .flags = ADDR_TYPE_RT
626 },
627};
628
629/* l4_core -> timer5 */
630static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
631 .master = &omap2430_l4_core_hwmod,
632 .slave = &omap2430_timer5_hwmod,
633 .clk = "gpt5_ick",
634 .addr = omap2430_timer5_addrs,
635 .addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs),
636 .user = OCP_USER_MPU | OCP_USER_SDMA,
637};
638
639/* timer5 slave port */
640static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
641 &omap2430_l4_core__timer5,
642};
643
644/* timer5 hwmod */
645static struct omap_hwmod omap2430_timer5_hwmod = {
646 .name = "timer5",
647 .mpu_irqs = omap2430_timer5_mpu_irqs,
648 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
649 .main_clk = "gpt5_fck",
650 .prcm = {
651 .omap2 = {
652 .prcm_reg_id = 1,
653 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
654 .module_offs = CORE_MOD,
655 .idlest_reg_id = 1,
656 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
657 },
658 },
659 .slaves = omap2430_timer5_slaves,
660 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
661 .class = &omap2430_timer_hwmod_class,
662 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
663};
664
665/* timer6 */
666static struct omap_hwmod omap2430_timer6_hwmod;
667static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
668 { .irq = 42, },
669};
670
671static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
672 {
673 .pa_start = 0x4807e000,
674 .pa_end = 0x4807e000 + SZ_1K - 1,
675 .flags = ADDR_TYPE_RT
676 },
677};
678
679/* l4_core -> timer6 */
680static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
681 .master = &omap2430_l4_core_hwmod,
682 .slave = &omap2430_timer6_hwmod,
683 .clk = "gpt6_ick",
684 .addr = omap2430_timer6_addrs,
685 .addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs),
686 .user = OCP_USER_MPU | OCP_USER_SDMA,
687};
688
689/* timer6 slave port */
690static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
691 &omap2430_l4_core__timer6,
692};
693
694/* timer6 hwmod */
695static struct omap_hwmod omap2430_timer6_hwmod = {
696 .name = "timer6",
697 .mpu_irqs = omap2430_timer6_mpu_irqs,
698 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
699 .main_clk = "gpt6_fck",
700 .prcm = {
701 .omap2 = {
702 .prcm_reg_id = 1,
703 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
704 .module_offs = CORE_MOD,
705 .idlest_reg_id = 1,
706 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
707 },
708 },
709 .slaves = omap2430_timer6_slaves,
710 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
711 .class = &omap2430_timer_hwmod_class,
712 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
713};
714
715/* timer7 */
716static struct omap_hwmod omap2430_timer7_hwmod;
717static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
718 { .irq = 43, },
719};
720
721static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
722 {
723 .pa_start = 0x48080000,
724 .pa_end = 0x48080000 + SZ_1K - 1,
725 .flags = ADDR_TYPE_RT
726 },
727};
728
729/* l4_core -> timer7 */
730static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
731 .master = &omap2430_l4_core_hwmod,
732 .slave = &omap2430_timer7_hwmod,
733 .clk = "gpt7_ick",
734 .addr = omap2430_timer7_addrs,
735 .addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs),
736 .user = OCP_USER_MPU | OCP_USER_SDMA,
737};
738
739/* timer7 slave port */
740static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
741 &omap2430_l4_core__timer7,
742};
743
744/* timer7 hwmod */
745static struct omap_hwmod omap2430_timer7_hwmod = {
746 .name = "timer7",
747 .mpu_irqs = omap2430_timer7_mpu_irqs,
748 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
749 .main_clk = "gpt7_fck",
750 .prcm = {
751 .omap2 = {
752 .prcm_reg_id = 1,
753 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
754 .module_offs = CORE_MOD,
755 .idlest_reg_id = 1,
756 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
757 },
758 },
759 .slaves = omap2430_timer7_slaves,
760 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
761 .class = &omap2430_timer_hwmod_class,
762 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
763};
764
765/* timer8 */
766static struct omap_hwmod omap2430_timer8_hwmod;
767static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
768 { .irq = 44, },
769};
770
771static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
772 {
773 .pa_start = 0x48082000,
774 .pa_end = 0x48082000 + SZ_1K - 1,
775 .flags = ADDR_TYPE_RT
776 },
777};
778
779/* l4_core -> timer8 */
780static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
781 .master = &omap2430_l4_core_hwmod,
782 .slave = &omap2430_timer8_hwmod,
783 .clk = "gpt8_ick",
784 .addr = omap2430_timer8_addrs,
785 .addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs),
786 .user = OCP_USER_MPU | OCP_USER_SDMA,
787};
788
789/* timer8 slave port */
790static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
791 &omap2430_l4_core__timer8,
792};
793
794/* timer8 hwmod */
795static struct omap_hwmod omap2430_timer8_hwmod = {
796 .name = "timer8",
797 .mpu_irqs = omap2430_timer8_mpu_irqs,
798 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
799 .main_clk = "gpt8_fck",
800 .prcm = {
801 .omap2 = {
802 .prcm_reg_id = 1,
803 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
804 .module_offs = CORE_MOD,
805 .idlest_reg_id = 1,
806 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
807 },
808 },
809 .slaves = omap2430_timer8_slaves,
810 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
811 .class = &omap2430_timer_hwmod_class,
812 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
813};
814
815/* timer9 */
816static struct omap_hwmod omap2430_timer9_hwmod;
817static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
818 { .irq = 45, },
819};
820
821static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
822 {
823 .pa_start = 0x48084000,
824 .pa_end = 0x48084000 + SZ_1K - 1,
825 .flags = ADDR_TYPE_RT
826 },
827};
828
829/* l4_core -> timer9 */
830static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
831 .master = &omap2430_l4_core_hwmod,
832 .slave = &omap2430_timer9_hwmod,
833 .clk = "gpt9_ick",
834 .addr = omap2430_timer9_addrs,
835 .addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs),
836 .user = OCP_USER_MPU | OCP_USER_SDMA,
837};
838
839/* timer9 slave port */
840static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
841 &omap2430_l4_core__timer9,
842};
843
844/* timer9 hwmod */
845static struct omap_hwmod omap2430_timer9_hwmod = {
846 .name = "timer9",
847 .mpu_irqs = omap2430_timer9_mpu_irqs,
848 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
849 .main_clk = "gpt9_fck",
850 .prcm = {
851 .omap2 = {
852 .prcm_reg_id = 1,
853 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
854 .module_offs = CORE_MOD,
855 .idlest_reg_id = 1,
856 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
857 },
858 },
859 .slaves = omap2430_timer9_slaves,
860 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
861 .class = &omap2430_timer_hwmod_class,
862 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
863};
864
865/* timer10 */
866static struct omap_hwmod omap2430_timer10_hwmod;
867static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
868 { .irq = 46, },
869};
870
871static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
872 {
873 .pa_start = 0x48086000,
874 .pa_end = 0x48086000 + SZ_1K - 1,
875 .flags = ADDR_TYPE_RT
876 },
877};
878
879/* l4_core -> timer10 */
880static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
881 .master = &omap2430_l4_core_hwmod,
882 .slave = &omap2430_timer10_hwmod,
883 .clk = "gpt10_ick",
884 .addr = omap2430_timer10_addrs,
885 .addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs),
886 .user = OCP_USER_MPU | OCP_USER_SDMA,
887};
888
889/* timer10 slave port */
890static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
891 &omap2430_l4_core__timer10,
892};
893
894/* timer10 hwmod */
895static struct omap_hwmod omap2430_timer10_hwmod = {
896 .name = "timer10",
897 .mpu_irqs = omap2430_timer10_mpu_irqs,
898 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
899 .main_clk = "gpt10_fck",
900 .prcm = {
901 .omap2 = {
902 .prcm_reg_id = 1,
903 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
904 .module_offs = CORE_MOD,
905 .idlest_reg_id = 1,
906 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
907 },
908 },
909 .slaves = omap2430_timer10_slaves,
910 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
911 .class = &omap2430_timer_hwmod_class,
912 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
913};
914
915/* timer11 */
916static struct omap_hwmod omap2430_timer11_hwmod;
917static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
918 { .irq = 47, },
919};
920
921static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
922 {
923 .pa_start = 0x48088000,
924 .pa_end = 0x48088000 + SZ_1K - 1,
925 .flags = ADDR_TYPE_RT
926 },
927};
928
929/* l4_core -> timer11 */
930static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
931 .master = &omap2430_l4_core_hwmod,
932 .slave = &omap2430_timer11_hwmod,
933 .clk = "gpt11_ick",
934 .addr = omap2430_timer11_addrs,
935 .addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs),
936 .user = OCP_USER_MPU | OCP_USER_SDMA,
937};
938
939/* timer11 slave port */
940static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
941 &omap2430_l4_core__timer11,
942};
943
944/* timer11 hwmod */
945static struct omap_hwmod omap2430_timer11_hwmod = {
946 .name = "timer11",
947 .mpu_irqs = omap2430_timer11_mpu_irqs,
948 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
949 .main_clk = "gpt11_fck",
950 .prcm = {
951 .omap2 = {
952 .prcm_reg_id = 1,
953 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
954 .module_offs = CORE_MOD,
955 .idlest_reg_id = 1,
956 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
957 },
958 },
959 .slaves = omap2430_timer11_slaves,
960 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
961 .class = &omap2430_timer_hwmod_class,
962 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
963};
964
965/* timer12 */
966static struct omap_hwmod omap2430_timer12_hwmod;
967static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
968 { .irq = 48, },
969};
970
971static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
972 {
973 .pa_start = 0x4808a000,
974 .pa_end = 0x4808a000 + SZ_1K - 1,
975 .flags = ADDR_TYPE_RT
976 },
977};
978
979/* l4_core -> timer12 */
980static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
981 .master = &omap2430_l4_core_hwmod,
982 .slave = &omap2430_timer12_hwmod,
983 .clk = "gpt12_ick",
984 .addr = omap2430_timer12_addrs,
985 .addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs),
986 .user = OCP_USER_MPU | OCP_USER_SDMA,
987};
988
989/* timer12 slave port */
990static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
991 &omap2430_l4_core__timer12,
992};
993
994/* timer12 hwmod */
995static struct omap_hwmod omap2430_timer12_hwmod = {
996 .name = "timer12",
997 .mpu_irqs = omap2430_timer12_mpu_irqs,
998 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
999 .main_clk = "gpt12_fck",
1000 .prcm = {
1001 .omap2 = {
1002 .prcm_reg_id = 1,
1003 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
1004 .module_offs = CORE_MOD,
1005 .idlest_reg_id = 1,
1006 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
1007 },
1008 },
1009 .slaves = omap2430_timer12_slaves,
1010 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
1011 .class = &omap2430_timer_hwmod_class,
1012 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1013};
1014
396/* l4_wkup -> wd_timer2 */ 1015/* l4_wkup -> wd_timer2 */
397static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { 1016static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
398 { 1017 {
@@ -1514,6 +2133,20 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
1514 &omap2430_l4_wkup_hwmod, 2133 &omap2430_l4_wkup_hwmod,
1515 &omap2430_mpu_hwmod, 2134 &omap2430_mpu_hwmod,
1516 &omap2430_iva_hwmod, 2135 &omap2430_iva_hwmod,
2136
2137 &omap2430_timer1_hwmod,
2138 &omap2430_timer2_hwmod,
2139 &omap2430_timer3_hwmod,
2140 &omap2430_timer4_hwmod,
2141 &omap2430_timer5_hwmod,
2142 &omap2430_timer6_hwmod,
2143 &omap2430_timer7_hwmod,
2144 &omap2430_timer8_hwmod,
2145 &omap2430_timer9_hwmod,
2146 &omap2430_timer10_hwmod,
2147 &omap2430_timer11_hwmod,
2148 &omap2430_timer12_hwmod,
2149
1517 &omap2430_wd_timer2_hwmod, 2150 &omap2430_wd_timer2_hwmod,
1518 &omap2430_uart1_hwmod, 2151 &omap2430_uart1_hwmod,
1519 &omap2430_uart2_hwmod, 2152 &omap2430_uart2_hwmod,
@@ -1550,5 +2183,5 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
1550 2183
1551int __init omap2430_hwmod_init(void) 2184int __init omap2430_hwmod_init(void)
1552{ 2185{
1553 return omap_hwmod_init(omap2430_hwmods); 2186 return omap_hwmod_register(omap2430_hwmods);
1554} 2187}
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index e9d001228568..fc1b2b963bb9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -24,6 +24,7 @@
24#include <plat/gpio.h> 24#include <plat/gpio.h>
25#include <plat/smartreflex.h> 25#include <plat/smartreflex.h>
26#include <plat/mcspi.h> 26#include <plat/mcspi.h>
27#include <plat/dmtimer.h>
27 28
28#include "omap_hwmod_common_data.h" 29#include "omap_hwmod_common_data.h"
29 30
@@ -515,6 +516,640 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
515 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) 516 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
516}; 517};
517 518
519/* timer class */
520static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
521 .rev_offs = 0x0000,
522 .sysc_offs = 0x0010,
523 .syss_offs = 0x0014,
524 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
525 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
526 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
527 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
528 .sysc_fields = &omap_hwmod_sysc_type1,
529};
530
531static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
532 .name = "timer",
533 .sysc = &omap3xxx_timer_1ms_sysc,
534 .rev = OMAP_TIMER_IP_VERSION_1,
535};
536
537static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
538 .rev_offs = 0x0000,
539 .sysc_offs = 0x0010,
540 .syss_offs = 0x0014,
541 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
542 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
543 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
544 .sysc_fields = &omap_hwmod_sysc_type1,
545};
546
547static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
548 .name = "timer",
549 .sysc = &omap3xxx_timer_sysc,
550 .rev = OMAP_TIMER_IP_VERSION_1,
551};
552
553/* timer1 */
554static struct omap_hwmod omap3xxx_timer1_hwmod;
555static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
556 { .irq = 37, },
557};
558
559static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
560 {
561 .pa_start = 0x48318000,
562 .pa_end = 0x48318000 + SZ_1K - 1,
563 .flags = ADDR_TYPE_RT
564 },
565};
566
567/* l4_wkup -> timer1 */
568static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
569 .master = &omap3xxx_l4_wkup_hwmod,
570 .slave = &omap3xxx_timer1_hwmod,
571 .clk = "gpt1_ick",
572 .addr = omap3xxx_timer1_addrs,
573 .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
574 .user = OCP_USER_MPU | OCP_USER_SDMA,
575};
576
577/* timer1 slave port */
578static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
579 &omap3xxx_l4_wkup__timer1,
580};
581
582/* timer1 hwmod */
583static struct omap_hwmod omap3xxx_timer1_hwmod = {
584 .name = "timer1",
585 .mpu_irqs = omap3xxx_timer1_mpu_irqs,
586 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
587 .main_clk = "gpt1_fck",
588 .prcm = {
589 .omap2 = {
590 .prcm_reg_id = 1,
591 .module_bit = OMAP3430_EN_GPT1_SHIFT,
592 .module_offs = WKUP_MOD,
593 .idlest_reg_id = 1,
594 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
595 },
596 },
597 .slaves = omap3xxx_timer1_slaves,
598 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
599 .class = &omap3xxx_timer_1ms_hwmod_class,
600 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
601};
602
603/* timer2 */
604static struct omap_hwmod omap3xxx_timer2_hwmod;
605static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
606 { .irq = 38, },
607};
608
609static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
610 {
611 .pa_start = 0x49032000,
612 .pa_end = 0x49032000 + SZ_1K - 1,
613 .flags = ADDR_TYPE_RT
614 },
615};
616
617/* l4_per -> timer2 */
618static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
619 .master = &omap3xxx_l4_per_hwmod,
620 .slave = &omap3xxx_timer2_hwmod,
621 .clk = "gpt2_ick",
622 .addr = omap3xxx_timer2_addrs,
623 .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
624 .user = OCP_USER_MPU | OCP_USER_SDMA,
625};
626
627/* timer2 slave port */
628static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
629 &omap3xxx_l4_per__timer2,
630};
631
632/* timer2 hwmod */
633static struct omap_hwmod omap3xxx_timer2_hwmod = {
634 .name = "timer2",
635 .mpu_irqs = omap3xxx_timer2_mpu_irqs,
636 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
637 .main_clk = "gpt2_fck",
638 .prcm = {
639 .omap2 = {
640 .prcm_reg_id = 1,
641 .module_bit = OMAP3430_EN_GPT2_SHIFT,
642 .module_offs = OMAP3430_PER_MOD,
643 .idlest_reg_id = 1,
644 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
645 },
646 },
647 .slaves = omap3xxx_timer2_slaves,
648 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
649 .class = &omap3xxx_timer_1ms_hwmod_class,
650 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
651};
652
653/* timer3 */
654static struct omap_hwmod omap3xxx_timer3_hwmod;
655static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
656 { .irq = 39, },
657};
658
659static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
660 {
661 .pa_start = 0x49034000,
662 .pa_end = 0x49034000 + SZ_1K - 1,
663 .flags = ADDR_TYPE_RT
664 },
665};
666
667/* l4_per -> timer3 */
668static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
669 .master = &omap3xxx_l4_per_hwmod,
670 .slave = &omap3xxx_timer3_hwmod,
671 .clk = "gpt3_ick",
672 .addr = omap3xxx_timer3_addrs,
673 .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
674 .user = OCP_USER_MPU | OCP_USER_SDMA,
675};
676
677/* timer3 slave port */
678static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
679 &omap3xxx_l4_per__timer3,
680};
681
682/* timer3 hwmod */
683static struct omap_hwmod omap3xxx_timer3_hwmod = {
684 .name = "timer3",
685 .mpu_irqs = omap3xxx_timer3_mpu_irqs,
686 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
687 .main_clk = "gpt3_fck",
688 .prcm = {
689 .omap2 = {
690 .prcm_reg_id = 1,
691 .module_bit = OMAP3430_EN_GPT3_SHIFT,
692 .module_offs = OMAP3430_PER_MOD,
693 .idlest_reg_id = 1,
694 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
695 },
696 },
697 .slaves = omap3xxx_timer3_slaves,
698 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
699 .class = &omap3xxx_timer_hwmod_class,
700 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
701};
702
703/* timer4 */
704static struct omap_hwmod omap3xxx_timer4_hwmod;
705static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
706 { .irq = 40, },
707};
708
709static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
710 {
711 .pa_start = 0x49036000,
712 .pa_end = 0x49036000 + SZ_1K - 1,
713 .flags = ADDR_TYPE_RT
714 },
715};
716
717/* l4_per -> timer4 */
718static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
719 .master = &omap3xxx_l4_per_hwmod,
720 .slave = &omap3xxx_timer4_hwmod,
721 .clk = "gpt4_ick",
722 .addr = omap3xxx_timer4_addrs,
723 .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
724 .user = OCP_USER_MPU | OCP_USER_SDMA,
725};
726
727/* timer4 slave port */
728static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
729 &omap3xxx_l4_per__timer4,
730};
731
732/* timer4 hwmod */
733static struct omap_hwmod omap3xxx_timer4_hwmod = {
734 .name = "timer4",
735 .mpu_irqs = omap3xxx_timer4_mpu_irqs,
736 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
737 .main_clk = "gpt4_fck",
738 .prcm = {
739 .omap2 = {
740 .prcm_reg_id = 1,
741 .module_bit = OMAP3430_EN_GPT4_SHIFT,
742 .module_offs = OMAP3430_PER_MOD,
743 .idlest_reg_id = 1,
744 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
745 },
746 },
747 .slaves = omap3xxx_timer4_slaves,
748 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
749 .class = &omap3xxx_timer_hwmod_class,
750 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
751};
752
753/* timer5 */
754static struct omap_hwmod omap3xxx_timer5_hwmod;
755static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
756 { .irq = 41, },
757};
758
759static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
760 {
761 .pa_start = 0x49038000,
762 .pa_end = 0x49038000 + SZ_1K - 1,
763 .flags = ADDR_TYPE_RT
764 },
765};
766
767/* l4_per -> timer5 */
768static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
769 .master = &omap3xxx_l4_per_hwmod,
770 .slave = &omap3xxx_timer5_hwmod,
771 .clk = "gpt5_ick",
772 .addr = omap3xxx_timer5_addrs,
773 .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
774 .user = OCP_USER_MPU | OCP_USER_SDMA,
775};
776
777/* timer5 slave port */
778static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
779 &omap3xxx_l4_per__timer5,
780};
781
782/* timer5 hwmod */
783static struct omap_hwmod omap3xxx_timer5_hwmod = {
784 .name = "timer5",
785 .mpu_irqs = omap3xxx_timer5_mpu_irqs,
786 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
787 .main_clk = "gpt5_fck",
788 .prcm = {
789 .omap2 = {
790 .prcm_reg_id = 1,
791 .module_bit = OMAP3430_EN_GPT5_SHIFT,
792 .module_offs = OMAP3430_PER_MOD,
793 .idlest_reg_id = 1,
794 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
795 },
796 },
797 .slaves = omap3xxx_timer5_slaves,
798 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
799 .class = &omap3xxx_timer_hwmod_class,
800 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
801};
802
803/* timer6 */
804static struct omap_hwmod omap3xxx_timer6_hwmod;
805static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
806 { .irq = 42, },
807};
808
809static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
810 {
811 .pa_start = 0x4903A000,
812 .pa_end = 0x4903A000 + SZ_1K - 1,
813 .flags = ADDR_TYPE_RT
814 },
815};
816
817/* l4_per -> timer6 */
818static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
819 .master = &omap3xxx_l4_per_hwmod,
820 .slave = &omap3xxx_timer6_hwmod,
821 .clk = "gpt6_ick",
822 .addr = omap3xxx_timer6_addrs,
823 .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
824 .user = OCP_USER_MPU | OCP_USER_SDMA,
825};
826
827/* timer6 slave port */
828static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
829 &omap3xxx_l4_per__timer6,
830};
831
832/* timer6 hwmod */
833static struct omap_hwmod omap3xxx_timer6_hwmod = {
834 .name = "timer6",
835 .mpu_irqs = omap3xxx_timer6_mpu_irqs,
836 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
837 .main_clk = "gpt6_fck",
838 .prcm = {
839 .omap2 = {
840 .prcm_reg_id = 1,
841 .module_bit = OMAP3430_EN_GPT6_SHIFT,
842 .module_offs = OMAP3430_PER_MOD,
843 .idlest_reg_id = 1,
844 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
845 },
846 },
847 .slaves = omap3xxx_timer6_slaves,
848 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
849 .class = &omap3xxx_timer_hwmod_class,
850 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
851};
852
853/* timer7 */
854static struct omap_hwmod omap3xxx_timer7_hwmod;
855static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
856 { .irq = 43, },
857};
858
859static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
860 {
861 .pa_start = 0x4903C000,
862 .pa_end = 0x4903C000 + SZ_1K - 1,
863 .flags = ADDR_TYPE_RT
864 },
865};
866
867/* l4_per -> timer7 */
868static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
869 .master = &omap3xxx_l4_per_hwmod,
870 .slave = &omap3xxx_timer7_hwmod,
871 .clk = "gpt7_ick",
872 .addr = omap3xxx_timer7_addrs,
873 .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
874 .user = OCP_USER_MPU | OCP_USER_SDMA,
875};
876
877/* timer7 slave port */
878static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
879 &omap3xxx_l4_per__timer7,
880};
881
882/* timer7 hwmod */
883static struct omap_hwmod omap3xxx_timer7_hwmod = {
884 .name = "timer7",
885 .mpu_irqs = omap3xxx_timer7_mpu_irqs,
886 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
887 .main_clk = "gpt7_fck",
888 .prcm = {
889 .omap2 = {
890 .prcm_reg_id = 1,
891 .module_bit = OMAP3430_EN_GPT7_SHIFT,
892 .module_offs = OMAP3430_PER_MOD,
893 .idlest_reg_id = 1,
894 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
895 },
896 },
897 .slaves = omap3xxx_timer7_slaves,
898 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
899 .class = &omap3xxx_timer_hwmod_class,
900 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
901};
902
903/* timer8 */
904static struct omap_hwmod omap3xxx_timer8_hwmod;
905static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
906 { .irq = 44, },
907};
908
909static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
910 {
911 .pa_start = 0x4903E000,
912 .pa_end = 0x4903E000 + SZ_1K - 1,
913 .flags = ADDR_TYPE_RT
914 },
915};
916
917/* l4_per -> timer8 */
918static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
919 .master = &omap3xxx_l4_per_hwmod,
920 .slave = &omap3xxx_timer8_hwmod,
921 .clk = "gpt8_ick",
922 .addr = omap3xxx_timer8_addrs,
923 .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
924 .user = OCP_USER_MPU | OCP_USER_SDMA,
925};
926
927/* timer8 slave port */
928static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
929 &omap3xxx_l4_per__timer8,
930};
931
932/* timer8 hwmod */
933static struct omap_hwmod omap3xxx_timer8_hwmod = {
934 .name = "timer8",
935 .mpu_irqs = omap3xxx_timer8_mpu_irqs,
936 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
937 .main_clk = "gpt8_fck",
938 .prcm = {
939 .omap2 = {
940 .prcm_reg_id = 1,
941 .module_bit = OMAP3430_EN_GPT8_SHIFT,
942 .module_offs = OMAP3430_PER_MOD,
943 .idlest_reg_id = 1,
944 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
945 },
946 },
947 .slaves = omap3xxx_timer8_slaves,
948 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
949 .class = &omap3xxx_timer_hwmod_class,
950 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
951};
952
953/* timer9 */
954static struct omap_hwmod omap3xxx_timer9_hwmod;
955static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
956 { .irq = 45, },
957};
958
959static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
960 {
961 .pa_start = 0x49040000,
962 .pa_end = 0x49040000 + SZ_1K - 1,
963 .flags = ADDR_TYPE_RT
964 },
965};
966
967/* l4_per -> timer9 */
968static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
969 .master = &omap3xxx_l4_per_hwmod,
970 .slave = &omap3xxx_timer9_hwmod,
971 .clk = "gpt9_ick",
972 .addr = omap3xxx_timer9_addrs,
973 .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
974 .user = OCP_USER_MPU | OCP_USER_SDMA,
975};
976
977/* timer9 slave port */
978static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
979 &omap3xxx_l4_per__timer9,
980};
981
982/* timer9 hwmod */
983static struct omap_hwmod omap3xxx_timer9_hwmod = {
984 .name = "timer9",
985 .mpu_irqs = omap3xxx_timer9_mpu_irqs,
986 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
987 .main_clk = "gpt9_fck",
988 .prcm = {
989 .omap2 = {
990 .prcm_reg_id = 1,
991 .module_bit = OMAP3430_EN_GPT9_SHIFT,
992 .module_offs = OMAP3430_PER_MOD,
993 .idlest_reg_id = 1,
994 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
995 },
996 },
997 .slaves = omap3xxx_timer9_slaves,
998 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
999 .class = &omap3xxx_timer_hwmod_class,
1000 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1001};
1002
1003/* timer10 */
1004static struct omap_hwmod omap3xxx_timer10_hwmod;
1005static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1006 { .irq = 46, },
1007};
1008
1009static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
1010 {
1011 .pa_start = 0x48086000,
1012 .pa_end = 0x48086000 + SZ_1K - 1,
1013 .flags = ADDR_TYPE_RT
1014 },
1015};
1016
1017/* l4_core -> timer10 */
1018static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1019 .master = &omap3xxx_l4_core_hwmod,
1020 .slave = &omap3xxx_timer10_hwmod,
1021 .clk = "gpt10_ick",
1022 .addr = omap3xxx_timer10_addrs,
1023 .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
1024 .user = OCP_USER_MPU | OCP_USER_SDMA,
1025};
1026
1027/* timer10 slave port */
1028static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1029 &omap3xxx_l4_core__timer10,
1030};
1031
1032/* timer10 hwmod */
1033static struct omap_hwmod omap3xxx_timer10_hwmod = {
1034 .name = "timer10",
1035 .mpu_irqs = omap3xxx_timer10_mpu_irqs,
1036 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
1037 .main_clk = "gpt10_fck",
1038 .prcm = {
1039 .omap2 = {
1040 .prcm_reg_id = 1,
1041 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1042 .module_offs = CORE_MOD,
1043 .idlest_reg_id = 1,
1044 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1045 },
1046 },
1047 .slaves = omap3xxx_timer10_slaves,
1048 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1049 .class = &omap3xxx_timer_1ms_hwmod_class,
1050 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1051};
1052
1053/* timer11 */
1054static struct omap_hwmod omap3xxx_timer11_hwmod;
1055static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1056 { .irq = 47, },
1057};
1058
1059static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
1060 {
1061 .pa_start = 0x48088000,
1062 .pa_end = 0x48088000 + SZ_1K - 1,
1063 .flags = ADDR_TYPE_RT
1064 },
1065};
1066
1067/* l4_core -> timer11 */
1068static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1069 .master = &omap3xxx_l4_core_hwmod,
1070 .slave = &omap3xxx_timer11_hwmod,
1071 .clk = "gpt11_ick",
1072 .addr = omap3xxx_timer11_addrs,
1073 .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
1074 .user = OCP_USER_MPU | OCP_USER_SDMA,
1075};
1076
1077/* timer11 slave port */
1078static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1079 &omap3xxx_l4_core__timer11,
1080};
1081
1082/* timer11 hwmod */
1083static struct omap_hwmod omap3xxx_timer11_hwmod = {
1084 .name = "timer11",
1085 .mpu_irqs = omap3xxx_timer11_mpu_irqs,
1086 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
1087 .main_clk = "gpt11_fck",
1088 .prcm = {
1089 .omap2 = {
1090 .prcm_reg_id = 1,
1091 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1092 .module_offs = CORE_MOD,
1093 .idlest_reg_id = 1,
1094 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1095 },
1096 },
1097 .slaves = omap3xxx_timer11_slaves,
1098 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1099 .class = &omap3xxx_timer_hwmod_class,
1100 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1101};
1102
1103/* timer12*/
1104static struct omap_hwmod omap3xxx_timer12_hwmod;
1105static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1106 { .irq = 95, },
1107};
1108
1109static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1110 {
1111 .pa_start = 0x48304000,
1112 .pa_end = 0x48304000 + SZ_1K - 1,
1113 .flags = ADDR_TYPE_RT
1114 },
1115};
1116
1117/* l4_core -> timer12 */
1118static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1119 .master = &omap3xxx_l4_core_hwmod,
1120 .slave = &omap3xxx_timer12_hwmod,
1121 .clk = "gpt12_ick",
1122 .addr = omap3xxx_timer12_addrs,
1123 .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs),
1124 .user = OCP_USER_MPU | OCP_USER_SDMA,
1125};
1126
1127/* timer12 slave port */
1128static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1129 &omap3xxx_l4_core__timer12,
1130};
1131
1132/* timer12 hwmod */
1133static struct omap_hwmod omap3xxx_timer12_hwmod = {
1134 .name = "timer12",
1135 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1136 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
1137 .main_clk = "gpt12_fck",
1138 .prcm = {
1139 .omap2 = {
1140 .prcm_reg_id = 1,
1141 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1142 .module_offs = WKUP_MOD,
1143 .idlest_reg_id = 1,
1144 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1145 },
1146 },
1147 .slaves = omap3xxx_timer12_slaves,
1148 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1149 .class = &omap3xxx_timer_hwmod_class,
1150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1151};
1152
518/* l4_wkup -> wd_timer2 */ 1153/* l4_wkup -> wd_timer2 */
519static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { 1154static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
520 { 1155 {
@@ -2219,6 +2854,20 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
2219 &omap3xxx_l4_wkup_hwmod, 2854 &omap3xxx_l4_wkup_hwmod,
2220 &omap3xxx_mpu_hwmod, 2855 &omap3xxx_mpu_hwmod,
2221 &omap3xxx_iva_hwmod, 2856 &omap3xxx_iva_hwmod,
2857
2858 &omap3xxx_timer1_hwmod,
2859 &omap3xxx_timer2_hwmod,
2860 &omap3xxx_timer3_hwmod,
2861 &omap3xxx_timer4_hwmod,
2862 &omap3xxx_timer5_hwmod,
2863 &omap3xxx_timer6_hwmod,
2864 &omap3xxx_timer7_hwmod,
2865 &omap3xxx_timer8_hwmod,
2866 &omap3xxx_timer9_hwmod,
2867 &omap3xxx_timer10_hwmod,
2868 &omap3xxx_timer11_hwmod,
2869 &omap3xxx_timer12_hwmod,
2870
2222 &omap3xxx_wd_timer2_hwmod, 2871 &omap3xxx_wd_timer2_hwmod,
2223 &omap3xxx_uart1_hwmod, 2872 &omap3xxx_uart1_hwmod,
2224 &omap3xxx_uart2_hwmod, 2873 &omap3xxx_uart2_hwmod,
@@ -2270,5 +2919,5 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
2270 2919
2271int __init omap3xxx_hwmod_init(void) 2920int __init omap3xxx_hwmod_init(void)
2272{ 2921{
2273 return omap_hwmod_init(omap3xxx_hwmods); 2922 return omap_hwmod_register(omap3xxx_hwmods);
2274} 2923}
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 79a860178913..2c5882792e01 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -5125,6 +5125,6 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5125 5125
5126int __init omap44xx_hwmod_init(void) 5126int __init omap44xx_hwmod_init(void)
5127{ 5127{
5128 return omap_hwmod_init(omap44xx_hwmods); 5128 return omap_hwmod_register(omap44xx_hwmods);
5129} 5129}
5130 5130
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 47eef48b8830..1ac361b7b8cb 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -680,7 +680,7 @@ static int __init omap_serial_early_init(void)
680 num_uarts++; 680 num_uarts++;
681 681
682 /* 682 /*
683 * NOTE: omap_hwmod_init() has not yet been called, 683 * NOTE: omap_hwmod_setup*() has not yet been called,
684 * so no hwmod functions will work yet. 684 * so no hwmod functions will work yet.
685 */ 685 */
686 686
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 7b7c2683ae7b..fb8d656e4d0a 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -39,10 +39,11 @@
39#include <asm/mach/time.h> 39#include <asm/mach/time.h>
40#include <plat/dmtimer.h> 40#include <plat/dmtimer.h>
41#include <asm/localtimer.h> 41#include <asm/localtimer.h>
42#include <plat/common.h>
43#include <plat/omap_hwmod.h>
42 44
43#include "timer-gp.h" 45#include "timer-gp.h"
44 46
45#include <plat/common.h>
46 47
47/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ 48/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
48#define MAX_GPTIMER_ID 12 49#define MAX_GPTIMER_ID 12
@@ -132,9 +133,13 @@ static void __init omap2_gp_clockevent_init(void)
132{ 133{
133 u32 tick_rate; 134 u32 tick_rate;
134 int src; 135 int src;
136 char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */
135 137
136 inited = 1; 138 inited = 1;
137 139
140 sprintf(clockevent_hwmod_name, "timer%d", gptimer_id);
141 omap_hwmod_setup_one(clockevent_hwmod_name);
142
138 gptimer = omap_dm_timer_request_specific(gptimer_id); 143 gptimer = omap_dm_timer_request_specific(gptimer_id);
139 BUG_ON(gptimer == NULL); 144 BUG_ON(gptimer == NULL);
140 gptimer_wakeup = gptimer; 145 gptimer_wakeup = gptimer;
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index dfa3aff9761b..d6c70d2f4030 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -3,6 +3,12 @@
3 * 3 *
4 * OMAP Dual-Mode Timers 4 * OMAP Dual-Mode Timers
5 * 5 *
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
8 * Thara Gopinath <thara@ti.com>
9 *
10 * Platform device conversion and hwmod support.
11 *
6 * Copyright (C) 2005 Nokia Corporation 12 * Copyright (C) 2005 Nokia Corporation
7 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com> 13 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
8 * PWM and clock framwork support by Timo Teras. 14 * PWM and clock framwork support by Timo Teras.
@@ -44,6 +50,11 @@
44#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 50#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
45#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 51#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
46 52
53/*
54 * IP revision identifier so that Highlander IP
55 * in OMAP4 can be distinguished.
56 */
57#define OMAP_TIMER_IP_VERSION_1 0x1
47struct omap_dm_timer; 58struct omap_dm_timer;
48extern struct omap_dm_timer *gptimer_wakeup; 59extern struct omap_dm_timer *gptimer_wakeup;
49extern struct sys_timer omap_timer; 60extern struct sys_timer omap_timer;
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index fedd82971c9e..f96e72ed4db1 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * omap_hwmod macros, structures 2 * omap_hwmod macros, structures
3 * 3 *
4 * Copyright (C) 2009-2010 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley 5 * Paul Walmsley
6 * 6 *
7 * Created in collaboration with (alphabetical order): Benoît Cousson, 7 * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -30,6 +30,7 @@
30#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H 30#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
31 31
32#include <linux/kernel.h> 32#include <linux/kernel.h>
33#include <linux/init.h>
33#include <linux/list.h> 34#include <linux/list.h>
34#include <linux/ioport.h> 35#include <linux/ioport.h>
35#include <linux/spinlock.h> 36#include <linux/spinlock.h>
@@ -370,8 +371,10 @@ struct omap_hwmod_omap4_prcm {
370 * of standby, rather than relying on module smart-standby 371 * of standby, rather than relying on module smart-standby
371 * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for 372 * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
372 * SDRAM controller, etc. XXX probably belongs outside the main hwmod file 373 * SDRAM controller, etc. XXX probably belongs outside the main hwmod file
374 * XXX Should be HWMOD_SETUP_NO_RESET
373 * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM 375 * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
374 * controller, etc. XXX probably belongs outside the main hwmod file 376 * controller, etc. XXX probably belongs outside the main hwmod file
377 * XXX Should be HWMOD_SETUP_NO_IDLE
375 * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) 378 * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
376 * when module is enabled, rather than the default, which is to 379 * when module is enabled, rather than the default, which is to
377 * enable autoidle 380 * enable autoidle
@@ -535,11 +538,13 @@ struct omap_hwmod {
535 const struct omap_chip_id omap_chip; 538 const struct omap_chip_id omap_chip;
536}; 539};
537 540
538int omap_hwmod_init(struct omap_hwmod **ohs); 541int omap_hwmod_register(struct omap_hwmod **ohs);
539struct omap_hwmod *omap_hwmod_lookup(const char *name); 542struct omap_hwmod *omap_hwmod_lookup(const char *name);
540int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), 543int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
541 void *data); 544 void *data);
542 545
546int __init omap_hwmod_setup_one(const char *name);
547
543int omap_hwmod_enable(struct omap_hwmod *oh); 548int omap_hwmod_enable(struct omap_hwmod *oh);
544int _omap_hwmod_enable(struct omap_hwmod *oh); 549int _omap_hwmod_enable(struct omap_hwmod *oh);
545int omap_hwmod_idle(struct omap_hwmod *oh); 550int omap_hwmod_idle(struct omap_hwmod *oh);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 21:35:16 -0500