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authorArnd Bergmann <arnd@arndb.de>2013-04-09 16:24:06 -0400
committerArnd Bergmann <arnd@arndb.de>2013-04-09 16:28:45 -0400
commit19ce4f4a03e52bc694dc837a4a832111cb4271b3 (patch)
tree79757bb645e035166ca012373992e185f8d07081
parent228e3023eb0430b4b9ed0736f8f87c96a6cd9c7a (diff)
parentda821eb7d42935b0f7056d98c75fd1150f6636f4 (diff)
Merge tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>: add suppport common clock framework for exynos * tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (73 commits) ARM: EXYNOS: fix compilation error introduced due to common clock migration clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3} clk: exynos4: export clocks required for fimc-is clk: samsung: Fix compilation error clk: exynos5250: register display block gate clocks to common clock framework clk: exynos4: Add support for SoC-specific register save list clk: exynos4: Add missing registers to suspend save list clk: exynos4: Remove E4X12 prefix from SRC_DMC register clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register clk: exynos4: Add E4210 prefix to LCD1 clock registers clk: exynos4: Remove SoC-specific registers from save list clk: exynos4: Use SRC_MASK_PERIL{0,1} definitions clk: exynos4: Define {E,V}PLL registers clk: exynos4: Add missing mout_sata on Exynos4210 clk: exynos4: Add missing CMU_TOP and ISP clocks clk: exynos4: Add G3D clocks clk: exynos4: Add camera related clock definitions clk: exynos4: Export mout_core clock of Exynos4210 clk: samsung: Remove unimplemented ops for pll clk: exynos4: Export clocks used by exynos cpufreq drivers ... [arnd: add missing #address-cells property in mshc DT node] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/exynos4-clock.txt288
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5250-clock.txt177
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5440-clock.txt61
-rw-r--r--Documentation/devicetree/bindings/media/s5p-mfc.txt21
-rw-r--r--Documentation/devicetree/bindings/usb/exynos-usb.txt40
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/boot/dts/Makefile3
-rw-r--r--arch/arm/boot/dts/cros5250-common.dtsi138
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi58
-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts18
-rw-r--r--arch/arm/boot/dts/exynos4210-smdkv310.dts18
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts12
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi8
-rw-r--r--arch/arm/boot/dts/exynos4412-odroidx.dts111
-rw-r--r--arch/arm/boot/dts/exynos4412-origen.dts432
-rw-r--r--arch/arm/boot/dts/exynos4412-smdk4412.dts25
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi6
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts129
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts20
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts11
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi120
-rw-r--r--arch/arm/boot/dts/exynos5440-ssdk5440.dts19
-rw-r--r--arch/arm/boot/dts/exynos5440.dtsi66
-rw-r--r--arch/arm/mach-exynos/Kconfig2
-rw-r--r--arch/arm/mach-exynos/Makefile4
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c1601
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.h35
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c187
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c201
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c1645
-rw-r--r--arch/arm/mach-exynos/common.c54
-rw-r--r--arch/arm/mach-exynos/common.h8
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-clock.h107
-rw-r--r--arch/arm/mach-exynos/mach-armlex4210.c3
-rw-r--r--arch/arm/mach-exynos/mach-exynos4-dt.c121
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c140
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c5
-rw-r--r--arch/arm/mach-exynos/mach-origen.c5
-rw-r--r--arch/arm/mach-exynos/mach-smdk4x12.c5
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c7
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c3
-rw-r--r--arch/arm/plat-samsung/Kconfig4
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/samsung/Makefile8
-rw-r--r--drivers/clk/samsung/clk-exynos4.c1091
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c523
-rw-r--r--drivers/clk/samsung/clk-exynos5440.c139
-rw-r--r--drivers/clk/samsung/clk-pll.c419
-rw-r--r--drivers/clk/samsung/clk-pll.h41
-rw-r--r--drivers/clk/samsung/clk.c320
-rw-r--r--drivers/clk/samsung/clk.h289
-rw-r--r--drivers/clocksource/exynos_mct.c20
53 files changed, 4655 insertions, 4117 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
new file mode 100644
index 000000000000..ea5e26f16aec
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -0,0 +1,288 @@
1* Samsung Exynos4 Clock Controller
2
3The Exynos4 clock controller generates and supplies clock to various controllers
4within the Exynos4 SoC. The clock binding described here is applicable to all
5SoC's in the Exynos4 family.
6
7Required Properties:
8
9- comptible: should be one of the following.
10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
12
13- reg: physical base address of the controller and length of memory mapped
14 region.
15
16- #clock-cells: should be 1.
17
18The following is the list of clocks generated by the controller. Each clock is
19assigned an identifier and client nodes use this identifier to specify the
20clock which they consume. Some of the clocks are available only on a particular
21Exynos4 SoC and this is specified where applicable.
22
23
24 [Core Clocks]
25
26 Clock ID SoC (if specific)
27 -----------------------------------------------
28
29 xxti 1
30 xusbxti 2
31 fin_pll 3
32 fout_apll 4
33 fout_mpll 5
34 fout_epll 6
35 fout_vpll 7
36 sclk_apll 8
37 sclk_mpll 9
38 sclk_epll 10
39 sclk_vpll 11
40 arm_clk 12
41 aclk200 13
42 aclk100 14
43 aclk160 15
44 aclk133 16
45 mout_mpll_user_t 17 Exynos4x12
46 mout_mpll_user_c 18 Exynos4x12
47 mout_core 19
48 mout_apll 20
49
50
51 [Clock Gate for Special Clocks]
52
53 Clock ID SoC (if specific)
54 -----------------------------------------------
55
56 sclk_fimc0 128
57 sclk_fimc1 129
58 sclk_fimc2 130
59 sclk_fimc3 131
60 sclk_cam0 132
61 sclk_cam1 133
62 sclk_csis0 134
63 sclk_csis1 135
64 sclk_hdmi 136
65 sclk_mixer 137
66 sclk_dac 138
67 sclk_pixel 139
68 sclk_fimd0 140
69 sclk_mdnie0 141 Exynos4412
70 sclk_mdnie_pwm0 12 142 Exynos4412
71 sclk_mipi0 143
72 sclk_audio0 144
73 sclk_mmc0 145
74 sclk_mmc1 146
75 sclk_mmc2 147
76 sclk_mmc3 148
77 sclk_mmc4 149
78 sclk_sata 150 Exynos4210
79 sclk_uart0 151
80 sclk_uart1 152
81 sclk_uart2 153
82 sclk_uart3 154
83 sclk_uart4 155
84 sclk_audio1 156
85 sclk_audio2 157
86 sclk_spdif 158
87 sclk_spi0 159
88 sclk_spi1 160
89 sclk_spi2 161
90 sclk_slimbus 162
91 sclk_fimd1 163 Exynos4210
92 sclk_mipi1 164 Exynos4210
93 sclk_pcm1 165
94 sclk_pcm2 166
95 sclk_i2s1 167
96 sclk_i2s2 168
97 sclk_mipihsi 169 Exynos4412
98 sclk_mfc 170
99 sclk_pcm0 171
100 sclk_g3d 172
101 sclk_pwm_isp 173 Exynos4x12
102 sclk_spi0_isp 174 Exynos4x12
103 sclk_spi1_isp 175 Exynos4x12
104 sclk_uart_isp 176 Exynos4x12
105
106 [Peripheral Clock Gates]
107
108 Clock ID SoC (if specific)
109 -----------------------------------------------
110
111 fimc0 256
112 fimc1 257
113 fimc2 258
114 fimc3 259
115 csis0 260
116 csis1 261
117 jpeg 262
118 smmu_fimc0 263
119 smmu_fimc1 264
120 smmu_fimc2 265
121 smmu_fimc3 266
122 smmu_jpeg 267
123 vp 268
124 mixer 269
125 tvenc 270 Exynos4210
126 hdmi 271
127 smmu_tv 272
128 mfc 273
129 smmu_mfcl 274
130 smmu_mfcr 275
131 g3d 276
132 g2d 277 Exynos4210
133 rotator 278 Exynos4210
134 mdma 279 Exynos4210
135 smmu_g2d 280 Exynos4210
136 smmu_rotator 281 Exynos4210
137 smmu_mdma 282 Exynos4210
138 fimd0 283
139 mie0 284
140 mdnie0 285 Exynos4412
141 dsim0 286
142 smmu_fimd0 287
143 fimd1 288 Exynos4210
144 mie1 289 Exynos4210
145 dsim1 290 Exynos4210
146 smmu_fimd1 291 Exynos4210
147 pdma0 292
148 pdma1 293
149 pcie_phy 294
150 sata_phy 295 Exynos4210
151 tsi 296
152 sdmmc0 297
153 sdmmc1 298
154 sdmmc2 299
155 sdmmc3 300
156 sdmmc4 301
157 sata 302 Exynos4210
158 sromc 303
159 usb_host 304
160 usb_device 305
161 pcie 306
162 onenand 307
163 nfcon 308
164 smmu_pcie 309
165 gps 310
166 smmu_gps 311
167 uart0 312
168 uart1 313
169 uart2 314
170 uart3 315
171 uart4 316
172 i2c0 317
173 i2c1 318
174 i2c2 319
175 i2c3 320
176 i2c4 321
177 i2c5 322
178 i2c6 323
179 i2c7 324
180 i2c_hdmi 325
181 tsadc 326
182 spi0 327
183 spi1 328
184 spi2 329
185 i2s1 330
186 i2s2 331
187 pcm0 332
188 i2s0 333
189 pcm1 334
190 pcm2 335
191 pwm 336
192 slimbus 337
193 spdif 338
194 ac97 339
195 modemif 340
196 chipid 341
197 sysreg 342
198 hdmi_cec 343
199 mct 344
200 wdt 345
201 rtc 346
202 keyif 347
203 audss 348
204 mipi_hsi 349 Exynos4210
205 mdma2 350 Exynos4210
206 pixelasyncm0 351
207 pixelasyncm1 352
208 fimc_lite0 353 Exynos4x12
209 fimc_lite1 354 Exynos4x12
210 ppmuispx 355 Exynos4x12
211 ppmuispmx 356 Exynos4x12
212 fimc_isp 357 Exynos4x12
213 fimc_drc 358 Exynos4x12
214 fimc_fd 359 Exynos4x12
215 mcuisp 360 Exynos4x12
216 gicisp 361 Exynos4x12
217 smmu_isp 362 Exynos4x12
218 smmu_drc 363 Exynos4x12
219 smmu_fd 364 Exynos4x12
220 smmu_lite0 365 Exynos4x12
221 smmu_lite1 366 Exynos4x12
222 mcuctl_isp 367 Exynos4x12
223 mpwm_isp 368 Exynos4x12
224 i2c0_isp 369 Exynos4x12
225 i2c1_isp 370 Exynos4x12
226 mtcadc_isp 371 Exynos4x12
227 pwm_isp 372 Exynos4x12
228 wdt_isp 373 Exynos4x12
229 uart_isp 374 Exynos4x12
230 asyncaxim 375 Exynos4x12
231 smmu_ispcx 376 Exynos4x12
232 spi0_isp 377 Exynos4x12
233 spi1_isp 378 Exynos4x12
234 pwm_isp_sclk 379 Exynos4x12
235 spi0_isp_sclk 380 Exynos4x12
236 spi1_isp_sclk 381 Exynos4x12
237 uart_isp_sclk 382 Exynos4x12
238
239 [Mux Clocks]
240
241 Clock ID SoC (if specific)
242 -----------------------------------------------
243
244 mout_fimc0 384
245 mout_fimc1 385
246 mout_fimc2 386
247 mout_fimc3 387
248 mout_cam0 388
249 mout_cam1 389
250 mout_csis0 390
251 mout_csis1 391
252 mout_g3d0 392
253 mout_g3d1 393
254 mout_g3d 394
255 aclk400_mcuisp 395 Exynos4x12
256
257 [Div Clocks]
258
259 Clock ID SoC (if specific)
260 -----------------------------------------------
261
262 div_isp0 450 Exynos4x12
263 div_isp1 451 Exynos4x12
264 div_mcuisp0 452 Exynos4x12
265 div_mcuisp1 453 Exynos4x12
266 div_aclk200 454 Exynos4x12
267 div_aclk400_mcuisp 455 Exynos4x12
268
269
270Example 1: An example of a clock controller node is listed below.
271
272 clock: clock-controller@0x10030000 {
273 compatible = "samsung,exynos4210-clock";
274 reg = <0x10030000 0x20000>;
275 #clock-cells = <1>;
276 };
277
278Example 2: UART controller node that consumes the clock generated by the clock
279 controller. Refer to the standard clock bindings for information
280 about 'clocks' and 'clock-names' property.
281
282 serial@13820000 {
283 compatible = "samsung,exynos4210-uart";
284 reg = <0x13820000 0x100>;
285 interrupts = <0 54 0>;
286 clocks = <&clock 314>, <&clock 153>;
287 clock-names = "uart", "clk_uart_baud0";
288 };
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
new file mode 100644
index 000000000000..781a6276adf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -0,0 +1,177 @@
1* Samsung Exynos5250 Clock Controller
2
3The Exynos5250 clock controller generates and supplies clock to various
4controllers within the Exynos5250 SoC.
5
6Required Properties:
7
8- comptible: should be one of the following.
9 - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
10
11- reg: physical base address of the controller and length of memory mapped
12 region.
13
14- #clock-cells: should be 1.
15
16The following is the list of clocks generated by the controller. Each clock is
17assigned an identifier and client nodes use this identifier to specify the
18clock which they consume.
19
20
21 [Core Clocks]
22
23 Clock ID
24 ----------------------------
25
26 fin_pll 1
27
28 [Clock Gate for Special Clocks]
29
30 Clock ID
31 ----------------------------
32
33 sclk_cam_bayer 128
34 sclk_cam0 129
35 sclk_cam1 130
36 sclk_gscl_wa 131
37 sclk_gscl_wb 132
38 sclk_fimd1 133
39 sclk_mipi1 134
40 sclk_dp 135
41 sclk_hdmi 136
42 sclk_pixel 137
43 sclk_audio0 138
44 sclk_mmc0 139
45 sclk_mmc1 140
46 sclk_mmc2 141
47 sclk_mmc3 142
48 sclk_sata 143
49 sclk_usb3 144
50 sclk_jpeg 145
51 sclk_uart0 146
52 sclk_uart1 147
53 sclk_uart2 148
54 sclk_uart3 149
55 sclk_pwm 150
56 sclk_audio1 151
57 sclk_audio2 152
58 sclk_spdif 153
59 sclk_spi0 154
60 sclk_spi1 155
61 sclk_spi2 156
62
63
64 [Peripheral Clock Gates]
65
66 Clock ID
67 ----------------------------
68
69 gscl0 256
70 gscl1 257
71 gscl2 258
72 gscl3 259
73 gscl_wa 260
74 gscl_wb 261
75 smmu_gscl0 262
76 smmu_gscl1 263
77 smmu_gscl2 264
78 smmu_gscl3 265
79 mfc 266
80 smmu_mfcl 267
81 smmu_mfcr 268
82 rotator 269
83 jpeg 270
84 mdma1 271
85 smmu_rotator 272
86 smmu_jpeg 273
87 smmu_mdma1 274
88 pdma0 275
89 pdma1 276
90 sata 277
91 usbotg 278
92 mipi_hsi 279
93 sdmmc0 280
94 sdmmc1 281
95 sdmmc2 282
96 sdmmc3 283
97 sromc 284
98 usb2 285
99 usb3 286
100 sata_phyctrl 287
101 sata_phyi2c 288
102 uart0 289
103 uart1 290
104 uart2 291
105 uart3 292
106 uart4 293
107 i2c0 294
108 i2c1 295
109 i2c2 296
110 i2c3 297
111 i2c4 298
112 i2c5 299
113 i2c6 300
114 i2c7 301
115 i2c_hdmi 302
116 adc 303
117 spi0 304
118 spi1 305
119 spi2 306
120 i2s1 307
121 i2s2 308
122 pcm1 309
123 pcm2 310
124 pwm 311
125 spdif 312
126 ac97 313
127 hsi2c0 314
128 hsi2c1 315
129 hs12c2 316
130 hs12c3 317
131 chipid 318
132 sysreg 319
133 pmu 320
134 cmu_top 321
135 cmu_core 322
136 cmu_mem 323
137 tzpc0 324
138 tzpc1 325
139 tzpc2 326
140 tzpc3 327
141 tzpc4 328
142 tzpc5 329
143 tzpc6 330
144 tzpc7 331
145 tzpc8 332
146 tzpc9 333
147 hdmi_cec 334
148 mct 335
149 wdt 336
150 rtc 337
151 tmu 338
152 fimd1 339
153 mie1 340
154 dsim0 341
155 dp 342
156 mixer 343
157 hdmi 345
158
159Example 1: An example of a clock controller node is listed below.
160
161 clock: clock-controller@0x10010000 {
162 compatible = "samsung,exynos5250-clock";
163 reg = <0x10010000 0x30000>;
164 #clock-cells = <1>;
165 };
166
167Example 2: UART controller node that consumes the clock generated by the clock
168 controller. Refer to the standard clock bindings for information
169 about 'clocks' and 'clock-names' property.
170
171 serial@13820000 {
172 compatible = "samsung,exynos4210-uart";
173 reg = <0x13820000 0x100>;
174 interrupts = <0 54 0>;
175 clocks = <&clock 314>, <&clock 153>;
176 clock-names = "uart", "clk_uart_baud0";
177 };
diff --git a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
new file mode 100644
index 000000000000..4499e9966bc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
@@ -0,0 +1,61 @@
1* Samsung Exynos5440 Clock Controller
2
3The Exynos5440 clock controller generates and supplies clock to various
4controllers within the Exynos5440 SoC.
5
6Required Properties:
7
8- comptible: should be "samsung,exynos5440-clock".
9
10- reg: physical base address of the controller and length of memory mapped
11 region.
12
13- #clock-cells: should be 1.
14
15The following is the list of clocks generated by the controller. Each clock is
16assigned an identifier and client nodes use this identifier to specify the
17clock which they consume.
18
19
20 [Core Clocks]
21
22 Clock ID
23 ----------------------------
24
25 xtal 1
26 arm_clk 2
27
28 [Peripheral Clock Gates]
29
30 Clock ID
31 ----------------------------
32
33 spi_baud 16
34 pb0_250 17
35 pr0_250 18
36 pr1_250 19
37 b_250 20
38 b_125 21
39 b_200 22
40 sata 23
41 usb 24
42 gmac0 25
43 cs250 26
44 pb0_250_o 27
45 pr0_250_o 28
46 pr1_250_o 29
47 b_250_o 30
48 b_125_o 31
49 b_200_o 32
50 sata_o 33
51 usb_o 34
52 gmac0_o 35
53 cs250_o 36
54
55Example: An example of a clock controller node is listed below.
56
57 clock: clock-controller@0x10010000 {
58 compatible = "samsung,exynos5440-clock";
59 reg = <0x160000 0x10000>;
60 #clock-cells = <1>;
61 };
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
index 67ec3d4ccc7f..bf0182d8da25 100644
--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -21,3 +21,24 @@ Required properties:
21 21
22 - samsung,mfc-l : Base address of the second memory bank used by MFC 22 - samsung,mfc-l : Base address of the second memory bank used by MFC
23 for DMA contiguous memory allocation and its size. 23 for DMA contiguous memory allocation and its size.
24
25Optional properties:
26 - samsung,power-domain : power-domain property defined with a phandle
27 to respective power domain.
28
29Example:
30SoC specific DT entry:
31
32mfc: codec@13400000 {
33 compatible = "samsung,mfc-v5";
34 reg = <0x13400000 0x10000>;
35 interrupts = <0 94 0>;
36 samsung,power-domain = <&pd_mfc>;
37};
38
39Board specific DT entry:
40
41codec@13400000 {
42 samsung,mfc-r = <0x43000000 0x800000>;
43 samsung,mfc-l = <0x51000000 0x800000>;
44};
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
new file mode 100644
index 000000000000..f66fcddba46f
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -0,0 +1,40 @@
1Samsung Exynos SoC USB controller
2
3The USB devices interface with USB controllers on Exynos SOCs.
4The device node has following properties.
5
6EHCI
7Required properties:
8 - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
9 EHCI controller in host mode.
10 - reg: physical base address of the controller and length of memory mapped
11 region.
12 - interrupts: interrupt number to the cpu.
13
14Optional properties:
15 - samsung,vbus-gpio: if present, specifies the GPIO that
16 needs to be pulled up for the bus to be powered.
17
18Example:
19
20 usb@12110000 {
21 compatible = "samsung,exynos4210-ehci";
22 reg = <0x12110000 0x100>;
23 interrupts = <0 71 0>;
24 samsung,vbus-gpio = <&gpx2 6 1 3 3>;
25 };
26
27OHCI
28Required properties:
29 - compatible: should be "samsung,exynos4210-ohci" for USB 2.0
30 OHCI companion controller in host mode.
31 - reg: physical base address of the controller and length of memory mapped
32 region.
33 - interrupts: interrupt number to the cpu.
34
35Example:
36 usb@12120000 {
37 compatible = "samsung,exynos4210-ohci";
38 reg = <0x12120000 0x100>;
39 interrupts = <0 71 0>;
40 };
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 03301cb114ac..1dc16e539808 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -866,6 +866,7 @@ config ARCH_EXYNOS
866 select ARCH_HAS_HOLES_MEMORYMODEL 866 select ARCH_HAS_HOLES_MEMORYMODEL
867 select ARCH_SPARSEMEM_ENABLE 867 select ARCH_SPARSEMEM_ENABLE
868 select CLKDEV_LOOKUP 868 select CLKDEV_LOOKUP
869 select COMMON_CLK
869 select CPU_V7 870 select CPU_V7
870 select GENERIC_CLOCKEVENTS 871 select GENERIC_CLOCKEVENTS
871 select HAVE_CLK 872 select HAVE_CLK
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9c6255884cbb..d3cd880d70b3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -42,7 +42,10 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
42dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ 42dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
43 exynos4210-smdkv310.dtb \ 43 exynos4210-smdkv310.dtb \
44 exynos4210-trats.dtb \ 44 exynos4210-trats.dtb \
45 exynos4412-odroidx.dtb \
45 exynos4412-smdk4412.dtb \ 46 exynos4412-smdk4412.dtb \
47 exynos4412-origen.dtb \
48 exynos5250-arndale.dtb \
46 exynos5250-smdk5250.dtb \ 49 exynos5250-smdk5250.dtb \
47 exynos5250-snow.dtb \ 50 exynos5250-snow.dtb \
48 exynos5440-ssdk5440.dtb 51 exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi
index 46c098017036..62eceb4f0d3f 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -24,6 +24,144 @@
24 samsung,i2c-max-bus-freq = <378000>; 24 samsung,i2c-max-bus-freq = <378000>;
25 gpios = <&gpb3 0 2 3 0>, 25 gpios = <&gpb3 0 2 3 0>,
26 <&gpb3 1 2 3 0>; 26 <&gpb3 1 2 3 0>;
27
28 max77686@09 {
29 compatible = "maxim,max77686";
30 reg = <0x09>;
31
32 voltage-regulators {
33 ldo1_reg: LDO1 {
34 regulator-name = "P1.0V_LDO_OUT1";
35 regulator-min-microvolt = <1000000>;
36 regulator-max-microvolt = <1000000>;
37 regulator-always-on;
38 };
39
40 ldo2_reg: LDO2 {
41 regulator-name = "P1.8V_LDO_OUT2";
42 regulator-min-microvolt = <1800000>;
43 regulator-max-microvolt = <1800000>;
44 regulator-always-on;
45 };
46
47 ldo3_reg: LDO3 {
48 regulator-name = "P1.8V_LDO_OUT3";
49 regulator-min-microvolt = <1800000>;
50 regulator-max-microvolt = <1800000>;
51 regulator-always-on;
52 };
53
54 ldo7_reg: LDO7 {
55 regulator-name = "P1.1V_LDO_OUT7";
56 regulator-min-microvolt = <1100000>;
57 regulator-max-microvolt = <1100000>;
58 regulator-always-on;
59 };
60
61 ldo8_reg: LDO8 {
62 regulator-name = "P1.0V_LDO_OUT8";
63 regulator-min-microvolt = <1000000>;
64 regulator-max-microvolt = <1000000>;
65 regulator-always-on;
66 };
67
68 ldo10_reg: LDO10 {
69 regulator-name = "P1.8V_LDO_OUT10";
70 regulator-min-microvolt = <1800000>;
71 regulator-max-microvolt = <1800000>;
72 regulator-always-on;
73 };
74
75 ldo12_reg: LDO12 {
76 regulator-name = "P3.0V_LDO_OUT12";
77 regulator-min-microvolt = <3000000>;
78 regulator-max-microvolt = <3000000>;
79 regulator-always-on;
80 };
81
82 ldo14_reg: LDO14 {
83 regulator-name = "P1.8V_LDO_OUT14";
84 regulator-min-microvolt = <1800000>;
85 regulator-max-microvolt = <1800000>;
86 regulator-always-on;
87 };
88
89 ldo15_reg: LDO15 {
90 regulator-name = "P1.0V_LDO_OUT15";
91 regulator-min-microvolt = <1000000>;
92 regulator-max-microvolt = <1000000>;
93 regulator-always-on;
94 };
95
96 ldo16_reg: LDO16 {
97 regulator-name = "P1.8V_LDO_OUT16";
98 regulator-min-microvolt = <1800000>;
99 regulator-max-microvolt = <1800000>;
100 regulator-always-on;
101 };
102
103 buck1_reg: BUCK1 {
104 regulator-name = "vdd_mif";
105 regulator-min-microvolt = <950000>;
106 regulator-max-microvolt = <1300000>;
107 regulator-always-on;
108 regulator-boot-on;
109 };
110
111 buck2_reg: BUCK2 {
112 regulator-name = "vdd_arm";
113 regulator-min-microvolt = <850000>;
114 regulator-max-microvolt = <1350000>;
115 regulator-always-on;
116 regulator-boot-on;
117 };
118
119 buck3_reg: BUCK3 {
120 regulator-name = "vdd_int";
121 regulator-min-microvolt = <900000>;
122 regulator-max-microvolt = <1200000>;
123 regulator-always-on;
124 regulator-boot-on;
125 };
126
127 buck4_reg: BUCK4 {
128 regulator-name = "vdd_g3d";
129 regulator-min-microvolt = <850000>;
130 regulator-max-microvolt = <1300000>;
131 regulator-always-on;
132 regulator-boot-on;
133 };
134
135 buck5_reg: BUCK5 {
136 regulator-name = "P1.8V_BUCK_OUT5";
137 regulator-min-microvolt = <1800000>;
138 regulator-max-microvolt = <1800000>;
139 regulator-always-on;
140 regulator-boot-on;
141 };
142
143 buck6_reg: BUCK6 {
144 regulator-name = "P1.35V_BUCK_OUT6";
145 regulator-min-microvolt = <1350000>;
146 regulator-max-microvolt = <1350000>;
147 regulator-always-on;
148 };
149
150 buck7_reg: BUCK7 {
151 regulator-name = "P2.0V_BUCK_OUT7";
152 regulator-min-microvolt = <2000000>;
153 regulator-max-microvolt = <2000000>;
154 regulator-always-on;
155 };
156
157 buck8_reg: BUCK8 {
158 regulator-name = "P2.85V_BUCK_OUT8";
159 regulator-min-microvolt = <2850000>;
160 regulator-max-microvolt = <2850000>;
161 regulator-always-on;
162 };
163 };
164 };
27 }; 165 };
28 166
29 i2c@12C70000 { 167 i2c@12C70000 {
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 1a62bcf18aa3..9ac47d51c407 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -86,6 +86,8 @@
86 compatible = "samsung,s3c2410-wdt"; 86 compatible = "samsung,s3c2410-wdt";
87 reg = <0x10060000 0x100>; 87 reg = <0x10060000 0x100>;
88 interrupts = <0 43 0>; 88 interrupts = <0 43 0>;
89 clocks = <&clock 345>;
90 clock-names = "watchdog";
89 status = "disabled"; 91 status = "disabled";
90 }; 92 };
91 93
@@ -93,6 +95,8 @@
93 compatible = "samsung,s3c6410-rtc"; 95 compatible = "samsung,s3c6410-rtc";
94 reg = <0x10070000 0x100>; 96 reg = <0x10070000 0x100>;
95 interrupts = <0 44 0>, <0 45 0>; 97 interrupts = <0 44 0>, <0 45 0>;
98 clocks = <&clock 346>;
99 clock-names = "rtc";
96 status = "disabled"; 100 status = "disabled";
97 }; 101 };
98 102
@@ -100,6 +104,8 @@
100 compatible = "samsung,s5pv210-keypad"; 104 compatible = "samsung,s5pv210-keypad";
101 reg = <0x100A0000 0x100>; 105 reg = <0x100A0000 0x100>;
102 interrupts = <0 109 0>; 106 interrupts = <0 109 0>;
107 clocks = <&clock 347>;
108 clock-names = "keypad";
103 status = "disabled"; 109 status = "disabled";
104 }; 110 };
105 111
@@ -107,6 +113,8 @@
107 compatible = "samsung,exynos4210-sdhci"; 113 compatible = "samsung,exynos4210-sdhci";
108 reg = <0x12510000 0x100>; 114 reg = <0x12510000 0x100>;
109 interrupts = <0 73 0>; 115 interrupts = <0 73 0>;
116 clocks = <&clock 297>, <&clock 145>;
117 clock-names = "hsmmc", "mmc_busclk.2";
110 status = "disabled"; 118 status = "disabled";
111 }; 119 };
112 120
@@ -114,6 +122,8 @@
114 compatible = "samsung,exynos4210-sdhci"; 122 compatible = "samsung,exynos4210-sdhci";
115 reg = <0x12520000 0x100>; 123 reg = <0x12520000 0x100>;
116 interrupts = <0 74 0>; 124 interrupts = <0 74 0>;
125 clocks = <&clock 298>, <&clock 146>;
126 clock-names = "hsmmc", "mmc_busclk.2";
117 status = "disabled"; 127 status = "disabled";
118 }; 128 };
119 129
@@ -121,6 +131,8 @@
121 compatible = "samsung,exynos4210-sdhci"; 131 compatible = "samsung,exynos4210-sdhci";
122 reg = <0x12530000 0x100>; 132 reg = <0x12530000 0x100>;
123 interrupts = <0 75 0>; 133 interrupts = <0 75 0>;
134 clocks = <&clock 299>, <&clock 147>;
135 clock-names = "hsmmc", "mmc_busclk.2";
124 status = "disabled"; 136 status = "disabled";
125 }; 137 };
126 138
@@ -128,6 +140,16 @@
128 compatible = "samsung,exynos4210-sdhci"; 140 compatible = "samsung,exynos4210-sdhci";
129 reg = <0x12540000 0x100>; 141 reg = <0x12540000 0x100>;
130 interrupts = <0 76 0>; 142 interrupts = <0 76 0>;
143 clocks = <&clock 300>, <&clock 148>;
144 clock-names = "hsmmc", "mmc_busclk.2";
145 status = "disabled";
146 };
147
148 mfc: codec@13400000 {
149 compatible = "samsung,mfc-v5";
150 reg = <0x13400000 0x10000>;
151 interrupts = <0 94 0>;
152 samsung,power-domain = <&pd_mfc>;
131 status = "disabled"; 153 status = "disabled";
132 }; 154 };
133 155
@@ -135,6 +157,8 @@
135 compatible = "samsung,exynos4210-uart"; 157 compatible = "samsung,exynos4210-uart";
136 reg = <0x13800000 0x100>; 158 reg = <0x13800000 0x100>;
137 interrupts = <0 52 0>; 159 interrupts = <0 52 0>;
160 clocks = <&clock 312>, <&clock 151>;
161 clock-names = "uart", "clk_uart_baud0";
138 status = "disabled"; 162 status = "disabled";
139 }; 163 };
140 164
@@ -142,6 +166,8 @@
142 compatible = "samsung,exynos4210-uart"; 166 compatible = "samsung,exynos4210-uart";
143 reg = <0x13810000 0x100>; 167 reg = <0x13810000 0x100>;
144 interrupts = <0 53 0>; 168 interrupts = <0 53 0>;
169 clocks = <&clock 313>, <&clock 152>;
170 clock-names = "uart", "clk_uart_baud0";
145 status = "disabled"; 171 status = "disabled";
146 }; 172 };
147 173
@@ -149,6 +175,8 @@
149 compatible = "samsung,exynos4210-uart"; 175 compatible = "samsung,exynos4210-uart";
150 reg = <0x13820000 0x100>; 176 reg = <0x13820000 0x100>;
151 interrupts = <0 54 0>; 177 interrupts = <0 54 0>;
178 clocks = <&clock 314>, <&clock 153>;
179 clock-names = "uart", "clk_uart_baud0";
152 status = "disabled"; 180 status = "disabled";
153 }; 181 };
154 182
@@ -156,6 +184,8 @@
156 compatible = "samsung,exynos4210-uart"; 184 compatible = "samsung,exynos4210-uart";
157 reg = <0x13830000 0x100>; 185 reg = <0x13830000 0x100>;
158 interrupts = <0 55 0>; 186 interrupts = <0 55 0>;
187 clocks = <&clock 315>, <&clock 154>;
188 clock-names = "uart", "clk_uart_baud0";
159 status = "disabled"; 189 status = "disabled";
160 }; 190 };
161 191
@@ -165,6 +195,8 @@
165 compatible = "samsung,s3c2440-i2c"; 195 compatible = "samsung,s3c2440-i2c";
166 reg = <0x13860000 0x100>; 196 reg = <0x13860000 0x100>;
167 interrupts = <0 58 0>; 197 interrupts = <0 58 0>;
198 clocks = <&clock 317>;
199 clock-names = "i2c";
168 status = "disabled"; 200 status = "disabled";
169 }; 201 };
170 202
@@ -174,6 +206,8 @@
174 compatible = "samsung,s3c2440-i2c"; 206 compatible = "samsung,s3c2440-i2c";
175 reg = <0x13870000 0x100>; 207 reg = <0x13870000 0x100>;
176 interrupts = <0 59 0>; 208 interrupts = <0 59 0>;
209 clocks = <&clock 318>;
210 clock-names = "i2c";
177 status = "disabled"; 211 status = "disabled";
178 }; 212 };
179 213
@@ -183,6 +217,8 @@
183 compatible = "samsung,s3c2440-i2c"; 217 compatible = "samsung,s3c2440-i2c";
184 reg = <0x13880000 0x100>; 218 reg = <0x13880000 0x100>;
185 interrupts = <0 60 0>; 219 interrupts = <0 60 0>;
220 clocks = <&clock 319>;
221 clock-names = "i2c";
186 status = "disabled"; 222 status = "disabled";
187 }; 223 };
188 224
@@ -192,6 +228,8 @@
192 compatible = "samsung,s3c2440-i2c"; 228 compatible = "samsung,s3c2440-i2c";
193 reg = <0x13890000 0x100>; 229 reg = <0x13890000 0x100>;
194 interrupts = <0 61 0>; 230 interrupts = <0 61 0>;
231 clocks = <&clock 320>;
232 clock-names = "i2c";
195 status = "disabled"; 233 status = "disabled";
196 }; 234 };
197 235
@@ -201,6 +239,8 @@
201 compatible = "samsung,s3c2440-i2c"; 239 compatible = "samsung,s3c2440-i2c";
202 reg = <0x138A0000 0x100>; 240 reg = <0x138A0000 0x100>;
203 interrupts = <0 62 0>; 241 interrupts = <0 62 0>;
242 clocks = <&clock 321>;
243 clock-names = "i2c";
204 status = "disabled"; 244 status = "disabled";
205 }; 245 };
206 246
@@ -210,6 +250,8 @@
210 compatible = "samsung,s3c2440-i2c"; 250 compatible = "samsung,s3c2440-i2c";
211 reg = <0x138B0000 0x100>; 251 reg = <0x138B0000 0x100>;
212 interrupts = <0 63 0>; 252 interrupts = <0 63 0>;
253 clocks = <&clock 322>;
254 clock-names = "i2c";
213 status = "disabled"; 255 status = "disabled";
214 }; 256 };
215 257
@@ -219,6 +261,8 @@
219 compatible = "samsung,s3c2440-i2c"; 261 compatible = "samsung,s3c2440-i2c";
220 reg = <0x138C0000 0x100>; 262 reg = <0x138C0000 0x100>;
221 interrupts = <0 64 0>; 263 interrupts = <0 64 0>;
264 clocks = <&clock 323>;
265 clock-names = "i2c";
222 status = "disabled"; 266 status = "disabled";
223 }; 267 };
224 268
@@ -228,6 +272,8 @@
228 compatible = "samsung,s3c2440-i2c"; 272 compatible = "samsung,s3c2440-i2c";
229 reg = <0x138D0000 0x100>; 273 reg = <0x138D0000 0x100>;
230 interrupts = <0 65 0>; 274 interrupts = <0 65 0>;
275 clocks = <&clock 324>;
276 clock-names = "i2c";
231 status = "disabled"; 277 status = "disabled";
232 }; 278 };
233 279
@@ -239,6 +285,8 @@
239 rx-dma-channel = <&pdma0 6>; /* preliminary */ 285 rx-dma-channel = <&pdma0 6>; /* preliminary */
240 #address-cells = <1>; 286 #address-cells = <1>;
241 #size-cells = <0>; 287 #size-cells = <0>;
288 clocks = <&clock 327>, <&clock 159>;
289 clock-names = "spi", "spi_busclk0";
242 status = "disabled"; 290 status = "disabled";
243 }; 291 };
244 292
@@ -250,6 +298,8 @@
250 rx-dma-channel = <&pdma1 6>; /* preliminary */ 298 rx-dma-channel = <&pdma1 6>; /* preliminary */
251 #address-cells = <1>; 299 #address-cells = <1>;
252 #size-cells = <0>; 300 #size-cells = <0>;
301 clocks = <&clock 328>, <&clock 160>;
302 clock-names = "spi", "spi_busclk0";
253 status = "disabled"; 303 status = "disabled";
254 }; 304 };
255 305
@@ -261,6 +311,8 @@
261 rx-dma-channel = <&pdma0 8>; /* preliminary */ 311 rx-dma-channel = <&pdma0 8>; /* preliminary */
262 #address-cells = <1>; 312 #address-cells = <1>;
263 #size-cells = <0>; 313 #size-cells = <0>;
314 clocks = <&clock 329>, <&clock 161>;
315 clock-names = "spi", "spi_busclk0";
264 status = "disabled"; 316 status = "disabled";
265 }; 317 };
266 318
@@ -275,6 +327,8 @@
275 compatible = "arm,pl330", "arm,primecell"; 327 compatible = "arm,pl330", "arm,primecell";
276 reg = <0x12680000 0x1000>; 328 reg = <0x12680000 0x1000>;
277 interrupts = <0 35 0>; 329 interrupts = <0 35 0>;
330 clocks = <&clock 292>;
331 clock-names = "apb_pclk";
278 #dma-cells = <1>; 332 #dma-cells = <1>;
279 #dma-channels = <8>; 333 #dma-channels = <8>;
280 #dma-requests = <32>; 334 #dma-requests = <32>;
@@ -284,6 +338,8 @@
284 compatible = "arm,pl330", "arm,primecell"; 338 compatible = "arm,pl330", "arm,primecell";
285 reg = <0x12690000 0x1000>; 339 reg = <0x12690000 0x1000>;
286 interrupts = <0 36 0>; 340 interrupts = <0 36 0>;
341 clocks = <&clock 293>;
342 clock-names = "apb_pclk";
287 #dma-cells = <1>; 343 #dma-cells = <1>;
288 #dma-channels = <8>; 344 #dma-channels = <8>;
289 #dma-requests = <32>; 345 #dma-requests = <32>;
@@ -293,6 +349,8 @@
293 compatible = "arm,pl330", "arm,primecell"; 349 compatible = "arm,pl330", "arm,primecell";
294 reg = <0x12850000 0x1000>; 350 reg = <0x12850000 0x1000>;
295 interrupts = <0 34 0>; 351 interrupts = <0 34 0>;
352 clocks = <&clock 279>;
353 clock-names = "apb_pclk";
296 #dma-cells = <1>; 354 #dma-cells = <1>;
297 #dma-channels = <8>; 355 #dma-channels = <8>;
298 #dma-requests = <1>; 356 #dma-requests = <1>;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index f2710018e84e..1b30bc8e2654 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -57,6 +57,12 @@
57 status = "okay"; 57 status = "okay";
58 }; 58 };
59 59
60 codec@13400000 {
61 samsung,mfc-r = <0x43000000 0x800000>;
62 samsung,mfc-l = <0x51000000 0x800000>;
63 status = "okay";
64 };
65
60 serial@13800000 { 66 serial@13800000 {
61 status = "okay"; 67 status = "okay";
62 }; 68 };
@@ -121,4 +127,16 @@
121 linux,default-trigger = "heartbeat"; 127 linux,default-trigger = "heartbeat";
122 }; 128 };
123 }; 129 };
130
131 fixed-rate-clocks {
132 xxti {
133 compatible = "samsung,clock-xxti";
134 clock-frequency = <0>;
135 };
136
137 xusbxti {
138 compatible = "samsung,clock-xusbxti";
139 clock-frequency = <24000000>;
140 };
141 };
124}; 142};
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index f63490707f3a..f52c86e2d424 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -43,6 +43,12 @@
43 status = "okay"; 43 status = "okay";
44 }; 44 };
45 45
46 codec@13400000 {
47 samsung,mfc-r = <0x43000000 0x800000>;
48 samsung,mfc-l = <0x51000000 0x800000>;
49 status = "okay";
50 };
51
46 serial@13800000 { 52 serial@13800000 {
47 status = "okay"; 53 status = "okay";
48 }; 54 };
@@ -189,4 +195,16 @@
189 }; 195 };
190 }; 196 };
191 }; 197 };
198
199 fixed-rate-clocks {
200 xxti {
201 compatible = "samsung,clock-xxti";
202 clock-frequency = <12000000>;
203 };
204
205 xusbxti {
206 compatible = "samsung,clock-xusbxti";
207 clock-frequency = <24000000>;
208 };
209 };
192}; 210};
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index c346b64dff55..9a14484c7bb1 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -289,4 +289,16 @@
289 }; 289 };
290 }; 290 };
291 }; 291 };
292
293 fixed-rate-clocks {
294 xxti {
295 compatible = "samsung,clock-xxti";
296 clock-frequency = <0>;
297 };
298
299 xusbxti {
300 compatible = "samsung,clock-xusbxti";
301 clock-frequency = <24000000>;
302 };
303 };
292}; 304};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 49a2786e00b9..ff23ae29f5cf 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -55,6 +55,8 @@
55 interrupt-parent = <&mct_map>; 55 interrupt-parent = <&mct_map>;
56 interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 56 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
57 <4 0>, <5 0>; 57 <4 0>, <5 0>;
58 clocks = <&clock 3>, <&clock 344>;
59 clock-names = "fin_pll", "mct";
58 60
59 mct_map: mct-map { 61 mct_map: mct-map {
60 #interrupt-cells = <2>; 62 #interrupt-cells = <2>;
@@ -69,6 +71,12 @@
69 }; 71 };
70 }; 72 };
71 73
74 clock: clock-controller@0x10030000 {
75 compatible = "samsung,exynos4210-clock";
76 reg = <0x10030000 0x20000>;
77 #clock-cells = <1>;
78 };
79
72 pinctrl_0: pinctrl@11400000 { 80 pinctrl_0: pinctrl@11400000 {
73 compatible = "samsung,exynos4210-pinctrl"; 81 compatible = "samsung,exynos4210-pinctrl";
74 reg = <0x11400000 0x1000>; 82 reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
new file mode 100644
index 000000000000..53bc8bf77984
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -0,0 +1,111 @@
1/*
2 * Hardkernel's Exynos4412 based ODROID-X board device tree source
3 *
4 * Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com>
5 *
6 * Device tree source file for Hardkernel's ODROID-X board which is based on
7 * Samsung's Exynos4412 SoC.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14/dts-v1/;
15/include/ "exynos4412.dtsi"
16
17/ {
18 model = "Hardkernel ODROID-X board based on Exynos4412";
19 compatible = "hardkernel,odroid-x", "samsung,exynos4412";
20
21 memory {
22 reg = <0x40000000 0x40000000>;
23 };
24
25 leds {
26 compatible = "gpio-leds";
27 led1 {
28 label = "led1:heart";
29 gpios = <&gpc1 0 1>;
30 default-state = "on";
31 linux,default-trigger = "heartbeat";
32 };
33 led2 {
34 label = "led2:mmc0";
35 gpios = <&gpc1 2 1>;
36 default-state = "on";
37 linux,default-trigger = "mmc0";
38 };
39 };
40
41 mshc@12550000 {
42 #address-cells = <1>;
43 #size-cells = <0>;
44 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
45 pinctrl-names = "default";
46 status = "okay";
47
48 num-slots = <1>;
49 supports-highspeed;
50 broken-cd;
51 fifo-depth = <0x80>;
52 card-detect-delay = <200>;
53 samsung,dw-mshc-ciu-div = <3>;
54 samsung,dw-mshc-sdr-timing = <2 3>;
55 samsung,dw-mshc-ddr-timing = <1 2>;
56
57 slot@0 {
58 reg = <0>;
59 bus-width = <8>;
60 };
61 };
62
63 regulator_p3v3 {
64 compatible = "regulator-fixed";
65 regulator-name = "p3v3_en";
66 regulator-min-microvolt = <3300000>;
67 regulator-max-microvolt = <3300000>;
68 gpio = <&gpa1 1 1>;
69 enable-active-high;
70 regulator-boot-on;
71 };
72
73 rtc@10070000 {
74 status = "okay";
75 };
76
77 sdhci@12530000 {
78 bus-width = <4>;
79 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
80 pinctrl-names = "default";
81 status = "okay";
82 };
83
84 serial@13800000 {
85 status = "okay";
86 };
87
88 serial@13810000 {
89 status = "okay";
90 };
91
92 serial@13820000 {
93 status = "okay";
94 };
95
96 serial@13830000 {
97 status = "okay";
98 };
99
100 fixed-rate-clocks {
101 xxti {
102 compatible = "samsung,clock-xxti";
103 clock-frequency = <0>;
104 };
105
106 xusbxti {
107 compatible = "samsung,clock-xusbxti";
108 clock-frequency = <24000000>;
109 };
110 };
111};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
new file mode 100644
index 000000000000..1fecf7666dc0
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -0,0 +1,432 @@
1/*
2 * Insignal's Exynos4412 based Origen board device tree source
3 *
4 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Device tree source file for Insignal's Origen board which is based on
8 * Samsung's Exynos4412 SoC.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/dts-v1/;
16/include/ "exynos4412.dtsi"
17
18/ {
19 model = "Insignal Origen evaluation board based on Exynos4412";
20 compatible = "insignal,origen4412", "samsung,exynos4412";
21
22 memory {
23 reg = <0x40000000 0x40000000>;
24 };
25
26 chosen {
27 bootargs ="console=ttySAC2,115200";
28 };
29
30 mmc_reg: voltage-regulator {
31 compatible = "regulator-fixed";
32 regulator-name = "VMEM_VDD_2.8V";
33 regulator-min-microvolt = <2800000>;
34 regulator-max-microvolt = <2800000>;
35 gpio = <&gpx1 1 0>;
36 enable-active-high;
37 };
38
39 sdhci@12530000 {
40 bus-width = <4>;
41 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
42 pinctrl-names = "default";
43 vmmc-supply = <&mmc_reg>;
44 status = "okay";
45 };
46
47 mshc@12550000 {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
51 pinctrl-names = "default";
52 status = "okay";
53
54 num-slots = <1>;
55 supports-highspeed;
56 broken-cd;
57 fifo-depth = <0x80>;
58 card-detect-delay = <200>;
59 samsung,dw-mshc-ciu-div = <3>;
60 samsung,dw-mshc-sdr-timing = <2 3>;
61 samsung,dw-mshc-ddr-timing = <1 2>;
62
63 slot@0 {
64 reg = <0>;
65 bus-width = <8>;
66 };
67 };
68
69 codec@13400000 {
70 samsung,mfc-r = <0x43000000 0x800000>;
71 samsung,mfc-l = <0x51000000 0x800000>;
72 status = "okay";
73 };
74
75 serial@13800000 {
76 status = "okay";
77 };
78
79 serial@13810000 {
80 status = "okay";
81 };
82
83 serial@13820000 {
84 status = "okay";
85 };
86
87 serial@13830000 {
88 status = "okay";
89 };
90
91 i2c@13860000 {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 samsung,i2c-sda-delay = <100>;
95 samsung,i2c-max-bus-freq = <20000>;
96 pinctrl-0 = <&i2c0_bus>;
97 pinctrl-names = "default";
98 status = "okay";
99
100 s5m8767_pmic@66 {
101 compatible = "samsung,s5m8767-pmic";
102 reg = <0x66>;
103
104 s5m8767,pmic-buck-default-dvs-idx = <3>;
105
106 s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 0>,
107 <&gpx2 4 0>,
108 <&gpx2 5 0>;
109
110 s5m8767,pmic-buck-ds-gpios = <&gpm3 5 0>,
111 <&gpm3 6 0>,
112 <&gpm3 7 0>;
113
114 s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>,
115 <1200000>, <1200000>,
116 <1200000>, <1200000>,
117 <1200000>, <1200000>;
118
119 s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
120 <1100000>, <1100000>,
121 <1100000>, <1100000>,
122 <1100000>, <1100000>;
123
124 s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
125 <1200000>, <1200000>,
126 <1200000>, <1200000>,
127 <1200000>, <1200000>;
128
129 regulators {
130 ldo1_reg: LDO1 {
131 regulator-name = "VDD_ALIVE";
132 regulator-min-microvolt = <1100000>;
133 regulator-max-microvolt = <1100000>;
134 regulator-always-on;
135 regulator-boot-on;
136 op_mode = <1>; /* Normal Mode */
137 };
138
139 ldo2_reg: LDO2 {
140 regulator-name = "VDDQ_M12";
141 regulator-min-microvolt = <1200000>;
142 regulator-max-microvolt = <1200000>;
143 regulator-always-on;
144 op_mode = <1>; /* Normal Mode */
145 };
146
147 ldo3_reg: LDO3 {
148 regulator-name = "VDDIOAP_18";
149 regulator-min-microvolt = <1800000>;
150 regulator-max-microvolt = <1800000>;
151 regulator-always-on;
152 op_mode = <1>; /* Normal Mode */
153 };
154
155 ldo4_reg: LDO4 {
156 regulator-name = "VDDQ_PRE";
157 regulator-min-microvolt = <1800000>;
158 regulator-max-microvolt = <1800000>;
159 regulator-always-on;
160 op_mode = <1>; /* Normal Mode */
161 };
162
163 ldo5_reg: LDO5 {
164 regulator-name = "VDD18_2M";
165 regulator-min-microvolt = <1800000>;
166 regulator-max-microvolt = <1800000>;
167 regulator-always-on;
168 op_mode = <1>; /* Normal Mode */
169 };
170
171 ldo6_reg: LDO6 {
172 regulator-name = "VDD10_MPLL";
173 regulator-min-microvolt = <1000000>;
174 regulator-max-microvolt = <1000000>;
175 regulator-always-on;
176 op_mode = <1>; /* Normal Mode */
177 };
178
179 ldo7_reg: LDO7 {
180 regulator-name = "VDD10_XPLL";
181 regulator-min-microvolt = <1000000>;
182 regulator-max-microvolt = <1000000>;
183 regulator-always-on;
184 op_mode = <1>; /* Normal Mode */
185 };
186
187 ldo8_reg: LDO8 {
188 regulator-name = "VDD10_MIPI";
189 regulator-min-microvolt = <1000000>;
190 regulator-max-microvolt = <1000000>;
191 regulator-always-on;
192 op_mode = <1>; /* Normal Mode */
193 };
194
195 ldo9_reg: LDO9 {
196 regulator-name = "VDD33_LCD";
197 regulator-min-microvolt = <3300000>;
198 regulator-max-microvolt = <3300000>;
199 regulator-always-on;
200 op_mode = <1>; /* Normal Mode */
201 };
202
203 ldo10_reg: LDO10 {
204 regulator-name = "VDD18_MIPI";
205 regulator-min-microvolt = <1800000>;
206 regulator-max-microvolt = <1800000>;
207 regulator-always-on;
208 op_mode = <1>; /* Normal Mode */
209 };
210
211 ldo11_reg: LDO11 {
212 regulator-name = "VDD18_ABB1";
213 regulator-min-microvolt = <1800000>;
214 regulator-max-microvolt = <1800000>;
215 regulator-always-on;
216 op_mode = <1>; /* Normal Mode */
217 };
218
219 ldo12_reg: LDO12 {
220 regulator-name = "VDD33_UOTG";
221 regulator-min-microvolt = <3300000>;
222 regulator-max-microvolt = <3300000>;
223 regulator-always-on;
224 op_mode = <1>; /* Normal Mode */
225 };
226
227 ldo13_reg: LDO13 {
228 regulator-name = "VDDIOPERI_18";
229 regulator-min-microvolt = <1800000>;
230 regulator-max-microvolt = <1800000>;
231 regulator-always-on;
232 op_mode = <1>; /* Normal Mode */
233 };
234
235 ldo14_reg: LDO14 {
236 regulator-name = "VDD18_ABB02";
237 regulator-min-microvolt = <1800000>;
238 regulator-max-microvolt = <1800000>;
239 regulator-always-on;
240 op_mode = <1>; /* Normal Mode */
241 };
242
243 ldo15_reg: LDO15 {
244 regulator-name = "VDD10_USH";
245 regulator-min-microvolt = <1000000>;
246 regulator-max-microvolt = <1000000>;
247 regulator-always-on;
248 op_mode = <1>; /* Normal Mode */
249 };
250
251 ldo16_reg: LDO16 {
252 regulator-name = "VDD18_HSIC";
253 regulator-min-microvolt = <1800000>;
254 regulator-max-microvolt = <1800000>;
255 regulator-always-on;
256 op_mode = <1>; /* Normal Mode */
257 };
258
259 ldo17_reg: LDO17 {
260 regulator-name = "VDDIOAP_MMC012_28";
261 regulator-min-microvolt = <2800000>;
262 regulator-max-microvolt = <2800000>;
263 regulator-always-on;
264 op_mode = <1>; /* Normal Mode */
265 };
266
267 ldo18_reg: LDO18 {
268 regulator-name = "VDDIOPERI_28";
269 regulator-min-microvolt = <2800000>;
270 regulator-max-microvolt = <2800000>;
271 regulator-always-on;
272 op_mode = <1>; /* Normal Mode */
273 };
274
275 ldo19_reg: LDO19 {
276 regulator-name = "DVDD25";
277 regulator-min-microvolt = <2500000>;
278 regulator-max-microvolt = <2500000>;
279 regulator-always-on;
280 op_mode = <1>; /* Normal Mode */
281 };
282
283 ldo20_reg: LDO20 {
284 regulator-name = "VDD28_CAM";
285 regulator-min-microvolt = <2800000>;
286 regulator-max-microvolt = <2800000>;
287 regulator-always-on;
288 op_mode = <1>; /* Normal Mode */
289 };
290
291 ldo21_reg: LDO21 {
292 regulator-name = "VDD28_AF";
293 regulator-min-microvolt = <2800000>;
294 regulator-max-microvolt = <2800000>;
295 regulator-always-on;
296 op_mode = <1>; /* Normal Mode */
297 };
298
299 ldo22_reg: LDO22 {
300 regulator-name = "VDDA28_2M";
301 regulator-min-microvolt = <2800000>;
302 regulator-max-microvolt = <2800000>;
303 regulator-always-on;
304 op_mode = <1>; /* Normal Mode */
305 };
306
307 ldo23_reg: LDO23 {
308 regulator-name = "VDD28_TF";
309 regulator-min-microvolt = <2800000>;
310 regulator-max-microvolt = <2800000>;
311 regulator-always-on;
312 op_mode = <1>; /* Normal Mode */
313 };
314
315 ldo24_reg: LDO24 {
316 regulator-name = "VDD33_A31";
317 regulator-min-microvolt = <3300000>;
318 regulator-max-microvolt = <3300000>;
319 regulator-always-on;
320 op_mode = <1>; /* Normal Mode */
321 };
322
323 ldo25_reg: LDO25 {
324 regulator-name = "VDD18_CAM";
325 regulator-min-microvolt = <1800000>;
326 regulator-max-microvolt = <1800000>;
327 regulator-always-on;
328 op_mode = <1>; /* Normal Mode */
329 };
330
331 ldo26_reg: LDO26 {
332 regulator-name = "VDD18_A31";
333 regulator-min-microvolt = <1800000>;
334 regulator-max-microvolt = <1800000>;
335 regulator-always-on;
336 op_mode = <1>; /* Normal Mode */
337 };
338
339 ldo27_reg: LDO27 {
340 regulator-name = "GPS_1V8";
341 regulator-min-microvolt = <1800000>;
342 regulator-max-microvolt = <1800000>;
343 regulator-always-on;
344 op_mode = <1>; /* Normal Mode */
345 };
346
347 ldo28_reg: LDO28 {
348 regulator-name = "DVDD12";
349 regulator-min-microvolt = <1200000>;
350 regulator-max-microvolt = <1200000>;
351 regulator-always-on;
352 op_mode = <1>; /* Normal Mode */
353 };
354
355 buck1_reg: BUCK1 {
356 regulator-name = "vdd_mif";
357 regulator-min-microvolt = <950000>;
358 regulator-max-microvolt = <1100000>;
359 regulator-always-on;
360 regulator-boot-on;
361 op_mode = <1>; /* Normal Mode */
362 };
363
364 buck2_reg: BUCK2 {
365 regulator-name = "vdd_arm";
366 regulator-min-microvolt = <925000>;
367 regulator-max-microvolt = <1300000>;
368 regulator-always-on;
369 regulator-boot-on;
370 op_mode = <1>; /* Normal Mode */
371 };
372
373 buck3_reg: BUCK3 {
374 regulator-name = "vdd_int";
375 regulator-min-microvolt = <900000>;
376 regulator-max-microvolt = <1200000>;
377 regulator-always-on;
378 regulator-boot-on;
379 op_mode = <1>; /* Normal Mode */
380 };
381
382 buck4_reg: BUCK4 {
383 regulator-name = "vdd_g3d";
384 regulator-min-microvolt = <750000>;
385 regulator-max-microvolt = <1500000>;
386 regulator-always-on;
387 regulator-boot-on;
388 op_mode = <1>; /* Normal Mode */
389 };
390
391 buck5_reg: BUCK5 {
392 regulator-name = "vdd_m12";
393 regulator-min-microvolt = <750000>;
394 regulator-max-microvolt = <1500000>;
395 regulator-always-on;
396 regulator-boot-on;
397 op_mode = <1>; /* Normal Mode */
398 };
399
400 buck6_reg: BUCK6 {
401 regulator-name = "vdd12_5m";
402 regulator-min-microvolt = <750000>;
403 regulator-max-microvolt = <1500000>;
404 regulator-always-on;
405 regulator-boot-on;
406 op_mode = <1>; /* Normal Mode */
407 };
408
409 buck9_reg: BUCK9 {
410 regulator-name = "vddf28_emmc";
411 regulator-min-microvolt = <750000>;
412 regulator-max-microvolt = <3000000>;
413 regulator-always-on;
414 regulator-boot-on;
415 op_mode = <1>; /* Normal Mode */
416 };
417 };
418 };
419 };
420
421 fixed-rate-clocks {
422 xxti {
423 compatible = "samsung,clock-xxti";
424 clock-frequency = <0>;
425 };
426
427 xusbxti {
428 compatible = "samsung,clock-xusbxti";
429 clock-frequency = <24000000>;
430 };
431 };
432};
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index f05bf575cc45..874beeaef99d 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -27,6 +27,19 @@
27 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; 27 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
28 }; 28 };
29 29
30 sdhci@12530000 {
31 bus-width = <4>;
32 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
33 pinctrl-names = "default";
34 status = "okay";
35 };
36
37 codec@13400000 {
38 samsung,mfc-r = <0x43000000 0x800000>;
39 samsung,mfc-l = <0x51000000 0x800000>;
40 status = "okay";
41 };
42
30 serial@13800000 { 43 serial@13800000 {
31 status = "okay"; 44 status = "okay";
32 }; 45 };
@@ -42,4 +55,16 @@
42 serial@13830000 { 55 serial@13830000 {
43 status = "okay"; 56 status = "okay";
44 }; 57 };
58
59 fixed-rate-clocks {
60 xxti {
61 compatible = "samsung,clock-xxti";
62 clock-frequency = <0>;
63 };
64
65 xusbxti {
66 compatible = "samsung,clock-xusbxti";
67 clock-frequency = <24000000>;
68 };
69 };
45}; 70};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 821c9fdd1e3b..d75c047e80a9 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -34,6 +34,8 @@
34 interrupt-parent = <&mct_map>; 34 interrupt-parent = <&mct_map>;
35 interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 35 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
36 <4 0>, <5 0>, <6 0>, <7 0>; 36 <4 0>, <5 0>, <6 0>, <7 0>;
37 clocks = <&clock 3>, <&clock 344>;
38 clock-names = "fin_pll", "mct";
37 39
38 mct_map: mct-map { 40 mct_map: mct-map {
39 #interrupt-cells = <2>; 41 #interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 9a8780694909..7496b8d633ea 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -36,6 +36,12 @@
36 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>; 36 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
37 }; 37 };
38 38
39 clock: clock-controller@0x10030000 {
40 compatible = "samsung,exynos4412-clock";
41 reg = <0x10030000 0x20000>;
42 #clock-cells = <1>;
43 };
44
39 pinctrl_0: pinctrl@11400000 { 45 pinctrl_0: pinctrl@11400000 {
40 compatible = "samsung,exynos4x12-pinctrl"; 46 compatible = "samsung,exynos4x12-pinctrl";
41 reg = <0x11400000 0x1000>; 47 reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
new file mode 100644
index 000000000000..5de019cb0e58
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -0,0 +1,129 @@
1/*
2 * Samsung's Exynos5250 based Arndale board device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/dts-v1/;
13/include/ "exynos5250.dtsi"
14
15/ {
16 model = "Insignal Arndale evaluation board based on EXYNOS5250";
17 compatible = "insignal,arndale", "samsung,exynos5250";
18
19 memory {
20 reg = <0x40000000 0x80000000>;
21 };
22
23 chosen {
24 bootargs = "console=ttySAC2,115200";
25 };
26
27 i2c@12C60000 {
28 status = "disabled";
29 };
30
31 i2c@12C70000 {
32 status = "disabled";
33 };
34
35 i2c@12C80000 {
36 status = "disabled";
37 };
38
39 i2c@12C90000 {
40 status = "disabled";
41 };
42
43 i2c@12CA0000 {
44 status = "disabled";
45 };
46
47 i2c@12CB0000 {
48 status = "disabled";
49 };
50
51 i2c@12CC0000 {
52 status = "disabled";
53 };
54
55 i2c@12CD0000 {
56 status = "disabled";
57 };
58
59 i2c@121D0000 {
60 status = "disabled";
61 };
62
63 dwmmc_0: dwmmc0@12200000 {
64 num-slots = <1>;
65 supports-highspeed;
66 broken-cd;
67 fifo-depth = <0x80>;
68 card-detect-delay = <200>;
69 samsung,dw-mshc-ciu-div = <3>;
70 samsung,dw-mshc-sdr-timing = <2 3>;
71 samsung,dw-mshc-ddr-timing = <1 2>;
72
73 slot@0 {
74 reg = <0>;
75 bus-width = <8>;
76 gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
77 <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
78 <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>,
79 <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
80 <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>;
81 };
82 };
83
84 dwmmc_1: dwmmc1@12210000 {
85 status = "disabled";
86 };
87
88 dwmmc_2: dwmmc2@12220000 {
89 num-slots = <1>;
90 supports-highspeed;
91 fifo-depth = <0x80>;
92 card-detect-delay = <200>;
93 samsung,dw-mshc-ciu-div = <3>;
94 samsung,dw-mshc-sdr-timing = <2 3>;
95 samsung,dw-mshc-ddr-timing = <1 2>;
96
97 slot@0 {
98 reg = <0>;
99 bus-width = <4>;
100 samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
101 gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
102 <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
103 <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
104 };
105 };
106
107 dwmmc_3: dwmmc3@12230000 {
108 status = "disabled";
109 };
110
111 spi_0: spi@12d20000 {
112 status = "disabled";
113 };
114
115 spi_1: spi@12d30000 {
116 status = "disabled";
117 };
118
119 spi_2: spi@12d40000 {
120 status = "disabled";
121 };
122
123 fixed-rate-clocks {
124 xxti {
125 compatible = "samsung,clock-xxti";
126 clock-frequency = <24000000>;
127 };
128 };
129};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 1b8d4106d338..872ae1f93c75 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -231,4 +231,24 @@
231 samsung,i2s-controller = <&i2s0>; 231 samsung,i2s-controller = <&i2s0>;
232 samsung,audio-codec = <&wm8994>; 232 samsung,audio-codec = <&wm8994>;
233 }; 233 };
234
235 usb@12110000 {
236 samsung,vbus-gpio = <&gpx2 6 1 3 3>;
237 };
238
239 dp-controller {
240 samsung,color-space = <0>;
241 samsung,dynamic-range = <0>;
242 samsung,ycbcr-coeff = <0>;
243 samsung,color-depth = <1>;
244 samsung,link-rate = <0x0a>;
245 samsung,lane-count = <4>;
246 };
247
248 fixed-rate-clocks {
249 xxti {
250 compatible = "samsung,clock-xxti";
251 clock-frequency = <24000000>;
252 };
253 };
234}; 254};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 17dd951c1cd2..babd9f9b1bf9 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -40,4 +40,15 @@
40 <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>; 40 <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
41 }; 41 };
42 }; 42 };
43
44 usb@12110000 {
45 samsung,vbus-gpio = <&gpx1 1 1 3 3>;
46 };
47
48 fixed-rate-clocks {
49 xxti {
50 compatible = "samsung,clock-xxti";
51 clock-frequency = <24000000>;
52 };
53 };
43}; 54};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index c60108e0d27e..f8c9964f367c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -46,6 +46,22 @@
46 i2c8 = &i2c_8; 46 i2c8 = &i2c_8;
47 }; 47 };
48 48
49 pd_gsc: gsc-power-domain@0x10044000 {
50 compatible = "samsung,exynos4210-pd";
51 reg = <0x10044000 0x20>;
52 };
53
54 pd_mfc: mfc-power-domain@0x10044040 {
55 compatible = "samsung,exynos4210-pd";
56 reg = <0x10044040 0x20>;
57 };
58
59 clock: clock-controller@0x10010000 {
60 compatible = "samsung,exynos5250-clock";
61 reg = <0x10010000 0x30000>;
62 #clock-cells = <1>;
63 };
64
49 gic:interrupt-controller@10481000 { 65 gic:interrupt-controller@10481000 {
50 compatible = "arm,cortex-a9-gic"; 66 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>; 67 #interrupt-cells = <3>;
@@ -77,6 +93,8 @@
77 interrupt-parent = <&mct_map>; 93 interrupt-parent = <&mct_map>;
78 interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 94 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
79 <4 0>, <5 0>; 95 <4 0>, <5 0>;
96 clocks = <&clock 1>, <&clock 335>;
97 clock-names = "fin_pll", "mct";
80 98
81 mct_map: mct-map { 99 mct_map: mct-map {
82 #interrupt-cells = <2>; 100 #interrupt-cells = <2>;
@@ -95,54 +113,71 @@
95 compatible = "samsung,s3c2410-wdt"; 113 compatible = "samsung,s3c2410-wdt";
96 reg = <0x101D0000 0x100>; 114 reg = <0x101D0000 0x100>;
97 interrupts = <0 42 0>; 115 interrupts = <0 42 0>;
116 clocks = <&clock 336>;
117 clock-names = "watchdog";
98 }; 118 };
99 119
100 codec@11000000 { 120 codec@11000000 {
101 compatible = "samsung,mfc-v6"; 121 compatible = "samsung,mfc-v6";
102 reg = <0x11000000 0x10000>; 122 reg = <0x11000000 0x10000>;
103 interrupts = <0 96 0>; 123 interrupts = <0 96 0>;
124 samsung,power-domain = <&pd_mfc>;
104 }; 125 };
105 126
106 rtc { 127 rtc {
107 compatible = "samsung,s3c6410-rtc"; 128 compatible = "samsung,s3c6410-rtc";
108 reg = <0x101E0000 0x100>; 129 reg = <0x101E0000 0x100>;
109 interrupts = <0 43 0>, <0 44 0>; 130 interrupts = <0 43 0>, <0 44 0>;
131 clocks = <&clock 337>;
132 clock-names = "rtc";
110 }; 133 };
111 134
112 tmu@10060000 { 135 tmu@10060000 {
113 compatible = "samsung,exynos5250-tmu"; 136 compatible = "samsung,exynos5250-tmu";
114 reg = <0x10060000 0x100>; 137 reg = <0x10060000 0x100>;
115 interrupts = <0 65 0>; 138 interrupts = <0 65 0>;
139 clocks = <&clock 338>;
140 clock-names = "tmu_apbif";
116 }; 141 };
117 142
118 serial@12C00000 { 143 serial@12C00000 {
119 compatible = "samsung,exynos4210-uart"; 144 compatible = "samsung,exynos4210-uart";
120 reg = <0x12C00000 0x100>; 145 reg = <0x12C00000 0x100>;
121 interrupts = <0 51 0>; 146 interrupts = <0 51 0>;
147 clocks = <&clock 289>, <&clock 146>;
148 clock-names = "uart", "clk_uart_baud0";
122 }; 149 };
123 150
124 serial@12C10000 { 151 serial@12C10000 {
125 compatible = "samsung,exynos4210-uart"; 152 compatible = "samsung,exynos4210-uart";
126 reg = <0x12C10000 0x100>; 153 reg = <0x12C10000 0x100>;
127 interrupts = <0 52 0>; 154 interrupts = <0 52 0>;
155 clocks = <&clock 290>, <&clock 147>;
156 clock-names = "uart", "clk_uart_baud0";
128 }; 157 };
129 158
130 serial@12C20000 { 159 serial@12C20000 {
131 compatible = "samsung,exynos4210-uart"; 160 compatible = "samsung,exynos4210-uart";
132 reg = <0x12C20000 0x100>; 161 reg = <0x12C20000 0x100>;
133 interrupts = <0 53 0>; 162 interrupts = <0 53 0>;
163 clocks = <&clock 291>, <&clock 148>;
164 clock-names = "uart", "clk_uart_baud0";
134 }; 165 };
135 166
136 serial@12C30000 { 167 serial@12C30000 {
137 compatible = "samsung,exynos4210-uart"; 168 compatible = "samsung,exynos4210-uart";
138 reg = <0x12C30000 0x100>; 169 reg = <0x12C30000 0x100>;
139 interrupts = <0 54 0>; 170 interrupts = <0 54 0>;
171 clocks = <&clock 292>, <&clock 149>;
172 clock-names = "uart", "clk_uart_baud0";
140 }; 173 };
141 174
142 sata@122F0000 { 175 sata@122F0000 {
143 compatible = "samsung,exynos5-sata-ahci"; 176 compatible = "samsung,exynos5-sata-ahci";
144 reg = <0x122F0000 0x1ff>; 177 reg = <0x122F0000 0x1ff>;
145 interrupts = <0 115 0>; 178 interrupts = <0 115 0>;
179 clocks = <&clock 277>, <&clock 143>;
180 clock-names = "sata", "sclk_sata";
146 }; 181 };
147 182
148 sata-phy@12170000 { 183 sata-phy@12170000 {
@@ -156,6 +191,8 @@
156 interrupts = <0 56 0>; 191 interrupts = <0 56 0>;
157 #address-cells = <1>; 192 #address-cells = <1>;
158 #size-cells = <0>; 193 #size-cells = <0>;
194 clocks = <&clock 294>;
195 clock-names = "i2c";
159 }; 196 };
160 197
161 i2c_1: i2c@12C70000 { 198 i2c_1: i2c@12C70000 {
@@ -164,6 +201,8 @@
164 interrupts = <0 57 0>; 201 interrupts = <0 57 0>;
165 #address-cells = <1>; 202 #address-cells = <1>;
166 #size-cells = <0>; 203 #size-cells = <0>;
204 clocks = <&clock 295>;
205 clock-names = "i2c";
167 }; 206 };
168 207
169 i2c_2: i2c@12C80000 { 208 i2c_2: i2c@12C80000 {
@@ -172,6 +211,8 @@
172 interrupts = <0 58 0>; 211 interrupts = <0 58 0>;
173 #address-cells = <1>; 212 #address-cells = <1>;
174 #size-cells = <0>; 213 #size-cells = <0>;
214 clocks = <&clock 296>;
215 clock-names = "i2c";
175 }; 216 };
176 217
177 i2c_3: i2c@12C90000 { 218 i2c_3: i2c@12C90000 {
@@ -180,6 +221,8 @@
180 interrupts = <0 59 0>; 221 interrupts = <0 59 0>;
181 #address-cells = <1>; 222 #address-cells = <1>;
182 #size-cells = <0>; 223 #size-cells = <0>;
224 clocks = <&clock 297>;
225 clock-names = "i2c";
183 }; 226 };
184 227
185 i2c_4: i2c@12CA0000 { 228 i2c_4: i2c@12CA0000 {
@@ -188,6 +231,8 @@
188 interrupts = <0 60 0>; 231 interrupts = <0 60 0>;
189 #address-cells = <1>; 232 #address-cells = <1>;
190 #size-cells = <0>; 233 #size-cells = <0>;
234 clocks = <&clock 298>;
235 clock-names = "i2c";
191 }; 236 };
192 237
193 i2c_5: i2c@12CB0000 { 238 i2c_5: i2c@12CB0000 {
@@ -196,6 +241,8 @@
196 interrupts = <0 61 0>; 241 interrupts = <0 61 0>;
197 #address-cells = <1>; 242 #address-cells = <1>;
198 #size-cells = <0>; 243 #size-cells = <0>;
244 clocks = <&clock 299>;
245 clock-names = "i2c";
199 }; 246 };
200 247
201 i2c_6: i2c@12CC0000 { 248 i2c_6: i2c@12CC0000 {
@@ -204,6 +251,8 @@
204 interrupts = <0 62 0>; 251 interrupts = <0 62 0>;
205 #address-cells = <1>; 252 #address-cells = <1>;
206 #size-cells = <0>; 253 #size-cells = <0>;
254 clocks = <&clock 300>;
255 clock-names = "i2c";
207 }; 256 };
208 257
209 i2c_7: i2c@12CD0000 { 258 i2c_7: i2c@12CD0000 {
@@ -212,6 +261,8 @@
212 interrupts = <0 63 0>; 261 interrupts = <0 63 0>;
213 #address-cells = <1>; 262 #address-cells = <1>;
214 #size-cells = <0>; 263 #size-cells = <0>;
264 clocks = <&clock 301>;
265 clock-names = "i2c";
215 }; 266 };
216 267
217 i2c_8: i2c@12CE0000 { 268 i2c_8: i2c@12CE0000 {
@@ -220,6 +271,8 @@
220 interrupts = <0 64 0>; 271 interrupts = <0 64 0>;
221 #address-cells = <1>; 272 #address-cells = <1>;
222 #size-cells = <0>; 273 #size-cells = <0>;
274 clocks = <&clock 302>;
275 clock-names = "i2c";
223 }; 276 };
224 277
225 i2c@121D0000 { 278 i2c@121D0000 {
@@ -227,6 +280,8 @@
227 reg = <0x121D0000 0x100>; 280 reg = <0x121D0000 0x100>;
228 #address-cells = <1>; 281 #address-cells = <1>;
229 #size-cells = <0>; 282 #size-cells = <0>;
283 clocks = <&clock 288>;
284 clock-names = "i2c";
230 }; 285 };
231 286
232 spi_0: spi@12d20000 { 287 spi_0: spi@12d20000 {
@@ -238,6 +293,8 @@
238 dma-names = "tx", "rx"; 293 dma-names = "tx", "rx";
239 #address-cells = <1>; 294 #address-cells = <1>;
240 #size-cells = <0>; 295 #size-cells = <0>;
296 clocks = <&clock 304>, <&clock 154>;
297 clock-names = "spi", "spi_busclk0";
241 }; 298 };
242 299
243 spi_1: spi@12d30000 { 300 spi_1: spi@12d30000 {
@@ -249,6 +306,8 @@
249 dma-names = "tx", "rx"; 306 dma-names = "tx", "rx";
250 #address-cells = <1>; 307 #address-cells = <1>;
251 #size-cells = <0>; 308 #size-cells = <0>;
309 clocks = <&clock 305>, <&clock 155>;
310 clock-names = "spi", "spi_busclk0";
252 }; 311 };
253 312
254 spi_2: spi@12d40000 { 313 spi_2: spi@12d40000 {
@@ -260,6 +319,8 @@
260 dma-names = "tx", "rx"; 319 dma-names = "tx", "rx";
261 #address-cells = <1>; 320 #address-cells = <1>;
262 #size-cells = <0>; 321 #size-cells = <0>;
322 clocks = <&clock 306>, <&clock 156>;
323 clock-names = "spi", "spi_busclk0";
263 }; 324 };
264 325
265 dwmmc_0: dwmmc0@12200000 { 326 dwmmc_0: dwmmc0@12200000 {
@@ -268,6 +329,8 @@
268 interrupts = <0 75 0>; 329 interrupts = <0 75 0>;
269 #address-cells = <1>; 330 #address-cells = <1>;
270 #size-cells = <0>; 331 #size-cells = <0>;
332 clocks = <&clock 280>, <&clock 139>;
333 clock-names = "biu", "ciu";
271 }; 334 };
272 335
273 dwmmc_1: dwmmc1@12210000 { 336 dwmmc_1: dwmmc1@12210000 {
@@ -276,6 +339,8 @@
276 interrupts = <0 76 0>; 339 interrupts = <0 76 0>;
277 #address-cells = <1>; 340 #address-cells = <1>;
278 #size-cells = <0>; 341 #size-cells = <0>;
342 clocks = <&clock 281>, <&clock 140>;
343 clock-names = "biu", "ciu";
279 }; 344 };
280 345
281 dwmmc_2: dwmmc2@12220000 { 346 dwmmc_2: dwmmc2@12220000 {
@@ -284,6 +349,8 @@
284 interrupts = <0 77 0>; 349 interrupts = <0 77 0>;
285 #address-cells = <1>; 350 #address-cells = <1>;
286 #size-cells = <0>; 351 #size-cells = <0>;
352 clocks = <&clock 282>, <&clock 141>;
353 clock-names = "biu", "ciu";
287 }; 354 };
288 355
289 dwmmc_3: dwmmc3@12230000 { 356 dwmmc_3: dwmmc3@12230000 {
@@ -292,6 +359,8 @@
292 interrupts = <0 78 0>; 359 interrupts = <0 78 0>;
293 #address-cells = <1>; 360 #address-cells = <1>;
294 #size-cells = <0>; 361 #size-cells = <0>;
362 clocks = <&clock 283>, <&clock 142>;
363 clock-names = "biu", "ciu";
295 }; 364 };
296 365
297 i2s0: i2s@03830000 { 366 i2s0: i2s@03830000 {
@@ -323,6 +392,18 @@
323 dma-names = "tx", "rx"; 392 dma-names = "tx", "rx";
324 }; 393 };
325 394
395 usb@12110000 {
396 compatible = "samsung,exynos4210-ehci";
397 reg = <0x12110000 0x100>;
398 interrupts = <0 71 0>;
399 };
400
401 usb@12120000 {
402 compatible = "samsung,exynos4210-ohci";
403 reg = <0x12120000 0x100>;
404 interrupts = <0 71 0>;
405 };
406
326 amba { 407 amba {
327 #address-cells = <1>; 408 #address-cells = <1>;
328 #size-cells = <1>; 409 #size-cells = <1>;
@@ -334,6 +415,8 @@
334 compatible = "arm,pl330", "arm,primecell"; 415 compatible = "arm,pl330", "arm,primecell";
335 reg = <0x121A0000 0x1000>; 416 reg = <0x121A0000 0x1000>;
336 interrupts = <0 34 0>; 417 interrupts = <0 34 0>;
418 clocks = <&clock 275>;
419 clock-names = "apb_pclk";
337 #dma-cells = <1>; 420 #dma-cells = <1>;
338 #dma-channels = <8>; 421 #dma-channels = <8>;
339 #dma-requests = <32>; 422 #dma-requests = <32>;
@@ -343,6 +426,8 @@
343 compatible = "arm,pl330", "arm,primecell"; 426 compatible = "arm,pl330", "arm,primecell";
344 reg = <0x121B0000 0x1000>; 427 reg = <0x121B0000 0x1000>;
345 interrupts = <0 35 0>; 428 interrupts = <0 35 0>;
429 clocks = <&clock 276>;
430 clock-names = "apb_pclk";
346 #dma-cells = <1>; 431 #dma-cells = <1>;
347 #dma-channels = <8>; 432 #dma-channels = <8>;
348 #dma-requests = <32>; 433 #dma-requests = <32>;
@@ -352,6 +437,8 @@
352 compatible = "arm,pl330", "arm,primecell"; 437 compatible = "arm,pl330", "arm,primecell";
353 reg = <0x10800000 0x1000>; 438 reg = <0x10800000 0x1000>;
354 interrupts = <0 33 0>; 439 interrupts = <0 33 0>;
440 clocks = <&clock 271>;
441 clock-names = "apb_pclk";
355 #dma-cells = <1>; 442 #dma-cells = <1>;
356 #dma-channels = <8>; 443 #dma-channels = <8>;
357 #dma-requests = <1>; 444 #dma-requests = <1>;
@@ -361,6 +448,8 @@
361 compatible = "arm,pl330", "arm,primecell"; 448 compatible = "arm,pl330", "arm,primecell";
362 reg = <0x11C10000 0x1000>; 449 reg = <0x11C10000 0x1000>;
363 interrupts = <0 124 0>; 450 interrupts = <0 124 0>;
451 clocks = <&clock 271>;
452 clock-names = "apb_pclk";
364 #dma-cells = <1>; 453 #dma-cells = <1>;
365 #dma-channels = <8>; 454 #dma-channels = <8>;
366 #dma-requests = <1>; 455 #dma-requests = <1>;
@@ -614,34 +703,51 @@
614 }; 703 };
615 }; 704 };
616 705
706
617 gsc_0: gsc@0x13e00000 { 707 gsc_0: gsc@0x13e00000 {
618 compatible = "samsung,exynos5-gsc"; 708 compatible = "samsung,exynos5-gsc";
619 reg = <0x13e00000 0x1000>; 709 reg = <0x13e00000 0x1000>;
620 interrupts = <0 85 0>; 710 interrupts = <0 85 0>;
711 samsung,power-domain = <&pd_gsc>;
712 clocks = <&clock 256>;
713 clock-names = "gscl";
621 }; 714 };
622 715
623 gsc_1: gsc@0x13e10000 { 716 gsc_1: gsc@0x13e10000 {
624 compatible = "samsung,exynos5-gsc"; 717 compatible = "samsung,exynos5-gsc";
625 reg = <0x13e10000 0x1000>; 718 reg = <0x13e10000 0x1000>;
626 interrupts = <0 86 0>; 719 interrupts = <0 86 0>;
720 samsung,power-domain = <&pd_gsc>;
721 clocks = <&clock 257>;
722 clock-names = "gscl";
627 }; 723 };
628 724
629 gsc_2: gsc@0x13e20000 { 725 gsc_2: gsc@0x13e20000 {
630 compatible = "samsung,exynos5-gsc"; 726 compatible = "samsung,exynos5-gsc";
631 reg = <0x13e20000 0x1000>; 727 reg = <0x13e20000 0x1000>;
632 interrupts = <0 87 0>; 728 interrupts = <0 87 0>;
729 samsung,power-domain = <&pd_gsc>;
730 clocks = <&clock 258>;
731 clock-names = "gscl";
633 }; 732 };
634 733
635 gsc_3: gsc@0x13e30000 { 734 gsc_3: gsc@0x13e30000 {
636 compatible = "samsung,exynos5-gsc"; 735 compatible = "samsung,exynos5-gsc";
637 reg = <0x13e30000 0x1000>; 736 reg = <0x13e30000 0x1000>;
638 interrupts = <0 88 0>; 737 interrupts = <0 88 0>;
738 samsung,power-domain = <&pd_gsc>;
739 clocks = <&clock 259>;
740 clock-names = "gscl";
639 }; 741 };
640 742
641 hdmi { 743 hdmi {
642 compatible = "samsung,exynos5-hdmi"; 744 compatible = "samsung,exynos5-hdmi";
643 reg = <0x14530000 0x70000>; 745 reg = <0x14530000 0x70000>;
644 interrupts = <0 95 0>; 746 interrupts = <0 95 0>;
747 clocks = <&clock 333>, <&clock 136>, <&clock 137>,
748 <&clock 333>, <&clock 333>;
749 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
750 "sclk_hdmiphy", "hdmiphy";
645 }; 751 };
646 752
647 mixer { 753 mixer {
@@ -649,4 +755,18 @@
649 reg = <0x14450000 0x10000>; 755 reg = <0x14450000 0x10000>;
650 interrupts = <0 94 0>; 756 interrupts = <0 94 0>;
651 }; 757 };
758
759 dp-controller {
760 compatible = "samsung,exynos5-dp";
761 reg = <0x145b0000 0x1000>;
762 interrupts = <10 3>;
763 interrupt-parent = <&combiner>;
764 #address-cells = <1>;
765 #size-cells = <0>;
766
767 dptx-phy {
768 reg = <0x10040720>;
769 samsung,enable-mask = <1>;
770 };
771 };
652}; 772};
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index 81e2c964a900..a21eb4cbe893 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -28,19 +28,10 @@
28 status = "disabled"; 28 status = "disabled";
29 }; 29 };
30 30
31 i2c@F0000 { 31 fixed-rate-clocks {
32 status = "disabled"; 32 xtal {
33 }; 33 compatible = "samsung,clock-xtal";
34 34 clock-frequency = <50000000>;
35 i2c@100000 { 35 };
36 status = "disabled";
37 };
38
39 watchdog {
40 status = "disabled";
41 };
42
43 rtc {
44 status = "disabled";
45 }; 36 };
46}; 37};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 9a99755920c0..c374a31e9c3d 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -16,6 +16,12 @@
16 16
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 18
19 clock: clock-controller@0x160000 {
20 compatible = "samsung,exynos5440-clock";
21 reg = <0x160000 0x1000>;
22 #clock-cells = <1>;
23 };
24
19 gic:interrupt-controller@2E0000 { 25 gic:interrupt-controller@2E0000 {
20 compatible = "arm,cortex-a15-gic"; 26 compatible = "arm,cortex-a15-gic";
21 #interrupt-cells = <3>; 27 #interrupt-cells = <3>;
@@ -24,55 +30,51 @@
24 }; 30 };
25 31
26 cpus { 32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
27 cpu@0 { 36 cpu@0 {
28 compatible = "arm,cortex-a15"; 37 compatible = "arm,cortex-a15";
29 timer { 38 reg = <0>;
30 compatible = "arm,armv7-timer";
31 interrupts = <1 13 0xf08>;
32 clock-frequency = <1000000>;
33 };
34 }; 39 };
35 cpu@1 { 40 cpu@1 {
36 compatible = "arm,cortex-a15"; 41 compatible = "arm,cortex-a15";
37 timer { 42 reg = <1>;
38 compatible = "arm,armv7-timer";
39 interrupts = <1 14 0xf08>;
40 clock-frequency = <1000000>;
41 };
42 }; 43 };
43 cpu@2 { 44 cpu@2 {
44 compatible = "arm,cortex-a15"; 45 compatible = "arm,cortex-a15";
45 timer { 46 reg = <2>;
46 compatible = "arm,armv7-timer";
47 interrupts = <1 14 0xf08>;
48 clock-frequency = <1000000>;
49 };
50 }; 47 };
51 cpu@3 { 48 cpu@3 {
52 compatible = "arm,cortex-a15"; 49 compatible = "arm,cortex-a15";
53 timer { 50 reg = <3>;
54 compatible = "arm,armv7-timer";
55 interrupts = <1 14 0xf08>;
56 clock-frequency = <1000000>;
57 };
58 }; 51 };
59 }; 52 };
60 53
61 common { 54 timer {
62 compatible = "samsung,exynos5440"; 55 compatible = "arm,cortex-a15-timer",
63 56 "arm,armv7-timer";
57 interrupts = <1 13 0xf08>,
58 <1 14 0xf08>,
59 <1 11 0xf08>,
60 <1 10 0xf08>;
61 clock-frequency = <50000000>;
64 }; 62 };
65 63
66 serial@B0000 { 64 serial@B0000 {
67 compatible = "samsung,exynos4210-uart"; 65 compatible = "samsung,exynos4210-uart";
68 reg = <0xB0000 0x1000>; 66 reg = <0xB0000 0x1000>;
69 interrupts = <0 2 0>; 67 interrupts = <0 2 0>;
68 clocks = <&clock 21>, <&clock 21>;
69 clock-names = "uart", "clk_uart_baud0";
70 }; 70 };
71 71
72 serial@C0000 { 72 serial@C0000 {
73 compatible = "samsung,exynos4210-uart"; 73 compatible = "samsung,exynos4210-uart";
74 reg = <0xC0000 0x1000>; 74 reg = <0xC0000 0x1000>;
75 interrupts = <0 3 0>; 75 interrupts = <0 3 0>;
76 clocks = <&clock 21>, <&clock 21>;
77 clock-names = "uart", "clk_uart_baud0";
76 }; 78 };
77 79
78 spi { 80 spi {
@@ -83,6 +85,8 @@
83 rx-dma-channel = <&pdma0 4>; /* preliminary */ 85 rx-dma-channel = <&pdma0 4>; /* preliminary */
84 #address-cells = <1>; 86 #address-cells = <1>;
85 #size-cells = <0>; 87 #size-cells = <0>;
88 clocks = <&clock 21>, <&clock 16>;
89 clock-names = "spi", "spi_busclk0";
86 }; 90 };
87 91
88 pinctrl { 92 pinctrl {
@@ -110,25 +114,31 @@
110 }; 114 };
111 115
112 i2c@F0000 { 116 i2c@F0000 {
113 compatible = "samsung,s3c2440-i2c"; 117 compatible = "samsung,exynos5440-i2c";
114 reg = <0xF0000 0x1000>; 118 reg = <0xF0000 0x1000>;
115 interrupts = <0 5 0>; 119 interrupts = <0 5 0>;
116 #address-cells = <1>; 120 #address-cells = <1>;
117 #size-cells = <0>; 121 #size-cells = <0>;
122 clocks = <&clock 21>;
123 clock-names = "i2c";
118 }; 124 };
119 125
120 i2c@100000 { 126 i2c@100000 {
121 compatible = "samsung,s3c2440-i2c"; 127 compatible = "samsung,exynos5440-i2c";
122 reg = <0x100000 0x1000>; 128 reg = <0x100000 0x1000>;
123 interrupts = <0 6 0>; 129 interrupts = <0 6 0>;
124 #address-cells = <1>; 130 #address-cells = <1>;
125 #size-cells = <0>; 131 #size-cells = <0>;
132 clocks = <&clock 21>;
133 clock-names = "i2c";
126 }; 134 };
127 135
128 watchdog { 136 watchdog {
129 compatible = "samsung,s3c2410-wdt"; 137 compatible = "samsung,s3c2410-wdt";
130 reg = <0x110000 0x1000>; 138 reg = <0x110000 0x1000>;
131 interrupts = <0 1 0>; 139 interrupts = <0 1 0>;
140 clocks = <&clock 21>;
141 clock-names = "watchdog";
132 }; 142 };
133 143
134 amba { 144 amba {
@@ -142,6 +152,8 @@
142 compatible = "arm,pl330", "arm,primecell"; 152 compatible = "arm,pl330", "arm,primecell";
143 reg = <0x120000 0x1000>; 153 reg = <0x120000 0x1000>;
144 interrupts = <0 34 0>; 154 interrupts = <0 34 0>;
155 clocks = <&clock 21>;
156 clock-names = "apb_pclk";
145 #dma-cells = <1>; 157 #dma-cells = <1>;
146 #dma-channels = <8>; 158 #dma-channels = <8>;
147 #dma-requests = <32>; 159 #dma-requests = <32>;
@@ -151,6 +163,8 @@
151 compatible = "arm,pl330", "arm,primecell"; 163 compatible = "arm,pl330", "arm,primecell";
152 reg = <0x121000 0x1000>; 164 reg = <0x121000 0x1000>;
153 interrupts = <0 35 0>; 165 interrupts = <0 35 0>;
166 clocks = <&clock 21>;
167 clock-names = "apb_pclk";
154 #dma-cells = <1>; 168 #dma-cells = <1>;
155 #dma-channels = <8>; 169 #dma-channels = <8>;
156 #dma-requests = <32>; 170 #dma-requests = <32>;
@@ -161,5 +175,7 @@
161 compatible = "samsung,s3c6410-rtc"; 175 compatible = "samsung,s3c6410-rtc";
162 reg = <0x130000 0x1000>; 176 reg = <0x130000 0x1000>;
163 interrupts = <0 17 0>, <0 16 0>; 177 interrupts = <0 17 0>, <0 16 0>;
178 clocks = <&clock 21>;
179 clock-names = "rtc";
164 }; 180 };
165}; 181};
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index faca4326b46a..ef3b69a6277c 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -61,6 +61,7 @@ config SOC_EXYNOS5250
61 bool "SAMSUNG EXYNOS5250" 61 bool "SAMSUNG EXYNOS5250"
62 default y 62 default y
63 depends on ARCH_EXYNOS5 63 depends on ARCH_EXYNOS5
64 select PM_GENERIC_DOMAINS if PM
64 select S5P_PM if PM 65 select S5P_PM if PM
65 select S5P_SLEEP if PM 66 select S5P_SLEEP if PM
66 select S5P_DEV_MFC 67 select S5P_DEV_MFC
@@ -405,6 +406,7 @@ config MACH_EXYNOS4_DT
405 select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD 406 select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
406 select PINCTRL 407 select PINCTRL
407 select PINCTRL_EXYNOS 408 select PINCTRL_EXYNOS
409 select S5P_DEV_MFC
408 select USE_OF 410 select USE_OF
409 help 411 help
410 Machine support for Samsung Exynos4 machine with device tree enabled. 412 Machine support for Samsung Exynos4 machine with device tree enabled.
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index daf289b21486..d2f6b362b6dd 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -13,10 +13,6 @@ obj- :=
13# Core 13# Core
14 14
15obj-$(CONFIG_ARCH_EXYNOS) += common.o 15obj-$(CONFIG_ARCH_EXYNOS) += common.o
16obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
17obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
18obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
19obj-$(CONFIG_SOC_EXYNOS5250) += clock-exynos5.o
20 16
21obj-$(CONFIG_PM) += pm.o 17obj-$(CONFIG_PM) += pm.o
22obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o 18obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
deleted file mode 100644
index 8a8468d83c8c..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ /dev/null
@@ -1,1601 +0,0 @@
1/*
2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS4 - Clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/syscore_ops.h>
16
17#include <plat/cpu-freq.h>
18#include <plat/clock.h>
19#include <plat/cpu.h>
20#include <plat/pll.h>
21#include <plat/s5p-clock.h>
22#include <plat/clock-clksrc.h>
23#include <plat/pm.h>
24
25#include <mach/map.h>
26#include <mach/regs-clock.h>
27
28#include "common.h"
29#include "clock-exynos4.h"
30
31#ifdef CONFIG_PM_SLEEP
32static struct sleep_save exynos4_clock_save[] = {
33 SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
34 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
35 SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
36 SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
37 SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
38 SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
39 SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
40 SAVE_ITEM(EXYNOS4_CLKSRC_TV),
41 SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
42 SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
43 SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
44 SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
45 SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
46 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
47 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
48 SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
49 SAVE_ITEM(EXYNOS4_CLKDIV_TV),
50 SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
51 SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
52 SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
53 SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
54 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
55 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
56 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
57 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
58 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
59 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
60 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
61 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
62 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
63 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
64 SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
65 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
66 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
67 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
68 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
69 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
70 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
71 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
72 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
73 SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
74 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
75 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
76 SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
77 SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
78 SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
79 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
80 SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
81 SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
82 SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
83 SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
84 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
85 SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
86 SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
87 SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
88 SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
89 SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
90 SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
91 SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
92 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
93 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
94};
95#endif
96
97static struct clk exynos4_clk_sclk_hdmi27m = {
98 .name = "sclk_hdmi27m",
99 .rate = 27000000,
100};
101
102static struct clk exynos4_clk_sclk_hdmiphy = {
103 .name = "sclk_hdmiphy",
104};
105
106static struct clk exynos4_clk_sclk_usbphy0 = {
107 .name = "sclk_usbphy0",
108 .rate = 27000000,
109};
110
111static struct clk exynos4_clk_sclk_usbphy1 = {
112 .name = "sclk_usbphy1",
113};
114
115static struct clk dummy_apb_pclk = {
116 .name = "apb_pclk",
117 .id = -1,
118};
119
120static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
121{
122 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
123}
124
125static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
126{
127 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
128}
129
130static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
131{
132 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
133}
134
135int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
136{
137 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
138}
139
140static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
141{
142 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
143}
144
145static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
146{
147 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
148}
149
150static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
151{
152 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
153}
154
155static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
156{
157 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
158}
159
160static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
161{
162 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
163}
164
165static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
166{
167 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
168}
169
170int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
171{
172 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
173}
174
175static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
176{
177 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
178}
179
180int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
181{
182 return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
183}
184
185int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
186{
187 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
188}
189
190static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
191{
192 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
193}
194
195static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
196{
197 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
198}
199
200int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
201{
202 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
203}
204
205static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
206{
207 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
208}
209
210static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
211{
212 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
213}
214
215/* Core list of CMU_CPU side */
216
217static struct clksrc_clk exynos4_clk_mout_apll = {
218 .clk = {
219 .name = "mout_apll",
220 },
221 .sources = &clk_src_apll,
222 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
223};
224
225static struct clksrc_clk exynos4_clk_sclk_apll = {
226 .clk = {
227 .name = "sclk_apll",
228 .parent = &exynos4_clk_mout_apll.clk,
229 },
230 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
231};
232
233static struct clksrc_clk exynos4_clk_mout_epll = {
234 .clk = {
235 .name = "mout_epll",
236 },
237 .sources = &clk_src_epll,
238 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
239};
240
241struct clksrc_clk exynos4_clk_mout_mpll = {
242 .clk = {
243 .name = "mout_mpll",
244 },
245 .sources = &clk_src_mpll,
246
247 /* reg_src will be added in each SoCs' clock */
248};
249
250static struct clk *exynos4_clkset_moutcore_list[] = {
251 [0] = &exynos4_clk_mout_apll.clk,
252 [1] = &exynos4_clk_mout_mpll.clk,
253};
254
255static struct clksrc_sources exynos4_clkset_moutcore = {
256 .sources = exynos4_clkset_moutcore_list,
257 .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list),
258};
259
260static struct clksrc_clk exynos4_clk_moutcore = {
261 .clk = {
262 .name = "moutcore",
263 },
264 .sources = &exynos4_clkset_moutcore,
265 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
266};
267
268static struct clksrc_clk exynos4_clk_coreclk = {
269 .clk = {
270 .name = "core_clk",
271 .parent = &exynos4_clk_moutcore.clk,
272 },
273 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
274};
275
276static struct clksrc_clk exynos4_clk_armclk = {
277 .clk = {
278 .name = "armclk",
279 .parent = &exynos4_clk_coreclk.clk,
280 },
281};
282
283static struct clksrc_clk exynos4_clk_aclk_corem0 = {
284 .clk = {
285 .name = "aclk_corem0",
286 .parent = &exynos4_clk_coreclk.clk,
287 },
288 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
289};
290
291static struct clksrc_clk exynos4_clk_aclk_cores = {
292 .clk = {
293 .name = "aclk_cores",
294 .parent = &exynos4_clk_coreclk.clk,
295 },
296 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
297};
298
299static struct clksrc_clk exynos4_clk_aclk_corem1 = {
300 .clk = {
301 .name = "aclk_corem1",
302 .parent = &exynos4_clk_coreclk.clk,
303 },
304 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
305};
306
307static struct clksrc_clk exynos4_clk_periphclk = {
308 .clk = {
309 .name = "periphclk",
310 .parent = &exynos4_clk_coreclk.clk,
311 },
312 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
313};
314
315/* Core list of CMU_CORE side */
316
317static struct clk *exynos4_clkset_corebus_list[] = {
318 [0] = &exynos4_clk_mout_mpll.clk,
319 [1] = &exynos4_clk_sclk_apll.clk,
320};
321
322struct clksrc_sources exynos4_clkset_mout_corebus = {
323 .sources = exynos4_clkset_corebus_list,
324 .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list),
325};
326
327static struct clksrc_clk exynos4_clk_mout_corebus = {
328 .clk = {
329 .name = "mout_corebus",
330 },
331 .sources = &exynos4_clkset_mout_corebus,
332 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
333};
334
335static struct clksrc_clk exynos4_clk_sclk_dmc = {
336 .clk = {
337 .name = "sclk_dmc",
338 .parent = &exynos4_clk_mout_corebus.clk,
339 },
340 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
341};
342
343static struct clksrc_clk exynos4_clk_aclk_cored = {
344 .clk = {
345 .name = "aclk_cored",
346 .parent = &exynos4_clk_sclk_dmc.clk,
347 },
348 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
349};
350
351static struct clksrc_clk exynos4_clk_aclk_corep = {
352 .clk = {
353 .name = "aclk_corep",
354 .parent = &exynos4_clk_aclk_cored.clk,
355 },
356 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
357};
358
359static struct clksrc_clk exynos4_clk_aclk_acp = {
360 .clk = {
361 .name = "aclk_acp",
362 .parent = &exynos4_clk_mout_corebus.clk,
363 },
364 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
365};
366
367static struct clksrc_clk exynos4_clk_pclk_acp = {
368 .clk = {
369 .name = "pclk_acp",
370 .parent = &exynos4_clk_aclk_acp.clk,
371 },
372 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
373};
374
375/* Core list of CMU_TOP side */
376
377struct clk *exynos4_clkset_aclk_top_list[] = {
378 [0] = &exynos4_clk_mout_mpll.clk,
379 [1] = &exynos4_clk_sclk_apll.clk,
380};
381
382static struct clksrc_sources exynos4_clkset_aclk = {
383 .sources = exynos4_clkset_aclk_top_list,
384 .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
385};
386
387static struct clksrc_clk exynos4_clk_aclk_200 = {
388 .clk = {
389 .name = "aclk_200",
390 },
391 .sources = &exynos4_clkset_aclk,
392 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
393 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
394};
395
396static struct clksrc_clk exynos4_clk_aclk_100 = {
397 .clk = {
398 .name = "aclk_100",
399 },
400 .sources = &exynos4_clkset_aclk,
401 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
402 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
403};
404
405static struct clksrc_clk exynos4_clk_aclk_160 = {
406 .clk = {
407 .name = "aclk_160",
408 },
409 .sources = &exynos4_clkset_aclk,
410 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
411 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
412};
413
414struct clksrc_clk exynos4_clk_aclk_133 = {
415 .clk = {
416 .name = "aclk_133",
417 },
418 .sources = &exynos4_clkset_aclk,
419 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
420 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
421};
422
423static struct clk *exynos4_clkset_vpllsrc_list[] = {
424 [0] = &clk_fin_vpll,
425 [1] = &exynos4_clk_sclk_hdmi27m,
426};
427
428static struct clksrc_sources exynos4_clkset_vpllsrc = {
429 .sources = exynos4_clkset_vpllsrc_list,
430 .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
431};
432
433static struct clksrc_clk exynos4_clk_vpllsrc = {
434 .clk = {
435 .name = "vpll_src",
436 .enable = exynos4_clksrc_mask_top_ctrl,
437 .ctrlbit = (1 << 0),
438 },
439 .sources = &exynos4_clkset_vpllsrc,
440 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
441};
442
443static struct clk *exynos4_clkset_sclk_vpll_list[] = {
444 [0] = &exynos4_clk_vpllsrc.clk,
445 [1] = &clk_fout_vpll,
446};
447
448static struct clksrc_sources exynos4_clkset_sclk_vpll = {
449 .sources = exynos4_clkset_sclk_vpll_list,
450 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
451};
452
453static struct clksrc_clk exynos4_clk_sclk_vpll = {
454 .clk = {
455 .name = "sclk_vpll",
456 },
457 .sources = &exynos4_clkset_sclk_vpll,
458 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
459};
460
461static struct clk exynos4_init_clocks_off[] = {
462 {
463 .name = "timers",
464 .parent = &exynos4_clk_aclk_100.clk,
465 .enable = exynos4_clk_ip_peril_ctrl,
466 .ctrlbit = (1<<24),
467 }, {
468 .name = "csis",
469 .devname = "s5p-mipi-csis.0",
470 .enable = exynos4_clk_ip_cam_ctrl,
471 .ctrlbit = (1 << 4),
472 }, {
473 .name = "csis",
474 .devname = "s5p-mipi-csis.1",
475 .enable = exynos4_clk_ip_cam_ctrl,
476 .ctrlbit = (1 << 5),
477 }, {
478 .name = "jpeg",
479 .id = 0,
480 .enable = exynos4_clk_ip_cam_ctrl,
481 .ctrlbit = (1 << 6),
482 }, {
483 .name = "fimc",
484 .devname = "exynos4-fimc.0",
485 .enable = exynos4_clk_ip_cam_ctrl,
486 .ctrlbit = (1 << 0),
487 }, {
488 .name = "fimc",
489 .devname = "exynos4-fimc.1",
490 .enable = exynos4_clk_ip_cam_ctrl,
491 .ctrlbit = (1 << 1),
492 }, {
493 .name = "fimc",
494 .devname = "exynos4-fimc.2",
495 .enable = exynos4_clk_ip_cam_ctrl,
496 .ctrlbit = (1 << 2),
497 }, {
498 .name = "fimc",
499 .devname = "exynos4-fimc.3",
500 .enable = exynos4_clk_ip_cam_ctrl,
501 .ctrlbit = (1 << 3),
502 }, {
503 .name = "tsi",
504 .enable = exynos4_clk_ip_fsys_ctrl,
505 .ctrlbit = (1 << 4),
506 }, {
507 .name = "hsmmc",
508 .devname = "exynos4-sdhci.0",
509 .parent = &exynos4_clk_aclk_133.clk,
510 .enable = exynos4_clk_ip_fsys_ctrl,
511 .ctrlbit = (1 << 5),
512 }, {
513 .name = "hsmmc",
514 .devname = "exynos4-sdhci.1",
515 .parent = &exynos4_clk_aclk_133.clk,
516 .enable = exynos4_clk_ip_fsys_ctrl,
517 .ctrlbit = (1 << 6),
518 }, {
519 .name = "hsmmc",
520 .devname = "exynos4-sdhci.2",
521 .parent = &exynos4_clk_aclk_133.clk,
522 .enable = exynos4_clk_ip_fsys_ctrl,
523 .ctrlbit = (1 << 7),
524 }, {
525 .name = "hsmmc",
526 .devname = "exynos4-sdhci.3",
527 .parent = &exynos4_clk_aclk_133.clk,
528 .enable = exynos4_clk_ip_fsys_ctrl,
529 .ctrlbit = (1 << 8),
530 }, {
531 .name = "biu",
532 .parent = &exynos4_clk_aclk_133.clk,
533 .enable = exynos4_clk_ip_fsys_ctrl,
534 .ctrlbit = (1 << 9),
535 }, {
536 .name = "onenand",
537 .enable = exynos4_clk_ip_fsys_ctrl,
538 .ctrlbit = (1 << 15),
539 }, {
540 .name = "nfcon",
541 .enable = exynos4_clk_ip_fsys_ctrl,
542 .ctrlbit = (1 << 16),
543 }, {
544 .name = "dac",
545 .devname = "s5p-sdo",
546 .enable = exynos4_clk_ip_tv_ctrl,
547 .ctrlbit = (1 << 2),
548 }, {
549 .name = "mixer",
550 .devname = "s5p-mixer",
551 .enable = exynos4_clk_ip_tv_ctrl,
552 .ctrlbit = (1 << 1),
553 }, {
554 .name = "vp",
555 .devname = "s5p-mixer",
556 .enable = exynos4_clk_ip_tv_ctrl,
557 .ctrlbit = (1 << 0),
558 }, {
559 .name = "hdmi",
560 .devname = "exynos4-hdmi",
561 .enable = exynos4_clk_ip_tv_ctrl,
562 .ctrlbit = (1 << 3),
563 }, {
564 .name = "hdmiphy",
565 .devname = "exynos4-hdmi",
566 .enable = exynos4_clk_hdmiphy_ctrl,
567 .ctrlbit = (1 << 0),
568 }, {
569 .name = "dacphy",
570 .devname = "s5p-sdo",
571 .enable = exynos4_clk_dac_ctrl,
572 .ctrlbit = (1 << 0),
573 }, {
574 .name = "adc",
575 .enable = exynos4_clk_ip_peril_ctrl,
576 .ctrlbit = (1 << 15),
577 }, {
578 .name = "tmu_apbif",
579 .enable = exynos4_clk_ip_perir_ctrl,
580 .ctrlbit = (1 << 17),
581 }, {
582 .name = "keypad",
583 .enable = exynos4_clk_ip_perir_ctrl,
584 .ctrlbit = (1 << 16),
585 }, {
586 .name = "rtc",
587 .enable = exynos4_clk_ip_perir_ctrl,
588 .ctrlbit = (1 << 15),
589 }, {
590 .name = "watchdog",
591 .parent = &exynos4_clk_aclk_100.clk,
592 .enable = exynos4_clk_ip_perir_ctrl,
593 .ctrlbit = (1 << 14),
594 }, {
595 .name = "usbhost",
596 .enable = exynos4_clk_ip_fsys_ctrl ,
597 .ctrlbit = (1 << 12),
598 }, {
599 .name = "otg",
600 .enable = exynos4_clk_ip_fsys_ctrl,
601 .ctrlbit = (1 << 13),
602 }, {
603 .name = "spi",
604 .devname = "exynos4210-spi.0",
605 .enable = exynos4_clk_ip_peril_ctrl,
606 .ctrlbit = (1 << 16),
607 }, {
608 .name = "spi",
609 .devname = "exynos4210-spi.1",
610 .enable = exynos4_clk_ip_peril_ctrl,
611 .ctrlbit = (1 << 17),
612 }, {
613 .name = "spi",
614 .devname = "exynos4210-spi.2",
615 .enable = exynos4_clk_ip_peril_ctrl,
616 .ctrlbit = (1 << 18),
617 }, {
618 .name = "iis",
619 .devname = "samsung-i2s.1",
620 .enable = exynos4_clk_ip_peril_ctrl,
621 .ctrlbit = (1 << 20),
622 }, {
623 .name = "iis",
624 .devname = "samsung-i2s.2",
625 .enable = exynos4_clk_ip_peril_ctrl,
626 .ctrlbit = (1 << 21),
627 }, {
628 .name = "pcm",
629 .devname = "samsung-pcm.1",
630 .enable = exynos4_clk_ip_peril_ctrl,
631 .ctrlbit = (1 << 22),
632 }, {
633 .name = "pcm",
634 .devname = "samsung-pcm.2",
635 .enable = exynos4_clk_ip_peril_ctrl,
636 .ctrlbit = (1 << 23),
637 }, {
638 .name = "slimbus",
639 .enable = exynos4_clk_ip_peril_ctrl,
640 .ctrlbit = (1 << 25),
641 }, {
642 .name = "spdif",
643 .devname = "samsung-spdif",
644 .enable = exynos4_clk_ip_peril_ctrl,
645 .ctrlbit = (1 << 26),
646 }, {
647 .name = "ac97",
648 .devname = "samsung-ac97",
649 .enable = exynos4_clk_ip_peril_ctrl,
650 .ctrlbit = (1 << 27),
651 }, {
652 .name = "mfc",
653 .devname = "s5p-mfc",
654 .enable = exynos4_clk_ip_mfc_ctrl,
655 .ctrlbit = (1 << 0),
656 }, {
657 .name = "i2c",
658 .devname = "s3c2440-i2c.0",
659 .parent = &exynos4_clk_aclk_100.clk,
660 .enable = exynos4_clk_ip_peril_ctrl,
661 .ctrlbit = (1 << 6),
662 }, {
663 .name = "i2c",
664 .devname = "s3c2440-i2c.1",
665 .parent = &exynos4_clk_aclk_100.clk,
666 .enable = exynos4_clk_ip_peril_ctrl,
667 .ctrlbit = (1 << 7),
668 }, {
669 .name = "i2c",
670 .devname = "s3c2440-i2c.2",
671 .parent = &exynos4_clk_aclk_100.clk,
672 .enable = exynos4_clk_ip_peril_ctrl,
673 .ctrlbit = (1 << 8),
674 }, {
675 .name = "i2c",
676 .devname = "s3c2440-i2c.3",
677 .parent = &exynos4_clk_aclk_100.clk,
678 .enable = exynos4_clk_ip_peril_ctrl,
679 .ctrlbit = (1 << 9),
680 }, {
681 .name = "i2c",
682 .devname = "s3c2440-i2c.4",
683 .parent = &exynos4_clk_aclk_100.clk,
684 .enable = exynos4_clk_ip_peril_ctrl,
685 .ctrlbit = (1 << 10),
686 }, {
687 .name = "i2c",
688 .devname = "s3c2440-i2c.5",
689 .parent = &exynos4_clk_aclk_100.clk,
690 .enable = exynos4_clk_ip_peril_ctrl,
691 .ctrlbit = (1 << 11),
692 }, {
693 .name = "i2c",
694 .devname = "s3c2440-i2c.6",
695 .parent = &exynos4_clk_aclk_100.clk,
696 .enable = exynos4_clk_ip_peril_ctrl,
697 .ctrlbit = (1 << 12),
698 }, {
699 .name = "i2c",
700 .devname = "s3c2440-i2c.7",
701 .parent = &exynos4_clk_aclk_100.clk,
702 .enable = exynos4_clk_ip_peril_ctrl,
703 .ctrlbit = (1 << 13),
704 }, {
705 .name = "i2c",
706 .devname = "s3c2440-hdmiphy-i2c",
707 .parent = &exynos4_clk_aclk_100.clk,
708 .enable = exynos4_clk_ip_peril_ctrl,
709 .ctrlbit = (1 << 14),
710 }, {
711 .name = "sysmmu",
712 .devname = "exynos-sysmmu.0",
713 .enable = exynos4_clk_ip_mfc_ctrl,
714 .ctrlbit = (1 << 1),
715 }, {
716 .name = "sysmmu",
717 .devname = "exynos-sysmmu.1",
718 .enable = exynos4_clk_ip_mfc_ctrl,
719 .ctrlbit = (1 << 2),
720 }, {
721 .name = "sysmmu",
722 .devname = "exynos-sysmmu.2",
723 .enable = exynos4_clk_ip_tv_ctrl,
724 .ctrlbit = (1 << 4),
725 }, {
726 .name = "sysmmu",
727 .devname = "exynos-sysmmu.3",
728 .enable = exynos4_clk_ip_cam_ctrl,
729 .ctrlbit = (1 << 11),
730 }, {
731 .name = "sysmmu",
732 .devname = "exynos-sysmmu.4",
733 .enable = exynos4_clk_ip_image_ctrl,
734 .ctrlbit = (1 << 4),
735 }, {
736 .name = "sysmmu",
737 .devname = "exynos-sysmmu.5",
738 .enable = exynos4_clk_ip_cam_ctrl,
739 .ctrlbit = (1 << 7),
740 }, {
741 .name = "sysmmu",
742 .devname = "exynos-sysmmu.6",
743 .enable = exynos4_clk_ip_cam_ctrl,
744 .ctrlbit = (1 << 8),
745 }, {
746 .name = "sysmmu",
747 .devname = "exynos-sysmmu.7",
748 .enable = exynos4_clk_ip_cam_ctrl,
749 .ctrlbit = (1 << 9),
750 }, {
751 .name = "sysmmu",
752 .devname = "exynos-sysmmu.8",
753 .enable = exynos4_clk_ip_cam_ctrl,
754 .ctrlbit = (1 << 10),
755 }, {
756 .name = "sysmmu",
757 .devname = "exynos-sysmmu.10",
758 .enable = exynos4_clk_ip_lcd0_ctrl,
759 .ctrlbit = (1 << 4),
760 }
761};
762
763static struct clk exynos4_init_clocks_on[] = {
764 {
765 .name = "uart",
766 .devname = "s5pv210-uart.0",
767 .enable = exynos4_clk_ip_peril_ctrl,
768 .ctrlbit = (1 << 0),
769 }, {
770 .name = "uart",
771 .devname = "s5pv210-uart.1",
772 .enable = exynos4_clk_ip_peril_ctrl,
773 .ctrlbit = (1 << 1),
774 }, {
775 .name = "uart",
776 .devname = "s5pv210-uart.2",
777 .enable = exynos4_clk_ip_peril_ctrl,
778 .ctrlbit = (1 << 2),
779 }, {
780 .name = "uart",
781 .devname = "s5pv210-uart.3",
782 .enable = exynos4_clk_ip_peril_ctrl,
783 .ctrlbit = (1 << 3),
784 }, {
785 .name = "uart",
786 .devname = "s5pv210-uart.4",
787 .enable = exynos4_clk_ip_peril_ctrl,
788 .ctrlbit = (1 << 4),
789 }, {
790 .name = "uart",
791 .devname = "s5pv210-uart.5",
792 .enable = exynos4_clk_ip_peril_ctrl,
793 .ctrlbit = (1 << 5),
794 }
795};
796
797static struct clk exynos4_clk_pdma0 = {
798 .name = "dma",
799 .devname = "dma-pl330.0",
800 .enable = exynos4_clk_ip_fsys_ctrl,
801 .ctrlbit = (1 << 0),
802};
803
804static struct clk exynos4_clk_pdma1 = {
805 .name = "dma",
806 .devname = "dma-pl330.1",
807 .enable = exynos4_clk_ip_fsys_ctrl,
808 .ctrlbit = (1 << 1),
809};
810
811static struct clk exynos4_clk_mdma1 = {
812 .name = "dma",
813 .devname = "dma-pl330.2",
814 .enable = exynos4_clk_ip_image_ctrl,
815 .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
816};
817
818static struct clk exynos4_clk_fimd0 = {
819 .name = "fimd",
820 .devname = "exynos4-fb.0",
821 .enable = exynos4_clk_ip_lcd0_ctrl,
822 .ctrlbit = (1 << 0),
823};
824
825struct clk *exynos4_clkset_group_list[] = {
826 [0] = &clk_ext_xtal_mux,
827 [1] = &clk_xusbxti,
828 [2] = &exynos4_clk_sclk_hdmi27m,
829 [3] = &exynos4_clk_sclk_usbphy0,
830 [4] = &exynos4_clk_sclk_usbphy1,
831 [5] = &exynos4_clk_sclk_hdmiphy,
832 [6] = &exynos4_clk_mout_mpll.clk,
833 [7] = &exynos4_clk_mout_epll.clk,
834 [8] = &exynos4_clk_sclk_vpll.clk,
835};
836
837struct clksrc_sources exynos4_clkset_group = {
838 .sources = exynos4_clkset_group_list,
839 .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list),
840};
841
842static struct clk *exynos4_clkset_mout_g2d0_list[] = {
843 [0] = &exynos4_clk_mout_mpll.clk,
844 [1] = &exynos4_clk_sclk_apll.clk,
845};
846
847struct clksrc_sources exynos4_clkset_mout_g2d0 = {
848 .sources = exynos4_clkset_mout_g2d0_list,
849 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
850};
851
852static struct clk *exynos4_clkset_mout_g2d1_list[] = {
853 [0] = &exynos4_clk_mout_epll.clk,
854 [1] = &exynos4_clk_sclk_vpll.clk,
855};
856
857struct clksrc_sources exynos4_clkset_mout_g2d1 = {
858 .sources = exynos4_clkset_mout_g2d1_list,
859 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
860};
861
862static struct clk *exynos4_clkset_mout_mfc0_list[] = {
863 [0] = &exynos4_clk_mout_mpll.clk,
864 [1] = &exynos4_clk_sclk_apll.clk,
865};
866
867static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
868 .sources = exynos4_clkset_mout_mfc0_list,
869 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
870};
871
872static struct clksrc_clk exynos4_clk_mout_mfc0 = {
873 .clk = {
874 .name = "mout_mfc0",
875 },
876 .sources = &exynos4_clkset_mout_mfc0,
877 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
878};
879
880static struct clk *exynos4_clkset_mout_mfc1_list[] = {
881 [0] = &exynos4_clk_mout_epll.clk,
882 [1] = &exynos4_clk_sclk_vpll.clk,
883};
884
885static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
886 .sources = exynos4_clkset_mout_mfc1_list,
887 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
888};
889
890static struct clksrc_clk exynos4_clk_mout_mfc1 = {
891 .clk = {
892 .name = "mout_mfc1",
893 },
894 .sources = &exynos4_clkset_mout_mfc1,
895 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
896};
897
898static struct clk *exynos4_clkset_mout_mfc_list[] = {
899 [0] = &exynos4_clk_mout_mfc0.clk,
900 [1] = &exynos4_clk_mout_mfc1.clk,
901};
902
903static struct clksrc_sources exynos4_clkset_mout_mfc = {
904 .sources = exynos4_clkset_mout_mfc_list,
905 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
906};
907
908static struct clk *exynos4_clkset_sclk_dac_list[] = {
909 [0] = &exynos4_clk_sclk_vpll.clk,
910 [1] = &exynos4_clk_sclk_hdmiphy,
911};
912
913static struct clksrc_sources exynos4_clkset_sclk_dac = {
914 .sources = exynos4_clkset_sclk_dac_list,
915 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
916};
917
918static struct clksrc_clk exynos4_clk_sclk_dac = {
919 .clk = {
920 .name = "sclk_dac",
921 .enable = exynos4_clksrc_mask_tv_ctrl,
922 .ctrlbit = (1 << 8),
923 },
924 .sources = &exynos4_clkset_sclk_dac,
925 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
926};
927
928static struct clksrc_clk exynos4_clk_sclk_pixel = {
929 .clk = {
930 .name = "sclk_pixel",
931 .parent = &exynos4_clk_sclk_vpll.clk,
932 },
933 .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
934};
935
936static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
937 [0] = &exynos4_clk_sclk_pixel.clk,
938 [1] = &exynos4_clk_sclk_hdmiphy,
939};
940
941static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
942 .sources = exynos4_clkset_sclk_hdmi_list,
943 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
944};
945
946static struct clksrc_clk exynos4_clk_sclk_hdmi = {
947 .clk = {
948 .name = "sclk_hdmi",
949 .enable = exynos4_clksrc_mask_tv_ctrl,
950 .ctrlbit = (1 << 0),
951 },
952 .sources = &exynos4_clkset_sclk_hdmi,
953 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
954};
955
956static struct clk *exynos4_clkset_sclk_mixer_list[] = {
957 [0] = &exynos4_clk_sclk_dac.clk,
958 [1] = &exynos4_clk_sclk_hdmi.clk,
959};
960
961static struct clksrc_sources exynos4_clkset_sclk_mixer = {
962 .sources = exynos4_clkset_sclk_mixer_list,
963 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
964};
965
966static struct clksrc_clk exynos4_clk_sclk_mixer = {
967 .clk = {
968 .name = "sclk_mixer",
969 .enable = exynos4_clksrc_mask_tv_ctrl,
970 .ctrlbit = (1 << 4),
971 },
972 .sources = &exynos4_clkset_sclk_mixer,
973 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
974};
975
976static struct clksrc_clk *exynos4_sclk_tv[] = {
977 &exynos4_clk_sclk_dac,
978 &exynos4_clk_sclk_pixel,
979 &exynos4_clk_sclk_hdmi,
980 &exynos4_clk_sclk_mixer,
981};
982
983static struct clksrc_clk exynos4_clk_dout_mmc0 = {
984 .clk = {
985 .name = "dout_mmc0",
986 },
987 .sources = &exynos4_clkset_group,
988 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
989 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
990};
991
992static struct clksrc_clk exynos4_clk_dout_mmc1 = {
993 .clk = {
994 .name = "dout_mmc1",
995 },
996 .sources = &exynos4_clkset_group,
997 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
998 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
999};
1000
1001static struct clksrc_clk exynos4_clk_dout_mmc2 = {
1002 .clk = {
1003 .name = "dout_mmc2",
1004 },
1005 .sources = &exynos4_clkset_group,
1006 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
1007 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1008};
1009
1010static struct clksrc_clk exynos4_clk_dout_mmc3 = {
1011 .clk = {
1012 .name = "dout_mmc3",
1013 },
1014 .sources = &exynos4_clkset_group,
1015 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
1016 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1017};
1018
1019static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1020 .clk = {
1021 .name = "dout_mmc4",
1022 },
1023 .sources = &exynos4_clkset_group,
1024 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
1025 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1026};
1027
1028static struct clksrc_clk exynos4_clksrcs[] = {
1029 {
1030 .clk = {
1031 .name = "sclk_pwm",
1032 .enable = exynos4_clksrc_mask_peril0_ctrl,
1033 .ctrlbit = (1 << 24),
1034 },
1035 .sources = &exynos4_clkset_group,
1036 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1037 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1038 }, {
1039 .clk = {
1040 .name = "sclk_csis",
1041 .devname = "s5p-mipi-csis.0",
1042 .enable = exynos4_clksrc_mask_cam_ctrl,
1043 .ctrlbit = (1 << 24),
1044 },
1045 .sources = &exynos4_clkset_group,
1046 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1047 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1048 }, {
1049 .clk = {
1050 .name = "sclk_csis",
1051 .devname = "s5p-mipi-csis.1",
1052 .enable = exynos4_clksrc_mask_cam_ctrl,
1053 .ctrlbit = (1 << 28),
1054 },
1055 .sources = &exynos4_clkset_group,
1056 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1057 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1058 }, {
1059 .clk = {
1060 .name = "sclk_cam0",
1061 .enable = exynos4_clksrc_mask_cam_ctrl,
1062 .ctrlbit = (1 << 16),
1063 },
1064 .sources = &exynos4_clkset_group,
1065 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1066 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1067 }, {
1068 .clk = {
1069 .name = "sclk_cam1",
1070 .enable = exynos4_clksrc_mask_cam_ctrl,
1071 .ctrlbit = (1 << 20),
1072 },
1073 .sources = &exynos4_clkset_group,
1074 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1075 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1076 }, {
1077 .clk = {
1078 .name = "sclk_fimc",
1079 .devname = "exynos4-fimc.0",
1080 .enable = exynos4_clksrc_mask_cam_ctrl,
1081 .ctrlbit = (1 << 0),
1082 },
1083 .sources = &exynos4_clkset_group,
1084 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1085 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1086 }, {
1087 .clk = {
1088 .name = "sclk_fimc",
1089 .devname = "exynos4-fimc.1",
1090 .enable = exynos4_clksrc_mask_cam_ctrl,
1091 .ctrlbit = (1 << 4),
1092 },
1093 .sources = &exynos4_clkset_group,
1094 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1095 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1096 }, {
1097 .clk = {
1098 .name = "sclk_fimc",
1099 .devname = "exynos4-fimc.2",
1100 .enable = exynos4_clksrc_mask_cam_ctrl,
1101 .ctrlbit = (1 << 8),
1102 },
1103 .sources = &exynos4_clkset_group,
1104 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1105 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1106 }, {
1107 .clk = {
1108 .name = "sclk_fimc",
1109 .devname = "exynos4-fimc.3",
1110 .enable = exynos4_clksrc_mask_cam_ctrl,
1111 .ctrlbit = (1 << 12),
1112 },
1113 .sources = &exynos4_clkset_group,
1114 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1115 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1116 }, {
1117 .clk = {
1118 .name = "sclk_fimd",
1119 .devname = "exynos4-fb.0",
1120 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1121 .ctrlbit = (1 << 0),
1122 },
1123 .sources = &exynos4_clkset_group,
1124 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1125 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1126 }, {
1127 .clk = {
1128 .name = "sclk_mfc",
1129 .devname = "s5p-mfc",
1130 },
1131 .sources = &exynos4_clkset_mout_mfc,
1132 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1133 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1134 }, {
1135 .clk = {
1136 .name = "ciu",
1137 .parent = &exynos4_clk_dout_mmc4.clk,
1138 .enable = exynos4_clksrc_mask_fsys_ctrl,
1139 .ctrlbit = (1 << 16),
1140 },
1141 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1142 }
1143};
1144
1145static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1146 .clk = {
1147 .name = "uclk1",
1148 .devname = "exynos4210-uart.0",
1149 .enable = exynos4_clksrc_mask_peril0_ctrl,
1150 .ctrlbit = (1 << 0),
1151 },
1152 .sources = &exynos4_clkset_group,
1153 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1154 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1155};
1156
1157static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1158 .clk = {
1159 .name = "uclk1",
1160 .devname = "exynos4210-uart.1",
1161 .enable = exynos4_clksrc_mask_peril0_ctrl,
1162 .ctrlbit = (1 << 4),
1163 },
1164 .sources = &exynos4_clkset_group,
1165 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1166 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1167};
1168
1169static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1170 .clk = {
1171 .name = "uclk1",
1172 .devname = "exynos4210-uart.2",
1173 .enable = exynos4_clksrc_mask_peril0_ctrl,
1174 .ctrlbit = (1 << 8),
1175 },
1176 .sources = &exynos4_clkset_group,
1177 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1178 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1179};
1180
1181static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1182 .clk = {
1183 .name = "uclk1",
1184 .devname = "exynos4210-uart.3",
1185 .enable = exynos4_clksrc_mask_peril0_ctrl,
1186 .ctrlbit = (1 << 12),
1187 },
1188 .sources = &exynos4_clkset_group,
1189 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1190 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1191};
1192
1193static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1194 .clk = {
1195 .name = "sclk_mmc",
1196 .devname = "exynos4-sdhci.0",
1197 .parent = &exynos4_clk_dout_mmc0.clk,
1198 .enable = exynos4_clksrc_mask_fsys_ctrl,
1199 .ctrlbit = (1 << 0),
1200 },
1201 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1202};
1203
1204static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1205 .clk = {
1206 .name = "sclk_mmc",
1207 .devname = "exynos4-sdhci.1",
1208 .parent = &exynos4_clk_dout_mmc1.clk,
1209 .enable = exynos4_clksrc_mask_fsys_ctrl,
1210 .ctrlbit = (1 << 4),
1211 },
1212 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1213};
1214
1215static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1216 .clk = {
1217 .name = "sclk_mmc",
1218 .devname = "exynos4-sdhci.2",
1219 .parent = &exynos4_clk_dout_mmc2.clk,
1220 .enable = exynos4_clksrc_mask_fsys_ctrl,
1221 .ctrlbit = (1 << 8),
1222 },
1223 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1224};
1225
1226static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1227 .clk = {
1228 .name = "sclk_mmc",
1229 .devname = "exynos4-sdhci.3",
1230 .parent = &exynos4_clk_dout_mmc3.clk,
1231 .enable = exynos4_clksrc_mask_fsys_ctrl,
1232 .ctrlbit = (1 << 12),
1233 },
1234 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1235};
1236
1237static struct clksrc_clk exynos4_clk_mdout_spi0 = {
1238 .clk = {
1239 .name = "mdout_spi",
1240 .devname = "exynos4210-spi.0",
1241 },
1242 .sources = &exynos4_clkset_group,
1243 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1244 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1245};
1246
1247static struct clksrc_clk exynos4_clk_mdout_spi1 = {
1248 .clk = {
1249 .name = "mdout_spi",
1250 .devname = "exynos4210-spi.1",
1251 },
1252 .sources = &exynos4_clkset_group,
1253 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1254 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1255};
1256
1257static struct clksrc_clk exynos4_clk_mdout_spi2 = {
1258 .clk = {
1259 .name = "mdout_spi",
1260 .devname = "exynos4210-spi.2",
1261 },
1262 .sources = &exynos4_clkset_group,
1263 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1264 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1265};
1266
1267static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1268 .clk = {
1269 .name = "sclk_spi",
1270 .devname = "exynos4210-spi.0",
1271 .parent = &exynos4_clk_mdout_spi0.clk,
1272 .enable = exynos4_clksrc_mask_peril1_ctrl,
1273 .ctrlbit = (1 << 16),
1274 },
1275 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
1276};
1277
1278static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1279 .clk = {
1280 .name = "sclk_spi",
1281 .devname = "exynos4210-spi.1",
1282 .parent = &exynos4_clk_mdout_spi1.clk,
1283 .enable = exynos4_clksrc_mask_peril1_ctrl,
1284 .ctrlbit = (1 << 20),
1285 },
1286 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
1287};
1288
1289static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1290 .clk = {
1291 .name = "sclk_spi",
1292 .devname = "exynos4210-spi.2",
1293 .parent = &exynos4_clk_mdout_spi2.clk,
1294 .enable = exynos4_clksrc_mask_peril1_ctrl,
1295 .ctrlbit = (1 << 24),
1296 },
1297 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
1298};
1299
1300/* Clock initialization code */
1301static struct clksrc_clk *exynos4_sysclks[] = {
1302 &exynos4_clk_mout_apll,
1303 &exynos4_clk_sclk_apll,
1304 &exynos4_clk_mout_epll,
1305 &exynos4_clk_mout_mpll,
1306 &exynos4_clk_moutcore,
1307 &exynos4_clk_coreclk,
1308 &exynos4_clk_armclk,
1309 &exynos4_clk_aclk_corem0,
1310 &exynos4_clk_aclk_cores,
1311 &exynos4_clk_aclk_corem1,
1312 &exynos4_clk_periphclk,
1313 &exynos4_clk_mout_corebus,
1314 &exynos4_clk_sclk_dmc,
1315 &exynos4_clk_aclk_cored,
1316 &exynos4_clk_aclk_corep,
1317 &exynos4_clk_aclk_acp,
1318 &exynos4_clk_pclk_acp,
1319 &exynos4_clk_vpllsrc,
1320 &exynos4_clk_sclk_vpll,
1321 &exynos4_clk_aclk_200,
1322 &exynos4_clk_aclk_100,
1323 &exynos4_clk_aclk_160,
1324 &exynos4_clk_aclk_133,
1325 &exynos4_clk_dout_mmc0,
1326 &exynos4_clk_dout_mmc1,
1327 &exynos4_clk_dout_mmc2,
1328 &exynos4_clk_dout_mmc3,
1329 &exynos4_clk_dout_mmc4,
1330 &exynos4_clk_mout_mfc0,
1331 &exynos4_clk_mout_mfc1,
1332};
1333
1334static struct clk *exynos4_clk_cdev[] = {
1335 &exynos4_clk_pdma0,
1336 &exynos4_clk_pdma1,
1337 &exynos4_clk_mdma1,
1338 &exynos4_clk_fimd0,
1339};
1340
1341static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1342 &exynos4_clk_sclk_uart0,
1343 &exynos4_clk_sclk_uart1,
1344 &exynos4_clk_sclk_uart2,
1345 &exynos4_clk_sclk_uart3,
1346 &exynos4_clk_sclk_mmc0,
1347 &exynos4_clk_sclk_mmc1,
1348 &exynos4_clk_sclk_mmc2,
1349 &exynos4_clk_sclk_mmc3,
1350 &exynos4_clk_sclk_spi0,
1351 &exynos4_clk_sclk_spi1,
1352 &exynos4_clk_sclk_spi2,
1353 &exynos4_clk_mdout_spi0,
1354 &exynos4_clk_mdout_spi1,
1355 &exynos4_clk_mdout_spi2,
1356};
1357
1358static struct clk_lookup exynos4_clk_lookup[] = {
1359 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1360 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1361 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1362 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1363 CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1364 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1365 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1366 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1367 CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1368 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1369 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1370 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1371 CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1372 CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1373 CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1374};
1375
1376static int xtal_rate;
1377
1378static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1379{
1380 if (soc_is_exynos4210())
1381 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1382 pll_4508);
1383 else if (soc_is_exynos4212() || soc_is_exynos4412())
1384 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1385 else
1386 return 0;
1387}
1388
1389static struct clk_ops exynos4_fout_apll_ops = {
1390 .get_rate = exynos4_fout_apll_get_rate,
1391};
1392
1393static u32 exynos4_vpll_div[][8] = {
1394 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1395 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1396};
1397
1398static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1399{
1400 return clk->rate;
1401}
1402
1403static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1404{
1405 unsigned int vpll_con0, vpll_con1 = 0;
1406 unsigned int i;
1407
1408 /* Return if nothing changed */
1409 if (clk->rate == rate)
1410 return 0;
1411
1412 vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1413 vpll_con0 &= ~(0x1 << 27 | \
1414 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1415 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1416 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1417
1418 vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1419 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1420 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1421 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1422
1423 for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1424 if (exynos4_vpll_div[i][0] == rate) {
1425 vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1426 vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1427 vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1428 vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1429 vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1430 vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1431 vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1432 break;
1433 }
1434 }
1435
1436 if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1437 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1438 __func__);
1439 return -EINVAL;
1440 }
1441
1442 __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1443 __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1444
1445 /* Wait for VPLL lock */
1446 while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1447 continue;
1448
1449 clk->rate = rate;
1450 return 0;
1451}
1452
1453static struct clk_ops exynos4_vpll_ops = {
1454 .get_rate = exynos4_vpll_get_rate,
1455 .set_rate = exynos4_vpll_set_rate,
1456};
1457
1458void __init_or_cpufreq exynos4_setup_clocks(void)
1459{
1460 struct clk *xtal_clk;
1461 unsigned long apll = 0;
1462 unsigned long mpll = 0;
1463 unsigned long epll = 0;
1464 unsigned long vpll = 0;
1465 unsigned long vpllsrc;
1466 unsigned long xtal;
1467 unsigned long armclk;
1468 unsigned long sclk_dmc;
1469 unsigned long aclk_200;
1470 unsigned long aclk_100;
1471 unsigned long aclk_160;
1472 unsigned long aclk_133;
1473 unsigned int ptr;
1474
1475 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1476
1477 xtal_clk = clk_get(NULL, "xtal");
1478 BUG_ON(IS_ERR(xtal_clk));
1479
1480 xtal = clk_get_rate(xtal_clk);
1481
1482 xtal_rate = xtal;
1483
1484 clk_put(xtal_clk);
1485
1486 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1487
1488 if (soc_is_exynos4210()) {
1489 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1490 pll_4508);
1491 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1492 pll_4508);
1493 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1494 __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1495
1496 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1497 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1498 __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1499 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1500 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1501 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1502 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1503 __raw_readl(EXYNOS4_EPLL_CON1));
1504
1505 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1506 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1507 __raw_readl(EXYNOS4_VPLL_CON1));
1508 } else {
1509 /* nothing */
1510 }
1511
1512 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1513 clk_fout_mpll.rate = mpll;
1514 clk_fout_epll.rate = epll;
1515 clk_fout_vpll.ops = &exynos4_vpll_ops;
1516 clk_fout_vpll.rate = vpll;
1517
1518 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1519 apll, mpll, epll, vpll);
1520
1521 armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1522 sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1523
1524 aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1525 aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1526 aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1527 aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1528
1529 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1530 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1531 armclk, sclk_dmc, aclk_200,
1532 aclk_100, aclk_160, aclk_133);
1533
1534 clk_f.rate = armclk;
1535 clk_h.rate = sclk_dmc;
1536 clk_p.rate = aclk_100;
1537
1538 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1539 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1540}
1541
1542static struct clk *exynos4_clks[] __initdata = {
1543 &exynos4_clk_sclk_hdmi27m,
1544 &exynos4_clk_sclk_hdmiphy,
1545 &exynos4_clk_sclk_usbphy0,
1546 &exynos4_clk_sclk_usbphy1,
1547};
1548
1549#ifdef CONFIG_PM_SLEEP
1550static int exynos4_clock_suspend(void)
1551{
1552 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1553 return 0;
1554}
1555
1556static void exynos4_clock_resume(void)
1557{
1558 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1559}
1560
1561#else
1562#define exynos4_clock_suspend NULL
1563#define exynos4_clock_resume NULL
1564#endif
1565
1566static struct syscore_ops exynos4_clock_syscore_ops = {
1567 .suspend = exynos4_clock_suspend,
1568 .resume = exynos4_clock_resume,
1569};
1570
1571void __init exynos4_register_clocks(void)
1572{
1573 int ptr;
1574
1575 s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1576
1577 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1578 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1579
1580 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1581 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1582
1583 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1584 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1585
1586 s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1587 s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1588
1589 s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1590 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1591 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1592
1593 s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1594 s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1595 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1596
1597 register_syscore_ops(&exynos4_clock_syscore_ops);
1598 s3c24xx_register_clock(&dummy_apb_pclk);
1599
1600 s3c_pwmclk_init();
1601}
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
deleted file mode 100644
index bd12d5f8b63d..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Header file for exynos4 clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_CLOCK_H
13#define __ASM_ARCH_CLOCK_H __FILE__
14
15#include <linux/clk.h>
16
17extern struct clksrc_clk exynos4_clk_aclk_133;
18extern struct clksrc_clk exynos4_clk_mout_mpll;
19
20extern struct clksrc_sources exynos4_clkset_mout_corebus;
21extern struct clksrc_sources exynos4_clkset_group;
22
23extern struct clk *exynos4_clkset_aclk_top_list[];
24extern struct clk *exynos4_clkset_group_list[];
25
26extern struct clksrc_sources exynos4_clkset_mout_g2d0;
27extern struct clksrc_sources exynos4_clkset_mout_g2d1;
28
29extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
30extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
31extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
32extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
33extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
34
35#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
deleted file mode 100644
index 19af9f783c56..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ /dev/null
@@ -1,187 +0,0 @@
1/*
2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS4210 - Clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/syscore_ops.h>
17
18#include <plat/cpu-freq.h>
19#include <plat/clock.h>
20#include <plat/cpu.h>
21#include <plat/pll.h>
22#include <plat/s5p-clock.h>
23#include <plat/clock-clksrc.h>
24#include <plat/pm.h>
25
26#include <mach/hardware.h>
27#include <mach/map.h>
28#include <mach/regs-clock.h>
29
30#include "common.h"
31#include "clock-exynos4.h"
32
33#ifdef CONFIG_PM_SLEEP
34static struct sleep_save exynos4210_clock_save[] = {
35 SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
36 SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
37 SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
38 SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
39 SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
40 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
41 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
42 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
43};
44#endif
45
46static struct clksrc_clk *sysclks[] = {
47 /* nothing here yet */
48};
49
50static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
51 .clk = {
52 .name = "mout_g2d0",
53 },
54 .sources = &exynos4_clkset_mout_g2d0,
55 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
56};
57
58static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
59 .clk = {
60 .name = "mout_g2d1",
61 },
62 .sources = &exynos4_clkset_mout_g2d1,
63 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
64};
65
66static struct clk *exynos4210_clkset_mout_g2d_list[] = {
67 [0] = &exynos4210_clk_mout_g2d0.clk,
68 [1] = &exynos4210_clk_mout_g2d1.clk,
69};
70
71static struct clksrc_sources exynos4210_clkset_mout_g2d = {
72 .sources = exynos4210_clkset_mout_g2d_list,
73 .nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
74};
75
76static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
77{
78 return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
79}
80
81static struct clksrc_clk clksrcs[] = {
82 {
83 .clk = {
84 .name = "sclk_sata",
85 .id = -1,
86 .enable = exynos4_clksrc_mask_fsys_ctrl,
87 .ctrlbit = (1 << 24),
88 },
89 .sources = &exynos4_clkset_mout_corebus,
90 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
91 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
92 }, {
93 .clk = {
94 .name = "sclk_fimd",
95 .devname = "exynos4-fb.1",
96 .enable = exynos4_clksrc_mask_lcd1_ctrl,
97 .ctrlbit = (1 << 0),
98 },
99 .sources = &exynos4_clkset_group,
100 .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
101 .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
102 }, {
103 .clk = {
104 .name = "sclk_fimg2d",
105 },
106 .sources = &exynos4210_clkset_mout_g2d,
107 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
108 .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
109 },
110};
111
112static struct clk init_clocks_off[] = {
113 {
114 .name = "sataphy",
115 .id = -1,
116 .parent = &exynos4_clk_aclk_133.clk,
117 .enable = exynos4_clk_ip_fsys_ctrl,
118 .ctrlbit = (1 << 3),
119 }, {
120 .name = "sata",
121 .id = -1,
122 .parent = &exynos4_clk_aclk_133.clk,
123 .enable = exynos4_clk_ip_fsys_ctrl,
124 .ctrlbit = (1 << 10),
125 }, {
126 .name = "fimd",
127 .devname = "exynos4-fb.1",
128 .enable = exynos4_clk_ip_lcd1_ctrl,
129 .ctrlbit = (1 << 0),
130 }, {
131 .name = "sysmmu",
132 .devname = "exynos-sysmmu.9",
133 .enable = exynos4_clk_ip_image_ctrl,
134 .ctrlbit = (1 << 3),
135 }, {
136 .name = "sysmmu",
137 .devname = "exynos-sysmmu.11",
138 .enable = exynos4_clk_ip_lcd1_ctrl,
139 .ctrlbit = (1 << 4),
140 }, {
141 .name = "fimg2d",
142 .enable = exynos4_clk_ip_image_ctrl,
143 .ctrlbit = (1 << 0),
144 },
145};
146
147#ifdef CONFIG_PM_SLEEP
148static int exynos4210_clock_suspend(void)
149{
150 s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
151
152 return 0;
153}
154
155static void exynos4210_clock_resume(void)
156{
157 s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
158}
159
160#else
161#define exynos4210_clock_suspend NULL
162#define exynos4210_clock_resume NULL
163#endif
164
165static struct syscore_ops exynos4210_clock_syscore_ops = {
166 .suspend = exynos4210_clock_suspend,
167 .resume = exynos4210_clock_resume,
168};
169
170void __init exynos4210_register_clocks(void)
171{
172 int ptr;
173
174 exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
175 exynos4_clk_mout_mpll.reg_src.shift = 8;
176 exynos4_clk_mout_mpll.reg_src.size = 1;
177
178 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
179 s3c_register_clksrc(sysclks[ptr], 1);
180
181 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
182
183 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
184 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
185
186 register_syscore_ops(&exynos4210_clock_syscore_ops);
187}
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
deleted file mode 100644
index 529476f8ec71..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ /dev/null
@@ -1,201 +0,0 @@
1/*
2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS4212 - Clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/syscore_ops.h>
17
18#include <plat/cpu-freq.h>
19#include <plat/clock.h>
20#include <plat/cpu.h>
21#include <plat/pll.h>
22#include <plat/s5p-clock.h>
23#include <plat/clock-clksrc.h>
24#include <plat/pm.h>
25
26#include <mach/hardware.h>
27#include <mach/map.h>
28#include <mach/regs-clock.h>
29
30#include "common.h"
31#include "clock-exynos4.h"
32
33#ifdef CONFIG_PM_SLEEP
34static struct sleep_save exynos4212_clock_save[] = {
35 SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
36 SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
37 SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
38 SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
39};
40#endif
41
42static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
43{
44 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
45}
46
47static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
48{
49 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
50}
51
52static struct clk *clk_src_mpll_user_list[] = {
53 [0] = &clk_fin_mpll,
54 [1] = &exynos4_clk_mout_mpll.clk,
55};
56
57static struct clksrc_sources clk_src_mpll_user = {
58 .sources = clk_src_mpll_user_list,
59 .nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
60};
61
62static struct clksrc_clk clk_mout_mpll_user = {
63 .clk = {
64 .name = "mout_mpll_user",
65 },
66 .sources = &clk_src_mpll_user,
67 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
68};
69
70static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
71 .clk = {
72 .name = "mout_g2d0",
73 },
74 .sources = &exynos4_clkset_mout_g2d0,
75 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
76};
77
78static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
79 .clk = {
80 .name = "mout_g2d1",
81 },
82 .sources = &exynos4_clkset_mout_g2d1,
83 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
84};
85
86static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
87 [0] = &exynos4x12_clk_mout_g2d0.clk,
88 [1] = &exynos4x12_clk_mout_g2d1.clk,
89};
90
91static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
92 .sources = exynos4x12_clkset_mout_g2d_list,
93 .nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
94};
95
96static struct clksrc_clk *sysclks[] = {
97 &clk_mout_mpll_user,
98};
99
100static struct clksrc_clk clksrcs[] = {
101 {
102 .clk = {
103 .name = "sclk_fimg2d",
104 },
105 .sources = &exynos4x12_clkset_mout_g2d,
106 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
107 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
108 },
109};
110
111static struct clk init_clocks_off[] = {
112 {
113 .name = "sysmmu",
114 .devname = "exynos-sysmmu.9",
115 .enable = exynos4_clk_ip_dmc_ctrl,
116 .ctrlbit = (1 << 24),
117 }, {
118 .name = "sysmmu",
119 .devname = "exynos-sysmmu.12",
120 .enable = exynos4212_clk_ip_isp0_ctrl,
121 .ctrlbit = (7 << 8),
122 }, {
123 .name = "sysmmu",
124 .devname = "exynos-sysmmu.13",
125 .enable = exynos4212_clk_ip_isp1_ctrl,
126 .ctrlbit = (1 << 4),
127 }, {
128 .name = "sysmmu",
129 .devname = "exynos-sysmmu.14",
130 .enable = exynos4212_clk_ip_isp0_ctrl,
131 .ctrlbit = (1 << 11),
132 }, {
133 .name = "sysmmu",
134 .devname = "exynos-sysmmu.15",
135 .enable = exynos4212_clk_ip_isp0_ctrl,
136 .ctrlbit = (1 << 12),
137 }, {
138 .name = "flite",
139 .devname = "exynos-fimc-lite.0",
140 .enable = exynos4212_clk_ip_isp0_ctrl,
141 .ctrlbit = (1 << 4),
142 }, {
143 .name = "flite",
144 .devname = "exynos-fimc-lite.1",
145 .enable = exynos4212_clk_ip_isp0_ctrl,
146 .ctrlbit = (1 << 3),
147 }, {
148 .name = "fimg2d",
149 .enable = exynos4_clk_ip_dmc_ctrl,
150 .ctrlbit = (1 << 23),
151 },
152};
153
154#ifdef CONFIG_PM_SLEEP
155static int exynos4212_clock_suspend(void)
156{
157 s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
158
159 return 0;
160}
161
162static void exynos4212_clock_resume(void)
163{
164 s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
165}
166
167#else
168#define exynos4212_clock_suspend NULL
169#define exynos4212_clock_resume NULL
170#endif
171
172static struct syscore_ops exynos4212_clock_syscore_ops = {
173 .suspend = exynos4212_clock_suspend,
174 .resume = exynos4212_clock_resume,
175};
176
177void __init exynos4212_register_clocks(void)
178{
179 int ptr;
180
181 /* usbphy1 is removed */
182 exynos4_clkset_group_list[4] = NULL;
183
184 /* mout_mpll_user is used */
185 exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
186 exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
187
188 exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
189 exynos4_clk_mout_mpll.reg_src.shift = 12;
190 exynos4_clk_mout_mpll.reg_src.size = 1;
191
192 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
193 s3c_register_clksrc(sysclks[ptr], 1);
194
195 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
196
197 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
198 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
199
200 register_syscore_ops(&exynos4212_clock_syscore_ops);
201}
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
deleted file mode 100644
index b0ea31fc9fb8..000000000000
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ /dev/null
@@ -1,1645 +0,0 @@
1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Clock support for EXYNOS5 SoCs
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/syscore_ops.h>
16
17#include <plat/cpu-freq.h>
18#include <plat/clock.h>
19#include <plat/cpu.h>
20#include <plat/pll.h>
21#include <plat/s5p-clock.h>
22#include <plat/clock-clksrc.h>
23#include <plat/pm.h>
24
25#include <mach/map.h>
26#include <mach/regs-clock.h>
27
28#include "common.h"
29
30#ifdef CONFIG_PM_SLEEP
31static struct sleep_save exynos5_clock_save[] = {
32 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
33 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
34 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
35 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
36 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
37 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
38 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
39 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
40 SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
41 SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
42 SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
43 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
44 SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
45 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
46 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
47 SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
48 SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
49 SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
50 SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
51 SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
52 SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
53 SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
54 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
55 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
56 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
57 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
58 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
59 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
60 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
61 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
62 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
63 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
64 SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
65 SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
66 SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
67 SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
68 SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
69 SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
70 SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
71 SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
72 SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
73 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
74 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
75 SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
76 SAVE_ITEM(EXYNOS5_EPLL_CON0),
77 SAVE_ITEM(EXYNOS5_EPLL_CON1),
78 SAVE_ITEM(EXYNOS5_EPLL_CON2),
79 SAVE_ITEM(EXYNOS5_VPLL_CON0),
80 SAVE_ITEM(EXYNOS5_VPLL_CON1),
81 SAVE_ITEM(EXYNOS5_VPLL_CON2),
82 SAVE_ITEM(EXYNOS5_PWR_CTRL1),
83 SAVE_ITEM(EXYNOS5_PWR_CTRL2),
84};
85#endif
86
87static struct clk exynos5_clk_sclk_dptxphy = {
88 .name = "sclk_dptx",
89};
90
91static struct clk exynos5_clk_sclk_hdmi24m = {
92 .name = "sclk_hdmi24m",
93 .rate = 24000000,
94};
95
96static struct clk exynos5_clk_sclk_hdmi27m = {
97 .name = "sclk_hdmi27m",
98 .rate = 27000000,
99};
100
101static struct clk exynos5_clk_sclk_hdmiphy = {
102 .name = "sclk_hdmiphy",
103};
104
105static struct clk exynos5_clk_sclk_usbphy = {
106 .name = "sclk_usbphy",
107 .rate = 48000000,
108};
109
110static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
111{
112 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
113}
114
115static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
116{
117 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
118}
119
120static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
121{
122 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
123}
124
125static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
126{
127 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
128}
129
130static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
131{
132 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
133}
134
135static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
136{
137 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
138}
139
140static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
141{
142 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
143}
144
145static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
146{
147 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
148}
149
150static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
151{
152 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
153}
154
155static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
156{
157 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
158}
159
160static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
161{
162 return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
163}
164
165static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
166{
167 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
168}
169
170static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
171{
172 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
173}
174
175static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
176{
177 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
178}
179
180static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
181{
182 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
183}
184
185static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
186{
187 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
188}
189
190static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
191{
192 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
193}
194
195static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
196{
197 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
198}
199
200static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
201{
202 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
203}
204
205/* Core list of CMU_CPU side */
206
207static struct clksrc_clk exynos5_clk_mout_apll = {
208 .clk = {
209 .name = "mout_apll",
210 },
211 .sources = &clk_src_apll,
212 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
213};
214
215static struct clksrc_clk exynos5_clk_sclk_apll = {
216 .clk = {
217 .name = "sclk_apll",
218 .parent = &exynos5_clk_mout_apll.clk,
219 },
220 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
221};
222
223static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
224 .clk = {
225 .name = "mout_bpll_fout",
226 },
227 .sources = &clk_src_bpll_fout,
228 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
229};
230
231static struct clk *exynos5_clk_src_bpll_list[] = {
232 [0] = &clk_fin_bpll,
233 [1] = &exynos5_clk_mout_bpll_fout.clk,
234};
235
236static struct clksrc_sources exynos5_clk_src_bpll = {
237 .sources = exynos5_clk_src_bpll_list,
238 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list),
239};
240
241static struct clksrc_clk exynos5_clk_mout_bpll = {
242 .clk = {
243 .name = "mout_bpll",
244 },
245 .sources = &exynos5_clk_src_bpll,
246 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
247};
248
249static struct clk *exynos5_clk_src_bpll_user_list[] = {
250 [0] = &clk_fin_mpll,
251 [1] = &exynos5_clk_mout_bpll.clk,
252};
253
254static struct clksrc_sources exynos5_clk_src_bpll_user = {
255 .sources = exynos5_clk_src_bpll_user_list,
256 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
257};
258
259static struct clksrc_clk exynos5_clk_mout_bpll_user = {
260 .clk = {
261 .name = "mout_bpll_user",
262 },
263 .sources = &exynos5_clk_src_bpll_user,
264 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
265};
266
267static struct clksrc_clk exynos5_clk_mout_cpll = {
268 .clk = {
269 .name = "mout_cpll",
270 },
271 .sources = &clk_src_cpll,
272 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
273};
274
275static struct clksrc_clk exynos5_clk_mout_epll = {
276 .clk = {
277 .name = "mout_epll",
278 },
279 .sources = &clk_src_epll,
280 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
281};
282
283static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
284 .clk = {
285 .name = "mout_mpll_fout",
286 },
287 .sources = &clk_src_mpll_fout,
288 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
289};
290
291static struct clk *exynos5_clk_src_mpll_list[] = {
292 [0] = &clk_fin_mpll,
293 [1] = &exynos5_clk_mout_mpll_fout.clk,
294};
295
296static struct clksrc_sources exynos5_clk_src_mpll = {
297 .sources = exynos5_clk_src_mpll_list,
298 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
299};
300
301static struct clksrc_clk exynos5_clk_mout_mpll = {
302 .clk = {
303 .name = "mout_mpll",
304 },
305 .sources = &exynos5_clk_src_mpll,
306 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
307};
308
309static struct clk *exynos_clkset_vpllsrc_list[] = {
310 [0] = &clk_fin_vpll,
311 [1] = &exynos5_clk_sclk_hdmi27m,
312};
313
314static struct clksrc_sources exynos5_clkset_vpllsrc = {
315 .sources = exynos_clkset_vpllsrc_list,
316 .nr_sources = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
317};
318
319static struct clksrc_clk exynos5_clk_vpllsrc = {
320 .clk = {
321 .name = "vpll_src",
322 .enable = exynos5_clksrc_mask_top_ctrl,
323 .ctrlbit = (1 << 0),
324 },
325 .sources = &exynos5_clkset_vpllsrc,
326 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
327};
328
329static struct clk *exynos5_clkset_sclk_vpll_list[] = {
330 [0] = &exynos5_clk_vpllsrc.clk,
331 [1] = &clk_fout_vpll,
332};
333
334static struct clksrc_sources exynos5_clkset_sclk_vpll = {
335 .sources = exynos5_clkset_sclk_vpll_list,
336 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
337};
338
339static struct clksrc_clk exynos5_clk_sclk_vpll = {
340 .clk = {
341 .name = "sclk_vpll",
342 },
343 .sources = &exynos5_clkset_sclk_vpll,
344 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
345};
346
347static struct clksrc_clk exynos5_clk_sclk_pixel = {
348 .clk = {
349 .name = "sclk_pixel",
350 .parent = &exynos5_clk_sclk_vpll.clk,
351 },
352 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
353};
354
355static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
356 [0] = &exynos5_clk_sclk_pixel.clk,
357 [1] = &exynos5_clk_sclk_hdmiphy,
358};
359
360static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
361 .sources = exynos5_clkset_sclk_hdmi_list,
362 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
363};
364
365static struct clksrc_clk exynos5_clk_sclk_hdmi = {
366 .clk = {
367 .name = "sclk_hdmi",
368 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
369 .ctrlbit = (1 << 20),
370 },
371 .sources = &exynos5_clkset_sclk_hdmi,
372 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
373};
374
375static struct clksrc_clk *exynos5_sclk_tv[] = {
376 &exynos5_clk_sclk_pixel,
377 &exynos5_clk_sclk_hdmi,
378};
379
380static struct clk *exynos5_clk_src_mpll_user_list[] = {
381 [0] = &clk_fin_mpll,
382 [1] = &exynos5_clk_mout_mpll.clk,
383};
384
385static struct clksrc_sources exynos5_clk_src_mpll_user = {
386 .sources = exynos5_clk_src_mpll_user_list,
387 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
388};
389
390static struct clksrc_clk exynos5_clk_mout_mpll_user = {
391 .clk = {
392 .name = "mout_mpll_user",
393 },
394 .sources = &exynos5_clk_src_mpll_user,
395 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
396};
397
398static struct clk *exynos5_clkset_mout_cpu_list[] = {
399 [0] = &exynos5_clk_mout_apll.clk,
400 [1] = &exynos5_clk_mout_mpll.clk,
401};
402
403static struct clksrc_sources exynos5_clkset_mout_cpu = {
404 .sources = exynos5_clkset_mout_cpu_list,
405 .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
406};
407
408static struct clksrc_clk exynos5_clk_mout_cpu = {
409 .clk = {
410 .name = "mout_cpu",
411 },
412 .sources = &exynos5_clkset_mout_cpu,
413 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
414};
415
416static struct clksrc_clk exynos5_clk_dout_armclk = {
417 .clk = {
418 .name = "dout_armclk",
419 .parent = &exynos5_clk_mout_cpu.clk,
420 },
421 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
422};
423
424static struct clksrc_clk exynos5_clk_dout_arm2clk = {
425 .clk = {
426 .name = "dout_arm2clk",
427 .parent = &exynos5_clk_dout_armclk.clk,
428 },
429 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
430};
431
432static struct clk exynos5_clk_armclk = {
433 .name = "armclk",
434 .parent = &exynos5_clk_dout_arm2clk.clk,
435};
436
437/* Core list of CMU_CDREX side */
438
439static struct clk *exynos5_clkset_cdrex_list[] = {
440 [0] = &exynos5_clk_mout_mpll.clk,
441 [1] = &exynos5_clk_mout_bpll.clk,
442};
443
444static struct clksrc_sources exynos5_clkset_cdrex = {
445 .sources = exynos5_clkset_cdrex_list,
446 .nr_sources = ARRAY_SIZE(exynos5_clkset_cdrex_list),
447};
448
449static struct clksrc_clk exynos5_clk_cdrex = {
450 .clk = {
451 .name = "clk_cdrex",
452 },
453 .sources = &exynos5_clkset_cdrex,
454 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
455 .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
456};
457
458static struct clksrc_clk exynos5_clk_aclk_acp = {
459 .clk = {
460 .name = "aclk_acp",
461 .parent = &exynos5_clk_mout_mpll.clk,
462 },
463 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
464};
465
466static struct clksrc_clk exynos5_clk_pclk_acp = {
467 .clk = {
468 .name = "pclk_acp",
469 .parent = &exynos5_clk_aclk_acp.clk,
470 },
471 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
472};
473
474/* Core list of CMU_TOP side */
475
476static struct clk *exynos5_clkset_aclk_top_list[] = {
477 [0] = &exynos5_clk_mout_mpll_user.clk,
478 [1] = &exynos5_clk_mout_bpll_user.clk,
479};
480
481static struct clksrc_sources exynos5_clkset_aclk = {
482 .sources = exynos5_clkset_aclk_top_list,
483 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
484};
485
486static struct clksrc_clk exynos5_clk_aclk_400 = {
487 .clk = {
488 .name = "aclk_400",
489 },
490 .sources = &exynos5_clkset_aclk,
491 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
492 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
493};
494
495static struct clk *exynos5_clkset_aclk_333_166_list[] = {
496 [0] = &exynos5_clk_mout_cpll.clk,
497 [1] = &exynos5_clk_mout_mpll_user.clk,
498};
499
500static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
501 .sources = exynos5_clkset_aclk_333_166_list,
502 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
503};
504
505static struct clksrc_clk exynos5_clk_aclk_333 = {
506 .clk = {
507 .name = "aclk_333",
508 },
509 .sources = &exynos5_clkset_aclk_333_166,
510 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
511 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
512};
513
514static struct clksrc_clk exynos5_clk_aclk_166 = {
515 .clk = {
516 .name = "aclk_166",
517 },
518 .sources = &exynos5_clkset_aclk_333_166,
519 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
520 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
521};
522
523static struct clksrc_clk exynos5_clk_aclk_266 = {
524 .clk = {
525 .name = "aclk_266",
526 .parent = &exynos5_clk_mout_mpll_user.clk,
527 },
528 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
529};
530
531static struct clksrc_clk exynos5_clk_aclk_200 = {
532 .clk = {
533 .name = "aclk_200",
534 },
535 .sources = &exynos5_clkset_aclk,
536 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
537 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
538};
539
540static struct clksrc_clk exynos5_clk_aclk_66_pre = {
541 .clk = {
542 .name = "aclk_66_pre",
543 .parent = &exynos5_clk_mout_mpll_user.clk,
544 },
545 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
546};
547
548static struct clksrc_clk exynos5_clk_aclk_66 = {
549 .clk = {
550 .name = "aclk_66",
551 .parent = &exynos5_clk_aclk_66_pre.clk,
552 },
553 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
554};
555
556static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
557 .clk = {
558 .name = "mout_aclk_300_gscl_mid",
559 },
560 .sources = &exynos5_clkset_aclk,
561 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
562};
563
564static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
565 [0] = &exynos5_clk_sclk_vpll.clk,
566 [1] = &exynos5_clk_mout_cpll.clk,
567};
568
569static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
570 .sources = exynos5_clkset_aclk_300_mid1_list,
571 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
572};
573
574static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
575 .clk = {
576 .name = "mout_aclk_300_gscl_mid1",
577 },
578 .sources = &exynos5_clkset_aclk_300_gscl_mid1,
579 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
580};
581
582static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
583 [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
584 [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
585};
586
587static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
588 .sources = exynos5_clkset_aclk_300_gscl_list,
589 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
590};
591
592static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
593 .clk = {
594 .name = "mout_aclk_300_gscl",
595 },
596 .sources = &exynos5_clkset_aclk_300_gscl,
597 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
598};
599
600static struct clk *exynos5_clk_src_gscl_300_list[] = {
601 [0] = &clk_ext_xtal_mux,
602 [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
603};
604
605static struct clksrc_sources exynos5_clk_src_gscl_300 = {
606 .sources = exynos5_clk_src_gscl_300_list,
607 .nr_sources = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
608};
609
610static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
611 .clk = {
612 .name = "aclk_300_gscl",
613 },
614 .sources = &exynos5_clk_src_gscl_300,
615 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
616};
617
618static struct clk exynos5_init_clocks_off[] = {
619 {
620 .name = "timers",
621 .parent = &exynos5_clk_aclk_66.clk,
622 .enable = exynos5_clk_ip_peric_ctrl,
623 .ctrlbit = (1 << 24),
624 }, {
625 .name = "tmu_apbif",
626 .parent = &exynos5_clk_aclk_66.clk,
627 .enable = exynos5_clk_ip_peris_ctrl,
628 .ctrlbit = (1 << 21),
629 }, {
630 .name = "rtc",
631 .parent = &exynos5_clk_aclk_66.clk,
632 .enable = exynos5_clk_ip_peris_ctrl,
633 .ctrlbit = (1 << 20),
634 }, {
635 .name = "watchdog",
636 .parent = &exynos5_clk_aclk_66.clk,
637 .enable = exynos5_clk_ip_peris_ctrl,
638 .ctrlbit = (1 << 19),
639 }, {
640 .name = "biu", /* bus interface unit clock */
641 .devname = "dw_mmc.0",
642 .parent = &exynos5_clk_aclk_200.clk,
643 .enable = exynos5_clk_ip_fsys_ctrl,
644 .ctrlbit = (1 << 12),
645 }, {
646 .name = "biu",
647 .devname = "dw_mmc.1",
648 .parent = &exynos5_clk_aclk_200.clk,
649 .enable = exynos5_clk_ip_fsys_ctrl,
650 .ctrlbit = (1 << 13),
651 }, {
652 .name = "biu",
653 .devname = "dw_mmc.2",
654 .parent = &exynos5_clk_aclk_200.clk,
655 .enable = exynos5_clk_ip_fsys_ctrl,
656 .ctrlbit = (1 << 14),
657 }, {
658 .name = "biu",
659 .devname = "dw_mmc.3",
660 .parent = &exynos5_clk_aclk_200.clk,
661 .enable = exynos5_clk_ip_fsys_ctrl,
662 .ctrlbit = (1 << 15),
663 }, {
664 .name = "sata",
665 .devname = "exynos5-sata",
666 .parent = &exynos5_clk_aclk_200.clk,
667 .enable = exynos5_clk_ip_fsys_ctrl,
668 .ctrlbit = (1 << 6),
669 }, {
670 .name = "sata-phy",
671 .devname = "exynos5-sata-phy",
672 .parent = &exynos5_clk_aclk_200.clk,
673 .enable = exynos5_clk_ip_fsys_ctrl,
674 .ctrlbit = (1 << 24),
675 }, {
676 .name = "i2c",
677 .devname = "exynos5-sata-phy-i2c",
678 .parent = &exynos5_clk_aclk_200.clk,
679 .enable = exynos5_clk_ip_fsys_ctrl,
680 .ctrlbit = (1 << 25),
681 }, {
682 .name = "mfc",
683 .devname = "s5p-mfc-v6",
684 .enable = exynos5_clk_ip_mfc_ctrl,
685 .ctrlbit = (1 << 0),
686 }, {
687 .name = "hdmi",
688 .devname = "exynos5-hdmi",
689 .enable = exynos5_clk_ip_disp1_ctrl,
690 .ctrlbit = (1 << 6),
691 }, {
692 .name = "hdmiphy",
693 .devname = "exynos5-hdmi",
694 .enable = exynos5_clk_hdmiphy_ctrl,
695 .ctrlbit = (1 << 0),
696 }, {
697 .name = "mixer",
698 .devname = "exynos5-mixer",
699 .enable = exynos5_clk_ip_disp1_ctrl,
700 .ctrlbit = (1 << 5),
701 }, {
702 .name = "dp",
703 .devname = "exynos-dp",
704 .enable = exynos5_clk_ip_disp1_ctrl,
705 .ctrlbit = (1 << 4),
706 }, {
707 .name = "jpeg",
708 .enable = exynos5_clk_ip_gen_ctrl,
709 .ctrlbit = (1 << 2),
710 }, {
711 .name = "dsim0",
712 .enable = exynos5_clk_ip_disp1_ctrl,
713 .ctrlbit = (1 << 3),
714 }, {
715 .name = "iis",
716 .devname = "samsung-i2s.1",
717 .enable = exynos5_clk_ip_peric_ctrl,
718 .ctrlbit = (1 << 20),
719 }, {
720 .name = "iis",
721 .devname = "samsung-i2s.2",
722 .enable = exynos5_clk_ip_peric_ctrl,
723 .ctrlbit = (1 << 21),
724 }, {
725 .name = "pcm",
726 .devname = "samsung-pcm.1",
727 .enable = exynos5_clk_ip_peric_ctrl,
728 .ctrlbit = (1 << 22),
729 }, {
730 .name = "pcm",
731 .devname = "samsung-pcm.2",
732 .enable = exynos5_clk_ip_peric_ctrl,
733 .ctrlbit = (1 << 23),
734 }, {
735 .name = "spdif",
736 .devname = "samsung-spdif",
737 .enable = exynos5_clk_ip_peric_ctrl,
738 .ctrlbit = (1 << 26),
739 }, {
740 .name = "ac97",
741 .devname = "samsung-ac97",
742 .enable = exynos5_clk_ip_peric_ctrl,
743 .ctrlbit = (1 << 27),
744 }, {
745 .name = "usbhost",
746 .enable = exynos5_clk_ip_fsys_ctrl ,
747 .ctrlbit = (1 << 18),
748 }, {
749 .name = "usbotg",
750 .enable = exynos5_clk_ip_fsys_ctrl,
751 .ctrlbit = (1 << 7),
752 }, {
753 .name = "nfcon",
754 .enable = exynos5_clk_ip_fsys_ctrl,
755 .ctrlbit = (1 << 22),
756 }, {
757 .name = "iop",
758 .enable = exynos5_clk_ip_fsys_ctrl,
759 .ctrlbit = ((1 << 30) | (1 << 26) | (1 << 23)),
760 }, {
761 .name = "core_iop",
762 .enable = exynos5_clk_ip_core_ctrl,
763 .ctrlbit = ((1 << 21) | (1 << 3)),
764 }, {
765 .name = "mcu_iop",
766 .enable = exynos5_clk_ip_fsys_ctrl,
767 .ctrlbit = (1 << 0),
768 }, {
769 .name = "i2c",
770 .devname = "s3c2440-i2c.0",
771 .parent = &exynos5_clk_aclk_66.clk,
772 .enable = exynos5_clk_ip_peric_ctrl,
773 .ctrlbit = (1 << 6),
774 }, {
775 .name = "i2c",
776 .devname = "s3c2440-i2c.1",
777 .parent = &exynos5_clk_aclk_66.clk,
778 .enable = exynos5_clk_ip_peric_ctrl,
779 .ctrlbit = (1 << 7),
780 }, {
781 .name = "i2c",
782 .devname = "s3c2440-i2c.2",
783 .parent = &exynos5_clk_aclk_66.clk,
784 .enable = exynos5_clk_ip_peric_ctrl,
785 .ctrlbit = (1 << 8),
786 }, {
787 .name = "i2c",
788 .devname = "s3c2440-i2c.3",
789 .parent = &exynos5_clk_aclk_66.clk,
790 .enable = exynos5_clk_ip_peric_ctrl,
791 .ctrlbit = (1 << 9),
792 }, {
793 .name = "i2c",
794 .devname = "s3c2440-i2c.4",
795 .parent = &exynos5_clk_aclk_66.clk,
796 .enable = exynos5_clk_ip_peric_ctrl,
797 .ctrlbit = (1 << 10),
798 }, {
799 .name = "i2c",
800 .devname = "s3c2440-i2c.5",
801 .parent = &exynos5_clk_aclk_66.clk,
802 .enable = exynos5_clk_ip_peric_ctrl,
803 .ctrlbit = (1 << 11),
804 }, {
805 .name = "i2c",
806 .devname = "s3c2440-i2c.6",
807 .parent = &exynos5_clk_aclk_66.clk,
808 .enable = exynos5_clk_ip_peric_ctrl,
809 .ctrlbit = (1 << 12),
810 }, {
811 .name = "i2c",
812 .devname = "s3c2440-i2c.7",
813 .parent = &exynos5_clk_aclk_66.clk,
814 .enable = exynos5_clk_ip_peric_ctrl,
815 .ctrlbit = (1 << 13),
816 }, {
817 .name = "i2c",
818 .devname = "s3c2440-hdmiphy-i2c",
819 .parent = &exynos5_clk_aclk_66.clk,
820 .enable = exynos5_clk_ip_peric_ctrl,
821 .ctrlbit = (1 << 14),
822 }, {
823 .name = "spi",
824 .devname = "exynos4210-spi.0",
825 .parent = &exynos5_clk_aclk_66.clk,
826 .enable = exynos5_clk_ip_peric_ctrl,
827 .ctrlbit = (1 << 16),
828 }, {
829 .name = "spi",
830 .devname = "exynos4210-spi.1",
831 .parent = &exynos5_clk_aclk_66.clk,
832 .enable = exynos5_clk_ip_peric_ctrl,
833 .ctrlbit = (1 << 17),
834 }, {
835 .name = "spi",
836 .devname = "exynos4210-spi.2",
837 .parent = &exynos5_clk_aclk_66.clk,
838 .enable = exynos5_clk_ip_peric_ctrl,
839 .ctrlbit = (1 << 18),
840 }, {
841 .name = "gscl",
842 .devname = "exynos-gsc.0",
843 .enable = exynos5_clk_ip_gscl_ctrl,
844 .ctrlbit = (1 << 0),
845 }, {
846 .name = "gscl",
847 .devname = "exynos-gsc.1",
848 .enable = exynos5_clk_ip_gscl_ctrl,
849 .ctrlbit = (1 << 1),
850 }, {
851 .name = "gscl",
852 .devname = "exynos-gsc.2",
853 .enable = exynos5_clk_ip_gscl_ctrl,
854 .ctrlbit = (1 << 2),
855 }, {
856 .name = "gscl",
857 .devname = "exynos-gsc.3",
858 .enable = exynos5_clk_ip_gscl_ctrl,
859 .ctrlbit = (1 << 3),
860 }, {
861 .name = "sysmmu",
862 .devname = "exynos-sysmmu.1",
863 .enable = &exynos5_clk_ip_mfc_ctrl,
864 .ctrlbit = (1 << 1),
865 }, {
866 .name = "sysmmu",
867 .devname = "exynos-sysmmu.0",
868 .enable = &exynos5_clk_ip_mfc_ctrl,
869 .ctrlbit = (1 << 2),
870 }, {
871 .name = "sysmmu",
872 .devname = "exynos-sysmmu.2",
873 .enable = &exynos5_clk_ip_disp1_ctrl,
874 .ctrlbit = (1 << 9)
875 }, {
876 .name = "sysmmu",
877 .devname = "exynos-sysmmu.3",
878 .enable = &exynos5_clk_ip_gen_ctrl,
879 .ctrlbit = (1 << 7),
880 }, {
881 .name = "sysmmu",
882 .devname = "exynos-sysmmu.4",
883 .enable = &exynos5_clk_ip_gen_ctrl,
884 .ctrlbit = (1 << 6)
885 }, {
886 .name = "sysmmu",
887 .devname = "exynos-sysmmu.5",
888 .enable = &exynos5_clk_ip_gscl_ctrl,
889 .ctrlbit = (1 << 7),
890 }, {
891 .name = "sysmmu",
892 .devname = "exynos-sysmmu.6",
893 .enable = &exynos5_clk_ip_gscl_ctrl,
894 .ctrlbit = (1 << 8),
895 }, {
896 .name = "sysmmu",
897 .devname = "exynos-sysmmu.7",
898 .enable = &exynos5_clk_ip_gscl_ctrl,
899 .ctrlbit = (1 << 9),
900 }, {
901 .name = "sysmmu",
902 .devname = "exynos-sysmmu.8",
903 .enable = &exynos5_clk_ip_gscl_ctrl,
904 .ctrlbit = (1 << 10),
905 }, {
906 .name = "sysmmu",
907 .devname = "exynos-sysmmu.9",
908 .enable = &exynos5_clk_ip_isp0_ctrl,
909 .ctrlbit = (0x3F << 8),
910 }, {
911 .name = "sysmmu",
912 .devname = "exynos-sysmmu.10",
913 .enable = &exynos5_clk_ip_isp1_ctrl,
914 .ctrlbit = (0xF << 4),
915 }, {
916 .name = "sysmmu",
917 .devname = "exynos-sysmmu.11",
918 .enable = &exynos5_clk_ip_disp1_ctrl,
919 .ctrlbit = (1 << 8)
920 }, {
921 .name = "sysmmu",
922 .devname = "exynos-sysmmu.12",
923 .enable = &exynos5_clk_ip_gscl_ctrl,
924 .ctrlbit = (1 << 11),
925 }, {
926 .name = "sysmmu",
927 .devname = "exynos-sysmmu.13",
928 .enable = &exynos5_clk_ip_gscl_ctrl,
929 .ctrlbit = (1 << 12),
930 }, {
931 .name = "sysmmu",
932 .devname = "exynos-sysmmu.14",
933 .enable = &exynos5_clk_ip_acp_ctrl,
934 .ctrlbit = (1 << 7)
935 }
936};
937
938static struct clk exynos5_init_clocks_on[] = {
939 {
940 .name = "uart",
941 .devname = "s5pv210-uart.0",
942 .enable = exynos5_clk_ip_peric_ctrl,
943 .ctrlbit = (1 << 0),
944 }, {
945 .name = "uart",
946 .devname = "s5pv210-uart.1",
947 .enable = exynos5_clk_ip_peric_ctrl,
948 .ctrlbit = (1 << 1),
949 }, {
950 .name = "uart",
951 .devname = "s5pv210-uart.2",
952 .enable = exynos5_clk_ip_peric_ctrl,
953 .ctrlbit = (1 << 2),
954 }, {
955 .name = "uart",
956 .devname = "s5pv210-uart.3",
957 .enable = exynos5_clk_ip_peric_ctrl,
958 .ctrlbit = (1 << 3),
959 }, {
960 .name = "uart",
961 .devname = "s5pv210-uart.4",
962 .enable = exynos5_clk_ip_peric_ctrl,
963 .ctrlbit = (1 << 4),
964 }, {
965 .name = "uart",
966 .devname = "s5pv210-uart.5",
967 .enable = exynos5_clk_ip_peric_ctrl,
968 .ctrlbit = (1 << 5),
969 }
970};
971
972static struct clk exynos5_clk_pdma0 = {
973 .name = "dma",
974 .devname = "dma-pl330.0",
975 .enable = exynos5_clk_ip_fsys_ctrl,
976 .ctrlbit = (1 << 1),
977};
978
979static struct clk exynos5_clk_pdma1 = {
980 .name = "dma",
981 .devname = "dma-pl330.1",
982 .enable = exynos5_clk_ip_fsys_ctrl,
983 .ctrlbit = (1 << 2),
984};
985
986static struct clk exynos5_clk_mdma1 = {
987 .name = "dma",
988 .devname = "dma-pl330.2",
989 .enable = exynos5_clk_ip_gen_ctrl,
990 .ctrlbit = (1 << 4),
991};
992
993static struct clk exynos5_clk_fimd1 = {
994 .name = "fimd",
995 .devname = "exynos5-fb.1",
996 .enable = exynos5_clk_ip_disp1_ctrl,
997 .ctrlbit = (1 << 0),
998};
999
1000static struct clk *exynos5_clkset_group_list[] = {
1001 [0] = &clk_ext_xtal_mux,
1002 [1] = NULL,
1003 [2] = &exynos5_clk_sclk_hdmi24m,
1004 [3] = &exynos5_clk_sclk_dptxphy,
1005 [4] = &exynos5_clk_sclk_usbphy,
1006 [5] = &exynos5_clk_sclk_hdmiphy,
1007 [6] = &exynos5_clk_mout_mpll_user.clk,
1008 [7] = &exynos5_clk_mout_epll.clk,
1009 [8] = &exynos5_clk_sclk_vpll.clk,
1010 [9] = &exynos5_clk_mout_cpll.clk,
1011};
1012
1013static struct clksrc_sources exynos5_clkset_group = {
1014 .sources = exynos5_clkset_group_list,
1015 .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
1016};
1017
1018/* Possible clock sources for aclk_266_gscl_sub Mux */
1019static struct clk *clk_src_gscl_266_list[] = {
1020 [0] = &clk_ext_xtal_mux,
1021 [1] = &exynos5_clk_aclk_266.clk,
1022};
1023
1024static struct clksrc_sources clk_src_gscl_266 = {
1025 .sources = clk_src_gscl_266_list,
1026 .nr_sources = ARRAY_SIZE(clk_src_gscl_266_list),
1027};
1028
1029static struct clksrc_clk exynos5_clk_dout_mmc0 = {
1030 .clk = {
1031 .name = "dout_mmc0",
1032 },
1033 .sources = &exynos5_clkset_group,
1034 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
1035 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
1036};
1037
1038static struct clksrc_clk exynos5_clk_dout_mmc1 = {
1039 .clk = {
1040 .name = "dout_mmc1",
1041 },
1042 .sources = &exynos5_clkset_group,
1043 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
1044 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1045};
1046
1047static struct clksrc_clk exynos5_clk_dout_mmc2 = {
1048 .clk = {
1049 .name = "dout_mmc2",
1050 },
1051 .sources = &exynos5_clkset_group,
1052 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
1053 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1054};
1055
1056static struct clksrc_clk exynos5_clk_dout_mmc3 = {
1057 .clk = {
1058 .name = "dout_mmc3",
1059 },
1060 .sources = &exynos5_clkset_group,
1061 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
1062 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1063};
1064
1065static struct clksrc_clk exynos5_clk_dout_mmc4 = {
1066 .clk = {
1067 .name = "dout_mmc4",
1068 },
1069 .sources = &exynos5_clkset_group,
1070 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
1071 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1072};
1073
1074static struct clksrc_clk exynos5_clk_sclk_uart0 = {
1075 .clk = {
1076 .name = "uclk1",
1077 .devname = "exynos4210-uart.0",
1078 .enable = exynos5_clksrc_mask_peric0_ctrl,
1079 .ctrlbit = (1 << 0),
1080 },
1081 .sources = &exynos5_clkset_group,
1082 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
1083 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
1084};
1085
1086static struct clksrc_clk exynos5_clk_sclk_uart1 = {
1087 .clk = {
1088 .name = "uclk1",
1089 .devname = "exynos4210-uart.1",
1090 .enable = exynos5_clksrc_mask_peric0_ctrl,
1091 .ctrlbit = (1 << 4),
1092 },
1093 .sources = &exynos5_clkset_group,
1094 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
1095 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
1096};
1097
1098static struct clksrc_clk exynos5_clk_sclk_uart2 = {
1099 .clk = {
1100 .name = "uclk1",
1101 .devname = "exynos4210-uart.2",
1102 .enable = exynos5_clksrc_mask_peric0_ctrl,
1103 .ctrlbit = (1 << 8),
1104 },
1105 .sources = &exynos5_clkset_group,
1106 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
1107 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
1108};
1109
1110static struct clksrc_clk exynos5_clk_sclk_uart3 = {
1111 .clk = {
1112 .name = "uclk1",
1113 .devname = "exynos4210-uart.3",
1114 .enable = exynos5_clksrc_mask_peric0_ctrl,
1115 .ctrlbit = (1 << 12),
1116 },
1117 .sources = &exynos5_clkset_group,
1118 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
1119 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
1120};
1121
1122static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
1123 .clk = {
1124 .name = "ciu", /* card interface unit clock */
1125 .devname = "dw_mmc.0",
1126 .parent = &exynos5_clk_dout_mmc0.clk,
1127 .enable = exynos5_clksrc_mask_fsys_ctrl,
1128 .ctrlbit = (1 << 0),
1129 },
1130 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1131};
1132
1133static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
1134 .clk = {
1135 .name = "ciu",
1136 .devname = "dw_mmc.1",
1137 .parent = &exynos5_clk_dout_mmc1.clk,
1138 .enable = exynos5_clksrc_mask_fsys_ctrl,
1139 .ctrlbit = (1 << 4),
1140 },
1141 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1142};
1143
1144static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
1145 .clk = {
1146 .name = "ciu",
1147 .devname = "dw_mmc.2",
1148 .parent = &exynos5_clk_dout_mmc2.clk,
1149 .enable = exynos5_clksrc_mask_fsys_ctrl,
1150 .ctrlbit = (1 << 8),
1151 },
1152 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1153};
1154
1155static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
1156 .clk = {
1157 .name = "ciu",
1158 .devname = "dw_mmc.3",
1159 .parent = &exynos5_clk_dout_mmc3.clk,
1160 .enable = exynos5_clksrc_mask_fsys_ctrl,
1161 .ctrlbit = (1 << 12),
1162 },
1163 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1164};
1165
1166static struct clksrc_clk exynos5_clk_mdout_spi0 = {
1167 .clk = {
1168 .name = "mdout_spi",
1169 .devname = "exynos4210-spi.0",
1170 },
1171 .sources = &exynos5_clkset_group,
1172 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
1173 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
1174};
1175
1176static struct clksrc_clk exynos5_clk_mdout_spi1 = {
1177 .clk = {
1178 .name = "mdout_spi",
1179 .devname = "exynos4210-spi.1",
1180 },
1181 .sources = &exynos5_clkset_group,
1182 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
1183 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
1184};
1185
1186static struct clksrc_clk exynos5_clk_mdout_spi2 = {
1187 .clk = {
1188 .name = "mdout_spi",
1189 .devname = "exynos4210-spi.2",
1190 },
1191 .sources = &exynos5_clkset_group,
1192 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
1193 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
1194};
1195
1196static struct clksrc_clk exynos5_clk_sclk_spi0 = {
1197 .clk = {
1198 .name = "sclk_spi",
1199 .devname = "exynos4210-spi.0",
1200 .parent = &exynos5_clk_mdout_spi0.clk,
1201 .enable = exynos5_clksrc_mask_peric1_ctrl,
1202 .ctrlbit = (1 << 16),
1203 },
1204 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
1205};
1206
1207static struct clksrc_clk exynos5_clk_sclk_spi1 = {
1208 .clk = {
1209 .name = "sclk_spi",
1210 .devname = "exynos4210-spi.1",
1211 .parent = &exynos5_clk_mdout_spi1.clk,
1212 .enable = exynos5_clksrc_mask_peric1_ctrl,
1213 .ctrlbit = (1 << 20),
1214 },
1215 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
1216};
1217
1218static struct clksrc_clk exynos5_clk_sclk_spi2 = {
1219 .clk = {
1220 .name = "sclk_spi",
1221 .devname = "exynos4210-spi.2",
1222 .parent = &exynos5_clk_mdout_spi2.clk,
1223 .enable = exynos5_clksrc_mask_peric1_ctrl,
1224 .ctrlbit = (1 << 24),
1225 },
1226 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
1227};
1228
1229static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
1230 .clk = {
1231 .name = "sclk_fimd",
1232 .devname = "exynos5-fb.1",
1233 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
1234 .ctrlbit = (1 << 0),
1235 },
1236 .sources = &exynos5_clkset_group,
1237 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
1238 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
1239};
1240
1241static struct clksrc_clk exynos5_clksrcs[] = {
1242 {
1243 .clk = {
1244 .name = "aclk_266_gscl",
1245 },
1246 .sources = &clk_src_gscl_266,
1247 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
1248 }, {
1249 .clk = {
1250 .name = "sclk_g3d",
1251 .devname = "mali-t604.0",
1252 .enable = exynos5_clk_block_ctrl,
1253 .ctrlbit = (1 << 1),
1254 },
1255 .sources = &exynos5_clkset_aclk,
1256 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
1257 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
1258 }, {
1259 .clk = {
1260 .name = "sclk_sata",
1261 .devname = "exynos5-sata",
1262 .enable = exynos5_clksrc_mask_fsys_ctrl,
1263 .ctrlbit = (1 << 24),
1264 },
1265 .sources = &exynos5_clkset_aclk,
1266 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
1267 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
1268 }, {
1269 .clk = {
1270 .name = "sclk_gscl_wrap",
1271 .devname = "s5p-mipi-csis.0",
1272 .enable = exynos5_clksrc_mask_gscl_ctrl,
1273 .ctrlbit = (1 << 24),
1274 },
1275 .sources = &exynos5_clkset_group,
1276 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
1277 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
1278 }, {
1279 .clk = {
1280 .name = "sclk_gscl_wrap",
1281 .devname = "s5p-mipi-csis.1",
1282 .enable = exynos5_clksrc_mask_gscl_ctrl,
1283 .ctrlbit = (1 << 28),
1284 },
1285 .sources = &exynos5_clkset_group,
1286 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
1287 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
1288 }, {
1289 .clk = {
1290 .name = "sclk_cam0",
1291 .enable = exynos5_clksrc_mask_gscl_ctrl,
1292 .ctrlbit = (1 << 16),
1293 },
1294 .sources = &exynos5_clkset_group,
1295 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
1296 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
1297 }, {
1298 .clk = {
1299 .name = "sclk_cam1",
1300 .enable = exynos5_clksrc_mask_gscl_ctrl,
1301 .ctrlbit = (1 << 20),
1302 },
1303 .sources = &exynos5_clkset_group,
1304 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
1305 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
1306 }, {
1307 .clk = {
1308 .name = "sclk_jpeg",
1309 .parent = &exynos5_clk_mout_cpll.clk,
1310 },
1311 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
1312 },
1313};
1314
1315/* Clock initialization code */
1316static struct clksrc_clk *exynos5_sysclks[] = {
1317 &exynos5_clk_mout_apll,
1318 &exynos5_clk_sclk_apll,
1319 &exynos5_clk_mout_bpll,
1320 &exynos5_clk_mout_bpll_fout,
1321 &exynos5_clk_mout_bpll_user,
1322 &exynos5_clk_mout_cpll,
1323 &exynos5_clk_mout_epll,
1324 &exynos5_clk_mout_mpll,
1325 &exynos5_clk_mout_mpll_fout,
1326 &exynos5_clk_mout_mpll_user,
1327 &exynos5_clk_vpllsrc,
1328 &exynos5_clk_sclk_vpll,
1329 &exynos5_clk_mout_cpu,
1330 &exynos5_clk_dout_armclk,
1331 &exynos5_clk_dout_arm2clk,
1332 &exynos5_clk_cdrex,
1333 &exynos5_clk_aclk_400,
1334 &exynos5_clk_aclk_333,
1335 &exynos5_clk_aclk_266,
1336 &exynos5_clk_aclk_200,
1337 &exynos5_clk_aclk_166,
1338 &exynos5_clk_aclk_300_gscl,
1339 &exynos5_clk_mout_aclk_300_gscl,
1340 &exynos5_clk_mout_aclk_300_gscl_mid,
1341 &exynos5_clk_mout_aclk_300_gscl_mid1,
1342 &exynos5_clk_aclk_66_pre,
1343 &exynos5_clk_aclk_66,
1344 &exynos5_clk_dout_mmc0,
1345 &exynos5_clk_dout_mmc1,
1346 &exynos5_clk_dout_mmc2,
1347 &exynos5_clk_dout_mmc3,
1348 &exynos5_clk_dout_mmc4,
1349 &exynos5_clk_aclk_acp,
1350 &exynos5_clk_pclk_acp,
1351 &exynos5_clk_sclk_spi0,
1352 &exynos5_clk_sclk_spi1,
1353 &exynos5_clk_sclk_spi2,
1354 &exynos5_clk_mdout_spi0,
1355 &exynos5_clk_mdout_spi1,
1356 &exynos5_clk_mdout_spi2,
1357 &exynos5_clk_sclk_fimd1,
1358};
1359
1360static struct clk *exynos5_clk_cdev[] = {
1361 &exynos5_clk_pdma0,
1362 &exynos5_clk_pdma1,
1363 &exynos5_clk_mdma1,
1364 &exynos5_clk_fimd1,
1365};
1366
1367static struct clksrc_clk *exynos5_clksrc_cdev[] = {
1368 &exynos5_clk_sclk_uart0,
1369 &exynos5_clk_sclk_uart1,
1370 &exynos5_clk_sclk_uart2,
1371 &exynos5_clk_sclk_uart3,
1372 &exynos5_clk_sclk_mmc0,
1373 &exynos5_clk_sclk_mmc1,
1374 &exynos5_clk_sclk_mmc2,
1375 &exynos5_clk_sclk_mmc3,
1376};
1377
1378static struct clk_lookup exynos5_clk_lookup[] = {
1379 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
1380 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
1381 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
1382 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
1383 CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
1384 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
1385 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
1386 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
1387 CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
1388 CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
1389 CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
1390 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
1391 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
1392 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1393 CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
1394};
1395
1396static unsigned long exynos5_epll_get_rate(struct clk *clk)
1397{
1398 return clk->rate;
1399}
1400
1401static struct clk *exynos5_clks[] __initdata = {
1402 &exynos5_clk_sclk_hdmi27m,
1403 &exynos5_clk_sclk_hdmiphy,
1404 &clk_fout_bpll,
1405 &clk_fout_bpll_div2,
1406 &clk_fout_cpll,
1407 &clk_fout_mpll_div2,
1408 &exynos5_clk_armclk,
1409};
1410
1411static u32 epll_div[][6] = {
1412 { 192000000, 0, 48, 3, 1, 0 },
1413 { 180000000, 0, 45, 3, 1, 0 },
1414 { 73728000, 1, 73, 3, 3, 47710 },
1415 { 67737600, 1, 90, 4, 3, 20762 },
1416 { 49152000, 0, 49, 3, 3, 9961 },
1417 { 45158400, 0, 45, 3, 3, 10381 },
1418 { 180633600, 0, 45, 3, 1, 10381 },
1419};
1420
1421static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1422{
1423 unsigned int epll_con, epll_con_k;
1424 unsigned int i;
1425 unsigned int tmp;
1426 unsigned int epll_rate;
1427 unsigned int locktime;
1428 unsigned int lockcnt;
1429
1430 /* Return if nothing changed */
1431 if (clk->rate == rate)
1432 return 0;
1433
1434 if (clk->parent)
1435 epll_rate = clk_get_rate(clk->parent);
1436 else
1437 epll_rate = clk_ext_xtal_mux.rate;
1438
1439 if (epll_rate != 24000000) {
1440 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1441 return -EINVAL;
1442 }
1443
1444 epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1445 epll_con &= ~(0x1 << 27 | \
1446 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1447 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1448 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1449
1450 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1451 if (epll_div[i][0] == rate) {
1452 epll_con_k = epll_div[i][5] << 0;
1453 epll_con |= epll_div[i][1] << 27;
1454 epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1455 epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1456 epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1457 break;
1458 }
1459 }
1460
1461 if (i == ARRAY_SIZE(epll_div)) {
1462 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1463 __func__);
1464 return -EINVAL;
1465 }
1466
1467 epll_rate /= 1000000;
1468
1469 /* 3000 max_cycls : specification data */
1470 locktime = 3000 / epll_rate * epll_div[i][3];
1471 lockcnt = locktime * 10000 / (10000 / epll_rate);
1472
1473 __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1474
1475 __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1476 __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1477
1478 do {
1479 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1480 } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1481
1482 clk->rate = rate;
1483
1484 return 0;
1485}
1486
1487static struct clk_ops exynos5_epll_ops = {
1488 .get_rate = exynos5_epll_get_rate,
1489 .set_rate = exynos5_epll_set_rate,
1490};
1491
1492static int xtal_rate;
1493
1494static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1495{
1496 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1497}
1498
1499static struct clk_ops exynos5_fout_apll_ops = {
1500 .get_rate = exynos5_fout_apll_get_rate,
1501};
1502
1503#ifdef CONFIG_PM
1504static int exynos5_clock_suspend(void)
1505{
1506 s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1507
1508 return 0;
1509}
1510
1511static void exynos5_clock_resume(void)
1512{
1513 s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1514}
1515#else
1516#define exynos5_clock_suspend NULL
1517#define exynos5_clock_resume NULL
1518#endif
1519
1520static struct syscore_ops exynos5_clock_syscore_ops = {
1521 .suspend = exynos5_clock_suspend,
1522 .resume = exynos5_clock_resume,
1523};
1524
1525void __init_or_cpufreq exynos5_setup_clocks(void)
1526{
1527 struct clk *xtal_clk;
1528 unsigned long apll;
1529 unsigned long bpll;
1530 unsigned long cpll;
1531 unsigned long mpll;
1532 unsigned long epll;
1533 unsigned long vpll;
1534 unsigned long vpllsrc;
1535 unsigned long xtal;
1536 unsigned long armclk;
1537 unsigned long mout_cdrex;
1538 unsigned long aclk_400;
1539 unsigned long aclk_333;
1540 unsigned long aclk_266;
1541 unsigned long aclk_200;
1542 unsigned long aclk_166;
1543 unsigned long aclk_66;
1544 unsigned int ptr;
1545
1546 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1547
1548 xtal_clk = clk_get(NULL, "xtal");
1549 BUG_ON(IS_ERR(xtal_clk));
1550
1551 xtal = clk_get_rate(xtal_clk);
1552
1553 xtal_rate = xtal;
1554
1555 clk_put(xtal_clk);
1556
1557 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1558
1559 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1560 bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1561 cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1562 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1563 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1564 __raw_readl(EXYNOS5_EPLL_CON1));
1565
1566 vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1567 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1568 __raw_readl(EXYNOS5_VPLL_CON1));
1569
1570 clk_fout_apll.ops = &exynos5_fout_apll_ops;
1571 clk_fout_bpll.rate = bpll;
1572 clk_fout_bpll_div2.rate = bpll >> 1;
1573 clk_fout_cpll.rate = cpll;
1574 clk_fout_mpll.rate = mpll;
1575 clk_fout_mpll_div2.rate = mpll >> 1;
1576 clk_fout_epll.rate = epll;
1577 clk_fout_vpll.rate = vpll;
1578
1579 printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1580 "M=%ld, E=%ld V=%ld",
1581 apll, bpll, cpll, mpll, epll, vpll);
1582
1583 armclk = clk_get_rate(&exynos5_clk_armclk);
1584 mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1585
1586 aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1587 aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1588 aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1589 aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1590 aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1591 aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1592
1593 printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1594 "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1595 "ACLK166=%ld, ACLK66=%ld\n",
1596 armclk, mout_cdrex, aclk_400,
1597 aclk_333, aclk_266, aclk_200,
1598 aclk_166, aclk_66);
1599
1600
1601 clk_fout_epll.ops = &exynos5_epll_ops;
1602
1603 if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1604 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1605 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1606
1607 clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1608 clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1609
1610 clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1611 clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1612
1613 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1614 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1615}
1616
1617void __init exynos5_register_clocks(void)
1618{
1619 int ptr;
1620
1621 s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1622
1623 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1624 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1625
1626 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1627 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1628
1629 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1630 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1631
1632 s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1633 s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1634
1635 s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1636 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1637 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1638
1639 s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1640 s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1641 clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1642
1643 register_syscore_ops(&exynos5_clock_syscore_ops);
1644 s3c_pwmclk_init();
1645}
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index db7dbd0eb6b4..d3efd6768ff8 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -25,6 +25,8 @@
25#include <linux/irqdomain.h> 25#include <linux/irqdomain.h>
26#include <linux/irqchip.h> 26#include <linux/irqchip.h>
27#include <linux/of_address.h> 27#include <linux/of_address.h>
28#include <linux/clocksource.h>
29#include <linux/clk-provider.h>
28#include <linux/irqchip/arm-gic.h> 30#include <linux/irqchip/arm-gic.h>
29 31
30#include <asm/proc-fns.h> 32#include <asm/proc-fns.h>
@@ -39,7 +41,6 @@
39#include <mach/regs-gpio.h> 41#include <mach/regs-gpio.h>
40 42
41#include <plat/cpu.h> 43#include <plat/cpu.h>
42#include <plat/clock.h>
43#include <plat/devs.h> 44#include <plat/devs.h>
44#include <plat/pm.h> 45#include <plat/pm.h>
45#include <plat/sdhci.h> 46#include <plat/sdhci.h>
@@ -65,17 +66,16 @@ static const char name_exynos5440[] = "EXYNOS5440";
65static void exynos4_map_io(void); 66static void exynos4_map_io(void);
66static void exynos5_map_io(void); 67static void exynos5_map_io(void);
67static void exynos5440_map_io(void); 68static void exynos5440_map_io(void);
68static void exynos4_init_clocks(int xtal);
69static void exynos5_init_clocks(int xtal);
70static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no); 69static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
71static int exynos_init(void); 70static int exynos_init(void);
72 71
72unsigned long xxti_f = 0, xusbxti_f = 0;
73
73static struct cpu_table cpu_ids[] __initdata = { 74static struct cpu_table cpu_ids[] __initdata = {
74 { 75 {
75 .idcode = EXYNOS4210_CPU_ID, 76 .idcode = EXYNOS4210_CPU_ID,
76 .idmask = EXYNOS4_CPU_MASK, 77 .idmask = EXYNOS4_CPU_MASK,
77 .map_io = exynos4_map_io, 78 .map_io = exynos4_map_io,
78 .init_clocks = exynos4_init_clocks,
79 .init_uarts = exynos4_init_uarts, 79 .init_uarts = exynos4_init_uarts,
80 .init = exynos_init, 80 .init = exynos_init,
81 .name = name_exynos4210, 81 .name = name_exynos4210,
@@ -83,7 +83,6 @@ static struct cpu_table cpu_ids[] __initdata = {
83 .idcode = EXYNOS4212_CPU_ID, 83 .idcode = EXYNOS4212_CPU_ID,
84 .idmask = EXYNOS4_CPU_MASK, 84 .idmask = EXYNOS4_CPU_MASK,
85 .map_io = exynos4_map_io, 85 .map_io = exynos4_map_io,
86 .init_clocks = exynos4_init_clocks,
87 .init_uarts = exynos4_init_uarts, 86 .init_uarts = exynos4_init_uarts,
88 .init = exynos_init, 87 .init = exynos_init,
89 .name = name_exynos4212, 88 .name = name_exynos4212,
@@ -91,7 +90,6 @@ static struct cpu_table cpu_ids[] __initdata = {
91 .idcode = EXYNOS4412_CPU_ID, 90 .idcode = EXYNOS4412_CPU_ID,
92 .idmask = EXYNOS4_CPU_MASK, 91 .idmask = EXYNOS4_CPU_MASK,
93 .map_io = exynos4_map_io, 92 .map_io = exynos4_map_io,
94 .init_clocks = exynos4_init_clocks,
95 .init_uarts = exynos4_init_uarts, 93 .init_uarts = exynos4_init_uarts,
96 .init = exynos_init, 94 .init = exynos_init,
97 .name = name_exynos4412, 95 .name = name_exynos4412,
@@ -99,7 +97,6 @@ static struct cpu_table cpu_ids[] __initdata = {
99 .idcode = EXYNOS5250_SOC_ID, 97 .idcode = EXYNOS5250_SOC_ID,
100 .idmask = EXYNOS5_SOC_MASK, 98 .idmask = EXYNOS5_SOC_MASK,
101 .map_io = exynos5_map_io, 99 .map_io = exynos5_map_io,
102 .init_clocks = exynos5_init_clocks,
103 .init = exynos_init, 100 .init = exynos_init,
104 .name = name_exynos5250, 101 .name = name_exynos5250,
105 }, { 102 }, {
@@ -397,43 +394,26 @@ static void __init exynos5_map_io(void)
397 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); 394 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
398} 395}
399 396
400static void __init exynos4_init_clocks(int xtal)
401{
402 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
403
404 s3c24xx_register_baseclocks(xtal);
405 s5p_register_clocks(xtal);
406
407 if (soc_is_exynos4210())
408 exynos4210_register_clocks();
409 else if (soc_is_exynos4212() || soc_is_exynos4412())
410 exynos4212_register_clocks();
411
412 exynos4_register_clocks();
413 exynos4_setup_clocks();
414}
415
416static void __init exynos5440_map_io(void) 397static void __init exynos5440_map_io(void)
417{ 398{
418 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0)); 399 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
419} 400}
420 401
421static void __init exynos5_init_clocks(int xtal) 402void __init exynos_init_time(void)
422{ 403{
423 printk(KERN_DEBUG "%s: initializing clocks\n", __func__); 404 if (of_have_populated_dt()) {
424 405#ifdef CONFIG_OF
425 /* EXYNOS5440 can support only common clock framework */ 406 of_clk_init(NULL);
426 407 clocksource_of_init();
427 if (soc_is_exynos5440()) 408#endif
428 return; 409 } else {
429 410 /* todo: remove after migrating legacy E4 platforms to dt */
430#ifdef CONFIG_SOC_EXYNOS5250 411#ifdef CONFIG_ARCH_EXYNOS4
431 s3c24xx_register_baseclocks(xtal); 412 exynos4_clk_init(NULL);
432 s5p_register_clocks(xtal); 413 exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
433
434 exynos5_register_clocks();
435 exynos5_setup_clocks();
436#endif 414#endif
415 mct_init();
416 }
437} 417}
438 418
439void __init exynos4_init_irq(void) 419void __init exynos4_init_irq(void)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 3b186eaaaa7b..cb89ab886950 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,7 +12,11 @@
12#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H 12#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
13#define __ARCH_ARM_MACH_EXYNOS_COMMON_H 13#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
14 14
15#include <linux/of.h>
16
15extern void mct_init(void); 17extern void mct_init(void);
18void exynos_init_time(void);
19extern unsigned long xxti_f, xusbxti_f;
16 20
17struct map_desc; 21struct map_desc;
18void exynos_init_io(struct map_desc *mach_desc, int size); 22void exynos_init_io(struct map_desc *mach_desc, int size);
@@ -22,6 +26,10 @@ void exynos4_restart(char mode, const char *cmd);
22void exynos5_restart(char mode, const char *cmd); 26void exynos5_restart(char mode, const char *cmd);
23void exynos_init_late(void); 27void exynos_init_late(void);
24 28
29/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
30void exynos4_clk_init(struct device_node *np);
31void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
32
25#ifdef CONFIG_PM_GENERIC_DOMAINS 33#ifdef CONFIG_PM_GENERIC_DOMAINS
26int exynos_pm_late_initcall(void); 34int exynos_pm_late_initcall(void);
27#else 35#else
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index d36ad76ad6a4..20fbbdddd105 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -256,113 +256,6 @@
256#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) 256#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
257#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) 257#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
258 258
259/* For EXYNOS5250 */
260
261#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
262#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
263#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
264#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)
265#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
266#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)
267#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)
268#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)
269
270#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020)
271#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024)
272
273#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
274#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
275
276#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
277
278#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
279
280#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
281#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
282#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)
283#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
284#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
285#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)
286#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
287
288#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
289#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)
290#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
291#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
292#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
293#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
294#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)
295#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
296#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
297#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
298#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)
299
300#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
301#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
302#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
303#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)
304#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
305#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
306#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
307
308#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
309#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
310#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
311#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
312#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
313#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)
314#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
315#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
316#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
317#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
318#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
319#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
320#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
321#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)
322#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)
323#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)
324#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)
325
326#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
327#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
328#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)
329#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
330#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
331#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
332#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)
333#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
334#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
335#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
336#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
337#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
338#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
339
340#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
341#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
342#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
343
344#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
345
346#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
347
348#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
349
350#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
351#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
352#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
353#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
354#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
355#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
356#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
357#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
358
359#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
360#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
361#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
362#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
363#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
364#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
365
366/* Compatibility defines and inclusion */ 259/* Compatibility defines and inclusion */
367 260
368#include <mach/regs-pmu.h> 261#include <mach/regs-pmu.h>
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index 3b1a34742679..2c23b659ae3e 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -177,7 +177,6 @@ static void __init armlex4210_smsc911x_init(void)
177static void __init armlex4210_map_io(void) 177static void __init armlex4210_map_io(void)
178{ 178{
179 exynos_init_io(NULL, 0); 179 exynos_init_io(NULL, 0);
180 s3c24xx_init_clocks(24000000);
181 s3c24xx_init_uarts(armlex4210_uartcfgs, 180 s3c24xx_init_uarts(armlex4210_uartcfgs,
182 ARRAY_SIZE(armlex4210_uartcfgs)); 181 ARRAY_SIZE(armlex4210_uartcfgs));
183} 182}
@@ -202,6 +201,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
202 .map_io = armlex4210_map_io, 201 .map_io = armlex4210_map_io,
203 .init_machine = armlex4210_machine_init, 202 .init_machine = armlex4210_machine_init,
204 .init_late = exynos_init_late, 203 .init_late = exynos_init_late,
205 .init_time = mct_init, 204 .init_time = exynos_init_time,
206 .restart = exynos4_restart, 205 .restart = exynos4_restart,
207MACHINE_END 206MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index c4ae108e192d..ac27f3cd121f 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -11,122 +11,26 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12*/ 12*/
13 13
14#include <linux/kernel.h>
14#include <linux/of_platform.h> 15#include <linux/of_platform.h>
16#include <linux/of_fdt.h>
15#include <linux/serial_core.h> 17#include <linux/serial_core.h>
18#include <linux/memblock.h>
16#include <linux/clocksource.h> 19#include <linux/clocksource.h>
17 20
18#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
19#include <mach/map.h> 22#include <plat/mfc.h>
20
21#include <plat/cpu.h>
22#include <plat/regs-serial.h>
23 23
24#include "common.h" 24#include "common.h"
25 25
26/*
27 * The following lookup table is used to override device names when devices
28 * are registered from device tree. This is temporarily added to enable
29 * device tree support addition for the Exynos4 architecture.
30 *
31 * For drivers that require platform data to be provided from the machine
32 * file, a platform data pointer can also be supplied along with the
33 * devices names. Usually, the platform data elements that cannot be parsed
34 * from the device tree by the drivers (example: function pointers) are
35 * supplied. But it should be noted that this is a temporary mechanism and
36 * at some point, the drivers should be capable of parsing all the platform
37 * data from the device tree.
38 */
39static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
40 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
41 "exynos4210-uart.0", NULL),
42 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
43 "exynos4210-uart.1", NULL),
44 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
45 "exynos4210-uart.2", NULL),
46 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
47 "exynos4210-uart.3", NULL),
48 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
49 "exynos4-sdhci.0", NULL),
50 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
51 "exynos4-sdhci.1", NULL),
52 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
53 "exynos4-sdhci.2", NULL),
54 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
55 "exynos4-sdhci.3", NULL),
56 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
57 "s3c2440-i2c.0", NULL),
58 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
59 "s3c2440-i2c.1", NULL),
60 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
61 "s3c2440-i2c.2", NULL),
62 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
63 "s3c2440-i2c.3", NULL),
64 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
65 "s3c2440-i2c.4", NULL),
66 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
67 "s3c2440-i2c.5", NULL),
68 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
69 "s3c2440-i2c.6", NULL),
70 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
71 "s3c2440-i2c.7", NULL),
72 OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
73 "exynos4210-spi.0", NULL),
74 OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
75 "exynos4210-spi.1", NULL),
76 OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
77 "exynos4210-spi.2", NULL),
78 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
79 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
80 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
81 OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
82 "exynos-tmu", NULL),
83 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
84 "exynos-sysmmu.0", NULL), /* MFC_L */
85 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
86 "exynos-sysmmu.1", NULL), /* MFC_R */
87 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
88 "exynos-sysmmu.2", NULL), /* TV */
89 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
90 "exynos-sysmmu.3", NULL), /* JPEG */
91 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
92 "exynos-sysmmu.4", NULL), /* ROTATOR */
93 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
94 "exynos-sysmmu.5", NULL), /* FIMC0 */
95 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
96 "exynos-sysmmu.6", NULL), /* FIMC1 */
97 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
98 "exynos-sysmmu.7", NULL), /* FIMC2 */
99 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
100 "exynos-sysmmu.8", NULL), /* FIMC3 */
101 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
102 "exynos-sysmmu.9", NULL), /* G2D(4210) */
103 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
104 "exynos-sysmmu.9", NULL), /* G2D(4x12) */
105 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
106 "exynos-sysmmu.10", NULL), /* FIMD0 */
107 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
108 "exynos-sysmmu.11", NULL), /* FIMD1(4210) */
109 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
110 "exynos-sysmmu.12", NULL), /* IS0(4x12) */
111 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
112 "exynos-sysmmu.13", NULL), /* IS1(4x12) */
113 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
114 "exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
115 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
116 "exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
117 {},
118};
119
120static void __init exynos4_dt_map_io(void) 26static void __init exynos4_dt_map_io(void)
121{ 27{
122 exynos_init_io(NULL, 0); 28 exynos_init_io(NULL, 0);
123 s3c24xx_init_clocks(24000000);
124} 29}
125 30
126static void __init exynos4_dt_machine_init(void) 31static void __init exynos4_dt_machine_init(void)
127{ 32{
128 of_platform_populate(NULL, of_default_bus_match_table, 33 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
129 exynos4_auxdata_lookup, NULL);
130} 34}
131 35
132static char const *exynos4_dt_compat[] __initdata = { 36static char const *exynos4_dt_compat[] __initdata = {
@@ -136,6 +40,18 @@ static char const *exynos4_dt_compat[] __initdata = {
136 NULL 40 NULL
137}; 41};
138 42
43static void __init exynos4_reserve(void)
44{
45#ifdef CONFIG_S5P_DEV_MFC
46 struct s5p_mfc_dt_meminfo mfc_mem;
47
48 /* Reserve memory for MFC only if it's available */
49 mfc_mem.compatible = "samsung,mfc-v5";
50 if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
51 s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
52 mfc_mem.lsize);
53#endif
54}
139DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") 55DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
140 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ 56 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
141 .smp = smp_ops(exynos_smp_ops), 57 .smp = smp_ops(exynos_smp_ops),
@@ -143,7 +59,8 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
143 .map_io = exynos4_dt_map_io, 59 .map_io = exynos4_dt_map_io,
144 .init_machine = exynos4_dt_machine_init, 60 .init_machine = exynos4_dt_machine_init,
145 .init_late = exynos_init_late, 61 .init_late = exynos_init_late,
146 .init_time = clocksource_of_init, 62 .init_time = exynos_init_time,
147 .dt_compat = exynos4_dt_compat, 63 .dt_compat = exynos4_dt_compat,
148 .restart = exynos4_restart, 64 .restart = exynos4_restart,
65 .reserve = exynos4_reserve,
149MACHINE_END 66MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 7da4791bfb8b..753b94f3fca7 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,152 +11,21 @@
11 11
12#include <linux/of_platform.h> 12#include <linux/of_platform.h>
13#include <linux/of_fdt.h> 13#include <linux/of_fdt.h>
14#include <linux/serial_core.h>
15#include <linux/memblock.h> 14#include <linux/memblock.h>
16#include <linux/io.h> 15#include <linux/io.h>
17#include <linux/clocksource.h> 16#include <linux/clocksource.h>
18 17
19#include <asm/mach/arch.h> 18#include <asm/mach/arch.h>
20#include <mach/map.h>
21#include <mach/regs-pmu.h> 19#include <mach/regs-pmu.h>
22 20
23#include <plat/cpu.h> 21#include <plat/cpu.h>
24#include <plat/regs-serial.h>
25#include <plat/mfc.h> 22#include <plat/mfc.h>
26 23
27#include "common.h" 24#include "common.h"
28 25
29/*
30 * The following lookup table is used to override device names when devices
31 * are registered from device tree. This is temporarily added to enable
32 * device tree support addition for the EXYNOS5 architecture.
33 *
34 * For drivers that require platform data to be provided from the machine
35 * file, a platform data pointer can also be supplied along with the
36 * devices names. Usually, the platform data elements that cannot be parsed
37 * from the device tree by the drivers (example: function pointers) are
38 * supplied. But it should be noted that this is a temporary mechanism and
39 * at some point, the drivers should be capable of parsing all the platform
40 * data from the device tree.
41 */
42static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
43 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
44 "exynos4210-uart.0", NULL),
45 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
46 "exynos4210-uart.1", NULL),
47 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
48 "exynos4210-uart.2", NULL),
49 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
50 "exynos4210-uart.3", NULL),
51 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
52 "s3c2440-i2c.0", NULL),
53 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
54 "s3c2440-i2c.1", NULL),
55 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
56 "s3c2440-i2c.2", NULL),
57 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
58 "s3c2440-i2c.3", NULL),
59 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
60 "s3c2440-i2c.4", NULL),
61 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
62 "s3c2440-i2c.5", NULL),
63 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
64 "s3c2440-i2c.6", NULL),
65 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
66 "s3c2440-i2c.7", NULL),
67 OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
68 "s3c2440-hdmiphy-i2c", NULL),
69 OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
70 "dw_mmc.0", NULL),
71 OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
72 "dw_mmc.1", NULL),
73 OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
74 "dw_mmc.2", NULL),
75 OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
76 "dw_mmc.3", NULL),
77 OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
78 "exynos4210-spi.0", NULL),
79 OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
80 "exynos4210-spi.1", NULL),
81 OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
82 "exynos4210-spi.2", NULL),
83 OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
84 "exynos5-sata", NULL),
85 OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
86 "exynos5-sata-phy", NULL),
87 OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
88 "exynos5-sata-phy-i2c", NULL),
89 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
90 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
91 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
92 OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
93 "exynos-gsc.0", NULL),
94 OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
95 "exynos-gsc.1", NULL),
96 OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
97 "exynos-gsc.2", NULL),
98 OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
99 "exynos-gsc.3", NULL),
100 OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
101 "exynos5-hdmi", NULL),
102 OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
103 "exynos5-mixer", NULL),
104 OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
105 OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
106 "exynos-tmu", NULL),
107 OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000,
108 "samsung-i2s.0", NULL),
109 OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000,
110 "samsung-i2s.1", NULL),
111 OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000,
112 "samsung-i2s.2", NULL),
113 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
114 "exynos-sysmmu.0", "mfc"), /* MFC_L */
115 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
116 "exynos-sysmmu.1", "mfc"), /* MFC_R */
117 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
118 "exynos-sysmmu.2", NULL), /* TV */
119 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
120 "exynos-sysmmu.3", "jpeg"), /* JPEG */
121 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
122 "exynos-sysmmu.4", NULL), /* ROTATOR */
123 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
124 "exynos-sysmmu.5", "gscl"), /* GSCL0 */
125 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
126 "exynos-sysmmu.6", "gscl"), /* GSCL1 */
127 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
128 "exynos-sysmmu.7", "gscl"), /* GSCL2 */
129 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
130 "exynos-sysmmu.8", "gscl"), /* GSCL3 */
131 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
132 "exynos-sysmmu.9", NULL), /* FIMC-IS0 */
133 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
134 "exynos-sysmmu.10", NULL), /* FIMC-IS1 */
135 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
136 "exynos-sysmmu.11", NULL), /* FIMD1 */
137 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
138 "exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
139 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
140 "exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
141 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
142 "exynos-sysmmu.14", NULL), /* G2D */
143 {},
144};
145
146static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
147 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
148 "exynos4210-uart.0", NULL),
149 {},
150};
151
152static void __init exynos5_dt_map_io(void) 26static void __init exynos5_dt_map_io(void)
153{ 27{
154 unsigned long root = of_get_flat_dt_root();
155
156 exynos_init_io(NULL, 0); 28 exynos_init_io(NULL, 0);
157
158 if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
159 s3c24xx_init_clocks(24000000);
160} 29}
161 30
162static void __init exynos5_dt_machine_init(void) 31static void __init exynos5_dt_machine_init(void)
@@ -183,12 +52,7 @@ static void __init exynos5_dt_machine_init(void)
183 } 52 }
184 } 53 }
185 54
186 if (of_machine_is_compatible("samsung,exynos5250")) 55 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
187 of_platform_populate(NULL, of_default_bus_match_table,
188 exynos5250_auxdata_lookup, NULL);
189 else if (of_machine_is_compatible("samsung,exynos5440"))
190 of_platform_populate(NULL, of_default_bus_match_table,
191 exynos5440_auxdata_lookup, NULL);
192} 56}
193 57
194static char const *exynos5_dt_compat[] __initdata = { 58static char const *exynos5_dt_compat[] __initdata = {
@@ -217,7 +81,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
217 .map_io = exynos5_dt_map_io, 81 .map_io = exynos5_dt_map_io,
218 .init_machine = exynos5_dt_machine_init, 82 .init_machine = exynos5_dt_machine_init,
219 .init_late = exynos_init_late, 83 .init_late = exynos_init_late,
220 .init_time = clocksource_of_init, 84 .init_time = exynos_init_time,
221 .dt_compat = exynos5_dt_compat, 85 .dt_compat = exynos5_dt_compat,
222 .restart = exynos5_restart, 86 .restart = exynos5_restart,
223 .reserve = exynos5_reserve, 87 .reserve = exynos5_reserve,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index da3605d15110..0c10852423c3 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1330,8 +1330,9 @@ static struct platform_device *nuri_devices[] __initdata = {
1330static void __init nuri_map_io(void) 1330static void __init nuri_map_io(void)
1331{ 1331{
1332 exynos_init_io(NULL, 0); 1332 exynos_init_io(NULL, 0);
1333 s3c24xx_init_clocks(clk_xusbxti.rate);
1334 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); 1333 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
1334 xxti_f = 0;
1335 xusbxti_f = 24000000;
1335} 1336}
1336 1337
1337static void __init nuri_reserve(void) 1338static void __init nuri_reserve(void)
@@ -1380,7 +1381,7 @@ MACHINE_START(NURI, "NURI")
1380 .map_io = nuri_map_io, 1381 .map_io = nuri_map_io,
1381 .init_machine = nuri_machine_init, 1382 .init_machine = nuri_machine_init,
1382 .init_late = exynos_init_late, 1383 .init_late = exynos_init_late,
1383 .init_time = mct_init, 1384 .init_time = exynos_init_time,
1384 .reserve = &nuri_reserve, 1385 .reserve = &nuri_reserve,
1385 .restart = exynos4_restart, 1386 .restart = exynos4_restart,
1386MACHINE_END 1387MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 1772cd284f4c..a9aa5c034b23 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -754,8 +754,9 @@ static void s5p_tv_setup(void)
754static void __init origen_map_io(void) 754static void __init origen_map_io(void)
755{ 755{
756 exynos_init_io(NULL, 0); 756 exynos_init_io(NULL, 0);
757 s3c24xx_init_clocks(clk_xusbxti.rate);
758 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); 757 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
758 xxti_f = 0;
759 xusbxti_f = 24000000;
759} 760}
760 761
761static void __init origen_power_init(void) 762static void __init origen_power_init(void)
@@ -815,7 +816,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
815 .map_io = origen_map_io, 816 .map_io = origen_map_io,
816 .init_machine = origen_machine_init, 817 .init_machine = origen_machine_init,
817 .init_late = exynos_init_late, 818 .init_late = exynos_init_late,
818 .init_time = mct_init, 819 .init_time = exynos_init_time,
819 .reserve = &origen_reserve, 820 .reserve = &origen_reserve,
820 .restart = exynos4_restart, 821 .restart = exynos4_restart,
821MACHINE_END 822MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index 34a6356364eb..184faa3bd93a 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -322,7 +322,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
322static void __init smdk4x12_map_io(void) 322static void __init smdk4x12_map_io(void)
323{ 323{
324 exynos_init_io(NULL, 0); 324 exynos_init_io(NULL, 0);
325 s3c24xx_init_clocks(clk_xusbxti.rate);
326 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs)); 325 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
327} 326}
328 327
@@ -376,7 +375,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
376 .init_irq = exynos4_init_irq, 375 .init_irq = exynos4_init_irq,
377 .map_io = smdk4x12_map_io, 376 .map_io = smdk4x12_map_io,
378 .init_machine = smdk4x12_machine_init, 377 .init_machine = smdk4x12_machine_init,
379 .init_time = mct_init, 378 .init_time = exynos_init_time,
380 .restart = exynos4_restart, 379 .restart = exynos4_restart,
381 .reserve = &smdk4x12_reserve, 380 .reserve = &smdk4x12_reserve,
382MACHINE_END 381MACHINE_END
@@ -390,7 +389,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
390 .map_io = smdk4x12_map_io, 389 .map_io = smdk4x12_map_io,
391 .init_machine = smdk4x12_machine_init, 390 .init_machine = smdk4x12_machine_init,
392 .init_late = exynos_init_late, 391 .init_late = exynos_init_late,
393 .init_time = mct_init, 392 .init_time = exynos_init_time,
394 .restart = exynos4_restart, 393 .restart = exynos4_restart,
395 .reserve = &smdk4x12_reserve, 394 .reserve = &smdk4x12_reserve,
396MACHINE_END 395MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 893b14e8c62a..75eca7d4e128 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -371,8 +371,9 @@ static void s5p_tv_setup(void)
371static void __init smdkv310_map_io(void) 371static void __init smdkv310_map_io(void)
372{ 372{
373 exynos_init_io(NULL, 0); 373 exynos_init_io(NULL, 0);
374 s3c24xx_init_clocks(clk_xusbxti.rate);
375 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); 374 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
375 xxti_f = 12000000;
376 xusbxti_f = 24000000;
376} 377}
377 378
378static void __init smdkv310_reserve(void) 379static void __init smdkv310_reserve(void)
@@ -423,7 +424,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
423 .init_irq = exynos4_init_irq, 424 .init_irq = exynos4_init_irq,
424 .map_io = smdkv310_map_io, 425 .map_io = smdkv310_map_io,
425 .init_machine = smdkv310_machine_init, 426 .init_machine = smdkv310_machine_init,
426 .init_time = mct_init, 427 .init_time = exynos_init_time,
427 .reserve = &smdkv310_reserve, 428 .reserve = &smdkv310_reserve,
428 .restart = exynos4_restart, 429 .restart = exynos4_restart,
429MACHINE_END 430MACHINE_END
@@ -436,7 +437,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
436 .map_io = smdkv310_map_io, 437 .map_io = smdkv310_map_io,
437 .init_machine = smdkv310_machine_init, 438 .init_machine = smdkv310_machine_init,
438 .init_late = exynos_init_late, 439 .init_late = exynos_init_late,
439 .init_time = mct_init, 440 .init_time = exynos_init_time,
440 .reserve = &smdkv310_reserve, 441 .reserve = &smdkv310_reserve,
441 .restart = exynos4_restart, 442 .restart = exynos4_restart,
442MACHINE_END 443MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index c870b0aaa5e0..72f08fd7cfa9 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -1092,9 +1092,10 @@ static struct platform_device *universal_devices[] __initdata = {
1092static void __init universal_map_io(void) 1092static void __init universal_map_io(void)
1093{ 1093{
1094 exynos_init_io(NULL, 0); 1094 exynos_init_io(NULL, 0);
1095 s3c24xx_init_clocks(clk_xusbxti.rate);
1096 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); 1095 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
1097 samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4); 1096 samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
1097 xxti_f = 0;
1098 xusbxti_f = 24000000;
1098} 1099}
1099 1100
1100static void s5p_tv_setup(void) 1101static void s5p_tv_setup(void)
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index b708b3e56d27..6cb19c6aa9d6 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -25,7 +25,7 @@ config PLAT_S5P
25 select PLAT_SAMSUNG 25 select PLAT_SAMSUNG
26 select S3C_GPIO_TRACK 26 select S3C_GPIO_TRACK
27 select S5P_GPIO_DRVSTR 27 select S5P_GPIO_DRVSTR
28 select SAMSUNG_CLKSRC 28 select SAMSUNG_CLKSRC if !COMMON_CLK
29 select SAMSUNG_GPIOLIB_4BIT 29 select SAMSUNG_GPIOLIB_4BIT
30 select SAMSUNG_IRQ_VIC_TIMER 30 select SAMSUNG_IRQ_VIC_TIMER
31 help 31 help
@@ -89,7 +89,7 @@ config SAMSUNG_CLKSRC
89 used by newer systems such as the S3C64XX. 89 used by newer systems such as the S3C64XX.
90 90
91config S5P_CLOCK 91config S5P_CLOCK
92 def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) 92 def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
93 help 93 help
94 Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs 94 Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
95 95
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 79e98e416724..17e8dc4e417c 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_ARCH_U8500) += ux500/
29obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o 29obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
30obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o 30obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
31obj-$(CONFIG_ARCH_TEGRA) += tegra/ 31obj-$(CONFIG_ARCH_TEGRA) += tegra/
32obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
32 33
33obj-$(CONFIG_X86) += x86/ 34obj-$(CONFIG_X86) += x86/
34 35
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
new file mode 100644
index 000000000000..b7c232e67425
--- /dev/null
+++ b/drivers/clk/samsung/Makefile
@@ -0,0 +1,8 @@
1#
2# Samsung Clock specific Makefile
3#
4
5obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
6obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
7obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
8obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
new file mode 100644
index 000000000000..71046694d9dd
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -0,0 +1,1091 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for all Exynos4 SoCs.
11*/
12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#include <plat/cpu.h>
20#include "clk.h"
21#include "clk-pll.h"
22
23/* Exynos4 clock controller register offsets */
24#define SRC_LEFTBUS 0x4200
25#define DIV_LEFTBUS 0x4500
26#define GATE_IP_LEFTBUS 0x4800
27#define E4X12_GATE_IP_IMAGE 0x4930
28#define SRC_RIGHTBUS 0x8200
29#define DIV_RIGHTBUS 0x8500
30#define GATE_IP_RIGHTBUS 0x8800
31#define E4X12_GATE_IP_PERIR 0x8960
32#define EPLL_LOCK 0xc010
33#define VPLL_LOCK 0xc020
34#define EPLL_CON0 0xc110
35#define EPLL_CON1 0xc114
36#define EPLL_CON2 0xc118
37#define VPLL_CON0 0xc120
38#define VPLL_CON1 0xc124
39#define VPLL_CON2 0xc128
40#define SRC_TOP0 0xc210
41#define SRC_TOP1 0xc214
42#define SRC_CAM 0xc220
43#define SRC_TV 0xc224
44#define SRC_MFC 0xcc28
45#define SRC_G3D 0xc22c
46#define E4210_SRC_IMAGE 0xc230
47#define SRC_LCD0 0xc234
48#define E4210_SRC_LCD1 0xc238
49#define E4X12_SRC_ISP 0xc238
50#define SRC_MAUDIO 0xc23c
51#define SRC_FSYS 0xc240
52#define SRC_PERIL0 0xc250
53#define SRC_PERIL1 0xc254
54#define E4X12_SRC_CAM1 0xc258
55#define SRC_MASK_TOP 0xc310
56#define SRC_MASK_CAM 0xc320
57#define SRC_MASK_TV 0xc324
58#define SRC_MASK_LCD0 0xc334
59#define E4210_SRC_MASK_LCD1 0xc338
60#define E4X12_SRC_MASK_ISP 0xc338
61#define SRC_MASK_MAUDIO 0xc33c
62#define SRC_MASK_FSYS 0xc340
63#define SRC_MASK_PERIL0 0xc350
64#define SRC_MASK_PERIL1 0xc354
65#define DIV_TOP 0xc510
66#define DIV_CAM 0xc520
67#define DIV_TV 0xc524
68#define DIV_MFC 0xc528
69#define DIV_G3D 0xc52c
70#define DIV_IMAGE 0xc530
71#define DIV_LCD0 0xc534
72#define E4210_DIV_LCD1 0xc538
73#define E4X12_DIV_ISP 0xc538
74#define DIV_MAUDIO 0xc53c
75#define DIV_FSYS0 0xc540
76#define DIV_FSYS1 0xc544
77#define DIV_FSYS2 0xc548
78#define DIV_FSYS3 0xc54c
79#define DIV_PERIL0 0xc550
80#define DIV_PERIL1 0xc554
81#define DIV_PERIL2 0xc558
82#define DIV_PERIL3 0xc55c
83#define DIV_PERIL4 0xc560
84#define DIV_PERIL5 0xc564
85#define E4X12_DIV_CAM1 0xc568
86#define GATE_SCLK_CAM 0xc820
87#define GATE_IP_CAM 0xc920
88#define GATE_IP_TV 0xc924
89#define GATE_IP_MFC 0xc928
90#define GATE_IP_G3D 0xc92c
91#define E4210_GATE_IP_IMAGE 0xc930
92#define GATE_IP_LCD0 0xc934
93#define E4210_GATE_IP_LCD1 0xc938
94#define E4X12_GATE_IP_ISP 0xc938
95#define E4X12_GATE_IP_MAUDIO 0xc93c
96#define GATE_IP_FSYS 0xc940
97#define GATE_IP_GPS 0xc94c
98#define GATE_IP_PERIL 0xc950
99#define E4210_GATE_IP_PERIR 0xc960
100#define GATE_BLOCK 0xc970
101#define E4X12_MPLL_CON0 0x10108
102#define SRC_DMC 0x10200
103#define SRC_MASK_DMC 0x10300
104#define DIV_DMC0 0x10500
105#define DIV_DMC1 0x10504
106#define GATE_IP_DMC 0x10900
107#define APLL_CON0 0x14100
108#define E4210_MPLL_CON0 0x14108
109#define SRC_CPU 0x14200
110#define DIV_CPU0 0x14500
111#define DIV_CPU1 0x14504
112#define GATE_SCLK_CPU 0x14800
113#define GATE_IP_CPU 0x14900
114#define E4X12_DIV_ISP0 0x18300
115#define E4X12_DIV_ISP1 0x18304
116#define E4X12_GATE_ISP0 0x18800
117#define E4X12_GATE_ISP1 0x18804
118
119/* the exynos4 soc type */
120enum exynos4_soc {
121 EXYNOS4210,
122 EXYNOS4X12,
123};
124
125/*
126 * Let each supported clock get a unique id. This id is used to lookup the clock
127 * for device tree based platforms. The clocks are categorized into three
128 * sections: core, sclk gate and bus interface gate clocks.
129 *
130 * When adding a new clock to this list, it is advised to choose a clock
131 * category and add it to the end of that category. That is because the the
132 * device tree source file is referring to these ids and any change in the
133 * sequence number of existing clocks will require corresponding change in the
134 * device tree files. This limitation would go away when pre-processor support
135 * for dtc would be available.
136 */
137enum exynos4_clks {
138 none,
139
140 /* core clocks */
141 xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
142 sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100,
143 aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core,
144 mout_apll, /* 20 */
145
146 /* gate for special clocks (sclk) */
147 sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
148 sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac,
149 sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0,
150 sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4,
151 sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
152 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
153 sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
154 sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
155 sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp,
156
157 /* gate clocks */
158 fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
159 smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi,
160 smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d,
161 smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1,
162 mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0,
163 sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie,
164 onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3,
165 uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc,
166 spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus,
167 spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif,
168 audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0,
169 fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp,
170 gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp,
171 mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp,
172 asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk,
173 spi1_isp_sclk, uart_isp_sclk,
174
175 /* mux clocks */
176 mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
177 mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d,
178 aclk400_mcuisp,
179
180 /* div clocks */
181 div_isp0 = 450, div_isp1, div_mcuisp0, div_mcuisp1, div_aclk200,
182 div_aclk400_mcuisp,
183
184 nr_clks,
185};
186
187/*
188 * list of controller registers to be saved and restored during a
189 * suspend/resume cycle.
190 */
191static __initdata unsigned long exynos4210_clk_save[] = {
192 E4210_SRC_IMAGE,
193 E4210_SRC_LCD1,
194 E4210_SRC_MASK_LCD1,
195 E4210_DIV_LCD1,
196 E4210_GATE_IP_IMAGE,
197 E4210_GATE_IP_LCD1,
198 E4210_GATE_IP_PERIR,
199 E4210_MPLL_CON0,
200};
201
202static __initdata unsigned long exynos4x12_clk_save[] = {
203 E4X12_GATE_IP_IMAGE,
204 E4X12_GATE_IP_PERIR,
205 E4X12_SRC_CAM1,
206 E4X12_DIV_ISP,
207 E4X12_DIV_CAM1,
208 E4X12_MPLL_CON0,
209};
210
211static __initdata unsigned long exynos4_clk_regs[] = {
212 SRC_LEFTBUS,
213 DIV_LEFTBUS,
214 GATE_IP_LEFTBUS,
215 SRC_RIGHTBUS,
216 DIV_RIGHTBUS,
217 GATE_IP_RIGHTBUS,
218 EPLL_CON0,
219 EPLL_CON1,
220 EPLL_CON2,
221 VPLL_CON0,
222 VPLL_CON1,
223 VPLL_CON2,
224 SRC_TOP0,
225 SRC_TOP1,
226 SRC_CAM,
227 SRC_TV,
228 SRC_MFC,
229 SRC_G3D,
230 SRC_LCD0,
231 SRC_MAUDIO,
232 SRC_FSYS,
233 SRC_PERIL0,
234 SRC_PERIL1,
235 SRC_MASK_TOP,
236 SRC_MASK_CAM,
237 SRC_MASK_TV,
238 SRC_MASK_LCD0,
239 SRC_MASK_MAUDIO,
240 SRC_MASK_FSYS,
241 SRC_MASK_PERIL0,
242 SRC_MASK_PERIL1,
243 DIV_TOP,
244 DIV_CAM,
245 DIV_TV,
246 DIV_MFC,
247 DIV_G3D,
248 DIV_IMAGE,
249 DIV_LCD0,
250 DIV_MAUDIO,
251 DIV_FSYS0,
252 DIV_FSYS1,
253 DIV_FSYS2,
254 DIV_FSYS3,
255 DIV_PERIL0,
256 DIV_PERIL1,
257 DIV_PERIL2,
258 DIV_PERIL3,
259 DIV_PERIL4,
260 DIV_PERIL5,
261 GATE_SCLK_CAM,
262 GATE_IP_CAM,
263 GATE_IP_TV,
264 GATE_IP_MFC,
265 GATE_IP_G3D,
266 GATE_IP_LCD0,
267 GATE_IP_FSYS,
268 GATE_IP_GPS,
269 GATE_IP_PERIL,
270 GATE_BLOCK,
271 SRC_MASK_DMC,
272 SRC_DMC,
273 DIV_DMC0,
274 DIV_DMC1,
275 GATE_IP_DMC,
276 APLL_CON0,
277 SRC_CPU,
278 DIV_CPU0,
279 DIV_CPU1,
280 GATE_SCLK_CPU,
281 GATE_IP_CPU,
282};
283
284/* list of all parent clock list */
285PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
286PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
287PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
288PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
289PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
290PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
291PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
292PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
293PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
294PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
295PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", };
296PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
297 "spdif_extclk", };
298PNAME(mout_onenand_p) = {"aclk133", "aclk160", };
299PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
300
301/* Exynos 4210-specific parent groups */
302PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", };
303PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", };
304PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", };
305PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m",
306 "sclk_usbphy0", "none", "sclk_hdmiphy",
307 "sclk_mpll", "sclk_epll", "sclk_vpll", };
308PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
309 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
310 "sclk_epll", "sclk_vpll" };
311PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
312 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
313 "sclk_epll", "sclk_vpll", };
314PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
315 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
316 "sclk_epll", "sclk_vpll", };
317PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
318PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
319
320/* Exynos 4x12-specific parent groups */
321PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
322PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", };
323PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
324PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
325 "none", "sclk_hdmiphy", "mout_mpll_user_t",
326 "sclk_epll", "sclk_vpll", };
327PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
328 "sclk_usbphy0", "xxti", "xusbxti",
329 "mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
330PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
331 "sclk_usbphy0", "xxti", "xusbxti",
332 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
333PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
334 "sclk_usbphy0", "xxti", "xusbxti",
335 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
336PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", };
337PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
338PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
339PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
340
341/* fixed rate clocks generated outside the soc */
342struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
343 FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
344 FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
345};
346
347/* fixed rate clocks generated inside the soc */
348struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
349 FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
350 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
351 FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
352};
353
354struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
355 FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
356};
357
358/* list of mux clocks supported in all exynos4 soc's */
359struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
360 MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
361 CLK_SET_RATE_PARENT, 0),
362 MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
363 MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
364 MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
365 MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
366 CLK_SET_RATE_PARENT, 0),
367 MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
368 CLK_SET_RATE_PARENT, 0),
369 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
370 MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
371 MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),
372 MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
373};
374
375/* list of mux clocks supported in exynos4210 soc */
376struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
377 MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
378 MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
379 MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
380 MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
381 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
382 MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
383 MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
384 MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
385 MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
386 MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
387 MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
388 MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
389 MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"),
390 MUX_A(mout_core, "mout_core", mout_core_p4210,
391 SRC_CPU, 16, 1, "mout_core"),
392 MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
393 SRC_TOP0, 8, 1, "sclk_vpll"),
394 MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
395 MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
396 MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
397 MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
398 MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
399 MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
400 MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
401 MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
402 MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
403 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
404 CLK_SET_RATE_PARENT, 0),
405 MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
406 MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
407 MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
408 MUX(none, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
409 MUX(none, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
410 MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
411 MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
412 MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
413 MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
414 MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
415 MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
416 MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
417 MUX(none, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
418 MUX(none, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
419 MUX(none, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
420 MUX(none, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
421 MUX(none, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
422 MUX(none, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
423 MUX(none, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
424};
425
426/* list of mux clocks supported in exynos4x12 soc */
427struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
428 MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
429 SRC_CPU, 24, 1),
430 MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
431 MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
432 MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12,
433 SRC_TOP1, 12, 1),
434 MUX(none, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
435 SRC_TOP1, 16, 1),
436 MUX(aclk200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
437 MUX(aclk400_mcuisp, "aclk400_mcuisp", mout_user_aclk400_mcuisp_p4x12,
438 SRC_TOP1, 24, 1),
439 MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
440 MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
441 MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
442 MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
443 MUX(none, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
444 MUX(none, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
445 MUX(none, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
446 MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
447 MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
448 MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
449 MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p,
450 SRC_DMC, 12, 1, "sclk_mpll"),
451 MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,
452 SRC_TOP0, 8, 1, "sclk_vpll"),
453 MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
454 MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
455 MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
456 MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
457 MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
458 MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
459 MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
460 MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
461 MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
462 MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
463 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
464 CLK_SET_RATE_PARENT, 0),
465 MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
466 MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
467 MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
468 MUX(none, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
469 MUX(none, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
470 MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
471 MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
472 MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
473 MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
474 MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
475 MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
476 MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
477 MUX(none, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
478 MUX(none, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
479 MUX(none, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
480 MUX(none, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
481 MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
482 MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
483 MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
484 MUX(none, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
485 MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
486 MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
487 MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
488};
489
490/* list of divider clocks supported in all exynos4 soc's */
491struct samsung_div_clock exynos4_div_clks[] __initdata = {
492 DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3),
493 DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3),
494 DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
495 DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
496 DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
497 DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
498 DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
499 DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
500 DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
501 DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
502 DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
503 DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
504 CLK_SET_RATE_PARENT, 0),
505 DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
506 DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
507 DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
508 DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
509 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
510 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
511 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
512 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
513 DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
514 DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
515 DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
516 DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
517 DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
518 DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
519 DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
520 DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
521 DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
522 DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
523 DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
524 DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),
525 DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
526 DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
527 DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
528 DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
529 DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
530 DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
531 DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
532 DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
533 DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
534 DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
535 DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
536 DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
537 DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
538 DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "arm_clk"),
539 DIV_A(sclk_apll, "sclk_apll", "mout_apll",
540 DIV_CPU0, 24, 3, "sclk_apll"),
541 DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
542 CLK_SET_RATE_PARENT, 0),
543 DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
544 CLK_SET_RATE_PARENT, 0),
545 DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
546 CLK_SET_RATE_PARENT, 0),
547 DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
548 CLK_SET_RATE_PARENT, 0),
549 DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
550 CLK_SET_RATE_PARENT, 0),
551};
552
553/* list of divider clocks supported in exynos4210 soc */
554struct samsung_div_clock exynos4210_div_clks[] __initdata = {
555 DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
556 DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
557 DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
558 DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
559 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
560 DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
561 CLK_SET_RATE_PARENT, 0),
562};
563
564/* list of divider clocks supported in exynos4x12 soc */
565struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
566 DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
567 DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
568 DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
569 DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
570 DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
571 DIV(div_aclk200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
572 DIV(none, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
573 DIV(div_aclk400_mcuisp, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
574 DIV_TOP, 24, 3),
575 DIV(none, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
576 DIV(none, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
577 DIV(none, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
578 DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
579 DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
580 DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
581 DIV(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
582 DIV(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
583 DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
584 DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
585 DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
586};
587
588/* list of gate clocks supported in all exynos4 soc's */
589struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
590 /*
591 * After all Exynos4 based platforms are migrated to use device tree,
592 * the device name and clock alias names specified below for some
593 * of the clocks can be removed.
594 */
595 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
596 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 0),
597 GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
598 GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
599 GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
600 GATE(fimd1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
601 GATE(mie1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
602 GATE(dsim1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
603 GATE(smmu_fimd1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 0),
604 GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
605 GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
606 GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
607 CLK_SET_RATE_PARENT, 0),
608 GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
609 GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
610 GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
611 GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
612 GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
613 GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
614 GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
615 CLK_SET_RATE_PARENT, 0),
616 GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
617 CLK_SET_RATE_PARENT, 0),
618 GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0",
619 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
620 GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
621 CLK_SET_RATE_PARENT, 0),
622 GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
623 CLK_SET_RATE_PARENT, 0),
624 GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
625 GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
626 GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
627 GATE_A(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"),
628 GATE_A(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"),
629 GATE_A(usb_host, "usb_host", "aclk133",
630 GATE_IP_FSYS, 12, 0, 0, "usbhost"),
631 GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0",
632 SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
633 GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1",
634 SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
635 GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2",
636 SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
637 GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3",
638 SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
639 GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0",
640 SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
641 GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1",
642 SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
643 GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0",
644 SRC_MASK_LCD0, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
645 GATE_DA(sclk_mmc0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc_pre0",
646 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0,
647 "mmc_busclk.2"),
648 GATE_DA(sclk_mmc1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc_pre1",
649 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0,
650 "mmc_busclk.2"),
651 GATE_DA(sclk_mmc2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc_pre2",
652 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0,
653 "mmc_busclk.2"),
654 GATE_DA(sclk_mmc3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc_pre3",
655 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0,
656 "mmc_busclk.2"),
657 GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4",
658 SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"),
659 GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0",
660 SRC_MASK_PERIL0, 0, CLK_SET_RATE_PARENT,
661 0, "clk_uart_baud0"),
662 GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1",
663 SRC_MASK_PERIL0, 4, CLK_SET_RATE_PARENT,
664 0, "clk_uart_baud0"),
665 GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2",
666 SRC_MASK_PERIL0, 8, CLK_SET_RATE_PARENT,
667 0, "clk_uart_baud0"),
668 GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3",
669 SRC_MASK_PERIL0, 12, CLK_SET_RATE_PARENT,
670 0, "clk_uart_baud0"),
671 GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4",
672 SRC_MASK_PERIL0, 16, CLK_SET_RATE_PARENT,
673 0, "clk_uart_baud0"),
674 GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
675 CLK_SET_RATE_PARENT, 0),
676 GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0",
677 SRC_MASK_PERIL1, 16, CLK_SET_RATE_PARENT,
678 0, "spi_busclk0"),
679 GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1",
680 SRC_MASK_PERIL1, 20, CLK_SET_RATE_PARENT,
681 0, "spi_busclk0"),
682 GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2",
683 SRC_MASK_PERIL1, 24, CLK_SET_RATE_PARENT,
684 0, "spi_busclk0"),
685 GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160",
686 GATE_IP_CAM, 0, 0, 0, "fimc"),
687 GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160",
688 GATE_IP_CAM, 1, 0, 0, "fimc"),
689 GATE_DA(fimc2, "exynos4-fimc.2", "fimc2", "aclk160",
690 GATE_IP_CAM, 2, 0, 0, "fimc"),
691 GATE_DA(fimc3, "exynos4-fimc.3", "fimc3", "aclk160",
692 GATE_IP_CAM, 3, 0, 0, "fimc"),
693 GATE_DA(csis0, "s5p-mipi-csis.0", "csis0", "aclk160",
694 GATE_IP_CAM, 4, 0, 0, "fimc"),
695 GATE_DA(csis1, "s5p-mipi-csis.1", "csis1", "aclk160",
696 GATE_IP_CAM, 5, 0, 0, "fimc"),
697 GATE_DA(smmu_fimc0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160",
698 GATE_IP_CAM, 7, 0, 0, "sysmmu"),
699 GATE_DA(smmu_fimc1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160",
700 GATE_IP_CAM, 8, 0, 0, "sysmmu"),
701 GATE_DA(smmu_fimc2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160",
702 GATE_IP_CAM, 9, 0, 0, "sysmmu"),
703 GATE_DA(smmu_fimc3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160",
704 GATE_IP_CAM, 10, 0, 0, "sysmmu"),
705 GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160",
706 GATE_IP_CAM, 11, 0, 0, "sysmmu"),
707 GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
708 GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
709 GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160",
710 GATE_IP_TV, 4, 0, 0, "sysmmu"),
711 GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"),
712 GATE_DA(smmu_mfcl, "exynos-sysmmu.0", "smmu_mfcl", "aclk100",
713 GATE_IP_MFC, 1, 0, 0, "sysmmu"),
714 GATE_DA(smmu_mfcr, "exynos-sysmmu.1", "smmu_mfcr", "aclk100",
715 GATE_IP_MFC, 2, 0, 0, "sysmmu"),
716 GATE_DA(fimd0, "exynos4-fb.0", "fimd0", "aclk160",
717 GATE_IP_LCD0, 0, 0, 0, "fimd"),
718 GATE_DA(smmu_fimd0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160",
719 GATE_IP_LCD0, 4, 0, 0, "sysmmu"),
720 GATE_DA(pdma0, "dma-pl330.0", "pdma0", "aclk133",
721 GATE_IP_FSYS, 0, 0, 0, "dma"),
722 GATE_DA(pdma1, "dma-pl330.1", "pdma1", "aclk133",
723 GATE_IP_FSYS, 1, 0, 0, "dma"),
724 GATE_DA(sdmmc0, "exynos4-sdhci.0", "sdmmc0", "aclk133",
725 GATE_IP_FSYS, 5, 0, 0, "hsmmc"),
726 GATE_DA(sdmmc1, "exynos4-sdhci.1", "sdmmc1", "aclk133",
727 GATE_IP_FSYS, 6, 0, 0, "hsmmc"),
728 GATE_DA(sdmmc2, "exynos4-sdhci.2", "sdmmc2", "aclk133",
729 GATE_IP_FSYS, 7, 0, 0, "hsmmc"),
730 GATE_DA(sdmmc3, "exynos4-sdhci.3", "sdmmc3", "aclk133",
731 GATE_IP_FSYS, 8, 0, 0, "hsmmc"),
732 GATE_DA(uart0, "exynos4210-uart.0", "uart0", "aclk100",
733 GATE_IP_PERIL, 0, 0, 0, "uart"),
734 GATE_DA(uart1, "exynos4210-uart.1", "uart1", "aclk100",
735 GATE_IP_PERIL, 1, 0, 0, "uart"),
736 GATE_DA(uart2, "exynos4210-uart.2", "uart2", "aclk100",
737 GATE_IP_PERIL, 2, 0, 0, "uart"),
738 GATE_DA(uart3, "exynos4210-uart.3", "uart3", "aclk100",
739 GATE_IP_PERIL, 3, 0, 0, "uart"),
740 GATE_DA(uart4, "exynos4210-uart.4", "uart4", "aclk100",
741 GATE_IP_PERIL, 4, 0, 0, "uart"),
742 GATE_DA(i2c0, "s3c2440-i2c.0", "i2c0", "aclk100",
743 GATE_IP_PERIL, 6, 0, 0, "i2c"),
744 GATE_DA(i2c1, "s3c2440-i2c.1", "i2c1", "aclk100",
745 GATE_IP_PERIL, 7, 0, 0, "i2c"),
746 GATE_DA(i2c2, "s3c2440-i2c.2", "i2c2", "aclk100",
747 GATE_IP_PERIL, 8, 0, 0, "i2c"),
748 GATE_DA(i2c3, "s3c2440-i2c.3", "i2c3", "aclk100",
749 GATE_IP_PERIL, 9, 0, 0, "i2c"),
750 GATE_DA(i2c4, "s3c2440-i2c.4", "i2c4", "aclk100",
751 GATE_IP_PERIL, 10, 0, 0, "i2c"),
752 GATE_DA(i2c5, "s3c2440-i2c.5", "i2c5", "aclk100",
753 GATE_IP_PERIL, 11, 0, 0, "i2c"),
754 GATE_DA(i2c6, "s3c2440-i2c.6", "i2c6", "aclk100",
755 GATE_IP_PERIL, 12, 0, 0, "i2c"),
756 GATE_DA(i2c7, "s3c2440-i2c.7", "i2c7", "aclk100",
757 GATE_IP_PERIL, 13, 0, 0, "i2c"),
758 GATE_DA(i2c_hdmi, "s3c2440-hdmiphy-i2c", "i2c-hdmi", "aclk100",
759 GATE_IP_PERIL, 14, 0, 0, "i2c"),
760 GATE_DA(spi0, "exynos4210-spi.0", "spi0", "aclk100",
761 GATE_IP_PERIL, 16, 0, 0, "spi"),
762 GATE_DA(spi1, "exynos4210-spi.1", "spi1", "aclk100",
763 GATE_IP_PERIL, 17, 0, 0, "spi"),
764 GATE_DA(spi2, "exynos4210-spi.2", "spi2", "aclk100",
765 GATE_IP_PERIL, 18, 0, 0, "spi"),
766 GATE_DA(i2s1, "samsung-i2s.1", "i2s1", "aclk100",
767 GATE_IP_PERIL, 20, 0, 0, "iis"),
768 GATE_DA(i2s2, "samsung-i2s.2", "i2s2", "aclk100",
769 GATE_IP_PERIL, 21, 0, 0, "iis"),
770 GATE_DA(pcm1, "samsung-pcm.1", "pcm1", "aclk100",
771 GATE_IP_PERIL, 22, 0, 0, "pcm"),
772 GATE_DA(pcm2, "samsung-pcm.2", "pcm2", "aclk100",
773 GATE_IP_PERIL, 23, 0, 0, "pcm"),
774 GATE_DA(spdif, "samsung-spdif", "spdif", "aclk100",
775 GATE_IP_PERIL, 26, 0, 0, "spdif"),
776 GATE_DA(ac97, "samsung-ac97", "ac97", "aclk100",
777 GATE_IP_PERIL, 27, 0, 0, "ac97"),
778};
779
780/* list of gate clocks supported in exynos4210 soc */
781struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
782 GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
783 GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
784 GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
785 GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
786 GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
787 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0),
788 GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
789 GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
790 GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
791 GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
792 GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
793 GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
794 GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
795 GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
796 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0),
797 GATE(smmu_rotator, "smmu_rotator", "aclk200",
798 E4210_GATE_IP_IMAGE, 4, 0, 0),
799 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1",
800 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
801 GATE(sclk_sata, "sclk_sata", "div_sata",
802 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
803 GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
804 GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
805 GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"),
806 GATE_A(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 0, 0, "mct"),
807 GATE_A(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
808 GATE_A(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 0, 0, "rtc"),
809 GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"),
810 GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1",
811 E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
812};
813
814/* list of gate clocks supported in exynos4x12 soc */
815struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
816 GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
817 GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
818 GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
819 GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
820 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),
821 GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
822 GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
823 GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0),
824 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),
825 GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",
826 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
827 GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
828 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
829 GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi",
830 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
831 GATE(smmu_rotator, "smmu_rotator", "aclk200",
832 E4X12_GATE_IP_IMAGE, 4, 0, 0),
833 GATE_A(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 0, 0, "mct"),
834 GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"),
835 GATE_A(keyif, "keyif", "aclk100",
836 E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"),
837 GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp",
838 E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),
839 GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre",
840 E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0),
841 GATE(sclk_spi1_isp, "sclk_spi1_isp", "div_spi1_isp_pre",
842 E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0),
843 GATE(sclk_uart_isp, "sclk_uart_isp", "div_uart_isp",
844 E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0),
845 GATE(pwm_isp_sclk, "pwm_isp_sclk", "sclk_pwm_isp",
846 E4X12_GATE_IP_ISP, 0, 0, 0),
847 GATE(spi0_isp_sclk, "spi0_isp_sclk", "sclk_spi0_isp",
848 E4X12_GATE_IP_ISP, 1, 0, 0),
849 GATE(spi1_isp_sclk, "spi1_isp_sclk", "sclk_spi1_isp",
850 E4X12_GATE_IP_ISP, 2, 0, 0),
851 GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp",
852 E4X12_GATE_IP_ISP, 3, 0, 0),
853 GATE_A(wdt, "watchdog", "aclk100",
854 E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
855 GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100",
856 E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"),
857 GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",
858 E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
859 GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0,
860 CLK_IGNORE_UNUSED, 0),
861 GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1,
862 CLK_IGNORE_UNUSED, 0),
863 GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2,
864 CLK_IGNORE_UNUSED, 0),
865 GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
866 CLK_IGNORE_UNUSED, 0),
867 GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
868 CLK_IGNORE_UNUSED, 0),
869 GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
870 CLK_IGNORE_UNUSED, 0),
871 GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
872 CLK_IGNORE_UNUSED, 0),
873 GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
874 CLK_IGNORE_UNUSED, 0),
875 GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
876 CLK_IGNORE_UNUSED, 0),
877 GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
878 CLK_IGNORE_UNUSED, 0),
879 GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
880 CLK_IGNORE_UNUSED, 0),
881 GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
882 CLK_IGNORE_UNUSED, 0),
883 GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
884 CLK_IGNORE_UNUSED, 0),
885 GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
886 CLK_IGNORE_UNUSED, 0),
887 GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
888 CLK_IGNORE_UNUSED, 0),
889 GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
890 CLK_IGNORE_UNUSED, 0),
891 GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
892 CLK_IGNORE_UNUSED, 0),
893 GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
894 CLK_IGNORE_UNUSED, 0),
895 GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
896 CLK_IGNORE_UNUSED, 0),
897 GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
898 CLK_IGNORE_UNUSED, 0),
899 GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
900 CLK_IGNORE_UNUSED, 0),
901 GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
902 CLK_IGNORE_UNUSED, 0),
903 GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
904 CLK_IGNORE_UNUSED, 0),
905 GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
906 CLK_IGNORE_UNUSED, 0),
907 GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
908 CLK_IGNORE_UNUSED, 0),
909 GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
910 CLK_IGNORE_UNUSED, 0),
911};
912
913#ifdef CONFIG_OF
914static struct of_device_id exynos4_clk_ids[] __initdata = {
915 { .compatible = "samsung,exynos4210-clock",
916 .data = (void *)EXYNOS4210, },
917 { .compatible = "samsung,exynos4412-clock",
918 .data = (void *)EXYNOS4X12, },
919 { },
920};
921#endif
922
923/*
924 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
925 * resides in chipid register space, outside of the clock controller memory
926 * mapped space. So to determine the parent of fin_pll clock, the chipid
927 * controller is first remapped and the value of XOM[0] bit is read to
928 * determine the parent clock.
929 */
930static void __init exynos4_clk_register_finpll(void)
931{
932 struct samsung_fixed_rate_clock fclk;
933 struct device_node *np;
934 struct clk *clk;
935 void __iomem *chipid_base = S5P_VA_CHIPID;
936 unsigned long xom, finpll_f = 24000000;
937 char *parent_name;
938
939 np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
940 if (np)
941 chipid_base = of_iomap(np, 0);
942
943 if (chipid_base) {
944 xom = readl(chipid_base + 8);
945 parent_name = xom & 1 ? "xusbxti" : "xxti";
946 clk = clk_get(NULL, parent_name);
947 if (IS_ERR(clk)) {
948 pr_err("%s: failed to lookup parent clock %s, assuming "
949 "fin_pll clock frequency is 24MHz\n", __func__,
950 parent_name);
951 } else {
952 finpll_f = clk_get_rate(clk);
953 }
954 } else {
955 pr_err("%s: failed to map chipid registers, assuming "
956 "fin_pll clock frequency is 24MHz\n", __func__);
957 }
958
959 fclk.id = fin_pll;
960 fclk.name = "fin_pll";
961 fclk.parent_name = NULL;
962 fclk.flags = CLK_IS_ROOT;
963 fclk.fixed_rate = finpll_f;
964 samsung_clk_register_fixed_rate(&fclk, 1);
965
966 if (np)
967 iounmap(chipid_base);
968}
969
970/*
971 * This function allows non-dt platforms to specify the clock speed of the
972 * xxti and xusbxti clocks. These clocks are then registered with the specified
973 * clock speed.
974 */
975void __init exynos4_clk_register_fixed_ext(unsigned long xxti_f,
976 unsigned long xusbxti_f)
977{
978 exynos4_fixed_rate_ext_clks[0].fixed_rate = xxti_f;
979 exynos4_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
980 samsung_clk_register_fixed_rate(exynos4_fixed_rate_ext_clks,
981 ARRAY_SIZE(exynos4_fixed_rate_ext_clks));
982}
983
984static __initdata struct of_device_id ext_clk_match[] = {
985 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
986 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
987 {},
988};
989
990/* register exynos4 clocks */
991void __init exynos4_clk_init(struct device_node *np)
992{
993 void __iomem *reg_base;
994 struct clk *apll, *mpll, *epll, *vpll;
995 u32 exynos4_soc;
996
997 if (np) {
998 const struct of_device_id *match;
999 match = of_match_node(exynos4_clk_ids, np);
1000 exynos4_soc = (u32)match->data;
1001
1002 reg_base = of_iomap(np, 0);
1003 if (!reg_base)
1004 panic("%s: failed to map registers\n", __func__);
1005 } else {
1006 reg_base = S5P_VA_CMU;
1007 if (soc_is_exynos4210())
1008 exynos4_soc = EXYNOS4210;
1009 else if (soc_is_exynos4212() || soc_is_exynos4412())
1010 exynos4_soc = EXYNOS4X12;
1011 else
1012 panic("%s: unable to determine soc\n", __func__);
1013 }
1014
1015 if (exynos4_soc == EXYNOS4210)
1016 samsung_clk_init(np, reg_base, nr_clks,
1017 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1018 exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save));
1019 else
1020 samsung_clk_init(np, reg_base, nr_clks,
1021 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1022 exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
1023
1024 if (np)
1025 samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
1026 ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
1027 ext_clk_match);
1028
1029 exynos4_clk_register_finpll();
1030
1031 if (exynos4_soc == EXYNOS4210) {
1032 apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll",
1033 reg_base + APLL_CON0, pll_4508);
1034 mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll",
1035 reg_base + E4210_MPLL_CON0, pll_4508);
1036 epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll",
1037 reg_base + EPLL_CON0, pll_4600);
1038 vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc",
1039 reg_base + VPLL_CON0, pll_4650c);
1040 } else {
1041 apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
1042 reg_base + APLL_CON0);
1043 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
1044 reg_base + E4X12_MPLL_CON0);
1045 epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
1046 reg_base + EPLL_CON0);
1047 vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
1048 reg_base + VPLL_CON0);
1049 }
1050
1051 samsung_clk_add_lookup(apll, fout_apll);
1052 samsung_clk_add_lookup(mpll, fout_mpll);
1053 samsung_clk_add_lookup(epll, fout_epll);
1054 samsung_clk_add_lookup(vpll, fout_vpll);
1055
1056 samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
1057 ARRAY_SIZE(exynos4_fixed_rate_clks));
1058 samsung_clk_register_mux(exynos4_mux_clks,
1059 ARRAY_SIZE(exynos4_mux_clks));
1060 samsung_clk_register_div(exynos4_div_clks,
1061 ARRAY_SIZE(exynos4_div_clks));
1062 samsung_clk_register_gate(exynos4_gate_clks,
1063 ARRAY_SIZE(exynos4_gate_clks));
1064
1065 if (exynos4_soc == EXYNOS4210) {
1066 samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks,
1067 ARRAY_SIZE(exynos4210_fixed_rate_clks));
1068 samsung_clk_register_mux(exynos4210_mux_clks,
1069 ARRAY_SIZE(exynos4210_mux_clks));
1070 samsung_clk_register_div(exynos4210_div_clks,
1071 ARRAY_SIZE(exynos4210_div_clks));
1072 samsung_clk_register_gate(exynos4210_gate_clks,
1073 ARRAY_SIZE(exynos4210_gate_clks));
1074 } else {
1075 samsung_clk_register_mux(exynos4x12_mux_clks,
1076 ARRAY_SIZE(exynos4x12_mux_clks));
1077 samsung_clk_register_div(exynos4x12_div_clks,
1078 ARRAY_SIZE(exynos4x12_div_clks));
1079 samsung_clk_register_gate(exynos4x12_gate_clks,
1080 ARRAY_SIZE(exynos4x12_gate_clks));
1081 }
1082
1083 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
1084 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
1085 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
1086 _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
1087 _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
1088 _get_rate("arm_clk"));
1089}
1090CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4_clk_init);
1091CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
new file mode 100644
index 000000000000..7290faa518d2
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -0,0 +1,523 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for Exynos5250 SoC.
11*/
12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#include <plat/cpu.h>
20#include "clk.h"
21#include "clk-pll.h"
22
23#define SRC_CPU 0x200
24#define DIV_CPU0 0x500
25#define SRC_CORE1 0x4204
26#define SRC_TOP0 0x10210
27#define SRC_TOP2 0x10218
28#define SRC_GSCL 0x10220
29#define SRC_DISP1_0 0x1022c
30#define SRC_MAU 0x10240
31#define SRC_FSYS 0x10244
32#define SRC_GEN 0x10248
33#define SRC_PERIC0 0x10250
34#define SRC_PERIC1 0x10254
35#define SRC_MASK_GSCL 0x10320
36#define SRC_MASK_DISP1_0 0x1032c
37#define SRC_MASK_MAU 0x10334
38#define SRC_MASK_FSYS 0x10340
39#define SRC_MASK_GEN 0x10344
40#define SRC_MASK_PERIC0 0x10350
41#define SRC_MASK_PERIC1 0x10354
42#define DIV_TOP0 0x10510
43#define DIV_TOP1 0x10514
44#define DIV_GSCL 0x10520
45#define DIV_DISP1_0 0x1052c
46#define DIV_GEN 0x1053c
47#define DIV_MAU 0x10544
48#define DIV_FSYS0 0x10548
49#define DIV_FSYS1 0x1054c
50#define DIV_FSYS2 0x10550
51#define DIV_PERIC0 0x10558
52#define DIV_PERIC1 0x1055c
53#define DIV_PERIC2 0x10560
54#define DIV_PERIC3 0x10564
55#define DIV_PERIC4 0x10568
56#define DIV_PERIC5 0x1056c
57#define GATE_IP_GSCL 0x10920
58#define GATE_IP_MFC 0x1092c
59#define GATE_IP_GEN 0x10934
60#define GATE_IP_FSYS 0x10944
61#define GATE_IP_PERIC 0x10950
62#define GATE_IP_PERIS 0x10960
63#define SRC_CDREX 0x20200
64#define PLL_DIV2_SEL 0x20a24
65#define GATE_IP_DISP1 0x10928
66
67/*
68 * Let each supported clock get a unique id. This id is used to lookup the clock
69 * for device tree based platforms. The clocks are categorized into three
70 * sections: core, sclk gate and bus interface gate clocks.
71 *
72 * When adding a new clock to this list, it is advised to choose a clock
73 * category and add it to the end of that category. That is because the the
74 * device tree source file is referring to these ids and any change in the
75 * sequence number of existing clocks will require corresponding change in the
76 * device tree files. This limitation would go away when pre-processor support
77 * for dtc would be available.
78 */
79enum exynos5250_clks {
80 none,
81
82 /* core clocks */
83 fin_pll,
84
85 /* gate for special clocks (sclk) */
86 sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
87 sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0,
88 sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
89 sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
90 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
91
92 /* gate clocks */
93 gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
94 smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator,
95 jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata,
96 usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3,
97 sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0,
98 i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1,
99 spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
100 hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
101 tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
102 wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
103
104 nr_clks,
105};
106
107/*
108 * list of controller registers to be saved and restored during a
109 * suspend/resume cycle.
110 */
111static __initdata unsigned long exynos5250_clk_regs[] = {
112 SRC_CPU,
113 DIV_CPU0,
114 SRC_CORE1,
115 SRC_TOP0,
116 SRC_TOP2,
117 SRC_GSCL,
118 SRC_DISP1_0,
119 SRC_MAU,
120 SRC_FSYS,
121 SRC_GEN,
122 SRC_PERIC0,
123 SRC_PERIC1,
124 SRC_MASK_GSCL,
125 SRC_MASK_DISP1_0,
126 SRC_MASK_MAU,
127 SRC_MASK_FSYS,
128 SRC_MASK_GEN,
129 SRC_MASK_PERIC0,
130 SRC_MASK_PERIC1,
131 DIV_TOP0,
132 DIV_TOP1,
133 DIV_GSCL,
134 DIV_DISP1_0,
135 DIV_GEN,
136 DIV_MAU,
137 DIV_FSYS0,
138 DIV_FSYS1,
139 DIV_FSYS2,
140 DIV_PERIC0,
141 DIV_PERIC1,
142 DIV_PERIC2,
143 DIV_PERIC3,
144 DIV_PERIC4,
145 DIV_PERIC5,
146 GATE_IP_GSCL,
147 GATE_IP_MFC,
148 GATE_IP_GEN,
149 GATE_IP_FSYS,
150 GATE_IP_PERIC,
151 GATE_IP_PERIS,
152 SRC_CDREX,
153 PLL_DIV2_SEL,
154 GATE_IP_DISP1,
155};
156
157/* list of all parent clock list */
158PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
159PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
160PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
161PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
162PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
163PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
164PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
165PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
166PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
167PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
168PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll" };
169PNAME(mout_bpll_user_p) = { "fin_pll", "sclk_bpll" };
170PNAME(mout_aclk166_p) = { "sclk_cpll", "sclk_mpll_user" };
171PNAME(mout_aclk200_p) = { "sclk_mpll_user", "sclk_bpll_user" };
172PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
173PNAME(mout_usb3_p) = { "sclk_mpll_user", "sclk_cpll" };
174PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
175 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
176 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
177 "sclk_cpll" };
178PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
179 "sclk_uhostphy", "sclk_hdmiphy",
180 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
181 "sclk_cpll" };
182PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
183 "sclk_uhostphy", "sclk_hdmiphy",
184 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
185 "sclk_cpll" };
186PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
187 "sclk_uhostphy", "sclk_hdmiphy",
188 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
189 "sclk_cpll" };
190PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
191 "spdif_extclk" };
192
193/* fixed rate clocks generated outside the soc */
194struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
195 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
196};
197
198/* fixed rate clocks generated inside the soc */
199struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
200 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
201 FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
202 FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
203 FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
204};
205
206struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
207 FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
208 FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
209};
210
211struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
212 MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
213 MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
214 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
215 MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
216 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
217 MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
218 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
219 MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
220 MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1),
221 MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
222 MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
223 MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
224 MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
225 MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
226 MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
227 MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
228 MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
229 MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
230 MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
231 MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
232 MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
233 MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
234 MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
235 MUX(none, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
236 MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
237 MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
238 MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
239 MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
240 MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
241 MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
242 MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
243 MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
244 MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
245 MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
246 MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
247 MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
248 MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
249 MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
250 MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
251 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
252 MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
253 MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
254 MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
255};
256
257struct samsung_div_clock exynos5250_div_clks[] __initdata = {
258 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
259 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
260 DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3),
261 DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
262 DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3),
263 DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
264 DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
265 DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
266 DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
267 DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
268 DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
269 DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
270 DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
271 DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
272 DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
273 DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
274 DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
275 DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
276 DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
277 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
278 DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
279 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 8, 8),
280 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 24, 8),
281 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 8, 8),
282 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 24, 8),
283 DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
284 DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
285 DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
286 DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
287 DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
288 DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
289 DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
290 DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
291 DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
292 DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
293 DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
294 DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
295 DIV(none, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
296 DIV(none, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
297 DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
298 DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
299 DIV_F(none, "div_mipi1_pre", "div_mipi1",
300 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
301 DIV_F(none, "div_mmc_pre0", "div_mmc0",
302 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
303 DIV_F(none, "div_mmc_pre1", "div_mmc1",
304 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
305 DIV_F(none, "div_mmc_pre2", "div_mmc2",
306 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
307 DIV_F(none, "div_mmc_pre3", "div_mmc3",
308 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
309 DIV_F(none, "div_spi_pre0", "div_spi0",
310 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
311 DIV_F(none, "div_spi_pre1", "div_spi1",
312 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
313 DIV_F(none, "div_spi_pre2", "div_spi2",
314 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
315};
316
317struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
318 GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0),
319 GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0),
320 GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0),
321 GATE(gscl3, "gscl3", "aclk266", GATE_IP_GSCL, 3, 0, 0),
322 GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
323 GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
324 GATE(smmu_gscl0, "smmu_gscl0", "aclk266", GATE_IP_GSCL, 7, 0, 0),
325 GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0),
326 GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
327 GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
328 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
329 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
330 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
331 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
332 GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0),
333 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
334 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
335 GATE(smmu_jpeg, "smmu_jpeg", "aclk166", GATE_IP_GEN, 7, 0, 0),
336 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
337 GATE(pdma0, "pdma0", "aclk200", GATE_IP_FSYS, 1, 0, 0),
338 GATE(pdma1, "pdma1", "aclk200", GATE_IP_FSYS, 2, 0, 0),
339 GATE(sata, "sata", "aclk200", GATE_IP_FSYS, 6, 0, 0),
340 GATE(usbotg, "usbotg", "aclk200", GATE_IP_FSYS, 7, 0, 0),
341 GATE(mipi_hsi, "mipi_hsi", "aclk200", GATE_IP_FSYS, 8, 0, 0),
342 GATE(sdmmc0, "sdmmc0", "aclk200", GATE_IP_FSYS, 12, 0, 0),
343 GATE(sdmmc1, "sdmmc1", "aclk200", GATE_IP_FSYS, 13, 0, 0),
344 GATE(sdmmc2, "sdmmc2", "aclk200", GATE_IP_FSYS, 14, 0, 0),
345 GATE(sdmmc3, "sdmmc3", "aclk200", GATE_IP_FSYS, 15, 0, 0),
346 GATE(sromc, "sromc", "aclk200", GATE_IP_FSYS, 17, 0, 0),
347 GATE(usb2, "usb2", "aclk200", GATE_IP_FSYS, 18, 0, 0),
348 GATE(usb3, "usb3", "aclk200", GATE_IP_FSYS, 19, 0, 0),
349 GATE(sata_phyctrl, "sata_phyctrl", "aclk200", GATE_IP_FSYS, 24, 0, 0),
350 GATE(sata_phyi2c, "sata_phyi2c", "aclk200", GATE_IP_FSYS, 25, 0, 0),
351 GATE(uart0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
352 GATE(uart1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
353 GATE(uart2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
354 GATE(uart3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
355 GATE(uart4, "uart4", "aclk66", GATE_IP_PERIC, 4, 0, 0),
356 GATE(i2c0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
357 GATE(i2c1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
358 GATE(i2c2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
359 GATE(i2c3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
360 GATE(i2c4, "i2c4", "aclk66", GATE_IP_PERIC, 10, 0, 0),
361 GATE(i2c5, "i2c5", "aclk66", GATE_IP_PERIC, 11, 0, 0),
362 GATE(i2c6, "i2c6", "aclk66", GATE_IP_PERIC, 12, 0, 0),
363 GATE(i2c7, "i2c7", "aclk66", GATE_IP_PERIC, 13, 0, 0),
364 GATE(i2c_hdmi, "i2c_hdmi", "aclk66", GATE_IP_PERIC, 14, 0, 0),
365 GATE(adc, "adc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
366 GATE(spi0, "spi0", "aclk66", GATE_IP_PERIC, 16, 0, 0),
367 GATE(spi1, "spi1", "aclk66", GATE_IP_PERIC, 17, 0, 0),
368 GATE(spi2, "spi2", "aclk66", GATE_IP_PERIC, 18, 0, 0),
369 GATE(i2s1, "i2s1", "aclk66", GATE_IP_PERIC, 20, 0, 0),
370 GATE(i2s2, "i2s2", "aclk66", GATE_IP_PERIC, 21, 0, 0),
371 GATE(pcm1, "pcm1", "aclk66", GATE_IP_PERIC, 22, 0, 0),
372 GATE(pcm2, "pcm2", "aclk66", GATE_IP_PERIC, 23, 0, 0),
373 GATE(pwm, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
374 GATE(spdif, "spdif", "aclk66", GATE_IP_PERIC, 26, 0, 0),
375 GATE(ac97, "ac97", "aclk66", GATE_IP_PERIC, 27, 0, 0),
376 GATE(hsi2c0, "hsi2c0", "aclk66", GATE_IP_PERIC, 28, 0, 0),
377 GATE(hsi2c1, "hsi2c1", "aclk66", GATE_IP_PERIC, 29, 0, 0),
378 GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
379 GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
380 GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
381 GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
382 GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, 0, 0),
383 GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
384 GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
385 GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0),
386 GATE(tzpc3, "tzpc3", "aclk66", GATE_IP_PERIS, 9, 0, 0),
387 GATE(tzpc4, "tzpc4", "aclk66", GATE_IP_PERIS, 10, 0, 0),
388 GATE(tzpc5, "tzpc5", "aclk66", GATE_IP_PERIS, 11, 0, 0),
389 GATE(tzpc6, "tzpc6", "aclk66", GATE_IP_PERIS, 12, 0, 0),
390 GATE(tzpc7, "tzpc7", "aclk66", GATE_IP_PERIS, 13, 0, 0),
391 GATE(tzpc8, "tzpc8", "aclk66", GATE_IP_PERIS, 14, 0, 0),
392 GATE(tzpc9, "tzpc9", "aclk66", GATE_IP_PERIS, 15, 0, 0),
393 GATE(hdmi_cec, "hdmi_cec", "aclk66", GATE_IP_PERIS, 16, 0, 0),
394 GATE(mct, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
395 GATE(wdt, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
396 GATE(rtc, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
397 GATE(tmu, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
398 GATE(cmu_top, "cmu_top", "aclk66",
399 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
400 GATE(cmu_core, "cmu_core", "aclk66",
401 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
402 GATE(cmu_mem, "cmu_mem", "aclk66",
403 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
404 GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer",
405 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
406 GATE(sclk_cam0, "sclk_cam0", "div_cam0",
407 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
408 GATE(sclk_cam1, "sclk_cam1", "div_cam1",
409 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
410 GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa",
411 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
412 GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb",
413 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
414 GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1",
415 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
416 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1",
417 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
418 GATE(sclk_dp, "sclk_dp", "div_dp",
419 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
420 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
421 SRC_MASK_DISP1_0, 20, 0, 0),
422 GATE(sclk_audio0, "sclk_audio0", "div_audio0",
423 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
424 GATE(sclk_mmc0, "sclk_mmc0", "div_mmc0",
425 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
426 GATE(sclk_mmc1, "sclk_mmc1", "div_mmc1",
427 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
428 GATE(sclk_mmc2, "sclk_mmc2", "div_mmc2",
429 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
430 GATE(sclk_mmc3, "sclk_mmc3", "div_mmc3",
431 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
432 GATE(sclk_sata, "sclk_sata", "div_sata",
433 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
434 GATE(sclk_usb3, "sclk_usb3", "div_usb3",
435 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
436 GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg",
437 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
438 GATE(sclk_uart0, "sclk_uart0", "div_uart0",
439 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
440 GATE(sclk_uart1, "sclk_uart1", "div_uart1",
441 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
442 GATE(sclk_uart2, "sclk_uart2", "div_uart2",
443 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
444 GATE(sclk_uart3, "sclk_uart3", "div_uart3",
445 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
446 GATE(sclk_pwm, "sclk_pwm", "div_pwm",
447 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
448 GATE(sclk_audio1, "sclk_audio1", "div_audio1",
449 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
450 GATE(sclk_audio2, "sclk_audio2", "div_audio2",
451 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
452 GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
453 SRC_MASK_PERIC1, 4, 0, 0),
454 GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0",
455 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
456 GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1",
457 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
458 GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2",
459 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
460 GATE(fimd1, "fimd1", "aclk200", GATE_IP_DISP1, 0, 0, 0),
461 GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0),
462 GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0),
463 GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
464 GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0),
465 GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0),
466};
467
468static __initdata struct of_device_id ext_clk_match[] = {
469 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
470 { },
471};
472
473/* register exynox5250 clocks */
474void __init exynos5250_clk_init(struct device_node *np)
475{
476 void __iomem *reg_base;
477 struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
478
479 if (np) {
480 reg_base = of_iomap(np, 0);
481 if (!reg_base)
482 panic("%s: failed to map registers\n", __func__);
483 } else {
484 panic("%s: unable to determine soc\n", __func__);
485 }
486
487 samsung_clk_init(np, reg_base, nr_clks,
488 exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
489 NULL, 0);
490 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
491 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
492 ext_clk_match);
493
494 apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
495 reg_base + 0x100);
496 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
497 reg_base + 0x4100);
498 bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
499 reg_base + 0x20110);
500 gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
501 reg_base + 0x10150);
502 cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
503 reg_base + 0x10120);
504 epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
505 reg_base + 0x10130);
506 vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
507 reg_base + 0x10140);
508
509 samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
510 ARRAY_SIZE(exynos5250_fixed_rate_clks));
511 samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,
512 ARRAY_SIZE(exynos5250_fixed_factor_clks));
513 samsung_clk_register_mux(exynos5250_mux_clks,
514 ARRAY_SIZE(exynos5250_mux_clks));
515 samsung_clk_register_div(exynos5250_div_clks,
516 ARRAY_SIZE(exynos5250_div_clks));
517 samsung_clk_register_gate(exynos5250_gate_clks,
518 ARRAY_SIZE(exynos5250_gate_clks));
519
520 pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
521 _get_rate("armclk"));
522}
523CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
new file mode 100644
index 000000000000..a0a094c06f19
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -0,0 +1,139 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Author: Thomas Abraham <thomas.ab@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos5440 SoC.
10*/
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17
18#include <plat/cpu.h>
19#include "clk.h"
20#include "clk-pll.h"
21
22#define CLKEN_OV_VAL 0xf8
23#define CPU_CLK_STATUS 0xfc
24#define MISC_DOUT1 0x558
25
26/*
27 * Let each supported clock get a unique id. This id is used to lookup the clock
28 * for device tree based platforms.
29 */
30enum exynos5440_clks {
31 none, xtal, arm_clk,
32
33 spi_baud = 16, pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata,
34 usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o,
35 b_200_o, sata_o, usb_o, gmac0_o, cs250_o,
36
37 nr_clks,
38};
39
40/* parent clock name list */
41PNAME(mout_armclk_p) = { "cplla", "cpllb" };
42PNAME(mout_spi_p) = { "div125", "div200" };
43
44/* fixed rate clocks generated outside the soc */
45struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
46 FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0),
47};
48
49/* fixed rate clocks */
50struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
51 FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000),
52 FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
53 FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
54 FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000),
55 FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000),
56};
57
58/* fixed factor clocks */
59struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
60 FFACTOR(none, "div250", "ppll", 1, 4, 0),
61 FFACTOR(none, "div200", "ppll", 1, 5, 0),
62 FFACTOR(none, "div125", "div250", 1, 2, 0),
63};
64
65/* mux clocks */
66struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
67 MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
68 MUX_A(arm_clk, "arm_clk", mout_armclk_p,
69 CPU_CLK_STATUS, 0, 1, "armclk"),
70};
71
72/* divider clocks */
73struct samsung_div_clock exynos5440_div_clks[] __initdata = {
74 DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
75};
76
77/* gate clocks */
78struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
79 GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
80 GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
81 GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
82 GATE(b_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
83 GATE(b_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
84 GATE(b_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
85 GATE(sata, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
86 GATE(usb, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
87 GATE(gmac0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
88 GATE(cs250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
89 GATE(pb0_250_o, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
90 GATE(pr0_250_o, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
91 GATE(pr1_250_o, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
92 GATE(b_250_o, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
93 GATE(b_125_o, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
94 GATE(b_200_o, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
95 GATE(sata_o, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
96 GATE(usb_o, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
97 GATE(gmac0_o, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
98 GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
99};
100
101static __initdata struct of_device_id ext_clk_match[] = {
102 { .compatible = "samsung,clock-xtal", .data = (void *)0, },
103 {},
104};
105
106/* register exynos5440 clocks */
107void __init exynos5440_clk_init(struct device_node *np)
108{
109 void __iomem *reg_base;
110
111 reg_base = of_iomap(np, 0);
112 if (!reg_base) {
113 pr_err("%s: failed to map clock controller registers,"
114 " aborting clock initialization\n", __func__);
115 return;
116 }
117
118 samsung_clk_init(np, reg_base, nr_clks, NULL, 0, NULL, 0);
119 samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
120 ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
121
122 samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);
123 samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);
124
125 samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks,
126 ARRAY_SIZE(exynos5440_fixed_rate_clks));
127 samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks,
128 ARRAY_SIZE(exynos5440_fixed_factor_clks));
129 samsung_clk_register_mux(exynos5440_mux_clks,
130 ARRAY_SIZE(exynos5440_mux_clks));
131 samsung_clk_register_div(exynos5440_div_clks,
132 ARRAY_SIZE(exynos5440_div_clks));
133 samsung_clk_register_gate(exynos5440_gate_clks,
134 ARRAY_SIZE(exynos5440_gate_clks));
135
136 pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("armclk"));
137 pr_info("exynos5440 clock initialization complete\n");
138}
139CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init);
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
new file mode 100644
index 000000000000..89135f6be116
--- /dev/null
+++ b/drivers/clk/samsung/clk-pll.c
@@ -0,0 +1,419 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This file contains the utility functions to register the pll clocks.
10*/
11
12#include <linux/errno.h>
13#include "clk.h"
14#include "clk-pll.h"
15
16/*
17 * PLL35xx Clock Type
18 */
19
20#define PLL35XX_MDIV_MASK (0x3FF)
21#define PLL35XX_PDIV_MASK (0x3F)
22#define PLL35XX_SDIV_MASK (0x7)
23#define PLL35XX_MDIV_SHIFT (16)
24#define PLL35XX_PDIV_SHIFT (8)
25#define PLL35XX_SDIV_SHIFT (0)
26
27struct samsung_clk_pll35xx {
28 struct clk_hw hw;
29 const void __iomem *con_reg;
30};
31
32#define to_clk_pll35xx(_hw) container_of(_hw, struct samsung_clk_pll35xx, hw)
33
34static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
35 unsigned long parent_rate)
36{
37 struct samsung_clk_pll35xx *pll = to_clk_pll35xx(hw);
38 u32 mdiv, pdiv, sdiv, pll_con;
39 u64 fvco = parent_rate;
40
41 pll_con = __raw_readl(pll->con_reg);
42 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
43 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
44 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
45
46 fvco *= mdiv;
47 do_div(fvco, (pdiv << sdiv));
48
49 return (unsigned long)fvco;
50}
51
52static const struct clk_ops samsung_pll35xx_clk_ops = {
53 .recalc_rate = samsung_pll35xx_recalc_rate,
54};
55
56struct clk * __init samsung_clk_register_pll35xx(const char *name,
57 const char *pname, const void __iomem *con_reg)
58{
59 struct samsung_clk_pll35xx *pll;
60 struct clk *clk;
61 struct clk_init_data init;
62
63 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
64 if (!pll) {
65 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
66 return NULL;
67 }
68
69 init.name = name;
70 init.ops = &samsung_pll35xx_clk_ops;
71 init.flags = CLK_GET_RATE_NOCACHE;
72 init.parent_names = &pname;
73 init.num_parents = 1;
74
75 pll->hw.init = &init;
76 pll->con_reg = con_reg;
77
78 clk = clk_register(NULL, &pll->hw);
79 if (IS_ERR(clk)) {
80 pr_err("%s: failed to register pll clock %s\n", __func__,
81 name);
82 kfree(pll);
83 }
84
85 if (clk_register_clkdev(clk, name, NULL))
86 pr_err("%s: failed to register lookup for %s", __func__, name);
87
88 return clk;
89}
90
91/*
92 * PLL36xx Clock Type
93 */
94
95#define PLL36XX_KDIV_MASK (0xFFFF)
96#define PLL36XX_MDIV_MASK (0x1FF)
97#define PLL36XX_PDIV_MASK (0x3F)
98#define PLL36XX_SDIV_MASK (0x7)
99#define PLL36XX_MDIV_SHIFT (16)
100#define PLL36XX_PDIV_SHIFT (8)
101#define PLL36XX_SDIV_SHIFT (0)
102
103struct samsung_clk_pll36xx {
104 struct clk_hw hw;
105 const void __iomem *con_reg;
106};
107
108#define to_clk_pll36xx(_hw) container_of(_hw, struct samsung_clk_pll36xx, hw)
109
110static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
111 unsigned long parent_rate)
112{
113 struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw);
114 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
115 u64 fvco = parent_rate;
116
117 pll_con0 = __raw_readl(pll->con_reg);
118 pll_con1 = __raw_readl(pll->con_reg + 4);
119 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
120 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
121 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
122 kdiv = pll_con1 & PLL36XX_KDIV_MASK;
123
124 fvco *= (mdiv << 16) + kdiv;
125 do_div(fvco, (pdiv << sdiv));
126 fvco >>= 16;
127
128 return (unsigned long)fvco;
129}
130
131static const struct clk_ops samsung_pll36xx_clk_ops = {
132 .recalc_rate = samsung_pll36xx_recalc_rate,
133};
134
135struct clk * __init samsung_clk_register_pll36xx(const char *name,
136 const char *pname, const void __iomem *con_reg)
137{
138 struct samsung_clk_pll36xx *pll;
139 struct clk *clk;
140 struct clk_init_data init;
141
142 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
143 if (!pll) {
144 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
145 return NULL;
146 }
147
148 init.name = name;
149 init.ops = &samsung_pll36xx_clk_ops;
150 init.flags = CLK_GET_RATE_NOCACHE;
151 init.parent_names = &pname;
152 init.num_parents = 1;
153
154 pll->hw.init = &init;
155 pll->con_reg = con_reg;
156
157 clk = clk_register(NULL, &pll->hw);
158 if (IS_ERR(clk)) {
159 pr_err("%s: failed to register pll clock %s\n", __func__,
160 name);
161 kfree(pll);
162 }
163
164 if (clk_register_clkdev(clk, name, NULL))
165 pr_err("%s: failed to register lookup for %s", __func__, name);
166
167 return clk;
168}
169
170/*
171 * PLL45xx Clock Type
172 */
173
174#define PLL45XX_MDIV_MASK (0x3FF)
175#define PLL45XX_PDIV_MASK (0x3F)
176#define PLL45XX_SDIV_MASK (0x7)
177#define PLL45XX_MDIV_SHIFT (16)
178#define PLL45XX_PDIV_SHIFT (8)
179#define PLL45XX_SDIV_SHIFT (0)
180
181struct samsung_clk_pll45xx {
182 struct clk_hw hw;
183 enum pll45xx_type type;
184 const void __iomem *con_reg;
185};
186
187#define to_clk_pll45xx(_hw) container_of(_hw, struct samsung_clk_pll45xx, hw)
188
189static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
190 unsigned long parent_rate)
191{
192 struct samsung_clk_pll45xx *pll = to_clk_pll45xx(hw);
193 u32 mdiv, pdiv, sdiv, pll_con;
194 u64 fvco = parent_rate;
195
196 pll_con = __raw_readl(pll->con_reg);
197 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
198 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
199 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
200
201 if (pll->type == pll_4508)
202 sdiv = sdiv - 1;
203
204 fvco *= mdiv;
205 do_div(fvco, (pdiv << sdiv));
206
207 return (unsigned long)fvco;
208}
209
210static const struct clk_ops samsung_pll45xx_clk_ops = {
211 .recalc_rate = samsung_pll45xx_recalc_rate,
212};
213
214struct clk * __init samsung_clk_register_pll45xx(const char *name,
215 const char *pname, const void __iomem *con_reg,
216 enum pll45xx_type type)
217{
218 struct samsung_clk_pll45xx *pll;
219 struct clk *clk;
220 struct clk_init_data init;
221
222 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
223 if (!pll) {
224 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
225 return NULL;
226 }
227
228 init.name = name;
229 init.ops = &samsung_pll45xx_clk_ops;
230 init.flags = CLK_GET_RATE_NOCACHE;
231 init.parent_names = &pname;
232 init.num_parents = 1;
233
234 pll->hw.init = &init;
235 pll->con_reg = con_reg;
236 pll->type = type;
237
238 clk = clk_register(NULL, &pll->hw);
239 if (IS_ERR(clk)) {
240 pr_err("%s: failed to register pll clock %s\n", __func__,
241 name);
242 kfree(pll);
243 }
244
245 if (clk_register_clkdev(clk, name, NULL))
246 pr_err("%s: failed to register lookup for %s", __func__, name);
247
248 return clk;
249}
250
251/*
252 * PLL46xx Clock Type
253 */
254
255#define PLL46XX_MDIV_MASK (0x1FF)
256#define PLL46XX_PDIV_MASK (0x3F)
257#define PLL46XX_SDIV_MASK (0x7)
258#define PLL46XX_MDIV_SHIFT (16)
259#define PLL46XX_PDIV_SHIFT (8)
260#define PLL46XX_SDIV_SHIFT (0)
261
262#define PLL46XX_KDIV_MASK (0xFFFF)
263#define PLL4650C_KDIV_MASK (0xFFF)
264#define PLL46XX_KDIV_SHIFT (0)
265
266struct samsung_clk_pll46xx {
267 struct clk_hw hw;
268 enum pll46xx_type type;
269 const void __iomem *con_reg;
270};
271
272#define to_clk_pll46xx(_hw) container_of(_hw, struct samsung_clk_pll46xx, hw)
273
274static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
275 unsigned long parent_rate)
276{
277 struct samsung_clk_pll46xx *pll = to_clk_pll46xx(hw);
278 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
279 u64 fvco = parent_rate;
280
281 pll_con0 = __raw_readl(pll->con_reg);
282 pll_con1 = __raw_readl(pll->con_reg + 4);
283 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
284 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
285 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
286 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
287 pll_con1 & PLL46XX_KDIV_MASK;
288
289 shift = pll->type == pll_4600 ? 16 : 10;
290 fvco *= (mdiv << shift) + kdiv;
291 do_div(fvco, (pdiv << sdiv));
292 fvco >>= shift;
293
294 return (unsigned long)fvco;
295}
296
297static const struct clk_ops samsung_pll46xx_clk_ops = {
298 .recalc_rate = samsung_pll46xx_recalc_rate,
299};
300
301struct clk * __init samsung_clk_register_pll46xx(const char *name,
302 const char *pname, const void __iomem *con_reg,
303 enum pll46xx_type type)
304{
305 struct samsung_clk_pll46xx *pll;
306 struct clk *clk;
307 struct clk_init_data init;
308
309 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
310 if (!pll) {
311 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
312 return NULL;
313 }
314
315 init.name = name;
316 init.ops = &samsung_pll46xx_clk_ops;
317 init.flags = CLK_GET_RATE_NOCACHE;
318 init.parent_names = &pname;
319 init.num_parents = 1;
320
321 pll->hw.init = &init;
322 pll->con_reg = con_reg;
323 pll->type = type;
324
325 clk = clk_register(NULL, &pll->hw);
326 if (IS_ERR(clk)) {
327 pr_err("%s: failed to register pll clock %s\n", __func__,
328 name);
329 kfree(pll);
330 }
331
332 if (clk_register_clkdev(clk, name, NULL))
333 pr_err("%s: failed to register lookup for %s", __func__, name);
334
335 return clk;
336}
337
338/*
339 * PLL2550x Clock Type
340 */
341
342#define PLL2550X_R_MASK (0x1)
343#define PLL2550X_P_MASK (0x3F)
344#define PLL2550X_M_MASK (0x3FF)
345#define PLL2550X_S_MASK (0x7)
346#define PLL2550X_R_SHIFT (20)
347#define PLL2550X_P_SHIFT (14)
348#define PLL2550X_M_SHIFT (4)
349#define PLL2550X_S_SHIFT (0)
350
351struct samsung_clk_pll2550x {
352 struct clk_hw hw;
353 const void __iomem *reg_base;
354 unsigned long offset;
355};
356
357#define to_clk_pll2550x(_hw) container_of(_hw, struct samsung_clk_pll2550x, hw)
358
359static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
360 unsigned long parent_rate)
361{
362 struct samsung_clk_pll2550x *pll = to_clk_pll2550x(hw);
363 u32 r, p, m, s, pll_stat;
364 u64 fvco = parent_rate;
365
366 pll_stat = __raw_readl(pll->reg_base + pll->offset * 3);
367 r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
368 if (!r)
369 return 0;
370 p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK;
371 m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK;
372 s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK;
373
374 fvco *= m;
375 do_div(fvco, (p << s));
376
377 return (unsigned long)fvco;
378}
379
380static const struct clk_ops samsung_pll2550x_clk_ops = {
381 .recalc_rate = samsung_pll2550x_recalc_rate,
382};
383
384struct clk * __init samsung_clk_register_pll2550x(const char *name,
385 const char *pname, const void __iomem *reg_base,
386 const unsigned long offset)
387{
388 struct samsung_clk_pll2550x *pll;
389 struct clk *clk;
390 struct clk_init_data init;
391
392 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
393 if (!pll) {
394 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
395 return NULL;
396 }
397
398 init.name = name;
399 init.ops = &samsung_pll2550x_clk_ops;
400 init.flags = CLK_GET_RATE_NOCACHE;
401 init.parent_names = &pname;
402 init.num_parents = 1;
403
404 pll->hw.init = &init;
405 pll->reg_base = reg_base;
406 pll->offset = offset;
407
408 clk = clk_register(NULL, &pll->hw);
409 if (IS_ERR(clk)) {
410 pr_err("%s: failed to register pll clock %s\n", __func__,
411 name);
412 kfree(pll);
413 }
414
415 if (clk_register_clkdev(clk, name, NULL))
416 pr_err("%s: failed to register lookup for %s", __func__, name);
417
418 return clk;
419}
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
new file mode 100644
index 000000000000..f33786e9a78b
--- /dev/null
+++ b/drivers/clk/samsung/clk-pll.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for all PLL's in Samsung platforms
10*/
11
12#ifndef __SAMSUNG_CLK_PLL_H
13#define __SAMSUNG_CLK_PLL_H
14
15enum pll45xx_type {
16 pll_4500,
17 pll_4502,
18 pll_4508
19};
20
21enum pll46xx_type {
22 pll_4600,
23 pll_4650,
24 pll_4650c,
25};
26
27extern struct clk * __init samsung_clk_register_pll35xx(const char *name,
28 const char *pname, const void __iomem *con_reg);
29extern struct clk * __init samsung_clk_register_pll36xx(const char *name,
30 const char *pname, const void __iomem *con_reg);
31extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
32 const char *pname, const void __iomem *con_reg,
33 enum pll45xx_type type);
34extern struct clk * __init samsung_clk_register_pll46xx(const char *name,
35 const char *pname, const void __iomem *con_reg,
36 enum pll46xx_type type);
37extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
38 const char *pname, const void __iomem *reg_base,
39 const unsigned long offset);
40
41#endif /* __SAMSUNG_CLK_PLL_H */
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
new file mode 100644
index 000000000000..cd3c40ab50f3
--- /dev/null
+++ b/drivers/clk/samsung/clk.c
@@ -0,0 +1,320 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This file includes utility functions to register clocks to common
11 * clock framework for Samsung platforms.
12*/
13
14#include <linux/syscore_ops.h>
15#include "clk.h"
16
17static DEFINE_SPINLOCK(lock);
18static struct clk **clk_table;
19static void __iomem *reg_base;
20#ifdef CONFIG_OF
21static struct clk_onecell_data clk_data;
22#endif
23
24#ifdef CONFIG_PM_SLEEP
25static struct samsung_clk_reg_dump *reg_dump;
26static unsigned long nr_reg_dump;
27
28static int samsung_clk_suspend(void)
29{
30 struct samsung_clk_reg_dump *rd = reg_dump;
31 unsigned long i;
32
33 for (i = 0; i < nr_reg_dump; i++, rd++)
34 rd->value = __raw_readl(reg_base + rd->offset);
35
36 return 0;
37}
38
39static void samsung_clk_resume(void)
40{
41 struct samsung_clk_reg_dump *rd = reg_dump;
42 unsigned long i;
43
44 for (i = 0; i < nr_reg_dump; i++, rd++)
45 __raw_writel(rd->value, reg_base + rd->offset);
46}
47
48static struct syscore_ops samsung_clk_syscore_ops = {
49 .suspend = samsung_clk_suspend,
50 .resume = samsung_clk_resume,
51};
52#endif /* CONFIG_PM_SLEEP */
53
54/* setup the essentials required to support clock lookup using ccf */
55void __init samsung_clk_init(struct device_node *np, void __iomem *base,
56 unsigned long nr_clks, unsigned long *rdump,
57 unsigned long nr_rdump, unsigned long *soc_rdump,
58 unsigned long nr_soc_rdump)
59{
60 reg_base = base;
61
62#ifdef CONFIG_PM_SLEEP
63 if (rdump && nr_rdump) {
64 unsigned int idx;
65 reg_dump = kzalloc(sizeof(struct samsung_clk_reg_dump)
66 * (nr_rdump + nr_soc_rdump), GFP_KERNEL);
67 if (!reg_dump) {
68 pr_err("%s: memory alloc for register dump failed\n",
69 __func__);
70 return;
71 }
72
73 for (idx = 0; idx < nr_rdump; idx++)
74 reg_dump[idx].offset = rdump[idx];
75 for (idx = 0; idx < nr_soc_rdump; idx++)
76 reg_dump[nr_rdump + idx].offset = soc_rdump[idx];
77 nr_reg_dump = nr_rdump + nr_soc_rdump;
78 register_syscore_ops(&samsung_clk_syscore_ops);
79 }
80#endif
81
82 clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
83 if (!clk_table)
84 panic("could not allocate clock lookup table\n");
85
86 if (!np)
87 return;
88
89#ifdef CONFIG_OF
90 clk_data.clks = clk_table;
91 clk_data.clk_num = nr_clks;
92 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
93#endif
94}
95
96/* add a clock instance to the clock lookup table used for dt based lookup */
97void samsung_clk_add_lookup(struct clk *clk, unsigned int id)
98{
99 if (clk_table && id)
100 clk_table[id] = clk;
101}
102
103/* register a list of aliases */
104void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
105 unsigned int nr_clk)
106{
107 struct clk *clk;
108 unsigned int idx, ret;
109
110 if (!clk_table) {
111 pr_err("%s: clock table missing\n", __func__);
112 return;
113 }
114
115 for (idx = 0; idx < nr_clk; idx++, list++) {
116 if (!list->id) {
117 pr_err("%s: clock id missing for index %d\n", __func__,
118 idx);
119 continue;
120 }
121
122 clk = clk_table[list->id];
123 if (!clk) {
124 pr_err("%s: failed to find clock %d\n", __func__,
125 list->id);
126 continue;
127 }
128
129 ret = clk_register_clkdev(clk, list->alias, list->dev_name);
130 if (ret)
131 pr_err("%s: failed to register lookup %s\n",
132 __func__, list->alias);
133 }
134}
135
136/* register a list of fixed clocks */
137void __init samsung_clk_register_fixed_rate(
138 struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
139{
140 struct clk *clk;
141 unsigned int idx, ret;
142
143 for (idx = 0; idx < nr_clk; idx++, list++) {
144 clk = clk_register_fixed_rate(NULL, list->name,
145 list->parent_name, list->flags, list->fixed_rate);
146 if (IS_ERR(clk)) {
147 pr_err("%s: failed to register clock %s\n", __func__,
148 list->name);
149 continue;
150 }
151
152 samsung_clk_add_lookup(clk, list->id);
153
154 /*
155 * Unconditionally add a clock lookup for the fixed rate clocks.
156 * There are not many of these on any of Samsung platforms.
157 */
158 ret = clk_register_clkdev(clk, list->name, NULL);
159 if (ret)
160 pr_err("%s: failed to register clock lookup for %s",
161 __func__, list->name);
162 }
163}
164
165/* register a list of fixed factor clocks */
166void __init samsung_clk_register_fixed_factor(
167 struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
168{
169 struct clk *clk;
170 unsigned int idx;
171
172 for (idx = 0; idx < nr_clk; idx++, list++) {
173 clk = clk_register_fixed_factor(NULL, list->name,
174 list->parent_name, list->flags, list->mult, list->div);
175 if (IS_ERR(clk)) {
176 pr_err("%s: failed to register clock %s\n", __func__,
177 list->name);
178 continue;
179 }
180
181 samsung_clk_add_lookup(clk, list->id);
182 }
183}
184
185/* register a list of mux clocks */
186void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
187 unsigned int nr_clk)
188{
189 struct clk *clk;
190 unsigned int idx, ret;
191
192 for (idx = 0; idx < nr_clk; idx++, list++) {
193 clk = clk_register_mux(NULL, list->name, list->parent_names,
194 list->num_parents, list->flags, reg_base + list->offset,
195 list->shift, list->width, list->mux_flags, &lock);
196 if (IS_ERR(clk)) {
197 pr_err("%s: failed to register clock %s\n", __func__,
198 list->name);
199 continue;
200 }
201
202 samsung_clk_add_lookup(clk, list->id);
203
204 /* register a clock lookup only if a clock alias is specified */
205 if (list->alias) {
206 ret = clk_register_clkdev(clk, list->alias,
207 list->dev_name);
208 if (ret)
209 pr_err("%s: failed to register lookup %s\n",
210 __func__, list->alias);
211 }
212 }
213}
214
215/* register a list of div clocks */
216void __init samsung_clk_register_div(struct samsung_div_clock *list,
217 unsigned int nr_clk)
218{
219 struct clk *clk;
220 unsigned int idx, ret;
221
222 for (idx = 0; idx < nr_clk; idx++, list++) {
223 if (list->table)
224 clk = clk_register_divider_table(NULL, list->name,
225 list->parent_name, list->flags,
226 reg_base + list->offset, list->shift,
227 list->width, list->div_flags,
228 list->table, &lock);
229 else
230 clk = clk_register_divider(NULL, list->name,
231 list->parent_name, list->flags,
232 reg_base + list->offset, list->shift,
233 list->width, list->div_flags, &lock);
234 if (IS_ERR(clk)) {
235 pr_err("%s: failed to register clock %s\n", __func__,
236 list->name);
237 continue;
238 }
239
240 samsung_clk_add_lookup(clk, list->id);
241
242 /* register a clock lookup only if a clock alias is specified */
243 if (list->alias) {
244 ret = clk_register_clkdev(clk, list->alias,
245 list->dev_name);
246 if (ret)
247 pr_err("%s: failed to register lookup %s\n",
248 __func__, list->alias);
249 }
250 }
251}
252
253/* register a list of gate clocks */
254void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
255 unsigned int nr_clk)
256{
257 struct clk *clk;
258 unsigned int idx, ret;
259
260 for (idx = 0; idx < nr_clk; idx++, list++) {
261 clk = clk_register_gate(NULL, list->name, list->parent_name,
262 list->flags, reg_base + list->offset,
263 list->bit_idx, list->gate_flags, &lock);
264 if (IS_ERR(clk)) {
265 pr_err("%s: failed to register clock %s\n", __func__,
266 list->name);
267 continue;
268 }
269
270 /* register a clock lookup only if a clock alias is specified */
271 if (list->alias) {
272 ret = clk_register_clkdev(clk, list->alias,
273 list->dev_name);
274 if (ret)
275 pr_err("%s: failed to register lookup %s\n",
276 __func__, list->alias);
277 }
278
279 samsung_clk_add_lookup(clk, list->id);
280 }
281}
282
283/*
284 * obtain the clock speed of all external fixed clock sources from device
285 * tree and register it
286 */
287#ifdef CONFIG_OF
288void __init samsung_clk_of_register_fixed_ext(
289 struct samsung_fixed_rate_clock *fixed_rate_clk,
290 unsigned int nr_fixed_rate_clk,
291 struct of_device_id *clk_matches)
292{
293 const struct of_device_id *match;
294 struct device_node *np;
295 u32 freq;
296
297 for_each_matching_node_and_match(np, clk_matches, &match) {
298 if (of_property_read_u32(np, "clock-frequency", &freq))
299 continue;
300 fixed_rate_clk[(u32)match->data].fixed_rate = freq;
301 }
302 samsung_clk_register_fixed_rate(fixed_rate_clk, nr_fixed_rate_clk);
303}
304#endif
305
306/* utility function to get the rate of a specified clock */
307unsigned long _get_rate(const char *clk_name)
308{
309 struct clk *clk;
310 unsigned long rate;
311
312 clk = clk_get(NULL, clk_name);
313 if (IS_ERR(clk)) {
314 pr_err("%s: could not find clock %s\n", __func__, clk_name);
315 return 0;
316 }
317 rate = clk_get_rate(clk);
318 clk_put(clk);
319 return rate;
320}
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
new file mode 100644
index 000000000000..10b2111f0c0f
--- /dev/null
+++ b/drivers/clk/samsung/clk.h
@@ -0,0 +1,289 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for all Samsung platforms
11*/
12
13#ifndef __SAMSUNG_CLK_H
14#define __SAMSUNG_CLK_H
15
16#include <linux/clk.h>
17#include <linux/clkdev.h>
18#include <linux/io.h>
19#include <linux/clk-provider.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22
23#include <mach/map.h>
24
25/**
26 * struct samsung_clock_alias: information about mux clock
27 * @id: platform specific id of the clock.
28 * @dev_name: name of the device to which this clock belongs.
29 * @alias: optional clock alias name to be assigned to this clock.
30 */
31struct samsung_clock_alias {
32 unsigned int id;
33 const char *dev_name;
34 const char *alias;
35};
36
37#define ALIAS(_id, dname, a) \
38 { \
39 .id = _id, \
40 .dev_name = dname, \
41 .alias = a, \
42 }
43
44/**
45 * struct samsung_fixed_rate_clock: information about fixed-rate clock
46 * @id: platform specific id of the clock.
47 * @name: name of this fixed-rate clock.
48 * @parent_name: optional parent clock name.
49 * @flags: optional fixed-rate clock flags.
50 * @fixed-rate: fixed clock rate of this clock.
51 */
52struct samsung_fixed_rate_clock {
53 unsigned int id;
54 char *name;
55 const char *parent_name;
56 unsigned long flags;
57 unsigned long fixed_rate;
58};
59
60#define FRATE(_id, cname, pname, f, frate) \
61 { \
62 .id = _id, \
63 .name = cname, \
64 .parent_name = pname, \
65 .flags = f, \
66 .fixed_rate = frate, \
67 }
68
69/*
70 * struct samsung_fixed_factor_clock: information about fixed-factor clock
71 * @id: platform specific id of the clock.
72 * @name: name of this fixed-factor clock.
73 * @parent_name: parent clock name.
74 * @mult: fixed multiplication factor.
75 * @div: fixed division factor.
76 * @flags: optional fixed-factor clock flags.
77 */
78struct samsung_fixed_factor_clock {
79 unsigned int id;
80 char *name;
81 const char *parent_name;
82 unsigned long mult;
83 unsigned long div;
84 unsigned long flags;
85};
86
87#define FFACTOR(_id, cname, pname, m, d, f) \
88 { \
89 .id = _id, \
90 .name = cname, \
91 .parent_name = pname, \
92 .mult = m, \
93 .div = d, \
94 .flags = f, \
95 }
96
97/**
98 * struct samsung_mux_clock: information about mux clock
99 * @id: platform specific id of the clock.
100 * @dev_name: name of the device to which this clock belongs.
101 * @name: name of this mux clock.
102 * @parent_names: array of pointer to parent clock names.
103 * @num_parents: number of parents listed in @parent_names.
104 * @flags: optional flags for basic clock.
105 * @offset: offset of the register for configuring the mux.
106 * @shift: starting bit location of the mux control bit-field in @reg.
107 * @width: width of the mux control bit-field in @reg.
108 * @mux_flags: flags for mux-type clock.
109 * @alias: optional clock alias name to be assigned to this clock.
110 */
111struct samsung_mux_clock {
112 unsigned int id;
113 const char *dev_name;
114 const char *name;
115 const char **parent_names;
116 u8 num_parents;
117 unsigned long flags;
118 unsigned long offset;
119 u8 shift;
120 u8 width;
121 u8 mux_flags;
122 const char *alias;
123};
124
125#define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a) \
126 { \
127 .id = _id, \
128 .dev_name = dname, \
129 .name = cname, \
130 .parent_names = pnames, \
131 .num_parents = ARRAY_SIZE(pnames), \
132 .flags = f, \
133 .offset = o, \
134 .shift = s, \
135 .width = w, \
136 .mux_flags = mf, \
137 .alias = a, \
138 }
139
140#define MUX(_id, cname, pnames, o, s, w) \
141 __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL)
142
143#define MUX_A(_id, cname, pnames, o, s, w, a) \
144 __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
145
146#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
147 __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL)
148
149/**
150 * @id: platform specific id of the clock.
151 * struct samsung_div_clock: information about div clock
152 * @dev_name: name of the device to which this clock belongs.
153 * @name: name of this div clock.
154 * @parent_name: name of the parent clock.
155 * @flags: optional flags for basic clock.
156 * @offset: offset of the register for configuring the div.
157 * @shift: starting bit location of the div control bit-field in @reg.
158 * @div_flags: flags for div-type clock.
159 * @alias: optional clock alias name to be assigned to this clock.
160 */
161struct samsung_div_clock {
162 unsigned int id;
163 const char *dev_name;
164 const char *name;
165 const char *parent_name;
166 unsigned long flags;
167 unsigned long offset;
168 u8 shift;
169 u8 width;
170 u8 div_flags;
171 const char *alias;
172 struct clk_div_table *table;
173};
174
175#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t) \
176 { \
177 .id = _id, \
178 .dev_name = dname, \
179 .name = cname, \
180 .parent_name = pname, \
181 .flags = f, \
182 .offset = o, \
183 .shift = s, \
184 .width = w, \
185 .div_flags = df, \
186 .alias = a, \
187 .table = t, \
188 }
189
190#define DIV(_id, cname, pname, o, s, w) \
191 __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL)
192
193#define DIV_A(_id, cname, pname, o, s, w, a) \
194 __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
195
196#define DIV_F(_id, cname, pname, o, s, w, f, df) \
197 __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL)
198
199#define DIV_T(_id, cname, pname, o, s, w, t) \
200 __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t)
201
202/**
203 * struct samsung_gate_clock: information about gate clock
204 * @id: platform specific id of the clock.
205 * @dev_name: name of the device to which this clock belongs.
206 * @name: name of this gate clock.
207 * @parent_name: name of the parent clock.
208 * @flags: optional flags for basic clock.
209 * @offset: offset of the register for configuring the gate.
210 * @bit_idx: bit index of the gate control bit-field in @reg.
211 * @gate_flags: flags for gate-type clock.
212 * @alias: optional clock alias name to be assigned to this clock.
213 */
214struct samsung_gate_clock {
215 unsigned int id;
216 const char *dev_name;
217 const char *name;
218 const char *parent_name;
219 unsigned long flags;
220 unsigned long offset;
221 u8 bit_idx;
222 u8 gate_flags;
223 const char *alias;
224};
225
226#define __GATE(_id, dname, cname, pname, o, b, f, gf, a) \
227 { \
228 .id = _id, \
229 .dev_name = dname, \
230 .name = cname, \
231 .parent_name = pname, \
232 .flags = f, \
233 .offset = o, \
234 .bit_idx = b, \
235 .gate_flags = gf, \
236 .alias = a, \
237 }
238
239#define GATE(_id, cname, pname, o, b, f, gf) \
240 __GATE(_id, NULL, cname, pname, o, b, f, gf, NULL)
241
242#define GATE_A(_id, cname, pname, o, b, f, gf, a) \
243 __GATE(_id, NULL, cname, pname, o, b, f, gf, a)
244
245#define GATE_D(_id, dname, cname, pname, o, b, f, gf) \
246 __GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
247
248#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a) \
249 __GATE(_id, dname, cname, pname, o, b, f, gf, a)
250
251#define PNAME(x) static const char *x[] __initdata
252
253/**
254 * struct samsung_clk_reg_dump: register dump of clock controller registers.
255 * @offset: clock register offset from the controller base address.
256 * @value: the value to be register at offset.
257 */
258struct samsung_clk_reg_dump {
259 u32 offset;
260 u32 value;
261};
262
263extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
264 unsigned long nr_clks, unsigned long *rdump,
265 unsigned long nr_rdump, unsigned long *soc_rdump,
266 unsigned long nr_soc_rdump);
267extern void __init samsung_clk_of_register_fixed_ext(
268 struct samsung_fixed_rate_clock *fixed_rate_clk,
269 unsigned int nr_fixed_rate_clk,
270 struct of_device_id *clk_matches);
271
272extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
273
274extern void samsung_clk_register_alias(struct samsung_clock_alias *list,
275 unsigned int nr_clk);
276extern void __init samsung_clk_register_fixed_rate(
277 struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
278extern void __init samsung_clk_register_fixed_factor(
279 struct samsung_fixed_factor_clock *list, unsigned int nr_clk);
280extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list,
281 unsigned int nr_clk);
282extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list,
283 unsigned int nr_clk);
284extern void __init samsung_clk_register_gate(
285 struct samsung_gate_clock *clk_list, unsigned int nr_clk);
286
287extern unsigned long _get_rate(const char *clk_name);
288
289#endif /* __SAMSUNG_CLK_H */
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 957af8636c9d..509a6019c96c 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -477,12 +477,20 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
477}; 477};
478#endif /* CONFIG_LOCAL_TIMERS */ 478#endif /* CONFIG_LOCAL_TIMERS */
479 479
480static void __init exynos4_timer_resources(void __iomem *base) 480static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
481{ 481{
482 struct clk *mct_clk; 482 struct clk *mct_clk, *tick_clk;
483 mct_clk = clk_get(NULL, "xtal");
484 483
485 clk_rate = clk_get_rate(mct_clk); 484 tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
485 clk_get(NULL, "fin_pll");
486 if (IS_ERR(tick_clk))
487 panic("%s: unable to determine tick clock rate\n", __func__);
488 clk_rate = clk_get_rate(tick_clk);
489
490 mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
491 if (IS_ERR(mct_clk))
492 panic("%s: unable to retrieve mct clock instance\n", __func__);
493 clk_prepare_enable(mct_clk);
486 494
487 reg_base = base; 495 reg_base = base;
488 if (!reg_base) 496 if (!reg_base)
@@ -514,7 +522,7 @@ void __init mct_init(void)
514 panic("unable to determine mct controller type\n"); 522 panic("unable to determine mct controller type\n");
515 } 523 }
516 524
517 exynos4_timer_resources(S5P_VA_SYSTIMER); 525 exynos4_timer_resources(NULL, S5P_VA_SYSTIMER);
518 exynos4_clocksource_init(); 526 exynos4_clocksource_init();
519 exynos4_clockevent_init(); 527 exynos4_clockevent_init();
520} 528}
@@ -537,7 +545,7 @@ static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
537 for (i = MCT_L0_IRQ; i < nr_irqs; i++) 545 for (i = MCT_L0_IRQ; i < nr_irqs; i++)
538 mct_irqs[i] = irq_of_parse_and_map(np, i); 546 mct_irqs[i] = irq_of_parse_and_map(np, i);
539 547
540 exynos4_timer_resources(of_iomap(np, 0)); 548 exynos4_timer_resources(np, of_iomap(np, 0));
541 exynos4_clocksource_init(); 549 exynos4_clocksource_init();
542 exynos4_clockevent_init(); 550 exynos4_clockevent_init();
543} 551}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-18 00:12:22 -0500