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authorLinus Torvalds <torvalds@linux-foundation.org>2012-12-14 17:42:53 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-12-14 17:42:53 -0500
commit0beb58783f2168354e2b5297af45fc7db70adf12 (patch)
tree4debaf4f276990adf1892b7efe57edd344367464
parent6a57d104c8cb5b6adad6784b4ce6e2f7f9961a3a (diff)
parenteabc5fa51c1fae4b66cf883e3a3c2b3ca794494c (diff)
Merge tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device-tree updates, take 2, from Olof Johansson: "This branch contains device-tree updates for the SPEAr platform. They had dependencies on earlier branches from this merge window, which is why they were broken out in a separate branch." * tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: SPEAr3xx: Shirq: Move shirq controller out of plat/ ARM: SPEAr320: DT: Add SPEAr 320 HMI board support ARM: SPEAr3xx: DT: add shirq node for interrupt multiplexor ARM: SPEAr3xx: shirq: simplify and move the shared irq multiplexor to DT ARM: SPEAr1310: Fix AUXDATA for compact flash controller ARM: SPEAr13xx: Remove fields not required for ssp controller ARM: SPEAr1310: Move 1310 specific misc register into machine specific files ARM: SPEAr: DT: Update device nodes ARM: SPEAr: DT: add uart state to fix warning ARM: SPEAr: DT: Modify DT bindings for STMMAC ARM: SPEAr: DT: Fix existing DT support ARM: SPEAr: DT: Update partition info for MTD devices ARM: SPEAr: DT: Update pinctrl list ARM: SPEAr13xx: DT: Add spics gpio controller nodes
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/spear/shirq.txt48
-rw-r--r--arch/arm/boot/dts/Makefile3
-rw-r--r--arch/arm/boot/dts/spear1310-evb.dts165
-rw-r--r--arch/arm/boot/dts/spear1310.dtsi32
-rw-r--r--arch/arm/boot/dts/spear1340-evb.dts253
-rw-r--r--arch/arm/boot/dts/spear1340.dtsi61
-rw-r--r--arch/arm/boot/dts/spear13xx.dtsi72
-rw-r--r--arch/arm/boot/dts/spear300-evb.dts20
-rw-r--r--arch/arm/boot/dts/spear300.dtsi14
-rw-r--r--arch/arm/boot/dts/spear310-evb.dts30
-rw-r--r--arch/arm/boot/dts/spear310.dtsi18
-rw-r--r--arch/arm/boot/dts/spear320-evb.dts35
-rw-r--r--arch/arm/boot/dts/spear320-hmi.dts305
-rw-r--r--arch/arm/boot/dts/spear320.dtsi39
-rw-r--r--arch/arm/boot/dts/spear3xx.dtsi5
-rw-r--r--arch/arm/boot/dts/spear600-evb.dts46
-rw-r--r--arch/arm/boot/dts/spear600.dtsi16
-rw-r--r--arch/arm/mach-spear13xx/include/mach/spear.h8
-rw-r--r--arch/arm/mach-spear13xx/spear1310.c16
-rw-r--r--arch/arm/mach-spear13xx/spear13xx.c2
-rw-r--r--arch/arm/mach-spear3xx/include/mach/irqs.h10
-rw-r--r--arch/arm/mach-spear3xx/spear300.c103
-rw-r--r--arch/arm/mach-spear3xx/spear310.c202
-rw-r--r--arch/arm/mach-spear3xx/spear320.c205
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c4
-rw-r--r--arch/arm/plat-spear/Makefile2
-rw-r--r--arch/arm/plat-spear/shirq.c118
-rw-r--r--drivers/clk/spear/spear1310_clock.c1
-rw-r--r--drivers/irqchip/Makefile7
-rw-r--r--drivers/irqchip/spear-shirq.c316
-rw-r--r--include/linux/irqchip/spear-shirq.h (renamed from arch/arm/plat-spear/include/plat/shirq.h)49
31 files changed, 1428 insertions, 777 deletions
diff --git a/Documentation/devicetree/bindings/arm/spear/shirq.txt b/Documentation/devicetree/bindings/arm/spear/shirq.txt
new file mode 100644
index 000000000000..13fbb8866bd6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear/shirq.txt
@@ -0,0 +1,48 @@
1* SPEAr Shared IRQ layer (shirq)
2
3SPEAr3xx architecture includes shared/multiplexed irqs for certain set
4of devices. The multiplexor provides a single interrupt to parent
5interrupt controller (VIC) on behalf of a group of devices.
6
7There can be multiple groups available on SPEAr3xx variants but not
8exceeding 4. The number of devices in a group can differ, further they
9may share same set of status/mask registers spanning across different
10bit masks. Also in some cases the group may not have enable or other
11registers. This makes software little complex.
12
13A single node in the device tree is used to describe the shared
14interrupt multiplexor (one node for all groups). A group in the
15interrupt controller shares config/control registers with other groups.
16For example, a 32-bit interrupt enable/disable config register can
17accommodate upto 4 interrupt groups.
18
19Required properties:
20 - compatible: should be, either of
21 - "st,spear300-shirq"
22 - "st,spear310-shirq"
23 - "st,spear320-shirq"
24 - interrupt-controller: Identifies the node as an interrupt controller.
25 - #interrupt-cells: should be <1> which basically contains the offset
26 (starting from 0) of interrupts for all the groups.
27 - reg: Base address and size of shirq registers.
28 - interrupts: The list of interrupts generated by the groups which are
29 then connected to a parent interrupt controller. Each group is
30 associated with one of the interrupts, hence number of interrupts (to
31 parent) is equal to number of groups. The format of the interrupt
32 specifier depends in the interrupt parent controller.
33
34 Optional properties:
35 - interrupt-parent: pHandle of the parent interrupt controller, if not
36 inherited from the parent node.
37
38Example:
39
40The following is an example from the SPEAr320 SoC dtsi file.
41
42shirq: interrupt-controller@0xb3000000 {
43 compatible = "st,spear320-shirq";
44 reg = <0xb3000000 0x1000>;
45 interrupts = <28 29 30 1>;
46 #interrupt-cells = <1>;
47 interrupt-controller;
48};
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 2af359cfe985..d0ae1d3a90d9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -126,7 +126,8 @@ dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
126 spear1340-evb.dtb 126 spear1340-evb.dtb
127dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ 127dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
128 spear310-evb.dtb \ 128 spear310-evb.dtb \
129 spear320-evb.dtb 129 spear320-evb.dtb \
130 spear320-hmi.dtb
130dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb 131dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
131dtb-$(CONFIG_ARCH_SUNXI) += sun4i-cubieboard.dtb \ 132dtb-$(CONFIG_ARCH_SUNXI) += sun4i-cubieboard.dtb \
132 sun5i-olinuxino.dtb 133 sun5i-olinuxino.dtb
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index 2e4c5727468e..b56a801e42a2 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -30,10 +30,14 @@
30 pinctrl-0 = <&state_default>; 30 pinctrl-0 = <&state_default>;
31 31
32 state_default: pinmux { 32 state_default: pinmux {
33 i2c0-pmx { 33 i2c0 {
34 st,pins = "i2c0_grp"; 34 st,pins = "i2c0_grp";
35 st,function = "i2c0"; 35 st,function = "i2c0";
36 }; 36 };
37 i2s0 {
38 st,pins = "i2s0_grp";
39 st,function = "i2s0";
40 };
37 i2s1 { 41 i2s1 {
38 st,pins = "i2s1_grp"; 42 st,pins = "i2s1_grp";
39 st,function = "i2s1"; 43 st,function = "i2s1";
@@ -42,6 +46,10 @@
42 st,pins = "arm_gpio_grp"; 46 st,pins = "arm_gpio_grp";
43 st,function = "arm_gpio"; 47 st,function = "arm_gpio";
44 }; 48 };
49 clcd {
50 st,pins = "clcd_grp" , "clcd_high_res";
51 st,function = "clcd";
52 };
45 eth { 53 eth {
46 st,pins = "gmii_grp"; 54 st,pins = "gmii_grp";
47 st,function = "gmii"; 55 st,function = "gmii";
@@ -74,11 +82,6 @@
74 st,pins = "i2c_1_2_grp"; 82 st,pins = "i2c_1_2_grp";
75 st,function = "i2c_1_2"; 83 st,function = "i2c_1_2";
76 }; 84 };
77 pci {
78 st,pins = "pcie0_grp","pcie1_grp",
79 "pcie2_grp";
80 st,function = "pci";
81 };
82 smii { 85 smii {
83 st,pins = "smii_0_1_2_grp"; 86 st,pins = "smii_0_1_2_grp";
84 st,function = "smii_0_1_2"; 87 st,function = "smii_0_1_2";
@@ -88,6 +91,14 @@
88 "nand_16bit_grp"; 91 "nand_16bit_grp";
89 st,function = "nand"; 92 st,function = "nand";
90 }; 93 };
94 sata {
95 st,pins = "sata0_grp";
96 st,function = "sata";
97 };
98 pcie {
99 st,pins = "pcie1_grp", "pcie2_grp";
100 st,function = "pci_express";
101 };
91 }; 102 };
92 }; 103 };
93 104
@@ -109,9 +120,49 @@
109 120
110 fsmc: flash@b0000000 { 121 fsmc: flash@b0000000 {
111 status = "okay"; 122 status = "okay";
123
124 partition@0 {
125 label = "xloader";
126 reg = <0x0 0x80000>;
127 };
128 partition@80000 {
129 label = "u-boot";
130 reg = <0x80000 0x140000>;
131 };
132 partition@1C0000 {
133 label = "environment";
134 reg = <0x1C0000 0x40000>;
135 };
136 partition@200000 {
137 label = "dtb";
138 reg = <0x200000 0x40000>;
139 };
140 partition@240000 {
141 label = "linux";
142 reg = <0x240000 0xC00000>;
143 };
144 partition@E40000 {
145 label = "rootfs";
146 reg = <0xE40000 0x0>;
147 };
148 };
149
150 gpio_keys {
151 compatible = "gpio-keys";
152 #address-cells = <1>;
153 #size-cells = <0>;
154
155 button@1 {
156 label = "wakeup";
157 linux,code = <0x100>;
158 gpios = <&gpio0 7 0x4>;
159 debounce-interval = <20>;
160 gpio-key,wakeup = <1>;
161 };
112 }; 162 };
113 163
114 gmac0: eth@e2000000 { 164 gmac0: eth@e2000000 {
165 phy-mode = "gmii";
115 status = "okay"; 166 status = "okay";
116 }; 167 };
117 168
@@ -135,23 +186,27 @@
135 }; 186 };
136 partition@10000 { 187 partition@10000 {
137 label = "u-boot"; 188 label = "u-boot";
138 reg = <0x10000 0x40000>; 189 reg = <0x10000 0x50000>;
190 };
191 partition@60000 {
192 label = "environment";
193 reg = <0x60000 0x10000>;
139 }; 194 };
140 partition@50000 { 195 partition@70000 {
196 label = "dtb";
197 reg = <0x70000 0x10000>;
198 };
199 partition@80000 {
141 label = "linux"; 200 label = "linux";
142 reg = <0x50000 0x2c0000>; 201 reg = <0x80000 0x310000>;
143 }; 202 };
144 partition@310000 { 203 partition@390000 {
145 label = "rootfs"; 204 label = "rootfs";
146 reg = <0x310000 0x4f0000>; 205 reg = <0x390000 0x0>;
147 }; 206 };
148 }; 207 };
149 }; 208 };
150 209
151 spi0: spi@e0100000 {
152 status = "okay";
153 };
154
155 ehci@e4800000 { 210 ehci@e4800000 {
156 status = "okay"; 211 status = "okay";
157 }; 212 };
@@ -189,10 +244,6 @@
189 status = "okay"; 244 status = "okay";
190 }; 245 };
191 246
192 i2c1: i2c@5cd00000 {
193 status = "okay";
194 };
195
196 kbd@e0300000 { 247 kbd@e0300000 {
197 linux,keymap = < 0x00000001 248 linux,keymap = < 0x00000001
198 0x00010002 249 0x00010002
@@ -277,6 +328,7 @@
277 0x08080052 >; 328 0x08080052 >;
278 autorepeat; 329 autorepeat;
279 st,mode = <0>; 330 st,mode = <0>;
331 suspended_rate = <2000000>;
280 status = "okay"; 332 status = "okay";
281 }; 333 };
282 334
@@ -286,6 +338,81 @@
286 338
287 serial@e0000000 { 339 serial@e0000000 {
288 status = "okay"; 340 status = "okay";
341 pinctrl-names = "default";
342 pinctrl-0 = <>;
343 };
344
345 spi0: spi@e0100000 {
346 status = "okay";
347 num-cs = <3>;
348 cs-gpios = <&gpio1 7 0>, <&spics 0>, <&spics 1>;
349
350 stmpe610@0 {
351 compatible = "st,stmpe610";
352 reg = <0>;
353 #address-cells = <1>;
354 #size-cells = <0>;
355 spi-max-frequency = <1000000>;
356 spi-cpha;
357 pl022,hierarchy = <0>;
358 pl022,interface = <0>;
359 pl022,slave-tx-disable;
360 pl022,com-mode = <0>;
361 pl022,rx-level-trig = <0>;
362 pl022,tx-level-trig = <0>;
363 pl022,ctrl-len = <0x7>;
364 pl022,wait-state = <0>;
365 pl022,duplex = <0>;
366 interrupts = <6 0x4>;
367 interrupt-parent = <&gpio1>;
368 irq-trigger = <0x2>;
369
370 stmpe_touchscreen {
371 compatible = "st,stmpe-ts";
372 ts,sample-time = <4>;
373 ts,mod-12b = <1>;
374 ts,ref-sel = <0>;
375 ts,adc-freq = <1>;
376 ts,ave-ctrl = <1>;
377 ts,touch-det-delay = <2>;
378 ts,settling = <2>;
379 ts,fraction-z = <7>;
380 ts,i-drive = <1>;
381 };
382 };
383
384 m25p80@1 {
385 compatible = "st,m25p80";
386 reg = <1>;
387 spi-max-frequency = <12000000>;
388 spi-cpol;
389 spi-cpha;
390 pl022,hierarchy = <0>;
391 pl022,interface = <0>;
392 pl022,slave-tx-disable;
393 pl022,com-mode = <0x2>;
394 pl022,rx-level-trig = <0>;
395 pl022,tx-level-trig = <0>;
396 pl022,ctrl-len = <0x11>;
397 pl022,wait-state = <0>;
398 pl022,duplex = <0>;
399 };
400
401 spidev@2 {
402 compatible = "spidev";
403 reg = <2>;
404 spi-max-frequency = <25000000>;
405 spi-cpha;
406 pl022,hierarchy = <0>;
407 pl022,interface = <0>;
408 pl022,slave-tx-disable;
409 pl022,com-mode = <0x2>;
410 pl022,rx-level-trig = <0>;
411 pl022,tx-level-trig = <0>;
412 pl022,ctrl-len = <0x11>;
413 pl022,wait-state = <0>;
414 pl022,duplex = <0>;
415 };
289 }; 416 };
290 417
291 wdt@ec800620 { 418 wdt@ec800620 {
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 7cd25eb4f8e0..1513c1927cc8 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -17,6 +17,18 @@
17 compatible = "st,spear1310"; 17 compatible = "st,spear1310";
18 18
19 ahb { 19 ahb {
20 spics: spics@e0700000{
21 compatible = "st,spear-spics-gpio";
22 reg = <0xe0700000 0x1000>;
23 st-spics,peripcfg-reg = <0x3b0>;
24 st-spics,sw-enable-bit = <12>;
25 st-spics,cs-value-bit = <11>;
26 st-spics,cs-enable-mask = <3>;
27 st-spics,cs-enable-shift = <8>;
28 gpio-controller;
29 #gpio-cells = <2>;
30 };
31
20 ahci@b1000000 { 32 ahci@b1000000 {
21 compatible = "snps,spear-ahci"; 33 compatible = "snps,spear-ahci";
22 reg = <0xb1000000 0x10000>; 34 reg = <0xb1000000 0x10000>;
@@ -43,6 +55,7 @@
43 reg = <0x5c400000 0x8000>; 55 reg = <0x5c400000 0x8000>;
44 interrupts = <0 95 0x4>; 56 interrupts = <0 95 0x4>;
45 interrupt-names = "macirq"; 57 interrupt-names = "macirq";
58 phy-mode = "mii";
46 status = "disabled"; 59 status = "disabled";
47 }; 60 };
48 61
@@ -51,6 +64,7 @@
51 reg = <0x5c500000 0x8000>; 64 reg = <0x5c500000 0x8000>;
52 interrupts = <0 96 0x4>; 65 interrupts = <0 96 0x4>;
53 interrupt-names = "macirq"; 66 interrupt-names = "macirq";
67 phy-mode = "mii";
54 status = "disabled"; 68 status = "disabled";
55 }; 69 };
56 70
@@ -59,6 +73,7 @@
59 reg = <0x5c600000 0x8000>; 73 reg = <0x5c600000 0x8000>;
60 interrupts = <0 97 0x4>; 74 interrupts = <0 97 0x4>;
61 interrupt-names = "macirq"; 75 interrupt-names = "macirq";
76 phy-mode = "rmii";
62 status = "disabled"; 77 status = "disabled";
63 }; 78 };
64 79
@@ -67,6 +82,7 @@
67 reg = <0x5c700000 0x8000>; 82 reg = <0x5c700000 0x8000>;
68 interrupts = <0 98 0x4>; 83 interrupts = <0 98 0x4>;
69 interrupt-names = "macirq"; 84 interrupt-names = "macirq";
85 phy-mode = "rgmii";
70 status = "disabled"; 86 status = "disabled";
71 }; 87 };
72 88
@@ -76,13 +92,6 @@
76 #gpio-range-cells = <2>; 92 #gpio-range-cells = <2>;
77 }; 93 };
78 94
79 spi1: spi@5d400000 {
80 compatible = "arm,pl022", "arm,primecell";
81 reg = <0x5d400000 0x1000>;
82 interrupts = <0 99 0x4>;
83 status = "disabled";
84 };
85
86 apb { 95 apb {
87 i2c1: i2c@5cd00000 { 96 i2c1: i2c@5cd00000 {
88 #address-cells = <1>; 97 #address-cells = <1>;
@@ -147,6 +156,15 @@
147 status = "disabled"; 156 status = "disabled";
148 }; 157 };
149 158
159 spi1: spi@5d400000 {
160 compatible = "arm,pl022", "arm,primecell";
161 reg = <0x5d400000 0x1000>;
162 interrupts = <0 99 0x4>;
163 #address-cells = <1>;
164 #size-cells = <0>;
165 status = "disabled";
166 };
167
150 serial@5c800000 { 168 serial@5c800000 {
151 compatible = "arm,pl011", "arm,primecell"; 169 compatible = "arm,pl011", "arm,primecell";
152 reg = <0x5c800000 0x1000>; 170 reg = <0x5c800000 0x1000>;
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index 045f7123ffac..d6c30ae0a8d7 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -38,20 +38,15 @@
38 st,pins = "fsmc_8bit_grp"; 38 st,pins = "fsmc_8bit_grp";
39 st,function = "fsmc"; 39 st,function = "fsmc";
40 }; 40 };
41 kbd {
42 st,pins = "keyboard_row_col_grp",
43 "keyboard_col5_grp";
44 st,function = "keyboard";
45 };
46 uart0 { 41 uart0 {
47 st,pins = "uart0_grp", "uart0_enh_grp"; 42 st,pins = "uart0_grp";
48 st,function = "uart0"; 43 st,function = "uart0";
49 }; 44 };
50 i2c0-pmx { 45 i2c0 {
51 st,pins = "i2c0_grp"; 46 st,pins = "i2c0_grp";
52 st,function = "i2c0"; 47 st,function = "i2c0";
53 }; 48 };
54 i2c1-pmx { 49 i2c1 {
55 st,pins = "i2c1_grp"; 50 st,pins = "i2c1_grp";
56 st,function = "i2c1"; 51 st,function = "i2c1";
57 }; 52 };
@@ -64,14 +59,9 @@
64 st,function = "spdif_out"; 59 st,function = "spdif_out";
65 }; 60 };
66 ssp0 { 61 ssp0 {
67 st,pins = "ssp0_grp", "ssp0_cs1_grp", 62 st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp";
68 "ssp0_cs3_grp";
69 st,function = "ssp0"; 63 st,function = "ssp0";
70 }; 64 };
71 pwm {
72 st,pins = "pwm2_grp", "pwm3_grp";
73 st,function = "pwm";
74 };
75 smi-pmx { 65 smi-pmx {
76 st,pins = "smi_grp"; 66 st,pins = "smi_grp";
77 st,function = "smi"; 67 st,function = "smi";
@@ -84,6 +74,18 @@
84 st,pins = "gmii_grp", "rgmii_grp"; 74 st,pins = "gmii_grp", "rgmii_grp";
85 st,function = "gmac"; 75 st,function = "gmac";
86 }; 76 };
77 cam0 {
78 st,pins = "cam0_grp";
79 st,function = "cam0";
80 };
81 cam1 {
82 st,pins = "cam1_grp";
83 st,function = "cam1";
84 };
85 cam2 {
86 st,pins = "cam2_grp";
87 st,function = "cam2";
88 };
87 cam3 { 89 cam3 {
88 st,pins = "cam3_grp"; 90 st,pins = "cam3_grp";
89 st,function = "cam3"; 91 st,function = "cam3";
@@ -108,9 +110,18 @@
108 st,pins = "sata_grp"; 110 st,pins = "sata_grp";
109 st,function = "sata"; 111 st,function = "sata";
110 }; 112 };
113 pcie {
114 st,pins = "pcie_grp";
115 st,function = "pcie";
116 };
117
111 }; 118 };
112 }; 119 };
113 120
121 ahci@b1000000 {
122 status = "okay";
123 };
124
114 dma@ea800000 { 125 dma@ea800000 {
115 status = "okay"; 126 status = "okay";
116 }; 127 };
@@ -121,9 +132,35 @@
121 132
122 fsmc: flash@b0000000 { 133 fsmc: flash@b0000000 {
123 status = "okay"; 134 status = "okay";
135
136 partition@0 {
137 label = "xloader";
138 reg = <0x0 0x200000>;
139 };
140 partition@200000 {
141 label = "u-boot";
142 reg = <0x200000 0x200000>;
143 };
144 partition@400000 {
145 label = "environment";
146 reg = <0x400000 0x100000>;
147 };
148 partition@500000 {
149 label = "dtb";
150 reg = <0x500000 0x100000>;
151 };
152 partition@600000 {
153 label = "linux";
154 reg = <0x600000 0xC00000>;
155 };
156 partition@1200000 {
157 label = "rootfs";
158 reg = <0x1200000 0x0>;
159 };
124 }; 160 };
125 161
126 gmac0: eth@e2000000 { 162 gmac0: eth@e2000000 {
163 phy-mode = "rgmii";
127 status = "okay"; 164 status = "okay";
128 }; 165 };
129 166
@@ -147,31 +184,62 @@
147 }; 184 };
148 partition@10000 { 185 partition@10000 {
149 label = "u-boot"; 186 label = "u-boot";
150 reg = <0x10000 0x40000>; 187 reg = <0x10000 0x50000>;
188 };
189 partition@60000 {
190 label = "environment";
191 reg = <0x60000 0x10000>;
151 }; 192 };
152 partition@50000 { 193 partition@70000 {
194 label = "dtb";
195 reg = <0x70000 0x10000>;
196 };
197 partition@80000 {
153 label = "linux"; 198 label = "linux";
154 reg = <0x50000 0x2c0000>; 199 reg = <0x80000 0x310000>;
155 }; 200 };
156 partition@310000 { 201 partition@390000 {
157 label = "rootfs"; 202 label = "rootfs";
158 reg = <0x310000 0x4f0000>; 203 reg = <0x390000 0x0>;
159 }; 204 };
160 }; 205 };
161 }; 206 };
162 207
163 spi0: spi@e0100000 { 208 ehci@e4800000 {
164 status = "okay"; 209 status = "okay";
165 }; 210 };
166 211
167 ehci@e4800000 { 212 gpio_keys {
168 status = "okay"; 213 compatible = "gpio-keys";
214 #address-cells = <1>;
215 #size-cells = <0>;
216
217 button@1 {
218 label = "wakeup";
219 linux,code = <0x100>;
220 gpios = <&gpio1 1 0x4>;
221 debounce-interval = <20>;
222 gpio-key,wakeup = <1>;
223 };
169 }; 224 };
170 225
171 ehci@e5800000 { 226 ehci@e5800000 {
172 status = "okay"; 227 status = "okay";
173 }; 228 };
174 229
230 i2s0: i2s-play@b2400000 {
231 status = "okay";
232 };
233
234 i2s1: i2s-rec@b2000000 {
235 status = "okay";
236 };
237
238 incodec: dir-hifi {
239 compatible = "dummy,dir-hifi";
240 status = "okay";
241 };
242
175 ohci@e4000000 { 243 ohci@e4000000 {
176 status = "okay"; 244 status = "okay";
177 }; 245 };
@@ -180,11 +248,43 @@
180 status = "okay"; 248 status = "okay";
181 }; 249 };
182 250
251 outcodec: dit-hifi {
252 compatible = "dummy,dit-hifi";
253 status = "okay";
254 };
255
256 sound {
257 compatible = "spear,spear-evb";
258 audio-controllers = <&spdif0 &spdif1 &i2s0 &i2s1>;
259 audio-codecs = <&incodec &outcodec &sta529 &sta529>;
260 codec_dai_name = "dir-hifi", "dit-hifi", "sta529-audio", "sta529-audio";
261 stream_name = "spdif-cap", "spdif-play", "i2s-play", "i2s-cap";
262 dai_name = "spdifin-pcm", "spdifout-pcm", "i2s0-pcm", "i2s1-pcm";
263 nr_controllers = <4>;
264 status = "okay";
265 };
266
267 spdif0: spdif-in@d0100000 {
268 status = "okay";
269 };
270
271 spdif1: spdif-out@d0000000 {
272 status = "okay";
273 };
274
183 apb { 275 apb {
184 adc@e0080000 { 276 adc@e0080000 {
185 status = "okay"; 277 status = "okay";
186 }; 278 };
187 279
280 i2s-play@b2400000 {
281 status = "okay";
282 };
283
284 i2s-rec@b2000000 {
285 status = "okay";
286 };
287
188 gpio0: gpio@e0600000 { 288 gpio0: gpio@e0600000 {
189 status = "okay"; 289 status = "okay";
190 }; 290 };
@@ -199,10 +299,36 @@
199 299
200 i2c0: i2c@e0280000 { 300 i2c0: i2c@e0280000 {
201 status = "okay"; 301 status = "okay";
302
303 sta529: sta529@1a {
304 compatible = "st,sta529";
305 reg = <0x1a>;
306 };
202 }; 307 };
203 308
204 i2c1: i2c@b4000000 { 309 i2c1: i2c@b4000000 {
205 status = "okay"; 310 status = "okay";
311
312 eeprom0@56 {
313 compatible = "st,eeprom";
314 reg = <0x56>;
315 };
316
317 stmpe801@41 {
318 compatible = "st,stmpe801";
319 #address-cells = <1>;
320 #size-cells = <0>;
321 reg = <0x41>;
322 interrupts = <4 0x4>;
323 interrupt-parent = <&gpio0>;
324 irq-trigger = <0x2>;
325
326 stmpegpio: stmpe_gpio {
327 compatible = "st,stmpe-gpio";
328 gpio-controller;
329 #gpio-cells = <2>;
330 };
331 };
206 }; 332 };
207 333
208 kbd@e0300000 { 334 kbd@e0300000 {
@@ -289,6 +415,7 @@
289 0x08080052 >; 415 0x08080052 >;
290 autorepeat; 416 autorepeat;
291 st,mode = <0>; 417 st,mode = <0>;
418 suspended_rate = <2000000>;
292 status = "okay"; 419 status = "okay";
293 }; 420 };
294 421
@@ -298,10 +425,92 @@
298 425
299 serial@e0000000 { 426 serial@e0000000 {
300 status = "okay"; 427 status = "okay";
428 pinctrl-names = "default";
429 pinctrl-0 = <>;
301 }; 430 };
302 431
303 serial@b4100000 { 432 serial@b4100000 {
304 status = "okay"; 433 status = "okay";
434 pinctrl-names = "default";
435 pinctrl-0 = <>;
436 };
437
438 spi0: spi@e0100000 {
439 status = "okay";
440 num-cs = <3>;
441 cs-gpios = <&gpiopinctrl 80 0>, <&gpiopinctrl 24 0>,
442 <&gpiopinctrl 85 0>;
443
444 m25p80@0 {
445 compatible = "m25p80";
446 reg = <0>;
447 spi-max-frequency = <12000000>;
448 spi-cpol;
449 spi-cpha;
450 pl022,hierarchy = <0>;
451 pl022,interface = <0>;
452 pl022,slave-tx-disable;
453 pl022,com-mode = <0x2>;
454 pl022,rx-level-trig = <0>;
455 pl022,tx-level-trig = <0>;
456 pl022,ctrl-len = <0x11>;
457 pl022,wait-state = <0>;
458 pl022,duplex = <0>;
459 };
460
461 stmpe610@1 {
462 compatible = "st,stmpe610";
463 spi-max-frequency = <1000000>;
464 spi-cpha;
465 reg = <1>;
466 pl022,hierarchy = <0>;
467 pl022,interface = <0>;
468 pl022,slave-tx-disable;
469 pl022,com-mode = <0>;
470 pl022,rx-level-trig = <0>;
471 pl022,tx-level-trig = <0>;
472 pl022,ctrl-len = <0x7>;
473 pl022,wait-state = <0>;
474 pl022,duplex = <0>;
475 interrupts = <100 0>;
476 interrupt-parent = <&gpiopinctrl>;
477 irq-trigger = <0x2>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480
481 stmpe_touchscreen {
482 compatible = "st,stmpe-ts";
483 ts,sample-time = <4>;
484 ts,mod-12b = <1>;
485 ts,ref-sel = <0>;
486 ts,adc-freq = <1>;
487 ts,ave-ctrl = <1>;
488 ts,touch-det-delay = <2>;
489 ts,settling = <2>;
490 ts,fraction-z = <7>;
491 ts,i-drive = <1>;
492 };
493 };
494
495 spidev@2 {
496 compatible = "spidev";
497 reg = <2>;
498 spi-max-frequency = <25000000>;
499 spi-cpha;
500 pl022,hierarchy = <0>;
501 pl022,interface = <0>;
502 pl022,slave-tx-disable;
503 pl022,com-mode = <0x2>;
504 pl022,rx-level-trig = <0>;
505 pl022,tx-level-trig = <0>;
506 pl022,ctrl-len = <0x11>;
507 pl022,wait-state = <0>;
508 pl022,duplex = <0>;
509 };
510 };
511
512 timer@ec800600 {
513 status = "okay";
305 }; 514 };
306 515
307 wdt@ec800620 { 516 wdt@ec800620 {
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 6c09eb0a1b2b..34da11aa6795 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -17,6 +17,20 @@
17 compatible = "st,spear1340"; 17 compatible = "st,spear1340";
18 18
19 ahb { 19 ahb {
20
21 spics: spics@e0700000{
22 compatible = "st,spear-spics-gpio";
23 reg = <0xe0700000 0x1000>;
24 st-spics,peripcfg-reg = <0x42c>;
25 st-spics,sw-enable-bit = <21>;
26 st-spics,cs-value-bit = <20>;
27 st-spics,cs-enable-mask = <3>;
28 st-spics,cs-enable-shift = <18>;
29 gpio-controller;
30 #gpio-cells = <2>;
31 status = "disabled";
32 };
33
20 ahci@b1000000 { 34 ahci@b1000000 {
21 compatible = "snps,spear-ahci"; 35 compatible = "snps,spear-ahci";
22 reg = <0xb1000000 0x10000>; 36 reg = <0xb1000000 0x10000>;
@@ -24,15 +38,61 @@
24 status = "disabled"; 38 status = "disabled";
25 }; 39 };
26 40
41 i2s-play@b2400000 {
42 compatible = "snps,designware-i2s";
43 reg = <0xb2400000 0x10000>;
44 interrupt-names = "play_irq";
45 interrupts = <0 98 0x4
46 0 99 0x4>;
47 play;
48 channel = <8>;
49 status = "disabled";
50 };
51
52 i2s-rec@b2000000 {
53 compatible = "snps,designware-i2s";
54 reg = <0xb2000000 0x10000>;
55 interrupt-names = "record_irq";
56 interrupts = <0 100 0x4
57 0 101 0x4>;
58 record;
59 channel = <8>;
60 status = "disabled";
61 };
62
27 pinmux: pinmux@e0700000 { 63 pinmux: pinmux@e0700000 {
28 compatible = "st,spear1340-pinmux"; 64 compatible = "st,spear1340-pinmux";
29 reg = <0xe0700000 0x1000>; 65 reg = <0xe0700000 0x1000>;
30 #gpio-range-cells = <2>; 66 #gpio-range-cells = <2>;
31 }; 67 };
32 68
69 pwm: pwm@e0180000 {
70 compatible ="st,spear13xx-pwm";
71 reg = <0xe0180000 0x1000>;
72 #pwm-cells = <2>;
73 status = "disabled";
74 };
75
76 spdif-in@d0100000 {
77 compatible = "st,spdif-in";
78 reg = < 0xd0100000 0x20000
79 0xd0110000 0x10000 >;
80 interrupts = <0 84 0x4>;
81 status = "disabled";
82 };
83
84 spdif-out@d0000000 {
85 compatible = "st,spdif-out";
86 reg = <0xd0000000 0x20000>;
87 interrupts = <0 85 0x4>;
88 status = "disabled";
89 };
90
33 spi1: spi@5d400000 { 91 spi1: spi@5d400000 {
34 compatible = "arm,pl022", "arm,primecell"; 92 compatible = "arm,pl022", "arm,primecell";
35 reg = <0x5d400000 0x1000>; 93 reg = <0x5d400000 0x1000>;
94 #address-cells = <1>;
95 #size-cells = <0>;
36 interrupts = <0 99 0x4>; 96 interrupts = <0 99 0x4>;
37 status = "disabled"; 97 status = "disabled";
38 }; 98 };
@@ -44,6 +104,7 @@
44 compatible = "snps,designware-i2c"; 104 compatible = "snps,designware-i2c";
45 reg = <0xb4000000 0x1000>; 105 reg = <0xb4000000 0x1000>;
46 interrupts = <0 104 0x4>; 106 interrupts = <0 104 0x4>;
107 write-16bit;
47 status = "disabled"; 108 status = "disabled";
48 }; 109 };
49 110
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index f7b84aced654..009096d1d2c3 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -64,12 +64,26 @@
64 bootargs = "console=ttyAMA0,115200"; 64 bootargs = "console=ttyAMA0,115200";
65 }; 65 };
66 66
67 cpufreq {
68 compatible = "st,cpufreq-spear";
69 cpufreq_tbl = < 166000
70 200000
71 250000
72 300000
73 400000
74 500000
75 600000 >;
76 status = "disable";
77 };
78
67 ahb { 79 ahb {
68 #address-cells = <1>; 80 #address-cells = <1>;
69 #size-cells = <1>; 81 #size-cells = <1>;
70 compatible = "simple-bus"; 82 compatible = "simple-bus";
71 ranges = <0x50000000 0x50000000 0x10000000 83 ranges = <0x50000000 0x50000000 0x10000000
72 0xb0000000 0xb0000000 0x10000000 84 0xb0000000 0xb0000000 0x10000000
85 0xd0000000 0xd0000000 0x02000000
86 0xd8000000 0xd8000000 0x01000000
73 0xe0000000 0xe0000000 0x10000000>; 87 0xe0000000 0xe0000000 0x10000000>;
74 88
75 sdhci@b3000000 { 89 sdhci@b3000000 {
@@ -81,7 +95,7 @@
81 95
82 cf@b2800000 { 96 cf@b2800000 {
83 compatible = "arasan,cf-spear1340"; 97 compatible = "arasan,cf-spear1340";
84 reg = <0xb2800000 0x100>; 98 reg = <0xb2800000 0x1000>;
85 interrupts = <0 29 0x4>; 99 interrupts = <0 29 0x4>;
86 status = "disabled"; 100 status = "disabled";
87 }; 101 };
@@ -113,6 +127,7 @@
113 0 23 0x4>; 127 0 23 0x4>;
114 st,ale-off = <0x20000>; 128 st,ale-off = <0x20000>;
115 st,cle-off = <0x10000>; 129 st,cle-off = <0x10000>;
130 st,mode = <2>;
116 status = "disabled"; 131 status = "disabled";
117 }; 132 };
118 133
@@ -125,6 +140,13 @@
125 status = "disabled"; 140 status = "disabled";
126 }; 141 };
127 142
143 pcm {
144 compatible = "st,pcm-audio";
145 #address-cells = <0>;
146 #size-cells = <0>;
147 status = "disable";
148 };
149
128 smi: flash@ea000000 { 150 smi: flash@ea000000 {
129 compatible = "st,spear600-smi"; 151 compatible = "st,spear600-smi";
130 #address-cells = <1>; 152 #address-cells = <1>;
@@ -134,17 +156,11 @@
134 status = "disabled"; 156 status = "disabled";
135 }; 157 };
136 158
137 spi0: spi@e0100000 {
138 compatible = "arm,pl022", "arm,primecell";
139 reg = <0xe0100000 0x1000>;
140 interrupts = <0 31 0x4>;
141 status = "disabled";
142 };
143
144 ehci@e4800000 { 159 ehci@e4800000 {
145 compatible = "st,spear600-ehci", "usb-ehci"; 160 compatible = "st,spear600-ehci", "usb-ehci";
146 reg = <0xe4800000 0x1000>; 161 reg = <0xe4800000 0x1000>;
147 interrupts = <0 64 0x4>; 162 interrupts = <0 64 0x4>;
163 usbh0_id = <0>;
148 status = "disabled"; 164 status = "disabled";
149 }; 165 };
150 166
@@ -152,6 +168,7 @@
152 compatible = "st,spear600-ehci", "usb-ehci"; 168 compatible = "st,spear600-ehci", "usb-ehci";
153 reg = <0xe5800000 0x1000>; 169 reg = <0xe5800000 0x1000>;
154 interrupts = <0 66 0x4>; 170 interrupts = <0 66 0x4>;
171 usbh1_id = <1>;
155 status = "disabled"; 172 status = "disabled";
156 }; 173 };
157 174
@@ -159,6 +176,7 @@
159 compatible = "st,spear600-ohci", "usb-ohci"; 176 compatible = "st,spear600-ohci", "usb-ohci";
160 reg = <0xe4000000 0x1000>; 177 reg = <0xe4000000 0x1000>;
161 interrupts = <0 65 0x4>; 178 interrupts = <0 65 0x4>;
179 usbh0_id = <0>;
162 status = "disabled"; 180 status = "disabled";
163 }; 181 };
164 182
@@ -166,6 +184,7 @@
166 compatible = "st,spear600-ohci", "usb-ohci"; 184 compatible = "st,spear600-ohci", "usb-ohci";
167 reg = <0xe5000000 0x1000>; 185 reg = <0xe5000000 0x1000>;
168 interrupts = <0 67 0x4>; 186 interrupts = <0 67 0x4>;
187 usbh1_id = <1>;
169 status = "disabled"; 188 status = "disabled";
170 }; 189 };
171 190
@@ -175,6 +194,8 @@
175 compatible = "simple-bus"; 194 compatible = "simple-bus";
176 ranges = <0x50000000 0x50000000 0x10000000 195 ranges = <0x50000000 0x50000000 0x10000000
177 0xb0000000 0xb0000000 0x10000000 196 0xb0000000 0xb0000000 0x10000000
197 0xd0000000 0xd0000000 0x02000000
198 0xd8000000 0xd8000000 0x01000000
178 0xe0000000 0xe0000000 0x10000000>; 199 0xe0000000 0xe0000000 0x10000000>;
179 200
180 gpio0: gpio@e0600000 { 201 gpio0: gpio@e0600000 {
@@ -215,8 +236,35 @@
215 status = "disabled"; 236 status = "disabled";
216 }; 237 };
217 238
239 i2s@e0180000 {
240 compatible = "st,designware-i2s";
241 reg = <0xe0180000 0x1000>;
242 interrupt-names = "play_irq", "record_irq";
243 interrupts = <0 10 0x4
244 0 11 0x4 >;
245 status = "disabled";
246 };
247
248 i2s@e0200000 {
249 compatible = "st,designware-i2s";
250 reg = <0xe0200000 0x1000>;
251 interrupt-names = "play_irq", "record_irq";
252 interrupts = <0 26 0x4
253 0 53 0x4>;
254 status = "disabled";
255 };
256
257 spi0: spi@e0100000 {
258 compatible = "arm,pl022", "arm,primecell";
259 reg = <0xe0100000 0x1000>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 interrupts = <0 31 0x4>;
263 status = "disabled";
264 };
265
218 rtc@e0580000 { 266 rtc@e0580000 {
219 compatible = "st,spear-rtc"; 267 compatible = "st,spear600-rtc";
220 reg = <0xe0580000 0x1000>; 268 reg = <0xe0580000 0x1000>;
221 interrupts = <0 36 0x4>; 269 interrupts = <0 36 0x4>;
222 status = "disabled"; 270 status = "disabled";
@@ -232,7 +280,7 @@
232 adc@e0080000 { 280 adc@e0080000 {
233 compatible = "st,spear600-adc"; 281 compatible = "st,spear600-adc";
234 reg = <0xe0080000 0x1000>; 282 reg = <0xe0080000 0x1000>;
235 interrupts = <0 44 0x4>; 283 interrupts = <0 12 0x4>;
236 status = "disabled"; 284 status = "disabled";
237 }; 285 };
238 286
@@ -245,7 +293,8 @@
245 timer@ec800600 { 293 timer@ec800600 {
246 compatible = "arm,cortex-a9-twd-timer"; 294 compatible = "arm,cortex-a9-twd-timer";
247 reg = <0xec800600 0x20>; 295 reg = <0xec800600 0x20>;
248 interrupts = <1 13 0x301>; 296 interrupts = <1 13 0x4>;
297 status = "disabled";
249 }; 298 };
250 299
251 wdt@ec800620 { 300 wdt@ec800620 {
@@ -257,6 +306,7 @@
257 thermal@e07008c4 { 306 thermal@e07008c4 {
258 compatible = "st,thermal-spear1340"; 307 compatible = "st,thermal-spear1340";
259 reg = <0xe07008c4 0x4>; 308 reg = <0xe07008c4 0x4>;
309 thermal_flags = <0x7000>;
260 }; 310 };
261 }; 311 };
262 }; 312 };
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
index 1e7c7a8e2123..5de1431653e4 100644
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -100,15 +100,23 @@
100 }; 100 };
101 partition@10000 { 101 partition@10000 {
102 label = "u-boot"; 102 label = "u-boot";
103 reg = <0x10000 0x40000>; 103 reg = <0x10000 0x50000>;
104 }; 104 };
105 partition@50000 { 105 partition@60000 {
106 label = "environment";
107 reg = <0x60000 0x10000>;
108 };
109 partition@70000 {
110 label = "dtb";
111 reg = <0x70000 0x10000>;
112 };
113 partition@80000 {
106 label = "linux"; 114 label = "linux";
107 reg = <0x50000 0x2c0000>; 115 reg = <0x80000 0x310000>;
108 }; 116 };
109 partition@310000 { 117 partition@390000 {
110 label = "rootfs"; 118 label = "rootfs";
111 reg = <0x310000 0x4f0000>; 119 reg = <0x390000 0x0>;
112 }; 120 };
113 }; 121 };
114 }; 122 };
@@ -235,6 +243,8 @@
235 243
236 serial@d0000000 { 244 serial@d0000000 {
237 status = "okay"; 245 status = "okay";
246 pinctrl-names = "default";
247 pinctrl-0 = <>;
238 }; 248 };
239 249
240 wdt@fc880000 { 250 wdt@fc880000 {
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
index ed3627c116cc..090adc656015 100644
--- a/arch/arm/boot/dts/spear300.dtsi
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -27,7 +27,7 @@
27 }; 27 };
28 28
29 clcd@60000000 { 29 clcd@60000000 {
30 compatible = "arm,clcd-pl110", "arm,primecell"; 30 compatible = "arm,pl110", "arm,primecell";
31 reg = <0x60000000 0x1000>; 31 reg = <0x60000000 0x1000>;
32 interrupts = <30>; 32 interrupts = <30>;
33 status = "disabled"; 33 status = "disabled";
@@ -52,6 +52,14 @@
52 status = "disabled"; 52 status = "disabled";
53 }; 53 };
54 54
55 shirq: interrupt-controller@0x50000000 {
56 compatible = "st,spear300-shirq";
57 reg = <0x50000000 0x1000>;
58 interrupts = <28>;
59 #interrupt-cells = <1>;
60 interrupt-controller;
61 };
62
55 apb { 63 apb {
56 #address-cells = <1>; 64 #address-cells = <1>;
57 #size-cells = <1>; 65 #size-cells = <1>;
@@ -64,12 +72,16 @@
64 compatible = "arm,pl061", "arm,primecell"; 72 compatible = "arm,pl061", "arm,primecell";
65 gpio-controller; 73 gpio-controller;
66 reg = <0xa9000000 0x1000>; 74 reg = <0xa9000000 0x1000>;
75 interrupts = <8>;
76 interrupt-parent = <&shirq>;
67 status = "disabled"; 77 status = "disabled";
68 }; 78 };
69 79
70 kbd@a0000000 { 80 kbd@a0000000 {
71 compatible = "st,spear300-kbd"; 81 compatible = "st,spear300-kbd";
72 reg = <0xa0000000 0x1000>; 82 reg = <0xa0000000 0x1000>;
83 interrupts = <7>;
84 interrupt-parent = <&shirq>;
73 status = "disabled"; 85 status = "disabled";
74 }; 86 };
75 }; 87 };
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
index b00544e0cd5d..b09632963d15 100644
--- a/arch/arm/boot/dts/spear310-evb.dts
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -114,15 +114,23 @@
114 }; 114 };
115 partition@10000 { 115 partition@10000 {
116 label = "u-boot"; 116 label = "u-boot";
117 reg = <0x10000 0x40000>; 117 reg = <0x10000 0x50000>;
118 }; 118 };
119 partition@50000 { 119 partition@60000 {
120 label = "environment";
121 reg = <0x60000 0x10000>;
122 };
123 partition@70000 {
124 label = "dtb";
125 reg = <0x70000 0x10000>;
126 };
127 partition@80000 {
120 label = "linux"; 128 label = "linux";
121 reg = <0x50000 0x2c0000>; 129 reg = <0x80000 0x310000>;
122 }; 130 };
123 partition@310000 { 131 partition@390000 {
124 label = "rootfs"; 132 label = "rootfs";
125 reg = <0x310000 0x4f0000>; 133 reg = <0x390000 0x0>;
126 }; 134 };
127 }; 135 };
128 }; 136 };
@@ -158,26 +166,38 @@
158 166
159 serial@d0000000 { 167 serial@d0000000 {
160 status = "okay"; 168 status = "okay";
169 pinctrl-names = "default";
170 pinctrl-0 = <>;
161 }; 171 };
162 172
163 serial@b2000000 { 173 serial@b2000000 {
164 status = "okay"; 174 status = "okay";
175 pinctrl-names = "default";
176 pinctrl-0 = <>;
165 }; 177 };
166 178
167 serial@b2080000 { 179 serial@b2080000 {
168 status = "okay"; 180 status = "okay";
181 pinctrl-names = "default";
182 pinctrl-0 = <>;
169 }; 183 };
170 184
171 serial@b2100000 { 185 serial@b2100000 {
172 status = "okay"; 186 status = "okay";
187 pinctrl-names = "default";
188 pinctrl-0 = <>;
173 }; 189 };
174 190
175 serial@b2180000 { 191 serial@b2180000 {
176 status = "okay"; 192 status = "okay";
193 pinctrl-names = "default";
194 pinctrl-0 = <>;
177 }; 195 };
178 196
179 serial@b2200000 { 197 serial@b2200000 {
180 status = "okay"; 198 status = "okay";
199 pinctrl-names = "default";
200 pinctrl-0 = <>;
181 }; 201 };
182 202
183 wdt@fc880000 { 203 wdt@fc880000 {
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
index 930303e48df9..e814e5e97083 100644
--- a/arch/arm/boot/dts/spear310.dtsi
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -40,6 +40,14 @@
40 status = "disabled"; 40 status = "disabled";
41 }; 41 };
42 42
43 shirq: interrupt-controller@0xb4000000 {
44 compatible = "st,spear310-shirq";
45 reg = <0xb4000000 0x1000>;
46 interrupts = <28 29 30 1>;
47 #interrupt-cells = <1>;
48 interrupt-controller;
49 };
50
43 apb { 51 apb {
44 #address-cells = <1>; 52 #address-cells = <1>;
45 #size-cells = <1>; 53 #size-cells = <1>;
@@ -50,30 +58,40 @@
50 serial@b2000000 { 58 serial@b2000000 {
51 compatible = "arm,pl011", "arm,primecell"; 59 compatible = "arm,pl011", "arm,primecell";
52 reg = <0xb2000000 0x1000>; 60 reg = <0xb2000000 0x1000>;
61 interrupts = <8>;
62 interrupt-parent = <&shirq>;
53 status = "disabled"; 63 status = "disabled";
54 }; 64 };
55 65
56 serial@b2080000 { 66 serial@b2080000 {
57 compatible = "arm,pl011", "arm,primecell"; 67 compatible = "arm,pl011", "arm,primecell";
58 reg = <0xb2080000 0x1000>; 68 reg = <0xb2080000 0x1000>;
69 interrupts = <9>;
70 interrupt-parent = <&shirq>;
59 status = "disabled"; 71 status = "disabled";
60 }; 72 };
61 73
62 serial@b2100000 { 74 serial@b2100000 {
63 compatible = "arm,pl011", "arm,primecell"; 75 compatible = "arm,pl011", "arm,primecell";
64 reg = <0xb2100000 0x1000>; 76 reg = <0xb2100000 0x1000>;
77 interrupts = <10>;
78 interrupt-parent = <&shirq>;
65 status = "disabled"; 79 status = "disabled";
66 }; 80 };
67 81
68 serial@b2180000 { 82 serial@b2180000 {
69 compatible = "arm,pl011", "arm,primecell"; 83 compatible = "arm,pl011", "arm,primecell";
70 reg = <0xb2180000 0x1000>; 84 reg = <0xb2180000 0x1000>;
85 interrupts = <11>;
86 interrupt-parent = <&shirq>;
71 status = "disabled"; 87 status = "disabled";
72 }; 88 };
73 89
74 serial@b2200000 { 90 serial@b2200000 {
75 compatible = "arm,pl011", "arm,primecell"; 91 compatible = "arm,pl011", "arm,primecell";
76 reg = <0xb2200000 0x1000>; 92 reg = <0xb2200000 0x1000>;
93 interrupts = <12>;
94 interrupt-parent = <&shirq>;
77 status = "disabled"; 95 status = "disabled";
78 }; 96 };
79 97
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index ad4bfc68ee05..fdedbb514102 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -76,20 +76,12 @@
76 st,function = "mii2"; 76 st,function = "mii2";
77 }; 77 };
78 pwm0_1 { 78 pwm0_1 {
79 st,pins = "pwm0_1_pin_14_15_grp"; 79 st,pins = "pwm0_1_pin_37_38_grp";
80 st,function = "pwm0_1"; 80 st,function = "pwm0_1";
81 }; 81 };
82 pwm2 {
83 st,pins = "pwm2_pin_13_grp";
84 st,function = "pwm2";
85 };
86 }; 82 };
87 }; 83 };
88 84
89 clcd@90000000 {
90 status = "okay";
91 };
92
93 dma@fc400000 { 85 dma@fc400000 {
94 status = "okay"; 86 status = "okay";
95 }; 87 };
@@ -103,6 +95,7 @@
103 }; 95 };
104 96
105 sdhci@70000000 { 97 sdhci@70000000 {
98 power-gpio = <&gpiopinctrl 61 1>;
106 status = "okay"; 99 status = "okay";
107 }; 100 };
108 101
@@ -122,15 +115,23 @@
122 }; 115 };
123 partition@10000 { 116 partition@10000 {
124 label = "u-boot"; 117 label = "u-boot";
125 reg = <0x10000 0x40000>; 118 reg = <0x10000 0x50000>;
119 };
120 partition@60000 {
121 label = "environment";
122 reg = <0x60000 0x10000>;
123 };
124 partition@70000 {
125 label = "dtb";
126 reg = <0x70000 0x10000>;
126 }; 127 };
127 partition@50000 { 128 partition@80000 {
128 label = "linux"; 129 label = "linux";
129 reg = <0x50000 0x2c0000>; 130 reg = <0x80000 0x310000>;
130 }; 131 };
131 partition@310000 { 132 partition@390000 {
132 label = "rootfs"; 133 label = "rootfs";
133 reg = <0x310000 0x4f0000>; 134 reg = <0x390000 0x0>;
134 }; 135 };
135 }; 136 };
136 }; 137 };
@@ -182,14 +183,20 @@
182 183
183 serial@d0000000 { 184 serial@d0000000 {
184 status = "okay"; 185 status = "okay";
186 pinctrl-names = "default";
187 pinctrl-0 = <>;
185 }; 188 };
186 189
187 serial@a3000000 { 190 serial@a3000000 {
188 status = "okay"; 191 status = "okay";
192 pinctrl-names = "default";
193 pinctrl-0 = <>;
189 }; 194 };
190 195
191 serial@a4000000 { 196 serial@a4000000 {
192 status = "okay"; 197 status = "okay";
198 pinctrl-names = "default";
199 pinctrl-0 = <>;
193 }; 200 };
194 201
195 wdt@fc880000 { 202 wdt@fc880000 {
diff --git a/arch/arm/boot/dts/spear320-hmi.dts b/arch/arm/boot/dts/spear320-hmi.dts
new file mode 100644
index 000000000000..3075d2d3a8be
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-hmi.dts
@@ -0,0 +1,305 @@
1/*
2 * DTS file for SPEAr320 Evaluation Baord
3 *
4 * Copyright 2012 Shiraz Hashim <shiraz.hashim@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear320.dtsi"
16
17/ {
18 model = "ST SPEAr320 HMI Board";
19 compatible = "st,spear320-hmi", "st,spear320";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@b3000000 {
29 st,pinmux-mode = <4>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 ssp0 {
39 st,pins = "ssp0_grp";
40 st,function = "ssp0";
41 };
42 uart0 {
43 st,pins = "uart0_grp";
44 st,function = "uart0";
45 };
46 clcd {
47 st,pins = "clcd_grp";
48 st,function = "clcd";
49 };
50 fsmc {
51 st,pins = "fsmc_8bit_grp";
52 st,function = "fsmc";
53 };
54 sdhci {
55 st,pins = "sdhci_cd_12_grp";
56 st,function = "sdhci";
57 };
58 i2s {
59 st,pins = "i2s_grp";
60 st,function = "i2s";
61 };
62 uart1 {
63 st,pins = "uart1_grp";
64 st,function = "uart1";
65 };
66 uart2 {
67 st,pins = "uart2_grp";
68 st,function = "uart2";
69 };
70 can0 {
71 st,pins = "can0_grp";
72 st,function = "can0";
73 };
74 can1 {
75 st,pins = "can1_grp";
76 st,function = "can1";
77 };
78 mii0_1 {
79 st,pins = "rmii0_1_grp";
80 st,function = "mii0_1";
81 };
82 pwm0_1 {
83 st,pins = "pwm0_1_pin_37_38_grp";
84 st,function = "pwm0_1";
85 };
86 pwm2 {
87 st,pins = "pwm2_pin_34_grp";
88 st,function = "pwm2";
89 };
90 };
91 };
92
93 clcd@90000000 {
94 status = "okay";
95 };
96
97 dma@fc400000 {
98 status = "okay";
99 };
100
101 ehci@e1800000 {
102 status = "okay";
103 };
104
105 fsmc: flash@4c000000 {
106 status = "okay";
107
108 partition@0 {
109 label = "xloader";
110 reg = <0x0 0x80000>;
111 };
112 partition@80000 {
113 label = "u-boot";
114 reg = <0x80000 0x140000>;
115 };
116 partition@1C0000 {
117 label = "environment";
118 reg = <0x1C0000 0x40000>;
119 };
120 partition@200000 {
121 label = "dtb";
122 reg = <0x200000 0x40000>;
123 };
124 partition@240000 {
125 label = "linux";
126 reg = <0x240000 0xC00000>;
127 };
128 partition@E40000 {
129 label = "rootfs";
130 reg = <0xE40000 0x0>;
131 };
132 };
133
134 gpio_keys {
135 compatible = "gpio-keys";
136 #address-cells = <1>;
137 #size-cells = <0>;
138
139 button@1 {
140 label = "user button 1";
141 linux,code = <0x100>;
142 gpios = <&stmpegpio 3 0x4>;
143 debounce-interval = <20>;
144 gpio-key,wakeup = <1>;
145 };
146
147 button@2 {
148 label = "user button 2";
149 linux,code = <0x200>;
150 gpios = <&stmpegpio 2 0x4>;
151 debounce-interval = <20>;
152 gpio-key,wakeup = <1>;
153 };
154 };
155
156 ohci@e1900000 {
157 status = "okay";
158 };
159
160 ohci@e2100000 {
161 status = "okay";
162 };
163
164 pwm: pwm@a8000000 {
165 status = "okay";
166 };
167
168 sdhci@70000000 {
169 power-gpio = <&gpiopinctrl 50 1>;
170 power_always_enb;
171 status = "okay";
172 };
173
174 smi: flash@fc000000 {
175 status = "okay";
176 clock-rate=<50000000>;
177
178 flash@f8000000 {
179 #address-cells = <1>;
180 #size-cells = <1>;
181 reg = <0xf8000000 0x800000>;
182 st,smi-fast-mode;
183
184 partition@0 {
185 label = "xloader";
186 reg = <0x0 0x10000>;
187 };
188 partition@10000 {
189 label = "u-boot";
190 reg = <0x10000 0x50000>;
191 };
192 partition@60000 {
193 label = "environment";
194 reg = <0x60000 0x10000>;
195 };
196 partition@70000 {
197 label = "dtb";
198 reg = <0x70000 0x10000>;
199 };
200 partition@80000 {
201 label = "linux";
202 reg = <0x80000 0x310000>;
203 };
204 partition@390000 {
205 label = "rootfs";
206 reg = <0x390000 0x0>;
207 };
208 };
209 };
210
211 spi0: spi@d0100000 {
212 status = "okay";
213 };
214
215 spi1: spi@a5000000 {
216 status = "okay";
217 };
218
219 spi2: spi@a6000000 {
220 status = "okay";
221 };
222
223 usbd@e1100000 {
224 status = "okay";
225 };
226
227 apb {
228 gpio0: gpio@fc980000 {
229 status = "okay";
230 };
231
232 gpio@b3000000 {
233 status = "okay";
234 };
235
236 i2c0: i2c@d0180000 {
237 status = "okay";
238
239 stmpe811@41 {
240 compatible = "st,stmpe811";
241 #address-cells = <1>;
242 #size-cells = <0>;
243 reg = <0x41>;
244 irq-over-gpio;
245 irq-gpios = <&gpiopinctrl 29 0x4>;
246 id = <0>;
247 blocks = <0x5>;
248 irq-trigger = <0x1>;
249
250 stmpegpio: stmpe-gpio {
251 compatible = "stmpe,gpio";
252 reg = <0>;
253 gpio-controller;
254 #gpio-cells = <2>;
255 gpio,norequest-mask = <0xF3>;
256 };
257
258 stmpe610-ts {
259 compatible = "stmpe,ts";
260 reg = <0>;
261 ts,sample-time = <4>;
262 ts,mod-12b = <1>;
263 ts,ref-sel = <0>;
264 ts,adc-freq = <1>;
265 ts,ave-ctrl = <1>;
266 ts,touch-det-delay = <3>;
267 ts,settling = <4>;
268 ts,fraction-z = <7>;
269 ts,i-drive = <1>;
270 };
271 };
272 };
273
274 i2c1: i2c@a7000000 {
275 status = "okay";
276 };
277
278 rtc@fc900000 {
279 status = "okay";
280 };
281
282 serial@d0000000 {
283 status = "okay";
284 pinctrl-names = "default";
285 pinctrl-0 = <>;
286 };
287
288 serial@a3000000 {
289 status = "okay";
290 pinctrl-names = "default";
291 pinctrl-0 = <>;
292 };
293
294 serial@a4000000 {
295 status = "okay";
296 pinctrl-names = "default";
297 pinctrl-0 = <>;
298 };
299
300 wdt@fc880000 {
301 status = "okay";
302 };
303 };
304 };
305};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index 67d7ada71275..c056a84deabf 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -28,9 +28,10 @@
28 }; 28 };
29 29
30 clcd@90000000 { 30 clcd@90000000 {
31 compatible = "arm,clcd-pl110", "arm,primecell"; 31 compatible = "arm,pl110", "arm,primecell";
32 reg = <0x90000000 0x1000>; 32 reg = <0x90000000 0x1000>;
33 interrupts = <33>; 33 interrupts = <8>;
34 interrupt-parent = <&shirq>;
34 status = "disabled"; 35 status = "disabled";
35 }; 36 };
36 37
@@ -49,27 +50,51 @@
49 sdhci@70000000 { 50 sdhci@70000000 {
50 compatible = "st,sdhci-spear"; 51 compatible = "st,sdhci-spear";
51 reg = <0x70000000 0x100>; 52 reg = <0x70000000 0x100>;
52 interrupts = <29>; 53 interrupts = <10>;
54 interrupt-parent = <&shirq>;
53 status = "disabled"; 55 status = "disabled";
54 }; 56 };
55 57
58 shirq: interrupt-controller@0xb3000000 {
59 compatible = "st,spear320-shirq";
60 reg = <0xb3000000 0x1000>;
61 interrupts = <30 28 29 1>;
62 #interrupt-cells = <1>;
63 interrupt-controller;
64 };
65
56 spi1: spi@a5000000 { 66 spi1: spi@a5000000 {
57 compatible = "arm,pl022", "arm,primecell"; 67 compatible = "arm,pl022", "arm,primecell";
58 reg = <0xa5000000 0x1000>; 68 reg = <0xa5000000 0x1000>;
69 interrupts = <15>;
70 interrupt-parent = <&shirq>;
71 #address-cells = <1>;
72 #size-cells = <0>;
59 status = "disabled"; 73 status = "disabled";
60 }; 74 };
61 75
62 spi2: spi@a6000000 { 76 spi2: spi@a6000000 {
63 compatible = "arm,pl022", "arm,primecell"; 77 compatible = "arm,pl022", "arm,primecell";
64 reg = <0xa6000000 0x1000>; 78 reg = <0xa6000000 0x1000>;
79 interrupts = <16>;
80 interrupt-parent = <&shirq>;
81 #address-cells = <1>;
82 #size-cells = <0>;
65 status = "disabled"; 83 status = "disabled";
66 }; 84 };
67 85
86 pwm: pwm@a8000000 {
87 compatible ="st,spear-pwm";
88 reg = <0xa8000000 0x1000>;
89 #pwm-cells = <2>;
90 status = "disabled";
91 };
92
68 apb { 93 apb {
69 #address-cells = <1>; 94 #address-cells = <1>;
70 #size-cells = <1>; 95 #size-cells = <1>;
71 compatible = "simple-bus"; 96 compatible = "simple-bus";
72 ranges = <0xa0000000 0xa0000000 0x10000000 97 ranges = <0xa0000000 0xa0000000 0x20000000
73 0xd0000000 0xd0000000 0x30000000>; 98 0xd0000000 0xd0000000 0x30000000>;
74 99
75 i2c1: i2c@a7000000 { 100 i2c1: i2c@a7000000 {
@@ -77,18 +102,24 @@
77 #size-cells = <0>; 102 #size-cells = <0>;
78 compatible = "snps,designware-i2c"; 103 compatible = "snps,designware-i2c";
79 reg = <0xa7000000 0x1000>; 104 reg = <0xa7000000 0x1000>;
105 interrupts = <21>;
106 interrupt-parent = <&shirq>;
80 status = "disabled"; 107 status = "disabled";
81 }; 108 };
82 109
83 serial@a3000000 { 110 serial@a3000000 {
84 compatible = "arm,pl011", "arm,primecell"; 111 compatible = "arm,pl011", "arm,primecell";
85 reg = <0xa3000000 0x1000>; 112 reg = <0xa3000000 0x1000>;
113 interrupts = <13>;
114 interrupt-parent = <&shirq>;
86 status = "disabled"; 115 status = "disabled";
87 }; 116 };
88 117
89 serial@a4000000 { 118 serial@a4000000 {
90 compatible = "arm,pl011", "arm,primecell"; 119 compatible = "arm,pl011", "arm,primecell";
91 reg = <0xa4000000 0x1000>; 120 reg = <0xa4000000 0x1000>;
121 interrupts = <14>;
122 interrupt-parent = <&shirq>;
92 status = "disabled"; 123 status = "disabled";
93 }; 124 };
94 125
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index 3a8bb5736928..c2a852d43c48 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -53,6 +53,7 @@
53 reg = <0xe0800000 0x8000>; 53 reg = <0xe0800000 0x8000>;
54 interrupts = <23 22>; 54 interrupts = <23 22>;
55 interrupt-names = "macirq", "eth_wake_irq"; 55 interrupt-names = "macirq", "eth_wake_irq";
56 phy-mode = "mii";
56 status = "disabled"; 57 status = "disabled";
57 }; 58 };
58 59
@@ -69,6 +70,8 @@
69 compatible = "arm,pl022", "arm,primecell"; 70 compatible = "arm,pl022", "arm,primecell";
70 reg = <0xd0100000 0x1000>; 71 reg = <0xd0100000 0x1000>;
71 interrupts = <20>; 72 interrupts = <20>;
73 #address-cells = <1>;
74 #size-cells = <0>;
72 status = "disabled"; 75 status = "disabled";
73 }; 76 };
74 77
@@ -120,7 +123,7 @@
120 }; 123 };
121 124
122 rtc@fc900000 { 125 rtc@fc900000 {
123 compatible = "st,spear-rtc"; 126 compatible = "st,spear600-rtc";
124 reg = <0xfc900000 0x1000>; 127 reg = <0xfc900000 0x1000>;
125 interrupts = <10>; 128 interrupts = <10>;
126 status = "disabled"; 129 status = "disabled";
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 1119c22c9a82..d865a891776d 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,15 +24,35 @@
24 }; 24 };
25 25
26 ahb { 26 ahb {
27 clcd@fc200000 {
28 status = "okay";
29 };
30
27 dma@fc400000 { 31 dma@fc400000 {
28 status = "okay"; 32 status = "okay";
29 }; 33 };
30 34
35 ehci@e1800000 {
36 status = "okay";
37 };
38
39 ehci@e2000000 {
40 status = "okay";
41 };
42
31 gmac: ethernet@e0800000 { 43 gmac: ethernet@e0800000 {
32 phy-mode = "gmii"; 44 phy-mode = "gmii";
33 status = "okay"; 45 status = "okay";
34 }; 46 };
35 47
48 ohci@e1900000 {
49 status = "okay";
50 };
51
52 ohci@e2100000 {
53 status = "okay";
54 };
55
36 smi: flash@fc000000 { 56 smi: flash@fc000000 {
37 status = "okay"; 57 status = "okay";
38 clock-rate=<50000000>; 58 clock-rate=<50000000>;
@@ -49,15 +69,23 @@
49 }; 69 };
50 partition@10000 { 70 partition@10000 {
51 label = "u-boot"; 71 label = "u-boot";
52 reg = <0x10000 0x40000>; 72 reg = <0x10000 0x50000>;
53 }; 73 };
54 partition@50000 { 74 partition@60000 {
75 label = "environment";
76 reg = <0x60000 0x10000>;
77 };
78 partition@70000 {
79 label = "dtb";
80 reg = <0x70000 0x10000>;
81 };
82 partition@80000 {
55 label = "linux"; 83 label = "linux";
56 reg = <0x50000 0x2c0000>; 84 reg = <0x80000 0x310000>;
57 }; 85 };
58 partition@310000 { 86 partition@390000 {
59 label = "rootfs"; 87 label = "rootfs";
60 reg = <0x310000 0x4f0000>; 88 reg = <0x390000 0x0>;
61 }; 89 };
62 }; 90 };
63 }; 91 };
@@ -65,10 +93,18 @@
65 apb { 93 apb {
66 serial@d0000000 { 94 serial@d0000000 {
67 status = "okay"; 95 status = "okay";
96 pinctrl-names = "default";
97 pinctrl-0 = <>;
68 }; 98 };
69 99
70 serial@d0080000 { 100 serial@d0080000 {
71 status = "okay"; 101 status = "okay";
102 pinctrl-names = "default";
103 pinctrl-0 = <>;
104 };
105
106 rtc@fc900000 {
107 status = "okay";
72 }; 108 };
73 109
74 i2c@d0200000 { 110 i2c@d0200000 {
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index a3c36e47d7ef..e051dde5181f 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
45 #interrupt-cells = <1>; 45 #interrupt-cells = <1>;
46 }; 46 };
47 47
48 clcd@fc200000 {
49 compatible = "arm,pl110", "arm,primecell";
50 reg = <0xfc200000 0x1000>;
51 interrupt-parent = <&vic1>;
52 interrupts = <12>;
53 status = "disabled";
54 };
55
48 dma@fc400000 { 56 dma@fc400000 {
49 compatible = "arm,pl080", "arm,primecell"; 57 compatible = "arm,pl080", "arm,primecell";
50 reg = <0xfc400000 0x1000>; 58 reg = <0xfc400000 0x1000>;
@@ -59,6 +67,7 @@
59 interrupt-parent = <&vic1>; 67 interrupt-parent = <&vic1>;
60 interrupts = <24 23>; 68 interrupts = <24 23>;
61 interrupt-names = "macirq", "eth_wake_irq"; 69 interrupt-names = "macirq", "eth_wake_irq";
70 phy-mode = "gmii";
62 status = "disabled"; 71 status = "disabled";
63 }; 72 };
64 73
@@ -178,6 +187,13 @@
178 status = "disabled"; 187 status = "disabled";
179 }; 188 };
180 189
190 rtc@fc900000 {
191 compatible = "st,spear600-rtc";
192 reg = <0xfc900000 0x1000>;
193 interrupts = <10>;
194 status = "disabled";
195 };
196
181 timer@f0000000 { 197 timer@f0000000 {
182 compatible = "st,spear-timer"; 198 compatible = "st,spear-timer";
183 reg = <0xf0000000 0x400>; 199 reg = <0xf0000000 0x400>;
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index 07d90acc92c8..7cfa6818865a 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -47,14 +47,6 @@
47#define DMAC1_BASE UL(0xEB000000) 47#define DMAC1_BASE UL(0xEB000000)
48#define MCIF_CF_BASE UL(0xB2800000) 48#define MCIF_CF_BASE UL(0xB2800000)
49 49
50/* Devices present in SPEAr1310 */
51#ifdef CONFIG_MACH_SPEAR1310
52#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000)
53#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000)
54#define SPEAR1310_RAS_BASE UL(0xD8400000)
55#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
56#endif /* CONFIG_MACH_SPEAR1310 */
57
58/* Debug uart for linux, will be used for debug and uncompress messages */ 50/* Debug uart for linux, will be used for debug and uncompress messages */
59#define SPEAR_DBG_UART_BASE UART_BASE 51#define SPEAR_DBG_UART_BASE UART_BASE
60#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE 52#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
index 9fbbfc5650aa..02f4724bb0d4 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -15,6 +15,7 @@
15 15
16#include <linux/amba/pl022.h> 16#include <linux/amba/pl022.h>
17#include <linux/of_platform.h> 17#include <linux/of_platform.h>
18#include <linux/pata_arasan_cf_data.h>
18#include <asm/hardware/gic.h> 19#include <asm/hardware/gic.h>
19#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
20#include <asm/mach/map.h> 21#include <asm/mach/map.h>
@@ -27,16 +28,25 @@
27#define SPEAR1310_SATA1_BASE UL(0xB1800000) 28#define SPEAR1310_SATA1_BASE UL(0xB1800000)
28#define SPEAR1310_SATA2_BASE UL(0xB4000000) 29#define SPEAR1310_SATA2_BASE UL(0xB4000000)
29 30
31#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000)
32#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000)
33#define SPEAR1310_RAS_BASE UL(0xD8400000)
34#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
35
36static struct arasan_cf_pdata cf_pdata = {
37 .cf_if_clk = CF_IF_CLK_166M,
38 .quirk = CF_BROKEN_UDMA,
39 .dma_priv = &cf_dma_priv,
40};
41
30/* ssp device registration */ 42/* ssp device registration */
31static struct pl022_ssp_controller ssp1_plat_data = { 43static struct pl022_ssp_controller ssp1_plat_data = {
32 .bus_id = 0,
33 .enable_dma = 0, 44 .enable_dma = 0,
34 .num_chipselect = 3,
35}; 45};
36 46
37/* Add SPEAr1310 auxdata to pass platform data */ 47/* Add SPEAr1310 auxdata to pass platform data */
38static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = { 48static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
39 OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv), 49 OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_pdata),
40 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data), 50 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
41 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data), 51 OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
42 OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data), 52 OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index 5633d698f1e1..c4af775a8451 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -57,12 +57,10 @@ static struct dw_dma_slave ssp_dma_param[] = {
57}; 57};
58 58
59struct pl022_ssp_controller pl022_plat_data = { 59struct pl022_ssp_controller pl022_plat_data = {
60 .bus_id = 0,
61 .enable_dma = 1, 60 .enable_dma = 1,
62 .dma_filter = dw_dma_filter, 61 .dma_filter = dw_dma_filter,
63 .dma_rx_param = &ssp_dma_param[1], 62 .dma_rx_param = &ssp_dma_param[1],
64 .dma_tx_param = &ssp_dma_param[0], 63 .dma_tx_param = &ssp_dma_param[0],
65 .num_chipselect = 3,
66}; 64};
67 65
68/* CF device registration */ 66/* CF device registration */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 803de76f5f36..f95e5b2b6686 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -14,14 +14,6 @@
14#ifndef __MACH_IRQS_H 14#ifndef __MACH_IRQS_H
15#define __MACH_IRQS_H 15#define __MACH_IRQS_H
16 16
17/* FIXME: probe all these from DT */ 17#define NR_IRQS 256
18#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
19#define SPEAR3XX_IRQ_GEN_RAS_1 28
20#define SPEAR3XX_IRQ_GEN_RAS_2 29
21#define SPEAR3XX_IRQ_GEN_RAS_3 30
22#define SPEAR3XX_IRQ_VIC_END 32
23#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
24
25#define NR_IRQS 160
26 18
27#endif /* __MACH_IRQS_H */ 19#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 6ec300549960..a69cbfdb07ee 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -17,102 +17,9 @@
17#include <linux/of_platform.h> 17#include <linux/of_platform.h>
18#include <asm/hardware/vic.h> 18#include <asm/hardware/vic.h>
19#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
20#include <plat/shirq.h>
21#include <mach/generic.h> 20#include <mach/generic.h>
22#include <mach/spear.h> 21#include <mach/spear.h>
23 22
24/* Base address of various IPs */
25#define SPEAR300_TELECOM_BASE UL(0x50000000)
26
27/* Interrupt registers offsets and masks */
28#define SPEAR300_INT_ENB_MASK_REG 0x54
29#define SPEAR300_INT_STS_MASK_REG 0x58
30#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
31#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
32#define SPEAR300_I2S_IRQ_MASK (1 << 2)
33#define SPEAR300_TDM_IRQ_MASK (1 << 3)
34#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
35#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
36#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
37#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
38#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
39
40#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
41
42#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
43
44
45/* SPEAr300 Virtual irq definitions */
46/* IRQs sharing IRQ_GEN_RAS_1 */
47#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
48#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
49#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
50#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
51#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
52#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
53#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
54#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
55#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
56
57/* IRQs sharing IRQ_GEN_RAS_3 */
58#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
59
60/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
61#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
62
63/* spear3xx shared irq */
64static struct shirq_dev_config shirq_ras1_config[] = {
65 {
66 .virq = SPEAR300_VIRQ_IT_PERS_S,
67 .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
68 .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
69 }, {
70 .virq = SPEAR300_VIRQ_IT_CHANGE_S,
71 .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
72 .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
73 }, {
74 .virq = SPEAR300_VIRQ_I2S,
75 .enb_mask = SPEAR300_I2S_IRQ_MASK,
76 .status_mask = SPEAR300_I2S_IRQ_MASK,
77 }, {
78 .virq = SPEAR300_VIRQ_TDM,
79 .enb_mask = SPEAR300_TDM_IRQ_MASK,
80 .status_mask = SPEAR300_TDM_IRQ_MASK,
81 }, {
82 .virq = SPEAR300_VIRQ_CAMERA_L,
83 .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK,
84 .status_mask = SPEAR300_CAMERA_L_IRQ_MASK,
85 }, {
86 .virq = SPEAR300_VIRQ_CAMERA_F,
87 .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK,
88 .status_mask = SPEAR300_CAMERA_F_IRQ_MASK,
89 }, {
90 .virq = SPEAR300_VIRQ_CAMERA_V,
91 .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK,
92 .status_mask = SPEAR300_CAMERA_V_IRQ_MASK,
93 }, {
94 .virq = SPEAR300_VIRQ_KEYBOARD,
95 .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK,
96 .status_mask = SPEAR300_KEYBOARD_IRQ_MASK,
97 }, {
98 .virq = SPEAR300_VIRQ_GPIO1,
99 .enb_mask = SPEAR300_GPIO1_IRQ_MASK,
100 .status_mask = SPEAR300_GPIO1_IRQ_MASK,
101 },
102};
103
104static struct spear_shirq shirq_ras1 = {
105 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
106 .dev_config = shirq_ras1_config,
107 .dev_count = ARRAY_SIZE(shirq_ras1_config),
108 .regs = {
109 .enb_reg = SPEAR300_INT_ENB_MASK_REG,
110 .status_reg = SPEAR300_INT_STS_MASK_REG,
111 .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK,
112 .clear_reg = -1,
113 },
114};
115
116/* DMAC platform data's slave info */ 23/* DMAC platform data's slave info */
117struct pl08x_channel_data spear300_dma_info[] = { 24struct pl08x_channel_data spear300_dma_info[] = {
118 { 25 {
@@ -285,21 +192,11 @@ static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
285 192
286static void __init spear300_dt_init(void) 193static void __init spear300_dt_init(void)
287{ 194{
288 int ret;
289
290 pl080_plat_data.slave_channels = spear300_dma_info; 195 pl080_plat_data.slave_channels = spear300_dma_info;
291 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info); 196 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
292 197
293 of_platform_populate(NULL, of_default_bus_match_table, 198 of_platform_populate(NULL, of_default_bus_match_table,
294 spear300_auxdata_lookup, NULL); 199 spear300_auxdata_lookup, NULL);
295
296 /* shared irq registration */
297 shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
298 if (shirq_ras1.regs.base) {
299 ret = spear_shirq_register(&shirq_ras1);
300 if (ret)
301 pr_err("Error registering Shared IRQ\n");
302 }
303} 200}
304 201
305static const char * const spear300_dt_board_compat[] = { 202static const char * const spear300_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 1d0e435b9045..b963ebb10b56 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -18,7 +18,6 @@
18#include <linux/of_platform.h> 18#include <linux/of_platform.h>
19#include <asm/hardware/vic.h> 19#include <asm/hardware/vic.h>
20#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
21#include <plat/shirq.h>
22#include <mach/generic.h> 21#include <mach/generic.h>
23#include <mach/spear.h> 22#include <mach/spear.h>
24 23
@@ -27,176 +26,6 @@
27#define SPEAR310_UART3_BASE UL(0xB2100000) 26#define SPEAR310_UART3_BASE UL(0xB2100000)
28#define SPEAR310_UART4_BASE UL(0xB2180000) 27#define SPEAR310_UART4_BASE UL(0xB2180000)
29#define SPEAR310_UART5_BASE UL(0xB2200000) 28#define SPEAR310_UART5_BASE UL(0xB2200000)
30#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
31
32/* Interrupt registers offsets and masks */
33#define SPEAR310_INT_STS_MASK_REG 0x04
34#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
35#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
36#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
37#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
38#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
39#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
40#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
41#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
42#define SPEAR310_UART1_IRQ_MASK (1 << 8)
43#define SPEAR310_UART2_IRQ_MASK (1 << 9)
44#define SPEAR310_UART3_IRQ_MASK (1 << 10)
45#define SPEAR310_UART4_IRQ_MASK (1 << 11)
46#define SPEAR310_UART5_IRQ_MASK (1 << 12)
47#define SPEAR310_EMI_IRQ_MASK (1 << 13)
48#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
49#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
50#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
51
52#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
53#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
54#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
55#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
56
57/* SPEAr310 Virtual irq definitions */
58/* IRQs sharing IRQ_GEN_RAS_1 */
59#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
60#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
61#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
62#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
63#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
64#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
65#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
66#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
67
68/* IRQs sharing IRQ_GEN_RAS_2 */
69#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
70#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
71#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
72#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
73#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
74
75/* IRQs sharing IRQ_GEN_RAS_3 */
76#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
77#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
78
79/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
80#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
81#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
82#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
83
84
85/* spear3xx shared irq */
86static struct shirq_dev_config shirq_ras1_config[] = {
87 {
88 .virq = SPEAR310_VIRQ_SMII0,
89 .status_mask = SPEAR310_SMII0_IRQ_MASK,
90 }, {
91 .virq = SPEAR310_VIRQ_SMII1,
92 .status_mask = SPEAR310_SMII1_IRQ_MASK,
93 }, {
94 .virq = SPEAR310_VIRQ_SMII2,
95 .status_mask = SPEAR310_SMII2_IRQ_MASK,
96 }, {
97 .virq = SPEAR310_VIRQ_SMII3,
98 .status_mask = SPEAR310_SMII3_IRQ_MASK,
99 }, {
100 .virq = SPEAR310_VIRQ_WAKEUP_SMII0,
101 .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
102 }, {
103 .virq = SPEAR310_VIRQ_WAKEUP_SMII1,
104 .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
105 }, {
106 .virq = SPEAR310_VIRQ_WAKEUP_SMII2,
107 .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
108 }, {
109 .virq = SPEAR310_VIRQ_WAKEUP_SMII3,
110 .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
111 },
112};
113
114static struct spear_shirq shirq_ras1 = {
115 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
116 .dev_config = shirq_ras1_config,
117 .dev_count = ARRAY_SIZE(shirq_ras1_config),
118 .regs = {
119 .enb_reg = -1,
120 .status_reg = SPEAR310_INT_STS_MASK_REG,
121 .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
122 .clear_reg = -1,
123 },
124};
125
126static struct shirq_dev_config shirq_ras2_config[] = {
127 {
128 .virq = SPEAR310_VIRQ_UART1,
129 .status_mask = SPEAR310_UART1_IRQ_MASK,
130 }, {
131 .virq = SPEAR310_VIRQ_UART2,
132 .status_mask = SPEAR310_UART2_IRQ_MASK,
133 }, {
134 .virq = SPEAR310_VIRQ_UART3,
135 .status_mask = SPEAR310_UART3_IRQ_MASK,
136 }, {
137 .virq = SPEAR310_VIRQ_UART4,
138 .status_mask = SPEAR310_UART4_IRQ_MASK,
139 }, {
140 .virq = SPEAR310_VIRQ_UART5,
141 .status_mask = SPEAR310_UART5_IRQ_MASK,
142 },
143};
144
145static struct spear_shirq shirq_ras2 = {
146 .irq = SPEAR3XX_IRQ_GEN_RAS_2,
147 .dev_config = shirq_ras2_config,
148 .dev_count = ARRAY_SIZE(shirq_ras2_config),
149 .regs = {
150 .enb_reg = -1,
151 .status_reg = SPEAR310_INT_STS_MASK_REG,
152 .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
153 .clear_reg = -1,
154 },
155};
156
157static struct shirq_dev_config shirq_ras3_config[] = {
158 {
159 .virq = SPEAR310_VIRQ_EMI,
160 .status_mask = SPEAR310_EMI_IRQ_MASK,
161 },
162};
163
164static struct spear_shirq shirq_ras3 = {
165 .irq = SPEAR3XX_IRQ_GEN_RAS_3,
166 .dev_config = shirq_ras3_config,
167 .dev_count = ARRAY_SIZE(shirq_ras3_config),
168 .regs = {
169 .enb_reg = -1,
170 .status_reg = SPEAR310_INT_STS_MASK_REG,
171 .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
172 .clear_reg = -1,
173 },
174};
175
176static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
177 {
178 .virq = SPEAR310_VIRQ_TDM_HDLC,
179 .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
180 }, {
181 .virq = SPEAR310_VIRQ_RS485_0,
182 .status_mask = SPEAR310_RS485_0_IRQ_MASK,
183 }, {
184 .virq = SPEAR310_VIRQ_RS485_1,
185 .status_mask = SPEAR310_RS485_1_IRQ_MASK,
186 },
187};
188
189static struct spear_shirq shirq_intrcomm_ras = {
190 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
191 .dev_config = shirq_intrcomm_ras_config,
192 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
193 .regs = {
194 .enb_reg = -1,
195 .status_reg = SPEAR310_INT_STS_MASK_REG,
196 .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
197 .clear_reg = -1,
198 },
199};
200 29
201/* DMAC platform data's slave info */ 30/* DMAC platform data's slave info */
202struct pl08x_channel_data spear310_dma_info[] = { 31struct pl08x_channel_data spear310_dma_info[] = {
@@ -405,42 +234,11 @@ static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
405 234
406static void __init spear310_dt_init(void) 235static void __init spear310_dt_init(void)
407{ 236{
408 void __iomem *base;
409 int ret;
410
411 pl080_plat_data.slave_channels = spear310_dma_info; 237 pl080_plat_data.slave_channels = spear310_dma_info;
412 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); 238 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
413 239
414 of_platform_populate(NULL, of_default_bus_match_table, 240 of_platform_populate(NULL, of_default_bus_match_table,
415 spear310_auxdata_lookup, NULL); 241 spear310_auxdata_lookup, NULL);
416
417 /* shared irq registration */
418 base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
419 if (base) {
420 /* shirq 1 */
421 shirq_ras1.regs.base = base;
422 ret = spear_shirq_register(&shirq_ras1);
423 if (ret)
424 pr_err("Error registering Shared IRQ 1\n");
425
426 /* shirq 2 */
427 shirq_ras2.regs.base = base;
428 ret = spear_shirq_register(&shirq_ras2);
429 if (ret)
430 pr_err("Error registering Shared IRQ 2\n");
431
432 /* shirq 3 */
433 shirq_ras3.regs.base = base;
434 ret = spear_shirq_register(&shirq_ras3);
435 if (ret)
436 pr_err("Error registering Shared IRQ 3\n");
437
438 /* shirq 4 */
439 shirq_intrcomm_ras.regs.base = base;
440 ret = spear_shirq_register(&shirq_intrcomm_ras);
441 if (ret)
442 pr_err("Error registering Shared IRQ 4\n");
443 }
444} 242}
445 243
446static const char * const spear310_dt_board_compat[] = { 244static const char * const spear310_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index fd823c624575..66e3a0c33e75 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -19,7 +19,6 @@
19#include <linux/of_platform.h> 19#include <linux/of_platform.h>
20#include <asm/hardware/vic.h> 20#include <asm/hardware/vic.h>
21#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
22#include <plat/shirq.h>
23#include <mach/generic.h> 22#include <mach/generic.h>
24#include <mach/spear.h> 23#include <mach/spear.h>
25 24
@@ -28,184 +27,6 @@
28#define SPEAR320_SSP0_BASE UL(0xA5000000) 27#define SPEAR320_SSP0_BASE UL(0xA5000000)
29#define SPEAR320_SSP1_BASE UL(0xA6000000) 28#define SPEAR320_SSP1_BASE UL(0xA6000000)
30 29
31/* Interrupt registers offsets and masks */
32#define SPEAR320_INT_STS_MASK_REG 0x04
33#define SPEAR320_INT_CLR_MASK_REG 0x04
34#define SPEAR320_INT_ENB_MASK_REG 0x08
35#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
36#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
37#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
38#define SPEAR320_EMI_IRQ_MASK (1 << 7)
39#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
40#define SPEAR320_SPP_IRQ_MASK (1 << 9)
41#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
42#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
43#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
44#define SPEAR320_UART1_IRQ_MASK (1 << 13)
45#define SPEAR320_UART2_IRQ_MASK (1 << 14)
46#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
47#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
48#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
49#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
50#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
51#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
52#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
53
54#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
55#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
56#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
57
58/* SPEAr320 Virtual irq definitions */
59/* IRQs sharing IRQ_GEN_RAS_1 */
60#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
61#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
62#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
63
64/* IRQs sharing IRQ_GEN_RAS_2 */
65#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
66
67/* IRQs sharing IRQ_GEN_RAS_3 */
68#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
69#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
70#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
71
72/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
73#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
74#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
75#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
76#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
77#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
78#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
79#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
80#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
81#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
82#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
83#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
84
85/* spear3xx shared irq */
86static struct shirq_dev_config shirq_ras1_config[] = {
87 {
88 .virq = SPEAR320_VIRQ_EMI,
89 .status_mask = SPEAR320_EMI_IRQ_MASK,
90 .clear_mask = SPEAR320_EMI_IRQ_MASK,
91 }, {
92 .virq = SPEAR320_VIRQ_CLCD,
93 .status_mask = SPEAR320_CLCD_IRQ_MASK,
94 .clear_mask = SPEAR320_CLCD_IRQ_MASK,
95 }, {
96 .virq = SPEAR320_VIRQ_SPP,
97 .status_mask = SPEAR320_SPP_IRQ_MASK,
98 .clear_mask = SPEAR320_SPP_IRQ_MASK,
99 },
100};
101
102static struct spear_shirq shirq_ras1 = {
103 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
104 .dev_config = shirq_ras1_config,
105 .dev_count = ARRAY_SIZE(shirq_ras1_config),
106 .regs = {
107 .enb_reg = -1,
108 .status_reg = SPEAR320_INT_STS_MASK_REG,
109 .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
110 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
111 .reset_to_clear = 1,
112 },
113};
114
115static struct shirq_dev_config shirq_ras3_config[] = {
116 {
117 .virq = SPEAR320_VIRQ_PLGPIO,
118 .enb_mask = SPEAR320_GPIO_IRQ_MASK,
119 .status_mask = SPEAR320_GPIO_IRQ_MASK,
120 .clear_mask = SPEAR320_GPIO_IRQ_MASK,
121 }, {
122 .virq = SPEAR320_VIRQ_I2S_PLAY,
123 .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
124 .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
125 .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
126 }, {
127 .virq = SPEAR320_VIRQ_I2S_REC,
128 .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
129 .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
130 .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
131 },
132};
133
134static struct spear_shirq shirq_ras3 = {
135 .irq = SPEAR3XX_IRQ_GEN_RAS_3,
136 .dev_config = shirq_ras3_config,
137 .dev_count = ARRAY_SIZE(shirq_ras3_config),
138 .regs = {
139 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
140 .reset_to_enb = 1,
141 .status_reg = SPEAR320_INT_STS_MASK_REG,
142 .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
143 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
144 .reset_to_clear = 1,
145 },
146};
147
148static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
149 {
150 .virq = SPEAR320_VIRQ_CANU,
151 .status_mask = SPEAR320_CAN_U_IRQ_MASK,
152 .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
153 }, {
154 .virq = SPEAR320_VIRQ_CANL,
155 .status_mask = SPEAR320_CAN_L_IRQ_MASK,
156 .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
157 }, {
158 .virq = SPEAR320_VIRQ_UART1,
159 .status_mask = SPEAR320_UART1_IRQ_MASK,
160 .clear_mask = SPEAR320_UART1_IRQ_MASK,
161 }, {
162 .virq = SPEAR320_VIRQ_UART2,
163 .status_mask = SPEAR320_UART2_IRQ_MASK,
164 .clear_mask = SPEAR320_UART2_IRQ_MASK,
165 }, {
166 .virq = SPEAR320_VIRQ_SSP1,
167 .status_mask = SPEAR320_SSP1_IRQ_MASK,
168 .clear_mask = SPEAR320_SSP1_IRQ_MASK,
169 }, {
170 .virq = SPEAR320_VIRQ_SSP2,
171 .status_mask = SPEAR320_SSP2_IRQ_MASK,
172 .clear_mask = SPEAR320_SSP2_IRQ_MASK,
173 }, {
174 .virq = SPEAR320_VIRQ_SMII0,
175 .status_mask = SPEAR320_SMII0_IRQ_MASK,
176 .clear_mask = SPEAR320_SMII0_IRQ_MASK,
177 }, {
178 .virq = SPEAR320_VIRQ_MII1_SMII1,
179 .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
180 .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
181 }, {
182 .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
183 .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
184 .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
185 }, {
186 .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
187 .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
188 .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
189 }, {
190 .virq = SPEAR320_VIRQ_I2C1,
191 .status_mask = SPEAR320_I2C1_IRQ_MASK,
192 .clear_mask = SPEAR320_I2C1_IRQ_MASK,
193 },
194};
195
196static struct spear_shirq shirq_intrcomm_ras = {
197 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
198 .dev_config = shirq_intrcomm_ras_config,
199 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
200 .regs = {
201 .enb_reg = -1,
202 .status_reg = SPEAR320_INT_STS_MASK_REG,
203 .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
204 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
205 .reset_to_clear = 1,
206 },
207};
208
209/* DMAC platform data's slave info */ 30/* DMAC platform data's slave info */
210struct pl08x_channel_data spear320_dma_info[] = { 31struct pl08x_channel_data spear320_dma_info[] = {
211 { 32 {
@@ -416,41 +237,17 @@ static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
416 237
417static void __init spear320_dt_init(void) 238static void __init spear320_dt_init(void)
418{ 239{
419 void __iomem *base;
420 int ret;
421
422 pl080_plat_data.slave_channels = spear320_dma_info; 240 pl080_plat_data.slave_channels = spear320_dma_info;
423 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); 241 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
424 242
425 of_platform_populate(NULL, of_default_bus_match_table, 243 of_platform_populate(NULL, of_default_bus_match_table,
426 spear320_auxdata_lookup, NULL); 244 spear320_auxdata_lookup, NULL);
427
428 /* shared irq registration */
429 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
430 if (base) {
431 /* shirq 1 */
432 shirq_ras1.regs.base = base;
433 ret = spear_shirq_register(&shirq_ras1);
434 if (ret)
435 pr_err("Error registering Shared IRQ 1\n");
436
437 /* shirq 3 */
438 shirq_ras3.regs.base = base;
439 ret = spear_shirq_register(&shirq_ras3);
440 if (ret)
441 pr_err("Error registering Shared IRQ 3\n");
442
443 /* shirq 4 */
444 shirq_intrcomm_ras.regs.base = base;
445 ret = spear_shirq_register(&shirq_intrcomm_ras);
446 if (ret)
447 pr_err("Error registering Shared IRQ 4\n");
448 }
449} 245}
450 246
451static const char * const spear320_dt_board_compat[] = { 247static const char * const spear320_dt_board_compat[] = {
452 "st,spear320", 248 "st,spear320",
453 "st,spear320-evb", 249 "st,spear320-evb",
250 "st,spear320-hmi",
454 NULL, 251 NULL,
455}; 252};
456 253
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 98144baf8883..38fe95db31a7 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -15,6 +15,7 @@
15 15
16#include <linux/amba/pl022.h> 16#include <linux/amba/pl022.h>
17#include <linux/amba/pl08x.h> 17#include <linux/amba/pl08x.h>
18#include <linux/irqchip/spear-shirq.h>
18#include <linux/of_irq.h> 19#include <linux/of_irq.h>
19#include <linux/io.h> 20#include <linux/io.h>
20#include <asm/hardware/pl080.h> 21#include <asm/hardware/pl080.h>
@@ -121,6 +122,9 @@ struct sys_timer spear3xx_timer = {
121 122
122static const struct of_device_id vic_of_match[] __initconst = { 123static const struct of_device_id vic_of_match[] __initconst = {
123 { .compatible = "arm,pl190-vic", .data = vic_of_init, }, 124 { .compatible = "arm,pl190-vic", .data = vic_of_init, },
125 { .compatible = "st,spear300-shirq", .data = spear300_shirq_of_init, },
126 { .compatible = "st,spear310-shirq", .data = spear310_shirq_of_init, },
127 { .compatible = "st,spear320-shirq", .data = spear320_shirq_of_init, },
124 { /* Sentinel */ } 128 { /* Sentinel */ }
125}; 129};
126 130
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 2607bd05c525..01e88532a5db 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -5,5 +5,5 @@
5# Common support 5# Common support
6obj-y := restart.o time.o 6obj-y := restart.o time.o
7 7
8obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o shirq.o 8obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o
9obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o 9obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o
diff --git a/arch/arm/plat-spear/shirq.c b/arch/arm/plat-spear/shirq.c
deleted file mode 100644
index 853e891e1184..000000000000
--- a/arch/arm/plat-spear/shirq.c
+++ /dev/null
@@ -1,118 +0,0 @@
1/*
2 * arch/arm/plat-spear/shirq.c
3 *
4 * SPEAr platform shared irq layer source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/spinlock.h>
18#include <plat/shirq.h>
19
20struct spear_shirq *shirq;
21static DEFINE_SPINLOCK(lock);
22
23static void shirq_irq_mask(struct irq_data *d)
24{
25 struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
26 u32 val, id = d->irq - shirq->dev_config[0].virq;
27 unsigned long flags;
28
29 if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1)
30 return;
31
32 spin_lock_irqsave(&lock, flags);
33 val = readl(shirq->regs.base + shirq->regs.enb_reg);
34 if (shirq->regs.reset_to_enb)
35 val |= shirq->dev_config[id].enb_mask;
36 else
37 val &= ~(shirq->dev_config[id].enb_mask);
38 writel(val, shirq->regs.base + shirq->regs.enb_reg);
39 spin_unlock_irqrestore(&lock, flags);
40}
41
42static void shirq_irq_unmask(struct irq_data *d)
43{
44 struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
45 u32 val, id = d->irq - shirq->dev_config[0].virq;
46 unsigned long flags;
47
48 if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1)
49 return;
50
51 spin_lock_irqsave(&lock, flags);
52 val = readl(shirq->regs.base + shirq->regs.enb_reg);
53 if (shirq->regs.reset_to_enb)
54 val &= ~(shirq->dev_config[id].enb_mask);
55 else
56 val |= shirq->dev_config[id].enb_mask;
57 writel(val, shirq->regs.base + shirq->regs.enb_reg);
58 spin_unlock_irqrestore(&lock, flags);
59}
60
61static struct irq_chip shirq_chip = {
62 .name = "spear_shirq",
63 .irq_ack = shirq_irq_mask,
64 .irq_mask = shirq_irq_mask,
65 .irq_unmask = shirq_irq_unmask,
66};
67
68static void shirq_handler(unsigned irq, struct irq_desc *desc)
69{
70 u32 i, val, mask;
71 struct spear_shirq *shirq = irq_get_handler_data(irq);
72
73 desc->irq_data.chip->irq_ack(&desc->irq_data);
74 while ((val = readl(shirq->regs.base + shirq->regs.status_reg) &
75 shirq->regs.status_reg_mask)) {
76 for (i = 0; (i < shirq->dev_count) && val; i++) {
77 if (!(shirq->dev_config[i].status_mask & val))
78 continue;
79
80 generic_handle_irq(shirq->dev_config[i].virq);
81
82 /* clear interrupt */
83 val &= ~shirq->dev_config[i].status_mask;
84 if ((shirq->regs.clear_reg == -1) ||
85 shirq->dev_config[i].clear_mask == -1)
86 continue;
87 mask = readl(shirq->regs.base + shirq->regs.clear_reg);
88 if (shirq->regs.reset_to_clear)
89 mask &= ~shirq->dev_config[i].clear_mask;
90 else
91 mask |= shirq->dev_config[i].clear_mask;
92 writel(mask, shirq->regs.base + shirq->regs.clear_reg);
93 }
94 }
95 desc->irq_data.chip->irq_unmask(&desc->irq_data);
96}
97
98int spear_shirq_register(struct spear_shirq *shirq)
99{
100 int i;
101
102 if (!shirq || !shirq->dev_config || !shirq->regs.base)
103 return -EFAULT;
104
105 if (!shirq->dev_count)
106 return -EINVAL;
107
108 irq_set_chained_handler(shirq->irq, shirq_handler);
109 for (i = 0; i < shirq->dev_count; i++) {
110 irq_set_chip_and_handler(shirq->dev_config[i].virq,
111 &shirq_chip, handle_simple_irq);
112 set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID);
113 irq_set_chip_data(shirq->dev_config[i].virq, shirq);
114 }
115
116 irq_set_handler_data(shirq->irq, shirq);
117 return 0;
118}
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 147e25f00405..ed9af4278619 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -20,6 +20,7 @@
20#include <mach/spear.h> 20#include <mach/spear.h>
21#include "clk.h" 21#include "clk.h"
22 22
23#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
23/* PLL related registers and bit values */ 24/* PLL related registers and bit values */
24#define SPEAR1310_PLL_CFG (VA_MISC_BASE + 0x210) 25#define SPEAR1310_PLL_CFG (VA_MISC_BASE + 0x210)
25 /* PLL_CFG bit values */ 26 /* PLL_CFG bit values */
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 02bd37a6187f..bf4609a5bd9d 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -1,3 +1,4 @@
1obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o 1obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
2obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o 2obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o
3obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o 3obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
4obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
diff --git a/drivers/irqchip/spear-shirq.c b/drivers/irqchip/spear-shirq.c
new file mode 100644
index 000000000000..80e1d2fd9d4c
--- /dev/null
+++ b/drivers/irqchip/spear-shirq.c
@@ -0,0 +1,316 @@
1/*
2 * SPEAr platform shared irq layer source file
3 *
4 * Copyright (C) 2009-2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com>
6 *
7 * Copyright (C) 2012 ST Microelectronics
8 * Shiraz Hashim <shiraz.hashim@st.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16#include <linux/err.h>
17#include <linux/export.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/irqdomain.h>
22#include <linux/irqchip/spear-shirq.h>
23#include <linux/of.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
26#include <linux/spinlock.h>
27
28static DEFINE_SPINLOCK(lock);
29
30/* spear300 shared irq registers offsets and masks */
31#define SPEAR300_INT_ENB_MASK_REG 0x54
32#define SPEAR300_INT_STS_MASK_REG 0x58
33
34static struct spear_shirq spear300_shirq_ras1 = {
35 .irq_nr = 9,
36 .irq_bit_off = 0,
37 .regs = {
38 .enb_reg = SPEAR300_INT_ENB_MASK_REG,
39 .status_reg = SPEAR300_INT_STS_MASK_REG,
40 .clear_reg = -1,
41 },
42};
43
44static struct spear_shirq *spear300_shirq_blocks[] = {
45 &spear300_shirq_ras1,
46};
47
48/* spear310 shared irq registers offsets and masks */
49#define SPEAR310_INT_STS_MASK_REG 0x04
50
51static struct spear_shirq spear310_shirq_ras1 = {
52 .irq_nr = 8,
53 .irq_bit_off = 0,
54 .regs = {
55 .enb_reg = -1,
56 .status_reg = SPEAR310_INT_STS_MASK_REG,
57 .clear_reg = -1,
58 },
59};
60
61static struct spear_shirq spear310_shirq_ras2 = {
62 .irq_nr = 5,
63 .irq_bit_off = 8,
64 .regs = {
65 .enb_reg = -1,
66 .status_reg = SPEAR310_INT_STS_MASK_REG,
67 .clear_reg = -1,
68 },
69};
70
71static struct spear_shirq spear310_shirq_ras3 = {
72 .irq_nr = 1,
73 .irq_bit_off = 13,
74 .regs = {
75 .enb_reg = -1,
76 .status_reg = SPEAR310_INT_STS_MASK_REG,
77 .clear_reg = -1,
78 },
79};
80
81static struct spear_shirq spear310_shirq_intrcomm_ras = {
82 .irq_nr = 3,
83 .irq_bit_off = 14,
84 .regs = {
85 .enb_reg = -1,
86 .status_reg = SPEAR310_INT_STS_MASK_REG,
87 .clear_reg = -1,
88 },
89};
90
91static struct spear_shirq *spear310_shirq_blocks[] = {
92 &spear310_shirq_ras1,
93 &spear310_shirq_ras2,
94 &spear310_shirq_ras3,
95 &spear310_shirq_intrcomm_ras,
96};
97
98/* spear320 shared irq registers offsets and masks */
99#define SPEAR320_INT_STS_MASK_REG 0x04
100#define SPEAR320_INT_CLR_MASK_REG 0x04
101#define SPEAR320_INT_ENB_MASK_REG 0x08
102
103static struct spear_shirq spear320_shirq_ras1 = {
104 .irq_nr = 3,
105 .irq_bit_off = 7,
106 .regs = {
107 .enb_reg = -1,
108 .status_reg = SPEAR320_INT_STS_MASK_REG,
109 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
110 .reset_to_clear = 1,
111 },
112};
113
114static struct spear_shirq spear320_shirq_ras2 = {
115 .irq_nr = 1,
116 .irq_bit_off = 10,
117 .regs = {
118 .enb_reg = -1,
119 .status_reg = SPEAR320_INT_STS_MASK_REG,
120 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
121 .reset_to_clear = 1,
122 },
123};
124
125static struct spear_shirq spear320_shirq_ras3 = {
126 .irq_nr = 3,
127 .irq_bit_off = 0,
128 .invalid_irq = 1,
129 .regs = {
130 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
131 .reset_to_enb = 1,
132 .status_reg = SPEAR320_INT_STS_MASK_REG,
133 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
134 .reset_to_clear = 1,
135 },
136};
137
138static struct spear_shirq spear320_shirq_intrcomm_ras = {
139 .irq_nr = 11,
140 .irq_bit_off = 11,
141 .regs = {
142 .enb_reg = -1,
143 .status_reg = SPEAR320_INT_STS_MASK_REG,
144 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
145 .reset_to_clear = 1,
146 },
147};
148
149static struct spear_shirq *spear320_shirq_blocks[] = {
150 &spear320_shirq_ras3,
151 &spear320_shirq_ras1,
152 &spear320_shirq_ras2,
153 &spear320_shirq_intrcomm_ras,
154};
155
156static void shirq_irq_mask_unmask(struct irq_data *d, bool mask)
157{
158 struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
159 u32 val, offset = d->irq - shirq->irq_base;
160 unsigned long flags;
161
162 if (shirq->regs.enb_reg == -1)
163 return;
164
165 spin_lock_irqsave(&lock, flags);
166 val = readl(shirq->base + shirq->regs.enb_reg);
167
168 if (mask ^ shirq->regs.reset_to_enb)
169 val &= ~(0x1 << shirq->irq_bit_off << offset);
170 else
171 val |= 0x1 << shirq->irq_bit_off << offset;
172
173 writel(val, shirq->base + shirq->regs.enb_reg);
174 spin_unlock_irqrestore(&lock, flags);
175
176}
177
178static void shirq_irq_mask(struct irq_data *d)
179{
180 shirq_irq_mask_unmask(d, 1);
181}
182
183static void shirq_irq_unmask(struct irq_data *d)
184{
185 shirq_irq_mask_unmask(d, 0);
186}
187
188static struct irq_chip shirq_chip = {
189 .name = "spear-shirq",
190 .irq_ack = shirq_irq_mask,
191 .irq_mask = shirq_irq_mask,
192 .irq_unmask = shirq_irq_unmask,
193};
194
195static void shirq_handler(unsigned irq, struct irq_desc *desc)
196{
197 u32 i, j, val, mask, tmp;
198 struct irq_chip *chip;
199 struct spear_shirq *shirq = irq_get_handler_data(irq);
200
201 chip = irq_get_chip(irq);
202 chip->irq_ack(&desc->irq_data);
203
204 mask = ((0x1 << shirq->irq_nr) - 1) << shirq->irq_bit_off;
205 while ((val = readl(shirq->base + shirq->regs.status_reg) &
206 mask)) {
207
208 val >>= shirq->irq_bit_off;
209 for (i = 0, j = 1; i < shirq->irq_nr; i++, j <<= 1) {
210
211 if (!(j & val))
212 continue;
213
214 generic_handle_irq(shirq->irq_base + i);
215
216 /* clear interrupt */
217 if (shirq->regs.clear_reg == -1)
218 continue;
219
220 tmp = readl(shirq->base + shirq->regs.clear_reg);
221 if (shirq->regs.reset_to_clear)
222 tmp &= ~(j << shirq->irq_bit_off);
223 else
224 tmp |= (j << shirq->irq_bit_off);
225 writel(tmp, shirq->base + shirq->regs.clear_reg);
226 }
227 }
228 chip->irq_unmask(&desc->irq_data);
229}
230
231static void __init spear_shirq_register(struct spear_shirq *shirq)
232{
233 int i;
234
235 if (shirq->invalid_irq)
236 return;
237
238 irq_set_chained_handler(shirq->irq, shirq_handler);
239 for (i = 0; i < shirq->irq_nr; i++) {
240 irq_set_chip_and_handler(shirq->irq_base + i,
241 &shirq_chip, handle_simple_irq);
242 set_irq_flags(shirq->irq_base + i, IRQF_VALID);
243 irq_set_chip_data(shirq->irq_base + i, shirq);
244 }
245
246 irq_set_handler_data(shirq->irq, shirq);
247}
248
249static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
250 struct device_node *np)
251{
252 int i, irq_base, hwirq = 0, irq_nr = 0;
253 static struct irq_domain *shirq_domain;
254 void __iomem *base;
255
256 base = of_iomap(np, 0);
257 if (!base) {
258 pr_err("%s: failed to map shirq registers\n", __func__);
259 return -ENXIO;
260 }
261
262 for (i = 0; i < block_nr; i++)
263 irq_nr += shirq_blocks[i]->irq_nr;
264
265 irq_base = irq_alloc_descs(-1, 0, irq_nr, 0);
266 if (IS_ERR_VALUE(irq_base)) {
267 pr_err("%s: irq desc alloc failed\n", __func__);
268 goto err_unmap;
269 }
270
271 shirq_domain = irq_domain_add_legacy(np, irq_nr, irq_base, 0,
272 &irq_domain_simple_ops, NULL);
273 if (WARN_ON(!shirq_domain)) {
274 pr_warn("%s: irq domain init failed\n", __func__);
275 goto err_free_desc;
276 }
277
278 for (i = 0; i < block_nr; i++) {
279 shirq_blocks[i]->base = base;
280 shirq_blocks[i]->irq_base = irq_find_mapping(shirq_domain,
281 hwirq);
282 shirq_blocks[i]->irq = irq_of_parse_and_map(np, i);
283
284 spear_shirq_register(shirq_blocks[i]);
285 hwirq += shirq_blocks[i]->irq_nr;
286 }
287
288 return 0;
289
290err_free_desc:
291 irq_free_descs(irq_base, irq_nr);
292err_unmap:
293 iounmap(base);
294 return -ENXIO;
295}
296
297int __init spear300_shirq_of_init(struct device_node *np,
298 struct device_node *parent)
299{
300 return shirq_init(spear300_shirq_blocks,
301 ARRAY_SIZE(spear300_shirq_blocks), np);
302}
303
304int __init spear310_shirq_of_init(struct device_node *np,
305 struct device_node *parent)
306{
307 return shirq_init(spear310_shirq_blocks,
308 ARRAY_SIZE(spear310_shirq_blocks), np);
309}
310
311int __init spear320_shirq_of_init(struct device_node *np,
312 struct device_node *parent)
313{
314 return shirq_init(spear320_shirq_blocks,
315 ARRAY_SIZE(spear320_shirq_blocks), np);
316}
diff --git a/arch/arm/plat-spear/include/plat/shirq.h b/include/linux/irqchip/spear-shirq.h
index 88a7fbd24793..c8be16d213a3 100644
--- a/arch/arm/plat-spear/include/plat/shirq.h
+++ b/include/linux/irqchip/spear-shirq.h
@@ -1,9 +1,7 @@
1/* 1/*
2 * arch/arm/plat-spear/include/plat/shirq.h
3 *
4 * SPEAr platform shared irq layer header file 2 * SPEAr platform shared irq layer header file
5 * 3 *
6 * Copyright (C) 2009 ST Microelectronics 4 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com> 5 * Viresh Kumar <viresh.linux@gmail.com>
8 * 6 *
9 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
@@ -11,31 +9,15 @@
11 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
12 */ 10 */
13 11
14#ifndef __PLAT_SHIRQ_H 12#ifndef __SPEAR_SHIRQ_H
15#define __PLAT_SHIRQ_H 13#define __SPEAR_SHIRQ_H
16 14
17#include <linux/irq.h> 15#include <linux/irq.h>
18#include <linux/types.h> 16#include <linux/types.h>
19 17
20/* 18/*
21 * struct shirq_dev_config: shared irq device configuration
22 *
23 * virq: virtual irq number of device
24 * enb_mask: enable mask of device
25 * status_mask: status mask of device
26 * clear_mask: clear mask of device
27 */
28struct shirq_dev_config {
29 u32 virq;
30 u32 enb_mask;
31 u32 status_mask;
32 u32 clear_mask;
33};
34
35/*
36 * struct shirq_regs: shared irq register configuration 19 * struct shirq_regs: shared irq register configuration
37 * 20 *
38 * base: base address of shared irq register
39 * enb_reg: enable register offset 21 * enb_reg: enable register offset
40 * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt 22 * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt
41 * status_reg: status register offset 23 * status_reg: status register offset
@@ -44,11 +26,9 @@ struct shirq_dev_config {
44 * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt 26 * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt
45 */ 27 */
46struct shirq_regs { 28struct shirq_regs {
47 void __iomem *base;
48 u32 enb_reg; 29 u32 enb_reg;
49 u32 reset_to_enb; 30 u32 reset_to_enb;
50 u32 status_reg; 31 u32 status_reg;
51 u32 status_reg_mask;
52 u32 clear_reg; 32 u32 clear_reg;
53 u32 reset_to_clear; 33 u32 reset_to_clear;
54}; 34};
@@ -57,17 +37,28 @@ struct shirq_regs {
57 * struct spear_shirq: shared irq structure 37 * struct spear_shirq: shared irq structure
58 * 38 *
59 * irq: hardware irq number 39 * irq: hardware irq number
60 * dev_config: array of device config structures which are using "irq" line 40 * irq_base: base irq in linux domain
61 * dev_count: size of dev_config array 41 * irq_nr: no. of shared interrupts in a particular block
42 * irq_bit_off: starting bit offset in the status register
43 * invalid_irq: irq group is currently disabled
44 * base: base address of shared irq register
62 * regs: register configuration for shared irq block 45 * regs: register configuration for shared irq block
63 */ 46 */
64struct spear_shirq { 47struct spear_shirq {
65 u32 irq; 48 u32 irq;
66 struct shirq_dev_config *dev_config; 49 u32 irq_base;
67 u32 dev_count; 50 u32 irq_nr;
51 u32 irq_bit_off;
52 int invalid_irq;
53 void __iomem *base;
68 struct shirq_regs regs; 54 struct shirq_regs regs;
69}; 55};
70 56
71int spear_shirq_register(struct spear_shirq *shirq); 57int __init spear300_shirq_of_init(struct device_node *np,
58 struct device_node *parent);
59int __init spear310_shirq_of_init(struct device_node *np,
60 struct device_node *parent);
61int __init spear320_shirq_of_init(struct device_node *np,
62 struct device_node *parent);
72 63
73#endif /* __PLAT_SHIRQ_H */ 64#endif /* __SPEAR_SHIRQ_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 05:38:25 -0500