ARM i.MX6q: Link system reset controller (SRC) to IPU in DT

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

2 files changed, 3 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 83bc61cac61e..21e675848bd1 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -335,6 +335,7 @@
                         interrupts = <0 8 0x4 0 7 0x4>;
                         clocks = <&clks 133>, <&clks 134>, <&clks 137>;
                         clock-names = "bus", "di0", "di1";
+                        resets = <&src 4>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 804c0ec32399..8b6dfd1a1b2f 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -523,6 +523,7 @@
                                 compatible = "fsl,imx6q-src";
                                 reg = <0x020d8000 0x4000>;
                                 interrupts = <0 91 0x04 0 96 0x04>;
+                                #reset-cells = <1>;
                         };
 
                         gpc: gpc@020dc000 {
@@ -822,6 +823,7 @@
                         interrupts = <0 6 0x4 0 5 0x4>;
                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
                         clock-names = "bus", "di0", "di1";
+                        resets = <&src 2>;
                 };
         };
 };