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authorLinus Torvalds <torvalds@g5.osdl.org>2005-07-26 18:13:26 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-07-26 18:13:26 -0400
commitfc00a6274b786f6863b32c79ff6f92aa0960b789 (patch)
tree7078e320ac34aa104f9adefaedf7add3173fe160
parent0983f0509480f95584f8e945e5b9c5310e9038f3 (diff)
parenta8d11e3d0282e9607f65c73383c4030fd8f0e972 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
Diffstat
-rw-r--r--arch/arm/mach-s3c2410/Makefile2
-rw-r--r--arch/arm/mach-s3c2410/clock.c57
-rw-r--r--arch/arm/mach-s3c2410/irq.c260
-rw-r--r--arch/arm/mach-s3c2410/irq.h99
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c13
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-clock.c116
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-irq.c207
-rw-r--r--drivers/pcmcia/sa1100_jornada720.c19
-rw-r--r--include/asm-arm/arch-s3c2410/regs-iis.h10
9 files changed, 445 insertions, 338 deletions
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index f99b689e4392..55ed7c7e57da 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -23,6 +23,8 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
23# S3C2440 support 23# S3C2440 support
24 24
25obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o 25obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o
26obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o
27obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o
26 28
27# machine specific support 29# machine specific support
28 30
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index 8d986b8401c2..9a66050e887d 100644
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -448,60 +448,3 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
448 448
449 return 0; 449 return 0;
450} 450}
451
452/* S3C2440 extended clock support */
453
454#ifdef CONFIG_CPU_S3C2440
455
456static struct clk s3c2440_clk_upll = {
457 .name = "upll",
458 .id = -1,
459};
460
461static struct clk s3c2440_clk_cam = {
462 .name = "camif",
463 .parent = &clk_h,
464 .id = -1,
465 .enable = s3c24xx_clkcon_enable,
466 .ctrlbit = S3C2440_CLKCON_CAMERA,
467};
468
469static struct clk s3c2440_clk_ac97 = {
470 .name = "ac97",
471 .parent = &clk_p,
472 .id = -1,
473 .enable = s3c24xx_clkcon_enable,
474 .ctrlbit = S3C2440_CLKCON_CAMERA,
475};
476
477static int s3c2440_clk_add(struct sys_device *sysdev)
478{
479 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
480
481 s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal.rate);
482
483 printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n",
484 print_mhz(s3c2440_clk_upll.rate));
485
486 s3c24xx_register_clock(&s3c2440_clk_ac97);
487 s3c24xx_register_clock(&s3c2440_clk_cam);
488 s3c24xx_register_clock(&s3c2440_clk_upll);
489
490 clk_disable(&s3c2440_clk_ac97);
491 clk_disable(&s3c2440_clk_cam);
492
493 return 0;
494}
495
496static struct sysdev_driver s3c2440_clk_driver = {
497 .add = s3c2440_clk_add,
498};
499
500static int s3c24xx_clk_driver(void)
501{
502 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
503}
504
505arch_initcall(s3c24xx_clk_driver);
506
507#endif /* CONFIG_CPU_S3C2440 */
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index cf9f46d88061..973a5fe6769c 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -45,6 +45,9 @@
45 * 45 *
46 * 28-Jun-2005 Ben Dooks 46 * 28-Jun-2005 Ben Dooks
47 * Mark IRQ_LCD valid 47 * Mark IRQ_LCD valid
48 *
49 * 25-Jul-2005 Ben Dooks
50 * Split the S3C2440 IRQ code to seperate file
48*/ 51*/
49 52
50#include <linux/init.h> 53#include <linux/init.h>
@@ -65,11 +68,7 @@
65 68
66#include "cpu.h" 69#include "cpu.h"
67#include "pm.h" 70#include "pm.h"
68 71#include "irq.h"
69#define irqdbf(x...)
70#define irqdbf2(x...)
71
72#define EXTINT_OFF (IRQ_EINT4 - 4)
73 72
74/* wakeup irq control */ 73/* wakeup irq control */
75 74
@@ -181,7 +180,7 @@ s3c_irq_unmask(unsigned int irqno)
181 __raw_writel(mask, S3C2410_INTMSK); 180 __raw_writel(mask, S3C2410_INTMSK);
182} 181}
183 182
184static struct irqchip s3c_irq_level_chip = { 183struct irqchip s3c_irq_level_chip = {
185 .ack = s3c_irq_maskack, 184 .ack = s3c_irq_maskack,
186 .mask = s3c_irq_mask, 185 .mask = s3c_irq_mask,
187 .unmask = s3c_irq_unmask, 186 .unmask = s3c_irq_unmask,
@@ -370,84 +369,6 @@ static struct irqchip s3c_irq_eint0t4 = {
370#define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0)) 369#define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
371#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0)) 370#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
372 371
373static inline void
374s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
375 int subcheck)
376{
377 unsigned long mask;
378 unsigned long submask;
379
380 submask = __raw_readl(S3C2410_INTSUBMSK);
381 mask = __raw_readl(S3C2410_INTMSK);
382
383 submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
384
385 /* check to see if we need to mask the parent IRQ */
386
387 if ((submask & subcheck) == subcheck) {
388 __raw_writel(mask | parentbit, S3C2410_INTMSK);
389 }
390
391 /* write back masks */
392 __raw_writel(submask, S3C2410_INTSUBMSK);
393
394}
395
396static inline void
397s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
398{
399 unsigned long mask;
400 unsigned long submask;
401
402 submask = __raw_readl(S3C2410_INTSUBMSK);
403 mask = __raw_readl(S3C2410_INTMSK);
404
405 submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
406 mask &= ~parentbit;
407
408 /* write back masks */
409 __raw_writel(submask, S3C2410_INTSUBMSK);
410 __raw_writel(mask, S3C2410_INTMSK);
411}
412
413
414static inline void
415s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
416{
417 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
418
419 s3c_irqsub_mask(irqno, parentmask, group);
420
421 __raw_writel(bit, S3C2410_SUBSRCPND);
422
423 /* only ack parent if we've got all the irqs (seems we must
424 * ack, all and hope that the irq system retriggers ok when
425 * the interrupt goes off again)
426 */
427
428 if (1) {
429 __raw_writel(parentmask, S3C2410_SRCPND);
430 __raw_writel(parentmask, S3C2410_INTPND);
431 }
432}
433
434static inline void
435s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
436{
437 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
438
439 __raw_writel(bit, S3C2410_SUBSRCPND);
440
441 /* only ack parent if we've got all the irqs (seems we must
442 * ack, all and hope that the irq system retriggers ok when
443 * the interrupt goes off again)
444 */
445
446 if (1) {
447 __raw_writel(parentmask, S3C2410_SRCPND);
448 __raw_writel(parentmask, S3C2410_INTPND);
449 }
450}
451 372
452/* UART0 */ 373/* UART0 */
453 374
@@ -794,174 +715,3 @@ void __init s3c24xx_init_irq(void)
794 715
795 irqdbf("s3c2410: registered interrupt handlers\n"); 716 irqdbf("s3c2410: registered interrupt handlers\n");
796} 717}
797
798/* s3c2440 irq code
799*/
800
801#ifdef CONFIG_CPU_S3C2440
802
803/* WDT/AC97 */
804
805static void s3c_irq_demux_wdtac97(unsigned int irq,
806 struct irqdesc *desc,
807 struct pt_regs *regs)
808{
809 unsigned int subsrc, submsk;
810 struct irqdesc *mydesc;
811
812 /* read the current pending interrupts, and the mask
813 * for what it is available */
814
815 subsrc = __raw_readl(S3C2410_SUBSRCPND);
816 submsk = __raw_readl(S3C2410_INTSUBMSK);
817
818 subsrc &= ~submsk;
819 subsrc >>= 13;
820 subsrc &= 3;
821
822 if (subsrc != 0) {
823 if (subsrc & 1) {
824 mydesc = irq_desc + IRQ_S3C2440_WDT;
825 mydesc->handle( IRQ_S3C2440_WDT, mydesc, regs);
826 }
827 if (subsrc & 2) {
828 mydesc = irq_desc + IRQ_S3C2440_AC97;
829 mydesc->handle(IRQ_S3C2440_AC97, mydesc, regs);
830 }
831 }
832}
833
834
835#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0))
836
837static void
838s3c_irq_wdtac97_mask(unsigned int irqno)
839{
840 s3c_irqsub_mask(irqno, INTMSK_WDT, 3<<13);
841}
842
843static void
844s3c_irq_wdtac97_unmask(unsigned int irqno)
845{
846 s3c_irqsub_unmask(irqno, INTMSK_WDT);
847}
848
849static void
850s3c_irq_wdtac97_ack(unsigned int irqno)
851{
852 s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
853}
854
855static struct irqchip s3c_irq_wdtac97 = {
856 .mask = s3c_irq_wdtac97_mask,
857 .unmask = s3c_irq_wdtac97_unmask,
858 .ack = s3c_irq_wdtac97_ack,
859};
860
861/* camera irq */
862
863static void s3c_irq_demux_cam(unsigned int irq,
864 struct irqdesc *desc,
865 struct pt_regs *regs)
866{
867 unsigned int subsrc, submsk;
868 struct irqdesc *mydesc;
869
870 /* read the current pending interrupts, and the mask
871 * for what it is available */
872
873 subsrc = __raw_readl(S3C2410_SUBSRCPND);
874 submsk = __raw_readl(S3C2410_INTSUBMSK);
875
876 subsrc &= ~submsk;
877 subsrc >>= 11;
878 subsrc &= 3;
879
880 if (subsrc != 0) {
881 if (subsrc & 1) {
882 mydesc = irq_desc + IRQ_S3C2440_CAM_C;
883 mydesc->handle( IRQ_S3C2440_WDT, mydesc, regs);
884 }
885 if (subsrc & 2) {
886 mydesc = irq_desc + IRQ_S3C2440_CAM_P;
887 mydesc->handle(IRQ_S3C2440_AC97, mydesc, regs);
888 }
889 }
890}
891
892#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
893
894static void
895s3c_irq_cam_mask(unsigned int irqno)
896{
897 s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11);
898}
899
900static void
901s3c_irq_cam_unmask(unsigned int irqno)
902{
903 s3c_irqsub_unmask(irqno, INTMSK_CAM);
904}
905
906static void
907s3c_irq_cam_ack(unsigned int irqno)
908{
909 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
910}
911
912static struct irqchip s3c_irq_cam = {
913 .mask = s3c_irq_cam_mask,
914 .unmask = s3c_irq_cam_unmask,
915 .ack = s3c_irq_cam_ack,
916};
917
918static int s3c2440_irq_add(struct sys_device *sysdev)
919{
920 unsigned int irqno;
921
922 printk("S3C2440: IRQ Support\n");
923
924 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
925 set_irq_handler(IRQ_NFCON, do_level_IRQ);
926 set_irq_flags(IRQ_NFCON, IRQF_VALID);
927
928 /* add new chained handler for wdt, ac7 */
929
930 set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
931 set_irq_handler(IRQ_WDT, do_level_IRQ);
932 set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
933
934 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
935 set_irq_chip(irqno, &s3c_irq_wdtac97);
936 set_irq_handler(irqno, do_level_IRQ);
937 set_irq_flags(irqno, IRQF_VALID);
938 }
939
940 /* add chained handler for camera */
941
942 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
943 set_irq_handler(IRQ_CAM, do_level_IRQ);
944 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
945
946 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
947 set_irq_chip(irqno, &s3c_irq_cam);
948 set_irq_handler(irqno, do_level_IRQ);
949 set_irq_flags(irqno, IRQF_VALID);
950 }
951
952 return 0;
953}
954
955static struct sysdev_driver s3c2440_irq_driver = {
956 .add = s3c2440_irq_add,
957};
958
959static int s3c24xx_irq_driver(void)
960{
961 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
962}
963
964arch_initcall(s3c24xx_irq_driver);
965
966#endif /* CONFIG_CPU_S3C2440 */
967
diff --git a/arch/arm/mach-s3c2410/irq.h b/arch/arm/mach-s3c2410/irq.h
new file mode 100644
index 000000000000..4abf0ca14e00
--- /dev/null
+++ b/arch/arm/mach-s3c2410/irq.h
@@ -0,0 +1,99 @@
1/* arch/arm/mach-s3c2410/irq.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU IRQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Modifications:
13*/
14
15#define irqdbf(x...)
16#define irqdbf2(x...)
17
18#define EXTINT_OFF (IRQ_EINT4 - 4)
19
20extern struct irqchip s3c_irq_level_chip;
21
22static inline void
23s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
24 int subcheck)
25{
26 unsigned long mask;
27 unsigned long submask;
28
29 submask = __raw_readl(S3C2410_INTSUBMSK);
30 mask = __raw_readl(S3C2410_INTMSK);
31
32 submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
33
34 /* check to see if we need to mask the parent IRQ */
35
36 if ((submask & subcheck) == subcheck) {
37 __raw_writel(mask | parentbit, S3C2410_INTMSK);
38 }
39
40 /* write back masks */
41 __raw_writel(submask, S3C2410_INTSUBMSK);
42
43}
44
45static inline void
46s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
47{
48 unsigned long mask;
49 unsigned long submask;
50
51 submask = __raw_readl(S3C2410_INTSUBMSK);
52 mask = __raw_readl(S3C2410_INTMSK);
53
54 submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
55 mask &= ~parentbit;
56
57 /* write back masks */
58 __raw_writel(submask, S3C2410_INTSUBMSK);
59 __raw_writel(mask, S3C2410_INTMSK);
60}
61
62
63static inline void
64s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
65{
66 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
67
68 s3c_irqsub_mask(irqno, parentmask, group);
69
70 __raw_writel(bit, S3C2410_SUBSRCPND);
71
72 /* only ack parent if we've got all the irqs (seems we must
73 * ack, all and hope that the irq system retriggers ok when
74 * the interrupt goes off again)
75 */
76
77 if (1) {
78 __raw_writel(parentmask, S3C2410_SRCPND);
79 __raw_writel(parentmask, S3C2410_INTPND);
80 }
81}
82
83static inline void
84s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
85{
86 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
87
88 __raw_writel(bit, S3C2410_SUBSRCPND);
89
90 /* only ack parent if we've got all the irqs (seems we must
91 * ack, all and hope that the irq system retriggers ok when
92 * the interrupt goes off again)
93 */
94
95 if (1) {
96 __raw_writel(parentmask, S3C2410_SRCPND);
97 __raw_writel(parentmask, S3C2410_INTPND);
98 }
99}
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 206778ebfce7..1e7f343822d0 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -25,10 +25,11 @@
25 * 14-Jan-2005 BJD Add support for muitlple NAND devices 25 * 14-Jan-2005 BJD Add support for muitlple NAND devices
26 * 03-Mar-2005 BJD Ensured that bast-cpld.h is included 26 * 03-Mar-2005 BJD Ensured that bast-cpld.h is included
27 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA 27 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
28 * 14-Mar-2006 BJD Updated for __iomem changes 28 * 14-Mar-2005 BJD Updated for __iomem changes
29 * 22-Jun-2006 BJD Added DM9000 platform information 29 * 22-Jun-2005 BJD Added DM9000 platform information
30 * 28-Jun-2006 BJD Moved pm functionality out to common code 30 * 28-Jun-2005 BJD Moved pm functionality out to common code
31 * 17-Jul-2006 BJD Changed to platform device for SuperIO 16550s 31 * 17-Jul-2005 BJD Changed to platform device for SuperIO 16550s
32 * 25-Jul-2005 BJD Removed ASIX static mappings
32*/ 33*/
33 34
34#include <linux/kernel.h> 35#include <linux/kernel.h>
@@ -116,7 +117,6 @@ static struct map_desc bast_iodesc[] __initdata = {
116 /* slow, byte */ 117 /* slow, byte */
117 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, 118 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
118 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, 119 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
119 { VA_C2(BAST_VA_ASIXNET), PA_CS3(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
120 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, 120 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
121 { VA_C2(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE }, 121 { VA_C2(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
122 { VA_C2(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE }, 122 { VA_C2(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
@@ -126,7 +126,6 @@ static struct map_desc bast_iodesc[] __initdata = {
126 /* slow, word */ 126 /* slow, word */
127 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, 127 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
128 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, 128 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
129 { VA_C3(BAST_VA_ASIXNET), PA_CS3(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
130 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, 129 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
131 { VA_C3(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE }, 130 { VA_C3(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
132 { VA_C3(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE }, 131 { VA_C3(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
@@ -136,7 +135,6 @@ static struct map_desc bast_iodesc[] __initdata = {
136 /* fast, byte */ 135 /* fast, byte */
137 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, 136 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
138 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, 137 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
139 { VA_C4(BAST_VA_ASIXNET), PA_CS5(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
140 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, 138 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
141 { VA_C4(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE }, 139 { VA_C4(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
142 { VA_C4(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE }, 140 { VA_C4(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
@@ -146,7 +144,6 @@ static struct map_desc bast_iodesc[] __initdata = {
146 /* fast, word */ 144 /* fast, word */
147 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, 145 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
148 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, 146 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
149 { VA_C5(BAST_VA_ASIXNET), PA_CS5(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
150 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, 147 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
151 { VA_C5(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE }, 148 { VA_C5(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
152 { VA_C5(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE }, 149 { VA_C5(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
diff --git a/arch/arm/mach-s3c2410/s3c2440-clock.c b/arch/arm/mach-s3c2410/s3c2440-clock.c
new file mode 100644
index 000000000000..b018a1f680ce
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c2440-clock.c
@@ -0,0 +1,116 @@
1/* linux/arch/arm/mach-s3c2410/s3c2440-clock.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2440 Clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/sysdev.h>
32
33#include <linux/interrupt.h>
34#include <linux/ioport.h>
35
36#include <asm/hardware.h>
37#include <asm/atomic.h>
38#include <asm/irq.h>
39#include <asm/io.h>
40
41#include <asm/hardware/clock.h>
42#include <asm/arch/regs-clock.h>
43
44#include "clock.h"
45#include "cpu.h"
46
47/* S3C2440 extended clock support */
48
49static struct clk s3c2440_clk_upll = {
50 .name = "upll",
51 .id = -1,
52};
53
54static struct clk s3c2440_clk_cam = {
55 .name = "camif",
56 .id = -1,
57 .enable = s3c24xx_clkcon_enable,
58 .ctrlbit = S3C2440_CLKCON_CAMERA,
59};
60
61static struct clk s3c2440_clk_ac97 = {
62 .name = "ac97",
63 .id = -1,
64 .enable = s3c24xx_clkcon_enable,
65 .ctrlbit = S3C2440_CLKCON_CAMERA,
66};
67
68static int s3c2440_clk_add(struct sys_device *sysdev)
69{
70 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
71 struct clk *clk_h;
72 struct clk *clk_p;
73 struct clk *clk_xtal;
74
75 clk_xtal = clk_get(NULL, "xtal");
76 if (IS_ERR(clk_xtal)) {
77 printk(KERN_ERR "S3C2440: Failed to get clk_xtal\n");
78 return -EINVAL;
79 }
80
81 s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate);
82
83 printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n",
84 print_mhz(s3c2440_clk_upll.rate));
85
86 clk_p = clk_get(NULL, "pclk");
87 clk_h = clk_get(NULL, "hclk");
88
89 if (IS_ERR(clk_p) || IS_ERR(clk_h)) {
90 printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
91 return -EINVAL;
92 }
93
94 s3c2440_clk_cam.parent = clk_h;
95 s3c2440_clk_ac97.parent = clk_p;
96
97 s3c24xx_register_clock(&s3c2440_clk_ac97);
98 s3c24xx_register_clock(&s3c2440_clk_cam);
99 s3c24xx_register_clock(&s3c2440_clk_upll);
100
101 clk_disable(&s3c2440_clk_ac97);
102 clk_disable(&s3c2440_clk_cam);
103
104 return 0;
105}
106
107static struct sysdev_driver s3c2440_clk_driver = {
108 .add = s3c2440_clk_add,
109};
110
111static __init int s3c24xx_clk_driver(void)
112{
113 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
114}
115
116arch_initcall(s3c24xx_clk_driver);
diff --git a/arch/arm/mach-s3c2410/s3c2440-irq.c b/arch/arm/mach-s3c2410/s3c2440-irq.c
new file mode 100644
index 000000000000..7cb9912242a3
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c2440-irq.c
@@ -0,0 +1,207 @@
1/* linux/arch/arm/mach-s3c2410/s3c2440-irq.c
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * Changelog:
21 * 25-Jul-2005 BJD Split from irq.c
22 *
23*/
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/interrupt.h>
28#include <linux/ioport.h>
29#include <linux/ptrace.h>
30#include <linux/sysdev.h>
31
32#include <asm/hardware.h>
33#include <asm/irq.h>
34#include <asm/io.h>
35
36#include <asm/mach/irq.h>
37
38#include <asm/arch/regs-irq.h>
39#include <asm/arch/regs-gpio.h>
40
41#include "cpu.h"
42#include "pm.h"
43#include "irq.h"
44
45/* WDT/AC97 */
46
47static void s3c_irq_demux_wdtac97(unsigned int irq,
48 struct irqdesc *desc,
49 struct pt_regs *regs)
50{
51 unsigned int subsrc, submsk;
52 struct irqdesc *mydesc;
53
54 /* read the current pending interrupts, and the mask
55 * for what it is available */
56
57 subsrc = __raw_readl(S3C2410_SUBSRCPND);
58 submsk = __raw_readl(S3C2410_INTSUBMSK);
59
60 subsrc &= ~submsk;
61 subsrc >>= 13;
62 subsrc &= 3;
63
64 if (subsrc != 0) {
65 if (subsrc & 1) {
66 mydesc = irq_desc + IRQ_S3C2440_WDT;
67 mydesc->handle( IRQ_S3C2440_WDT, mydesc, regs);
68 }
69 if (subsrc & 2) {
70 mydesc = irq_desc + IRQ_S3C2440_AC97;
71 mydesc->handle(IRQ_S3C2440_AC97, mydesc, regs);
72 }
73 }
74}
75
76
77#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0))
78
79static void
80s3c_irq_wdtac97_mask(unsigned int irqno)
81{
82 s3c_irqsub_mask(irqno, INTMSK_WDT, 3<<13);
83}
84
85static void
86s3c_irq_wdtac97_unmask(unsigned int irqno)
87{
88 s3c_irqsub_unmask(irqno, INTMSK_WDT);
89}
90
91static void
92s3c_irq_wdtac97_ack(unsigned int irqno)
93{
94 s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
95}
96
97static struct irqchip s3c_irq_wdtac97 = {
98 .mask = s3c_irq_wdtac97_mask,
99 .unmask = s3c_irq_wdtac97_unmask,
100 .ack = s3c_irq_wdtac97_ack,
101};
102
103/* camera irq */
104
105static void s3c_irq_demux_cam(unsigned int irq,
106 struct irqdesc *desc,
107 struct pt_regs *regs)
108{
109 unsigned int subsrc, submsk;
110 struct irqdesc *mydesc;
111
112 /* read the current pending interrupts, and the mask
113 * for what it is available */
114
115 subsrc = __raw_readl(S3C2410_SUBSRCPND);
116 submsk = __raw_readl(S3C2410_INTSUBMSK);
117
118 subsrc &= ~submsk;
119 subsrc >>= 11;
120 subsrc &= 3;
121
122 if (subsrc != 0) {
123 if (subsrc & 1) {
124 mydesc = irq_desc + IRQ_S3C2440_CAM_C;
125 mydesc->handle( IRQ_S3C2440_WDT, mydesc, regs);
126 }
127 if (subsrc & 2) {
128 mydesc = irq_desc + IRQ_S3C2440_CAM_P;
129 mydesc->handle(IRQ_S3C2440_AC97, mydesc, regs);
130 }
131 }
132}
133
134#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
135
136static void
137s3c_irq_cam_mask(unsigned int irqno)
138{
139 s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11);
140}
141
142static void
143s3c_irq_cam_unmask(unsigned int irqno)
144{
145 s3c_irqsub_unmask(irqno, INTMSK_CAM);
146}
147
148static void
149s3c_irq_cam_ack(unsigned int irqno)
150{
151 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
152}
153
154static struct irqchip s3c_irq_cam = {
155 .mask = s3c_irq_cam_mask,
156 .unmask = s3c_irq_cam_unmask,
157 .ack = s3c_irq_cam_ack,
158};
159
160static int s3c2440_irq_add(struct sys_device *sysdev)
161{
162 unsigned int irqno;
163
164 printk("S3C2440: IRQ Support\n");
165
166 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
167 set_irq_handler(IRQ_NFCON, do_level_IRQ);
168 set_irq_flags(IRQ_NFCON, IRQF_VALID);
169
170 /* add new chained handler for wdt, ac7 */
171
172 set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
173 set_irq_handler(IRQ_WDT, do_level_IRQ);
174 set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
175
176 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
177 set_irq_chip(irqno, &s3c_irq_wdtac97);
178 set_irq_handler(irqno, do_level_IRQ);
179 set_irq_flags(irqno, IRQF_VALID);
180 }
181
182 /* add chained handler for camera */
183
184 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
185 set_irq_handler(IRQ_CAM, do_level_IRQ);
186 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
187
188 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
189 set_irq_chip(irqno, &s3c_irq_cam);
190 set_irq_handler(irqno, do_level_IRQ);
191 set_irq_flags(irqno, IRQF_VALID);
192 }
193
194 return 0;
195}
196
197static struct sysdev_driver s3c2440_irq_driver = {
198 .add = s3c2440_irq_add,
199};
200
201static int s3c24xx_irq_driver(void)
202{
203 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
204}
205
206arch_initcall(s3c24xx_irq_driver);
207
diff --git a/drivers/pcmcia/sa1100_jornada720.c b/drivers/pcmcia/sa1100_jornada720.c
index 0a387106acb0..7a87298bae99 100644
--- a/drivers/pcmcia/sa1100_jornada720.c
+++ b/drivers/pcmcia/sa1100_jornada720.c
@@ -30,20 +30,9 @@ static int jornada720_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
30 */ 30 */
31 GRER |= 0x00000002; 31 GRER |= 0x00000002;
32 /* Set GPIO_A<3:1> to be outputs for PCMCIA/CF power controller: */ 32 /* Set GPIO_A<3:1> to be outputs for PCMCIA/CF power controller: */
33 PA_DDR = 0; 33 sa1111_set_io_dir(SA1111_DEV(skt->dev), GPIO_A0|GPIO_A1|GPIO_A2|GPIO_A3, 0, 0);
34 PA_DWR = 0; 34 sa1111_set_io(SA1111_DEV(skt->dev), GPIO_A0|GPIO_A1|GPIO_A2|GPIO_A3, 0);
35 PA_SDR = 0; 35 sa1111_set_sleep_io(SA1111_DEV(skt->dev), GPIO_A0|GPIO_A1|GPIO_A2|GPIO_A3, 0);
36 PA_SSR = 0;
37
38 PB_DDR = 0;
39 PB_DWR = 0x01;
40 PB_SDR = 0;
41 PB_SSR = 0;
42
43 PC_DDR = 0x88;
44 PC_DWR = 0x20;
45 PC_SDR = 0;
46 PC_SSR = 0;
47 36
48 return sa1111_pcmcia_hw_init(skt); 37 return sa1111_pcmcia_hw_init(skt);
49} 38}
@@ -95,7 +84,7 @@ printk("%s(): config socket %d vcc %d vpp %d\n", __FUNCTION__,
95 unsigned long flags; 84 unsigned long flags;
96 85
97 local_irq_save(flags); 86 local_irq_save(flags);
98 PA_DWR = (PA_DWR & ~pa_dwr_mask) | pa_dwr_set; 87 sa1111_set_io(SA1111_DEV(skt->dev), pa_dwr_mask, pa_dwr_set);
99 local_irq_restore(flags); 88 local_irq_restore(flags);
100 } 89 }
101 90
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h
index 385b07d510da..fdd62e8cd6cb 100644
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ b/include/asm-arm/arch-s3c2410/regs-iis.h
@@ -15,6 +15,9 @@
15 * 12-03-2004 BJD Updated include protection 15 * 12-03-2004 BJD Updated include protection
16 * 07-03-2005 BJD Added FIFO size flags and S3C2440 MPLL 16 * 07-03-2005 BJD Added FIFO size flags and S3C2440 MPLL
17 * 05-04-2005 LCVR Added IISFCON definitions for the S3C2400 17 * 05-04-2005 LCVR Added IISFCON definitions for the S3C2400
18 * 18-07-2005 DA Change IISCON_MPLL to IISMOD_MPLL
19 * Correct IISMOD_256FS and IISMOD_384FS
20 * Add IISCON_PSCEN
18 */ 21 */
19 22
20#ifndef __ASM_ARCH_REGS_IIS_H 23#ifndef __ASM_ARCH_REGS_IIS_H
@@ -22,7 +25,6 @@
22 25
23#define S3C2410_IISCON (0x00) 26#define S3C2410_IISCON (0x00)
24 27
25#define S3C2440_IISCON_MPLL (1<<9)
26#define S3C2410_IISCON_LRINDEX (1<<8) 28#define S3C2410_IISCON_LRINDEX (1<<8)
27#define S3C2410_IISCON_TXFIFORDY (1<<7) 29#define S3C2410_IISCON_TXFIFORDY (1<<7)
28#define S3C2410_IISCON_RXFIFORDY (1<<6) 30#define S3C2410_IISCON_RXFIFORDY (1<<6)
@@ -30,10 +32,12 @@
30#define S3C2410_IISCON_RXDMAEN (1<<4) 32#define S3C2410_IISCON_RXDMAEN (1<<4)
31#define S3C2410_IISCON_TXIDLE (1<<3) 33#define S3C2410_IISCON_TXIDLE (1<<3)
32#define S3C2410_IISCON_RXIDLE (1<<2) 34#define S3C2410_IISCON_RXIDLE (1<<2)
35#define S3C2410_IISCON_PSCEN (1<<1)
33#define S3C2410_IISCON_IISEN (1<<0) 36#define S3C2410_IISCON_IISEN (1<<0)
34 37
35#define S3C2410_IISMOD (0x04) 38#define S3C2410_IISMOD (0x04)
36 39
40#define S3C2440_IISMOD_MPLL (1<<9)
37#define S3C2410_IISMOD_SLAVE (1<<8) 41#define S3C2410_IISMOD_SLAVE (1<<8)
38#define S3C2410_IISMOD_NOXFER (0<<6) 42#define S3C2410_IISMOD_NOXFER (0<<6)
39#define S3C2410_IISMOD_RXMODE (1<<6) 43#define S3C2410_IISMOD_RXMODE (1<<6)
@@ -46,8 +50,8 @@
46#define S3C2410_IISMOD_8BIT (0<<3) 50#define S3C2410_IISMOD_8BIT (0<<3)
47#define S3C2410_IISMOD_16BIT (1<<3) 51#define S3C2410_IISMOD_16BIT (1<<3)
48#define S3C2410_IISMOD_BITMASK (1<<3) 52#define S3C2410_IISMOD_BITMASK (1<<3)
49#define S3C2410_IISMOD_256FS (0<<1) 53#define S3C2410_IISMOD_256FS (0<<2)
50#define S3C2410_IISMOD_384FS (1<<1) 54#define S3C2410_IISMOD_384FS (1<<2)
51#define S3C2410_IISMOD_16FS (0<<0) 55#define S3C2410_IISMOD_16FS (0<<0)
52#define S3C2410_IISMOD_32FS (1<<0) 56#define S3C2410_IISMOD_32FS (1<<0)
53#define S3C2410_IISMOD_48FS (2<<0) 57#define S3C2410_IISMOD_48FS (2<<0)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 19:01:26 -0500