diff options
author | Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> | 2009-06-15 04:24:40 -0400 |
---|---|---|
committer | H. Peter Anvin <hpa@zytor.com> | 2009-06-16 19:56:08 -0400 |
commit | e8ce2c5ee826b3787202493effcd08d4b1e1e639 (patch) | |
tree | 45dfcd93086820963d196d88851d772d11b2f8e9 | |
parent | 5335612a574a45beab14193ec641ed2f45e7a523 (diff) |
x86, mce: unify smp_thermal_interrupt, prepare
Let them in same shape.
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
-rw-r--r-- | arch/x86/include/asm/mce.h | 25 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/mcheck/mce_intel_64.c | 20 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/mcheck/p4.c | 10 |
3 files changed, 38 insertions, 17 deletions
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 6568cdedcd89..3bc827c0f409 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h | |||
@@ -110,6 +110,7 @@ extern int mce_disabled; | |||
110 | extern int mce_p5_enabled; | 110 | extern int mce_p5_enabled; |
111 | 111 | ||
112 | #ifdef CONFIG_X86_OLD_MCE | 112 | #ifdef CONFIG_X86_OLD_MCE |
113 | extern int nr_mce_banks; | ||
113 | void amd_mcheck_init(struct cpuinfo_x86 *c); | 114 | void amd_mcheck_init(struct cpuinfo_x86 *c); |
114 | void intel_p4_mcheck_init(struct cpuinfo_x86 *c); | 115 | void intel_p4_mcheck_init(struct cpuinfo_x86 *c); |
115 | void intel_p6_mcheck_init(struct cpuinfo_x86 *c); | 116 | void intel_p6_mcheck_init(struct cpuinfo_x86 *c); |
@@ -128,15 +129,6 @@ static inline void enable_p5_mce(void) {} | |||
128 | /* Call the installed machine check handler for this CPU setup. */ | 129 | /* Call the installed machine check handler for this CPU setup. */ |
129 | extern void (*machine_check_vector)(struct pt_regs *, long error_code); | 130 | extern void (*machine_check_vector)(struct pt_regs *, long error_code); |
130 | 131 | ||
131 | #ifdef CONFIG_X86_OLD_MCE | ||
132 | extern int nr_mce_banks; | ||
133 | extern void intel_set_thermal_handler(void); | ||
134 | #else | ||
135 | static inline void intel_set_thermal_handler(void) { } | ||
136 | #endif | ||
137 | |||
138 | void intel_init_thermal(struct cpuinfo_x86 *c); | ||
139 | |||
140 | void mce_setup(struct mce *m); | 132 | void mce_setup(struct mce *m); |
141 | void mce_log(struct mce *m); | 133 | void mce_log(struct mce *m); |
142 | DECLARE_PER_CPU(struct sys_device, mce_dev); | 134 | DECLARE_PER_CPU(struct sys_device, mce_dev); |
@@ -175,8 +167,6 @@ int mce_available(struct cpuinfo_x86 *c); | |||
175 | DECLARE_PER_CPU(unsigned, mce_exception_count); | 167 | DECLARE_PER_CPU(unsigned, mce_exception_count); |
176 | DECLARE_PER_CPU(unsigned, mce_poll_count); | 168 | DECLARE_PER_CPU(unsigned, mce_poll_count); |
177 | 169 | ||
178 | void mce_log_therm_throt_event(__u64 status); | ||
179 | |||
180 | extern atomic_t mce_entry; | 170 | extern atomic_t mce_entry; |
181 | 171 | ||
182 | void do_machine_check(struct pt_regs *, long); | 172 | void do_machine_check(struct pt_regs *, long); |
@@ -205,5 +195,18 @@ void mcheck_init(struct cpuinfo_x86 *c); | |||
205 | 195 | ||
206 | extern void (*mce_threshold_vector)(void); | 196 | extern void (*mce_threshold_vector)(void); |
207 | 197 | ||
198 | /* | ||
199 | * Thermal handler | ||
200 | */ | ||
201 | |||
202 | void intel_set_thermal_handler(void); | ||
203 | void intel_init_thermal(struct cpuinfo_x86 *c); | ||
204 | |||
205 | #ifdef CONFIG_X86_NEW_MCE | ||
206 | void mce_log_therm_throt_event(__u64 status); | ||
207 | #else | ||
208 | static inline void mce_log_therm_throt_event(__u64 status) {} | ||
209 | #endif | ||
210 | |||
208 | #endif /* __KERNEL__ */ | 211 | #endif /* __KERNEL__ */ |
209 | #endif /* _ASM_X86_MCE_H */ | 212 | #endif /* _ASM_X86_MCE_H */ |
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c index a5232b2c4ca0..922e3a482f6f 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c | |||
@@ -16,6 +16,14 @@ | |||
16 | #include <asm/idle.h> | 16 | #include <asm/idle.h> |
17 | #include <asm/therm_throt.h> | 17 | #include <asm/therm_throt.h> |
18 | 18 | ||
19 | static void unexpected_thermal_interrupt(void) | ||
20 | { | ||
21 | printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n", | ||
22 | smp_processor_id()); | ||
23 | add_taint(TAINT_MACHINE_CHECK); | ||
24 | } | ||
25 | |||
26 | /* P4/Xeon Thermal transition interrupt handler: */ | ||
19 | static void intel_thermal_interrupt(void) | 27 | static void intel_thermal_interrupt(void) |
20 | { | 28 | { |
21 | __u64 msr_val; | 29 | __u64 msr_val; |
@@ -25,14 +33,22 @@ static void intel_thermal_interrupt(void) | |||
25 | mce_log_therm_throt_event(msr_val); | 33 | mce_log_therm_throt_event(msr_val); |
26 | } | 34 | } |
27 | 35 | ||
36 | /* Thermal interrupt handler for this CPU setup: */ | ||
37 | static void (*vendor_thermal_interrupt)(void) = unexpected_thermal_interrupt; | ||
38 | |||
28 | asmlinkage void smp_thermal_interrupt(void) | 39 | asmlinkage void smp_thermal_interrupt(void) |
29 | { | 40 | { |
30 | ack_APIC_irq(); | ||
31 | exit_idle(); | 41 | exit_idle(); |
32 | irq_enter(); | 42 | irq_enter(); |
33 | intel_thermal_interrupt(); | ||
34 | inc_irq_stat(irq_thermal_count); | 43 | inc_irq_stat(irq_thermal_count); |
44 | intel_thermal_interrupt(); | ||
35 | irq_exit(); | 45 | irq_exit(); |
46 | ack_APIC_irq(); | ||
47 | } | ||
48 | |||
49 | void intel_set_thermal_handler(void) | ||
50 | { | ||
51 | vendor_thermal_interrupt = intel_thermal_interrupt; | ||
36 | } | 52 | } |
37 | 53 | ||
38 | /* | 54 | /* |
diff --git a/arch/x86/kernel/cpu/mcheck/p4.c b/arch/x86/kernel/cpu/mcheck/p4.c index ddeed6e295af..75313f5b624e 100644 --- a/arch/x86/kernel/cpu/mcheck/p4.c +++ b/arch/x86/kernel/cpu/mcheck/p4.c | |||
@@ -12,6 +12,7 @@ | |||
12 | #include <asm/processor.h> | 12 | #include <asm/processor.h> |
13 | #include <asm/system.h> | 13 | #include <asm/system.h> |
14 | #include <asm/apic.h> | 14 | #include <asm/apic.h> |
15 | #include <asm/idle.h> | ||
15 | #include <asm/mce.h> | 16 | #include <asm/mce.h> |
16 | #include <asm/msr.h> | 17 | #include <asm/msr.h> |
17 | 18 | ||
@@ -47,10 +48,9 @@ static void intel_thermal_interrupt(void) | |||
47 | { | 48 | { |
48 | __u64 msr_val; | 49 | __u64 msr_val; |
49 | 50 | ||
50 | ack_APIC_irq(); | ||
51 | |||
52 | rdmsrl(MSR_IA32_THERM_STATUS, msr_val); | 51 | rdmsrl(MSR_IA32_THERM_STATUS, msr_val); |
53 | therm_throt_process(msr_val & THERM_STATUS_PROCHOT); | 52 | if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT)) |
53 | mce_log_therm_throt_event(msr_val); | ||
54 | } | 54 | } |
55 | 55 | ||
56 | /* Thermal interrupt handler for this CPU setup: */ | 56 | /* Thermal interrupt handler for this CPU setup: */ |
@@ -58,10 +58,12 @@ static void (*vendor_thermal_interrupt)(void) = unexpected_thermal_interrupt; | |||
58 | 58 | ||
59 | void smp_thermal_interrupt(struct pt_regs *regs) | 59 | void smp_thermal_interrupt(struct pt_regs *regs) |
60 | { | 60 | { |
61 | exit_idle(); | ||
61 | irq_enter(); | 62 | irq_enter(); |
62 | vendor_thermal_interrupt(); | ||
63 | inc_irq_stat(irq_thermal_count); | 63 | inc_irq_stat(irq_thermal_count); |
64 | vendor_thermal_interrupt(); | ||
64 | irq_exit(); | 65 | irq_exit(); |
66 | ack_APIC_irq(); | ||
65 | } | 67 | } |
66 | 68 | ||
67 | void intel_set_thermal_handler(void) | 69 | void intel_set_thermal_handler(void) |