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authorJiri Slaby <jirislaby@gmail.com>2007-05-08 03:35:46 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-08 14:15:22 -0400
commitdb05c3b1ddaa06e658548f3d99e31a188b0b3bcc (patch)
tree5b645d4da752988c21b6a66c7afe8a34f994c8df
parentffa68e79ffa952ec909b66505f004e7323316369 (diff)
Char: cyclades, cy_readX/writeX cleanup
cyclades, cy_readX/writeX cleanup - cy_readX are placeholders for readX, remove it - move cy_writeX macros into do {} while(0) to be safe Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat
-rw-r--r--drivers/char/cyclades.c315
-rw-r--r--include/linux/cyclades.h10
2 files changed, 153 insertions, 172 deletions
diff --git a/drivers/char/cyclades.c b/drivers/char/cyclades.c
index 3b62962b3512..9bf0fb2fa0d4 100644
--- a/drivers/char/cyclades.c
+++ b/drivers/char/cyclades.c
@@ -675,13 +675,13 @@ static void cy_send_xchar(struct tty_struct *tty, char ch);
675#define IS_CYC_Z(card) ((card).num_chips == -1) 675#define IS_CYC_Z(card) ((card).num_chips == -1)
676 676
677#define Z_FPGA_CHECK(card) \ 677#define Z_FPGA_CHECK(card) \
678 ((cy_readl(&((struct RUNTIME_9060 __iomem *) \ 678 ((readl(&((struct RUNTIME_9060 __iomem *) \
679 ((card).ctl_addr))->init_ctrl) & (1<<17)) != 0) 679 ((card).ctl_addr))->init_ctrl) & (1<<17)) != 0)
680 680
681#define ISZLOADED(card) (((ZO_V1==cy_readl(&((struct RUNTIME_9060 __iomem *) \ 681#define ISZLOADED(card) (((ZO_V1==readl(&((struct RUNTIME_9060 __iomem *) \
682 ((card).ctl_addr))->mail_box_0)) || \ 682 ((card).ctl_addr))->mail_box_0)) || \
683 Z_FPGA_CHECK(card)) && \ 683 Z_FPGA_CHECK(card)) && \
684 (ZFIRM_ID==cy_readl(&((struct FIRM_ID __iomem *) \ 684 (ZFIRM_ID==readl(&((struct FIRM_ID __iomem *) \
685 ((card).base_addr+ID_ADDRESS))->signature))) 685 ((card).base_addr+ID_ADDRESS))->signature)))
686 686
687#ifndef SERIAL_XMIT_SIZE 687#ifndef SERIAL_XMIT_SIZE
@@ -972,7 +972,7 @@ static int cyy_issue_cmd(void __iomem * base_addr, u_char cmd, int index)
972 972
973 /* Check to see that the previous command has completed */ 973 /* Check to see that the previous command has completed */
974 for (i = 0; i < 100; i++) { 974 for (i = 0; i < 100; i++) {
975 if (cy_readb(base_addr + (CyCCR << index)) == 0) { 975 if (readb(base_addr + (CyCCR << index)) == 0) {
976 break; 976 break;
977 } 977 }
978 udelay(10L); 978 udelay(10L);
@@ -1015,7 +1015,7 @@ static unsigned detect_isa_irq(void __iomem * address)
1015 1015
1016 cy_writeb(address + (CyCAR << index), 0); 1016 cy_writeb(address + (CyCAR << index), 0);
1017 cy_writeb(address + (CySRER << index), 1017 cy_writeb(address + (CySRER << index),
1018 cy_readb(address + (CySRER << index)) | CyTxRdy); 1018 readb(address + (CySRER << index)) | CyTxRdy);
1019 local_irq_restore(flags); 1019 local_irq_restore(flags);
1020 1020
1021 /* Wait ... */ 1021 /* Wait ... */
@@ -1025,11 +1025,11 @@ static unsigned detect_isa_irq(void __iomem * address)
1025 irq = probe_irq_off(irqs); 1025 irq = probe_irq_off(irqs);
1026 1026
1027 /* Clean up */ 1027 /* Clean up */
1028 save_xir = (u_char) cy_readb(address + (CyTIR << index)); 1028 save_xir = (u_char) readb(address + (CyTIR << index));
1029 save_car = cy_readb(address + (CyCAR << index)); 1029 save_car = readb(address + (CyCAR << index));
1030 cy_writeb(address + (CyCAR << index), (save_xir & 0x3)); 1030 cy_writeb(address + (CyCAR << index), (save_xir & 0x3));
1031 cy_writeb(address + (CySRER << index), 1031 cy_writeb(address + (CySRER << index),
1032 cy_readb(address + (CySRER << index)) & ~CyTxRdy); 1032 readb(address + (CySRER << index)) & ~CyTxRdy);
1033 cy_writeb(address + (CyTIR << index), (save_xir & 0x3f)); 1033 cy_writeb(address + (CyTIR << index), (save_xir & 0x3f));
1034 cy_writeb(address + (CyCAR << index), (save_car)); 1034 cy_writeb(address + (CyCAR << index), (save_car));
1035 cy_writeb(address + (Cy_ClrIntr << index), 0); 1035 cy_writeb(address + (Cy_ClrIntr << index), 0);
@@ -1055,34 +1055,34 @@ static void cyy_intr_chip(struct cyclades_card *cinfo, int chip,
1055#endif 1055#endif
1056 /* determine the channel & change to that context */ 1056 /* determine the channel & change to that context */
1057 spin_lock(&cinfo->card_lock); 1057 spin_lock(&cinfo->card_lock);
1058 save_xir = (u_char) cy_readb(base_addr + (CyRIR << index)); 1058 save_xir = (u_char) readb(base_addr + (CyRIR << index));
1059 channel = (u_short) (save_xir & CyIRChannel); 1059 channel = (u_short) (save_xir & CyIRChannel);
1060 i = channel + chip * 4 + cinfo->first_line; 1060 i = channel + chip * 4 + cinfo->first_line;
1061 info = &cy_port[i]; 1061 info = &cy_port[i];
1062 info->last_active = jiffies; 1062 info->last_active = jiffies;
1063 save_car = cy_readb(base_addr + (CyCAR << index)); 1063 save_car = readb(base_addr + (CyCAR << index));
1064 cy_writeb(base_addr + (CyCAR << index), save_xir); 1064 cy_writeb(base_addr + (CyCAR << index), save_xir);
1065 1065
1066 /* if there is nowhere to put the data, discard it */ 1066 /* if there is nowhere to put the data, discard it */
1067 if (info->tty == 0) { 1067 if (info->tty == 0) {
1068 j = (cy_readb(base_addr + (CyRIVR << index)) & 1068 j = (readb(base_addr + (CyRIVR << index)) &
1069 CyIVRMask); 1069 CyIVRMask);
1070 if (j == CyIVRRxEx) { /* exception */ 1070 if (j == CyIVRRxEx) { /* exception */
1071 data = cy_readb(base_addr + (CyRDSR << index)); 1071 data = readb(base_addr + (CyRDSR << index));
1072 } else { /* normal character reception */ 1072 } else { /* normal character reception */
1073 char_count = cy_readb(base_addr + 1073 char_count = readb(base_addr +
1074 (CyRDCR << index)); 1074 (CyRDCR << index));
1075 while (char_count--) { 1075 while (char_count--) {
1076 data = cy_readb(base_addr + 1076 data = readb(base_addr +
1077 (CyRDSR << index)); 1077 (CyRDSR << index));
1078 } 1078 }
1079 } 1079 }
1080 } else { /* there is an open port for this data */ 1080 } else { /* there is an open port for this data */
1081 tty = info->tty; 1081 tty = info->tty;
1082 j = (cy_readb(base_addr + (CyRIVR << index)) & 1082 j = (readb(base_addr + (CyRIVR << index)) &
1083 CyIVRMask); 1083 CyIVRMask);
1084 if (j == CyIVRRxEx) { /* exception */ 1084 if (j == CyIVRRxEx) { /* exception */
1085 data = cy_readb(base_addr + (CyRDSR << index)); 1085 data = readb(base_addr + (CyRDSR << index));
1086 1086
1087 /* For statistics only */ 1087 /* For statistics only */
1088 if (data & CyBREAK) 1088 if (data & CyBREAK)
@@ -1103,7 +1103,7 @@ static void cyy_intr_chip(struct cyclades_card *cinfo, int chip,
1103 if (data & CyBREAK) { 1103 if (data & CyBREAK) {
1104 tty_insert_flip_char( 1104 tty_insert_flip_char(
1105 tty, 1105 tty,
1106 cy_readb( 1106 readb(
1107 base_addr + 1107 base_addr +
1108 (CyRDSR << 1108 (CyRDSR <<
1109 index)), 1109 index)),
@@ -1116,7 +1116,7 @@ static void cyy_intr_chip(struct cyclades_card *cinfo, int chip,
1116 } else if (data & CyFRAME) { 1116 } else if (data & CyFRAME) {
1117 tty_insert_flip_char( 1117 tty_insert_flip_char(
1118 tty, 1118 tty,
1119 cy_readb( 1119 readb(
1120 base_addr + 1120 base_addr +
1121 (CyRDSR << 1121 (CyRDSR <<
1122 index)), 1122 index)),
@@ -1128,7 +1128,7 @@ static void cyy_intr_chip(struct cyclades_card *cinfo, int chip,
1128 /* Pieces of seven... */ 1128 /* Pieces of seven... */
1129 tty_insert_flip_char( 1129 tty_insert_flip_char(
1130 tty, 1130 tty,
1131 cy_readb( 1131 readb(
1132 base_addr + 1132 base_addr +
1133 (CyRDSR << 1133 (CyRDSR <<
1134 index)), 1134 index)),
@@ -1147,7 +1147,7 @@ static void cyy_intr_chip(struct cyclades_card *cinfo, int chip,
1147 */ 1147 */
1148 tty_insert_flip_char( 1148 tty_insert_flip_char(
1149 tty, 1149 tty,
1150 cy_readb( 1150 readb(
1151 base_addr + 1151 base_addr +
1152 (CyRDSR << 1152 (CyRDSR <<
1153 index)), 1153 index)),
@@ -1179,7 +1179,7 @@ static void cyy_intr_chip(struct cyclades_card *cinfo, int chip,
1179 } 1179 }
1180 } else { /* normal character reception */ 1180 } else { /* normal character reception */
1181 /* load # chars available from the chip */ 1181 /* load # chars available from the chip */
1182 char_count = cy_readb(base_addr + 1182 char_count = readb(base_addr +
1183 (CyRDCR << index)); 1183 (CyRDCR << index));
1184 1184
1185#ifdef CY_ENABLE_MONITORING 1185#ifdef CY_ENABLE_MONITORING
@@ -1191,7 +1191,7 @@ static void cyy_intr_chip(struct cyclades_card *cinfo, int chip,
1191#endif 1191#endif
1192 len = tty_buffer_request_room(tty, char_count); 1192 len = tty_buffer_request_room(tty, char_count);
1193 while (len--) { 1193 while (len--) {
1194 data = cy_readb(base_addr + 1194 data = readb(base_addr +
1195 (CyRDSR << index)); 1195 (CyRDSR << index));
1196 tty_insert_flip_char(tty, data, 1196 tty_insert_flip_char(tty, data,
1197 TTY_NORMAL); 1197 TTY_NORMAL);
@@ -1221,16 +1221,16 @@ static void cyy_intr_chip(struct cyclades_card *cinfo, int chip,
1221 1221
1222 /* determine the channel & change to that context */ 1222 /* determine the channel & change to that context */
1223 spin_lock(&cinfo->card_lock); 1223 spin_lock(&cinfo->card_lock);
1224 save_xir = (u_char) cy_readb(base_addr + (CyTIR << index)); 1224 save_xir = (u_char) readb(base_addr + (CyTIR << index));
1225 channel = (u_short) (save_xir & CyIRChannel); 1225 channel = (u_short) (save_xir & CyIRChannel);
1226 i = channel + chip * 4 + cinfo->first_line; 1226 i = channel + chip * 4 + cinfo->first_line;
1227 save_car = cy_readb(base_addr + (CyCAR << index)); 1227 save_car = readb(base_addr + (CyCAR << index));
1228 cy_writeb(base_addr + (CyCAR << index), save_xir); 1228 cy_writeb(base_addr + (CyCAR << index), save_xir);
1229 1229
1230 /* validate the port# (as configured and open) */ 1230 /* validate the port# (as configured and open) */
1231 if ((i < 0) || (NR_PORTS <= i)) { 1231 if ((i < 0) || (NR_PORTS <= i)) {
1232 cy_writeb(base_addr + (CySRER << index), 1232 cy_writeb(base_addr + (CySRER << index),
1233 cy_readb(base_addr + (CySRER << index)) & 1233 readb(base_addr + (CySRER << index)) &
1234 ~CyTxRdy); 1234 ~CyTxRdy);
1235 goto txend; 1235 goto txend;
1236 } 1236 }
@@ -1238,7 +1238,7 @@ static void cyy_intr_chip(struct cyclades_card *cinfo, int chip,
1238 info->last_active = jiffies; 1238 info->last_active = jiffies;
1239 if (info->tty == 0) { 1239 if (info->tty == 0) {
1240 cy_writeb(base_addr + (CySRER << index), 1240 cy_writeb(base_addr + (CySRER << index),
1241 cy_readb(base_addr + (CySRER << index)) & 1241 readb(base_addr + (CySRER << index)) &
1242 ~CyTxRdy); 1242 ~CyTxRdy);
1243 goto txdone; 1243 goto txdone;
1244 } 1244 }
@@ -1271,15 +1271,15 @@ static void cyy_intr_chip(struct cyclades_card *cinfo, int chip,
1271 1271
1272 while (char_count-- > 0) { 1272 while (char_count-- > 0) {
1273 if (!info->xmit_cnt) { 1273 if (!info->xmit_cnt) {
1274 if (cy_readb(base_addr + (CySRER << index)) & 1274 if (readb(base_addr + (CySRER << index)) &
1275 CyTxMpty) { 1275 CyTxMpty) {
1276 cy_writeb(base_addr + (CySRER << index), 1276 cy_writeb(base_addr + (CySRER << index),
1277 cy_readb(base_addr + 1277 readb(base_addr +
1278 (CySRER << index)) & 1278 (CySRER << index)) &
1279 ~CyTxMpty); 1279 ~CyTxMpty);
1280 } else { 1280 } else {
1281 cy_writeb(base_addr + (CySRER << index), 1281 cy_writeb(base_addr + (CySRER << index),
1282 (cy_readb(base_addr + 1282 (readb(base_addr +
1283 (CySRER << index)) & 1283 (CySRER << index)) &
1284 ~CyTxRdy) | CyTxMpty); 1284 ~CyTxRdy) | CyTxMpty);
1285 } 1285 }
@@ -1287,13 +1287,13 @@ static void cyy_intr_chip(struct cyclades_card *cinfo, int chip,
1287 } 1287 }
1288 if (info->xmit_buf == 0) { 1288 if (info->xmit_buf == 0) {
1289 cy_writeb(base_addr + (CySRER << index), 1289 cy_writeb(base_addr + (CySRER << index),
1290 cy_readb(base_addr + (CySRER << index))& 1290 readb(base_addr + (CySRER << index)) &
1291 ~CyTxRdy); 1291 ~CyTxRdy);
1292 goto txdone; 1292 goto txdone;
1293 } 1293 }
1294 if (info->tty->stopped || info->tty->hw_stopped) { 1294 if (info->tty->stopped || info->tty->hw_stopped) {
1295 cy_writeb(base_addr + (CySRER << index), 1295 cy_writeb(base_addr + (CySRER << index),
1296 cy_readb(base_addr + (CySRER << index))& 1296 readb(base_addr + (CySRER << index)) &
1297 ~CyTxRdy); 1297 ~CyTxRdy);
1298 goto txdone; 1298 goto txdone;
1299 } 1299 }
@@ -1346,15 +1346,15 @@ txend:
1346 1346
1347 /* determine the channel & change to that context */ 1347 /* determine the channel & change to that context */
1348 spin_lock(&cinfo->card_lock); 1348 spin_lock(&cinfo->card_lock);
1349 save_xir = (u_char) cy_readb(base_addr + (CyMIR << index)); 1349 save_xir = (u_char) readb(base_addr + (CyMIR << index));
1350 channel = (u_short) (save_xir & CyIRChannel); 1350 channel = (u_short) (save_xir & CyIRChannel);
1351 info = &cy_port[channel + chip * 4 + cinfo->first_line]; 1351 info = &cy_port[channel + chip * 4 + cinfo->first_line];
1352 info->last_active = jiffies; 1352 info->last_active = jiffies;
1353 save_car = cy_readb(base_addr + (CyCAR << index)); 1353 save_car = readb(base_addr + (CyCAR << index));
1354 cy_writeb(base_addr + (CyCAR << index), save_xir); 1354 cy_writeb(base_addr + (CyCAR << index), save_xir);
1355 1355
1356 mdm_change = cy_readb(base_addr + (CyMISR << index)); 1356 mdm_change = readb(base_addr + (CyMISR << index));
1357 mdm_status = cy_readb(base_addr + (CyMSVR1 << index)); 1357 mdm_status = readb(base_addr + (CyMSVR1 << index));
1358 1358
1359 if (info->tty == 0) { /* no place for data, ignore it */ 1359 if (info->tty == 0) { /* no place for data, ignore it */
1360 ; 1360 ;
@@ -1391,7 +1391,7 @@ txend:
1391 info->tty->hw_stopped = 0; 1391 info->tty->hw_stopped = 0;
1392 cy_writeb(base_addr + 1392 cy_writeb(base_addr +
1393 (CySRER << index), 1393 (CySRER << index),
1394 cy_readb(base_addr + 1394 readb(base_addr +
1395 (CySRER << 1395 (CySRER <<
1396 index))| 1396 index))|
1397 CyTxRdy); 1397 CyTxRdy);
@@ -1405,7 +1405,7 @@ txend:
1405 info->tty->hw_stopped = 1; 1405 info->tty->hw_stopped = 1;
1406 cy_writeb(base_addr + 1406 cy_writeb(base_addr +
1407 (CySRER << index), 1407 (CySRER << index),
1408 cy_readb(base_addr + 1408 readb(base_addr +
1409 (CySRER << 1409 (CySRER <<
1410 index)) & 1410 index)) &
1411 ~CyTxRdy); 1411 ~CyTxRdy);
@@ -1459,7 +1459,7 @@ static irqreturn_t cyy_interrupt(int irq, void *dev_id)
1459 base_addr = cinfo->base_addr + 1459 base_addr = cinfo->base_addr +
1460 (cy_chip_offset[chip] << index); 1460 (cy_chip_offset[chip] << index);
1461 too_many = 0; 1461 too_many = 0;
1462 while ((status = cy_readb(base_addr + 1462 while ((status = readb(base_addr +
1463 (CySVRR << index))) != 0x00) { 1463 (CySVRR << index))) != 0x00) {
1464 had_work++; 1464 had_work++;
1465 /* The purpose of the following test is to ensure that 1465 /* The purpose of the following test is to ensure that
@@ -1502,16 +1502,15 @@ cyz_fetch_msg(struct cyclades_card *cinfo,
1502 if (!ISZLOADED(*cinfo)) { 1502 if (!ISZLOADED(*cinfo)) {
1503 return -1; 1503 return -1;
1504 } 1504 }
1505 zfw_ctrl = cinfo->base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 1505 zfw_ctrl = cinfo->base_addr + (readl(&firm_id->zfwctrl_addr) & 0xfffff);
1506 0xfffff);
1507 board_ctrl = &zfw_ctrl->board_ctrl; 1506 board_ctrl = &zfw_ctrl->board_ctrl;
1508 1507
1509 loc_doorbell = cy_readl(&((struct RUNTIME_9060 __iomem *) 1508 loc_doorbell = readl(&((struct RUNTIME_9060 __iomem *)
1510 (cinfo->ctl_addr))->loc_doorbell); 1509 (cinfo->ctl_addr))->loc_doorbell);
1511 if (loc_doorbell) { 1510 if (loc_doorbell) {
1512 *cmd = (char)(0xff & loc_doorbell); 1511 *cmd = (char)(0xff & loc_doorbell);
1513 *channel = cy_readl(&board_ctrl->fwcmd_channel); 1512 *channel = readl(&board_ctrl->fwcmd_channel);
1514 *param = (__u32) cy_readl(&board_ctrl->fwcmd_param); 1513 *param = (__u32) readl(&board_ctrl->fwcmd_param);
1515 cy_writel(&((struct RUNTIME_9060 __iomem *)(cinfo->ctl_addr))-> 1514 cy_writel(&((struct RUNTIME_9060 __iomem *)(cinfo->ctl_addr))->
1516 loc_doorbell, 0xffffffff); 1515 loc_doorbell, 0xffffffff);
1517 return 1; 1516 return 1;
@@ -1533,16 +1532,15 @@ cyz_issue_cmd(struct cyclades_card *cinfo,
1533 if (!ISZLOADED(*cinfo)) { 1532 if (!ISZLOADED(*cinfo)) {
1534 return -1; 1533 return -1;
1535 } 1534 }
1536 zfw_ctrl = cinfo->base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 1535 zfw_ctrl = cinfo->base_addr + (readl(&firm_id->zfwctrl_addr) & 0xfffff);
1537 0xfffff);
1538 board_ctrl = &zfw_ctrl->board_ctrl; 1536 board_ctrl = &zfw_ctrl->board_ctrl;
1539 1537
1540 index = 0; 1538 index = 0;
1541 pci_doorbell = 1539 pci_doorbell =
1542 &((struct RUNTIME_9060 __iomem *)(cinfo->ctl_addr))->pci_doorbell; 1540 &((struct RUNTIME_9060 __iomem *)(cinfo->ctl_addr))->pci_doorbell;
1543 while ((cy_readl(pci_doorbell) & 0xff) != 0) { 1541 while ((readl(pci_doorbell) & 0xff) != 0) {
1544 if (index++ == 1000) { 1542 if (index++ == 1000) {
1545 return (int)(cy_readl(pci_doorbell) & 0xff); 1543 return (int)(readl(pci_doorbell) & 0xff);
1546 } 1544 }
1547 udelay(50L); 1545 udelay(50L);
1548 } 1546 }
@@ -1569,10 +1567,10 @@ cyz_handle_rx(struct cyclades_port *info,
1569#endif 1567#endif
1570 volatile __u32 rx_put, rx_get, new_rx_get, rx_bufsize, rx_bufaddr; 1568 volatile __u32 rx_put, rx_get, new_rx_get, rx_bufsize, rx_bufaddr;
1571 1569
1572 rx_get = new_rx_get = cy_readl(&buf_ctrl->rx_get); 1570 rx_get = new_rx_get = readl(&buf_ctrl->rx_get);
1573 rx_put = cy_readl(&buf_ctrl->rx_put); 1571 rx_put = readl(&buf_ctrl->rx_put);
1574 rx_bufsize = cy_readl(&buf_ctrl->rx_bufsize); 1572 rx_bufsize = readl(&buf_ctrl->rx_bufsize);
1575 rx_bufaddr = cy_readl(&buf_ctrl->rx_bufaddr); 1573 rx_bufaddr = readl(&buf_ctrl->rx_bufaddr);
1576 if (rx_put >= rx_get) 1574 if (rx_put >= rx_get)
1577 char_count = rx_put - rx_get; 1575 char_count = rx_put - rx_get;
1578 else 1576 else
@@ -1622,7 +1620,7 @@ cyz_handle_rx(struct cyclades_port *info,
1622#else 1620#else
1623 len = tty_buffer_request_room(tty, char_count); 1621 len = tty_buffer_request_room(tty, char_count);
1624 while (len--) { 1622 while (len--) {
1625 data = cy_readb(cinfo->base_addr + rx_bufaddr + 1623 data = readb(cinfo->base_addr + rx_bufaddr +
1626 new_rx_get); 1624 new_rx_get);
1627 new_rx_get = (new_rx_get + 1)& (rx_bufsize - 1); 1625 new_rx_get = (new_rx_get + 1)& (rx_bufsize - 1);
1628 tty_insert_flip_char(tty, data, TTY_NORMAL); 1626 tty_insert_flip_char(tty, data, TTY_NORMAL);
@@ -1633,13 +1631,12 @@ cyz_handle_rx(struct cyclades_port *info,
1633#ifdef CONFIG_CYZ_INTR 1631#ifdef CONFIG_CYZ_INTR
1634 /* Recalculate the number of chars in the RX buffer and issue 1632 /* Recalculate the number of chars in the RX buffer and issue
1635 a cmd in case it's higher than the RX high water mark */ 1633 a cmd in case it's higher than the RX high water mark */
1636 rx_put = cy_readl(&buf_ctrl->rx_put); 1634 rx_put = readl(&buf_ctrl->rx_put);
1637 if (rx_put >= rx_get) 1635 if (rx_put >= rx_get)
1638 char_count = rx_put - rx_get; 1636 char_count = rx_put - rx_get;
1639 else 1637 else
1640 char_count = rx_put - rx_get + rx_bufsize; 1638 char_count = rx_put - rx_get + rx_bufsize;
1641 if (char_count >= (int)cy_readl(&buf_ctrl-> 1639 if (char_count >= (int)readl(&buf_ctrl->rx_threshold)) {
1642 rx_threshold)) {
1643 cy_sched_event(info, Cy_EVENT_Z_RX_FULL); 1640 cy_sched_event(info, Cy_EVENT_Z_RX_FULL);
1644 } 1641 }
1645#endif 1642#endif
@@ -1668,10 +1665,10 @@ cyz_handle_tx(struct cyclades_port *info,
1668 if (info->xmit_cnt <= 0) /* Nothing to transmit */ 1665 if (info->xmit_cnt <= 0) /* Nothing to transmit */
1669 return; 1666 return;
1670 1667
1671 tx_get = cy_readl(&buf_ctrl->tx_get); 1668 tx_get = readl(&buf_ctrl->tx_get);
1672 tx_put = cy_readl(&buf_ctrl->tx_put); 1669 tx_put = readl(&buf_ctrl->tx_put);
1673 tx_bufsize = cy_readl(&buf_ctrl->tx_bufsize); 1670 tx_bufsize = readl(&buf_ctrl->tx_bufsize);
1674 tx_bufaddr = cy_readl(&buf_ctrl->tx_bufaddr); 1671 tx_bufaddr = readl(&buf_ctrl->tx_bufaddr);
1675 if (tx_put >= tx_get) 1672 if (tx_put >= tx_get)
1676 char_count = tx_get - tx_put - 1 + tx_bufsize; 1673 char_count = tx_get - tx_put - 1 + tx_bufsize;
1677 else 1674 else
@@ -1756,11 +1753,10 @@ static void cyz_handle_cmd(struct cyclades_card *cinfo)
1756 int delta_count; 1753 int delta_count;
1757 1754
1758 firm_id = cinfo->base_addr + ID_ADDRESS; 1755 firm_id = cinfo->base_addr + ID_ADDRESS;
1759 zfw_ctrl = cinfo->base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 1756 zfw_ctrl = cinfo->base_addr + (readl(&firm_id->zfwctrl_addr) & 0xfffff);
1760 0xfffff);
1761 board_ctrl = &zfw_ctrl->board_ctrl; 1757 board_ctrl = &zfw_ctrl->board_ctrl;
1762 fw_ver = cy_readl(&board_ctrl->fw_version); 1758 fw_ver = readl(&board_ctrl->fw_version);
1763 hw_ver = cy_readl(&((struct RUNTIME_9060 __iomem *)(cinfo->ctl_addr))-> 1759 hw_ver = readl(&((struct RUNTIME_9060 __iomem *)(cinfo->ctl_addr))->
1764 mail_box_0); 1760 mail_box_0);
1765 1761
1766 while (cyz_fetch_msg(cinfo, &channel, &cmd, &param) == 1) { 1762 while (cyz_fetch_msg(cinfo, &channel, &cmd, &param) == 1) {
@@ -1794,7 +1790,7 @@ static void cyz_handle_cmd(struct cyclades_card *cinfo)
1794 delta_count++; 1790 delta_count++;
1795 if (info->flags & ASYNC_CHECK_CD) { 1791 if (info->flags & ASYNC_CHECK_CD) {
1796 if ((fw_ver > 241 ? ((u_long) param) : 1792 if ((fw_ver > 241 ? ((u_long) param) :
1797 cy_readl(&ch_ctrl->rs_status)) & 1793 readl(&ch_ctrl->rs_status)) &
1798 C_RS_DCD) { 1794 C_RS_DCD) {
1799 cy_sched_event(info, 1795 cy_sched_event(info,
1800 Cy_EVENT_OPEN_WAKEUP); 1796 Cy_EVENT_OPEN_WAKEUP);
@@ -1923,12 +1919,12 @@ static void cyz_poll(unsigned long arg)
1923 1919
1924 firm_id = cinfo->base_addr + ID_ADDRESS; 1920 firm_id = cinfo->base_addr + ID_ADDRESS;
1925 zfw_ctrl = cinfo->base_addr + 1921 zfw_ctrl = cinfo->base_addr +
1926 (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); 1922 (readl(&firm_id->zfwctrl_addr) & 0xfffff);
1927 board_ctrl = &(zfw_ctrl->board_ctrl); 1923 board_ctrl = &(zfw_ctrl->board_ctrl);
1928 1924
1929 /* Skip first polling cycle to avoid racing conditions with the FW */ 1925 /* Skip first polling cycle to avoid racing conditions with the FW */
1930 if (!cinfo->intr_enabled) { 1926 if (!cinfo->intr_enabled) {
1931 cinfo->nports = (int)cy_readl(&board_ctrl->n_channel); 1927 cinfo->nports = (int)readl(&board_ctrl->n_channel);
1932 cinfo->intr_enabled = 1; 1928 cinfo->intr_enabled = 1;
1933 continue; 1929 continue;
1934 } 1930 }
@@ -2029,12 +2025,12 @@ static int startup(struct cyclades_port *info)
2029#ifdef CY_DEBUG_DTR 2025#ifdef CY_DEBUG_DTR
2030 printk("cyc:startup raising DTR\n"); 2026 printk("cyc:startup raising DTR\n");
2031 printk(" status: 0x%x, 0x%x\n", 2027 printk(" status: 0x%x, 0x%x\n",
2032 cy_readb(base_addr + (CyMSVR1 << index)), 2028 readb(base_addr + (CyMSVR1 << index)),
2033 cy_readb(base_addr + (CyMSVR2 << index))); 2029 readb(base_addr + (CyMSVR2 << index)));
2034#endif 2030#endif
2035 2031
2036 cy_writeb(base_addr + (CySRER << index), 2032 cy_writeb(base_addr + (CySRER << index),
2037 cy_readb(base_addr + (CySRER << index)) | CyRxData); 2033 readb(base_addr + (CySRER << index)) | CyRxData);
2038 info->flags |= ASYNC_INITIALIZED; 2034 info->flags |= ASYNC_INITIALIZED;
2039 2035
2040 if (info->tty) { 2036 if (info->tty) {
@@ -2064,7 +2060,7 @@ static int startup(struct cyclades_port *info)
2064 } 2060 }
2065 2061
2066 zfw_ctrl = cy_card[card].base_addr + 2062 zfw_ctrl = cy_card[card].base_addr +
2067 (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); 2063 (readl(&firm_id->zfwctrl_addr) & 0xfffff);
2068 board_ctrl = &zfw_ctrl->board_ctrl; 2064 board_ctrl = &zfw_ctrl->board_ctrl;
2069 ch_ctrl = zfw_ctrl->ch_ctrl; 2065 ch_ctrl = zfw_ctrl->ch_ctrl;
2070 2066
@@ -2112,7 +2108,7 @@ static int startup(struct cyclades_port *info)
2112 /* set timeout !!! */ 2108 /* set timeout !!! */
2113 /* set RTS and DTR !!! */ 2109 /* set RTS and DTR !!! */
2114 cy_writel(&ch_ctrl[channel].rs_control, 2110 cy_writel(&ch_ctrl[channel].rs_control,
2115 cy_readl(&ch_ctrl[channel].rs_control) | C_RS_RTS | 2111 readl(&ch_ctrl[channel].rs_control) | C_RS_RTS |
2116 C_RS_DTR); 2112 C_RS_DTR);
2117 retval = cyz_issue_cmd(&cy_card[info->card], channel, 2113 retval = cyz_issue_cmd(&cy_card[info->card], channel,
2118 C_CM_IOCTLM, 0L); 2114 C_CM_IOCTLM, 0L);
@@ -2168,7 +2164,7 @@ static void start_xmit(struct cyclades_port *info)
2168 CY_LOCK(info, flags); 2164 CY_LOCK(info, flags);
2169 cy_writeb(base_addr + (CyCAR << index), channel); 2165 cy_writeb(base_addr + (CyCAR << index), channel);
2170 cy_writeb(base_addr + (CySRER << index), 2166 cy_writeb(base_addr + (CySRER << index),
2171 cy_readb(base_addr + (CySRER << index)) | CyTxRdy); 2167 readb(base_addr + (CySRER << index)) | CyTxRdy);
2172 CY_UNLOCK(info, flags); 2168 CY_UNLOCK(info, flags);
2173 } else { 2169 } else {
2174#ifdef CONFIG_CYZ_INTR 2170#ifdef CONFIG_CYZ_INTR
@@ -2235,8 +2231,8 @@ static void shutdown(struct cyclades_port *info)
2235#ifdef CY_DEBUG_DTR 2231#ifdef CY_DEBUG_DTR
2236 printk("cyc shutdown dropping DTR\n"); 2232 printk("cyc shutdown dropping DTR\n");
2237 printk(" status: 0x%x, 0x%x\n", 2233 printk(" status: 0x%x, 0x%x\n",
2238 cy_readb(base_addr + (CyMSVR1 << index)), 2234 readb(base_addr + (CyMSVR1 << index)),
2239 cy_readb(base_addr + (CyMSVR2 << index))); 2235 readb(base_addr + (CyMSVR2 << index)));
2240#endif 2236#endif
2241 } 2237 }
2242 cyy_issue_cmd(base_addr, CyCHAN_CTL | CyDIS_RCVR, index); 2238 cyy_issue_cmd(base_addr, CyCHAN_CTL | CyDIS_RCVR, index);
@@ -2267,7 +2263,7 @@ static void shutdown(struct cyclades_port *info)
2267 } 2263 }
2268 2264
2269 zfw_ctrl = cy_card[card].base_addr + 2265 zfw_ctrl = cy_card[card].base_addr +
2270 (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); 2266 (readl(&firm_id->zfwctrl_addr) & 0xfffff);
2271 board_ctrl = &zfw_ctrl->board_ctrl; 2267 board_ctrl = &zfw_ctrl->board_ctrl;
2272 ch_ctrl = zfw_ctrl->ch_ctrl; 2268 ch_ctrl = zfw_ctrl->ch_ctrl;
2273 2269
@@ -2282,7 +2278,7 @@ static void shutdown(struct cyclades_port *info)
2282 2278
2283 if (!info->tty || (info->tty->termios->c_cflag & HUPCL)) { 2279 if (!info->tty || (info->tty->termios->c_cflag & HUPCL)) {
2284 cy_writel(&ch_ctrl[channel].rs_control, 2280 cy_writel(&ch_ctrl[channel].rs_control,
2285 (__u32)(cy_readl(&ch_ctrl[channel].rs_control)& 2281 (__u32)(readl(&ch_ctrl[channel].rs_control) &
2286 ~(C_RS_RTS | C_RS_DTR))); 2282 ~(C_RS_RTS | C_RS_DTR)));
2287 retval = cyz_issue_cmd(&cy_card[info->card], channel, 2283 retval = cyz_issue_cmd(&cy_card[info->card], channel,
2288 C_CM_IOCTLM, 0L); 2284 C_CM_IOCTLM, 0L);
@@ -2390,10 +2386,8 @@ block_til_ready(struct tty_struct *tty, struct file *filp,
2390#ifdef CY_DEBUG_DTR 2386#ifdef CY_DEBUG_DTR
2391 printk("cyc:block_til_ready raising DTR\n"); 2387 printk("cyc:block_til_ready raising DTR\n");
2392 printk(" status: 0x%x, 0x%x\n", 2388 printk(" status: 0x%x, 0x%x\n",
2393 cy_readb(base_addr + 2389 readb(base_addr + (CyMSVR1 << index)),
2394 (CyMSVR1 << index)), 2390 readb(base_addr + (CyMSVR2 << index)));
2395 cy_readb(base_addr +
2396 (CyMSVR2 << index)));
2397#endif 2391#endif
2398 } 2392 }
2399 CY_UNLOCK(info, flags); 2393 CY_UNLOCK(info, flags);
@@ -2410,7 +2404,7 @@ block_til_ready(struct tty_struct *tty, struct file *filp,
2410 cy_writeb(base_addr + (CyCAR << index), 2404 cy_writeb(base_addr + (CyCAR << index),
2411 (u_char) channel); 2405 (u_char) channel);
2412 if (!(info->flags & ASYNC_CLOSING) && (C_CLOCAL(tty) || 2406 if (!(info->flags & ASYNC_CLOSING) && (C_CLOCAL(tty) ||
2413 (cy_readb(base_addr + 2407 (readb(base_addr +
2414 (CyMSVR1 << index)) & CyDCD))) { 2408 (CyMSVR1 << index)) & CyDCD))) {
2415 CY_UNLOCK(info, flags); 2409 CY_UNLOCK(info, flags);
2416 break; 2410 break;
@@ -2444,19 +2438,17 @@ block_til_ready(struct tty_struct *tty, struct file *filp,
2444 return -EINVAL; 2438 return -EINVAL;
2445 } 2439 }
2446 2440
2447 zfw_ctrl = base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 2441 zfw_ctrl = base_addr + (readl(&firm_id->zfwctrl_addr)& 0xfffff);
2448 0xfffff);
2449 board_ctrl = &zfw_ctrl->board_ctrl; 2442 board_ctrl = &zfw_ctrl->board_ctrl;
2450 ch_ctrl = zfw_ctrl->ch_ctrl; 2443 ch_ctrl = zfw_ctrl->ch_ctrl;
2451 2444
2452 while (1) { 2445 while (1) {
2453 if ((tty->termios->c_cflag & CBAUD)) { 2446 if ((tty->termios->c_cflag & CBAUD)) {
2454 cy_writel(&ch_ctrl[channel].rs_control, 2447 cy_writel(&ch_ctrl[channel].rs_control,
2455 cy_readl(&ch_ctrl[channel]. 2448 readl(&ch_ctrl[channel].rs_control) |
2456 rs_control) | (C_RS_RTS | 2449 C_RS_RTS | C_RS_DTR);
2457 C_RS_DTR));
2458 retval = cyz_issue_cmd(&cy_card[info->card], 2450 retval = cyz_issue_cmd(&cy_card[info->card],
2459 channel, C_CM_IOCTLM, 0L); 2451 channel, C_CM_IOCTLM, 0L);
2460 if (retval != 0) { 2452 if (retval != 0) {
2461 printk("cyc:block_til_ready retval on " 2453 printk("cyc:block_til_ready retval on "
2462 "ttyC%d was %x\n", 2454 "ttyC%d was %x\n",
@@ -2475,7 +2467,7 @@ block_til_ready(struct tty_struct *tty, struct file *filp,
2475 break; 2467 break;
2476 } 2468 }
2477 if (!(info->flags & ASYNC_CLOSING) && (C_CLOCAL(tty) || 2469 if (!(info->flags & ASYNC_CLOSING) && (C_CLOCAL(tty) ||
2478 (cy_readl(&ch_ctrl[channel].rs_status) & 2470 (readl(&ch_ctrl[channel].rs_status) &
2479 C_RS_DCD))) { 2471 C_RS_DCD))) {
2480 break; 2472 break;
2481 } 2473 }
@@ -2540,11 +2532,10 @@ static int cy_open(struct tty_struct *tty, struct file *filp)
2540 struct FIRM_ID __iomem *firm_id = cinfo->base_addr + ID_ADDRESS; 2532 struct FIRM_ID __iomem *firm_id = cinfo->base_addr + ID_ADDRESS;
2541 2533
2542 if (!ISZLOADED(*cinfo)) { 2534 if (!ISZLOADED(*cinfo)) {
2543 if (((ZE_V1 == cy_readl( 2535 if (((ZE_V1 == readl(&((struct RUNTIME_9060 __iomem *)
2544 &((struct RUNTIME_9060 __iomem *)
2545 (cinfo->ctl_addr))->mail_box_0)) && 2536 (cinfo->ctl_addr))->mail_box_0)) &&
2546 Z_FPGA_CHECK(*cinfo)) && 2537 Z_FPGA_CHECK(*cinfo)) &&
2547 (ZFIRM_HLT == cy_readl( 2538 (ZFIRM_HLT == readl(
2548 &firm_id->signature))) { 2539 &firm_id->signature))) {
2549 printk("cyc:Cyclades-Z Error: you need an " 2540 printk("cyc:Cyclades-Z Error: you need an "
2550 "external power supply for this number " 2541 "external power supply for this number "
@@ -2565,15 +2556,14 @@ static int cy_open(struct tty_struct *tty, struct file *filp)
2565 struct BOARD_CTRL __iomem *board_ctrl; 2556 struct BOARD_CTRL __iomem *board_ctrl;
2566 2557
2567 zfw_ctrl = cinfo->base_addr + 2558 zfw_ctrl = cinfo->base_addr +
2568 (cy_readl(&firm_id->zfwctrl_addr) & 2559 (readl(&firm_id->zfwctrl_addr) &
2569 0xfffff); 2560 0xfffff);
2570 2561
2571 board_ctrl = &zfw_ctrl->board_ctrl; 2562 board_ctrl = &zfw_ctrl->board_ctrl;
2572 2563
2573 /* Enable interrupts on the PLX chip */ 2564 /* Enable interrupts on the PLX chip */
2574 cy_writew(cinfo->ctl_addr + 0x68, 2565 cy_writew(cinfo->ctl_addr + 0x68,
2575 cy_readw(cinfo->ctl_addr + 2566 readw(cinfo->ctl_addr + 0x68) | 0x0900);
2576 0x68) | 0x0900);
2577 /* Enable interrupts on the FW */ 2567 /* Enable interrupts on the FW */
2578 retval = cyz_issue_cmd(cinfo, 0, 2568 retval = cyz_issue_cmd(cinfo, 0,
2579 C_CM_IRQ_ENBL, 0L); 2569 C_CM_IRQ_ENBL, 0L);
@@ -2582,7 +2572,7 @@ static int cy_open(struct tty_struct *tty, struct file *filp)
2582 retval); 2572 retval);
2583 } 2573 }
2584 cinfo->nports = 2574 cinfo->nports =
2585 (int)cy_readl(&board_ctrl->n_channel); 2575 (int)readl(&board_ctrl->n_channel);
2586 cinfo->intr_enabled = 1; 2576 cinfo->intr_enabled = 1;
2587 } 2577 }
2588 } 2578 }
@@ -2701,7 +2691,7 @@ static void cy_wait_until_sent(struct tty_struct *tty, int timeout)
2701 index = cy_card[card].bus_index; 2691 index = cy_card[card].bus_index;
2702 base_addr = 2692 base_addr =
2703 cy_card[card].base_addr + (cy_chip_offset[chip] << index); 2693 cy_card[card].base_addr + (cy_chip_offset[chip] << index);
2704 while (cy_readb(base_addr + (CySRER << index)) & CyTxRdy) { 2694 while (readb(base_addr + (CySRER << index)) & CyTxRdy) {
2705#ifdef CY_DEBUG_WAIT_UNTIL_SENT 2695#ifdef CY_DEBUG_WAIT_UNTIL_SENT
2706 printk("Not clean (jiff=%lu)...", jiffies); 2696 printk("Not clean (jiff=%lu)...", jiffies);
2707#endif 2697#endif
@@ -2794,7 +2784,7 @@ static void cy_close(struct tty_struct *tty, struct file *filp)
2794 channel &= 0x03; 2784 channel &= 0x03;
2795 cy_writeb(base_addr + (CyCAR << index), (u_char) channel); 2785 cy_writeb(base_addr + (CyCAR << index), (u_char) channel);
2796 cy_writeb(base_addr + (CySRER << index), 2786 cy_writeb(base_addr + (CySRER << index),
2797 cy_readb(base_addr + (CySRER << index)) & ~CyRxData); 2787 readb(base_addr + (CySRER << index)) & ~CyRxData);
2798 if (info->flags & ASYNC_INITIALIZED) { 2788 if (info->flags & ASYNC_INITIALIZED) {
2799 /* Waiting for on-board buffers to be empty before closing 2789 /* Waiting for on-board buffers to be empty before closing
2800 the port */ 2790 the port */
@@ -2808,12 +2798,12 @@ static void cy_close(struct tty_struct *tty, struct file *filp)
2808 void __iomem *base_addr = cy_card[info->card].base_addr; 2798 void __iomem *base_addr = cy_card[info->card].base_addr;
2809 struct FIRM_ID __iomem *firm_id = base_addr + ID_ADDRESS; 2799 struct FIRM_ID __iomem *firm_id = base_addr + ID_ADDRESS;
2810 struct ZFW_CTRL __iomem *zfw_ctrl = 2800 struct ZFW_CTRL __iomem *zfw_ctrl =
2811 base_addr + (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); 2801 base_addr + (readl(&firm_id->zfwctrl_addr) & 0xfffff);
2812 struct CH_CTRL __iomem *ch_ctrl = zfw_ctrl->ch_ctrl; 2802 struct CH_CTRL __iomem *ch_ctrl = zfw_ctrl->ch_ctrl;
2813 int channel = info->line - cy_card[info->card].first_line; 2803 int channel = info->line - cy_card[info->card].first_line;
2814 int retval; 2804 int retval;
2815 2805
2816 if (cy_readl(&ch_ctrl[channel].flow_status) != C_FS_TXIDLE) { 2806 if (readl(&ch_ctrl[channel].flow_status) != C_FS_TXIDLE) {
2817 retval = cyz_issue_cmd(&cy_card[info->card], channel, 2807 retval = cyz_issue_cmd(&cy_card[info->card], channel,
2818 C_CM_IOCTLW, 0L); 2808 C_CM_IOCTLW, 0L);
2819 if (retval != 0) { 2809 if (retval != 0) {
@@ -3023,13 +3013,13 @@ static int cy_chars_in_buffer(struct tty_struct *tty)
3023 3013
3024 firm_id = cy_card[card].base_addr + ID_ADDRESS; 3014 firm_id = cy_card[card].base_addr + ID_ADDRESS;
3025 zfw_ctrl = cy_card[card].base_addr + 3015 zfw_ctrl = cy_card[card].base_addr +
3026 (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); 3016 (readl(&firm_id->zfwctrl_addr) & 0xfffff);
3027 ch_ctrl = &(zfw_ctrl->ch_ctrl[channel]); 3017 ch_ctrl = &(zfw_ctrl->ch_ctrl[channel]);
3028 buf_ctrl = &(zfw_ctrl->buf_ctrl[channel]); 3018 buf_ctrl = &(zfw_ctrl->buf_ctrl[channel]);
3029 3019
3030 tx_get = cy_readl(&buf_ctrl->tx_get); 3020 tx_get = readl(&buf_ctrl->tx_get);
3031 tx_put = cy_readl(&buf_ctrl->tx_put); 3021 tx_put = readl(&buf_ctrl->tx_put);
3032 tx_bufsize = cy_readl(&buf_ctrl->tx_bufsize); 3022 tx_bufsize = readl(&buf_ctrl->tx_bufsize);
3033 if (tx_put >= tx_get) 3023 if (tx_put >= tx_get)
3034 char_count = tx_put - tx_get; 3024 char_count = tx_put - tx_get;
3035 else 3025 else
@@ -3269,8 +3259,7 @@ static void set_line_char(struct cyclades_port *info)
3269 if (C_CLOCAL(info->tty)) { 3259 if (C_CLOCAL(info->tty)) {
3270 /* without modem intr */ 3260 /* without modem intr */
3271 cy_writeb(base_addr + (CySRER << index), 3261 cy_writeb(base_addr + (CySRER << index),
3272 cy_readb(base_addr + 3262 readb(base_addr + (CySRER << index)) | CyMdmCh);
3273 (CySRER << index)) | CyMdmCh);
3274 /* act on 1->0 modem transitions */ 3263 /* act on 1->0 modem transitions */
3275 if ((cflag & CRTSCTS) && info->rflow) { 3264 if ((cflag & CRTSCTS) && info->rflow) {
3276 cy_writeb(base_addr + (CyMCOR1 << index), 3265 cy_writeb(base_addr + (CyMCOR1 << index),
@@ -3284,7 +3273,7 @@ static void set_line_char(struct cyclades_port *info)
3284 } else { 3273 } else {
3285 /* without modem intr */ 3274 /* without modem intr */
3286 cy_writeb(base_addr + (CySRER << index), 3275 cy_writeb(base_addr + (CySRER << index),
3287 cy_readb(base_addr + 3276 readb(base_addr +
3288 (CySRER << index)) | CyMdmCh); 3277 (CySRER << index)) | CyMdmCh);
3289 /* act on 1->0 modem transitions */ 3278 /* act on 1->0 modem transitions */
3290 if ((cflag & CRTSCTS) && info->rflow) { 3279 if ((cflag & CRTSCTS) && info->rflow) {
@@ -3311,8 +3300,8 @@ static void set_line_char(struct cyclades_port *info)
3311#ifdef CY_DEBUG_DTR 3300#ifdef CY_DEBUG_DTR
3312 printk("cyc:set_line_char dropping DTR\n"); 3301 printk("cyc:set_line_char dropping DTR\n");
3313 printk(" status: 0x%x, 0x%x\n", 3302 printk(" status: 0x%x, 0x%x\n",
3314 cy_readb(base_addr + (CyMSVR1 << index)), 3303 readb(base_addr + (CyMSVR1 << index)),
3315 cy_readb(base_addr + (CyMSVR2 << index))); 3304 readb(base_addr + (CyMSVR2 << index)));
3316#endif 3305#endif
3317 } else { 3306 } else {
3318 if (info->rtsdtr_inv) { 3307 if (info->rtsdtr_inv) {
@@ -3325,8 +3314,8 @@ static void set_line_char(struct cyclades_port *info)
3325#ifdef CY_DEBUG_DTR 3314#ifdef CY_DEBUG_DTR
3326 printk("cyc:set_line_char raising DTR\n"); 3315 printk("cyc:set_line_char raising DTR\n");
3327 printk(" status: 0x%x, 0x%x\n", 3316 printk(" status: 0x%x, 0x%x\n",
3328 cy_readb(base_addr + (CyMSVR1 << index)), 3317 readb(base_addr + (CyMSVR1 << index)),
3329 cy_readb(base_addr + (CyMSVR2 << index))); 3318 readb(base_addr + (CyMSVR2 << index)));
3330#endif 3319#endif
3331 } 3320 }
3332 3321
@@ -3350,7 +3339,7 @@ static void set_line_char(struct cyclades_port *info)
3350 } 3339 }
3351 3340
3352 zfw_ctrl = cy_card[card].base_addr + 3341 zfw_ctrl = cy_card[card].base_addr +
3353 (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); 3342 (readl(&firm_id->zfwctrl_addr) & 0xfffff);
3354 board_ctrl = &zfw_ctrl->board_ctrl; 3343 board_ctrl = &zfw_ctrl->board_ctrl;
3355 ch_ctrl = &(zfw_ctrl->ch_ctrl[channel]); 3344 ch_ctrl = &(zfw_ctrl->ch_ctrl[channel]);
3356 buf_ctrl = &zfw_ctrl->buf_ctrl[channel]; 3345 buf_ctrl = &zfw_ctrl->buf_ctrl[channel];
@@ -3401,10 +3390,10 @@ static void set_line_char(struct cyclades_port *info)
3401 } 3390 }
3402 if (cflag & CSTOPB) { 3391 if (cflag & CSTOPB) {
3403 cy_writel(&ch_ctrl->comm_data_l, 3392 cy_writel(&ch_ctrl->comm_data_l,
3404 cy_readl(&ch_ctrl->comm_data_l) | C_DL_2STOP); 3393 readl(&ch_ctrl->comm_data_l) | C_DL_2STOP);
3405 } else { 3394 } else {
3406 cy_writel(&ch_ctrl->comm_data_l, 3395 cy_writel(&ch_ctrl->comm_data_l,
3407 cy_readl(&ch_ctrl->comm_data_l) | C_DL_1STOP); 3396 readl(&ch_ctrl->comm_data_l) | C_DL_1STOP);
3408 } 3397 }
3409 if (cflag & PARENB) { 3398 if (cflag & PARENB) {
3410 if (cflag & PARODD) { 3399 if (cflag & PARODD) {
@@ -3419,12 +3408,10 @@ static void set_line_char(struct cyclades_port *info)
3419 /* CTS flow control flag */ 3408 /* CTS flow control flag */
3420 if (cflag & CRTSCTS) { 3409 if (cflag & CRTSCTS) {
3421 cy_writel(&ch_ctrl->hw_flow, 3410 cy_writel(&ch_ctrl->hw_flow,
3422 cy_readl(&ch_ctrl-> 3411 readl(&ch_ctrl->hw_flow) | C_RS_CTS | C_RS_RTS);
3423 hw_flow) | C_RS_CTS | C_RS_RTS);
3424 } else { 3412 } else {
3425 cy_writel(&ch_ctrl->hw_flow, 3413 cy_writel(&ch_ctrl->hw_flow, readl(&ch_ctrl->hw_flow) &
3426 cy_readl(&ch_ctrl-> 3414 ~(C_RS_CTS | C_RS_RTS));
3427 hw_flow) & ~(C_RS_CTS | C_RS_RTS));
3428 } 3415 }
3429 /* As the HW flow control is done in firmware, the driver 3416 /* As the HW flow control is done in firmware, the driver
3430 doesn't need to care about it */ 3417 doesn't need to care about it */
@@ -3454,13 +3441,13 @@ static void set_line_char(struct cyclades_port *info)
3454 3441
3455 if (baud == 0) { /* baud rate is zero, turn off line */ 3442 if (baud == 0) { /* baud rate is zero, turn off line */
3456 cy_writel(&ch_ctrl->rs_control, 3443 cy_writel(&ch_ctrl->rs_control,
3457 cy_readl(&ch_ctrl->rs_control) & ~C_RS_DTR); 3444 readl(&ch_ctrl->rs_control) & ~C_RS_DTR);
3458#ifdef CY_DEBUG_DTR 3445#ifdef CY_DEBUG_DTR
3459 printk("cyc:set_line_char dropping Z DTR\n"); 3446 printk("cyc:set_line_char dropping Z DTR\n");
3460#endif 3447#endif
3461 } else { 3448 } else {
3462 cy_writel(&ch_ctrl->rs_control, 3449 cy_writel(&ch_ctrl->rs_control,
3463 cy_readl(&ch_ctrl->rs_control) | C_RS_DTR); 3450 readl(&ch_ctrl->rs_control) | C_RS_DTR);
3464#ifdef CY_DEBUG_DTR 3451#ifdef CY_DEBUG_DTR
3465 printk("cyc:set_line_char raising Z DTR\n"); 3452 printk("cyc:set_line_char raising Z DTR\n");
3466#endif 3453#endif
@@ -3575,7 +3562,7 @@ static int get_lsr_info(struct cyclades_port *info, unsigned int __user * value)
3575 cy_card[card].base_addr + (cy_chip_offset[chip] << index); 3562 cy_card[card].base_addr + (cy_chip_offset[chip] << index);
3576 3563
3577 CY_LOCK(info, flags); 3564 CY_LOCK(info, flags);
3578 status = cy_readb(base_addr + (CySRER << index)) & 3565 status = readb(base_addr + (CySRER << index)) &
3579 (CyTxRdy | CyTxMpty); 3566 (CyTxRdy | CyTxMpty);
3580 CY_UNLOCK(info, flags); 3567 CY_UNLOCK(info, flags);
3581 result = (status ? 0 : TIOCSER_TEMT); 3568 result = (status ? 0 : TIOCSER_TEMT);
@@ -3614,8 +3601,8 @@ static int cy_tiocmget(struct tty_struct *tty, struct file *file)
3614 3601
3615 CY_LOCK(info, flags); 3602 CY_LOCK(info, flags);
3616 cy_writeb(base_addr + (CyCAR << index), (u_char) channel); 3603 cy_writeb(base_addr + (CyCAR << index), (u_char) channel);
3617 status = cy_readb(base_addr + (CyMSVR1 << index)); 3604 status = readb(base_addr + (CyMSVR1 << index));
3618 status |= cy_readb(base_addr + (CyMSVR2 << index)); 3605 status |= readb(base_addr + (CyMSVR2 << index));
3619 CY_UNLOCK(info, flags); 3606 CY_UNLOCK(info, flags);
3620 3607
3621 if (info->rtsdtr_inv) { 3608 if (info->rtsdtr_inv) {
@@ -3639,10 +3626,10 @@ static int cy_tiocmget(struct tty_struct *tty, struct file *file)
3639 firm_id = cy_card[card].base_addr + ID_ADDRESS; 3626 firm_id = cy_card[card].base_addr + ID_ADDRESS;
3640 if (ISZLOADED(cy_card[card])) { 3627 if (ISZLOADED(cy_card[card])) {
3641 zfw_ctrl = cy_card[card].base_addr + 3628 zfw_ctrl = cy_card[card].base_addr +
3642 (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); 3629 (readl(&firm_id->zfwctrl_addr) & 0xfffff);
3643 board_ctrl = &zfw_ctrl->board_ctrl; 3630 board_ctrl = &zfw_ctrl->board_ctrl;
3644 ch_ctrl = zfw_ctrl->ch_ctrl; 3631 ch_ctrl = zfw_ctrl->ch_ctrl;
3645 lstatus = cy_readl(&ch_ctrl[channel].rs_status); 3632 lstatus = readl(&ch_ctrl[channel].rs_status);
3646 result = ((lstatus & C_RS_RTS) ? TIOCM_RTS : 0) | 3633 result = ((lstatus & C_RS_RTS) ? TIOCM_RTS : 0) |
3647 ((lstatus & C_RS_DTR) ? TIOCM_DTR : 0) | 3634 ((lstatus & C_RS_DTR) ? TIOCM_DTR : 0) |
3648 ((lstatus & C_RS_DCD) ? TIOCM_CAR : 0) | 3635 ((lstatus & C_RS_DCD) ? TIOCM_CAR : 0) |
@@ -3724,8 +3711,8 @@ cy_tiocmset(struct tty_struct *tty, struct file *file,
3724#ifdef CY_DEBUG_DTR 3711#ifdef CY_DEBUG_DTR
3725 printk("cyc:set_modem_info raising DTR\n"); 3712 printk("cyc:set_modem_info raising DTR\n");
3726 printk(" status: 0x%x, 0x%x\n", 3713 printk(" status: 0x%x, 0x%x\n",
3727 cy_readb(base_addr + (CyMSVR1 << index)), 3714 readb(base_addr + (CyMSVR1 << index)),
3728 cy_readb(base_addr + (CyMSVR2 << index))); 3715 readb(base_addr + (CyMSVR2 << index)));
3729#endif 3716#endif
3730 CY_UNLOCK(info, flags); 3717 CY_UNLOCK(info, flags);
3731 } 3718 }
@@ -3744,8 +3731,8 @@ cy_tiocmset(struct tty_struct *tty, struct file *file,
3744#ifdef CY_DEBUG_DTR 3731#ifdef CY_DEBUG_DTR
3745 printk("cyc:set_modem_info dropping DTR\n"); 3732 printk("cyc:set_modem_info dropping DTR\n");
3746 printk(" status: 0x%x, 0x%x\n", 3733 printk(" status: 0x%x, 0x%x\n",
3747 cy_readb(base_addr + (CyMSVR1 << index)), 3734 readb(base_addr + (CyMSVR1 << index)),
3748 cy_readb(base_addr + (CyMSVR2 << index))); 3735 readb(base_addr + (CyMSVR2 << index)));
3749#endif 3736#endif
3750 CY_UNLOCK(info, flags); 3737 CY_UNLOCK(info, flags);
3751 } 3738 }
@@ -3755,29 +3742,29 @@ cy_tiocmset(struct tty_struct *tty, struct file *file,
3755 firm_id = cy_card[card].base_addr + ID_ADDRESS; 3742 firm_id = cy_card[card].base_addr + ID_ADDRESS;
3756 if (ISZLOADED(cy_card[card])) { 3743 if (ISZLOADED(cy_card[card])) {
3757 zfw_ctrl = cy_card[card].base_addr + 3744 zfw_ctrl = cy_card[card].base_addr +
3758 (cy_readl(&firm_id->zfwctrl_addr) & 0xfffff); 3745 (readl(&firm_id->zfwctrl_addr) & 0xfffff);
3759 board_ctrl = &zfw_ctrl->board_ctrl; 3746 board_ctrl = &zfw_ctrl->board_ctrl;
3760 ch_ctrl = zfw_ctrl->ch_ctrl; 3747 ch_ctrl = zfw_ctrl->ch_ctrl;
3761 3748
3762 if (set & TIOCM_RTS) { 3749 if (set & TIOCM_RTS) {
3763 CY_LOCK(info, flags); 3750 CY_LOCK(info, flags);
3764 cy_writel(&ch_ctrl[channel].rs_control, 3751 cy_writel(&ch_ctrl[channel].rs_control,
3765 cy_readl(&ch_ctrl[channel]. 3752 readl(&ch_ctrl[channel].rs_control) |
3766 rs_control) | C_RS_RTS); 3753 C_RS_RTS);
3767 CY_UNLOCK(info, flags); 3754 CY_UNLOCK(info, flags);
3768 } 3755 }
3769 if (clear & TIOCM_RTS) { 3756 if (clear & TIOCM_RTS) {
3770 CY_LOCK(info, flags); 3757 CY_LOCK(info, flags);
3771 cy_writel(&ch_ctrl[channel].rs_control, 3758 cy_writel(&ch_ctrl[channel].rs_control,
3772 cy_readl(&ch_ctrl[channel]. 3759 readl(&ch_ctrl[channel].rs_control) &
3773 rs_control) & ~C_RS_RTS); 3760 ~C_RS_RTS);
3774 CY_UNLOCK(info, flags); 3761 CY_UNLOCK(info, flags);
3775 } 3762 }
3776 if (set & TIOCM_DTR) { 3763 if (set & TIOCM_DTR) {
3777 CY_LOCK(info, flags); 3764 CY_LOCK(info, flags);
3778 cy_writel(&ch_ctrl[channel].rs_control, 3765 cy_writel(&ch_ctrl[channel].rs_control,
3779 cy_readl(&ch_ctrl[channel]. 3766 readl(&ch_ctrl[channel].rs_control) |
3780 rs_control) | C_RS_DTR); 3767 C_RS_DTR);
3781#ifdef CY_DEBUG_DTR 3768#ifdef CY_DEBUG_DTR
3782 printk("cyc:set_modem_info raising Z DTR\n"); 3769 printk("cyc:set_modem_info raising Z DTR\n");
3783#endif 3770#endif
@@ -3786,8 +3773,8 @@ cy_tiocmset(struct tty_struct *tty, struct file *file,
3786 if (clear & TIOCM_DTR) { 3773 if (clear & TIOCM_DTR) {
3787 CY_LOCK(info, flags); 3774 CY_LOCK(info, flags);
3788 cy_writel(&ch_ctrl[channel].rs_control, 3775 cy_writel(&ch_ctrl[channel].rs_control,
3789 cy_readl(&ch_ctrl[channel]. 3776 readl(&ch_ctrl[channel].rs_control) &
3790 rs_control) & ~C_RS_DTR); 3777 ~C_RS_DTR);
3791#ifdef CY_DEBUG_DTR 3778#ifdef CY_DEBUG_DTR
3792 printk("cyc:set_modem_info clearing Z DTR\n"); 3779 printk("cyc:set_modem_info clearing Z DTR\n");
3793#endif 3780#endif
@@ -3924,7 +3911,7 @@ get_threshold(struct cyclades_port *info, unsigned long __user * value)
3924 base_addr = 3911 base_addr =
3925 cy_card[card].base_addr + (cy_chip_offset[chip] << index); 3912 cy_card[card].base_addr + (cy_chip_offset[chip] << index);
3926 3913
3927 tmp = cy_readb(base_addr + (CyCOR3 << index)) & CyREC_FIFO; 3914 tmp = readb(base_addr + (CyCOR3 << index)) & CyREC_FIFO;
3928 return put_user(tmp, value); 3915 return put_user(tmp, value);
3929 } else { 3916 } else {
3930 /* Nothing to do! */ 3917 /* Nothing to do! */
@@ -3984,7 +3971,7 @@ static int get_timeout(struct cyclades_port *info, unsigned long __user * value)
3984 base_addr = 3971 base_addr =
3985 cy_card[card].base_addr + (cy_chip_offset[chip] << index); 3972 cy_card[card].base_addr + (cy_chip_offset[chip] << index);
3986 3973
3987 tmp = cy_readb(base_addr + (CyRTPR << index)); 3974 tmp = readb(base_addr + (CyRTPR << index));
3988 return put_user(tmp, value); 3975 return put_user(tmp, value);
3989 } else { 3976 } else {
3990 /* Nothing to do! */ 3977 /* Nothing to do! */
@@ -4410,7 +4397,7 @@ static void cy_stop(struct tty_struct *tty)
4410 cy_writeb(base_addr + (CyCAR << index), 4397 cy_writeb(base_addr + (CyCAR << index),
4411 (u_char)(channel & 0x0003)); /* index channel */ 4398 (u_char)(channel & 0x0003)); /* index channel */
4412 cy_writeb(base_addr + (CySRER << index), 4399 cy_writeb(base_addr + (CySRER << index),
4413 cy_readb(base_addr + (CySRER << index)) & ~CyTxRdy); 4400 readb(base_addr + (CySRER << index)) & ~CyTxRdy);
4414 CY_UNLOCK(info, flags); 4401 CY_UNLOCK(info, flags);
4415 } else { 4402 } else {
4416 /* Nothing to do! */ 4403 /* Nothing to do! */
@@ -4444,7 +4431,7 @@ static void cy_start(struct tty_struct *tty)
4444 CY_LOCK(info, flags); 4431 CY_LOCK(info, flags);
4445 cy_writeb(base_addr + (CyCAR << index), (u_char) (channel & 0x0003)); /* index channel */ 4432 cy_writeb(base_addr + (CyCAR << index), (u_char) (channel & 0x0003)); /* index channel */
4446 cy_writeb(base_addr + (CySRER << index), 4433 cy_writeb(base_addr + (CySRER << index),
4447 cy_readb(base_addr + (CySRER << index)) | CyTxRdy); 4434 readb(base_addr + (CySRER << index)) | CyTxRdy);
4448 CY_UNLOCK(info, flags); 4435 CY_UNLOCK(info, flags);
4449 } else { 4436 } else {
4450 /* Nothing to do! */ 4437 /* Nothing to do! */
@@ -4537,7 +4524,7 @@ cyy_init_card(void __iomem * true_base_addr, int index)
4537 base_addr = 4524 base_addr =
4538 true_base_addr + (cy_chip_offset[chip_number] << index); 4525 true_base_addr + (cy_chip_offset[chip_number] << index);
4539 mdelay(1); 4526 mdelay(1);
4540 if (cy_readb(base_addr + (CyCCR << index)) != 0x00) { 4527 if (readb(base_addr + (CyCCR << index)) != 0x00) {
4541 /************* 4528 /*************
4542 printk(" chip #%d at %#6lx is never idle (CCR != 0)\n", 4529 printk(" chip #%d at %#6lx is never idle (CCR != 0)\n",
4543 chip_number, (unsigned long)base_addr); 4530 chip_number, (unsigned long)base_addr);
@@ -4554,7 +4541,7 @@ cyy_init_card(void __iomem * true_base_addr, int index)
4554 chip 4 GFRCR register appears at chip 0, there is no chip 4 4541 chip 4 GFRCR register appears at chip 0, there is no chip 4
4555 and this must be a Cyclom-16Y, not a Cyclom-32Ye. 4542 and this must be a Cyclom-16Y, not a Cyclom-32Ye.
4556 */ 4543 */
4557 if (chip_number == 4 && cy_readb(true_base_addr + 4544 if (chip_number == 4 && readb(true_base_addr +
4558 (cy_chip_offset[0] << index) + 4545 (cy_chip_offset[0] << index) +
4559 (CyGFRCR << index)) == 0) { 4546 (CyGFRCR << index)) == 0) {
4560 return chip_number; 4547 return chip_number;
@@ -4563,7 +4550,7 @@ cyy_init_card(void __iomem * true_base_addr, int index)
4563 cy_writeb(base_addr + (CyCCR << index), CyCHIP_RESET); 4550 cy_writeb(base_addr + (CyCCR << index), CyCHIP_RESET);
4564 mdelay(1); 4551 mdelay(1);
4565 4552
4566 if (cy_readb(base_addr + (CyGFRCR << index)) == 0x00) { 4553 if (readb(base_addr + (CyGFRCR << index)) == 0x00) {
4567 /* 4554 /*
4568 printk(" chip #%d at %#6lx is not responding ", 4555 printk(" chip #%d at %#6lx is not responding ",
4569 chip_number, (unsigned long)base_addr); 4556 chip_number, (unsigned long)base_addr);
@@ -4571,7 +4558,7 @@ cyy_init_card(void __iomem * true_base_addr, int index)
4571 */ 4558 */
4572 return chip_number; 4559 return chip_number;
4573 } 4560 }
4574 if ((0xf0 & (cy_readb(base_addr + (CyGFRCR << index)))) != 4561 if ((0xf0 & (readb(base_addr + (CyGFRCR << index)))) !=
4575 0x40) { 4562 0x40) {
4576 /* 4563 /*
4577 printk(" chip #%d at %#6lx is not valid (GFRCR == " 4564 printk(" chip #%d at %#6lx is not valid (GFRCR == "
@@ -4582,7 +4569,7 @@ cyy_init_card(void __iomem * true_base_addr, int index)
4582 return chip_number; 4569 return chip_number;
4583 } 4570 }
4584 cy_writeb(base_addr + (CyGCR << index), CyCH0_SERIAL); 4571 cy_writeb(base_addr + (CyGCR << index), CyCH0_SERIAL);
4585 if (cy_readb(base_addr + (CyGFRCR << index)) >= CD1400_REV_J) { 4572 if (readb(base_addr + (CyGFRCR << index)) >= CD1400_REV_J) {
4586 /* It is a CD1400 rev. J or later */ 4573 /* It is a CD1400 rev. J or later */
4587 /* Impossible to reach 5ms with this chip. 4574 /* Impossible to reach 5ms with this chip.
4588 Changed to 2ms instead (f = 500 Hz). */ 4575 Changed to 2ms instead (f = 500 Hz). */
@@ -4595,7 +4582,7 @@ cyy_init_card(void __iomem * true_base_addr, int index)
4595 /* 4582 /*
4596 printk(" chip #%d at %#6lx is rev 0x%2x\n", 4583 printk(" chip #%d at %#6lx is rev 0x%2x\n",
4597 chip_number, (unsigned long)base_addr, 4584 chip_number, (unsigned long)base_addr,
4598 cy_readb(base_addr+(CyGFRCR<<index))); 4585 readb(base_addr+(CyGFRCR<<index)));
4599 */ 4586 */
4600 } 4587 }
4601 return chip_number; 4588 return chip_number;
@@ -4717,14 +4704,14 @@ static int __init cy_detect_isa(void)
4717static void plx_init(void __iomem * addr, __u32 initctl) 4704static void plx_init(void __iomem * addr, __u32 initctl)
4718{ 4705{
4719 /* Reset PLX */ 4706 /* Reset PLX */
4720 cy_writel(addr + initctl, cy_readl(addr + initctl) | 0x40000000); 4707 cy_writel(addr + initctl, readl(addr + initctl) | 0x40000000);
4721 udelay(100L); 4708 udelay(100L);
4722 cy_writel(addr + initctl, cy_readl(addr + initctl) & ~0x40000000); 4709 cy_writel(addr + initctl, readl(addr + initctl) & ~0x40000000);
4723 4710
4724 /* Reload Config. Registers from EEPROM */ 4711 /* Reload Config. Registers from EEPROM */
4725 cy_writel(addr + initctl, cy_readl(addr + initctl) | 0x20000000); 4712 cy_writel(addr + initctl, readl(addr + initctl) | 0x20000000);
4726 udelay(100L); 4713 udelay(100L);
4727 cy_writel(addr + initctl, cy_readl(addr + initctl) & ~0x20000000); 4714 cy_writel(addr + initctl, readl(addr + initctl) & ~0x20000000);
4728} 4715}
4729 4716
4730/* 4717/*
@@ -4879,7 +4866,7 @@ static int __init cy_detect_pci(void)
4879 cy_card[j].pdev = pdev; 4866 cy_card[j].pdev = pdev;
4880 4867
4881 /* enable interrupts in the PCI interface */ 4868 /* enable interrupts in the PCI interface */
4882 plx_ver = cy_readb(cy_pci_addr2 + CyPLX_VER) & 0x0f; 4869 plx_ver = readb(cy_pci_addr2 + CyPLX_VER) & 0x0f;
4883 switch (plx_ver) { 4870 switch (plx_ver) {
4884 case PLX_9050: 4871 case PLX_9050:
4885 4872
@@ -4900,8 +4887,7 @@ static int __init cy_detect_pci(void)
4900 cy_pci_irq); 4887 cy_pci_irq);
4901 4888
4902 cy_writew(cy_pci_addr0 + 0x68, 4889 cy_writew(cy_pci_addr0 + 0x68,
4903 cy_readw(cy_pci_addr0 + 4890 readw(cy_pci_addr0 + 0x68) | 0x0900);
4904 0x68) | 0x0900);
4905 break; 4891 break;
4906 } 4892 }
4907 4893
@@ -4940,7 +4926,7 @@ static int __init cy_detect_pci(void)
4940 4926
4941 /* Disable interrupts on the PLX before resetting it */ 4927 /* Disable interrupts on the PLX before resetting it */
4942 cy_writew(cy_pci_addr0 + 0x68, 4928 cy_writew(cy_pci_addr0 + 0x68,
4943 cy_readw(cy_pci_addr0 + 0x68) & ~0x0900); 4929 readw(cy_pci_addr0 + 0x68) & ~0x0900);
4944 4930
4945 plx_init(cy_pci_addr0, 0x6c); 4931 plx_init(cy_pci_addr0, 0x6c);
4946 /* For some yet unknown reason, once the PLX9060 reloads 4932 /* For some yet unknown reason, once the PLX9060 reloads
@@ -4951,9 +4937,8 @@ static int __init cy_detect_pci(void)
4951 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 4937 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE,
4952 cy_pci_irq); 4938 cy_pci_irq);
4953 4939
4954 mailbox = 4940 mailbox = (__u32)readl(&((struct RUNTIME_9060 __iomem *)
4955 (__u32)cy_readl(&((struct RUNTIME_9060 __iomem *) 4941 cy_pci_addr0)->mail_box_0);
4956 cy_pci_addr0)->mail_box_0);
4957 4942
4958 if (pci_resource_flags(pdev, 2) & IORESOURCE_IO) { 4943 if (pci_resource_flags(pdev, 2) & IORESOURCE_IO) {
4959 printk(" Warning: PCI I/O bit incorrectly " 4944 printk(" Warning: PCI I/O bit incorrectly "
@@ -5005,10 +4990,10 @@ static int __init cy_detect_pci(void)
5005 WIN_CREG); 4990 WIN_CREG);
5006 printk("Cyclades-8Zo/PCI: FPGA id %lx, ver " 4991 printk("Cyclades-8Zo/PCI: FPGA id %lx, ver "
5007 "%lx\n", (ulong) (0xff & 4992 "%lx\n", (ulong) (0xff &
5008 cy_readl(&((struct CUSTOM_REG *) 4993 readl(&((struct CUSTOM_REG *)
5009 (cy_pci_addr2))->fpga_id)), 4994 (cy_pci_addr2))->fpga_id)),
5010 (ulong)(0xff & 4995 (ulong)(0xff &
5011 cy_readl(&((struct CUSTOM_REG *) 4996 readl(&((struct CUSTOM_REG *)
5012 (cy_pci_addr2))-> 4997 (cy_pci_addr2))->
5013 fpga_version))); 4998 fpga_version)));
5014 cy_writel(&((struct RUNTIME_9060 *) 4999 cy_writel(&((struct RUNTIME_9060 *)
@@ -5113,7 +5098,7 @@ static int __init cy_detect_pci(void)
5113 Ze_pdev[j] = Ze_pdev[j + 1]; 5098 Ze_pdev[j] = Ze_pdev[j + 1];
5114 } 5099 }
5115 ZeIndex--; 5100 ZeIndex--;
5116 mailbox = (__u32)cy_readl(&((struct RUNTIME_9060 __iomem *) 5101 mailbox = (__u32)readl(&((struct RUNTIME_9060 __iomem *)
5117 cy_pci_addr0)->mail_box_0); 5102 cy_pci_addr0)->mail_box_0);
5118#ifdef CY_PCI_DEBUG 5103#ifdef CY_PCI_DEBUG
5119 printk("Cyclades-Z/PCI: relocate winaddr=0x%lx ctladdr=0x%lx\n", 5104 printk("Cyclades-Z/PCI: relocate winaddr=0x%lx ctladdr=0x%lx\n",
@@ -5382,7 +5367,7 @@ static int __init cy_init(void)
5382 cinfo = &cy_card[board]; 5367 cinfo = &cy_card[board];
5383 if (cinfo->num_chips == -1) { /* Cyclades-Z */ 5368 if (cinfo->num_chips == -1) { /* Cyclades-Z */
5384 number_z_boards++; 5369 number_z_boards++;
5385 mailbox = cy_readl(&((struct RUNTIME_9060 __iomem *) 5370 mailbox = readl(&((struct RUNTIME_9060 __iomem *)
5386 cy_card[board].ctl_addr)-> 5371 cy_card[board].ctl_addr)->
5387 mail_box_0); 5372 mail_box_0);
5388 nports = (mailbox == ZE_V1) ? ZE_V1_NPORTS : 8; 5373 nports = (mailbox == ZE_V1) ? ZE_V1_NPORTS : 8;
@@ -5478,7 +5463,7 @@ static int __init cy_init(void)
5478 info->icount.overrun = info->icount.brk = 0; 5463 info->icount.overrun = info->icount.brk = 0;
5479 chip_number = (port - cinfo->first_line) / 4; 5464 chip_number = (port - cinfo->first_line) / 4;
5480 if ((info->chip_rev = 5465 if ((info->chip_rev =
5481 cy_readb(cinfo->base_addr + 5466 readb(cinfo->base_addr +
5482 (cy_chip_offset[chip_number] << 5467 (cy_chip_offset[chip_number] <<
5483 index) + (CyGFRCR << index))) >= 5468 index) + (CyGFRCR << index))) >=
5484 CD1400_REV_J) { 5469 CD1400_REV_J) {
diff --git a/include/linux/cyclades.h b/include/linux/cyclades.h
index 4c5b4763f5b8..f0ad61f69792 100644
--- a/include/linux/cyclades.h
+++ b/include/linux/cyclades.h
@@ -539,13 +539,9 @@ struct cyclades_chip {
539 * (required to support Alpha systems) * 539 * (required to support Alpha systems) *
540 ***************************************/ 540 ***************************************/
541 541
542#define cy_writeb(port,val) {writeb((val),(port)); mb();} 542#define cy_writeb(port,val) do { writeb((val), (port)); mb(); } while (0)
543#define cy_writew(port,val) {writew((val),(port)); mb();} 543#define cy_writew(port,val) do { writew((val), (port)); mb(); } while (0)
544#define cy_writel(port,val) {writel((val),(port)); mb();} 544#define cy_writel(port,val) do { writel((val), (port)); mb(); } while (0)
545
546#define cy_readb(port) readb(port)
547#define cy_readw(port) readw(port)
548#define cy_readl(port) readl(port)
549 545
550/* 546/*
551 * Statistics counters 547 * Statistics counters
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 04:39:08 -0500