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authorTakashi Iwai <tiwai@suse.de>2010-04-27 09:35:59 -0400
committerTakashi Iwai <tiwai@suse.de>2010-04-27 09:35:59 -0400
commitcb7b76961f73e4ae934d44f7b2e7ba974442f2fe (patch)
treeeb51f7cfb942433ff111d0dfcf0def8411335e20
parentb28528a124d0235d84e6c9b3edeedd70f8767740 (diff)
parent07779fdd1a236145b5f5dc6916c6b84d9712b305 (diff)
Merge branch 'for-2.6.35' of git://git.kernel.org/pub/scm/linux/kernel/git/lrg/asoc-2.6 into topic/asoc
-rw-r--r--sound/soc/codecs/tlv320aic3x.c81
-rw-r--r--sound/soc/codecs/tlv320dac33.c250
2 files changed, 277 insertions, 54 deletions
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 556123b4059c..584bc1e67f76 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -38,6 +38,7 @@
38#include <linux/delay.h> 38#include <linux/delay.h>
39#include <linux/pm.h> 39#include <linux/pm.h>
40#include <linux/i2c.h> 40#include <linux/i2c.h>
41#include <linux/regulator/consumer.h>
41#include <linux/platform_device.h> 42#include <linux/platform_device.h>
42#include <sound/core.h> 43#include <sound/core.h>
43#include <sound/pcm.h> 44#include <sound/pcm.h>
@@ -49,11 +50,18 @@
49 50
50#include "tlv320aic3x.h" 51#include "tlv320aic3x.h"
51 52
52#define AIC3X_VERSION "0.2" 53#define AIC3X_NUM_SUPPLIES 4
54static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
55 "IOVDD", /* I/O Voltage */
56 "DVDD", /* Digital Core Voltage */
57 "AVDD", /* Analog DAC Voltage */
58 "DRVDD", /* ADC Analog and Output Driver Voltage */
59};
53 60
54/* codec private data */ 61/* codec private data */
55struct aic3x_priv { 62struct aic3x_priv {
56 struct snd_soc_codec codec; 63 struct snd_soc_codec codec;
64 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
57 unsigned int sysclk; 65 unsigned int sysclk;
58 int master; 66 int master;
59}; 67};
@@ -999,7 +1007,8 @@ static int aic3x_set_bias_level(struct snd_soc_codec *codec,
999 1007
1000 switch (level) { 1008 switch (level) {
1001 case SND_SOC_BIAS_ON: 1009 case SND_SOC_BIAS_ON:
1002 /* all power is driven by DAPM system */ 1010 break;
1011 case SND_SOC_BIAS_PREPARE:
1003 if (aic3x->master) { 1012 if (aic3x->master) {
1004 /* enable pll */ 1013 /* enable pll */
1005 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); 1014 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
@@ -1007,48 +1016,9 @@ static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1007 reg | PLL_ENABLE); 1016 reg | PLL_ENABLE);
1008 } 1017 }
1009 break; 1018 break;
1010 case SND_SOC_BIAS_PREPARE:
1011 break;
1012 case SND_SOC_BIAS_STANDBY: 1019 case SND_SOC_BIAS_STANDBY:
1013 /* 1020 /* fall through and disable pll */
1014 * all power is driven by DAPM system,
1015 * so output power is safe if bypass was set
1016 */
1017 if (aic3x->master) {
1018 /* disable pll */
1019 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1020 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1021 reg & ~PLL_ENABLE);
1022 }
1023 break;
1024 case SND_SOC_BIAS_OFF: 1021 case SND_SOC_BIAS_OFF:
1025 /* force all power off */
1026 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
1027 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
1028 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
1029 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
1030
1031 reg = aic3x_read_reg_cache(codec, DAC_PWR);
1032 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
1033
1034 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1035 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
1036 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1037 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
1038
1039 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1040 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
1041 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1042 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
1043
1044 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1045 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
1046
1047 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1048 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
1049 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1050 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
1051
1052 if (aic3x->master) { 1022 if (aic3x->master) {
1053 /* disable pll */ 1023 /* disable pll */
1054 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); 1024 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
@@ -1308,6 +1278,9 @@ static int aic3x_unregister(struct aic3x_priv *aic3x)
1308 snd_soc_unregister_dai(&aic3x_dai); 1278 snd_soc_unregister_dai(&aic3x_dai);
1309 snd_soc_unregister_codec(&aic3x->codec); 1279 snd_soc_unregister_codec(&aic3x->codec);
1310 1280
1281 regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1282 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1283
1311 kfree(aic3x); 1284 kfree(aic3x);
1312 aic3x_codec = NULL; 1285 aic3x_codec = NULL;
1313 1286
@@ -1329,6 +1302,7 @@ static int aic3x_i2c_probe(struct i2c_client *i2c,
1329{ 1302{
1330 struct snd_soc_codec *codec; 1303 struct snd_soc_codec *codec;
1331 struct aic3x_priv *aic3x; 1304 struct aic3x_priv *aic3x;
1305 int ret, i;
1332 1306
1333 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL); 1307 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1334 if (aic3x == NULL) { 1308 if (aic3x == NULL) {
@@ -1344,7 +1318,30 @@ static int aic3x_i2c_probe(struct i2c_client *i2c,
1344 1318
1345 i2c_set_clientdata(i2c, aic3x); 1319 i2c_set_clientdata(i2c, aic3x);
1346 1320
1321 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1322 aic3x->supplies[i].supply = aic3x_supply_names[i];
1323
1324 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1325 aic3x->supplies);
1326 if (ret != 0) {
1327 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1328 goto err_get;
1329 }
1330
1331 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1332 aic3x->supplies);
1333 if (ret != 0) {
1334 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1335 goto err_enable;
1336 }
1337
1347 return aic3x_register(codec); 1338 return aic3x_register(codec);
1339
1340err_enable:
1341 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1342err_get:
1343 kfree(aic3x);
1344 return ret;
1348} 1345}
1349 1346
1350static int aic3x_i2c_remove(struct i2c_client *client) 1347static int aic3x_i2c_remove(struct i2c_client *client)
diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c
index 824bb354ebc9..3eddaec728c1 100644
--- a/sound/soc/codecs/tlv320dac33.c
+++ b/sound/soc/codecs/tlv320dac33.c
@@ -50,6 +50,18 @@
50 50
51#define LATENCY_TIME_MS 20 51#define LATENCY_TIME_MS 20
52 52
53#define MODE7_LTHR 10
54#define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
55
56#define BURST_BASEFREQ_HZ 49152000
57
58#define SAMPLES_TO_US(rate, samples) \
59 (1000000000 / ((rate * 1000) / samples))
60
61#define US_TO_SAMPLES(rate, us) \
62 (rate / (1000000 / us))
63
64
53static struct snd_soc_codec *tlv320dac33_codec; 65static struct snd_soc_codec *tlv320dac33_codec;
54 66
55enum dac33_state { 67enum dac33_state {
@@ -92,9 +104,18 @@ struct tlv320dac33_priv {
92 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */ 104 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
93 unsigned int nsample; /* burst read amount from host */ 105 unsigned int nsample; /* burst read amount from host */
94 u8 burst_bclkdiv; /* BCLK divider value in burst mode */ 106 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
107 unsigned int burst_rate; /* Interface speed in Burst modes */
95 108
96 int keep_bclk; /* Keep the BCLK continuously running 109 int keep_bclk; /* Keep the BCLK continuously running
97 * in FIFO modes */ 110 * in FIFO modes */
111 spinlock_t lock;
112 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
113 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
114
115 unsigned int mode1_us_burst; /* Time to burst read n number of
116 * samples */
117 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
118
98 enum dac33_state state; 119 enum dac33_state state;
99}; 120};
100 121
@@ -384,10 +405,14 @@ static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
384 return 0; 405 return 0;
385 406
386 if (ucontrol->value.integer.value[0] < dac33->nsample_min || 407 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
387 ucontrol->value.integer.value[0] > dac33->nsample_max) 408 ucontrol->value.integer.value[0] > dac33->nsample_max) {
388 ret = -EINVAL; 409 ret = -EINVAL;
389 else 410 } else {
390 dac33->nsample = ucontrol->value.integer.value[0]; 411 dac33->nsample = ucontrol->value.integer.value[0];
412 /* Re calculate the burst time */
413 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
414 dac33->nsample);
415 }
391 416
392 return ret; 417 return ret;
393} 418}
@@ -557,13 +582,34 @@ static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
557 switch (dac33->fifo_mode) { 582 switch (dac33->fifo_mode) {
558 case DAC33_FIFO_MODE1: 583 case DAC33_FIFO_MODE1:
559 dac33_write16(codec, DAC33_NSAMPLE_MSB, 584 dac33_write16(codec, DAC33_NSAMPLE_MSB,
560 DAC33_THRREG(dac33->nsample)); 585 DAC33_THRREG(dac33->nsample + dac33->alarm_threshold));
586
587 /* Take the timestamps */
588 spin_lock_irq(&dac33->lock);
589 dac33->t_stamp2 = ktime_to_us(ktime_get());
590 dac33->t_stamp1 = dac33->t_stamp2;
591 spin_unlock_irq(&dac33->lock);
592
561 dac33_write16(codec, DAC33_PREFILL_MSB, 593 dac33_write16(codec, DAC33_PREFILL_MSB,
562 DAC33_THRREG(dac33->alarm_threshold)); 594 DAC33_THRREG(dac33->alarm_threshold));
595 /* Enable Alarm Threshold IRQ with a delay */
596 udelay(SAMPLES_TO_US(dac33->burst_rate,
597 dac33->alarm_threshold));
598 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
563 break; 599 break;
564 case DAC33_FIFO_MODE7: 600 case DAC33_FIFO_MODE7:
601 /* Take the timestamp */
602 spin_lock_irq(&dac33->lock);
603 dac33->t_stamp1 = ktime_to_us(ktime_get());
604 /* Move back the timestamp with drain time */
605 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
606 spin_unlock_irq(&dac33->lock);
607
565 dac33_write16(codec, DAC33_PREFILL_MSB, 608 dac33_write16(codec, DAC33_PREFILL_MSB,
566 DAC33_THRREG(10)); 609 DAC33_THRREG(MODE7_LTHR));
610
611 /* Enable Upper Threshold IRQ */
612 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
567 break; 613 break;
568 default: 614 default:
569 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", 615 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
@@ -580,6 +626,11 @@ static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
580 626
581 switch (dac33->fifo_mode) { 627 switch (dac33->fifo_mode) {
582 case DAC33_FIFO_MODE1: 628 case DAC33_FIFO_MODE1:
629 /* Take the timestamp */
630 spin_lock_irq(&dac33->lock);
631 dac33->t_stamp2 = ktime_to_us(ktime_get());
632 spin_unlock_irq(&dac33->lock);
633
583 dac33_write16(codec, DAC33_NSAMPLE_MSB, 634 dac33_write16(codec, DAC33_NSAMPLE_MSB,
584 DAC33_THRREG(dac33->nsample)); 635 DAC33_THRREG(dac33->nsample));
585 break; 636 break;
@@ -632,7 +683,13 @@ static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
632 struct snd_soc_codec *codec = dev; 683 struct snd_soc_codec *codec = dev;
633 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 684 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
634 685
635 queue_work(dac33->dac33_wq, &dac33->work); 686 spin_lock(&dac33->lock);
687 dac33->t_stamp1 = ktime_to_us(ktime_get());
688 spin_unlock(&dac33->lock);
689
690 /* Do not schedule the workqueue in Mode7 */
691 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
692 queue_work(dac33->dac33_wq, &dac33->work);
636 693
637 return IRQ_HANDLED; 694 return IRQ_HANDLED;
638} 695}
@@ -782,11 +839,10 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
782 case DAC33_FIFO_MODE1: 839 case DAC33_FIFO_MODE1:
783 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B, 840 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
784 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL)); 841 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
785 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
786 break; 842 break;
787 case DAC33_FIFO_MODE7: 843 case DAC33_FIFO_MODE7:
788 /* Disable all interrupts */ 844 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
789 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0); 845 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
790 break; 846 break;
791 default: 847 default:
792 /* in FIFO bypass mode, the interrupts are not used */ 848 /* in FIFO bypass mode, the interrupts are not used */
@@ -864,10 +920,8 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
864 * Configure the threshold levels, and leave 10 sample space 920 * Configure the threshold levels, and leave 10 sample space
865 * at the bottom, and also at the top of the FIFO 921 * at the bottom, and also at the top of the FIFO
866 */ 922 */
867 dac33_write16(codec, DAC33_UTHR_MSB, 923 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(MODE7_UTHR));
868 DAC33_THRREG(DAC33_BUFFER_SIZE_SAMPLES - 10)); 924 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
869 dac33_write16(codec, DAC33_LTHR_MSB,
870 DAC33_THRREG(10));
871 break; 925 break;
872 default: 926 default:
873 break; 927 break;
@@ -886,6 +940,10 @@ static void dac33_calculate_times(struct snd_pcm_substream *substream)
886 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 940 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
887 unsigned int nsample_limit; 941 unsigned int nsample_limit;
888 942
943 /* In bypass mode we don't need to calculate */
944 if (!dac33->fifo_mode)
945 return;
946
889 /* Number of samples (16bit, stereo) in one period */ 947 /* Number of samples (16bit, stereo) in one period */
890 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4; 948 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
891 949
@@ -919,6 +977,24 @@ static void dac33_calculate_times(struct snd_pcm_substream *substream)
919 977
920 if (dac33->nsample > dac33->nsample_max) 978 if (dac33->nsample > dac33->nsample_max)
921 dac33->nsample = dac33->nsample_max; 979 dac33->nsample = dac33->nsample_max;
980
981 switch (dac33->fifo_mode) {
982 case DAC33_FIFO_MODE1:
983 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
984 dac33->nsample);
985 dac33->t_stamp1 = 0;
986 dac33->t_stamp2 = 0;
987 break;
988 case DAC33_FIFO_MODE7:
989 dac33->mode7_us_to_lthr =
990 SAMPLES_TO_US(substream->runtime->rate,
991 MODE7_UTHR - MODE7_LTHR + 1);
992 dac33->t_stamp1 = 0;
993 break;
994 default:
995 break;
996 }
997
922} 998}
923 999
924static int dac33_pcm_prepare(struct snd_pcm_substream *substream, 1000static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
@@ -963,6 +1039,151 @@ static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
963 return ret; 1039 return ret;
964} 1040}
965 1041
1042static snd_pcm_sframes_t dac33_dai_delay(
1043 struct snd_pcm_substream *substream,
1044 struct snd_soc_dai *dai)
1045{
1046 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1047 struct snd_soc_device *socdev = rtd->socdev;
1048 struct snd_soc_codec *codec = socdev->card->codec;
1049 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1050 unsigned long long t0, t1, t_now;
1051 unsigned int time_delta;
1052 int samples_out, samples_in, samples;
1053 snd_pcm_sframes_t delay = 0;
1054
1055 switch (dac33->fifo_mode) {
1056 case DAC33_FIFO_BYPASS:
1057 break;
1058 case DAC33_FIFO_MODE1:
1059 spin_lock(&dac33->lock);
1060 t0 = dac33->t_stamp1;
1061 t1 = dac33->t_stamp2;
1062 spin_unlock(&dac33->lock);
1063 t_now = ktime_to_us(ktime_get());
1064
1065 /* We have not started to fill the FIFO yet, delay is 0 */
1066 if (!t1)
1067 goto out;
1068
1069 if (t0 > t1) {
1070 /*
1071 * Phase 1:
1072 * After Alarm threshold, and before nSample write
1073 */
1074 time_delta = t_now - t0;
1075 samples_out = time_delta ? US_TO_SAMPLES(
1076 substream->runtime->rate,
1077 time_delta) : 0;
1078
1079 if (likely(dac33->alarm_threshold > samples_out))
1080 delay = dac33->alarm_threshold - samples_out;
1081 else
1082 delay = 0;
1083 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1084 /*
1085 * Phase 2:
1086 * After nSample write (during burst operation)
1087 */
1088 time_delta = t_now - t0;
1089 samples_out = time_delta ? US_TO_SAMPLES(
1090 substream->runtime->rate,
1091 time_delta) : 0;
1092
1093 time_delta = t_now - t1;
1094 samples_in = time_delta ? US_TO_SAMPLES(
1095 dac33->burst_rate,
1096 time_delta) : 0;
1097
1098 samples = dac33->alarm_threshold;
1099 samples += (samples_in - samples_out);
1100
1101 if (likely(samples > 0))
1102 delay = samples;
1103 else
1104 delay = 0;
1105 } else {
1106 /*
1107 * Phase 3:
1108 * After burst operation, before next alarm threshold
1109 */
1110 time_delta = t_now - t0;
1111 samples_out = time_delta ? US_TO_SAMPLES(
1112 substream->runtime->rate,
1113 time_delta) : 0;
1114
1115 samples_in = dac33->nsample;
1116 samples = dac33->alarm_threshold;
1117 samples += (samples_in - samples_out);
1118
1119 if (likely(samples > 0))
1120 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1121 DAC33_BUFFER_SIZE_SAMPLES : samples;
1122 else
1123 delay = 0;
1124 }
1125 break;
1126 case DAC33_FIFO_MODE7:
1127 spin_lock(&dac33->lock);
1128 t0 = dac33->t_stamp1;
1129 spin_unlock(&dac33->lock);
1130 t_now = ktime_to_us(ktime_get());
1131
1132 /* We have not started to fill the FIFO yet, delay is 0 */
1133 if (!t0)
1134 goto out;
1135
1136 if (t_now <= t0) {
1137 /*
1138 * Either the timestamps are messed or equal. Report
1139 * maximum delay
1140 */
1141 delay = MODE7_UTHR;
1142 goto out;
1143 }
1144
1145 time_delta = t_now - t0;
1146 if (time_delta <= dac33->mode7_us_to_lthr) {
1147 /*
1148 * Phase 1:
1149 * After burst (draining phase)
1150 */
1151 samples_out = US_TO_SAMPLES(
1152 substream->runtime->rate,
1153 time_delta);
1154
1155 if (likely(MODE7_UTHR > samples_out))
1156 delay = MODE7_UTHR - samples_out;
1157 else
1158 delay = 0;
1159 } else {
1160 /*
1161 * Phase 2:
1162 * During burst operation
1163 */
1164 time_delta = time_delta - dac33->mode7_us_to_lthr;
1165
1166 samples_out = US_TO_SAMPLES(
1167 substream->runtime->rate,
1168 time_delta);
1169 samples_in = US_TO_SAMPLES(
1170 dac33->burst_rate,
1171 time_delta);
1172 delay = MODE7_LTHR + samples_in - samples_out;
1173
1174 if (unlikely(delay > MODE7_UTHR))
1175 delay = MODE7_UTHR;
1176 }
1177 break;
1178 default:
1179 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1180 dac33->fifo_mode);
1181 break;
1182 }
1183out:
1184 return delay;
1185}
1186
966static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1187static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
967 int clk_id, unsigned int freq, int dir) 1188 int clk_id, unsigned int freq, int dir)
968{ 1189{
@@ -1174,6 +1395,7 @@ static struct snd_soc_dai_ops dac33_dai_ops = {
1174 .hw_params = dac33_hw_params, 1395 .hw_params = dac33_hw_params,
1175 .prepare = dac33_pcm_prepare, 1396 .prepare = dac33_pcm_prepare,
1176 .trigger = dac33_pcm_trigger, 1397 .trigger = dac33_pcm_trigger,
1398 .delay = dac33_dai_delay,
1177 .set_sysclk = dac33_set_dai_sysclk, 1399 .set_sysclk = dac33_set_dai_sysclk,
1178 .set_fmt = dac33_set_dai_fmt, 1400 .set_fmt = dac33_set_dai_fmt,
1179}; 1401};
@@ -1214,6 +1436,7 @@ static int __devinit dac33_i2c_probe(struct i2c_client *client,
1214 1436
1215 mutex_init(&codec->mutex); 1437 mutex_init(&codec->mutex);
1216 mutex_init(&dac33->mutex); 1438 mutex_init(&dac33->mutex);
1439 spin_lock_init(&dac33->lock);
1217 INIT_LIST_HEAD(&codec->dapm_widgets); 1440 INIT_LIST_HEAD(&codec->dapm_widgets);
1218 INIT_LIST_HEAD(&codec->dapm_paths); 1441 INIT_LIST_HEAD(&codec->dapm_paths);
1219 1442
@@ -1238,9 +1461,12 @@ static int __devinit dac33_i2c_probe(struct i2c_client *client,
1238 1461
1239 dac33->power_gpio = pdata->power_gpio; 1462 dac33->power_gpio = pdata->power_gpio;
1240 dac33->burst_bclkdiv = pdata->burst_bclkdiv; 1463 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1464 /* Pre calculate the burst rate */
1465 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
1241 dac33->keep_bclk = pdata->keep_bclk; 1466 dac33->keep_bclk = pdata->keep_bclk;
1242 dac33->irq = client->irq; 1467 dac33->irq = client->irq;
1243 dac33->nsample = NSAMPLE_MAX; 1468 dac33->nsample = NSAMPLE_MAX;
1469 dac33->nsample_max = NSAMPLE_MAX;
1244 /* Disable FIFO use by default */ 1470 /* Disable FIFO use by default */
1245 dac33->fifo_mode = DAC33_FIFO_BYPASS; 1471 dac33->fifo_mode = DAC33_FIFO_BYPASS;
1246 1472