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authorSylvain Munaut <tnt@246tNt.com>2007-09-16 06:53:29 -0400
committerGrant Likely <grant.likely@secretlab.ca>2007-10-16 19:09:49 -0400
commitba11c79aba8d8e9faf556a32bb8b414b4a846ac7 (patch)
treec5eff26bd39a2e3e217fdf6ad7bda90196a34e14
parent9ea68df515392a556388f12c876ca74654e37483 (diff)
[POWERPC] bestcomm: FEC task support
This is the microcode for the FEC task and the associated support code. The microcode itself comes directly from the offical API (v2.2) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat
-rw-r--r--arch/powerpc/sysdev/bestcomm/Kconfig7
-rw-r--r--arch/powerpc/sysdev/bestcomm/Makefile2
-rw-r--r--arch/powerpc/sysdev/bestcomm/bcom_fec_rx_task.c78
-rw-r--r--arch/powerpc/sysdev/bestcomm/bcom_fec_tx_task.c91
-rw-r--r--arch/powerpc/sysdev/bestcomm/fec.c270
-rw-r--r--arch/powerpc/sysdev/bestcomm/fec.h61
6 files changed, 509 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/bestcomm/Kconfig b/arch/powerpc/sysdev/bestcomm/Kconfig
index 9d087cefa22c..831763b0639e 100644
--- a/arch/powerpc/sysdev/bestcomm/Kconfig
+++ b/arch/powerpc/sysdev/bestcomm/Kconfig
@@ -23,3 +23,10 @@ config PPC_BESTCOMM_ATA
23 help 23 help
24 This option enables the support for the ATA task. 24 This option enables the support for the ATA task.
25 25
26config PPC_BESTCOMM_FEC
27 tristate "Bestcomm FEC tasks support"
28 depends on PPC_BESTCOMM
29 default n
30 help
31 This option enables the support for the FEC tasks.
32
diff --git a/arch/powerpc/sysdev/bestcomm/Makefile b/arch/powerpc/sysdev/bestcomm/Makefile
index b7a6a40c7d23..537d1744e6b9 100644
--- a/arch/powerpc/sysdev/bestcomm/Makefile
+++ b/arch/powerpc/sysdev/bestcomm/Makefile
@@ -4,7 +4,9 @@
4 4
5bestcomm-core-objs := bestcomm.o sram.o 5bestcomm-core-objs := bestcomm.o sram.o
6bestcomm-ata-objs := ata.o bcom_ata_task.o 6bestcomm-ata-objs := ata.o bcom_ata_task.o
7bestcomm-fec-objs := fec.o bcom_fec_rx_task.o bcom_fec_tx_task.o
7 8
8obj-$(CONFIG_PPC_BESTCOMM) += bestcomm-core.o 9obj-$(CONFIG_PPC_BESTCOMM) += bestcomm-core.o
9obj-$(CONFIG_PPC_BESTCOMM_ATA) += bestcomm-ata.o 10obj-$(CONFIG_PPC_BESTCOMM_ATA) += bestcomm-ata.o
11obj-$(CONFIG_PPC_BESTCOMM_FEC) += bestcomm-fec.o
10 12
diff --git a/arch/powerpc/sysdev/bestcomm/bcom_fec_rx_task.c b/arch/powerpc/sysdev/bestcomm/bcom_fec_rx_task.c
new file mode 100644
index 000000000000..a1ad6a02fcef
--- /dev/null
+++ b/arch/powerpc/sysdev/bestcomm/bcom_fec_rx_task.c
@@ -0,0 +1,78 @@
1/*
2 * Bestcomm FEC RX task microcode
3 *
4 * Copyright (c) 2004 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * Automatically created based on BestCommAPI-2.2/code_dma/image_rtos1/dma_image.hex
11 * on Tue Mar 22 11:19:38 2005 GMT
12 */
13
14#include <asm/types.h>
15
16/*
17 * The header consists of the following fields:
18 * u32 magic;
19 * u8 desc_size;
20 * u8 var_size;
21 * u8 inc_size;
22 * u8 first_var;
23 * u8 reserved[8];
24 *
25 * The size fields contain the number of 32-bit words.
26 */
27
28u32 bcom_fec_rx_task[] = {
29 /* header */
30 0x4243544b,
31 0x18060709,
32 0x00000000,
33 0x00000000,
34
35 /* Task descriptors */
36 0x808220e3, /* LCD: idx0 = var1, idx1 = var4; idx1 <= var3; idx0 += inc4, idx1 += inc3 */
37 0x10601010, /* DRD1A: var4 = var2; FN=0 MORE init=3 WS=0 RS=0 */
38 0xb8800264, /* LCD: idx2 = *idx1, idx3 = var0; idx2 < var9; idx2 += inc4, idx3 += inc4 */
39 0x10001308, /* DRD1A: var4 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
40 0x60140002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=2 RS=2 */
41 0x0cccfcca, /* DRD2B1: *idx3 = EU3(); EU3(*idx3,var10) */
42 0x80004000, /* LCDEXT: idx2 = 0x00000000; ; */
43 0xb8c58029, /* LCD: idx3 = *(idx1 + var00000015); idx3 once var0; idx3 += inc5 */
44 0x60000002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=0 RS=0 */
45 0x088cf8cc, /* DRD2B1: idx2 = EU3(); EU3(idx3,var12) */
46 0x991982f2, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var11; idx2 += inc6, idx3 += inc2 */
47 0x006acf80, /* DRD1A: *idx3 = *idx0; FN=0 init=3 WS=1 RS=1 */
48 0x80004000, /* LCDEXT: idx2 = 0x00000000; ; */
49 0x9999802d, /* LCD: idx3 = idx3; idx3 once var0; idx3 += inc5 */
50 0x70000002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
51 0x034cfc4e, /* DRD2B1: var13 = EU3(); EU3(*idx1,var14) */
52 0x00008868, /* DRD1A: idx2 = var13; FN=0 init=0 WS=0 RS=0 */
53 0x99198341, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var13; idx2 += inc0, idx3 += inc1 */
54 0x007ecf80, /* DRD1A: *idx3 = *idx0; FN=0 init=3 WS=3 RS=3 */
55 0x99198272, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var9; idx2 += inc6, idx3 += inc2 */
56 0x046acf80, /* DRD1A: *idx3 = *idx0; FN=0 INT init=3 WS=1 RS=1 */
57 0x9819002d, /* LCD: idx2 = idx0; idx2 once var0; idx2 += inc5 */
58 0x0060c790, /* DRD1A: *idx1 = *idx2; FN=0 init=3 WS=0 RS=0 */
59 0x000001f8, /* NOP */
60
61 /* VAR[9]-VAR[14] */
62 0x40000000,
63 0x7fff7fff,
64 0x00000000,
65 0x00000003,
66 0x40000008,
67 0x43ffffff,
68
69 /* INC[0]-INC[6] */
70 0x40000000,
71 0xe0000000,
72 0xe0000000,
73 0xa0000008,
74 0x20000000,
75 0x00000000,
76 0x4000ffff,
77};
78
diff --git a/arch/powerpc/sysdev/bestcomm/bcom_fec_tx_task.c b/arch/powerpc/sysdev/bestcomm/bcom_fec_tx_task.c
new file mode 100644
index 000000000000..b1c495c3a65a
--- /dev/null
+++ b/arch/powerpc/sysdev/bestcomm/bcom_fec_tx_task.c
@@ -0,0 +1,91 @@
1/*
2 * Bestcomm FEC TX task microcode
3 *
4 * Copyright (c) 2004 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * Automatically created based on BestCommAPI-2.2/code_dma/image_rtos1/dma_image.hex
11 * on Tue Mar 22 11:19:29 2005 GMT
12 */
13
14#include <asm/types.h>
15
16/*
17 * The header consists of the following fields:
18 * u32 magic;
19 * u8 desc_size;
20 * u8 var_size;
21 * u8 inc_size;
22 * u8 first_var;
23 * u8 reserved[8];
24 *
25 * The size fields contain the number of 32-bit words.
26 */
27
28u32 bcom_fec_tx_task[] = {
29 /* header */
30 0x4243544b,
31 0x2407070d,
32 0x00000000,
33 0x00000000,
34
35 /* Task descriptors */
36 0x8018001b, /* LCD: idx0 = var0; idx0 <= var0; idx0 += inc3 */
37 0x60000005, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 WS=0 RS=0 */
38 0x01ccfc0d, /* DRD2B1: var7 = EU3(); EU3(*idx0,var13) */
39 0x8082a123, /* LCD: idx0 = var1, idx1 = var5; idx1 <= var4; idx0 += inc4, idx1 += inc3 */
40 0x10801418, /* DRD1A: var5 = var3; FN=0 MORE init=4 WS=0 RS=0 */
41 0xf88103a4, /* LCDEXT: idx2 = *idx1, idx3 = var2; idx2 < var14; idx2 += inc4, idx3 += inc4 */
42 0x801a6024, /* LCD: idx4 = var0; ; idx4 += inc4 */
43 0x10001708, /* DRD1A: var5 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
44 0x60140002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=2 RS=2 */
45 0x0cccfccf, /* DRD2B1: *idx3 = EU3(); EU3(*idx3,var15) */
46 0x991a002c, /* LCD: idx2 = idx2, idx3 = idx4; idx2 once var0; idx2 += inc5, idx3 += inc4 */
47 0x70000002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
48 0x024cfc4d, /* DRD2B1: var9 = EU3(); EU3(*idx1,var13) */
49 0x60000003, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=3 EXT init=0 WS=0 RS=0 */
50 0x0cccf247, /* DRD2B1: *idx3 = EU3(); EU3(var9,var7) */
51 0x80004000, /* LCDEXT: idx2 = 0x00000000; ; */
52 0xb8c80029, /* LCD: idx3 = *(idx1 + var0000001a); idx3 once var0; idx3 += inc5 */
53 0x70000002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
54 0x088cf8d1, /* DRD2B1: idx2 = EU3(); EU3(idx3,var17) */
55 0x00002f10, /* DRD1A: var11 = idx2; FN=0 init=0 WS=0 RS=0 */
56 0x99198432, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var16; idx2 += inc6, idx3 += inc2 */
57 0x008ac398, /* DRD1A: *idx0 = *idx3; FN=0 init=4 WS=1 RS=1 */
58 0x80004000, /* LCDEXT: idx2 = 0x00000000; ; */
59 0x9999802d, /* LCD: idx3 = idx3; idx3 once var0; idx3 += inc5 */
60 0x70000002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
61 0x048cfc53, /* DRD2B1: var18 = EU3(); EU3(*idx1,var19) */
62 0x60000008, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=8 EXT init=0 WS=0 RS=0 */
63 0x088cf48b, /* DRD2B1: idx2 = EU3(); EU3(var18,var11) */
64 0x99198481, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var18; idx2 += inc0, idx3 += inc1 */
65 0x009ec398, /* DRD1A: *idx0 = *idx3; FN=0 init=4 WS=3 RS=3 */
66 0x991983b2, /* LCD: idx2 = idx2, idx3 = idx3; idx2 > var14; idx2 += inc6, idx3 += inc2 */
67 0x088ac398, /* DRD1A: *idx0 = *idx3; FN=0 TFD init=4 WS=1 RS=1 */
68 0x9919002d, /* LCD: idx2 = idx2; idx2 once var0; idx2 += inc5 */
69 0x60000005, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 WS=0 RS=0 */
70 0x0c4cf88e, /* DRD2B1: *idx1 = EU3(); EU3(idx2,var14) */
71 0x000001f8, /* NOP */
72
73 /* VAR[13]-VAR[19] */
74 0x0c000000,
75 0x40000000,
76 0x7fff7fff,
77 0x00000000,
78 0x00000003,
79 0x40000004,
80 0x43ffffff,
81
82 /* INC[0]-INC[6] */
83 0x40000000,
84 0xe0000000,
85 0xe0000000,
86 0xa0000008,
87 0x20000000,
88 0x00000000,
89 0x4000ffff,
90};
91
diff --git a/arch/powerpc/sysdev/bestcomm/fec.c b/arch/powerpc/sysdev/bestcomm/fec.c
new file mode 100644
index 000000000000..957a988d23ea
--- /dev/null
+++ b/arch/powerpc/sysdev/bestcomm/fec.c
@@ -0,0 +1,270 @@
1/*
2 * Bestcomm FEC tasks driver
3 *
4 *
5 * Copyright (C) 2006-2007 Sylvain Munaut <tnt@246tNt.com>
6 * Copyright (C) 2003-2004 MontaVista, Software, Inc.
7 * ( by Dale Farnsworth <dfarnsworth@mvista.com> )
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/types.h>
17#include <asm/io.h>
18
19#include "bestcomm.h"
20#include "bestcomm_priv.h"
21#include "fec.h"
22
23
24/* ======================================================================== */
25/* Task image/var/inc */
26/* ======================================================================== */
27
28/* fec tasks images */
29extern u32 bcom_fec_rx_task[];
30extern u32 bcom_fec_tx_task[];
31
32/* rx task vars that need to be set before enabling the task */
33struct bcom_fec_rx_var {
34 u32 enable; /* (u16*) address of task's control register */
35 u32 fifo; /* (u32*) address of fec's fifo */
36 u32 bd_base; /* (struct bcom_bd*) beginning of ring buffer */
37 u32 bd_last; /* (struct bcom_bd*) end of ring buffer */
38 u32 bd_start; /* (struct bcom_bd*) current bd */
39 u32 buffer_size; /* size of receive buffer */
40};
41
42/* rx task incs that need to be set before enabling the task */
43struct bcom_fec_rx_inc {
44 u16 pad0;
45 s16 incr_bytes;
46 u16 pad1;
47 s16 incr_dst;
48 u16 pad2;
49 s16 incr_dst_ma;
50};
51
52/* tx task vars that need to be set before enabling the task */
53struct bcom_fec_tx_var {
54 u32 DRD; /* (u32*) address of self-modified DRD */
55 u32 fifo; /* (u32*) address of fec's fifo */
56 u32 enable; /* (u16*) address of task's control register */
57 u32 bd_base; /* (struct bcom_bd*) beginning of ring buffer */
58 u32 bd_last; /* (struct bcom_bd*) end of ring buffer */
59 u32 bd_start; /* (struct bcom_bd*) current bd */
60 u32 buffer_size; /* set by uCode for each packet */
61};
62
63/* tx task incs that need to be set before enabling the task */
64struct bcom_fec_tx_inc {
65 u16 pad0;
66 s16 incr_bytes;
67 u16 pad1;
68 s16 incr_src;
69 u16 pad2;
70 s16 incr_src_ma;
71};
72
73/* private structure in the task */
74struct bcom_fec_priv {
75 phys_addr_t fifo;
76 int maxbufsize;
77};
78
79
80/* ======================================================================== */
81/* Task support code */
82/* ======================================================================== */
83
84struct bcom_task *
85bcom_fec_rx_init(int queue_len, phys_addr_t fifo, int maxbufsize)
86{
87 struct bcom_task *tsk;
88 struct bcom_fec_priv *priv;
89
90 tsk = bcom_task_alloc(queue_len, sizeof(struct bcom_fec_bd),
91 sizeof(struct bcom_fec_priv));
92 if (!tsk)
93 return NULL;
94
95 tsk->flags = BCOM_FLAGS_NONE;
96
97 priv = tsk->priv;
98 priv->fifo = fifo;
99 priv->maxbufsize = maxbufsize;
100
101 if (bcom_fec_rx_reset(tsk)) {
102 bcom_task_free(tsk);
103 return NULL;
104 }
105
106 return tsk;
107}
108EXPORT_SYMBOL_GPL(bcom_fec_rx_init);
109
110int
111bcom_fec_rx_reset(struct bcom_task *tsk)
112{
113 struct bcom_fec_priv *priv = tsk->priv;
114 struct bcom_fec_rx_var *var;
115 struct bcom_fec_rx_inc *inc;
116
117 /* Shutdown the task */
118 bcom_disable_task(tsk->tasknum);
119
120 /* Reset the microcode */
121 var = (struct bcom_fec_rx_var *) bcom_task_var(tsk->tasknum);
122 inc = (struct bcom_fec_rx_inc *) bcom_task_inc(tsk->tasknum);
123
124 if (bcom_load_image(tsk->tasknum, bcom_fec_rx_task))
125 return -1;
126
127 var->enable = bcom_eng->regs_base +
128 offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]);
129 var->fifo = (u32) priv->fifo;
130 var->bd_base = tsk->bd_pa;
131 var->bd_last = tsk->bd_pa + ((tsk->num_bd-1) * tsk->bd_size);
132 var->bd_start = tsk->bd_pa;
133 var->buffer_size = priv->maxbufsize;
134
135 inc->incr_bytes = -(s16)sizeof(u32); /* These should be in the */
136 inc->incr_dst = sizeof(u32); /* task image, but we stick */
137 inc->incr_dst_ma= sizeof(u8); /* to the official ones */
138
139 /* Reset the BDs */
140 tsk->index = 0;
141 tsk->outdex = 0;
142
143 memset(tsk->bd, 0x00, tsk->num_bd * tsk->bd_size);
144
145 /* Configure some stuff */
146 bcom_set_task_pragma(tsk->tasknum, BCOM_FEC_RX_BD_PRAGMA);
147 bcom_set_task_auto_start(tsk->tasknum, tsk->tasknum);
148
149 out_8(&bcom_eng->regs->ipr[BCOM_INITIATOR_FEC_RX], BCOM_IPR_FEC_RX);
150
151 out_be32(&bcom_eng->regs->IntPend, 1<<tsk->tasknum); /* Clear ints */
152
153 return 0;
154}
155EXPORT_SYMBOL_GPL(bcom_fec_rx_reset);
156
157void
158bcom_fec_rx_release(struct bcom_task *tsk)
159{
160 /* Nothing special for the FEC tasks */
161 bcom_task_free(tsk);
162}
163EXPORT_SYMBOL_GPL(bcom_fec_rx_release);
164
165
166
167 /* Return 2nd to last DRD */
168 /* This is an ugly hack, but at least it's only done
169 once at initialization */
170static u32 *self_modified_drd(int tasknum)
171{
172 u32 *desc;
173 int num_descs;
174 int drd_count;
175 int i;
176
177 num_descs = bcom_task_num_descs(tasknum);
178 desc = bcom_task_desc(tasknum) + num_descs - 1;
179 drd_count = 0;
180 for (i=0; i<num_descs; i++, desc--)
181 if (bcom_desc_is_drd(*desc) && ++drd_count == 3)
182 break;
183 return desc;
184}
185
186struct bcom_task *
187bcom_fec_tx_init(int queue_len, phys_addr_t fifo)
188{
189 struct bcom_task *tsk;
190 struct bcom_fec_priv *priv;
191
192 tsk = bcom_task_alloc(queue_len, sizeof(struct bcom_fec_bd),
193 sizeof(struct bcom_fec_priv));
194 if (!tsk)
195 return NULL;
196
197 tsk->flags = BCOM_FLAGS_ENABLE_TASK;
198
199 priv = tsk->priv;
200 priv->fifo = fifo;
201
202 if (bcom_fec_tx_reset(tsk)) {
203 bcom_task_free(tsk);
204 return NULL;
205 }
206
207 return tsk;
208}
209EXPORT_SYMBOL_GPL(bcom_fec_tx_init);
210
211int
212bcom_fec_tx_reset(struct bcom_task *tsk)
213{
214 struct bcom_fec_priv *priv = tsk->priv;
215 struct bcom_fec_tx_var *var;
216 struct bcom_fec_tx_inc *inc;
217
218 /* Shutdown the task */
219 bcom_disable_task(tsk->tasknum);
220
221 /* Reset the microcode */
222 var = (struct bcom_fec_tx_var *) bcom_task_var(tsk->tasknum);
223 inc = (struct bcom_fec_tx_inc *) bcom_task_inc(tsk->tasknum);
224
225 if (bcom_load_image(tsk->tasknum, bcom_fec_tx_task))
226 return -1;
227
228 var->enable = bcom_eng->regs_base +
229 offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]);
230 var->fifo = (u32) priv->fifo;
231 var->DRD = bcom_sram_va2pa(self_modified_drd(tsk->tasknum));
232 var->bd_base = tsk->bd_pa;
233 var->bd_last = tsk->bd_pa + ((tsk->num_bd-1) * tsk->bd_size);
234 var->bd_start = tsk->bd_pa;
235
236 inc->incr_bytes = -(s16)sizeof(u32); /* These should be in the */
237 inc->incr_src = sizeof(u32); /* task image, but we stick */
238 inc->incr_src_ma= sizeof(u8); /* to the official ones */
239
240 /* Reset the BDs */
241 tsk->index = 0;
242 tsk->outdex = 0;
243
244 memset(tsk->bd, 0x00, tsk->num_bd * tsk->bd_size);
245
246 /* Configure some stuff */
247 bcom_set_task_pragma(tsk->tasknum, BCOM_FEC_TX_BD_PRAGMA);
248 bcom_set_task_auto_start(tsk->tasknum, tsk->tasknum);
249
250 out_8(&bcom_eng->regs->ipr[BCOM_INITIATOR_FEC_TX], BCOM_IPR_FEC_TX);
251
252 out_be32(&bcom_eng->regs->IntPend, 1<<tsk->tasknum); /* Clear ints */
253
254 return 0;
255}
256EXPORT_SYMBOL_GPL(bcom_fec_tx_reset);
257
258void
259bcom_fec_tx_release(struct bcom_task *tsk)
260{
261 /* Nothing special for the FEC tasks */
262 bcom_task_free(tsk);
263}
264EXPORT_SYMBOL_GPL(bcom_fec_tx_release);
265
266
267MODULE_DESCRIPTION("BestComm FEC tasks driver");
268MODULE_AUTHOR("Dale Farnsworth <dfarnsworth@mvista.com>");
269MODULE_LICENSE("GPL v2");
270
diff --git a/arch/powerpc/sysdev/bestcomm/fec.h b/arch/powerpc/sysdev/bestcomm/fec.h
new file mode 100644
index 000000000000..ee565d94d503
--- /dev/null
+++ b/arch/powerpc/sysdev/bestcomm/fec.h
@@ -0,0 +1,61 @@
1/*
2 * Header for Bestcomm FEC tasks driver
3 *
4 *
5 * Copyright (C) 2006-2007 Sylvain Munaut <tnt@246tNt.com>
6 * Copyright (C) 2003-2004 MontaVista, Software, Inc.
7 * ( by Dale Farnsworth <dfarnsworth@mvista.com> )
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#ifndef __BESTCOMM_FEC_H__
15#define __BESTCOMM_FEC_H__
16
17
18struct bcom_fec_bd {
19 u32 status;
20 u32 skb_pa;
21};
22
23#define BCOM_FEC_TX_BD_TFD 0x08000000ul /* transmit frame done */
24#define BCOM_FEC_TX_BD_TC 0x04000000ul /* transmit CRC */
25#define BCOM_FEC_TX_BD_ABC 0x02000000ul /* append bad CRC */
26
27#define BCOM_FEC_RX_BD_L 0x08000000ul /* buffer is last in frame */
28#define BCOM_FEC_RX_BD_BC 0x00800000ul /* DA is broadcast */
29#define BCOM_FEC_RX_BD_MC 0x00400000ul /* DA is multicast and not broadcast */
30#define BCOM_FEC_RX_BD_LG 0x00200000ul /* Rx frame length violation */
31#define BCOM_FEC_RX_BD_NO 0x00100000ul /* Rx non-octet aligned frame */
32#define BCOM_FEC_RX_BD_CR 0x00040000ul /* Rx CRC error */
33#define BCOM_FEC_RX_BD_OV 0x00020000ul /* overrun */
34#define BCOM_FEC_RX_BD_TR 0x00010000ul /* Rx frame truncated */
35#define BCOM_FEC_RX_BD_LEN_MASK 0x000007fful /* mask for length of received frame */
36#define BCOM_FEC_RX_BD_ERRORS (BCOM_FEC_RX_BD_LG | BCOM_FEC_RX_BD_NO | \
37 BCOM_FEC_RX_BD_CR | BCOM_FEC_RX_BD_OV | BCOM_FEC_RX_BD_TR)
38
39
40extern struct bcom_task *
41bcom_fec_rx_init(int queue_len, phys_addr_t fifo, int maxbufsize);
42
43extern int
44bcom_fec_rx_reset(struct bcom_task *tsk);
45
46extern void
47bcom_fec_rx_release(struct bcom_task *tsk);
48
49
50extern struct bcom_task *
51bcom_fec_tx_init(int queue_len, phys_addr_t fifo);
52
53extern int
54bcom_fec_tx_reset(struct bcom_task *tsk);
55
56extern void
57bcom_fec_tx_release(struct bcom_task *tsk);
58
59
60#endif /* __BESTCOMM_FEC_H__ */
61
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