diff options
author | Matthew Wilcox <matthew@wil.cx> | 2007-09-09 10:56:38 -0400 |
---|---|---|
committer | James Bottomley <jejb@mulgrave.localdomain> | 2007-10-12 14:48:11 -0400 |
commit | b009bef6cd2c6c2b870088d9ae67dbc4ec2ca317 (patch) | |
tree | 613913c0dc95d2ade63ced852b24d23b9c4b09c4 | |
parent | faac48ecf475c8e214190dabe600585e0bd4f455 (diff) |
[SCSI] advansys: Remove some custom wrappers
- Replace ASC_ASSERT() with BUG_ON().
In a few places, get rid of the assertion altogether -- the ensuing
crash will tell us all we need to know. Use BUG() where it fits better
than BUG_ON(). Also fix a fencepost error in advansys_proc_info().
- Replace DvcSleepMilliSecond with mdelay.
Despite its name using 'sleep', the implementation was a delay.
I've marked some places with XXX where we should probably be using
msleep instead. They need to be audited to be sure we can sleep in
that context.
- Replace DvcDelayMicroSecond with udelay.
- Replace DvcDelayNanoSecond with udelay too.
All callers were multiples of 1000.
- Remove DvcEnterCritical and DvcLeaveCritical.
These functions are no-ops, and as the comments said, the spinlock
protects the critical sections.
Signed-off-by: Matthew Wilcox <matthew@wil.cx>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
-rw-r--r-- | drivers/scsi/advansys.c | 213 |
1 files changed, 49 insertions, 164 deletions
diff --git a/drivers/scsi/advansys.c b/drivers/scsi/advansys.c index 60a918820d0d..9c5d37d9c79a 100644 --- a/drivers/scsi/advansys.c +++ b/drivers/scsi/advansys.c | |||
@@ -70,9 +70,6 @@ | |||
70 | */ | 70 | */ |
71 | #warning this driver is still not properly converted to the DMA API | 71 | #warning this driver is still not properly converted to the DMA API |
72 | 72 | ||
73 | /* Enable driver assertions. */ | ||
74 | #define ADVANSYS_ASSERT | ||
75 | |||
76 | /* Enable driver /proc statistics. */ | 73 | /* Enable driver /proc statistics. */ |
77 | #define ADVANSYS_STATS | 74 | #define ADVANSYS_STATS |
78 | 75 | ||
@@ -1121,10 +1118,6 @@ static uchar AscGetChipScsiCtrl(PortAddr); | |||
1121 | static uchar AscGetChipVersion(PortAddr, ushort); | 1118 | static uchar AscGetChipVersion(PortAddr, ushort); |
1122 | static ASC_DCNT AscLoadMicroCode(PortAddr, ushort, uchar *, ushort); | 1119 | static ASC_DCNT AscLoadMicroCode(PortAddr, ushort, uchar *, ushort); |
1123 | static void AscToggleIRQAct(PortAddr); | 1120 | static void AscToggleIRQAct(PortAddr); |
1124 | static inline ulong DvcEnterCritical(void); | ||
1125 | static inline void DvcLeaveCritical(ulong); | ||
1126 | static void DvcSleepMilliSecond(ASC_DCNT); | ||
1127 | static void DvcDelayNanoSecond(ASC_DVC_VAR *, ASC_DCNT); | ||
1128 | static void DvcPutScsiQ(PortAddr, ushort, uchar *, int); | 1121 | static void DvcPutScsiQ(PortAddr, ushort, uchar *, int); |
1129 | static void DvcGetQinfo(PortAddr, ushort, uchar *, int); | 1122 | static void DvcGetQinfo(PortAddr, ushort, uchar *, int); |
1130 | static ushort AscInitAsc1000Driver(ASC_DVC_VAR *); | 1123 | static ushort AscInitAsc1000Driver(ASC_DVC_VAR *); |
@@ -2226,15 +2219,8 @@ typedef struct adv_scsi_req_q { | |||
2226 | 2219 | ||
2227 | #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */ | 2220 | #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */ |
2228 | 2221 | ||
2229 | /* | ||
2230 | * Device drivers must define the following functions. | ||
2231 | */ | ||
2232 | static inline ulong DvcEnterCritical(void); | ||
2233 | static inline void DvcLeaveCritical(ulong); | ||
2234 | static void DvcSleepMilliSecond(ADV_DCNT); | ||
2235 | static ADV_PADDR DvcGetPhyAddr(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *, | 2222 | static ADV_PADDR DvcGetPhyAddr(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *, |
2236 | uchar *, ASC_SDCNT *, int); | 2223 | uchar *, ASC_SDCNT *, int); |
2237 | static void DvcDelayMicroSecond(ADV_DVC_VAR *, ushort); | ||
2238 | 2224 | ||
2239 | /* | 2225 | /* |
2240 | * Adv Library functions available to drivers. | 2226 | * Adv Library functions available to drivers. |
@@ -2670,24 +2656,6 @@ do { \ | |||
2670 | ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len)); | 2656 | ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len)); |
2671 | #endif /* ADVANSYS_DEBUG */ | 2657 | #endif /* ADVANSYS_DEBUG */ |
2672 | 2658 | ||
2673 | #ifndef ADVANSYS_ASSERT | ||
2674 | #define ASC_ASSERT(a) | ||
2675 | #else /* ADVANSYS_ASSERT */ | ||
2676 | |||
2677 | #define ASC_ASSERT(a) \ | ||
2678 | { \ | ||
2679 | if (!(a)) { \ | ||
2680 | printk("ASC_ASSERT() Failure: file %s, line %d\n", \ | ||
2681 | __FILE__, __LINE__); \ | ||
2682 | } \ | ||
2683 | } | ||
2684 | |||
2685 | #endif /* ADVANSYS_ASSERT */ | ||
2686 | |||
2687 | /* | ||
2688 | * --- Driver Structures | ||
2689 | */ | ||
2690 | |||
2691 | #ifdef ADVANSYS_STATS | 2659 | #ifdef ADVANSYS_STATS |
2692 | 2660 | ||
2693 | /* Per board statistics structure */ | 2661 | /* Per board statistics structure */ |
@@ -2949,7 +2917,7 @@ advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start, | |||
2949 | if (ASC_WIDE_BOARD(boardp)) { | 2917 | if (ASC_WIDE_BOARD(boardp)) { |
2950 | cp = boardp->prtbuf; | 2918 | cp = boardp->prtbuf; |
2951 | cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE); | 2919 | cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE); |
2952 | ASC_ASSERT(cplen < ASC_PRTBUF_SIZE); | 2920 | BUG_ON(cplen >= ASC_PRTBUF_SIZE); |
2953 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, | 2921 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, |
2954 | cplen); | 2922 | cplen); |
2955 | totcnt += cnt; | 2923 | totcnt += cnt; |
@@ -2967,7 +2935,7 @@ advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start, | |||
2967 | */ | 2935 | */ |
2968 | cp = boardp->prtbuf; | 2936 | cp = boardp->prtbuf; |
2969 | cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE); | 2937 | cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE); |
2970 | ASC_ASSERT(cplen < ASC_PRTBUF_SIZE); | 2938 | BUG_ON(cplen >= ASC_PRTBUF_SIZE); |
2971 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); | 2939 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); |
2972 | totcnt += cnt; | 2940 | totcnt += cnt; |
2973 | leftlen -= cnt; | 2941 | leftlen -= cnt; |
@@ -2987,7 +2955,7 @@ advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start, | |||
2987 | } else { | 2955 | } else { |
2988 | cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE); | 2956 | cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE); |
2989 | } | 2957 | } |
2990 | ASC_ASSERT(cplen < ASC_PRTBUF_SIZE); | 2958 | BUG_ON(cplen >= ASC_PRTBUF_SIZE); |
2991 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); | 2959 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); |
2992 | totcnt += cnt; | 2960 | totcnt += cnt; |
2993 | leftlen -= cnt; | 2961 | leftlen -= cnt; |
@@ -3003,7 +2971,7 @@ advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start, | |||
3003 | */ | 2971 | */ |
3004 | cp = boardp->prtbuf; | 2972 | cp = boardp->prtbuf; |
3005 | cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE); | 2973 | cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE); |
3006 | ASC_ASSERT(cplen < ASC_PRTBUF_SIZE); | 2974 | BUG_ON(cplen >= ASC_PRTBUF_SIZE); |
3007 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); | 2975 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); |
3008 | totcnt += cnt; | 2976 | totcnt += cnt; |
3009 | leftlen -= cnt; | 2977 | leftlen -= cnt; |
@@ -3020,7 +2988,7 @@ advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start, | |||
3020 | */ | 2988 | */ |
3021 | cp = boardp->prtbuf; | 2989 | cp = boardp->prtbuf; |
3022 | cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE); | 2990 | cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE); |
3023 | ASC_ASSERT(cplen <= ASC_PRTBUF_SIZE); | 2991 | BUG_ON(cplen >= ASC_PRTBUF_SIZE); |
3024 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); | 2992 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); |
3025 | totcnt += cnt; | 2993 | totcnt += cnt; |
3026 | leftlen -= cnt; | 2994 | leftlen -= cnt; |
@@ -3042,7 +3010,7 @@ advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start, | |||
3042 | } else { | 3010 | } else { |
3043 | cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE); | 3011 | cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE); |
3044 | } | 3012 | } |
3045 | ASC_ASSERT(cplen < ASC_PRTBUF_SIZE); | 3013 | BUG_ON(cplen >= ASC_PRTBUF_SIZE); |
3046 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); | 3014 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); |
3047 | totcnt += cnt; | 3015 | totcnt += cnt; |
3048 | leftlen -= cnt; | 3016 | leftlen -= cnt; |
@@ -3139,7 +3107,7 @@ static const char *advansys_info(struct Scsi_Host *shost) | |||
3139 | ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base, | 3107 | ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base, |
3140 | (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, shost->irq); | 3108 | (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, shost->irq); |
3141 | } | 3109 | } |
3142 | ASC_ASSERT(strlen(info) < ASC_INFO_SIZE); | 3110 | BUG_ON(strlen(info) >= ASC_INFO_SIZE); |
3143 | ASC_DBG(1, "advansys_info: end\n"); | 3111 | ASC_DBG(1, "advansys_info: end\n"); |
3144 | return info; | 3112 | return info; |
3145 | } | 3113 | } |
@@ -4201,7 +4169,6 @@ adv_get_sglist(asc_board_t *boardp, adv_req_t *reqp, struct scsi_cmnd *scp, | |||
4201 | * Point the previous ADV_SG_BLOCK structure to | 4169 | * Point the previous ADV_SG_BLOCK structure to |
4202 | * the newly allocated ADV_SG_BLOCK structure. | 4170 | * the newly allocated ADV_SG_BLOCK structure. |
4203 | */ | 4171 | */ |
4204 | ASC_ASSERT(prev_sg_block != NULL); | ||
4205 | prev_sg_block->sg_ptr = | 4172 | prev_sg_block->sg_ptr = |
4206 | cpu_to_le32(sg_block_paddr); | 4173 | cpu_to_le32(sg_block_paddr); |
4207 | } | 4174 | } |
@@ -4262,7 +4229,7 @@ static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep) | |||
4262 | ASC_DBG1(1, "asc_isr_callback: shost 0x%lx\n", (ulong)shost); | 4229 | ASC_DBG1(1, "asc_isr_callback: shost 0x%lx\n", (ulong)shost); |
4263 | 4230 | ||
4264 | boardp = ASC_BOARDP(shost); | 4231 | boardp = ASC_BOARDP(shost); |
4265 | ASC_ASSERT(asc_dvc_varp == &boardp->dvc_var.asc_dvc_var); | 4232 | BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var); |
4266 | 4233 | ||
4267 | /* | 4234 | /* |
4268 | * 'qdonep' contains the command's ending status. | 4235 | * 'qdonep' contains the command's ending status. |
@@ -4408,7 +4375,7 @@ static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp) | |||
4408 | ASC_DBG1(1, "adv_isr_callback: shost 0x%lx\n", (ulong)shost); | 4375 | ASC_DBG1(1, "adv_isr_callback: shost 0x%lx\n", (ulong)shost); |
4409 | 4376 | ||
4410 | boardp = ASC_BOARDP(shost); | 4377 | boardp = ASC_BOARDP(shost); |
4411 | ASC_ASSERT(adv_dvc_varp == &boardp->dvc_var.adv_dvc_var); | 4378 | BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var); |
4412 | 4379 | ||
4413 | /* | 4380 | /* |
4414 | * 'done_status' contains the command's ending status. | 4381 | * 'done_status' contains the command's ending status. |
@@ -5738,7 +5705,7 @@ static int asc_prt_line(char *buf, int buflen, char *fmt, ...) | |||
5738 | 5705 | ||
5739 | va_start(args, fmt); | 5706 | va_start(args, fmt); |
5740 | ret = vsprintf(s, fmt, args); | 5707 | ret = vsprintf(s, fmt, args); |
5741 | ASC_ASSERT(ret < ASC_PRTLINE_SIZE); | 5708 | BUG_ON(ret >= ASC_PRTLINE_SIZE); |
5742 | if (buf == NULL) { | 5709 | if (buf == NULL) { |
5743 | (void)printk(s); | 5710 | (void)printk(s); |
5744 | ret = 0; | 5711 | ret = 0; |
@@ -5756,36 +5723,6 @@ static int asc_prt_line(char *buf, int buflen, char *fmt, ...) | |||
5756 | */ | 5723 | */ |
5757 | 5724 | ||
5758 | /* | 5725 | /* |
5759 | * Delay for 'n' milliseconds. Don't use the 'jiffies' | ||
5760 | * global variable which is incremented once every 5 ms | ||
5761 | * from a timer interrupt, because this function may be | ||
5762 | * called when interrupts are disabled. | ||
5763 | */ | ||
5764 | static void DvcSleepMilliSecond(ADV_DCNT n) | ||
5765 | { | ||
5766 | ASC_DBG1(4, "DvcSleepMilliSecond: %lu\n", (ulong)n); | ||
5767 | mdelay(n); | ||
5768 | } | ||
5769 | |||
5770 | /* | ||
5771 | * Currently and inline noop but leave as a placeholder. | ||
5772 | * Leave DvcEnterCritical() as a noop placeholder. | ||
5773 | */ | ||
5774 | static inline ulong DvcEnterCritical(void) | ||
5775 | { | ||
5776 | return 0; | ||
5777 | } | ||
5778 | |||
5779 | /* | ||
5780 | * Critical sections are all protected by the board spinlock. | ||
5781 | * Leave DvcLeaveCritical() as a noop placeholder. | ||
5782 | */ | ||
5783 | static inline void DvcLeaveCritical(ulong flags) | ||
5784 | { | ||
5785 | return; | ||
5786 | } | ||
5787 | |||
5788 | /* | ||
5789 | * void | 5726 | * void |
5790 | * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words) | 5727 | * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words) |
5791 | * | 5728 | * |
@@ -6317,10 +6254,9 @@ static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b) | |||
6317 | (ulong)b, sgblockno); | 6254 | (ulong)b, sgblockno); |
6318 | printk(" sg_cnt %u, sg_ptr 0x%lx\n", | 6255 | printk(" sg_cnt %u, sg_ptr 0x%lx\n", |
6319 | b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr)); | 6256 | b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr)); |
6320 | ASC_ASSERT(b->sg_cnt <= NO_OF_SG_PER_BLOCK); | 6257 | BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK); |
6321 | if (b->sg_ptr != 0) { | 6258 | if (b->sg_ptr != 0) |
6322 | ASC_ASSERT(b->sg_cnt == NO_OF_SG_PER_BLOCK); | 6259 | BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK); |
6323 | } | ||
6324 | for (i = 0; i < b->sg_cnt; i++) { | 6260 | for (i = 0; i < b->sg_cnt; i++) { |
6325 | printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n", | 6261 | printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n", |
6326 | i, (ulong)b->sg_list[i].sg_addr, | 6262 | i, (ulong)b->sg_list[i].sg_addr, |
@@ -6590,7 +6526,7 @@ static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc) | |||
6590 | uchar scsi_status; | 6526 | uchar scsi_status; |
6591 | asc_board_t *boardp; | 6527 | asc_board_t *boardp; |
6592 | 6528 | ||
6593 | ASC_ASSERT(asc_dvc->drv_ptr != NULL); | 6529 | BUG_ON(!asc_dvc->drv_ptr); |
6594 | boardp = asc_dvc->drv_ptr; | 6530 | boardp = asc_dvc->drv_ptr; |
6595 | 6531 | ||
6596 | iop_base = asc_dvc->iop_base; | 6532 | iop_base = asc_dvc->iop_base; |
@@ -7199,7 +7135,7 @@ static int AscIsrQDone(ASC_DVC_VAR *asc_dvc) | |||
7199 | AscSetChipControl(iop_base, | 7135 | AscSetChipControl(iop_base, |
7200 | (uchar)(CC_SCSI_RESET | 7136 | (uchar)(CC_SCSI_RESET |
7201 | | CC_HALT)); | 7137 | | CC_HALT)); |
7202 | DvcDelayNanoSecond(asc_dvc, 60000); | 7138 | udelay(60); |
7203 | AscSetChipControl(iop_base, CC_HALT); | 7139 | AscSetChipControl(iop_base, CC_HALT); |
7204 | AscSetChipStatus(iop_base, | 7140 | AscSetChipStatus(iop_base, |
7205 | CIW_CLR_SCSI_RESET_INT); | 7141 | CIW_CLR_SCSI_RESET_INT); |
@@ -7276,7 +7212,7 @@ static int AscISR(ASC_DVC_VAR *asc_dvc) | |||
7276 | saved_ctrl_reg &= (uchar)(~CC_HALT); | 7212 | saved_ctrl_reg &= (uchar)(~CC_HALT); |
7277 | while ((AscGetChipStatus(iop_base) & | 7213 | while ((AscGetChipStatus(iop_base) & |
7278 | CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) { | 7214 | CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) { |
7279 | DvcSleepMilliSecond(100); | 7215 | mdelay(100); |
7280 | } | 7216 | } |
7281 | AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT)); | 7217 | AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT)); |
7282 | AscSetChipControl(iop_base, CC_HALT); | 7218 | AscSetChipControl(iop_base, CC_HALT); |
@@ -7549,7 +7485,6 @@ static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = { | |||
7549 | static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) | 7485 | static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) |
7550 | { | 7486 | { |
7551 | PortAddr iop_base; | 7487 | PortAddr iop_base; |
7552 | ulong last_int_level; | ||
7553 | int sta; | 7488 | int sta; |
7554 | int n_q_required; | 7489 | int n_q_required; |
7555 | int disable_syn_offset_one_fix; | 7490 | int disable_syn_offset_one_fix; |
@@ -7593,9 +7528,7 @@ static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) | |||
7593 | scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT); | 7528 | scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT); |
7594 | } | 7529 | } |
7595 | } | 7530 | } |
7596 | last_int_level = DvcEnterCritical(); | ||
7597 | if (asc_dvc->in_critical_cnt != 0) { | 7531 | if (asc_dvc->in_critical_cnt != 0) { |
7598 | DvcLeaveCritical(last_int_level); | ||
7599 | AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY); | 7532 | AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY); |
7600 | return (ERR); | 7533 | return (ERR); |
7601 | } | 7534 | } |
@@ -7603,13 +7536,11 @@ static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) | |||
7603 | if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) { | 7536 | if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) { |
7604 | if ((sg_entry_cnt = sg_head->entry_cnt) == 0) { | 7537 | if ((sg_entry_cnt = sg_head->entry_cnt) == 0) { |
7605 | asc_dvc->in_critical_cnt--; | 7538 | asc_dvc->in_critical_cnt--; |
7606 | DvcLeaveCritical(last_int_level); | ||
7607 | return (ERR); | 7539 | return (ERR); |
7608 | } | 7540 | } |
7609 | #if !CC_VERY_LONG_SG_LIST | 7541 | #if !CC_VERY_LONG_SG_LIST |
7610 | if (sg_entry_cnt > ASC_MAX_SG_LIST) { | 7542 | if (sg_entry_cnt > ASC_MAX_SG_LIST) { |
7611 | asc_dvc->in_critical_cnt--; | 7543 | asc_dvc->in_critical_cnt--; |
7612 | DvcLeaveCritical(last_int_level); | ||
7613 | return (ERR); | 7544 | return (ERR); |
7614 | } | 7545 | } |
7615 | #endif /* !CC_VERY_LONG_SG_LIST */ | 7546 | #endif /* !CC_VERY_LONG_SG_LIST */ |
@@ -7724,7 +7655,6 @@ static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) | |||
7724 | AscSendScsiQueue(asc_dvc, scsiq, | 7655 | AscSendScsiQueue(asc_dvc, scsiq, |
7725 | n_q_required)) == 1) { | 7656 | n_q_required)) == 1) { |
7726 | asc_dvc->in_critical_cnt--; | 7657 | asc_dvc->in_critical_cnt--; |
7727 | DvcLeaveCritical(last_int_level); | ||
7728 | return (sta); | 7658 | return (sta); |
7729 | } | 7659 | } |
7730 | } | 7660 | } |
@@ -7769,13 +7699,11 @@ static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) | |||
7769 | if ((sta = AscSendScsiQueue(asc_dvc, scsiq, | 7699 | if ((sta = AscSendScsiQueue(asc_dvc, scsiq, |
7770 | n_q_required)) == 1) { | 7700 | n_q_required)) == 1) { |
7771 | asc_dvc->in_critical_cnt--; | 7701 | asc_dvc->in_critical_cnt--; |
7772 | DvcLeaveCritical(last_int_level); | ||
7773 | return (sta); | 7702 | return (sta); |
7774 | } | 7703 | } |
7775 | } | 7704 | } |
7776 | } | 7705 | } |
7777 | asc_dvc->in_critical_cnt--; | 7706 | asc_dvc->in_critical_cnt--; |
7778 | DvcLeaveCritical(last_int_level); | ||
7779 | return (sta); | 7707 | return (sta); |
7780 | } | 7708 | } |
7781 | 7709 | ||
@@ -8308,7 +8236,7 @@ static int AscHostReqRiscHalt(PortAddr iop_base) | |||
8308 | sta = 1; | 8236 | sta = 1; |
8309 | break; | 8237 | break; |
8310 | } | 8238 | } |
8311 | DvcSleepMilliSecond(100); | 8239 | mdelay(100); |
8312 | } while (count++ < 20); | 8240 | } while (count++ < 20); |
8313 | AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code); | 8241 | AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code); |
8314 | return (sta); | 8242 | return (sta); |
@@ -8326,22 +8254,12 @@ static int AscStopQueueExe(PortAddr iop_base) | |||
8326 | ASC_STOP_ACK_RISC_STOP) { | 8254 | ASC_STOP_ACK_RISC_STOP) { |
8327 | return (1); | 8255 | return (1); |
8328 | } | 8256 | } |
8329 | DvcSleepMilliSecond(100); | 8257 | mdelay(100); |
8330 | } while (count++ < 20); | 8258 | } while (count++ < 20); |
8331 | } | 8259 | } |
8332 | return (0); | 8260 | return (0); |
8333 | } | 8261 | } |
8334 | 8262 | ||
8335 | static void DvcDelayMicroSecond(ADV_DVC_VAR *asc_dvc, ushort micro_sec) | ||
8336 | { | ||
8337 | udelay(micro_sec); | ||
8338 | } | ||
8339 | |||
8340 | static void DvcDelayNanoSecond(ASC_DVC_VAR *asc_dvc, ASC_DCNT nano_sec) | ||
8341 | { | ||
8342 | udelay((nano_sec + 999) / 1000); | ||
8343 | } | ||
8344 | |||
8345 | static int AscStartChip(PortAddr iop_base) | 8263 | static int AscStartChip(PortAddr iop_base) |
8346 | { | 8264 | { |
8347 | AscSetChipControl(iop_base, 0); | 8265 | AscSetChipControl(iop_base, 0); |
@@ -8460,16 +8378,16 @@ static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc) | |||
8460 | iop_base = asc_dvc->iop_base; | 8378 | iop_base = asc_dvc->iop_base; |
8461 | while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) | 8379 | while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) |
8462 | && (i-- > 0)) { | 8380 | && (i-- > 0)) { |
8463 | DvcSleepMilliSecond(100); | 8381 | mdelay(100); |
8464 | } | 8382 | } |
8465 | AscStopChip(iop_base); | 8383 | AscStopChip(iop_base); |
8466 | AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT); | 8384 | AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT); |
8467 | DvcDelayNanoSecond(asc_dvc, 60000); | 8385 | udelay(60); |
8468 | AscSetChipIH(iop_base, INS_RFLAG_WTM); | 8386 | AscSetChipIH(iop_base, INS_RFLAG_WTM); |
8469 | AscSetChipIH(iop_base, INS_HALT); | 8387 | AscSetChipIH(iop_base, INS_HALT); |
8470 | AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT); | 8388 | AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT); |
8471 | AscSetChipControl(iop_base, CC_HALT); | 8389 | AscSetChipControl(iop_base, CC_HALT); |
8472 | DvcSleepMilliSecond(200); | 8390 | mdelay(200); |
8473 | AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT); | 8391 | AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT); |
8474 | AscSetChipStatus(iop_base, 0); | 8392 | AscSetChipStatus(iop_base, 0); |
8475 | return (AscIsChipHalted(iop_base)); | 8393 | return (AscIsChipHalted(iop_base)); |
@@ -8711,8 +8629,7 @@ static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc) | |||
8711 | if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) && | 8629 | if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) && |
8712 | !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) { | 8630 | !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) { |
8713 | AscResetChipAndScsiBus(asc_dvc); | 8631 | AscResetChipAndScsiBus(asc_dvc); |
8714 | DvcSleepMilliSecond((ASC_DCNT) | 8632 | mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */ |
8715 | ((ushort)asc_dvc->scsi_reset_wait * 1000)); | ||
8716 | } | 8633 | } |
8717 | asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC; | 8634 | asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC; |
8718 | if (asc_dvc->err_code != 0) | 8635 | if (asc_dvc->err_code != 0) |
@@ -8869,8 +8786,7 @@ static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc) | |||
8869 | (AscGetChipScsiCtrl(iop_base) != 0)) { | 8786 | (AscGetChipScsiCtrl(iop_base) != 0)) { |
8870 | asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE; | 8787 | asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE; |
8871 | AscResetChipAndScsiBus(asc_dvc); | 8788 | AscResetChipAndScsiBus(asc_dvc); |
8872 | DvcSleepMilliSecond((ASC_DCNT) | 8789 | mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */ |
8873 | ((ushort)asc_dvc->scsi_reset_wait * 1000)); | ||
8874 | } | 8790 | } |
8875 | if (AscIsChipHalted(iop_base) == FALSE) { | 8791 | if (AscIsChipHalted(iop_base) == FALSE) { |
8876 | asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP; | 8792 | asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP; |
@@ -9084,7 +9000,7 @@ static int __devinit AscTestExternalLram(ASC_DVC_VAR *asc_dvc) | |||
9084 | saved_word = AscReadLramWord(iop_base, q_addr); | 9000 | saved_word = AscReadLramWord(iop_base, q_addr); |
9085 | AscSetChipLramAddr(iop_base, q_addr); | 9001 | AscSetChipLramAddr(iop_base, q_addr); |
9086 | AscSetChipLramData(iop_base, 0x55AA); | 9002 | AscSetChipLramData(iop_base, 0x55AA); |
9087 | DvcSleepMilliSecond(10); | 9003 | mdelay(10); |
9088 | AscSetChipLramAddr(iop_base, q_addr); | 9004 | AscSetChipLramAddr(iop_base, q_addr); |
9089 | if (AscGetChipLramData(iop_base) == 0x55AA) { | 9005 | if (AscGetChipLramData(iop_base) == 0x55AA) { |
9090 | sta = 1; | 9006 | sta = 1; |
@@ -9101,7 +9017,7 @@ static int __devinit AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg) | |||
9101 | retry = 0; | 9017 | retry = 0; |
9102 | while (TRUE) { | 9018 | while (TRUE) { |
9103 | AscSetChipEEPCmd(iop_base, cmd_reg); | 9019 | AscSetChipEEPCmd(iop_base, cmd_reg); |
9104 | DvcSleepMilliSecond(1); | 9020 | mdelay(1); |
9105 | read_back = AscGetChipEEPCmd(iop_base); | 9021 | read_back = AscGetChipEEPCmd(iop_base); |
9106 | if (read_back == cmd_reg) { | 9022 | if (read_back == cmd_reg) { |
9107 | return (1); | 9023 | return (1); |
@@ -9120,7 +9036,7 @@ static int __devinit AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg) | |||
9120 | retry = 0; | 9036 | retry = 0; |
9121 | while (TRUE) { | 9037 | while (TRUE) { |
9122 | AscSetChipEEPData(iop_base, data_reg); | 9038 | AscSetChipEEPData(iop_base, data_reg); |
9123 | DvcSleepMilliSecond(1); | 9039 | mdelay(1); |
9124 | read_back = AscGetChipEEPData(iop_base); | 9040 | read_back = AscGetChipEEPData(iop_base); |
9125 | if (read_back == data_reg) { | 9041 | if (read_back == data_reg) { |
9126 | return (1); | 9042 | return (1); |
@@ -9133,13 +9049,13 @@ static int __devinit AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg) | |||
9133 | 9049 | ||
9134 | static void __devinit AscWaitEEPRead(void) | 9050 | static void __devinit AscWaitEEPRead(void) |
9135 | { | 9051 | { |
9136 | DvcSleepMilliSecond(1); | 9052 | mdelay(1); |
9137 | return; | 9053 | return; |
9138 | } | 9054 | } |
9139 | 9055 | ||
9140 | static void __devinit AscWaitEEPWrite(void) | 9056 | static void __devinit AscWaitEEPWrite(void) |
9141 | { | 9057 | { |
9142 | DvcSleepMilliSecond(20); | 9058 | mdelay(20); |
9143 | return; | 9059 | return; |
9144 | } | 9060 | } |
9145 | 9061 | ||
@@ -11364,7 +11280,7 @@ AdvInitGetConfig(struct pci_dev *pdev, asc_board_t *boardp) | |||
11364 | */ | 11280 | */ |
11365 | AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, | 11281 | AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, |
11366 | ADV_CTRL_REG_CMD_RESET); | 11282 | ADV_CTRL_REG_CMD_RESET); |
11367 | DvcSleepMilliSecond(100); | 11283 | mdelay(100); |
11368 | AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, | 11284 | AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, |
11369 | ADV_CTRL_REG_CMD_WR_IO_REG); | 11285 | ADV_CTRL_REG_CMD_WR_IO_REG); |
11370 | 11286 | ||
@@ -12048,7 +11964,7 @@ static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc) | |||
12048 | */ | 11964 | */ |
12049 | for (i = 0; i < 2; i++) { | 11965 | for (i = 0; i < 2; i++) { |
12050 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE); | 11966 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE); |
12051 | DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */ | 11967 | mdelay(10); /* Wait for 10ms before reading back. */ |
12052 | byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); | 11968 | byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); |
12053 | if ((byte & RAM_TEST_DONE) == 0 | 11969 | if ((byte & RAM_TEST_DONE) == 0 |
12054 | || (byte & 0x0F) != PRE_TEST_VALUE) { | 11970 | || (byte & 0x0F) != PRE_TEST_VALUE) { |
@@ -12057,7 +11973,7 @@ static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc) | |||
12057 | } | 11973 | } |
12058 | 11974 | ||
12059 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); | 11975 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); |
12060 | DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */ | 11976 | mdelay(10); /* Wait for 10ms before reading back. */ |
12061 | if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST) | 11977 | if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST) |
12062 | != NORMAL_VALUE) { | 11978 | != NORMAL_VALUE) { |
12063 | asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; | 11979 | asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; |
@@ -12073,7 +11989,7 @@ static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc) | |||
12073 | * err_code, and return an error. | 11989 | * err_code, and return an error. |
12074 | */ | 11990 | */ |
12075 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE); | 11991 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE); |
12076 | DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */ | 11992 | mdelay(10); /* Wait for 10ms before checking status. */ |
12077 | 11993 | ||
12078 | byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); | 11994 | byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); |
12079 | if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { | 11995 | if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { |
@@ -12529,7 +12445,7 @@ static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc) | |||
12529 | */ | 12445 | */ |
12530 | for (i = 0; i < 2; i++) { | 12446 | for (i = 0; i < 2; i++) { |
12531 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE); | 12447 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE); |
12532 | DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */ | 12448 | mdelay(10); /* Wait for 10ms before reading back. */ |
12533 | byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); | 12449 | byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); |
12534 | if ((byte & RAM_TEST_DONE) == 0 | 12450 | if ((byte & RAM_TEST_DONE) == 0 |
12535 | || (byte & 0x0F) != PRE_TEST_VALUE) { | 12451 | || (byte & 0x0F) != PRE_TEST_VALUE) { |
@@ -12538,7 +12454,7 @@ static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc) | |||
12538 | } | 12454 | } |
12539 | 12455 | ||
12540 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); | 12456 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); |
12541 | DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */ | 12457 | mdelay(10); /* Wait for 10ms before reading back. */ |
12542 | if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST) | 12458 | if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST) |
12543 | != NORMAL_VALUE) { | 12459 | != NORMAL_VALUE) { |
12544 | asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; | 12460 | asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; |
@@ -12554,7 +12470,7 @@ static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc) | |||
12554 | * err_code, and return an error. | 12470 | * err_code, and return an error. |
12555 | */ | 12471 | */ |
12556 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE); | 12472 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE); |
12557 | DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */ | 12473 | mdelay(10); /* Wait for 10ms before checking status. */ |
12558 | 12474 | ||
12559 | byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); | 12475 | byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); |
12560 | if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { | 12476 | if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { |
@@ -13645,12 +13561,11 @@ static void __devinit AdvWaitEEPCmd(AdvPortAddr iop_base) | |||
13645 | ASC_EEP_CMD_DONE) { | 13561 | ASC_EEP_CMD_DONE) { |
13646 | break; | 13562 | break; |
13647 | } | 13563 | } |
13648 | DvcSleepMilliSecond(1); | 13564 | mdelay(1); |
13649 | } | 13565 | } |
13650 | if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) == | 13566 | if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) == |
13651 | 0) { | 13567 | 0) |
13652 | ASC_ASSERT(0); | 13568 | BUG(); |
13653 | } | ||
13654 | return; | 13569 | return; |
13655 | } | 13570 | } |
13656 | 13571 | ||
@@ -13688,7 +13603,7 @@ AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf) | |||
13688 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, | 13603 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, |
13689 | ASC_EEP_CMD_WRITE | addr); | 13604 | ASC_EEP_CMD_WRITE | addr); |
13690 | AdvWaitEEPCmd(iop_base); | 13605 | AdvWaitEEPCmd(iop_base); |
13691 | DvcSleepMilliSecond(ADV_EEP_DELAY_MS); | 13606 | mdelay(ADV_EEP_DELAY_MS); |
13692 | } | 13607 | } |
13693 | 13608 | ||
13694 | /* | 13609 | /* |
@@ -13756,7 +13671,7 @@ AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf) | |||
13756 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, | 13671 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, |
13757 | ASC_EEP_CMD_WRITE | addr); | 13672 | ASC_EEP_CMD_WRITE | addr); |
13758 | AdvWaitEEPCmd(iop_base); | 13673 | AdvWaitEEPCmd(iop_base); |
13759 | DvcSleepMilliSecond(ADV_EEP_DELAY_MS); | 13674 | mdelay(ADV_EEP_DELAY_MS); |
13760 | } | 13675 | } |
13761 | 13676 | ||
13762 | /* | 13677 | /* |
@@ -13824,7 +13739,7 @@ AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf) | |||
13824 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, | 13739 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, |
13825 | ASC_EEP_CMD_WRITE | addr); | 13740 | ASC_EEP_CMD_WRITE | addr); |
13826 | AdvWaitEEPCmd(iop_base); | 13741 | AdvWaitEEPCmd(iop_base); |
13827 | DvcSleepMilliSecond(ADV_EEP_DELAY_MS); | 13742 | mdelay(ADV_EEP_DELAY_MS); |
13828 | } | 13743 | } |
13829 | 13744 | ||
13830 | /* | 13745 | /* |
@@ -13882,14 +13797,11 @@ AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf) | |||
13882 | */ | 13797 | */ |
13883 | static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq) | 13798 | static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq) |
13884 | { | 13799 | { |
13885 | ulong last_int_level; | ||
13886 | AdvPortAddr iop_base; | 13800 | AdvPortAddr iop_base; |
13887 | ADV_DCNT req_size; | 13801 | ADV_DCNT req_size; |
13888 | ADV_PADDR req_paddr; | 13802 | ADV_PADDR req_paddr; |
13889 | ADV_CARR_T *new_carrp; | 13803 | ADV_CARR_T *new_carrp; |
13890 | 13804 | ||
13891 | ASC_ASSERT(scsiq != NULL); /* 'scsiq' should never be NULL. */ | ||
13892 | |||
13893 | /* | 13805 | /* |
13894 | * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID. | 13806 | * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID. |
13895 | */ | 13807 | */ |
@@ -13901,14 +13813,11 @@ static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq) | |||
13901 | 13813 | ||
13902 | iop_base = asc_dvc->iop_base; | 13814 | iop_base = asc_dvc->iop_base; |
13903 | 13815 | ||
13904 | last_int_level = DvcEnterCritical(); | ||
13905 | |||
13906 | /* | 13816 | /* |
13907 | * Allocate a carrier ensuring at least one carrier always | 13817 | * Allocate a carrier ensuring at least one carrier always |
13908 | * remains on the freelist and initialize fields. | 13818 | * remains on the freelist and initialize fields. |
13909 | */ | 13819 | */ |
13910 | if ((new_carrp = asc_dvc->carr_freelist) == NULL) { | 13820 | if ((new_carrp = asc_dvc->carr_freelist) == NULL) { |
13911 | DvcLeaveCritical(last_int_level); | ||
13912 | return ADV_BUSY; | 13821 | return ADV_BUSY; |
13913 | } | 13822 | } |
13914 | asc_dvc->carr_freelist = (ADV_CARR_T *) | 13823 | asc_dvc->carr_freelist = (ADV_CARR_T *) |
@@ -13931,8 +13840,8 @@ static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq) | |||
13931 | req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *)scsiq, | 13840 | req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *)scsiq, |
13932 | (ADV_SDCNT *)&req_size, ADV_IS_SCSIQ_FLAG); | 13841 | (ADV_SDCNT *)&req_size, ADV_IS_SCSIQ_FLAG); |
13933 | 13842 | ||
13934 | ASC_ASSERT(ADV_32BALIGN(req_paddr) == req_paddr); | 13843 | BUG_ON(req_paddr & 31); |
13935 | ASC_ASSERT(req_size >= sizeof(ADV_SCSI_REQ_Q)); | 13844 | BUG_ON(req_size < sizeof(ADV_SCSI_REQ_Q)); |
13936 | 13845 | ||
13937 | /* Wait for assertion before making little-endian */ | 13846 | /* Wait for assertion before making little-endian */ |
13938 | req_paddr = cpu_to_le32(req_paddr); | 13847 | req_paddr = cpu_to_le32(req_paddr); |
@@ -13991,8 +13900,6 @@ static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq) | |||
13991 | le32_to_cpu(new_carrp->carr_pa)); | 13900 | le32_to_cpu(new_carrp->carr_pa)); |
13992 | } | 13901 | } |
13993 | 13902 | ||
13994 | DvcLeaveCritical(last_int_level); | ||
13995 | |||
13996 | return ADV_SUCCESS; | 13903 | return ADV_SUCCESS; |
13997 | } | 13904 | } |
13998 | 13905 | ||
@@ -14024,7 +13931,7 @@ static int AdvResetSB(ADV_DVC_VAR *asc_dvc) | |||
14024 | * The hold time delay is done on the host because the RISC has no | 13931 | * The hold time delay is done on the host because the RISC has no |
14025 | * microsecond accurate timer. | 13932 | * microsecond accurate timer. |
14026 | */ | 13933 | */ |
14027 | DvcDelayMicroSecond(asc_dvc, (ushort)ASC_SCSI_RESET_HOLD_TIME_US); | 13934 | udelay(ASC_SCSI_RESET_HOLD_TIME_US); |
14028 | 13935 | ||
14029 | /* | 13936 | /* |
14030 | * Send the SCSI Bus Reset end idle command which de-asserts | 13937 | * Send the SCSI Bus Reset end idle command which de-asserts |
@@ -14035,7 +13942,7 @@ static int AdvResetSB(ADV_DVC_VAR *asc_dvc) | |||
14035 | return status; | 13942 | return status; |
14036 | } | 13943 | } |
14037 | 13944 | ||
14038 | DvcSleepMilliSecond((ADV_DCNT)asc_dvc->scsi_reset_wait * 1000); | 13945 | mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */ |
14039 | 13946 | ||
14040 | return status; | 13947 | return status; |
14041 | } | 13948 | } |
@@ -14086,7 +13993,7 @@ static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc) | |||
14086 | */ | 13993 | */ |
14087 | AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP); | 13994 | AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP); |
14088 | AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET); | 13995 | AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET); |
14089 | DvcSleepMilliSecond(100); | 13996 | mdelay(100); |
14090 | AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, | 13997 | AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, |
14091 | ADV_CTRL_REG_CMD_WR_IO_REG); | 13998 | ADV_CTRL_REG_CMD_WR_IO_REG); |
14092 | 13999 | ||
@@ -14158,11 +14065,8 @@ static int AdvISR(ADV_DVC_VAR *asc_dvc) | |||
14158 | ushort target_bit; | 14065 | ushort target_bit; |
14159 | ADV_CARR_T *free_carrp; | 14066 | ADV_CARR_T *free_carrp; |
14160 | ADV_VADDR irq_next_vpa; | 14067 | ADV_VADDR irq_next_vpa; |
14161 | int flags; | ||
14162 | ADV_SCSI_REQ_Q *scsiq; | 14068 | ADV_SCSI_REQ_Q *scsiq; |
14163 | 14069 | ||
14164 | flags = DvcEnterCritical(); | ||
14165 | |||
14166 | iop_base = asc_dvc->iop_base; | 14070 | iop_base = asc_dvc->iop_base; |
14167 | 14071 | ||
14168 | /* Reading the register clears the interrupt. */ | 14072 | /* Reading the register clears the interrupt. */ |
@@ -14170,7 +14074,6 @@ static int AdvISR(ADV_DVC_VAR *asc_dvc) | |||
14170 | 14074 | ||
14171 | if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB | | 14075 | if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB | |
14172 | ADV_INTR_STATUS_INTRC)) == 0) { | 14076 | ADV_INTR_STATUS_INTRC)) == 0) { |
14173 | DvcLeaveCritical(flags); | ||
14174 | return ADV_FALSE; | 14077 | return ADV_FALSE; |
14175 | } | 14078 | } |
14176 | 14079 | ||
@@ -14243,7 +14146,6 @@ static int AdvISR(ADV_DVC_VAR *asc_dvc) | |||
14243 | asc_dvc->carr_freelist = free_carrp; | 14146 | asc_dvc->carr_freelist = free_carrp; |
14244 | asc_dvc->carr_pending_cnt--; | 14147 | asc_dvc->carr_pending_cnt--; |
14245 | 14148 | ||
14246 | ASC_ASSERT(scsiq != NULL); | ||
14247 | target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id); | 14149 | target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id); |
14248 | 14150 | ||
14249 | /* | 14151 | /* |
@@ -14264,18 +14166,7 @@ static int AdvISR(ADV_DVC_VAR *asc_dvc) | |||
14264 | * Fall through and continue processing other completed | 14166 | * Fall through and continue processing other completed |
14265 | * requests... | 14167 | * requests... |
14266 | */ | 14168 | */ |
14267 | |||
14268 | /* | ||
14269 | * Disable interrupts again in case the driver inadvertently | ||
14270 | * enabled interrupts in its callback function. | ||
14271 | * | ||
14272 | * The DvcEnterCritical() return value is ignored, because | ||
14273 | * the 'flags' saved when AdvISR() was first entered will be | ||
14274 | * used to restore the interrupt flag on exit. | ||
14275 | */ | ||
14276 | (void)DvcEnterCritical(); | ||
14277 | } | 14169 | } |
14278 | DvcLeaveCritical(flags); | ||
14279 | return ADV_TRUE; | 14170 | return ADV_TRUE; |
14280 | } | 14171 | } |
14281 | 14172 | ||
@@ -14297,13 +14188,10 @@ static int | |||
14297 | AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc, | 14188 | AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc, |
14298 | ushort idle_cmd, ADV_DCNT idle_cmd_parameter) | 14189 | ushort idle_cmd, ADV_DCNT idle_cmd_parameter) |
14299 | { | 14190 | { |
14300 | ulong last_int_level; | ||
14301 | int result; | 14191 | int result; |
14302 | ADV_DCNT i, j; | 14192 | ADV_DCNT i, j; |
14303 | AdvPortAddr iop_base; | 14193 | AdvPortAddr iop_base; |
14304 | 14194 | ||
14305 | last_int_level = DvcEnterCritical(); | ||
14306 | |||
14307 | iop_base = asc_dvc->iop_base; | 14195 | iop_base = asc_dvc->iop_base; |
14308 | 14196 | ||
14309 | /* | 14197 | /* |
@@ -14343,16 +14231,13 @@ AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc, | |||
14343 | for (j = 0; j < SCSI_US_PER_MSEC; j++) { | 14231 | for (j = 0; j < SCSI_US_PER_MSEC; j++) { |
14344 | AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, | 14232 | AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, |
14345 | result); | 14233 | result); |
14346 | if (result != 0) { | 14234 | if (result != 0) |
14347 | DvcLeaveCritical(last_int_level); | ||
14348 | return result; | 14235 | return result; |
14349 | } | 14236 | udelay(1); |
14350 | DvcDelayMicroSecond(asc_dvc, (ushort)1); | ||
14351 | } | 14237 | } |
14352 | } | 14238 | } |
14353 | 14239 | ||
14354 | ASC_ASSERT(0); /* The idle command should never timeout. */ | 14240 | BUG(); /* The idle command should never timeout. */ |
14355 | DvcLeaveCritical(last_int_level); | ||
14356 | return ADV_ERROR; | 14241 | return ADV_ERROR; |
14357 | } | 14242 | } |
14358 | 14243 | ||