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authorMatthew Wilcox <matthew@wil.cx>2007-10-02 21:55:36 -0400
committerJames Bottomley <jejb@mulgrave.localdomain>2007-10-12 14:53:45 -0400
commitafbb68c35f4bdf0964d88e9e005e6f62ba57d134 (patch)
tree2805842e1971132ee56cc133d0e800a00b414698
parent9d0e96eba19e9973a1c21ddd1fdbc049b231bf3b (diff)
[SCSI] advansys: Make sdtr_period_tbl a pointer
It's somewhat neater to make this a pointer to one of two tables than initialising an array in the driver. Also delete the unused AscSynIndexToPeriod and rename host_init_sdtr_index to min_sdtr_index Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
-rw-r--r--drivers/scsi/advansys.c90
1 files changed, 25 insertions, 65 deletions
diff --git a/drivers/scsi/advansys.c b/drivers/scsi/advansys.c
index 93bf3ec514b8..93b1a47ebaf8 100644
--- a/drivers/scsi/advansys.c
+++ b/drivers/scsi/advansys.c
@@ -481,34 +481,22 @@ typedef struct asc_risc_sg_list_q {
481#define ASC_MAX_PCI_INRAM_TOTAL_QNG 20 481#define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
482#define ASC_MAX_INRAM_TAG_QNG 16 482#define ASC_MAX_INRAM_TAG_QNG 16
483#define ASC_IOADR_GAP 0x10 483#define ASC_IOADR_GAP 0x10
484#define ASC_MAX_SYN_XFER_NO 16
485#define ASC_SYN_MAX_OFFSET 0x0F 484#define ASC_SYN_MAX_OFFSET 0x0F
486#define ASC_DEF_SDTR_OFFSET 0x0F 485#define ASC_DEF_SDTR_OFFSET 0x0F
487#define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02 486#define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
488#define SYN_XFER_NS_0 25 487#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
489#define SYN_XFER_NS_1 30 488
490#define SYN_XFER_NS_2 35 489/* The narrow chip only supports a limited selection of transfer rates.
491#define SYN_XFER_NS_3 40 490 * These are encoded in the range 0..7 or 0..15 depending whether the chip
492#define SYN_XFER_NS_4 50 491 * is Ultra-capable or not. These tables let us convert from one to the other.
493#define SYN_XFER_NS_5 60 492 */
494#define SYN_XFER_NS_6 70 493static const unsigned char asc_syn_xfer_period[8] = {
495#define SYN_XFER_NS_7 85 494 25, 30, 35, 40, 50, 60, 70, 85
496#define SYN_ULTRA_XFER_NS_0 12 495};
497#define SYN_ULTRA_XFER_NS_1 19 496
498#define SYN_ULTRA_XFER_NS_2 25 497static const unsigned char asc_syn_ultra_xfer_period[16] = {
499#define SYN_ULTRA_XFER_NS_3 32 498 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
500#define SYN_ULTRA_XFER_NS_4 38 499};
501#define SYN_ULTRA_XFER_NS_5 44
502#define SYN_ULTRA_XFER_NS_6 50
503#define SYN_ULTRA_XFER_NS_7 57
504#define SYN_ULTRA_XFER_NS_8 63
505#define SYN_ULTRA_XFER_NS_9 69
506#define SYN_ULTRA_XFER_NS_10 75
507#define SYN_ULTRA_XFER_NS_11 82
508#define SYN_ULTRA_XFER_NS_12 88
509#define SYN_ULTRA_XFER_NS_13 94
510#define SYN_ULTRA_XFER_NS_14 100
511#define SYN_ULTRA_XFER_NS_15 107
512 500
513typedef struct ext_msg { 501typedef struct ext_msg {
514 uchar msg_type; 502 uchar msg_type;
@@ -572,7 +560,6 @@ typedef struct asc_dvc_cfg {
572#define ASC_INIT_STATE_WITHOUT_EEP 0x8000 560#define ASC_INIT_STATE_WITHOUT_EEP 0x8000
573#define ASC_BUG_FIX_IF_NOT_DWB 0x0001 561#define ASC_BUG_FIX_IF_NOT_DWB 0x0001
574#define ASC_BUG_FIX_ASYN_USE_SYN 0x0002 562#define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
575#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
576#define ASC_MIN_TAGGED_CMD 7 563#define ASC_MIN_TAGGED_CMD 7
577#define ASC_MAX_SCSI_RESET_WAIT 30 564#define ASC_MAX_SCSI_RESET_WAIT 30
578 565
@@ -602,7 +589,7 @@ typedef struct asc_dvc_var {
602 uchar max_dvc_qng[ASC_MAX_TID + 1]; 589 uchar max_dvc_qng[ASC_MAX_TID + 1];
603 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1]; 590 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
604 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1]; 591 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
605 uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO]; 592 const uchar *sdtr_period_tbl;
606 ASC_DVC_CFG *cfg; 593 ASC_DVC_CFG *cfg;
607 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always; 594 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
608 char redo_scam; 595 char redo_scam;
@@ -611,8 +598,8 @@ typedef struct asc_dvc_var {
611 ASC_DCNT max_dma_count; 598 ASC_DCNT max_dma_count;
612 ASC_SCSI_BIT_ID_TYPE no_scam; 599 ASC_SCSI_BIT_ID_TYPE no_scam;
613 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer; 600 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
601 uchar min_sdtr_index;
614 uchar max_sdtr_index; 602 uchar max_sdtr_index;
615 uchar host_init_sdtr_index;
616 struct asc_board *drv_ptr; 603 struct asc_board *drv_ptr;
617 ASC_DCNT uc_break; 604 ASC_DCNT uc_break;
618} ASC_DVC_VAR; 605} ASC_DVC_VAR;
@@ -896,7 +883,6 @@ typedef struct asc_mc_saved {
896#define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id)) 883#define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
897#define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data) 884#define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
898#define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id)) 885#define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
899#define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
900#define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE) 886#define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
901#define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD) 887#define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
902#define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION) 888#define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
@@ -8556,14 +8542,14 @@ static void AscAckInterrupt(PortAddr iop_base)
8556 8542
8557static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time) 8543static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
8558{ 8544{
8559 uchar *period_table; 8545 const uchar *period_table;
8560 int max_index; 8546 int max_index;
8561 int min_index; 8547 int min_index;
8562 int i; 8548 int i;
8563 8549
8564 period_table = asc_dvc->sdtr_period_tbl; 8550 period_table = asc_dvc->sdtr_period_tbl;
8565 max_index = (int)asc_dvc->max_sdtr_index; 8551 max_index = (int)asc_dvc->max_sdtr_index;
8566 min_index = (int)asc_dvc->host_init_sdtr_index; 8552 min_index = (int)asc_dvc->min_sdtr_index;
8567 if ((syn_time <= period_table[max_index])) { 8553 if ((syn_time <= period_table[max_index])) {
8568 for (i = min_index; i < (max_index - 1); i++) { 8554 for (i = min_index; i < (max_index - 1); i++) {
8569 if (syn_time <= period_table[i]) { 8555 if (syn_time <= period_table[i]) {
@@ -8612,9 +8598,8 @@ AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
8612 uchar sdtr_period_ix; 8598 uchar sdtr_period_ix;
8613 8599
8614 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period); 8600 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8615 if (sdtr_period_ix > asc_dvc->max_sdtr_index) { 8601 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
8616 return 0xFF; 8602 return 0xFF;
8617 }
8618 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 8603 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
8619 return byte; 8604 return byte;
8620} 8605}
@@ -8725,15 +8710,14 @@ static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
8725 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 8710 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
8726 } 8711 }
8727 if ((ext_msg.xfer_period < 8712 if ((ext_msg.xfer_period <
8728 asc_dvc->sdtr_period_tbl[asc_dvc-> 8713 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
8729 host_init_sdtr_index])
8730 || (ext_msg.xfer_period > 8714 || (ext_msg.xfer_period >
8731 asc_dvc->sdtr_period_tbl[asc_dvc-> 8715 asc_dvc->sdtr_period_tbl[asc_dvc->
8732 max_sdtr_index])) { 8716 max_sdtr_index])) {
8733 sdtr_accept = FALSE; 8717 sdtr_accept = FALSE;
8734 ext_msg.xfer_period = 8718 ext_msg.xfer_period =
8735 asc_dvc->sdtr_period_tbl[asc_dvc-> 8719 asc_dvc->sdtr_period_tbl[asc_dvc->
8736 host_init_sdtr_index]; 8720 min_sdtr_index];
8737 } 8721 }
8738 if (sdtr_accept) { 8722 if (sdtr_accept) {
8739 sdtr_data = 8723 sdtr_data =
@@ -8757,7 +8741,6 @@ static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
8757 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); 8741 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8758 } else { 8742 } else {
8759 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) { 8743 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
8760
8761 q_cntl &= ~QC_MSG_OUT; 8744 q_cntl &= ~QC_MSG_OUT;
8762 asc_dvc->sdtr_done |= target_id; 8745 asc_dvc->sdtr_done |= target_id;
8763 asc_dvc->init_sdtr |= target_id; 8746 asc_dvc->init_sdtr |= target_id;
@@ -8772,7 +8755,6 @@ static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
8772 tid_no); 8755 tid_no);
8773 boardp->sdtr_data[tid_no] = sdtr_data; 8756 boardp->sdtr_data[tid_no] = sdtr_data;
8774 } else { 8757 } else {
8775
8776 q_cntl |= QC_MSG_OUT; 8758 q_cntl |= QC_MSG_OUT;
8777 AscMsgOutSDTR(asc_dvc, 8759 AscMsgOutSDTR(asc_dvc,
8778 ext_msg.xfer_period, 8760 ext_msg.xfer_period,
@@ -11407,7 +11389,7 @@ static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
11407 asc_dvc->queue_full_or_busy = 0; 11389 asc_dvc->queue_full_or_busy = 0;
11408 asc_dvc->redo_scam = 0; 11390 asc_dvc->redo_scam = 0;
11409 asc_dvc->res2 = 0; 11391 asc_dvc->res2 = 0;
11410 asc_dvc->host_init_sdtr_index = 0; 11392 asc_dvc->min_sdtr_index = 0;
11411 asc_dvc->cfg->can_tagged_qng = 0; 11393 asc_dvc->cfg->can_tagged_qng = 0;
11412 asc_dvc->cfg->cmd_qng_enabled = 0; 11394 asc_dvc->cfg->cmd_qng_enabled = 0;
11413 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL; 11395 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
@@ -11421,34 +11403,12 @@ static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
11421 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 11403 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
11422 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type); 11404 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
11423 asc_dvc->cfg->chip_version = chip_version; 11405 asc_dvc->cfg->chip_version = chip_version;
11424 asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0; 11406 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
11425 asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
11426 asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
11427 asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
11428 asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
11429 asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
11430 asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
11431 asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
11432 asc_dvc->max_sdtr_index = 7; 11407 asc_dvc->max_sdtr_index = 7;
11433 if ((asc_dvc->bus_type & ASC_IS_PCI) && 11408 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
11434 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 11409 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
11435 asc_dvc->bus_type = ASC_IS_PCI_ULTRA; 11410 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
11436 asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0; 11411 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
11437 asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
11438 asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
11439 asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
11440 asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
11441 asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
11442 asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
11443 asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
11444 asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
11445 asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
11446 asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
11447 asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
11448 asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
11449 asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
11450 asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
11451 asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
11452 asc_dvc->max_sdtr_index = 15; 11412 asc_dvc->max_sdtr_index = 15;
11453 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) { 11413 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
11454 AscSetExtraControl(iop_base, 11414 AscSetExtraControl(iop_base,
@@ -11889,7 +11849,7 @@ static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
11889 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config); 11849 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
11890 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 11850 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
11891 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 11851 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
11892 asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 11852 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
11893 } 11853 }
11894 11854
11895 for (i = 0; i <= ASC_MAX_TID; i++) { 11855 for (i = 0; i <= ASC_MAX_TID; i++) {
@@ -11897,7 +11857,7 @@ static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
11897 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng; 11857 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
11898 asc_dvc->cfg->sdtr_period_offset[i] = 11858 asc_dvc->cfg->sdtr_period_offset[i] =
11899 (uchar)(ASC_DEF_SDTR_OFFSET | 11859 (uchar)(ASC_DEF_SDTR_OFFSET |
11900 (asc_dvc->host_init_sdtr_index << 4)); 11860 (asc_dvc->min_sdtr_index << 4));
11901 } 11861 }
11902 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base); 11862 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
11903 if (write_eep) { 11863 if (write_eep) {