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authorStephen Rothwell <sfr@canb.auug.org.au>2007-12-06 02:02:28 -0500
committerPaul Mackerras <paulus@samba.org>2007-12-10 21:42:12 -0500
commit7cd1de6bc1a46867fa5b9405e8ce0cbf9bc4a884 (patch)
treec8f2bd2f58d169c76bd701fff804231dea60c523
parent96188ce57ba2e497dbbac78a137ae5c732db5fed (diff)
[POWERPC] Clean up pci-bridge.h
No semantic changes. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
-rw-r--r--include/asm-powerpc/pci-bridge.h95
1 files changed, 42 insertions, 53 deletions
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index d8bdc79db12e..e0213149fb11 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -1,16 +1,17 @@
1#ifndef _ASM_POWERPC_PCI_BRIDGE_H 1#ifndef _ASM_POWERPC_PCI_BRIDGE_H
2#define _ASM_POWERPC_PCI_BRIDGE_H 2#define _ASM_POWERPC_PCI_BRIDGE_H
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
5#include <linux/pci.h> 10#include <linux/pci.h>
6#include <linux/list.h> 11#include <linux/list.h>
7#include <linux/ioport.h> 12#include <linux/ioport.h>
8 13
9#ifndef CONFIG_PPC64 14#ifndef CONFIG_PPC64
10
11struct device_node;
12struct pci_controller;
13
14/* 15/*
15 * Structure of a PCI controller (host bridge) 16 * Structure of a PCI controller (host bridge)
16 */ 17 */
@@ -51,11 +52,11 @@ struct pci_controller {
51 * set. 52 * set.
52 * BIG_ENDIAN - cfg_addr is a big endian register 53 * BIG_ENDIAN - cfg_addr is a big endian register
53 */ 54 */
54#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001) 55#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
55#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002) 56#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
56#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004) 57#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
57#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008) 58#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
58#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010) 59#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
59 u32 indirect_type; 60 u32 indirect_type;
60 61
61 /* Currently, we limit ourselves to 1 IO range and 3 mem 62 /* Currently, we limit ourselves to 1 IO range and 3 mem
@@ -81,18 +82,18 @@ static inline int isa_vaddr_is_ioport(void __iomem *address)
81 82
82/* These are used for config access before all the PCI probing 83/* These are used for config access before all the PCI probing
83 has been done. */ 84 has been done. */
84int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn, 85extern int early_read_config_byte(struct pci_controller *hose, int bus,
85 int where, u8 *val); 86 int dev_fn, int where, u8 *val);
86int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn, 87extern int early_read_config_word(struct pci_controller *hose, int bus,
87 int where, u16 *val); 88 int dev_fn, int where, u16 *val);
88int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn, 89extern int early_read_config_dword(struct pci_controller *hose, int bus,
89 int where, u32 *val); 90 int dev_fn, int where, u32 *val);
90int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn, 91extern int early_write_config_byte(struct pci_controller *hose, int bus,
91 int where, u8 val); 92 int dev_fn, int where, u8 val);
92int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn, 93extern int early_write_config_word(struct pci_controller *hose, int bus,
93 int where, u16 val); 94 int dev_fn, int where, u16 val);
94int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, 95extern int early_write_config_dword(struct pci_controller *hose, int bus,
95 int where, u32 val); 96 int dev_fn, int where, u32 val);
96 97
97extern int early_find_capability(struct pci_controller *hose, int bus, 98extern int early_find_capability(struct pci_controller *hose, int bus,
98 int dev_fn, int cap); 99 int dev_fn, int cap);
@@ -104,15 +105,7 @@ extern void setup_grackle(struct pci_controller *hose);
104extern void __init update_bridge_resource(struct pci_dev *dev, 105extern void __init update_bridge_resource(struct pci_dev *dev,
105 struct resource *res); 106 struct resource *res);
106 107
107#else 108#else /* CONFIG_PPC64 */
108
109
110/*
111 * This program is free software; you can redistribute it and/or
112 * modify it under the terms of the GNU General Public License
113 * as published by the Free Software Foundation; either version
114 * 2 of the License, or (at your option) any later version.
115 */
116 109
117/* 110/*
118 * Structure of a PCI controller (host bridge) 111 * Structure of a PCI controller (host bridge)
@@ -159,8 +152,8 @@ struct pci_controller {
159 * PCI stuff, for nodes representing PCI devices, pointed to 152 * PCI stuff, for nodes representing PCI devices, pointed to
160 * by device_node->data. 153 * by device_node->data.
161 */ 154 */
162struct pci_controller;
163struct iommu_table; 155struct iommu_table;
156struct device_node;
164 157
165struct pci_dn { 158struct pci_dn {
166 int busno; /* pci bus number */ 159 int busno; /* pci bus number */
@@ -179,9 +172,9 @@ struct pci_dn {
179 int eeh_mode; /* See eeh.h for possible EEH_MODEs */ 172 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
180 int eeh_config_addr; 173 int eeh_config_addr;
181 int eeh_pe_config_addr; /* new-style partition endpoint address */ 174 int eeh_pe_config_addr; /* new-style partition endpoint address */
182 int eeh_check_count; /* # times driver ignored error */ 175 int eeh_check_count; /* # times driver ignored error */
183 int eeh_freeze_count; /* # times this device froze up. */ 176 int eeh_freeze_count; /* # times this device froze up. */
184 int eeh_false_positives; /* # times this device reported #ff's */ 177 int eeh_false_positives; /* # times this device reported #ff's */
185 u32 config_space[16]; /* saved PCI config space */ 178 u32 config_space[16]; /* saved PCI config space */
186#endif 179#endif
187}; 180};
@@ -189,7 +182,7 @@ struct pci_dn {
189/* Get the pointer to a device_node's pci_dn */ 182/* Get the pointer to a device_node's pci_dn */
190#define PCI_DN(dn) ((struct pci_dn *) (dn)->data) 183#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
191 184
192struct device_node *fetch_dev_dn(struct pci_dev *dev); 185extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
193 186
194/* Get a device_node from a pci_dev. This code must be fast except 187/* Get a device_node from a pci_dev. This code must be fast except
195 * in the case where the sysdata is incorrect and needs to be fixed 188 * in the case where the sysdata is incorrect and needs to be fixed
@@ -227,14 +220,14 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
227} 220}
228 221
229/** Find the bus corresponding to the indicated device node */ 222/** Find the bus corresponding to the indicated device node */
230struct pci_bus * pcibios_find_pci_bus(struct device_node *dn); 223extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
231 224
232/** Remove all of the PCI devices under this bus */ 225/** Remove all of the PCI devices under this bus */
233void pcibios_remove_pci_devices(struct pci_bus *bus); 226extern void pcibios_remove_pci_devices(struct pci_bus *bus);
234 227
235/** Discover new pci devices under this bus, and add them */ 228/** Discover new pci devices under this bus, and add them */
236void pcibios_add_pci_devices(struct pci_bus * bus); 229extern void pcibios_add_pci_devices(struct pci_bus *bus);
237void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus); 230extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
238 231
239extern int pcibios_remove_root_bus(struct pci_controller *phb); 232extern int pcibios_remove_root_bus(struct pci_controller *phb);
240 233
@@ -270,20 +263,18 @@ extern int pcibios_map_io_space(struct pci_bus *bus);
270#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1) 263#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
271#endif 264#endif
272 265
273#endif /* CONFIG_PPC64 */ 266#endif /* CONFIG_PPC64 */
274 267
275/* Get the PCI host controller for an OF device */ 268/* Get the PCI host controller for an OF device */
276extern struct pci_controller* 269extern struct pci_controller *pci_find_hose_for_OF_device(
277pci_find_hose_for_OF_device(struct device_node* node); 270 struct device_node* node);
278 271
279/* Fill up host controller resources from the OF node */ 272/* Fill up host controller resources from the OF node */
280extern void 273extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
281pci_process_bridge_OF_ranges(struct pci_controller *hose, 274 struct device_node *dev, int primary);
282 struct device_node *dev, int primary);
283 275
284/* Allocate & free a PCI host bridge structure */ 276/* Allocate & free a PCI host bridge structure */
285extern struct pci_controller * 277extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
286pcibios_alloc_controller(struct device_node *dev);
287extern void pcibios_free_controller(struct pci_controller *phb); 278extern void pcibios_free_controller(struct pci_controller *phb);
288 279
289#ifdef CONFIG_PCI 280#ifdef CONFIG_PCI
@@ -298,9 +289,7 @@ static inline int pcibios_vaddr_is_ioport(void __iomem *address)
298{ 289{
299 return 0; 290 return 0;
300} 291}
301#endif 292#endif /* CONFIG_PCI */
302 293
303 294#endif /* __KERNEL__ */
304 295#endif /* _ASM_POWERPC_PCI_BRIDGE_H */
305#endif /* __KERNEL__ */
306#endif