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authorJeff Garzik <jeff@garzik.org>2007-07-13 15:20:15 -0400
committerJeff Garzik <jeff@garzik.org>2007-07-20 05:58:23 -0400
commit6c1153e00af8de755ec278d873a97c9ce2a72d10 (patch)
tree901f5fb572f64d753162a2bb98ce43d1732bdf01
parent9a79b2274186fade17134929d4f85b70d59a3840 (diff)
[libata] sata_mv: Micro-optimization and cleanups
* Micro-optimization in the EDMA interrupt handling code * s/EDMA_ERR_CRBQ_PAR/EDMA_ERR_CRQB_PAR/ * Document EDMA Error Interrupt Cause register bits Signed-off-by: Jeff Garzik <jeff@garzik.org>
-rw-r--r--drivers/ata/sata_mv.c65
1 files changed, 31 insertions, 34 deletions
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index fb8a749423ca..0ccd990c8dac 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -227,26 +227,26 @@ enum {
227 227
228 EDMA_ERR_IRQ_CAUSE_OFS = 0x8, 228 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
229 EDMA_ERR_IRQ_MASK_OFS = 0xc, 229 EDMA_ERR_IRQ_MASK_OFS = 0xc,
230 EDMA_ERR_D_PAR = (1 << 0), 230 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
231 EDMA_ERR_PRD_PAR = (1 << 1), 231 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
232 EDMA_ERR_DEV = (1 << 2), 232 EDMA_ERR_DEV = (1 << 2), /* device error */
233 EDMA_ERR_DEV_DCON = (1 << 3), 233 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
234 EDMA_ERR_DEV_CON = (1 << 4), 234 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
235 EDMA_ERR_SERR = (1 << 5), 235 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
236 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 236 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
237 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 237 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
238 EDMA_ERR_BIST_ASYNC = (1 << 8), 238 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
239 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 239 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
240 EDMA_ERR_CRBQ_PAR = (1 << 9), 240 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
241 EDMA_ERR_CRPB_PAR = (1 << 10), 241 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
242 EDMA_ERR_INTRL_PAR = (1 << 11), 242 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
243 EDMA_ERR_IORDY = (1 << 12), 243 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
244 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), 244 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
245 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), 245 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
246 EDMA_ERR_LNK_DATA_RX = (0xf << 17), 246 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
247 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), 247 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
248 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), 248 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
249 EDMA_ERR_TRANS_PROTO = (1 << 31), 249 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
250 EDMA_ERR_OVERRUN_5 = (1 << 5), 250 EDMA_ERR_OVERRUN_5 = (1 << 5),
251 EDMA_ERR_UNDERRUN_5 = (1 << 6), 251 EDMA_ERR_UNDERRUN_5 = (1 << 6),
252 EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 252 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
@@ -255,7 +255,7 @@ enum {
255 EDMA_ERR_DEV_CON | 255 EDMA_ERR_DEV_CON |
256 EDMA_ERR_SERR | 256 EDMA_ERR_SERR |
257 EDMA_ERR_SELF_DIS | 257 EDMA_ERR_SELF_DIS |
258 EDMA_ERR_CRBQ_PAR | 258 EDMA_ERR_CRQB_PAR |
259 EDMA_ERR_CRPB_PAR | 259 EDMA_ERR_CRPB_PAR |
260 EDMA_ERR_INTRL_PAR | 260 EDMA_ERR_INTRL_PAR |
261 EDMA_ERR_IORDY | 261 EDMA_ERR_IORDY |
@@ -270,7 +270,7 @@ enum {
270 EDMA_ERR_OVERRUN_5 | 270 EDMA_ERR_OVERRUN_5 |
271 EDMA_ERR_UNDERRUN_5 | 271 EDMA_ERR_UNDERRUN_5 |
272 EDMA_ERR_SELF_DIS_5 | 272 EDMA_ERR_SELF_DIS_5 |
273 EDMA_ERR_CRBQ_PAR | 273 EDMA_ERR_CRQB_PAR |
274 EDMA_ERR_CRPB_PAR | 274 EDMA_ERR_CRPB_PAR |
275 EDMA_ERR_INTRL_PAR | 275 EDMA_ERR_INTRL_PAR |
276 EDMA_ERR_IORDY, 276 EDMA_ERR_IORDY,
@@ -1393,7 +1393,7 @@ static void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
1393 if (edma_err_cause & EDMA_ERR_DEV) 1393 if (edma_err_cause & EDMA_ERR_DEV)
1394 err_mask |= AC_ERR_DEV; 1394 err_mask |= AC_ERR_DEV;
1395 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 1395 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
1396 EDMA_ERR_CRBQ_PAR | EDMA_ERR_CRPB_PAR | 1396 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
1397 EDMA_ERR_INTRL_PAR)) { 1397 EDMA_ERR_INTRL_PAR)) {
1398 err_mask |= AC_ERR_ATA_BUS; 1398 err_mask |= AC_ERR_ATA_BUS;
1399 action |= ATA_EH_HARDRESET; 1399 action |= ATA_EH_HARDRESET;
@@ -1489,33 +1489,30 @@ static void mv_intr_edma(struct ata_port *ap)
1489 1489
1490 while (1) { 1490 while (1) {
1491 u16 status; 1491 u16 status;
1492 unsigned int tag;
1492 1493
1493 /* get s/w response queue last-read pointer, and compare */ 1494 /* get s/w response queue last-read pointer, and compare */
1494 out_index = pp->resp_idx & MV_MAX_Q_DEPTH_MASK; 1495 out_index = pp->resp_idx & MV_MAX_Q_DEPTH_MASK;
1495 if (in_index == out_index) 1496 if (in_index == out_index)
1496 break; 1497 break;
1497 1498
1498
1499 /* 50xx: get active ATA command */ 1499 /* 50xx: get active ATA command */
1500 if (IS_GEN_I(hpriv)) 1500 if (IS_GEN_I(hpriv))
1501 qc = ata_qc_from_tag(ap, ap->active_tag); 1501 tag = ap->active_tag;
1502 1502
1503 /* 60xx: get active ATA command via tag, to enable support 1503 /* Gen II/IIE: get active ATA command via tag, to enable
1504 * for queueing. this works transparently for queued and 1504 * support for queueing. this works transparently for
1505 * non-queued modes. 1505 * queued and non-queued modes.
1506 */ 1506 */
1507 else { 1507 else if (IS_GEN_II(hpriv))
1508 unsigned int tag; 1508 tag = (le16_to_cpu(pp->crpb[out_index].id)
1509 >> CRPB_IOID_SHIFT_6) & 0x3f;
1509 1510
1510 if (IS_GEN_II(hpriv)) 1511 else /* IS_GEN_IIE */
1511 tag = (le16_to_cpu(pp->crpb[out_index].id) 1512 tag = (le16_to_cpu(pp->crpb[out_index].id)
1512 >> CRPB_IOID_SHIFT_6) & 0x3f; 1513 >> CRPB_IOID_SHIFT_7) & 0x3f;
1513 else
1514 tag = (le16_to_cpu(pp->crpb[out_index].id)
1515 >> CRPB_IOID_SHIFT_7) & 0x3f;
1516 1514
1517 qc = ata_qc_from_tag(ap, tag); 1515 qc = ata_qc_from_tag(ap, tag);
1518 }
1519 1516
1520 /* lower 8 bits of status are EDMA_ERR_IRQ_CAUSE_OFS 1517 /* lower 8 bits of status are EDMA_ERR_IRQ_CAUSE_OFS
1521 * bits (WARNING: might not necessarily be associated 1518 * bits (WARNING: might not necessarily be associated